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imx: mx6: fix mmdc ch0 clk for 6SL
[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / clock.c
CommitLineData
23608e23
JL		 1/*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 *
1a459660 4 * SPDX-License-Identifier: GPL-2.0+
23608e23
JL		 5 */
6
7#include <common.h>
5a660169 8#include <div64.h>
23608e23 9#include <asm/io.h>
1221ce45 10#include <linux/errno.h>
23608e23 11#include <asm/arch/imx-regs.h>
6a376046 12#include <asm/arch/crm_regs.h>
23608e23 13#include <asm/arch/clock.h>
6a376046 14#include <asm/arch/sys_proto.h>
23608e23
JL		 15
16enum pll_clocks {
17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */
9ba18ff8
PF		 21 PLL_AUDIO, /* AUDIO PLL */
22 PLL_VIDEO, /* AUDIO PLL */
23608e23
JL		 23};
24
6a376046 25struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
23608e23 26
112fd2ec
BT		 27#ifdef CONFIG_MXC_OCOTP
28void enable_ocotp_clk(unsigned char enable)
29{
30 u32 reg;
31
32 reg = __raw_readl(&imx_ccm->CCGR2);
33 if (enable)
34 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
35 else
36 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
37 __raw_writel(reg, &imx_ccm->CCGR2);
38}
39#endif
40
224beb83
NK		 41#ifdef CONFIG_NAND_MXS
42void setup_gpmi_io_clk(u32 cfg)
43{
44 /* Disable clocks per ERR007177 from MX6 errata */
45 clrbits_le32(&imx_ccm->CCGR4,
46 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
48 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
49 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
50 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
51
90447ef0
YL		 52#if defined(CONFIG_MX6SX)
53 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
54
55 clrsetbits_le32(&imx_ccm->cs2cdr,
56 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
57 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
58 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
59 cfg);
60
61 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
62#else
224beb83
NK		 63 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
64
65 clrsetbits_le32(&imx_ccm->cs2cdr,
66 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
67 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
68 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
69 cfg);
70
71 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
90447ef0 72#endif
224beb83
NK		 73 setbits_le32(&imx_ccm->CCGR4,
74 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
76 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
77 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
78 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
79}
80#endif
81
3f467529
WG		 82void enable_usboh3_clk(unsigned char enable)
83{
84 u32 reg;
85
86 reg = __raw_readl(&imx_ccm->CCGR6);
87 if (enable)
0bb7e316 88 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
3f467529 89 else
0bb7e316 90 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
3f467529
WG		 91 __raw_writel(reg, &imx_ccm->CCGR6);
92
93}
94
3d8f1798 95#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
224beb83
NK		 96void enable_enet_clk(unsigned char enable)
97{
43cb127b
PF		 98 u32 mask, *addr;
99
3974b7f6
PF		 100 if (is_mx6ull()) {
101 mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
102 addr = &imx_ccm->CCGR0;
103 } else if (is_mx6ul()) {
43cb127b
PF		 104 mask = MXC_CCM_CCGR3_ENET_MASK;
105 addr = &imx_ccm->CCGR3;
106 } else {
107 mask = MXC_CCM_CCGR1_ENET_MASK;
108 addr = &imx_ccm->CCGR1;
109 }
224beb83
NK		 110
111 if (enable)
43cb127b 112 setbits_le32(addr, mask);
224beb83 113 else
43cb127b 114 clrbits_le32(addr, mask);
224beb83
NK		 115}
116#endif
117
118#ifdef CONFIG_MXC_UART
119void enable_uart_clk(unsigned char enable)
120{
43cb127b
PF		 121 u32 mask;
122
3974b7f6 123 if (is_mx6ul() || is_mx6ull())
43cb127b
PF		 124 mask = MXC_CCM_CCGR5_UART_MASK;
125 else
126 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
224beb83
NK		 127
128 if (enable)
129 setbits_le32(&imx_ccm->CCGR5, mask);
130 else
131 clrbits_le32(&imx_ccm->CCGR5, mask);
132}
133#endif
134
224beb83
NK		 135#ifdef CONFIG_MMC
136int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
137{
138 u32 mask;
139
140 if (bus_num > 3)
141 return -EINVAL;
142
143 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
144 if (enable)
145 setbits_le32(&imx_ccm->CCGR6, mask);
146 else
147 clrbits_le32(&imx_ccm->CCGR6, mask);
148
149 return 0;
150}
151#endif
152
fac96408 153#ifdef CONFIG_SYS_I2C_MXC
21a26940 154/* i2c_num can be from 0 - 3 */
cc54a0f7
TK		 155int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
156{
157 u32 reg;
158 u32 mask;
19c6ec70 159 u32 *addr;
cc54a0f7 160
21a26940 161 if (i2c_num > 3)
cc54a0f7 162 return -EINVAL;
21a26940
HS		 163 if (i2c_num < 3) {
164 mask = MXC_CCM_CCGR_CG_MASK
165 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
166 + (i2c_num << 1));
167 reg = __raw_readl(&imx_ccm->CCGR2);
168 if (enable)
169 reg |= mask;
170 else
171 reg &= ~mask;
172 __raw_writel(reg, &imx_ccm->CCGR2);
173 } else {
3974b7f6 174 if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
19c6ec70
PF		 175 mask = MXC_CCM_CCGR6_I2C4_MASK;
176 addr = &imx_ccm->CCGR6;
177 } else {
178 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
179 addr = &imx_ccm->CCGR1;
180 }
181 reg = __raw_readl(addr);
21a26940
HS		 182 if (enable)
183 reg |= mask;
184 else
185 reg &= ~mask;
19c6ec70 186 __raw_writel(reg, addr);
21a26940 187 }
cc54a0f7
TK		 188 return 0;
189}
190#endif
191
a0ae0091
HS		 192/* spi_num can be from 0 - SPI_MAX_NUM */
193int enable_spi_clk(unsigned char enable, unsigned spi_num)
194{
195 u32 reg;
196 u32 mask;
197
198 if (spi_num > SPI_MAX_NUM)
199 return -EINVAL;
200
201 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
202 reg = __raw_readl(&imx_ccm->CCGR1);
203 if (enable)
204 reg |= mask;
205 else
206 reg &= ~mask;
207 __raw_writel(reg, &imx_ccm->CCGR1);
208 return 0;
209}
23608e23
JL		 210static u32 decode_pll(enum pll_clocks pll, u32 infreq)
211{
9ba18ff8 212 u32 div, test_div, pll_num, pll_denom;
23608e23
JL		 213
214 switch (pll) {
215 case PLL_SYS:
216 div = __raw_readl(&imx_ccm->analog_pll_sys);
217 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
218
2eb268f6 219 return (infreq * div) >> 1;
23608e23
JL		 220 case PLL_BUS:
221 div = __raw_readl(&imx_ccm->analog_pll_528);
222 div &= BM_ANADIG_PLL_528_DIV_SELECT;
223
224 return infreq * (20 + (div << 1));
225 case PLL_USBOTG:
226 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
227 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
228
229 return infreq * (20 + (div << 1));
230 case PLL_ENET:
231 div = __raw_readl(&imx_ccm->analog_pll_enet);
232 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
233
89cfd0f5 234 return 25000000 * (div + (div >> 1) + 1);
9ba18ff8
PF		 235 case PLL_AUDIO:
236 div = __raw_readl(&imx_ccm->analog_pll_audio);
237 if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
238 return 0;
239 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
240 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
241 return MXC_HCLK;
242 pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
243 pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
244 test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
245 BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
246 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
247 if (test_div == 3) {
248 debug("Error test_div\n");
249 return 0;
250 }
251 test_div = 1 << (2 - test_div);
252
253 return infreq * (div + pll_num / pll_denom) / test_div;
254 case PLL_VIDEO:
255 div = __raw_readl(&imx_ccm->analog_pll_video);
256 if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
257 return 0;
258 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
259 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
260 return MXC_HCLK;
261 pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
262 pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
263 test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
264 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
265 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
266 if (test_div == 3) {
267 debug("Error test_div\n");
268 return 0;
269 }
270 test_div = 1 << (2 - test_div);
271
272 return infreq * (div + pll_num / pll_denom) / test_div;
23608e23
JL		 273 default:
274 return 0;
275 }
276 /* NOTREACHED */
277}
762a88cc
PA		 278static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
279{
280 u32 div;
281 u64 freq;
282
283 switch (pll) {
284 case PLL_BUS:
3974b7f6 285 if (!is_mx6ul() && !is_mx6ull()) {
43cb127b 286 if (pfd_num == 3) {
1f175627 287 /* No PFD3 on PLL2 */
43cb127b
PF		 288 return 0;
289 }
762a88cc
PA		 290 }
291 div = __raw_readl(&imx_ccm->analog_pfd_528);
292 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
293 break;
294 case PLL_USBOTG:
295 div = __raw_readl(&imx_ccm->analog_pfd_480);
296 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
297 break;
298 default:
299 /* No PFD on other PLL */
300 return 0;
301 }
302
5a660169 303 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
762a88cc
PA		 304 ANATOP_PFD_FRAC_SHIFT(pfd_num));
305}
23608e23
JL		 306
307static u32 get_mcu_main_clk(void)
308{
309 u32 reg, freq;
310
311 reg = __raw_readl(&imx_ccm->cacrr);
312 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
313 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
833b6435 314 freq = decode_pll(PLL_SYS, MXC_HCLK);
23608e23
JL		 315
316 return freq / (reg + 1);
317}
318
6a376046 319u32 get_periph_clk(void)
23608e23 320{
43cb127b 321 u32 reg, div = 0, freq = 0;
23608e23
JL		 322
323 reg = __raw_readl(&imx_ccm->cbcdr);
324 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
43cb127b
PF		 325 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
326 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
23608e23
JL		 327 reg = __raw_readl(&imx_ccm->cbcmr);
328 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
329 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
330
331 switch (reg) {
332 case 0:
833b6435 333 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23
JL		 334 break;
335 case 1:
336 case 2:
833b6435 337 freq = MXC_HCLK;
23608e23
JL		 338 break;
339 default:
340 break;
341 }
342 } else {
343 reg = __raw_readl(&imx_ccm->cbcmr);
344 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
345 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
346
347 switch (reg) {
348 case 0:
833b6435 349 freq = decode_pll(PLL_BUS, MXC_HCLK);
23608e23
JL		 350 break;
351 case 1:
762a88cc 352 freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23
JL		 353 break;
354 case 2:
762a88cc 355 freq = mxc_get_pll_pfd(PLL_BUS, 0);
23608e23
JL		 356 break;
357 case 3:
762a88cc
PA		 358 /* static / 2 divider */
359 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
23608e23
JL		 360 break;
361 default:
362 break;
363 }
364 }
365
43cb127b 366 return freq / (div + 1);
23608e23
JL		 367}
368
23608e23
JL		 369static u32 get_ipg_clk(void)
370{
371 u32 reg, ipg_podf;
372
373 reg = __raw_readl(&imx_ccm->cbcdr);
374 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
375 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
376
377 return get_ahb_clk() / (ipg_podf + 1);
378}
379
380static u32 get_ipg_per_clk(void)
381{
382 u32 reg, perclk_podf;
383
384 reg = __raw_readl(&imx_ccm->cscmr1);
b949fd2c 385 if (is_mx6sl() || is_mx6sx() ||
3974b7f6 386 is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
e1c2d68b
PF		 387 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
388 return MXC_HCLK; /* OSC 24Mhz */
389 }
390
23608e23
JL		 391 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
392
393 return get_ipg_clk() / (perclk_podf + 1);
394}
395
396static u32 get_uart_clk(void)
397{
398 u32 reg, uart_podf;
762a88cc 399 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
23608e23 400 reg = __raw_readl(&imx_ccm->cscdr1);
e1c2d68b 401
3974b7f6
PF		 402 if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
403 is_mx6ull()) {
e1c2d68b
PF		 404 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
405 freq = MXC_HCLK;
406 }
407
23608e23
JL		 408 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
409 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
410
25b4aa14 411 return freq / (uart_podf + 1);
23608e23
JL		 412}
413
414static u32 get_cspi_clk(void)
415{
416 u32 reg, cspi_podf;
417
418 reg = __raw_readl(&imx_ccm->cscdr2);
e1c2d68b
PF		 419 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
420 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
421
3974b7f6
PF		 422 if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
423 is_mx6ull()) {
e1c2d68b
PF		 424 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
425 return MXC_HCLK / (cspi_podf + 1);
426 }
23608e23 427
762a88cc 428 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
23608e23
JL		 429}
430
431static u32 get_axi_clk(void)
432{
433 u32 root_freq, axi_podf;
434 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
435
436 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
437 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
438
439 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
440 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
762a88cc 441 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
8f2e2f15
FE		 442 else
443 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23
JL		 444 } else
445 root_freq = get_periph_clk();
446
447 return root_freq / (axi_podf + 1);
448}
449
450static u32 get_emi_slow_clk(void)
451{
d55e0dab 452 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
23608e23
JL		 453
454 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
455 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
456 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
d55e0dab
AG		 457 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
458 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
23608e23
JL		 459
460 switch (emi_clk_sel) {
461 case 0:
462 root_freq = get_axi_clk();
463 break;
464 case 1:
833b6435 465 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23
JL		 466 break;
467 case 2:
762a88cc 468 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23
JL		 469 break;
470 case 3:
762a88cc 471 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
23608e23
JL		 472 break;
473 }
474
d55e0dab 475 return root_freq / (emi_slow_podf + 1);
23608e23
JL		 476}
477
25b4aa14
FE		 478static u32 get_mmdc_ch0_clk(void)
479{
480 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
481 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
25b4aa14 482
9ba18ff8 483 u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
43cb127b 484
3974b7f6 485 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
43cb127b
PF		 486 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
487 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
488 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
489 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
490 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
b949fd2c 491 if (is_mx6sl()) {
43cb127b
PF		 492 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
493 freq = MXC_HCLK;
494 else
495 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
496 } else {
497 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
498 freq = decode_pll(PLL_BUS, MXC_HCLK);
499 else
500 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
501 }
502 } else {
503 per2_clk2_podf = 0;
504 switch ((cbcmr &
505 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
506 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
507 case 0:
508 freq = decode_pll(PLL_BUS, MXC_HCLK);
509 break;
510 case 1:
511 freq = mxc_get_pll_pfd(PLL_BUS, 2);
512 break;
513 case 2:
514 freq = mxc_get_pll_pfd(PLL_BUS, 0);
515 break;
516 case 3:
0e81982d
PF		 517 if (is_mx6sl()) {
518 freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
519 break;
520 }
521
9ba18ff8
PF		 522 pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
523 switch (pmu_misc2_audio_div) {
524 case 0:
525 case 2:
526 pmu_misc2_audio_div = 1;
527 break;
528 case 1:
529 pmu_misc2_audio_div = 2;
530 break;
531 case 3:
532 pmu_misc2_audio_div = 4;
533 break;
534 }
535 freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
536 pmu_misc2_audio_div;
43cb127b
PF		 537 break;
538 }
539 }
540 return freq / (podf + 1) / (per2_clk2_podf + 1);
541 } else {
542 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
543 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
544 return get_periph_clk() / (podf + 1);
25b4aa14 545 }
25b4aa14 546}
c655b816 547
ad153782
PF		 548#if defined(CONFIG_VIDEO_MXS)
549static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
550 u32 post_div)
551{
552 u32 reg = 0;
553 ulong start;
554
555 debug("pll5 div = %d, num = %d, denom = %d\n",
556 pll_div, pll_num, pll_denom);
557
558 /* Power up PLL5 video */
559 writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
560 BM_ANADIG_PLL_VIDEO_BYPASS |
561 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
562 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
563 &imx_ccm->analog_pll_video_clr);
564
565 /* Set div, num and denom */
566 switch (post_div) {
567 case 1:
568 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
569 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
570 &imx_ccm->analog_pll_video_set);
571 break;
572 case 2:
573 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
574 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
575 &imx_ccm->analog_pll_video_set);
576 break;
577 case 4:
578 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
579 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
580 &imx_ccm->analog_pll_video_set);
581 break;
582 default:
583 puts("Wrong test_div!\n");
584 return -EINVAL;
585 }
586
587 writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
588 &imx_ccm->analog_pll_video_num);
589 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
590 &imx_ccm->analog_pll_video_denom);
591
592 /* Wait PLL5 lock */
593 start = get_timer(0); /* Get current timestamp */
594
595 do {
596 reg = readl(&imx_ccm->analog_pll_video);
597 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
598 /* Enable PLL out */
599 writel(BM_ANADIG_PLL_VIDEO_ENABLE,
600 &imx_ccm->analog_pll_video_set);
601 return 0;
602 }
603 } while (get_timer(0) < (start + 10)); /* Wait 10ms */
604
605 puts("Lock PLL5 timeout\n");
606
607 return -ETIME;
608}
609
610/*
611 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
612 *
613 * 'freq' using KHz as unit, see driver/video/mxsfb.c.
614 */
615void mxs_set_lcdclk(u32 base_addr, u32 freq)
616{
617 u32 reg = 0;
618 u32 hck = MXC_HCLK / 1000;
619 /* DIV_SELECT ranges from 27 to 54 */
620 u32 min = hck * 27;
621 u32 max = hck * 54;
622 u32 temp, best = 0;
623 u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
624 u32 pll_div, pll_num, pll_denom, post_div = 1;
625
626 debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
627
3974b7f6 628 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
ad153782
PF		 629 debug("This chip not support lcd!\n");
630 return;
631 }
632
633 if (base_addr == LCDIF1_BASE_ADDR) {
634 reg = readl(&imx_ccm->cscdr2);
635 /* Can't change clocks when clock not from pre-mux */
636 if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
637 return;
638 }
639
b949fd2c 640 if (is_mx6sx()) {
ad153782
PF		 641 reg = readl(&imx_ccm->cscdr2);
642 /* Can't change clocks when clock not from pre-mux */
643 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
644 return;
645 }
646
647 temp = freq * max_pred * max_postd;
ad153782
PF		 648 if (temp < min) {
649 /*
650 * Register: PLL_VIDEO
651 * Bit Field: POST_DIV_SELECT
652 * 00 — Divide by 4.
653 * 01 — Divide by 2.
654 * 10 — Divide by 1.
655 * 11 — Reserved
656 * No need to check post_div(1)
657 */
658 for (post_div = 2; post_div <= 4; post_div <<= 1) {
659 if ((temp * post_div) > min) {
660 freq *= post_div;
661 break;
662 }
663 }
664
665 if (post_div > 4) {
666 printf("Fail to set rate to %dkhz", freq);
667 return;
668 }
669 }
670
671 /* Choose the best pred and postd to match freq for lcd */
672 for (i = 1; i <= max_pred; i++) {
673 for (j = 1; j <= max_postd; j++) {
674 temp = freq * i * j;
675 if (temp > max || temp < min)
676 continue;
677 if (best == 0 || temp < best) {
678 best = temp;
679 pred = i;
680 postd = j;
681 }
682 }
683 }
684
685 if (best == 0) {
686 printf("Fail to set rate to %dKHz", freq);
687 return;
688 }
689
690 debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
691
692 pll_div = best / hck;
693 pll_denom = 1000000;
694 pll_num = (best - hck * pll_div) * pll_denom / hck;
695
696 /*
697 * pll_num
698 * (24MHz * (pll_div + --------- ))
699 * pll_denom
700 *freq KHz = --------------------------------
701 * post_div * pred * postd * 1000
702 */
703
704 if (base_addr == LCDIF1_BASE_ADDR) {
705 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
706 return;
707
708 /* Select pre-lcd clock to PLL5 and set pre divider */
709 clrsetbits_le32(&imx_ccm->cscdr2,
710 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
711 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
712 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
713 ((pred - 1) <<
714 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
715
716 /* Set the post divider */
717 clrsetbits_le32(&imx_ccm->cbcmr,
718 MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
719 ((postd - 1) <<
720 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
b949fd2c 721 } else if (is_mx6sx()) {
ad153782
PF		 722 /* Setting LCDIF2 for i.MX6SX */
723 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
724 return;
725
726 /* Select pre-lcd clock to PLL5 and set pre divider */
727 clrsetbits_le32(&imx_ccm->cscdr2,
728 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
729 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
730 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
731 ((pred - 1) <<
732 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
733
734 /* Set the post divider */
735 clrsetbits_le32(&imx_ccm->cscmr1,
736 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
737 ((postd - 1) <<
738 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
739 }
740}
741
742int enable_lcdif_clock(u32 base_addr)
743{
744 u32 reg = 0;
745 u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
746
b949fd2c 747 if (is_mx6sx()) {
9655ebdd
YL		 748 if ((base_addr != LCDIF1_BASE_ADDR) &&
749 (base_addr != LCDIF2_BASE_ADDR)) {
ad153782
PF		 750 puts("Wrong LCD interface!\n");
751 return -EINVAL;
752 }
753 /* Set to pre-mux clock at default */
754 lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
755 MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
756 MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
757 lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
758 (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
759 MXC_CCM_CCGR3_DISP_AXI_MASK) :
760 (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
761 MXC_CCM_CCGR3_DISP_AXI_MASK);
3974b7f6 762 } else if (is_mx6ul() || is_mx6ull()) {
ad153782
PF		 763 if (base_addr != LCDIF1_BASE_ADDR) {
764 puts("Wrong LCD interface!\n");
765 return -EINVAL;
766 }
767 /* Set to pre-mux clock at default */
768 lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
769 lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
770 } else {
771 return 0;
772 }
773
774 reg = readl(&imx_ccm->cscdr2);
775 reg &= ~lcdif_clk_sel_mask;
776 writel(reg, &imx_ccm->cscdr2);
777
778 /* Enable the LCDIF pix clock */
779 reg = readl(&imx_ccm->CCGR3);
780 reg |= lcdif_ccgr3_mask;
781 writel(reg, &imx_ccm->CCGR3);
782
783 reg = readl(&imx_ccm->CCGR2);
784 reg |= MXC_CCM_CCGR2_LCD_MASK;
785 writel(reg, &imx_ccm->CCGR2);
0ff47e59
JH		 786
787 return 0;
ad153782
PF		 788}
789#endif
790
43cb127b 791#ifdef CONFIG_FSL_QSPI
b93ab2ee
PF		 792/* qspi_num can be from 0 - 1 */
793void enable_qspi_clk(int qspi_num)
794{
795 u32 reg = 0;
796 /* Enable QuadSPI clock */
797 switch (qspi_num) {
798 case 0:
799 /* disable the clock gate */
800 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
801
802 /* set 50M : (50 = 396 / 2 / 4) */
803 reg = readl(&imx_ccm->cscmr1);
804 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
805 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
806 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
807 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
808 writel(reg, &imx_ccm->cscmr1);
809
810 /* enable the clock gate */
811 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
812 break;
813 case 1:
814 /*
815 * disable the clock gate
816 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
817 * disable both of them.
818 */
819 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
820 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
821
822 /* set 50M : (50 = 396 / 2 / 4) */
823 reg = readl(&imx_ccm->cs2cdr);
824 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
825 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
826 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
827 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
828 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
829 writel(reg, &imx_ccm->cs2cdr);
830
831 /*enable the clock gate*/
832 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
833 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
834 break;
835 default:
836 break;
837 }
838}
839#endif
840
c655b816 841#ifdef CONFIG_FEC_MXC
6d97dc10 842int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
31f07964
FE		 843{
844 u32 reg = 0;
845 s32 timeout = 100000;
846
847 struct anatop_regs __iomem *anatop =
848 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
849
7731745c 850 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
5f98d0b5
FE		 851 return -EINVAL;
852
e2748b41
PF		 853 reg = readl(&anatop->pll_enet);
854
6d97dc10
PF		 855 if (fec_id == 0) {
856 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
857 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
858 } else if (fec_id == 1) {
859 /* Only i.MX6SX/UL support ENET2 */
3974b7f6 860 if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
6d97dc10
PF		 861 return -EINVAL;
862 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
863 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
864 } else {
865 return -EINVAL;
866 }
5f98d0b5 867
31f07964
FE		 868 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
869 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
870 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
871 writel(reg, &anatop->pll_enet);
872 while (timeout--) {
873 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
874 break;
875 }
876 if (timeout < 0)
877 return -ETIMEDOUT;
878 }
879
880 /* Enable FEC clock */
6d97dc10
PF		 881 if (fec_id == 0)
882 reg |= BM_ANADIG_PLL_ENET_ENABLE;
883 else
884 reg |= BM_ANADIG_PLL_ENET2_ENABLE;
31f07964
FE		 885 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
886 writel(reg, &anatop->pll_enet);
887
5c045cdd 888#ifdef CONFIG_MX6SX
27e3a3c7
YL		 889 /* Disable enet system clcok before switching clock parent */
890 reg = readl(&imx_ccm->CCGR3);
891 reg &= ~MXC_CCM_CCGR3_ENET_MASK;
892 writel(reg, &imx_ccm->CCGR3);
893
5c045cdd
FE		 894 /*
895 * Set enet ahb clock to 200MHz
896 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
897 */
898 reg = readl(&imx_ccm->chsccdr);
899 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
900 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
901 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
902 /* PLL2 PFD2 */
903 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
904 /* Div = 2*/
905 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
906 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
907 writel(reg, &imx_ccm->chsccdr);
908
909 /* Enable enet system clock */
910 reg = readl(&imx_ccm->CCGR3);
911 reg |= MXC_CCM_CCGR3_ENET_MASK;
912 writel(reg, &imx_ccm->CCGR3);
913#endif
31f07964
FE		 914 return 0;
915}
25b4aa14 916#endif
23608e23
JL		 917
918static u32 get_usdhc_clk(u32 port)
919{
920 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
921 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
922 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
923
924 switch (port) {
925 case 0:
926 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
927 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
928 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
929
930 break;
931 case 1:
932 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
933 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
934 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
935
936 break;
937 case 2:
938 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
939 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
940 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
941
942 break;
943 case 3:
944 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
945 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
946 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
947
948 break;
949 default:
950 break;
951 }
952
953 if (clk_sel)
762a88cc 954 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
23608e23 955 else
762a88cc 956 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23
JL		 957
958 return root_freq / (usdhc_podf + 1);
959}
960
961u32 imx_get_uartclk(void)
962{
963 return get_uart_clk();
964}
965
ff167df5
JL		 966u32 imx_get_fecclk(void)
967{
adadc915 968 return mxc_get_clock(MXC_IPG_CLK);
ff167df5
JL		 969}
970
43cb127b 971#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
79814492 972static int enable_enet_pll(uint32_t en)
64e7cdb5 973{
64e7cdb5
EN		 974 struct mxc_ccm_reg *const imx_ccm
975 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
79814492
MV		 976 s32 timeout = 100000;
977 u32 reg = 0;
64e7cdb5
EN		 978
979 /* Enable PLLs */
980 reg = readl(&imx_ccm->analog_pll_enet);
981 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
982 writel(reg, &imx_ccm->analog_pll_enet);
983 reg |= BM_ANADIG_PLL_SYS_ENABLE;
984 while (timeout--) {
985 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
986 break;
987 }
988 if (timeout <= 0)
989 return -EIO;
990 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
991 writel(reg, &imx_ccm->analog_pll_enet);
79814492 992 reg |= en;
64e7cdb5 993 writel(reg, &imx_ccm->analog_pll_enet);
79814492
MV		 994 return 0;
995}
43cb127b 996#endif
64e7cdb5 997
43cb127b 998#ifdef CONFIG_CMD_SATA
79814492
MV		 999static void ungate_sata_clock(void)
1000{
1001 struct mxc_ccm_reg *const imx_ccm =
1002 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1003
1004 /* Enable SATA clock. */
1005 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1006}
1007
79814492
MV		 1008int enable_sata_clock(void)
1009{
1010 ungate_sata_clock();
1011 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
1012}
8d29cef5
NK		 1013
1014void disable_sata_clock(void)
1015{
1016 struct mxc_ccm_reg *const imx_ccm =
1017 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1018
1019 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1020}
d95b6ab8 1021#endif
79814492 1022
43cb127b
PF		 1023#ifdef CONFIG_PCIE_IMX
1024static void ungate_pcie_clock(void)
1025{
1026 struct mxc_ccm_reg *const imx_ccm =
1027 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1028
1029 /* Enable PCIe clock. */
1030 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
1031}
1032
79814492
MV		 1033int enable_pcie_clock(void)
1034{
1035 struct anatop_regs *anatop_regs =
1036 (struct anatop_regs *)ANATOP_BASE_ADDR;
1037 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1b8ad74a 1038 u32 lvds1_clk_sel;
79814492
MV		 1039
1040 /*
1041 * Here be dragons!
1042 *
1043 * The register ANATOP_MISC1 is not documented in the Freescale
1044 * MX6RM. The register that is mapped in the ANATOP space and
1045 * marked as ANATOP_MISC1 is actually documented in the PMU section
1046 * of the datasheet as PMU_MISC1.
1047 *
1b8ad74a
FE		 1048 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1049 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1050 * for PCI express link that is clocked from the i.MX6.
79814492
MV		 1051 */
1052#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1053#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1054#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
1b8ad74a
FE		 1055#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1056#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1057
b949fd2c 1058 if (is_mx6sx())
1b8ad74a
FE		 1059 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
1060 else
1061 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1062
79814492
MV		 1063 clrsetbits_le32(&anatop_regs->ana_misc1,
1064 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1065 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1b8ad74a 1066 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
79814492
MV		 1067
1068 /* PCIe reference clock sourced from AXI. */
1069 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1070
1071 /* Party time! Ungate the clock to the PCIe. */
43cb127b 1072#ifdef CONFIG_CMD_SATA
79814492 1073 ungate_sata_clock();
d95b6ab8 1074#endif
79814492
MV		 1075 ungate_pcie_clock();
1076
1077 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1078 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
64e7cdb5 1079}
43cb127b 1080#endif
64e7cdb5 1081
36c1ca4d
NG		 1082#ifdef CONFIG_SECURE_BOOT
1083void hab_caam_clock_enable(unsigned char enable)
1084{
1085 u32 reg;
1086
3974b7f6
PF		 1087 if (is_mx6ull()) {
1088 /* CG5, DCP clock */
1089 reg = __raw_readl(&imx_ccm->CCGR0);
1090 if (enable)
1091 reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
1092 else
1093 reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
1094 __raw_writel(reg, &imx_ccm->CCGR0);
1095 } else {
1096 /* CG4 ~ CG6, CAAM clocks */
1097 reg = __raw_readl(&imx_ccm->CCGR0);
1098 if (enable)
1099 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1100 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1101 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1102 else
1103 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1104 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1105 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1106 __raw_writel(reg, &imx_ccm->CCGR0);
1107 }
36c1ca4d
NG		 1108
1109 /* EMI slow clk */
1110 reg = __raw_readl(&imx_ccm->CCGR6);
1111 if (enable)
1112 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1113 else
1114 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1115 __raw_writel(reg, &imx_ccm->CCGR6);
1116}
1117#endif
1118
cf202d26
NG		 1119static void enable_pll3(void)
1120{
1121 struct anatop_regs __iomem *anatop =
1122 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1123
1124 /* make sure pll3 is enabled */
1125 if ((readl(&anatop->usb1_pll_480_ctrl) &
1126 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1127 /* enable pll's power */
1128 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1129 &anatop->usb1_pll_480_ctrl_set);
1130 writel(0x80, &anatop->ana_misc2_clr);
1131 /* wait for pll lock */
1132 while ((readl(&anatop->usb1_pll_480_ctrl) &
1133 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1134 ;
1135 /* disable bypass */
1136 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1137 &anatop->usb1_pll_480_ctrl_clr);
1138 /* enable pll output */
1139 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1140 &anatop->usb1_pll_480_ctrl_set);
1141 }
1142}
1143
1144void enable_thermal_clk(void)
1145{
1146 enable_pll3();
1147}
1148
23608e23
JL		 1149unsigned int mxc_get_clock(enum mxc_clock clk)
1150{
1151 switch (clk) {
1152 case MXC_ARM_CLK:
1153 return get_mcu_main_clk();
1154 case MXC_PER_CLK:
1155 return get_periph_clk();
1156 case MXC_AHB_CLK:
1157 return get_ahb_clk();
1158 case MXC_IPG_CLK:
1159 return get_ipg_clk();
1160 case MXC_IPG_PERCLK:
e7bed5c2 1161 case MXC_I2C_CLK:
23608e23
JL		 1162 return get_ipg_per_clk();
1163 case MXC_UART_CLK:
1164 return get_uart_clk();
1165 case MXC_CSPI_CLK:
1166 return get_cspi_clk();
1167 case MXC_AXI_CLK:
1168 return get_axi_clk();
1169 case MXC_EMI_SLOW_CLK:
1170 return get_emi_slow_clk();
1171 case MXC_DDR_CLK:
1172 return get_mmdc_ch0_clk();
1173 case MXC_ESDHC_CLK:
1174 return get_usdhc_clk(0);
1175 case MXC_ESDHC2_CLK:
1176 return get_usdhc_clk(1);
1177 case MXC_ESDHC3_CLK:
1178 return get_usdhc_clk(2);
1179 case MXC_ESDHC4_CLK:
1180 return get_usdhc_clk(3);
1181 case MXC_SATA_CLK:
1182 return get_ahb_clk();
1183 default:
eb412d79 1184 printf("Unsupported MXC CLK: %d\n", clk);
23608e23
JL		 1185 break;
1186 }
1187
eb412d79 1188 return 0;
23608e23
JL		 1189}
1190
1191/*
1192 * Dump some core clockes.
1193 */
1194int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1195{
1196 u32 freq;
833b6435 1197 freq = decode_pll(PLL_SYS, MXC_HCLK);
23608e23 1198 printf("PLL_SYS %8d MHz\n", freq / 1000000);
833b6435 1199 freq = decode_pll(PLL_BUS, MXC_HCLK);
23608e23 1200 printf("PLL_BUS %8d MHz\n", freq / 1000000);
833b6435 1201 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23 1202 printf("PLL_OTG %8d MHz\n", freq / 1000000);
833b6435 1203 freq = decode_pll(PLL_ENET, MXC_HCLK);
23608e23
JL		 1204 printf("PLL_NET %8d MHz\n", freq / 1000000);
1205
1206 printf("\n");
d78e7f27 1207 printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
23608e23
JL		 1208 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1209 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
cc446726 1210#ifdef CONFIG_MXC_SPI
23608e23 1211 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
cc446726 1212#endif
23608e23
JL		 1213 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1214 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1215 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1216 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1217 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1218 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1219 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
1220 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
1221 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
1222
1223 return 0;
1224}
1225
d95b6ab8 1226#ifndef CONFIG_MX6SX
5ea7f0e3
PKS		 1227void enable_ipu_clock(void)
1228{
1229 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1230 int reg;
1231 reg = readl(&mxc_ccm->CCGR3);
a0a0dacf 1232 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
5ea7f0e3 1233 writel(reg, &mxc_ccm->CCGR3);
8d779461
PF		 1234
1235 if (is_mx6dqp()) {
1236 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1237 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1238 }
5ea7f0e3 1239}
d95b6ab8 1240#endif
90d7cc42
AB		 1241
1242#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
1243 defined(CONFIG_MX6S)
1244static void disable_ldb_di_clock_sources(void)
1245{
1246 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1247 int reg;
1248
1249 /* Make sure PFDs are disabled at boot. */
1250 reg = readl(&mxc_ccm->analog_pfd_528);
1251 /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
b949fd2c 1252 if (is_mx6sdl())
90d7cc42
AB		 1253 reg |= 0x80008080;
1254 else
1255 reg |= 0x80808080;
1256 writel(reg, &mxc_ccm->analog_pfd_528);
1257
1258 /* Disable PLL3 PFDs */
1259 reg = readl(&mxc_ccm->analog_pfd_480);
1260 reg |= 0x80808080;
1261 writel(reg, &mxc_ccm->analog_pfd_480);
1262
1263 /* Disable PLL5 */
1264 reg = readl(&mxc_ccm->analog_pll_video);
1265 reg &= ~(1 << 13);
1266 writel(reg, &mxc_ccm->analog_pll_video);
1267}
1268
1269static void enable_ldb_di_clock_sources(void)
1270{
1271 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1272 int reg;
1273
1274 reg = readl(&mxc_ccm->analog_pfd_528);
b949fd2c 1275 if (is_mx6sdl())
90d7cc42
AB		 1276 reg &= ~(0x80008080);
1277 else
1278 reg &= ~(0x80808080);
1279 writel(reg, &mxc_ccm->analog_pfd_528);
1280
1281 reg = readl(&mxc_ccm->analog_pfd_480);
1282 reg &= ~(0x80808080);
1283 writel(reg, &mxc_ccm->analog_pfd_480);
1284}
1285
1286/*
1287 * Try call this function as early in the boot process as possible since the
1288 * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
1289 */
1290void select_ldb_di_clock_source(enum ldb_di_clock clk)
1291{
1292 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1293 int reg;
1294
1295 /*
1296 * Need to follow a strict procedure when changing the LDB
1297 * clock, else we can introduce a glitch. Things to keep in
1298 * mind:
1299 * 1. The current and new parent clocks must be disabled.
1300 * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
1301 * no CG bit.
1302 * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
1303 * the top four options are in one mux and the PLL3 option along
1304 * with another option is in the second mux. There is third mux
1305 * used to decide between the first and second mux.
1306 * The code below switches the parent to the bottom mux first
1307 * and then manipulates the top mux. This ensures that no glitch
1308 * will enter the divider.
1309 *
1310 * Need to disable MMDC_CH1 clock manually as there is no CG bit
1311 * for this clock. The only way to disable this clock is to move
1312 * it to pll3_sw_clk and then to disable pll3_sw_clk
1313 * Make sure periph2_clk2_sel is set to pll3_sw_clk
1314 */
1315
1316 /* Disable all ldb_di clock parents */
1317 disable_ldb_di_clock_sources();
1318
1319 /* Set MMDC_CH1 mask bit */
1320 reg = readl(&mxc_ccm->ccdr);
1321 reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1322 writel(reg, &mxc_ccm->ccdr);
1323
1324 /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
1325 reg = readl(&mxc_ccm->cbcmr);
1326 reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
1327 writel(reg, &mxc_ccm->cbcmr);
1328
1329 /*
1330 * Set the periph2_clk_sel to the top mux so that
1331 * mmdc_ch1 is from pll3_sw_clk.
1332 */
1333 reg = readl(&mxc_ccm->cbcdr);
1334 reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1335 writel(reg, &mxc_ccm->cbcdr);
1336
1337 /* Wait for the clock switch */
1338 while (readl(&mxc_ccm->cdhipr))
1339 ;
1340 /* Disable pll3_sw_clk by selecting bypass clock source */
1341 reg = readl(&mxc_ccm->ccsr);
1342 reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1343 writel(reg, &mxc_ccm->ccsr);
1344
1345 /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
1346 reg = readl(&mxc_ccm->cs2cdr);
1347 reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1348 | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1349 writel(reg, &mxc_ccm->cs2cdr);
1350
1351 /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
1352 reg = readl(&mxc_ccm->cs2cdr);
1353 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1354 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1355 reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1356 | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1357 writel(reg, &mxc_ccm->cs2cdr);
1358
1359 /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
1360 reg = readl(&mxc_ccm->cs2cdr);
1361 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1362 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1363 reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1364 | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1365 writel(reg, &mxc_ccm->cs2cdr);
1366
1367 /* Unbypass pll3_sw_clk */
1368 reg = readl(&mxc_ccm->ccsr);
1369 reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1370 writel(reg, &mxc_ccm->ccsr);
1371
1372 /*
1373 * Set the periph2_clk_sel back to the bottom mux so that
1374 * mmdc_ch1 is from its original parent.
1375 */
1376 reg = readl(&mxc_ccm->cbcdr);
1377 reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1378 writel(reg, &mxc_ccm->cbcdr);
1379
1380 /* Wait for the clock switch */
1381 while (readl(&mxc_ccm->cdhipr))
1382 ;
1383 /* Clear MMDC_CH1 mask bit */
1384 reg = readl(&mxc_ccm->ccdr);
1385 reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1386 writel(reg, &mxc_ccm->ccdr);
1387
1388 enable_ldb_di_clock_sources();
1389}
1390#endif
1391
4db4d42e
LM		 1392#ifndef CONFIG_SYS_NO_FLASH
1393void enable_eim_clk(unsigned char enable)
1394{
1395 u32 reg;
1396
1397 reg = __raw_readl(&imx_ccm->CCGR6);
1398 if (enable)
1399 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1400 else
1401 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1402 __raw_writel(reg, &imx_ccm->CCGR6);
1403}
1404#endif
1405
23608e23
JL		 1406/***************************************************/
1407
1408U_BOOT_CMD(
1409 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
1410 "display clocks",
1411 ""
1412);
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