[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / cpu_init.c

/*
 * (C) Copyright 2000-2007
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <watchdog.h>
#include <asm/ppc4xx-emac.h>
#include <asm/processor.h>
#include <asm/ppc4xx-gpio.h>
#include <asm/ppc4xx.h>

DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_SYS_PLL_RECONFIG
#define CONFIG_SYS_PLL_RECONFIG	0
#endif

#if defined(CONFIG_440EPX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
static void reset_with_rli(void)
{
	u32 reg;

	/*
	 * Set reload inhibit so configuration will persist across
	 * processor resets
	 */
	mfcpr(CPR0_ICFG, reg);
	reg |= CPR0_ICFG_RLI_MASK;
	mtcpr(CPR0_ICFG, reg);

	/* Reset processor if configuration changed */
	__asm__ __volatile__ ("sync; isync");
	mtspr(SPRN_DBCR0, 0x20000000);
}
#endif

void reconfigure_pll(u32 new_cpu_freq)
{
#if defined(CONFIG_440EPX)
	int	reset_needed = 0;
	u32	reg, temp;
	u32	prbdv0, target_prbdv0,				/* CLK_PRIMBD */
		fwdva, target_fwdva, fwdvb, target_fwdvb,	/* CLK_PLLD */
		fbdv, target_fbdv, lfbdv, target_lfbdv,
		perdv0,	target_perdv0,				/* CLK_PERD */
		spcid0,	target_spcid0;				/* CLK_SPCID */

	/* Reconfigure clocks if necessary.
	 * See PPC440EPx User's Manual, sections 8.2 and 14 */
	if (new_cpu_freq == 667) {
		target_prbdv0 = 2;
		target_fwdva = 2;
		target_fwdvb = 4;
		target_fbdv = 20;
		target_lfbdv = 1;
		target_perdv0 = 4;
		target_spcid0 = 4;

		mfcpr(CPR0_PRIMBD0, reg);
		temp = (reg & PRBDV_MASK) >> 24;
		prbdv0 = temp ? temp : 8;
		if (prbdv0 != target_prbdv0) {
			reg &= ~PRBDV_MASK;
			reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
			mtcpr(CPR0_PRIMBD0, reg);
			reset_needed = 1;
		}

		mfcpr(CPR0_PLLD, reg);

		temp = (reg & PLLD_FWDVA_MASK) >> 16;
		fwdva = temp ? temp : 16;

		temp = (reg & PLLD_FWDVB_MASK) >> 8;
		fwdvb = temp ? temp : 8;

		temp = (reg & PLLD_FBDV_MASK) >> 24;
		fbdv = temp ? temp : 32;

		temp = (reg & PLLD_LFBDV_MASK);
		lfbdv = temp ? temp : 64;

		if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
			reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
				 PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
			reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
				((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
				((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
				(target_lfbdv == 64 ? 0 : target_lfbdv);
			mtcpr(CPR0_PLLD, reg);
			reset_needed = 1;
		}

		mfcpr(CPR0_PERD, reg);
		perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
		if (perdv0 != target_perdv0) {
			reg &= ~CPR0_PERD_PERDV0_MASK;
			reg |= (target_perdv0 << 24);
			mtcpr(CPR0_PERD, reg);
			reset_needed = 1;
		}

		mfcpr(CPR0_SPCID, reg);
		temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
		spcid0 = temp ? temp : 4;
		if (spcid0 != target_spcid0) {
			reg &= ~CPR0_SPCID_SPCIDV0_MASK;
			reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
			mtcpr(CPR0_SPCID, reg);
			reset_needed = 1;
		}
	}

	/* Get current value of FWDVA.*/
	mfcpr(CPR0_PLLD, reg);
	temp = (reg & PLLD_FWDVA_MASK) >> 16;

	/*
	 * Check to see if FWDVA has been set to value of 1. if it has we must
	 * modify it.
	 */
	if (temp == 1) {
		/*
		 * Load register that contains current boot strapping option.
		 */
		mfcpr(CPR0_ICFG, reg);
		/*
		 * Strapping option bits (ICS) are already in correct position,
		 * only masking needed.
		 */
		reg &= CPR0_ICFG_ICS_MASK;

		if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
		    (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
			mfcpr(CPR0_PLLD, reg);

			/* Get current value of fbdv.  */
			temp = (reg & PLLD_FBDV_MASK) >> 24;
			fbdv = temp ? temp : 32;

			/* Get current value of lfbdv. */
			temp = (reg & PLLD_LFBDV_MASK);
			lfbdv = temp ? temp : 64;

			/*
			 * Get current value of FWDVA. Assign current FWDVA to
			 * new FWDVB.
			 */
			mfcpr(CPR0_PLLD, reg);
			target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
			fwdvb = target_fwdvb ? target_fwdvb : 8;

			/*
			 * Get current value of FWDVB. Assign current FWDVB to
			 * new FWDVA.
			 */
			target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
			fwdva = target_fwdva ? target_fwdva : 16;

			/*
			 * Update CPR0_PLLD with switched FWDVA and FWDVB.
			 */
			reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
				PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
			reg |= ((fwdva == 16 ? 0 : fwdva) << 16) |
				((fwdvb == 8 ? 0 : fwdvb) << 8) |
				((fbdv == 32 ? 0 : fbdv) << 24) |
				(lfbdv == 64 ? 0 : lfbdv);
			mtcpr(CPR0_PLLD, reg);

			/* Acknowledge that a reset is required. */
			reset_needed = 1;
		}
	}

	/* Now reset the CPU if needed */
	if (reset_needed)
		reset_with_rli();
#endif

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
	u32 reg;

	/*
	 * See "9.2.1.1 Booting with Option E" in the 460EX/GT
	 * users manual
	 */
	mfcpr(CPR0_PLLC, reg);
	if ((reg & (CPR0_PLLC_RST | CPR0_PLLC_ENG)) == CPR0_PLLC_RST) {
		/*
		 * Set engage bit
		 */
		reg = (reg & ~CPR0_PLLC_RST) | CPR0_PLLC_ENG;
		mtcpr(CPR0_PLLC, reg);

		/* Now reset the CPU */
		reset_with_rli();
	}
#endif
}

#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
void
chip_21_errata(void)
{
	/*
	 * See rev 1.09 of the 405EX/405EXr errata.  CHIP_21 says that
	 * sometimes reading the PVR and/or SDR0_ECID results in incorrect
	 * values.  Since the rev-D chip uses the SDR0_ECID bits to control
	 * internal features, that means the second PCIe or ethernet of an EX
	 * variant could fail to work.  Also, security features of both EX and
	 * EXr might be incorrectly disabled.
	 *
	 * The suggested workaround is as follows (covering rev-C and rev-D):
	 *
	 * 1.Read the PVR and SDR0_ECID3.
	 *
	 * 2.If the PVR matches an expected Revision C PVR value AND if
	 * SDR0_ECID3[12:15] is different from PVR[28:31], then processor is
	 * Revision C: continue executing the initialization code (no reset
	 * required).  else go to step 3.
	 *
	 * 3.If the PVR matches an expected Revision D PVR value AND if
	 * SDR0_ECID3[10:11] matches its expected value, then continue
	 * executing initialization code, no reset required.  else write
	 * DBCR0[RST] = 0b11 to generate a SysReset.
	 */

	u32 pvr;
	u32 pvr_28_31;
	u32 ecid3;
	u32 ecid3_10_11;
	u32 ecid3_12_15;

	/* Step 1: */
	pvr = get_pvr();
	mfsdr(SDR0_ECID3, ecid3);

	/* Step 2: */
	pvr_28_31 = pvr & 0xf;
	ecid3_10_11 = (ecid3 >> 20) & 0x3;
	ecid3_12_15 = (ecid3 >> 16) & 0xf;
	if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_C) &&
			(pvr_28_31 != ecid3_12_15)) {
		/* No reset required. */
		return;
	}

	/* Step 3: */
	if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_D) &&
			(ecid3_10_11 == CONFIG_405EX_CHIP21_ECID3_REV_D)) {
		/* No reset required. */
		return;
	}

	/* Reset required. */
	__asm__ __volatile__ ("sync; isync");
	mtspr(SPRN_DBCR0, 0x30000000);
}
#endif

/*
 * Breath some life into the CPU...
 *
 * Reconfigure PLL if necessary,
 * set up the memory map,
 * initialize a bunch of registers
 */
void
cpu_init_f (void)
{
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
	u32 val;
#endif

#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
	chip_21_errata();
#endif

	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);

#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
    !defined(CONFIG_SYS_4xx_GPIO_TABLE)
	/*
	 * GPIO0 setup (select GPIO or alternate function)
	 */
#if defined(CONFIG_SYS_GPIO0_OR)
	out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR);		/* set initial state of output pins	*/
#endif
#if defined(CONFIG_SYS_GPIO0_ODR)
	out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR);	/* open-drain select			*/
#endif
	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH);	/* output select			*/
	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H);	/* input select				*/
	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH);	/* three-state select			*/
	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
#if defined(CONFIG_SYS_GPIO0_ISR2H)
	out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
	out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
#endif
#if defined (CONFIG_SYS_GPIO0_TCR)
	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);	/* enable output driver for outputs	*/
#endif
#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */

#if defined (CONFIG_405EP)
	/*
	 * Set EMAC noise filter bits
	 */
	mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE);
#endif /* CONFIG_405EP */

#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
	gpio_set_chip_configuration();
#endif /* CONFIG_SYS_4xx_GPIO_TABLE */

	/*
	 * External Bus Controller (EBC) Setup
	 */
#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
#if (defined(CONFIG_405GP) || \
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
     defined(CONFIG_405EX) || defined(CONFIG_405))
	/*
	 * Move the next instructions into icache, since these modify the flash
	 * we are running from!
	 */
	asm volatile("	bl	0f"		::: "lr");
	asm volatile("0:	mflr	3"		::: "r3");
	asm volatile("	addi	4, 0, 14"	::: "r4");
	asm volatile("	mtctr	4"		::: "ctr");
	asm volatile("1:	icbt	0, 3");
	asm volatile("	addi	3, 3, 32"	::: "r3");
	asm volatile("	bdnz	1b"		::: "ctr", "cr0");
	asm volatile("	addis	3, 0, 0x0"	::: "r3");
	asm volatile("	ori	3, 3, 0xA000"	::: "r3");
	asm volatile("	mtctr	3"		::: "ctr");
	asm volatile("2:	bdnz	2b"		::: "ctr", "cr0");
#endif

	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
	mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
	mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
	mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
	mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
	mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
	mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
	mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
	mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
	mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
	mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
	mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
	mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
#endif

#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
	mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
	mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
#endif

#if defined (CONFIG_SYS_EBC_CFG)
	mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
#endif

#if defined(CONFIG_WATCHDOG)
	val = mfspr(SPRN_TCR);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
	val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
#elif defined(CONFIG_440EPX)
	val |= 0xb0000000;      /* generate system reset after 1.34 seconds */
#else
	val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
#endif
#if defined(CONFIG_SYS_4xx_RESET_TYPE)
	val &= ~0x30000000;			/* clear WRC bits */
	val |= CONFIG_SYS_4xx_RESET_TYPE << 28;	/* set board specific WRC type */
#endif
	mtspr(SPRN_TCR, val);

	val = mfspr(SPRN_TSR);
	val |= 0x80000000;      /* enable watchdog timer */
	mtspr(SPRN_TSR, val);

	reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */

#if defined(CONFIG_440GX)
	/* Take the GX out of compatibility mode
	 * Travis Sawyer, 9 Mar 2004
	 * NOTE: 440gx user manual inconsistency here
	 *       Compatibility mode and Ethernet Clock select are not
	 *       correct in the manual
	 */
	mfsdr(SDR0_MFR, val);
	val &= ~0x10000000;
	mtsdr(SDR0_MFR,val);
#endif /* CONFIG_440GX */

#if defined(CONFIG_460EX)
	/*
	 * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
	 * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
	 * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
	 */
	mfsdr(SDR0_AHB_CFG, val);
	val |= 0x80;
	val &= ~0x40;
	mtsdr(SDR0_AHB_CFG, val);
	mfsdr(SDR0_USB2HOST_CFG, val);
	val &= ~0xf00;
	val |= 0x400;
	mtsdr(SDR0_USB2HOST_CFG, val);
#endif /* CONFIG_460EX */

#if defined(CONFIG_405EX) || \
    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
    defined(CONFIG_460SX)
	/*
	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
	 */
	mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
	      PLB4Ax_ACR_RDP_4DEEP);
	mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
	      PLB4Ax_ACR_RDP_4DEEP);
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
}

/*
 * initialize higher level parts of CPU like time base and timers
 */
int cpu_init_r (void)
{
#if defined(CONFIG_405GP)
	uint pvr = get_pvr();

	/*
	 * Set edge conditioning circuitry on PPC405GPr
	 * for compatibility to existing PPC405GP designs.
	 */
	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
		mtdcr(CPC0_ECR, 0x60606000);
	}
#endif  /* defined(CONFIG_405GP) */

	return 0;
}

#if defined(CONFIG_PCI) && \
	(defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
	 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
/*
 * 440EP(x)/GR(x) PCI async/sync clocking restriction:
 *
 * In asynchronous PCI mode, the synchronous PCI clock must meet
 * certain requirements. The following equation describes the
 * relationship that must be maintained between the asynchronous PCI
 * clock and synchronous PCI clock. Select an appropriate PCI:PLB
 * ratio to maintain the relationship:
 *
 * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
 */
static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
{
	if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000)))
		return 0;
	else
		return 1;
}

int ppc4xx_pci_sync_clock_config(u32 async)
{
	sys_info_t sys_info;
	u32 sync;
	int div;
	u32 reg;
	u32 spcid_val[] = {
		CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
		CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };

	get_sys_info(&sys_info);
	sync = sys_info.freqPCI;

	/*
	 * First check if the equation above is met
	 */
	if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
		/*
		 * Reconfigure PCI sync clock to meet the equation.
		 * Start with highest possible PCI sync frequency
		 * (divider 1).
		 */
		for (div = 1; div <= 4; div++) {
			sync = sys_info.freqPLB / div;
			if (ppc4xx_pci_sync_clock_ok(sync, async))
			    break;
		}

		if (div <= 4) {
			mtcpr(CPR0_SPCID, spcid_val[div]);

			mfcpr(CPR0_ICFG, reg);
			reg |= CPR0_ICFG_RLI_MASK;
			mtcpr(CPR0_ICFG, reg);

			/* do chip reset */
			mtspr(SPRN_DBCR0, 0x20000000);
		} else {
			/* Impossible to configure the PCI sync clock */
			return -1;
		}
	}

	return 0;
}
#endif
Commit	Line	Data
4a9cbbe8	1	/*
dbbd1257	2	* (C) Copyright 2000-2007
4a9cbbe8 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4a9cbbe8 WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
4a9cbbe8 WD	6	*/
	7
	8	#include <common.h>
	9	#include <watchdog.h>
b36df561	10	#include <asm/ppc4xx-emac.h>
4a9cbbe8	11	#include <asm/processor.h>
09887762	12	#include <asm/ppc4xx-gpio.h>
b36df561	13	#include <asm/ppc4xx.h>
4a9cbbe8	14
d87080b7	15	DECLARE_GLOBAL_DATA_PTR;
d87080b7	16
6d0f6bcf JCPV	17	#ifndef CONFIG_SYS_PLL_RECONFIG
6d0f6bcf JCPV	18	#define CONFIG_SYS_PLL_RECONFIG 0
f66e2c8b MN	19	#endif
f66e2c8b MN	20
fe7cca71 SR	21	#if defined(CONFIG_440EPX) \|\| \
	22	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	23	static void reset_with_rli(void)
	24	{
	25	u32 reg;
	26
	27	/*
	28	* Set reload inhibit so configuration will persist across
	29	* processor resets
	30	*/
	31	mfcpr(CPR0_ICFG, reg);
	32	reg \|= CPR0_ICFG_RLI_MASK;
	33	mtcpr(CPR0_ICFG, reg);
	34
	35	/* Reset processor if configuration changed */
	36	__asm__ __volatile__ ("sync; isync");
	37	mtspr(SPRN_DBCR0, 0x20000000);
	38	}
	39	#endif
	40
f66e2c8b MN	41	void reconfigure_pll(u32 new_cpu_freq)
	42	{
	43	#if defined(CONFIG_440EPX)
	44	int reset_needed = 0;
	45	u32 reg, temp;
	46	u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
	47	fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
	48	fbdv, target_fbdv, lfbdv, target_lfbdv,
	49	perdv0, target_perdv0, /* CLK_PERD */
	50	spcid0, target_spcid0; /* CLK_SPCID */
	51
	52	/* Reconfigure clocks if necessary.
	53	* See PPC440EPx User's Manual, sections 8.2 and 14 */
	54	if (new_cpu_freq == 667) {
	55	target_prbdv0 = 2;
	56	target_fwdva = 2;
	57	target_fwdvb = 4;
	58	target_fbdv = 20;
	59	target_lfbdv = 1;
	60	target_perdv0 = 4;
	61	target_spcid0 = 4;
	62
ddc922ff	63	mfcpr(CPR0_PRIMBD0, reg);
f66e2c8b MN	64	temp = (reg & PRBDV_MASK) >> 24;
	65	prbdv0 = temp ? temp : 8;
	66	if (prbdv0 != target_prbdv0) {
	67	reg &= ~PRBDV_MASK;
	68	reg \|= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
ddc922ff	69	mtcpr(CPR0_PRIMBD0, reg);
f66e2c8b MN	70	reset_needed = 1;
	71	}
	72
d1c3b275	73	mfcpr(CPR0_PLLD, reg);
f66e2c8b MN	74
	75	temp = (reg & PLLD_FWDVA_MASK) >> 16;
	76	fwdva = temp ? temp : 16;
	77
	78	temp = (reg & PLLD_FWDVB_MASK) >> 8;
	79	fwdvb = temp ? temp : 8;
	80
	81	temp = (reg & PLLD_FBDV_MASK) >> 24;
	82	fbdv = temp ? temp : 32;
	83
	84	temp = (reg & PLLD_LFBDV_MASK);
	85	lfbdv = temp ? temp : 64;
	86
	87	if (fwdva != target_fwdva \|\| fbdv != target_fbdv \|\| lfbdv != target_lfbdv) {
	88	reg &= ~(PLLD_FWDVA_MASK \| PLLD_FWDVB_MASK \|
	89	PLLD_FBDV_MASK \| PLLD_LFBDV_MASK);
	90	reg \|= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) \|
	91	((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) \|
	92	((target_fbdv == 32 ? 0 : target_fbdv) << 24) \|
	93	(target_lfbdv == 64 ? 0 : target_lfbdv);
d1c3b275	94	mtcpr(CPR0_PLLD, reg);
f66e2c8b MN	95	reset_needed = 1;
	96	}
	97
d1c3b275	98	mfcpr(CPR0_PERD, reg);
f66e2c8b MN	99	perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
	100	if (perdv0 != target_perdv0) {
	101	reg &= ~CPR0_PERD_PERDV0_MASK;
	102	reg \|= (target_perdv0 << 24);
d1c3b275	103	mtcpr(CPR0_PERD, reg);
f66e2c8b MN	104	reset_needed = 1;
	105	}
	106
d1c3b275	107	mfcpr(CPR0_SPCID, reg);
f66e2c8b MN	108	temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
	109	spcid0 = temp ? temp : 4;
	110	if (spcid0 != target_spcid0) {
	111	reg &= ~CPR0_SPCID_SPCIDV0_MASK;
	112	reg \|= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
d1c3b275	113	mtcpr(CPR0_SPCID, reg);
f66e2c8b MN	114	reset_needed = 1;
f66e2c8b MN	115	}
c550afad RS	116	}
	117
	118	/* Get current value of FWDVA.*/
	119	mfcpr(CPR0_PLLD, reg);
	120	temp = (reg & PLLD_FWDVA_MASK) >> 16;
f66e2c8b	121
c550afad RS	122	/*
	123	* Check to see if FWDVA has been set to value of 1. if it has we must
	124	* modify it.
	125	*/
	126	if (temp == 1) {
c550afad RS	127	/*
	128	* Load register that contains current boot strapping option.
	129	*/
	130	mfcpr(CPR0_ICFG, reg);
c1ab75c7 SR	131	/*
	132	* Strapping option bits (ICS) are already in correct position,
	133	* only masking needed.
	134	*/
	135	reg &= CPR0_ICFG_ICS_MASK;
c550afad RS	136
	137	if ((reg == BOOT_STRAP_OPTION_A) \|\| (reg == BOOT_STRAP_OPTION_B) \|\|
	138	(reg == BOOT_STRAP_OPTION_D) \|\| (reg == BOOT_STRAP_OPTION_E)) {
c1ab75c7 SR	139	mfcpr(CPR0_PLLD, reg);
	140
	141	/* Get current value of fbdv. */
	142	temp = (reg & PLLD_FBDV_MASK) >> 24;
	143	fbdv = temp ? temp : 32;
	144
	145	/* Get current value of lfbdv. */
	146	temp = (reg & PLLD_LFBDV_MASK);
	147	lfbdv = temp ? temp : 64;
	148
c550afad RS	149	/*
	150	* Get current value of FWDVA. Assign current FWDVA to
	151	* new FWDVB.
	152	*/
	153	mfcpr(CPR0_PLLD, reg);
	154	target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
	155	fwdvb = target_fwdvb ? target_fwdvb : 8;
c1ab75c7	156
c550afad RS	157	/*
	158	* Get current value of FWDVB. Assign current FWDVB to
	159	* new FWDVA.
	160	*/
	161	target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
	162	fwdva = target_fwdva ? target_fwdva : 16;
c1ab75c7	163
c550afad RS	164	/*
	165	* Update CPR0_PLLD with switched FWDVA and FWDVB.
	166	*/
	167	reg &= ~(PLLD_FWDVA_MASK \| PLLD_FWDVB_MASK \|
	168	PLLD_FBDV_MASK \| PLLD_LFBDV_MASK);
	169	reg \|= ((fwdva == 16 ? 0 : fwdva) << 16) \|
	170	((fwdvb == 8 ? 0 : fwdvb) << 8) \|
	171	((fbdv == 32 ? 0 : fbdv) << 24) \|
	172	(lfbdv == 64 ? 0 : lfbdv);
	173	mtcpr(CPR0_PLLD, reg);
c1ab75c7	174
c550afad RS	175	/* Acknowledge that a reset is required. */
	176	reset_needed = 1;
	177	}
	178	}
	179
fe7cca71 SR	180	/* Now reset the CPU if needed */
	181	if (reset_needed)
	182	reset_with_rli();
	183	#endif
	184
	185	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	186	u32 reg;
	187
	188	/*
	189	* See "9.2.1.1 Booting with Option E" in the 460EX/GT
	190	* users manual
	191	*/
	192	mfcpr(CPR0_PLLC, reg);
	193	if ((reg & (CPR0_PLLC_RST \| CPR0_PLLC_ENG)) == CPR0_PLLC_RST) {
c550afad	194	/*
fe7cca71	195	* Set engage bit
c550afad	196	*/
fe7cca71 SR	197	reg = (reg & ~CPR0_PLLC_RST) \| CPR0_PLLC_ENG;
fe7cca71 SR	198	mtcpr(CPR0_PLLC, reg);
f66e2c8b	199
fe7cca71 SR	200	/* Now reset the CPU */
fe7cca71 SR	201	reset_with_rli();
f66e2c8b MN	202	}
	203	#endif
	204	}
	205
644362c4 SF	206	#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
	207	void
	208	chip_21_errata(void)
	209	{
	210	/*
	211	* See rev 1.09 of the 405EX/405EXr errata. CHIP_21 says that
	212	* sometimes reading the PVR and/or SDR0_ECID results in incorrect
	213	* values. Since the rev-D chip uses the SDR0_ECID bits to control
	214	* internal features, that means the second PCIe or ethernet of an EX
	215	* variant could fail to work. Also, security features of both EX and
	216	* EXr might be incorrectly disabled.
	217	*
	218	* The suggested workaround is as follows (covering rev-C and rev-D):
	219	*
	220	* 1.Read the PVR and SDR0_ECID3.
	221	*
	222	* 2.If the PVR matches an expected Revision C PVR value AND if
	223	* SDR0_ECID3[12:15] is different from PVR[28:31], then processor is
	224	* Revision C: continue executing the initialization code (no reset
	225	* required). else go to step 3.
	226	*
	227	* 3.If the PVR matches an expected Revision D PVR value AND if
	228	* SDR0_ECID3[10:11] matches its expected value, then continue
	229	* executing initialization code, no reset required. else write
	230	* DBCR0[RST] = 0b11 to generate a SysReset.
	231	*/
	232
	233	u32 pvr;
	234	u32 pvr_28_31;
	235	u32 ecid3;
	236	u32 ecid3_10_11;
	237	u32 ecid3_12_15;
	238
	239	/* Step 1: */
	240	pvr = get_pvr();
	241	mfsdr(SDR0_ECID3, ecid3);
	242
	243	/* Step 2: */
	244	pvr_28_31 = pvr & 0xf;
	245	ecid3_10_11 = (ecid3 >> 20) & 0x3;
	246	ecid3_12_15 = (ecid3 >> 16) & 0xf;
	247	if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_C) &&
	248	(pvr_28_31 != ecid3_12_15)) {
	249	/* No reset required. */
	250	return;
	251	}
	252
	253	/* Step 3: */
	254	if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_D) &&
	255	(ecid3_10_11 == CONFIG_405EX_CHIP21_ECID3_REV_D)) {
	256	/* No reset required. */
	257	return;
	258	}
	259
	260	/* Reset required. */
	261	__asm__ __volatile__ ("sync; isync");
	262	mtspr(SPRN_DBCR0, 0x30000000);
	263	}
	264	#endif
	265
4a9cbbe8 WD	266	/*
	267	* Breath some life into the CPU...
	268	*
f66e2c8b MN	269	* Reconfigure PLL if necessary,
f66e2c8b MN	270	* set up the memory map,
4a9cbbe8 WD	271	* initialize a bunch of registers
	272	*/
	273	void
	274	cpu_init_f (void)
	275	{
f5564837	276	#if defined(CONFIG_WATCHDOG) \|\| defined(CONFIG_440GX) \|\| defined(CONFIG_460EX)
745d8a0d	277	u32 val;
f11033e7	278	#endif
5de85140	279
644362c4 SF	280	#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
	281	chip_21_errata();
	282	#endif
	283
6d0f6bcf	284	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
f11033e7	285
1b8fec13	286	#if (defined(CONFIG_405EP) \|\| defined (CONFIG_405EX)) && \
9ed3246e	287	!defined(CONFIG_SYS_4xx_GPIO_TABLE)
b867d705 SR	288	/*
	289	* GPIO0 setup (select GPIO or alternate function)
	290	*/
6d0f6bcf JCPV	291	#if defined(CONFIG_SYS_GPIO0_OR)
6d0f6bcf JCPV	292	out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */
e0a46554	293	#endif
6d0f6bcf JCPV	294	#if defined(CONFIG_SYS_GPIO0_ODR)
6d0f6bcf JCPV	295	out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */
e0a46554	296	#endif
6d0f6bcf JCPV	297	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
	298	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
	299	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
	300	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
	301	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
	302	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
	303	#if defined(CONFIG_SYS_GPIO0_ISR2H)
	304	out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
	305	out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
dbbd1257	306	#endif
6d0f6bcf JCPV	307	#if defined (CONFIG_SYS_GPIO0_TCR)
6d0f6bcf JCPV	308	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
dbbd1257	309	#endif
6d0f6bcf	310	#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
b867d705	311
bec92646	312	#if defined (CONFIG_405EP)
b867d705 SR	313	/*
	314	* Set EMAC noise filter bits
	315	*/
afabb498	316	mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE \| CPC0_EPCTL_E1NFE);
b867d705 SR	317	#endif /* CONFIG_405EP */
b867d705 SR	318
6d0f6bcf	319	#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
0d974d52	320	gpio_set_chip_configuration();
6d0f6bcf	321	#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
a4c8d138	322
4a9cbbe8 WD	323	/*
	324	* External Bus Controller (EBC) Setup
	325	*/
6d0f6bcf	326	#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
3fb85889	327	#if (defined(CONFIG_405GP) \|\| \
e01bd218	328	defined(CONFIG_405EP) \|\| defined(CONFIG_405EZ) \|\| \
dbbd1257	329	defined(CONFIG_405EX) \|\| defined(CONFIG_405))
4a9cbbe8 WD	330	/*
	331	* Move the next instructions into icache, since these modify the flash
	332	* we are running from!
	333	*/
	334	asm volatile(" bl 0f" ::: "lr");
	335	asm volatile("0: mflr 3" ::: "r3");
1636d1c8	336	asm volatile(" addi 4, 0, 14" ::: "r4");
4a9cbbe8 WD	337	asm volatile(" mtctr 4" ::: "ctr");
	338	asm volatile("1: icbt 0, 3");
	339	asm volatile(" addi 3, 3, 32" ::: "r3");
	340	asm volatile(" bdnz 1b" ::: "ctr", "cr0");
	341	asm volatile(" addis 3, 0, 0x0" ::: "r3");
	342	asm volatile(" ori 3, 3, 0xA000" ::: "r3");
	343	asm volatile(" mtctr 3" ::: "ctr");
	344	asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
a4c8d138	345	#endif
4a9cbbe8	346
d1c3b275 SR	347	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
d1c3b275 SR	348	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
4a9cbbe8 WD	349	#endif
4a9cbbe8 WD	350
6d0f6bcf	351	#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
d1c3b275 SR	352	mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
d1c3b275 SR	353	mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
4a9cbbe8 WD	354	#endif
4a9cbbe8 WD	355
6d0f6bcf	356	#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
d1c3b275 SR	357	mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
d1c3b275 SR	358	mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
4a9cbbe8 WD	359	#endif
4a9cbbe8 WD	360
6d0f6bcf	361	#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
d1c3b275 SR	362	mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
d1c3b275 SR	363	mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
4a9cbbe8 WD	364	#endif
4a9cbbe8 WD	365
6d0f6bcf	366	#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
d1c3b275 SR	367	mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
d1c3b275 SR	368	mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
4a9cbbe8 WD	369	#endif
4a9cbbe8 WD	370
6d0f6bcf	371	#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
d1c3b275 SR	372	mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
d1c3b275 SR	373	mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
4a9cbbe8 WD	374	#endif
4a9cbbe8 WD	375
6d0f6bcf	376	#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
d1c3b275 SR	377	mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
d1c3b275 SR	378	mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
4a9cbbe8 WD	379	#endif
4a9cbbe8 WD	380
6d0f6bcf	381	#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
d1c3b275 SR	382	mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
d1c3b275 SR	383	mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
4a9cbbe8 WD	384	#endif
4a9cbbe8 WD	385
6d0f6bcf JCPV	386	#if defined (CONFIG_SYS_EBC_CFG)
6d0f6bcf JCPV	387	mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
ca43ba18	388	#endif
4a9cbbe8	389
f11033e7	390	#if defined(CONFIG_WATCHDOG)
f472069f	391	val = mfspr(SPRN_TCR);
846b0dd2	392	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
c157d8e2	393	val \|= 0xb8000000; /* generate system reset after 1.34 seconds */
a11e0696 IL	394	#elif defined(CONFIG_440EPX)
a11e0696 IL	395	val \|= 0xb0000000; /* generate system reset after 1.34 seconds */
c157d8e2	396	#else
4a9cbbe8	397	val \|= 0xf0000000; /* generate system reset after 2.684 seconds */
1c2ce226	398	#endif
6d0f6bcf	399	#if defined(CONFIG_SYS_4xx_RESET_TYPE)
1c2ce226	400	val &= ~0x30000000; /* clear WRC bits */
6d0f6bcf	401	val \|= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
c157d8e2	402	#endif
f472069f	403	mtspr(SPRN_TCR, val);
4a9cbbe8	404
f472069f	405	val = mfspr(SPRN_TSR);
4a9cbbe8	406	val \|= 0x80000000; /* enable watchdog timer */
f472069f	407	mtspr(SPRN_TSR, val);
4a9cbbe8 WD	408
	409	reset_4xx_watchdog();
	410	#endif /* CONFIG_WATCHDOG */
745d8a0d	411
5de85140 SR	412	#if defined(CONFIG_440GX)
	413	/* Take the GX out of compatibility mode
	414	* Travis Sawyer, 9 Mar 2004
	415	* NOTE: 440gx user manual inconsistency here
	416	* Compatibility mode and Ethernet Clock select are not
	417	* correct in the manual
	418	*/
d1c3b275	419	mfsdr(SDR0_MFR, val);
5de85140	420	val &= ~0x10000000;
d1c3b275	421	mtsdr(SDR0_MFR,val);
5de85140 SR	422	#endif /* CONFIG_440GX */
5de85140 SR	423
745d8a0d SR	424	#if defined(CONFIG_460EX)
	425	/*
	426	* Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
	427	* clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
	428	* regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
	429	*/
	430	mfsdr(SDR0_AHB_CFG, val);
	431	val \|= 0x80;
	432	val &= ~0x40;
	433	mtsdr(SDR0_AHB_CFG, val);
	434	mfsdr(SDR0_USB2HOST_CFG, val);
	435	val &= ~0xf00;
	436	val \|= 0x400;
	437	mtsdr(SDR0_USB2HOST_CFG, val);
	438	#endif /* CONFIG_460EX */
079589bc	439
f5564837 SR	440	#if defined(CONFIG_405EX) \|\| \
f5564837 SR	441	defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE) \|\| \
079589bc	442	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT) \|\| \
9ed3246e	443	defined(CONFIG_460SX)
079589bc PH	444	/*
	445	* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
	446	*/
5e7abce9 SR	447	mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) \|
	448	PLB4Ax_ACR_RDP_4DEEP);
	449	mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) \|
	450	PLB4Ax_ACR_RDP_4DEEP);
079589bc	451	#endif /* CONFIG_440SP/SPE \|\| CONFIG_460EX/GT \|\| CONFIG_405EX */
4a9cbbe8 WD	452	}
	453
	454	/*
	455	* initialize higher level parts of CPU like time base and timers
	456	*/
	457	int cpu_init_r (void)
	458	{
b867d705	459	#if defined(CONFIG_405GP)
38daa27d	460	uint pvr = get_pvr();
38daa27d SR	461
	462	/*
	463	* Set edge conditioning circuitry on PPC405GPr
	464	* for compatibility to existing PPC405GP designs.
	465	*/
baa3d528	466	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
d1c3b275	467	mtdcr(CPC0_ECR, 0x60606000);
38daa27d	468	}
b867d705	469	#endif /* defined(CONFIG_405GP) */
2801b2d2	470
9cd69016	471	return 0;
4a9cbbe8	472	}
5e47f953 SR	473
	474	#if defined(CONFIG_PCI) && \
	475	(defined(CONFIG_440EP) \|\| defined(CONFIG_440EPX) \|\| \
	476	defined(CONFIG_440GR) \|\| defined(CONFIG_440GRX))
	477	/*
	478	* 440EP(x)/GR(x) PCI async/sync clocking restriction:
	479	*
	480	* In asynchronous PCI mode, the synchronous PCI clock must meet
	481	* certain requirements. The following equation describes the
	482	* relationship that must be maintained between the asynchronous PCI
	483	* clock and synchronous PCI clock. Select an appropriate PCI:PLB
	484	* ratio to maintain the relationship:
	485	*
	486	* AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
	487	*/
	488	static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
	489	{
	490	if (((async - 1000000) > sync) \|\| (sync > ((2 * async) - 1000000)))
	491	return 0;
	492	else
	493	return 1;
	494	}
	495
	496	int ppc4xx_pci_sync_clock_config(u32 async)
	497	{
	498	sys_info_t sys_info;
	499	u32 sync;
	500	int div;
	501	u32 reg;
	502	u32 spcid_val[] = {
	503	CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
	504	CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };
	505
	506	get_sys_info(&sys_info);
	507	sync = sys_info.freqPCI;
	508
	509	/*
	510	* First check if the equation above is met
	511	*/
	512	if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
	513	/*
	514	* Reconfigure PCI sync clock to meet the equation.
	515	* Start with highest possible PCI sync frequency
	516	* (divider 1).
	517	*/
	518	for (div = 1; div <= 4; div++) {
	519	sync = sys_info.freqPLB / div;
	520	if (ppc4xx_pci_sync_clock_ok(sync, async))
	521	break;
	522	}
	523
	524	if (div <= 4) {
	525	mtcpr(CPR0_SPCID, spcid_val[div]);
	526
	527	mfcpr(CPR0_ICFG, reg);
	528	reg \|= CPR0_ICFG_RLI_MASK;
	529	mtcpr(CPR0_ICFG, reg);
	530
	531	/* do chip reset */
	532	mtspr(SPRN_DBCR0, 0x20000000);
	533	} else {
	534	/* Impossible to configure the PCI sync clock */
	535	return -1;
	536	}
537	}
538
539	return 0;
540	}
541	#endif