[people/ms/u-boot.git] / board / amcc / sequoia / sequoia.c

/*
 * (C) Copyright 2006-2009
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * (C) Copyright 2006
 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
 * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/ppc4xx.h>
#include <asm/ppc4xx-gpio.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/bitops.h>

DECLARE_GLOBAL_DATA_PTR;

#if !defined(CONFIG_SYS_NO_FLASH)
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
#endif

extern void __ft_board_setup(void *blob, bd_t *bd);
ulong flash_get_size(ulong base, int banknum);

static inline u32 get_async_pci_freq(void)
{
	if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
		CONFIG_SYS_BCSR5_PCI66EN)
		return 66666666;
	else
		return 33333333;
}

int board_early_init_f(void)
{
	u32 sdr0_cust0;
	u32 sdr0_pfc1, sdr0_pfc2;
	u32 reg;

	mtdcr(EBC0_CFGADDR, EBC0_CFG);
	mtdcr(EBC0_CFGDATA, 0xb8400000);

	/*
	 * Setup the interrupt controller polarities, triggers, etc.
	 */
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
	mtdcr(UIC0ER, 0x00000000);	/* disable all */
	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */

	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
	mtdcr(UIC1ER, 0x00000000);	/* disable all */
	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC1SR, 0xffffffff);	/* clear all */

	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
	mtdcr(UIC2ER, 0x00000000);	/* disable all */
	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC2SR, 0xffffffff);	/* clear all */

	/* Check and reconfigure the PCI sync clock if necessary */
	ppc4xx_pci_sync_clock_config(get_async_pci_freq());

	/* 50MHz tmrclk */
	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);

	/* clear write protects */
	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);

	/* enable Ethernet */
	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);

	/* enable USB device */
	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);

	/* select Ethernet (and optionally IIC1) pins */
	mfsdr(SDR0_PFC1, sdr0_pfc1);
	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
		SDR0_PFC1_SELECT_CONFIG_4;
#ifdef CONFIG_I2C_MULTI_BUS
	sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
#endif
	/* Two UARTs, so we need 4-pin mode.  Also, we want CTS/RTS mode. */
	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;

	mfsdr(SDR0_PFC2, sdr0_pfc2);
	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
		SDR0_PFC2_SELECT_CONFIG_4;
	mtsdr(SDR0_PFC2, sdr0_pfc2);
	mtsdr(SDR0_PFC1, sdr0_pfc1);

	/* PCI arbiter enabled */
	mfsdr(SDR0_PCI0, reg);
	mtsdr(SDR0_PCI0, 0x80000000 | reg);

	/* setup NAND FLASH */
	mfsdr(SDR0_CUST0, sdr0_cust0);
	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
		SDR0_CUST0_NDFC_ENABLE		|
		SDR0_CUST0_NDFC_BW_8_BIT	|
		SDR0_CUST0_NDFC_ARE_MASK	|
		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
	mtsdr(SDR0_CUST0, sdr0_cust0);

	return 0;
}

int misc_init_r(void)
{
#if !defined(CONFIG_SYS_NO_FLASH)
	uint pbcr;
	int size_val = 0;
#endif
#ifdef CONFIG_440EPX
	unsigned long usb2d0cr = 0;
	unsigned long usb2phy0cr, usb2h0cr = 0;
	unsigned long sdr0_pfc1;
	char *act = getenv("usbact");
#endif
	u32 reg;

#if !defined(CONFIG_SYS_NO_FLASH)
	/* Re-do flash sizing to get full correct info */

	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

#if defined(CONFIG_SYS_RAMBOOT)
	mtdcr(EBC0_CFGADDR, PB3CR);
#else
	mtdcr(EBC0_CFGADDR, PB0CR);
#endif
	pbcr = mfdcr(EBC0_CFGDATA);
	size_val = ffs(gd->bd->bi_flashsize) - 21;
	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_SYS_RAMBOOT)
	mtdcr(EBC0_CFGADDR, PB3CR);
#else
	mtdcr(EBC0_CFGADDR, PB0CR);
#endif
	mtdcr(EBC0_CFGDATA, pbcr);

	/*
	 * Re-check to get correct base address
	 */
	flash_get_size(gd->bd->bi_flashstart, 0);

#ifdef CONFIG_ENV_IS_IN_FLASH
	/* Monitor protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    -CONFIG_SYS_MONITOR_LEN,
			    0xffffffff,
			    &flash_info[0]);

	/* Env protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    CONFIG_ENV_ADDR_REDUND,
			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
			    &flash_info[0]);
#endif
#endif /* CONFIG_SYS_NO_FLASH */

	/*
	 * USB suff...
	 */
#ifdef CONFIG_440EPX
	if (act == NULL || strcmp(act, "hostdev") == 0) {
		/* SDR Setting */
		mfsdr(SDR0_PFC1, sdr0_pfc1);
		mfsdr(SDR0_USB2D0CR, usb2d0cr);
		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
		mfsdr(SDR0_USB2H0CR, usb2h0cr);

		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;

		/*
		 * An 8-bit/60MHz interface is the only possible alternative
		 * when connecting the Device to the PHY
		 */
		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;

		/*
		 * To enable the USB 2.0 Device function
		 * through the UTMI interface
		 */
		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;

		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;

		mtsdr(SDR0_PFC1, sdr0_pfc1);
		mtsdr(SDR0_USB2D0CR, usb2d0cr);
		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
		mtsdr(SDR0_USB2H0CR, usb2h0cr);

		/*clear resets*/
		udelay (1000);
		mtsdr(SDR0_SRST1, 0x00000000);
		udelay (1000);
		mtsdr(SDR0_SRST0, 0x00000000);

		printf("USB:   Host(int phy) Device(ext phy)\n");

	} else if (strcmp(act, "dev") == 0) {
		/*-------------------PATCH-------------------------------*/
		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);

		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);

		udelay (1000);
		mtsdr(SDR0_SRST1, 0x672c6000);

		udelay (1000);
		mtsdr(SDR0_SRST0, 0x00000080);

		udelay (1000);
		mtsdr(SDR0_SRST1, 0x60206000);

		*(unsigned int *)(0xe0000350) = 0x00000001;

		udelay (1000);
		mtsdr(SDR0_SRST1, 0x60306000);
		/*-------------------PATCH-------------------------------*/

		/* SDR Setting */
		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
		mfsdr(SDR0_USB2H0CR, usb2h0cr);
		mfsdr(SDR0_USB2D0CR, usb2d0cr);
		mfsdr(SDR0_PFC1, sdr0_pfc1);

		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;

		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;

		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;

		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;

		mtsdr(SDR0_USB2H0CR, usb2h0cr);
		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
		mtsdr(SDR0_USB2D0CR, usb2d0cr);
		mtsdr(SDR0_PFC1, sdr0_pfc1);

		/* clear resets */
		udelay (1000);
		mtsdr(SDR0_SRST1, 0x00000000);
		udelay (1000);
		mtsdr(SDR0_SRST0, 0x00000000);

		printf("USB:   Device(int phy)\n");
	}
#endif /* CONFIG_440EPX */

	mfsdr(SDR0_SRST1, reg);		/* enable security/kasumi engines */
	reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
	mtsdr(SDR0_SRST1, reg);

	/*
	 * Clear PLB4A0_ACR[WRP]
	 * This fix will make the MAL burst disabling patch for the Linux
	 * EMAC driver obsolete.
	 */
	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
	mtdcr(PLB4A0_ACR, reg);

	return 0;
}

int checkboard(void)
{
	char buf[64];
	int i = getenv_f("serial#", buf, sizeof(buf));
	u8 rev;
	u32 clock = get_async_pci_freq();

#ifdef CONFIG_440EPX
	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
#else
	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif

	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
	printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);

	if (i > 0) {
		puts(", serial# ");
		puts(buf);
	}
	putc('\n');

	/*
	 * Reconfiguration of the PCI sync clock is already done,
	 * now check again if everything is in range:
	 */
	if (ppc4xx_pci_sync_clock_config(clock)) {
		printf("ERROR: PCI clocking incorrect (async=%d "
		       "sync=%ld)!\n", clock, get_PCI_freq());
	}

	return (0);
}

#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
/*
 * Assign interrupts to PCI devices.
 */
void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
}
#endif

#if defined(CONFIG_SYS_RAMBOOT)
/*
 * On NAND-booting sequoia, we need to patch the chips select numbers
 * in the dtb (CS0 - NAND, CS3 - NOR)
 */
void ft_board_setup(void *blob, bd_t *bd)
{
	int rc;
	int len;
	int nodeoffset;
	struct fdt_property *prop;
	u32 *reg;
	char path[32];

	/* First do common fdt setup */
	__ft_board_setup(blob, bd);

	/* And now configure NOR chip select to 3 instead of 0 */
	strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
	nodeoffset = fdt_path_offset(blob, path);
	prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
	if (prop == NULL) {
		printf("Unable to update NOR chip select for NAND booting\n");
		return;
	}
	reg = (u32 *)&prop->data[0];
	reg[0] = 3;
	rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
	if (rc) {
		printf("Unable to update property NOR mappings, err=%s\n",
		       fdt_strerror(rc));
		return;
	}

	/* And now configure NAND chip select to 0 instead of 3 */
	strcpy(path, "/plb/opb/ebc/ndfc@3,0");
	nodeoffset = fdt_path_offset(blob, path);
	prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
	if (prop == NULL) {
		printf("Unable to update NDFC chip select for NAND booting\n");
		return;
	}
	reg = (u32 *)&prop->data[0];
	reg[0] = 0;
	rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
	if (rc) {
		printf("Unable to update property NDFC mappings, err=%s\n",
		       fdt_strerror(rc));
		return;
	}
}
#endif /* CONFIG_SYS_RAMBOOT */
Commit	Line	Data
887e2ec9	1	/*
5132106a	2	* (C) Copyright 2006-2009
887e2ec9 SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* (C) Copyright 2006
	6	* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
865f0f97	7	* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
887e2ec9	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
887e2ec9 SR	10	*/
	11
	12	#include <common.h>
13628884 SR	13	#include <libfdt.h>
13628884 SR	14	#include <fdt_support.h>
b36df561	15	#include <asm/ppc4xx.h>
09887762	16	#include <asm/ppc4xx-gpio.h>
887e2ec9	17	#include <asm/processor.h>
5a5958b7	18	#include <asm/io.h>
83a49c8d	19	#include <asm/bitops.h>
887e2ec9 SR	20
	21	DECLARE_GLOBAL_DATA_PTR;
	22
d873133f	23	#if !defined(CONFIG_SYS_NO_FLASH)
6d0f6bcf	24	extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
d873133f	25	#endif
887e2ec9	26
5132106a SR	27	extern void __ft_board_setup(void blob, bd_t bd);
5132106a SR	28	ulong flash_get_size(ulong base, int banknum);
1b3c360c	29
23c51a2d SR	30	static inline u32 get_async_pci_freq(void)
	31	{
	32	if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
	33	CONFIG_SYS_BCSR5_PCI66EN)
	34	return 66666666;
	35	else
	36	return 33333333;
	37	}
	38
887e2ec9 SR	39	int board_early_init_f(void)
887e2ec9 SR	40	{
a78bc443 SR	41	u32 sdr0_cust0;
	42	u32 sdr0_pfc1, sdr0_pfc2;
	43	u32 reg;
887e2ec9	44
d1c3b275 SR	45	mtdcr(EBC0_CFGADDR, EBC0_CFG);
d1c3b275 SR	46	mtdcr(EBC0_CFGDATA, 0xb8400000);
887e2ec9	47
83a49c8d	48	/*
887e2ec9	49	* Setup the interrupt controller polarities, triggers, etc.
83a49c8d	50	*/
952e7760 SR	51	mtdcr(UIC0SR, 0xffffffff); /* clear all */
	52	mtdcr(UIC0ER, 0x00000000); /* disable all */
	53	mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
	54	mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
	55	mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
	56	mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
	57	mtdcr(UIC0SR, 0xffffffff); /* clear all */
887e2ec9	58
952e7760 SR	59	mtdcr(UIC1SR, 0xffffffff); /* clear all */
	60	mtdcr(UIC1ER, 0x00000000); /* disable all */
	61	mtdcr(UIC1CR, 0x00000000); /* all non-critical */
	62	mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
	63	mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
	64	mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
	65	mtdcr(UIC1SR, 0xffffffff); /* clear all */
887e2ec9	66
952e7760 SR	67	mtdcr(UIC2SR, 0xffffffff); /* clear all */
	68	mtdcr(UIC2ER, 0x00000000); /* disable all */
	69	mtdcr(UIC2CR, 0x00000000); /* all non-critical */
	70	mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
	71	mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
	72	mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
	73	mtdcr(UIC2SR, 0xffffffff); /* clear all */
887e2ec9	74
23c51a2d SR	75	/* Check and reconfigure the PCI sync clock if necessary */
	76	ppc4xx_pci_sync_clock_config(get_async_pci_freq());
	77
887e2ec9	78	/* 50MHz tmrclk */
6d0f6bcf	79	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
887e2ec9 SR	80
887e2ec9 SR	81	/* clear write protects */
6d0f6bcf	82	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
887e2ec9 SR	83
887e2ec9 SR	84	/* enable Ethernet */
6d0f6bcf	85	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
887e2ec9 SR	86
887e2ec9 SR	87	/* enable USB device */
6d0f6bcf	88	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
887e2ec9	89
b738654d	90	/* select Ethernet (and optionally IIC1) pins */
887e2ec9	91	mfsdr(SDR0_PFC1, sdr0_pfc1);
83a49c8d MF	92	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) \|
83a49c8d MF	93	SDR0_PFC1_SELECT_CONFIG_4;
b738654d MN	94	#ifdef CONFIG_I2C_MULTI_BUS
	95	sdr0_pfc1 \|= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) \| SDR0_PFC1_SIS_IIC1_SEL);
	96	#endif
eab10073 SF	97	/* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
	98	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) \| SDR0_PFC1_U0IM_4PINS;
	99	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) \| SDR0_PFC1_U0ME_CTS_RTS;
	100	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) \| SDR0_PFC1_U1ME_CTS_RTS;
	101
887e2ec9	102	mfsdr(SDR0_PFC2, sdr0_pfc2);
83a49c8d MF	103	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) \|
83a49c8d MF	104	SDR0_PFC2_SELECT_CONFIG_4;
887e2ec9 SR	105	mtsdr(SDR0_PFC2, sdr0_pfc2);
	106	mtsdr(SDR0_PFC1, sdr0_pfc1);
	107
	108	/* PCI arbiter enabled */
d1c3b275 SR	109	mfsdr(SDR0_PCI0, reg);
d1c3b275 SR	110	mtsdr(SDR0_PCI0, 0x80000000 \| reg);
887e2ec9 SR	111
	112	/* setup NAND FLASH */
	113	mfsdr(SDR0_CUST0, sdr0_cust0);
511d0c72	114	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL \|
887e2ec9 SR	115	SDR0_CUST0_NDFC_ENABLE \|
	116	SDR0_CUST0_NDFC_BW_8_BIT \|
	117	SDR0_CUST0_NDFC_ARE_MASK \|
6d0f6bcf	118	(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
511d0c72	119	mtsdr(SDR0_CUST0, sdr0_cust0);
887e2ec9 SR	120
	121	return 0;
	122	}
	123
887e2ec9 SR	124	int misc_init_r(void)
887e2ec9 SR	125	{
d873133f	126	#if !defined(CONFIG_SYS_NO_FLASH)
887e2ec9 SR	127	uint pbcr;
887e2ec9 SR	128	int size_val = 0;
d873133f	129	#endif
854bc8da	130	#ifdef CONFIG_440EPX
887e2ec9 SR	131	unsigned long usb2d0cr = 0;
	132	unsigned long usb2phy0cr, usb2h0cr = 0;
	133	unsigned long sdr0_pfc1;
	134	char *act = getenv("usbact");
854bc8da	135	#endif
d873133f	136	u32 reg;
887e2ec9	137
d873133f	138	#if !defined(CONFIG_SYS_NO_FLASH)
83a49c8d	139	/* Re-do flash sizing to get full correct info */
1b3c360c SR	140
	141	/* adjust flash start and offset */
	142	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	143	gd->bd->bi_flashoffset = 0;
	144
345b77ba	145	#if defined(CONFIG_SYS_RAMBOOT)
d1c3b275	146	mtdcr(EBC0_CFGADDR, PB3CR);
887e2ec9	147	#else
d1c3b275	148	mtdcr(EBC0_CFGADDR, PB0CR);
887e2ec9	149	#endif
d1c3b275	150	pbcr = mfdcr(EBC0_CFGDATA);
865f0f97	151	size_val = ffs(gd->bd->bi_flashsize) - 21;
887e2ec9	152	pbcr = (pbcr & 0x0001ffff) \| gd->bd->bi_flashstart \| (size_val << 17);
345b77ba	153	#if defined(CONFIG_SYS_RAMBOOT)
d1c3b275	154	mtdcr(EBC0_CFGADDR, PB3CR);
887e2ec9	155	#else
d1c3b275	156	mtdcr(EBC0_CFGADDR, PB0CR);
887e2ec9	157	#endif
d1c3b275	158	mtdcr(EBC0_CFGDATA, pbcr);
887e2ec9	159
1b3c360c SR	160	/*
	161	* Re-check to get correct base address
	162	*/
	163	flash_get_size(gd->bd->bi_flashstart, 0);
887e2ec9	164
5a1aceb0	165	#ifdef CONFIG_ENV_IS_IN_FLASH
887e2ec9 SR	166	/* Monitor protection ON by default */
887e2ec9 SR	167	(void)flash_protect(FLAG_PROTECT_SET,
6d0f6bcf	168	-CONFIG_SYS_MONITOR_LEN,
887e2ec9 SR	169	0xffffffff,
	170	&flash_info[0]);
	171
	172	/* Env protection ON by default */
	173	(void)flash_protect(FLAG_PROTECT_SET,
0e8d1586 JCPV	174	CONFIG_ENV_ADDR_REDUND,
0e8d1586 JCPV	175	CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
887e2ec9 SR	176	&flash_info[0]);
887e2ec9 SR	177	#endif
d873133f	178	#endif /* CONFIG_SYS_NO_FLASH */
887e2ec9 SR	179
	180	/*
	181	* USB suff...
	182	*/
854bc8da	183	#ifdef CONFIG_440EPX
83a49c8d	184	if (act == NULL \|\| strcmp(act, "hostdev") == 0) {
887e2ec9	185	/* SDR Setting */
511d0c72	186	mfsdr(SDR0_PFC1, sdr0_pfc1);
f780b833	187	mfsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72 WD	188	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
511d0c72 WD	189	mfsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9 SR	190
887e2ec9 SR	191	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d	192	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
511d0c72	193	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
83a49c8d	194	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
887e2ec9	195	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d	196	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_DVBUS_PURDIS;
887e2ec9	197	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d	198	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_DWNSTR_HOST;
887e2ec9	199	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d	200	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_UTMICN_HOST;
887e2ec9	201
83a49c8d MF	202	/*
	203	* An 8-bit/60MHz interface is the only possible alternative
	204	* when connecting the Device to the PHY
	205	*/
511d0c72	206	usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
83a49c8d	207	usb2h0cr = usb2h0cr \| SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
887e2ec9	208
83a49c8d MF	209	/*
	210	* To enable the USB 2.0 Device function
	211	* through the UTMI interface
	212	*/
511d0c72	213	usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
83a49c8d	214	usb2d0cr = usb2d0cr \| SDR0_USB2D0CR_USB2DEV_SELECTION;
887e2ec9	215
511d0c72	216	sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
83a49c8d	217	sdr0_pfc1 = sdr0_pfc1 \| SDR0_PFC1_UES_USB2D_SEL;
887e2ec9	218
511d0c72	219	mtsdr(SDR0_PFC1, sdr0_pfc1);
f780b833	220	mtsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72 WD	221	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
511d0c72 WD	222	mtsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9 SR	223
	224	/clear resets/
	225	udelay (1000);
	226	mtsdr(SDR0_SRST1, 0x00000000);
	227	udelay (1000);
	228	mtsdr(SDR0_SRST0, 0x00000000);
	229
	230	printf("USB: Host(int phy) Device(ext phy)\n");
	231
	232	} else if (strcmp(act, "dev") == 0) {
	233	/-------------------PATCH-------------------------------/
	234	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
	235
	236	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d	237	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
887e2ec9	238	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d	239	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_DVBUS_PURDIS;
887e2ec9	240	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d	241	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_DWNSTR_HOST;
887e2ec9	242	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d	243	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_UTMICN_HOST;
887e2ec9 SR	244	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
	245
	246	udelay (1000);
	247	mtsdr(SDR0_SRST1, 0x672c6000);
	248
	249	udelay (1000);
	250	mtsdr(SDR0_SRST0, 0x00000080);
	251
	252	udelay (1000);
	253	mtsdr(SDR0_SRST1, 0x60206000);
	254
	255	(unsigned int )(0xe0000350) = 0x00000001;
	256
	257	udelay (1000);
	258	mtsdr(SDR0_SRST1, 0x60306000);
	259	/-------------------PATCH-------------------------------/
	260
	261	/* SDR Setting */
511d0c72	262	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
887e2ec9	263	mfsdr(SDR0_USB2H0CR, usb2h0cr);
f780b833	264	mfsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9 SR	265	mfsdr(SDR0_PFC1, sdr0_pfc1);
	266
	267	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d	268	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
511d0c72	269	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
83a49c8d	270	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
887e2ec9	271	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d	272	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_DVBUS_PUREN;
887e2ec9	273	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d	274	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_DWNSTR_DEV;
887e2ec9	275	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d	276	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_UTMICN_DEV;
887e2ec9 SR	277
887e2ec9 SR	278	usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
83a49c8d	279	usb2h0cr = usb2h0cr \| SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
887e2ec9 SR	280
887e2ec9 SR	281	usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
83a49c8d	282	usb2d0cr = usb2d0cr \| SDR0_USB2D0CR_EBC_SELECTION;
887e2ec9 SR	283
887e2ec9 SR	284	sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
83a49c8d	285	sdr0_pfc1 = sdr0_pfc1 \| SDR0_PFC1_UES_EBCHR_SEL;
887e2ec9	286
511d0c72 WD	287	mtsdr(SDR0_USB2H0CR, usb2h0cr);
511d0c72 WD	288	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
f780b833	289	mtsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9 SR	290	mtsdr(SDR0_PFC1, sdr0_pfc1);
887e2ec9 SR	291
83a49c8d	292	/* clear resets */
887e2ec9 SR	293	udelay (1000);
	294	mtsdr(SDR0_SRST1, 0x00000000);
	295	udelay (1000);
	296	mtsdr(SDR0_SRST0, 0x00000000);
	297
	298	printf("USB: Device(int phy)\n");
	299	}
854bc8da	300	#endif /* CONFIG_440EPX */
887e2ec9	301
8ce16f55 JO	302	mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
	303	reg &= ~(SDR0_SRST1_CRYP0 \| SDR0_SRST1_KASU0);
	304	mtsdr(SDR0_SRST1, reg);
	305
a78bc443 SR	306	/*
	307	* Clear PLB4A0_ACR[WRP]
	308	* This fix will make the MAL burst disabling patch for the Linux
	309	* EMAC driver obsolete.
	310	*/
5e7abce9 SR	311	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
5e7abce9 SR	312	mtdcr(PLB4A0_ACR, reg);
a78bc443	313
887e2ec9 SR	314	return 0;
	315	}
	316
	317	int checkboard(void)
	318	{
f0c0b3a9 WD	319	char buf[64];
f0c0b3a9 WD	320	int i = getenv_f("serial#", buf, sizeof(buf));
e0b9ea8c	321	u8 rev;
23c51a2d	322	u32 clock = get_async_pci_freq();
887e2ec9	323
854bc8da	324	#ifdef CONFIG_440EPX
887e2ec9	325	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
854bc8da SR	326	#else
	327	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
	328	#endif
e0b9ea8c	329
6d0f6bcf	330	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
23c51a2d	331	printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
e0b9ea8c	332
f0c0b3a9	333	if (i > 0) {
887e2ec9	334	puts(", serial# ");
f0c0b3a9	335	puts(buf);
887e2ec9 SR	336	}
	337	putc('\n');
	338
23c51a2d SR	339	/*
	340	* Reconfiguration of the PCI sync clock is already done,
	341	* now check again if everything is in range:
	342	*/
	343	if (ppc4xx_pci_sync_clock_config(clock)) {
	344	printf("ERROR: PCI clocking incorrect (async=%d "
	345	"sync=%ld)!\n", clock, get_PCI_freq());
	346	}
	347
887e2ec9 SR	348	return (0);
	349	}
	350
1f84021a MF	351	#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
	352	/*
	353	* Assign interrupts to PCI devices.
	354	*/
a760b020	355	void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
1f84021a	356	{
d1631fe1	357	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
1f84021a MF	358	}
	359	#endif
	360
345b77ba	361	#if defined(CONFIG_SYS_RAMBOOT)
5132106a SR	362	/*
	363	* On NAND-booting sequoia, we need to patch the chips select numbers
	364	* in the dtb (CS0 - NAND, CS3 - NOR)
	365	*/
	366	void ft_board_setup(void blob, bd_t bd)
	367	{
	368	int rc;
	369	int len;
	370	int nodeoffset;
	371	struct fdt_property *prop;
	372	u32 *reg;
	373	char path[32];
	374
	375	/* First do common fdt setup */
	376	__ft_board_setup(blob, bd);
	377
	378	/* And now configure NOR chip select to 3 instead of 0 */
	379	strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
	380	nodeoffset = fdt_path_offset(blob, path);
	381	prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
	382	if (prop == NULL) {
	383	printf("Unable to update NOR chip select for NAND booting\n");
	384	return;
	385	}
	386	reg = (u32 *)&prop->data[0];
	387	reg[0] = 3;
	388	rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
	389	if (rc) {
	390	printf("Unable to update property NOR mappings, err=%s\n",
	391	fdt_strerror(rc));
	392	return;
	393	}
	394
	395	/* And now configure NAND chip select to 0 instead of 3 */
	396	strcpy(path, "/plb/opb/ebc/ndfc@3,0");
	397	nodeoffset = fdt_path_offset(blob, path);
	398	prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
	399	if (prop == NULL) {
	400	printf("Unable to update NDFC chip select for NAND booting\n");
	401	return;
	402	}
	403	reg = (u32 *)&prop->data[0];
	404	reg[0] = 0;
	405	rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
	406	if (rc) {
	407	printf("Unable to update property NDFC mappings, err=%s\n",
	408	fdt_strerror(rc));
	409	return;
	410	}
	411	}
345b77ba	412	#endif /* CONFIG_SYS_RAMBOOT */