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1938f4a5 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2002-2006 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Marius Groeger <mgroeger@sysgo.de> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
11 | */ |
12 | ||
13 | #include <common.h> | |
14 | #include <linux/compiler.h> | |
15 | #include <version.h> | |
16 | #include <environment.h> | |
17 | #include <fdtdec.h> | |
f828bf25 | 18 | #include <fs.h> |
e4fef6cf SG |
19 | #if defined(CONFIG_CMD_IDE) |
20 | #include <ide.h> | |
21 | #endif | |
22 | #include <i2c.h> | |
1938f4a5 SG |
23 | #include <initcall.h> |
24 | #include <logbuff.h> | |
e4fef6cf SG |
25 | |
26 | /* TODO: Can we move these into arch/ headers? */ | |
27 | #ifdef CONFIG_8xx | |
28 | #include <mpc8xx.h> | |
29 | #endif | |
30 | #ifdef CONFIG_5xx | |
31 | #include <mpc5xx.h> | |
32 | #endif | |
33 | #ifdef CONFIG_MPC5xxx | |
34 | #include <mpc5xxx.h> | |
35 | #endif | |
36 | ||
a733b06b | 37 | #include <os.h> |
1938f4a5 | 38 | #include <post.h> |
e4fef6cf | 39 | #include <spi.h> |
c5d4001a | 40 | #include <status_led.h> |
71c52dba | 41 | #include <trace.h> |
e4fef6cf | 42 | #include <watchdog.h> |
a733b06b | 43 | #include <asm/errno.h> |
1938f4a5 | 44 | #include <asm/io.h> |
e4fef6cf SG |
45 | #ifdef CONFIG_MP |
46 | #include <asm/mp.h> | |
47 | #endif | |
1938f4a5 | 48 | #include <asm/sections.h> |
48a33806 SG |
49 | #ifdef CONFIG_X86 |
50 | #include <asm/init_helpers.h> | |
51 | #include <asm/relocate.h> | |
52 | #endif | |
a733b06b SG |
53 | #ifdef CONFIG_SANDBOX |
54 | #include <asm/state.h> | |
55 | #endif | |
1938f4a5 SG |
56 | #include <linux/compiler.h> |
57 | ||
58 | /* | |
59 | * Pointer to initial global data area | |
60 | * | |
61 | * Here we initialize it if needed. | |
62 | */ | |
63 | #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR | |
64 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
65 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
66 | DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); | |
67 | #else | |
68 | DECLARE_GLOBAL_DATA_PTR; | |
69 | #endif | |
70 | ||
71 | /* | |
72 | * sjg: IMO this code should be | |
73 | * refactored to a single function, something like: | |
74 | * | |
75 | * void led_set_state(enum led_colour_t colour, int on); | |
76 | */ | |
77 | /************************************************************************ | |
78 | * Coloured LED functionality | |
79 | ************************************************************************ | |
80 | * May be supplied by boards if desired | |
81 | */ | |
c5d4001a JH |
82 | __weak void coloured_LED_init(void) {} |
83 | __weak void red_led_on(void) {} | |
84 | __weak void red_led_off(void) {} | |
85 | __weak void green_led_on(void) {} | |
86 | __weak void green_led_off(void) {} | |
87 | __weak void yellow_led_on(void) {} | |
88 | __weak void yellow_led_off(void) {} | |
89 | __weak void blue_led_on(void) {} | |
90 | __weak void blue_led_off(void) {} | |
1938f4a5 SG |
91 | |
92 | /* | |
93 | * Why is gd allocated a register? Prior to reloc it might be better to | |
94 | * just pass it around to each function in this file? | |
95 | * | |
96 | * After reloc one could argue that it is hardly used and doesn't need | |
97 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
98 | * global data for all modules, so that post-reloc we can avoid the massive | |
99 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
100 | * a structure... | |
101 | */ | |
102 | ||
103 | /* | |
104 | * Could the CONFIG_SPL_BUILD infection become a flag in gd? | |
105 | */ | |
106 | ||
e4fef6cf SG |
107 | #if defined(CONFIG_WATCHDOG) |
108 | static int init_func_watchdog_init(void) | |
109 | { | |
110 | puts(" Watchdog enabled\n"); | |
111 | WATCHDOG_RESET(); | |
112 | ||
113 | return 0; | |
114 | } | |
115 | ||
116 | int init_func_watchdog_reset(void) | |
117 | { | |
118 | WATCHDOG_RESET(); | |
119 | ||
120 | return 0; | |
121 | } | |
122 | #endif /* CONFIG_WATCHDOG */ | |
123 | ||
124 | void __board_add_ram_info(int use_default) | |
125 | { | |
126 | /* please define platform specific board_add_ram_info() */ | |
127 | } | |
128 | ||
129 | void board_add_ram_info(int) | |
130 | __attribute__ ((weak, alias("__board_add_ram_info"))); | |
131 | ||
1938f4a5 SG |
132 | static int init_baud_rate(void) |
133 | { | |
134 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); | |
135 | return 0; | |
136 | } | |
137 | ||
138 | static int display_text_info(void) | |
139 | { | |
a733b06b | 140 | #ifndef CONFIG_SANDBOX |
1938f4a5 SG |
141 | ulong bss_start, bss_end; |
142 | ||
632efa74 SG |
143 | bss_start = (ulong)&__bss_start; |
144 | bss_end = (ulong)&__bss_end; | |
b60eff31 | 145 | |
1938f4a5 SG |
146 | debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n", |
147 | CONFIG_SYS_TEXT_BASE, bss_start, bss_end); | |
a733b06b | 148 | #endif |
1938f4a5 SG |
149 | |
150 | #ifdef CONFIG_MODEM_SUPPORT | |
151 | debug("Modem Support enabled\n"); | |
152 | #endif | |
153 | #ifdef CONFIG_USE_IRQ | |
154 | debug("IRQ Stack: %08lx\n", IRQ_STACK_START); | |
155 | debug("FIQ Stack: %08lx\n", FIQ_STACK_START); | |
156 | #endif | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
161 | static int announce_dram_init(void) | |
162 | { | |
163 | puts("DRAM: "); | |
164 | return 0; | |
165 | } | |
166 | ||
3da7e5a5 | 167 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) |
e4fef6cf SG |
168 | static int init_func_ram(void) |
169 | { | |
170 | #ifdef CONFIG_BOARD_TYPES | |
171 | int board_type = gd->board_type; | |
172 | #else | |
173 | int board_type = 0; /* use dummy arg */ | |
174 | #endif | |
175 | ||
176 | gd->ram_size = initdram(board_type); | |
177 | ||
178 | if (gd->ram_size > 0) | |
179 | return 0; | |
180 | ||
181 | puts("*** failed ***\n"); | |
182 | return 1; | |
183 | } | |
184 | #endif | |
185 | ||
1938f4a5 SG |
186 | static int show_dram_config(void) |
187 | { | |
fa39ffe5 | 188 | unsigned long long size; |
1938f4a5 SG |
189 | |
190 | #ifdef CONFIG_NR_DRAM_BANKS | |
191 | int i; | |
192 | ||
193 | debug("\nRAM Configuration:\n"); | |
194 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
195 | size += gd->bd->bi_dram[i].size; | |
196 | debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); | |
197 | #ifdef DEBUG | |
198 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
199 | #endif | |
200 | } | |
201 | debug("\nDRAM: "); | |
202 | #else | |
203 | size = gd->ram_size; | |
204 | #endif | |
205 | ||
e4fef6cf SG |
206 | print_size(size, ""); |
207 | board_add_ram_info(0); | |
208 | putc('\n'); | |
1938f4a5 SG |
209 | |
210 | return 0; | |
211 | } | |
212 | ||
213 | void __dram_init_banksize(void) | |
214 | { | |
215 | #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) | |
216 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
217 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
218 | #endif | |
219 | } | |
220 | ||
221 | void dram_init_banksize(void) | |
222 | __attribute__((weak, alias("__dram_init_banksize"))); | |
223 | ||
ea818dbb | 224 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
225 | static int init_func_i2c(void) |
226 | { | |
227 | puts("I2C: "); | |
815a76f2 | 228 | #ifdef CONFIG_SYS_I2C |
229 | i2c_init_all(); | |
230 | #else | |
e4fef6cf | 231 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
815a76f2 | 232 | #endif |
e4fef6cf SG |
233 | puts("ready\n"); |
234 | return 0; | |
235 | } | |
236 | #endif | |
237 | ||
238 | #if defined(CONFIG_HARD_SPI) | |
239 | static int init_func_spi(void) | |
240 | { | |
241 | puts("SPI: "); | |
242 | spi_init(); | |
243 | puts("ready\n"); | |
244 | return 0; | |
245 | } | |
246 | #endif | |
247 | ||
248 | __maybe_unused | |
1938f4a5 SG |
249 | static int zero_global_data(void) |
250 | { | |
251 | memset((void *)gd, '\0', sizeof(gd_t)); | |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
256 | static int setup_mon_len(void) | |
257 | { | |
b60eff31 AA |
258 | #ifdef __ARM__ |
259 | gd->mon_len = (ulong)&__bss_end - (ulong)_start; | |
a733b06b SG |
260 | #elif defined(CONFIG_SANDBOX) |
261 | gd->mon_len = (ulong)&_end - (ulong)_init; | |
632efa74 | 262 | #else |
e4fef6cf SG |
263 | /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ |
264 | gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 265 | #endif |
1938f4a5 SG |
266 | return 0; |
267 | } | |
268 | ||
269 | __weak int arch_cpu_init(void) | |
270 | { | |
271 | return 0; | |
272 | } | |
273 | ||
f828bf25 SG |
274 | #ifdef CONFIG_OF_HOSTFILE |
275 | ||
f828bf25 SG |
276 | static int read_fdt_from_file(void) |
277 | { | |
278 | struct sandbox_state *state = state_get_current(); | |
95fac6ab | 279 | const char *fname = state->fdt_fname; |
f828bf25 | 280 | void *blob; |
95fac6ab | 281 | ssize_t size; |
f828bf25 | 282 | int err; |
95fac6ab | 283 | int fd; |
f828bf25 SG |
284 | |
285 | blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0); | |
286 | if (!state->fdt_fname) { | |
95fac6ab | 287 | err = fdt_create_empty_tree(blob, 256); |
f828bf25 SG |
288 | if (!err) |
289 | goto done; | |
95fac6ab SG |
290 | printf("Unable to create empty FDT: %s\n", fdt_strerror(err)); |
291 | return -EINVAL; | |
292 | } | |
293 | ||
294 | size = os_get_filesize(fname); | |
295 | if (size < 0) { | |
296 | printf("Failed to file FDT file '%s'\n", fname); | |
297 | return -ENOENT; | |
298 | } | |
299 | fd = os_open(fname, OS_O_RDONLY); | |
300 | if (fd < 0) { | |
301 | printf("Failed to open FDT file '%s'\n", fname); | |
302 | return -EACCES; | |
f828bf25 | 303 | } |
95fac6ab SG |
304 | if (os_read(fd, blob, size) != size) { |
305 | os_close(fd); | |
f828bf25 | 306 | return -EIO; |
95fac6ab SG |
307 | } |
308 | os_close(fd); | |
f828bf25 SG |
309 | |
310 | done: | |
311 | gd->fdt_blob = blob; | |
312 | ||
313 | return 0; | |
314 | } | |
315 | #endif | |
316 | ||
a733b06b SG |
317 | #ifdef CONFIG_SANDBOX |
318 | static int setup_ram_buf(void) | |
319 | { | |
5c2859cd SG |
320 | struct sandbox_state *state = state_get_current(); |
321 | ||
322 | gd->arch.ram_buf = state->ram_buf; | |
323 | gd->ram_size = state->ram_size; | |
a733b06b SG |
324 | |
325 | return 0; | |
326 | } | |
327 | #endif | |
328 | ||
1938f4a5 SG |
329 | static int setup_fdt(void) |
330 | { | |
331 | #ifdef CONFIG_OF_EMBED | |
332 | /* Get a pointer to the FDT */ | |
6ab6b2af | 333 | gd->fdt_blob = __dtb_dt_begin; |
1938f4a5 SG |
334 | #elif defined CONFIG_OF_SEPARATE |
335 | /* FDT is at end of image */ | |
632efa74 | 336 | gd->fdt_blob = (ulong *)&_end; |
f828bf25 SG |
337 | #elif defined(CONFIG_OF_HOSTFILE) |
338 | if (read_fdt_from_file()) { | |
339 | puts("Failed to read control FDT\n"); | |
340 | return -1; | |
341 | } | |
1938f4a5 SG |
342 | #endif |
343 | /* Allow the early environment to override the fdt address */ | |
344 | gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, | |
345 | (uintptr_t)gd->fdt_blob); | |
346 | return 0; | |
347 | } | |
348 | ||
349 | /* Get the top of usable RAM */ | |
350 | __weak ulong board_get_usable_ram_top(ulong total_size) | |
351 | { | |
352 | return gd->ram_top; | |
353 | } | |
354 | ||
355 | static int setup_dest_addr(void) | |
356 | { | |
357 | debug("Monitor len: %08lX\n", gd->mon_len); | |
358 | /* | |
359 | * Ram is setup, size stored in gd !! | |
360 | */ | |
361 | debug("Ram size: %08lX\n", (ulong)gd->ram_size); | |
362 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) | |
363 | /* | |
364 | * Subtract specified amount of memory to hide so that it won't | |
365 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
366 | * the Linux kernel should now get passed the now "corrected" | |
367 | * memory size and won't touch it either. This should work | |
368 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
369 | * arch/powerpc with bootwrapper support, that recalculate the | |
370 | * memory size from the SDRAM controller setup will have to | |
371 | * get fixed. | |
372 | */ | |
373 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; | |
374 | #endif | |
375 | #ifdef CONFIG_SYS_SDRAM_BASE | |
376 | gd->ram_top = CONFIG_SYS_SDRAM_BASE; | |
377 | #endif | |
e4fef6cf | 378 | gd->ram_top += get_effective_memsize(); |
1938f4a5 | 379 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 380 | gd->relocaddr = gd->ram_top; |
1938f4a5 | 381 | debug("Ram top: %08lX\n", (ulong)gd->ram_top); |
e4fef6cf SG |
382 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
383 | /* | |
384 | * We need to make sure the location we intend to put secondary core | |
385 | * boot code is reserved and not used by any part of u-boot | |
386 | */ | |
a0ba279a MY |
387 | if (gd->relocaddr > determine_mp_bootpg(NULL)) { |
388 | gd->relocaddr = determine_mp_bootpg(NULL); | |
389 | debug("Reserving MP boot page to %08lx\n", gd->relocaddr); | |
e4fef6cf SG |
390 | } |
391 | #endif | |
1938f4a5 SG |
392 | return 0; |
393 | } | |
394 | ||
395 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) | |
396 | static int reserve_logbuffer(void) | |
397 | { | |
398 | /* reserve kernel log buffer */ | |
a0ba279a | 399 | gd->relocaddr -= LOGBUFF_RESERVE; |
1938f4a5 | 400 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
a0ba279a | 401 | gd->relocaddr); |
1938f4a5 SG |
402 | return 0; |
403 | } | |
404 | #endif | |
405 | ||
406 | #ifdef CONFIG_PRAM | |
407 | /* reserve protected RAM */ | |
408 | static int reserve_pram(void) | |
409 | { | |
410 | ulong reg; | |
411 | ||
412 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); | |
a0ba279a | 413 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 414 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 415 | gd->relocaddr); |
1938f4a5 SG |
416 | return 0; |
417 | } | |
418 | #endif /* CONFIG_PRAM */ | |
419 | ||
420 | /* Round memory pointer down to next 4 kB limit */ | |
421 | static int reserve_round_4k(void) | |
422 | { | |
a0ba279a | 423 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
424 | return 0; |
425 | } | |
426 | ||
427 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
428 | defined(CONFIG_ARM) | |
429 | static int reserve_mmu(void) | |
430 | { | |
431 | /* reserve TLB table */ | |
cce6be7f | 432 | gd->arch.tlb_size = PGTABLE_SIZE; |
a0ba279a | 433 | gd->relocaddr -= gd->arch.tlb_size; |
1938f4a5 SG |
434 | |
435 | /* round down to next 64 kB limit */ | |
a0ba279a | 436 | gd->relocaddr &= ~(0x10000 - 1); |
1938f4a5 | 437 | |
a0ba279a | 438 | gd->arch.tlb_addr = gd->relocaddr; |
1938f4a5 SG |
439 | debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, |
440 | gd->arch.tlb_addr + gd->arch.tlb_size); | |
441 | return 0; | |
442 | } | |
443 | #endif | |
444 | ||
445 | #ifdef CONFIG_LCD | |
446 | static int reserve_lcd(void) | |
447 | { | |
448 | #ifdef CONFIG_FB_ADDR | |
449 | gd->fb_base = CONFIG_FB_ADDR; | |
450 | #else | |
451 | /* reserve memory for LCD display (always full pages) */ | |
a0ba279a MY |
452 | gd->relocaddr = lcd_setmem(gd->relocaddr); |
453 | gd->fb_base = gd->relocaddr; | |
1938f4a5 SG |
454 | #endif /* CONFIG_FB_ADDR */ |
455 | return 0; | |
456 | } | |
457 | #endif /* CONFIG_LCD */ | |
458 | ||
71c52dba SG |
459 | static int reserve_trace(void) |
460 | { | |
461 | #ifdef CONFIG_TRACE | |
462 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
463 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
464 | debug("Reserving %dk for trace data at: %08lx\n", | |
465 | CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
466 | #endif | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
e4fef6cf | 471 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \ |
48a33806 | 472 | && !defined(CONFIG_ARM) && !defined(CONFIG_X86) |
e4fef6cf SG |
473 | static int reserve_video(void) |
474 | { | |
475 | /* reserve memory for video display (always full pages) */ | |
a0ba279a MY |
476 | gd->relocaddr = video_setmem(gd->relocaddr); |
477 | gd->fb_base = gd->relocaddr; | |
e4fef6cf SG |
478 | |
479 | return 0; | |
480 | } | |
481 | #endif | |
482 | ||
1938f4a5 SG |
483 | static int reserve_uboot(void) |
484 | { | |
485 | /* | |
486 | * reserve memory for U-Boot code, data & bss | |
487 | * round down to next 4 kB limit | |
488 | */ | |
a0ba279a MY |
489 | gd->relocaddr -= gd->mon_len; |
490 | gd->relocaddr &= ~(4096 - 1); | |
e4fef6cf SG |
491 | #ifdef CONFIG_E500 |
492 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
a0ba279a | 493 | gd->relocaddr &= ~(65536 - 1); |
e4fef6cf | 494 | #endif |
1938f4a5 SG |
495 | |
496 | debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, | |
a0ba279a MY |
497 | gd->relocaddr); |
498 | ||
499 | gd->start_addr_sp = gd->relocaddr; | |
500 | ||
1938f4a5 SG |
501 | return 0; |
502 | } | |
503 | ||
8cae8a68 | 504 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
505 | /* reserve memory for malloc() area */ |
506 | static int reserve_malloc(void) | |
507 | { | |
a0ba279a | 508 | gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; |
1938f4a5 | 509 | debug("Reserving %dk for malloc() at: %08lx\n", |
a0ba279a | 510 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
1938f4a5 SG |
511 | return 0; |
512 | } | |
513 | ||
514 | /* (permanently) allocate a Board Info struct */ | |
515 | static int reserve_board(void) | |
516 | { | |
a0ba279a MY |
517 | gd->start_addr_sp -= sizeof(bd_t); |
518 | gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); | |
1938f4a5 SG |
519 | memset(gd->bd, '\0', sizeof(bd_t)); |
520 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", | |
a0ba279a | 521 | sizeof(bd_t), gd->start_addr_sp); |
1938f4a5 SG |
522 | return 0; |
523 | } | |
8cae8a68 | 524 | #endif |
1938f4a5 SG |
525 | |
526 | static int setup_machine(void) | |
527 | { | |
528 | #ifdef CONFIG_MACH_TYPE | |
529 | gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ | |
530 | #endif | |
531 | return 0; | |
532 | } | |
533 | ||
534 | static int reserve_global_data(void) | |
535 | { | |
a0ba279a MY |
536 | gd->start_addr_sp -= sizeof(gd_t); |
537 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); | |
1938f4a5 | 538 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
a0ba279a | 539 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
540 | return 0; |
541 | } | |
542 | ||
543 | static int reserve_fdt(void) | |
544 | { | |
545 | /* | |
546 | * If the device tree is sitting immediate above our image then we | |
547 | * must relocate it. If it is embedded in the data section, then it | |
548 | * will be relocated with other data. | |
549 | */ | |
550 | if (gd->fdt_blob) { | |
551 | gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); | |
552 | ||
a0ba279a MY |
553 | gd->start_addr_sp -= gd->fdt_size; |
554 | gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); | |
a733b06b | 555 | debug("Reserving %lu Bytes for FDT at: %08lx\n", |
a0ba279a | 556 | gd->fdt_size, gd->start_addr_sp); |
1938f4a5 SG |
557 | } |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
562 | static int reserve_stacks(void) | |
563 | { | |
8cae8a68 SG |
564 | #ifdef CONFIG_SPL_BUILD |
565 | # ifdef CONFIG_ARM | |
a0ba279a MY |
566 | gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */ |
567 | gd->irq_sp = gd->start_addr_sp; | |
8cae8a68 SG |
568 | # endif |
569 | #else | |
e4fef6cf SG |
570 | # ifdef CONFIG_PPC |
571 | ulong *s; | |
572 | # endif | |
8cae8a68 | 573 | |
1938f4a5 | 574 | /* setup stack pointer for exceptions */ |
a0ba279a MY |
575 | gd->start_addr_sp -= 16; |
576 | gd->start_addr_sp &= ~0xf; | |
577 | gd->irq_sp = gd->start_addr_sp; | |
1938f4a5 SG |
578 | |
579 | /* | |
580 | * Handle architecture-specific things here | |
581 | * TODO(sjg@chromium.org): Perhaps create arch_reserve_stack() | |
582 | * to handle this and put in arch/xxx/lib/stack.c | |
583 | */ | |
cce6be7f | 584 | # if defined(CONFIG_ARM) && !defined(CONFIG_ARM64) |
1938f4a5 | 585 | # ifdef CONFIG_USE_IRQ |
a0ba279a | 586 | gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ); |
1938f4a5 | 587 | debug("Reserving %zu Bytes for IRQ stack at: %08lx\n", |
a0ba279a | 588 | CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp); |
1938f4a5 SG |
589 | |
590 | /* 8-byte alignment for ARM ABI compliance */ | |
a0ba279a | 591 | gd->start_addr_sp &= ~0x07; |
1938f4a5 SG |
592 | # endif |
593 | /* leave 3 words for abort-stack, plus 1 for alignment */ | |
a0ba279a | 594 | gd->start_addr_sp -= 16; |
e4fef6cf SG |
595 | # elif defined(CONFIG_PPC) |
596 | /* Clear initial stack frame */ | |
a0ba279a | 597 | s = (ulong *) gd->start_addr_sp; |
e4fef6cf SG |
598 | *s = 0; /* Terminate back chain */ |
599 | *++s = 0; /* NULL return address */ | |
8cae8a68 | 600 | # endif /* Architecture specific code */ |
1938f4a5 SG |
601 | |
602 | return 0; | |
8cae8a68 | 603 | #endif |
1938f4a5 SG |
604 | } |
605 | ||
606 | static int display_new_sp(void) | |
607 | { | |
a0ba279a | 608 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
609 | |
610 | return 0; | |
611 | } | |
612 | ||
e4fef6cf SG |
613 | #ifdef CONFIG_PPC |
614 | static int setup_board_part1(void) | |
615 | { | |
616 | bd_t *bd = gd->bd; | |
617 | ||
618 | /* | |
619 | * Save local variables to board info struct | |
620 | */ | |
621 | ||
622 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ | |
623 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
624 | ||
625 | #ifdef CONFIG_SYS_SRAM_BASE | |
626 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
627 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
628 | #endif | |
629 | ||
58dac327 | 630 | #if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ |
e4fef6cf SG |
631 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
632 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ | |
633 | #endif | |
634 | #if defined(CONFIG_MPC5xxx) | |
635 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ | |
636 | #endif | |
637 | #if defined(CONFIG_MPC83xx) | |
638 | bd->bi_immrbar = CONFIG_SYS_IMMR; | |
639 | #endif | |
e4fef6cf SG |
640 | |
641 | return 0; | |
642 | } | |
643 | ||
644 | static int setup_board_part2(void) | |
645 | { | |
646 | bd_t *bd = gd->bd; | |
647 | ||
648 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ | |
649 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
650 | #if defined(CONFIG_CPM2) | |
651 | bd->bi_cpmfreq = gd->arch.cpm_clk; | |
652 | bd->bi_brgfreq = gd->arch.brg_clk; | |
653 | bd->bi_sccfreq = gd->arch.scc_clk; | |
654 | bd->bi_vco = gd->arch.vco_out; | |
655 | #endif /* CONFIG_CPM2 */ | |
656 | #if defined(CONFIG_MPC512X) | |
657 | bd->bi_ipsfreq = gd->arch.ips_clk; | |
658 | #endif /* CONFIG_MPC512X */ | |
659 | #if defined(CONFIG_MPC5xxx) | |
660 | bd->bi_ipbfreq = gd->arch.ipb_clk; | |
661 | bd->bi_pcifreq = gd->pci_clk; | |
662 | #endif /* CONFIG_MPC5xxx */ | |
663 | ||
664 | return 0; | |
665 | } | |
666 | #endif | |
667 | ||
668 | #ifdef CONFIG_SYS_EXTBDINFO | |
669 | static int setup_board_extra(void) | |
670 | { | |
671 | bd_t *bd = gd->bd; | |
672 | ||
673 | strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); | |
674 | strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, | |
675 | sizeof(bd->bi_r_version)); | |
676 | ||
677 | bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ | |
678 | bd->bi_plb_busfreq = gd->bus_clk; | |
679 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ | |
680 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
681 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
682 | bd->bi_pci_busfreq = get_PCI_freq(); | |
683 | bd->bi_opbfreq = get_OPB_freq(); | |
684 | #elif defined(CONFIG_XILINX_405) | |
685 | bd->bi_pci_busfreq = get_PCI_freq(); | |
686 | #endif | |
687 | ||
688 | return 0; | |
689 | } | |
690 | #endif | |
691 | ||
1938f4a5 SG |
692 | #ifdef CONFIG_POST |
693 | static int init_post(void) | |
694 | { | |
695 | post_bootmode_init(); | |
696 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
697 | ||
698 | return 0; | |
699 | } | |
700 | #endif | |
701 | ||
1938f4a5 SG |
702 | static int setup_dram_config(void) |
703 | { | |
704 | /* Ram is board specific, so move it to board code ... */ | |
705 | dram_init_banksize(); | |
706 | ||
707 | return 0; | |
708 | } | |
709 | ||
710 | static int reloc_fdt(void) | |
711 | { | |
712 | if (gd->new_fdt) { | |
713 | memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); | |
714 | gd->fdt_blob = gd->new_fdt; | |
715 | } | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
720 | static int setup_reloc(void) | |
721 | { | |
a0ba279a | 722 | gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; |
1938f4a5 SG |
723 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
724 | ||
725 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); | |
a733b06b | 726 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", |
a0ba279a MY |
727 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), |
728 | gd->start_addr_sp); | |
1938f4a5 SG |
729 | |
730 | return 0; | |
731 | } | |
732 | ||
733 | /* ARM calls relocate_code from its crt0.S */ | |
808434cd | 734 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
735 | |
736 | static int jump_to_copy(void) | |
737 | { | |
48a33806 SG |
738 | /* |
739 | * x86 is special, but in a nice way. It uses a trampoline which | |
740 | * enables the dcache if possible. | |
741 | * | |
742 | * For now, other archs use relocate_code(), which is implemented | |
743 | * similarly for all archs. When we do generic relocation, hopefully | |
744 | * we can make all archs enable the dcache prior to relocation. | |
745 | */ | |
746 | #ifdef CONFIG_X86 | |
747 | /* | |
748 | * SDRAM and console are now initialised. The final stack can now | |
749 | * be setup in SDRAM. Code execution will continue in Flash, but | |
750 | * with the stack in SDRAM and Global Data in temporary memory | |
751 | * (CPU cache) | |
752 | */ | |
753 | board_init_f_r_trampoline(gd->start_addr_sp); | |
754 | #else | |
a0ba279a | 755 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 756 | #endif |
1938f4a5 SG |
757 | |
758 | return 0; | |
759 | } | |
760 | #endif | |
761 | ||
762 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
763 | static int mark_bootstage(void) | |
764 | { | |
765 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
d59476b6 SG |
770 | static int initf_malloc(void) |
771 | { | |
772 | #ifdef CONFIG_SYS_MALLOC_F_LEN | |
773 | assert(gd->malloc_base); /* Set up by crt0.S */ | |
774 | gd->malloc_limit = gd->malloc_base + CONFIG_SYS_MALLOC_F_LEN; | |
775 | gd->malloc_ptr = 0; | |
776 | #endif | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
1938f4a5 | 781 | static init_fnc_t init_sequence_f[] = { |
a733b06b SG |
782 | #ifdef CONFIG_SANDBOX |
783 | setup_ram_buf, | |
e4fef6cf | 784 | #endif |
1938f4a5 | 785 | setup_mon_len, |
71c52dba SG |
786 | setup_fdt, |
787 | trace_early_init, | |
e4fef6cf SG |
788 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
789 | /* TODO: can this go into arch_cpu_init()? */ | |
790 | probecpu, | |
791 | #endif | |
1938f4a5 | 792 | arch_cpu_init, /* basic arch cpu dependent setup */ |
48a33806 SG |
793 | #ifdef CONFIG_X86 |
794 | cpu_init_f, /* TODO(sjg@chromium.org): remove */ | |
795 | # ifdef CONFIG_OF_CONTROL | |
796 | find_fdt, /* TODO(sjg@chromium.org): remove */ | |
797 | # endif | |
798 | #endif | |
1938f4a5 SG |
799 | mark_bootstage, |
800 | #ifdef CONFIG_OF_CONTROL | |
801 | fdtdec_check_fdt, | |
802 | #endif | |
803 | #if defined(CONFIG_BOARD_EARLY_INIT_F) | |
804 | board_early_init_f, | |
805 | #endif | |
e4fef6cf SG |
806 | /* TODO: can any of this go into arch_cpu_init()? */ |
807 | #if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT) | |
808 | get_clocks, /* get CPU and bus clocks (etc.) */ | |
809 | #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ | |
810 | && !defined(CONFIG_TQM885D) | |
811 | adjust_sdram_tbs_8xx, | |
812 | #endif | |
813 | /* TODO: can we rename this to timer_init()? */ | |
814 | init_timebase, | |
815 | #endif | |
6dc9bace | 816 | #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) |
1938f4a5 | 817 | timer_init, /* initialize timer */ |
e4fef6cf | 818 | #endif |
e4fef6cf SG |
819 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
820 | #if !defined(CONFIG_CPM2) | |
821 | dpram_init, | |
822 | #endif | |
823 | #endif | |
824 | #if defined(CONFIG_BOARD_POSTCLK_INIT) | |
825 | board_postclk_init, | |
b8521b74 MY |
826 | #endif |
827 | #ifdef CONFIG_FSL_ESDHC | |
828 | get_clocks, | |
1938f4a5 SG |
829 | #endif |
830 | env_init, /* initialize environment */ | |
e4fef6cf SG |
831 | #if defined(CONFIG_8xx_CPUCLK_DEFAULT) |
832 | /* get CPU and bus clocks according to the environment variable */ | |
833 | get_clocks_866, | |
834 | /* adjust sdram refresh rate according to the new clock */ | |
835 | sdram_adjust_866, | |
836 | init_timebase, | |
837 | #endif | |
d59476b6 | 838 | initf_malloc, |
1938f4a5 SG |
839 | init_baud_rate, /* initialze baudrate settings */ |
840 | serial_init, /* serial communications setup */ | |
841 | console_init_f, /* stage 1 init of console */ | |
a733b06b SG |
842 | #ifdef CONFIG_SANDBOX |
843 | sandbox_early_getopt_check, | |
844 | #endif | |
845 | #ifdef CONFIG_OF_CONTROL | |
846 | fdtdec_prepare_fdt, | |
48a33806 | 847 | #endif |
1938f4a5 SG |
848 | display_options, /* say that we are here */ |
849 | display_text_info, /* show debugging info if required */ | |
58dac327 | 850 | #if defined(CONFIG_MPC8260) |
e4fef6cf SG |
851 | prt_8260_rsr, |
852 | prt_8260_clks, | |
58dac327 | 853 | #endif /* CONFIG_MPC8260 */ |
e4fef6cf SG |
854 | #if defined(CONFIG_MPC83xx) |
855 | prt_83xx_rsr, | |
856 | #endif | |
857 | #ifdef CONFIG_PPC | |
858 | checkcpu, | |
859 | #endif | |
1938f4a5 | 860 | print_cpuinfo, /* display cpu info (and speed) */ |
e4fef6cf SG |
861 | #if defined(CONFIG_MPC5xxx) |
862 | prt_mpc5xxx_clks, | |
863 | #endif /* CONFIG_MPC5xxx */ | |
1938f4a5 SG |
864 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
865 | checkboard, /* display board info */ | |
e4fef6cf SG |
866 | #endif |
867 | INIT_FUNC_WATCHDOG_INIT | |
868 | #if defined(CONFIG_MISC_INIT_F) | |
869 | misc_init_f, | |
870 | #endif | |
871 | INIT_FUNC_WATCHDOG_RESET | |
ea818dbb | 872 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
873 | init_func_i2c, |
874 | #endif | |
875 | #if defined(CONFIG_HARD_SPI) | |
876 | init_func_spi, | |
877 | #endif | |
878 | #ifdef CONFIG_X86 | |
879 | dram_init_f, /* configure available RAM banks */ | |
8b42dfc3 | 880 | calculate_relocation_address, |
1938f4a5 SG |
881 | #endif |
882 | announce_dram_init, | |
883 | /* TODO: unify all these dram functions? */ | |
884 | #ifdef CONFIG_ARM | |
885 | dram_init, /* configure available RAM banks */ | |
886 | #endif | |
3da7e5a5 | 887 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) |
e4fef6cf SG |
888 | init_func_ram, |
889 | #endif | |
890 | #ifdef CONFIG_POST | |
891 | post_init_f, | |
892 | #endif | |
893 | INIT_FUNC_WATCHDOG_RESET | |
894 | #if defined(CONFIG_SYS_DRAM_TEST) | |
895 | testdram, | |
896 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
897 | INIT_FUNC_WATCHDOG_RESET | |
898 | ||
1938f4a5 SG |
899 | #ifdef CONFIG_POST |
900 | init_post, | |
901 | #endif | |
e4fef6cf | 902 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
903 | /* |
904 | * Now that we have DRAM mapped and working, we can | |
905 | * relocate the code and continue running from DRAM. | |
906 | * | |
907 | * Reserve memory at end of RAM for (top down in that order): | |
908 | * - area that won't get touched by U-Boot and Linux (optional) | |
909 | * - kernel log buffer | |
910 | * - protected RAM | |
911 | * - LCD framebuffer | |
912 | * - monitor code | |
913 | * - board info struct | |
914 | */ | |
915 | setup_dest_addr, | |
916 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) | |
917 | reserve_logbuffer, | |
918 | #endif | |
919 | #ifdef CONFIG_PRAM | |
920 | reserve_pram, | |
921 | #endif | |
922 | reserve_round_4k, | |
923 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
924 | defined(CONFIG_ARM) | |
925 | reserve_mmu, | |
926 | #endif | |
927 | #ifdef CONFIG_LCD | |
928 | reserve_lcd, | |
e4fef6cf | 929 | #endif |
71c52dba | 930 | reserve_trace, |
e4fef6cf SG |
931 | /* TODO: Why the dependency on CONFIG_8xx? */ |
932 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \ | |
48a33806 | 933 | && !defined(CONFIG_ARM) && !defined(CONFIG_X86) |
e4fef6cf | 934 | reserve_video, |
1938f4a5 SG |
935 | #endif |
936 | reserve_uboot, | |
8cae8a68 | 937 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
938 | reserve_malloc, |
939 | reserve_board, | |
8cae8a68 | 940 | #endif |
1938f4a5 SG |
941 | setup_machine, |
942 | reserve_global_data, | |
943 | reserve_fdt, | |
944 | reserve_stacks, | |
945 | setup_dram_config, | |
946 | show_dram_config, | |
e4fef6cf SG |
947 | #ifdef CONFIG_PPC |
948 | setup_board_part1, | |
949 | INIT_FUNC_WATCHDOG_RESET | |
950 | setup_board_part2, | |
951 | #endif | |
1938f4a5 | 952 | display_new_sp, |
e4fef6cf SG |
953 | #ifdef CONFIG_SYS_EXTBDINFO |
954 | setup_board_extra, | |
955 | #endif | |
956 | INIT_FUNC_WATCHDOG_RESET | |
1938f4a5 SG |
957 | reloc_fdt, |
958 | setup_reloc, | |
808434cd | 959 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
960 | jump_to_copy, |
961 | #endif | |
962 | NULL, | |
963 | }; | |
964 | ||
965 | void board_init_f(ulong boot_flags) | |
966 | { | |
2a1680e3 YS |
967 | #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA |
968 | /* | |
969 | * For some archtectures, global data is initialized and used before | |
970 | * calling this function. The data should be preserved. For others, | |
971 | * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack | |
972 | * here to host global data until relocation. | |
973 | */ | |
1938f4a5 SG |
974 | gd_t data; |
975 | ||
976 | gd = &data; | |
977 | ||
cce6be7f DF |
978 | /* |
979 | * Clear global data before it is accessed at debug print | |
980 | * in initcall_run_list. Otherwise the debug print probably | |
981 | * get the wrong vaule of gd->have_console. | |
982 | */ | |
cce6be7f DF |
983 | zero_global_data(); |
984 | #endif | |
985 | ||
1938f4a5 | 986 | gd->flags = boot_flags; |
9aed5a27 | 987 | gd->have_console = 0; |
1938f4a5 SG |
988 | |
989 | if (initcall_run_list(init_sequence_f)) | |
990 | hang(); | |
991 | ||
808434cd | 992 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
993 | /* NOTREACHED - jump_to_copy() does not return */ |
994 | hang(); | |
995 | #endif | |
996 | } | |
997 | ||
48a33806 SG |
998 | #ifdef CONFIG_X86 |
999 | /* | |
1000 | * For now this code is only used on x86. | |
1001 | * | |
1002 | * init_sequence_f_r is the list of init functions which are run when | |
1003 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
1004 | * The following limitations must be considered when implementing an | |
1005 | * '_f_r' function: | |
1006 | * - 'static' variables are read-only | |
1007 | * - Global Data (gd->xxx) is read/write | |
1008 | * | |
1009 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
1010 | * supported). It _should_, if possible, copy global data to RAM and | |
1011 | * initialise the CPU caches (to speed up the relocation process) | |
1012 | * | |
1013 | * NOTE: At present only x86 uses this route, but it is intended that | |
1014 | * all archs will move to this when generic relocation is implemented. | |
1015 | */ | |
1016 | static init_fnc_t init_sequence_f_r[] = { | |
1017 | init_cache_f_r, | |
1018 | copy_uboot_to_ram, | |
1019 | clear_bss, | |
1020 | do_elf_reloc_fixups, | |
1021 | ||
1022 | NULL, | |
1023 | }; | |
1024 | ||
1025 | void board_init_f_r(void) | |
1026 | { | |
1027 | if (initcall_run_list(init_sequence_f_r)) | |
1028 | hang(); | |
1029 | ||
1030 | /* | |
1031 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
1032 | * Transfer execution from Flash to RAM by calculating the address | |
1033 | * of the in-RAM copy of board_init_r() and calling it | |
1034 | */ | |
1035 | (board_init_r + gd->reloc_off)(gd, gd->relocaddr); | |
1036 | ||
1037 | /* NOTREACHED - board_init_r() does not return */ | |
1038 | hang(); | |
1039 | } | |
1040 | #endif /* CONFIG_X86 */ |