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1938f4a5 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2002-2006 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Marius Groeger <mgroeger@sysgo.de> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
11 | */ |
12 | ||
13 | #include <common.h> | |
24b852a7 | 14 | #include <console.h> |
1938f4a5 | 15 | #include <environment.h> |
ab7cd627 | 16 | #include <dm.h> |
1938f4a5 | 17 | #include <fdtdec.h> |
f828bf25 | 18 | #include <fs.h> |
e4fef6cf | 19 | #include <i2c.h> |
1938f4a5 | 20 | #include <initcall.h> |
96d4b75c | 21 | #include <init_helpers.h> |
1938f4a5 | 22 | #include <logbuff.h> |
fb5cf7f1 | 23 | #include <malloc.h> |
0eb25b61 | 24 | #include <mapmem.h> |
e4fef6cf SG |
25 | |
26 | /* TODO: Can we move these into arch/ headers? */ | |
27 | #ifdef CONFIG_8xx | |
28 | #include <mpc8xx.h> | |
29 | #endif | |
30 | #ifdef CONFIG_5xx | |
31 | #include <mpc5xx.h> | |
32 | #endif | |
33 | #ifdef CONFIG_MPC5xxx | |
34 | #include <mpc5xxx.h> | |
35 | #endif | |
ec3b4820 | 36 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
a76df709 GH |
37 | #include <asm/mp.h> |
38 | #endif | |
e4fef6cf | 39 | |
a733b06b | 40 | #include <os.h> |
1938f4a5 | 41 | #include <post.h> |
e4fef6cf | 42 | #include <spi.h> |
c5d4001a | 43 | #include <status_led.h> |
1057e6cf | 44 | #include <timer.h> |
71c52dba | 45 | #include <trace.h> |
5a541945 | 46 | #include <video.h> |
e4fef6cf | 47 | #include <watchdog.h> |
1938f4a5 SG |
48 | #include <asm/io.h> |
49 | #include <asm/sections.h> | |
de5e5cea | 50 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) || defined(CONFIG_XTENSA) |
48a33806 SG |
51 | #include <asm/relocate.h> |
52 | #endif | |
ab7cd627 | 53 | #include <dm/root.h> |
056285fd | 54 | #include <linux/errno.h> |
1938f4a5 SG |
55 | |
56 | /* | |
57 | * Pointer to initial global data area | |
58 | * | |
59 | * Here we initialize it if needed. | |
60 | */ | |
61 | #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR | |
62 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
63 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
64 | DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); | |
65 | #else | |
66 | DECLARE_GLOBAL_DATA_PTR; | |
67 | #endif | |
68 | ||
69 | /* | |
4c509343 | 70 | * TODO(sjg@chromium.org): IMO this code should be |
1938f4a5 SG |
71 | * refactored to a single function, something like: |
72 | * | |
73 | * void led_set_state(enum led_colour_t colour, int on); | |
74 | */ | |
75 | /************************************************************************ | |
76 | * Coloured LED functionality | |
77 | ************************************************************************ | |
78 | * May be supplied by boards if desired | |
79 | */ | |
c5d4001a JH |
80 | __weak void coloured_LED_init(void) {} |
81 | __weak void red_led_on(void) {} | |
82 | __weak void red_led_off(void) {} | |
83 | __weak void green_led_on(void) {} | |
84 | __weak void green_led_off(void) {} | |
85 | __weak void yellow_led_on(void) {} | |
86 | __weak void yellow_led_off(void) {} | |
87 | __weak void blue_led_on(void) {} | |
88 | __weak void blue_led_off(void) {} | |
1938f4a5 SG |
89 | |
90 | /* | |
91 | * Why is gd allocated a register? Prior to reloc it might be better to | |
92 | * just pass it around to each function in this file? | |
93 | * | |
94 | * After reloc one could argue that it is hardly used and doesn't need | |
95 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
96 | * global data for all modules, so that post-reloc we can avoid the massive | |
97 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
98 | * a structure... | |
99 | */ | |
100 | ||
d54d7eb9 | 101 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) |
e4fef6cf SG |
102 | static int init_func_watchdog_init(void) |
103 | { | |
ea3310e8 TR |
104 | # if defined(CONFIG_HW_WATCHDOG) && \ |
105 | (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ | |
14a380a8 | 106 | defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ |
46d7a3b3 | 107 | defined(CONFIG_DESIGNWARE_WATCHDOG) || \ |
14a380a8 | 108 | defined(CONFIG_IMX_WATCHDOG)) |
d54d7eb9 | 109 | hw_watchdog_init(); |
e4fef6cf | 110 | puts(" Watchdog enabled\n"); |
ba169d98 | 111 | # endif |
e4fef6cf SG |
112 | WATCHDOG_RESET(); |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
117 | int init_func_watchdog_reset(void) | |
118 | { | |
119 | WATCHDOG_RESET(); | |
120 | ||
121 | return 0; | |
122 | } | |
123 | #endif /* CONFIG_WATCHDOG */ | |
124 | ||
dd2a6cd0 | 125 | __weak void board_add_ram_info(int use_default) |
e4fef6cf SG |
126 | { |
127 | /* please define platform specific board_add_ram_info() */ | |
128 | } | |
129 | ||
1938f4a5 SG |
130 | static int init_baud_rate(void) |
131 | { | |
132 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); | |
133 | return 0; | |
134 | } | |
135 | ||
136 | static int display_text_info(void) | |
137 | { | |
9b217498 | 138 | #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) |
9fdee7d7 | 139 | ulong bss_start, bss_end, text_base; |
1938f4a5 | 140 | |
632efa74 SG |
141 | bss_start = (ulong)&__bss_start; |
142 | bss_end = (ulong)&__bss_end; | |
b60eff31 | 143 | |
d54d7eb9 | 144 | #ifdef CONFIG_SYS_TEXT_BASE |
9fdee7d7 | 145 | text_base = CONFIG_SYS_TEXT_BASE; |
d54d7eb9 | 146 | #else |
9fdee7d7 | 147 | text_base = CONFIG_SYS_MONITOR_BASE; |
d54d7eb9 | 148 | #endif |
9fdee7d7 DS |
149 | |
150 | debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", | |
151 | text_base, bss_start, bss_end); | |
a733b06b | 152 | #endif |
1938f4a5 | 153 | |
1938f4a5 SG |
154 | #ifdef CONFIG_USE_IRQ |
155 | debug("IRQ Stack: %08lx\n", IRQ_STACK_START); | |
156 | debug("FIQ Stack: %08lx\n", FIQ_STACK_START); | |
157 | #endif | |
158 | ||
159 | return 0; | |
160 | } | |
161 | ||
162 | static int announce_dram_init(void) | |
163 | { | |
164 | puts("DRAM: "); | |
165 | return 0; | |
166 | } | |
167 | ||
e310b93e | 168 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
169 | static int init_func_ram(void) |
170 | { | |
088454cd | 171 | return initdram(); |
e4fef6cf SG |
172 | } |
173 | #endif | |
174 | ||
1938f4a5 SG |
175 | static int show_dram_config(void) |
176 | { | |
fa39ffe5 | 177 | unsigned long long size; |
1938f4a5 SG |
178 | |
179 | #ifdef CONFIG_NR_DRAM_BANKS | |
180 | int i; | |
181 | ||
182 | debug("\nRAM Configuration:\n"); | |
183 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
184 | size += gd->bd->bi_dram[i].size; | |
715f599f BM |
185 | debug("Bank #%d: %llx ", i, |
186 | (unsigned long long)(gd->bd->bi_dram[i].start)); | |
1938f4a5 SG |
187 | #ifdef DEBUG |
188 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
189 | #endif | |
190 | } | |
191 | debug("\nDRAM: "); | |
192 | #else | |
193 | size = gd->ram_size; | |
194 | #endif | |
195 | ||
e4fef6cf SG |
196 | print_size(size, ""); |
197 | board_add_ram_info(0); | |
198 | putc('\n'); | |
1938f4a5 SG |
199 | |
200 | return 0; | |
201 | } | |
202 | ||
76b00aca | 203 | __weak int dram_init_banksize(void) |
1938f4a5 SG |
204 | { |
205 | #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) | |
206 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
207 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
208 | #endif | |
76b00aca SG |
209 | |
210 | return 0; | |
1938f4a5 SG |
211 | } |
212 | ||
ea818dbb | 213 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
214 | static int init_func_i2c(void) |
215 | { | |
216 | puts("I2C: "); | |
815a76f2 | 217 | #ifdef CONFIG_SYS_I2C |
218 | i2c_init_all(); | |
219 | #else | |
e4fef6cf | 220 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
815a76f2 | 221 | #endif |
e4fef6cf SG |
222 | puts("ready\n"); |
223 | return 0; | |
224 | } | |
225 | #endif | |
226 | ||
227 | #if defined(CONFIG_HARD_SPI) | |
228 | static int init_func_spi(void) | |
229 | { | |
230 | puts("SPI: "); | |
231 | spi_init(); | |
232 | puts("ready\n"); | |
233 | return 0; | |
234 | } | |
235 | #endif | |
236 | ||
237 | __maybe_unused | |
1938f4a5 SG |
238 | static int zero_global_data(void) |
239 | { | |
240 | memset((void *)gd, '\0', sizeof(gd_t)); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static int setup_mon_len(void) | |
246 | { | |
e945f6dc | 247 | #if defined(__ARM__) || defined(__MICROBLAZE__) |
b60eff31 | 248 | gd->mon_len = (ulong)&__bss_end - (ulong)_start; |
9b217498 | 249 | #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) |
a733b06b | 250 | gd->mon_len = (ulong)&_end - (ulong)_init; |
ea3310e8 | 251 | #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) |
d54d7eb9 | 252 | gd->mon_len = CONFIG_SYS_MONITOR_LEN; |
e2099d78 | 253 | #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) |
2e88bb28 | 254 | gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); |
b0b35953 | 255 | #elif defined(CONFIG_SYS_MONITOR_BASE) |
e4fef6cf SG |
256 | /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ |
257 | gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 258 | #endif |
1938f4a5 SG |
259 | return 0; |
260 | } | |
261 | ||
262 | __weak int arch_cpu_init(void) | |
263 | { | |
264 | return 0; | |
265 | } | |
266 | ||
8ebf5069 PB |
267 | __weak int mach_cpu_init(void) |
268 | { | |
269 | return 0; | |
270 | } | |
271 | ||
1938f4a5 SG |
272 | /* Get the top of usable RAM */ |
273 | __weak ulong board_get_usable_ram_top(ulong total_size) | |
274 | { | |
1e4d11a5 SW |
275 | #ifdef CONFIG_SYS_SDRAM_BASE |
276 | /* | |
4c509343 | 277 | * Detect whether we have so much RAM that it goes past the end of our |
1e4d11a5 SW |
278 | * 32-bit address space. If so, clip the usable RAM so it doesn't. |
279 | */ | |
280 | if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) | |
281 | /* | |
282 | * Will wrap back to top of 32-bit space when reservations | |
283 | * are made. | |
284 | */ | |
285 | return 0; | |
286 | #endif | |
1938f4a5 SG |
287 | return gd->ram_top; |
288 | } | |
289 | ||
290 | static int setup_dest_addr(void) | |
291 | { | |
292 | debug("Monitor len: %08lX\n", gd->mon_len); | |
293 | /* | |
294 | * Ram is setup, size stored in gd !! | |
295 | */ | |
296 | debug("Ram size: %08lX\n", (ulong)gd->ram_size); | |
36cc0de0 | 297 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) |
1938f4a5 SG |
298 | /* |
299 | * Subtract specified amount of memory to hide so that it won't | |
300 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
301 | * the Linux kernel should now get passed the now "corrected" | |
36cc0de0 YS |
302 | * memory size and won't touch it either. This should work |
303 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
304 | * arch/powerpc with bootwrapper support, that recalculate the | |
305 | * memory size from the SDRAM controller setup will have to | |
306 | * get fixed. | |
1938f4a5 | 307 | */ |
36cc0de0 YS |
308 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; |
309 | #endif | |
1938f4a5 SG |
310 | #ifdef CONFIG_SYS_SDRAM_BASE |
311 | gd->ram_top = CONFIG_SYS_SDRAM_BASE; | |
312 | #endif | |
e4fef6cf | 313 | gd->ram_top += get_effective_memsize(); |
1938f4a5 | 314 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 315 | gd->relocaddr = gd->ram_top; |
1938f4a5 | 316 | debug("Ram top: %08lX\n", (ulong)gd->ram_top); |
ec3b4820 | 317 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
e4fef6cf SG |
318 | /* |
319 | * We need to make sure the location we intend to put secondary core | |
320 | * boot code is reserved and not used by any part of u-boot | |
321 | */ | |
a0ba279a MY |
322 | if (gd->relocaddr > determine_mp_bootpg(NULL)) { |
323 | gd->relocaddr = determine_mp_bootpg(NULL); | |
324 | debug("Reserving MP boot page to %08lx\n", gd->relocaddr); | |
e4fef6cf SG |
325 | } |
326 | #endif | |
1938f4a5 SG |
327 | return 0; |
328 | } | |
329 | ||
b56db486 | 330 | #if defined(CONFIG_LOGBUFFER) |
1938f4a5 SG |
331 | static int reserve_logbuffer(void) |
332 | { | |
b56db486 | 333 | #ifndef CONFIG_ALT_LB_ADDR |
1938f4a5 | 334 | /* reserve kernel log buffer */ |
a0ba279a | 335 | gd->relocaddr -= LOGBUFF_RESERVE; |
1938f4a5 | 336 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
a0ba279a | 337 | gd->relocaddr); |
b56db486 SG |
338 | #endif |
339 | ||
1938f4a5 SG |
340 | return 0; |
341 | } | |
342 | #endif | |
343 | ||
344 | #ifdef CONFIG_PRAM | |
345 | /* reserve protected RAM */ | |
346 | static int reserve_pram(void) | |
347 | { | |
348 | ulong reg; | |
349 | ||
350 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); | |
a0ba279a | 351 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 352 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 353 | gd->relocaddr); |
1938f4a5 SG |
354 | return 0; |
355 | } | |
356 | #endif /* CONFIG_PRAM */ | |
357 | ||
358 | /* Round memory pointer down to next 4 kB limit */ | |
359 | static int reserve_round_4k(void) | |
360 | { | |
a0ba279a | 361 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
362 | return 0; |
363 | } | |
364 | ||
80d4bcd3 | 365 | #ifdef CONFIG_ARM |
1938f4a5 SG |
366 | static int reserve_mmu(void) |
367 | { | |
80d4bcd3 | 368 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) |
1938f4a5 | 369 | /* reserve TLB table */ |
cce6be7f | 370 | gd->arch.tlb_size = PGTABLE_SIZE; |
a0ba279a | 371 | gd->relocaddr -= gd->arch.tlb_size; |
1938f4a5 SG |
372 | |
373 | /* round down to next 64 kB limit */ | |
a0ba279a | 374 | gd->relocaddr &= ~(0x10000 - 1); |
1938f4a5 | 375 | |
a0ba279a | 376 | gd->arch.tlb_addr = gd->relocaddr; |
1938f4a5 SG |
377 | debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, |
378 | gd->arch.tlb_addr + gd->arch.tlb_size); | |
50e93b95 YS |
379 | |
380 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE | |
381 | /* | |
382 | * Record allocated tlb_addr in case gd->tlb_addr to be overwritten | |
383 | * with location within secure ram. | |
384 | */ | |
385 | gd->arch.tlb_allocated = gd->arch.tlb_addr; | |
80d4bcd3 | 386 | #endif |
50e93b95 YS |
387 | #endif |
388 | ||
1938f4a5 SG |
389 | return 0; |
390 | } | |
391 | #endif | |
392 | ||
5a541945 SG |
393 | static int reserve_video(void) |
394 | { | |
0f079eb5 | 395 | #ifdef CONFIG_DM_VIDEO |
5a541945 SG |
396 | ulong addr; |
397 | int ret; | |
398 | ||
399 | addr = gd->relocaddr; | |
400 | ret = video_reserve(&addr); | |
401 | if (ret) | |
402 | return ret; | |
403 | gd->relocaddr = addr; | |
0f079eb5 | 404 | #elif defined(CONFIG_LCD) |
5a541945 | 405 | # ifdef CONFIG_FB_ADDR |
1938f4a5 | 406 | gd->fb_base = CONFIG_FB_ADDR; |
5a541945 | 407 | # else |
1938f4a5 | 408 | /* reserve memory for LCD display (always full pages) */ |
a0ba279a MY |
409 | gd->relocaddr = lcd_setmem(gd->relocaddr); |
410 | gd->fb_base = gd->relocaddr; | |
5a541945 | 411 | # endif /* CONFIG_FB_ADDR */ |
0f079eb5 SG |
412 | #elif defined(CONFIG_VIDEO) && \ |
413 | (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ | |
d54d7eb9 | 414 | !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ |
ea3310e8 | 415 | !defined(CONFIG_M68K) |
e4fef6cf | 416 | /* reserve memory for video display (always full pages) */ |
a0ba279a MY |
417 | gd->relocaddr = video_setmem(gd->relocaddr); |
418 | gd->fb_base = gd->relocaddr; | |
0f079eb5 | 419 | #endif |
e4fef6cf SG |
420 | |
421 | return 0; | |
422 | } | |
e4fef6cf | 423 | |
8703ef3f SG |
424 | static int reserve_trace(void) |
425 | { | |
426 | #ifdef CONFIG_TRACE | |
427 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
428 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
429 | debug("Reserving %dk for trace data at: %08lx\n", | |
430 | CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
431 | #endif | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
1938f4a5 SG |
436 | static int reserve_uboot(void) |
437 | { | |
438 | /* | |
439 | * reserve memory for U-Boot code, data & bss | |
440 | * round down to next 4 kB limit | |
441 | */ | |
a0ba279a MY |
442 | gd->relocaddr -= gd->mon_len; |
443 | gd->relocaddr &= ~(4096 - 1); | |
e4fef6cf SG |
444 | #ifdef CONFIG_E500 |
445 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
a0ba279a | 446 | gd->relocaddr &= ~(65536 - 1); |
e4fef6cf | 447 | #endif |
1938f4a5 SG |
448 | |
449 | debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, | |
a0ba279a MY |
450 | gd->relocaddr); |
451 | ||
452 | gd->start_addr_sp = gd->relocaddr; | |
453 | ||
1938f4a5 SG |
454 | return 0; |
455 | } | |
456 | ||
457 | /* reserve memory for malloc() area */ | |
458 | static int reserve_malloc(void) | |
459 | { | |
a0ba279a | 460 | gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; |
1938f4a5 | 461 | debug("Reserving %dk for malloc() at: %08lx\n", |
a0ba279a | 462 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
1938f4a5 SG |
463 | return 0; |
464 | } | |
465 | ||
466 | /* (permanently) allocate a Board Info struct */ | |
467 | static int reserve_board(void) | |
468 | { | |
d54d7eb9 SZ |
469 | if (!gd->bd) { |
470 | gd->start_addr_sp -= sizeof(bd_t); | |
471 | gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); | |
472 | memset(gd->bd, '\0', sizeof(bd_t)); | |
473 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", | |
474 | sizeof(bd_t), gd->start_addr_sp); | |
475 | } | |
1938f4a5 SG |
476 | return 0; |
477 | } | |
478 | ||
479 | static int setup_machine(void) | |
480 | { | |
481 | #ifdef CONFIG_MACH_TYPE | |
482 | gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ | |
483 | #endif | |
484 | return 0; | |
485 | } | |
486 | ||
487 | static int reserve_global_data(void) | |
488 | { | |
a0ba279a MY |
489 | gd->start_addr_sp -= sizeof(gd_t); |
490 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); | |
1938f4a5 | 491 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
a0ba279a | 492 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
493 | return 0; |
494 | } | |
495 | ||
496 | static int reserve_fdt(void) | |
497 | { | |
e9acb9ea | 498 | #ifndef CONFIG_OF_EMBED |
1938f4a5 | 499 | /* |
4c509343 | 500 | * If the device tree is sitting immediately above our image then we |
1938f4a5 SG |
501 | * must relocate it. If it is embedded in the data section, then it |
502 | * will be relocated with other data. | |
503 | */ | |
504 | if (gd->fdt_blob) { | |
505 | gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); | |
506 | ||
a0ba279a MY |
507 | gd->start_addr_sp -= gd->fdt_size; |
508 | gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); | |
a733b06b | 509 | debug("Reserving %lu Bytes for FDT at: %08lx\n", |
a0ba279a | 510 | gd->fdt_size, gd->start_addr_sp); |
1938f4a5 | 511 | } |
e9acb9ea | 512 | #endif |
1938f4a5 SG |
513 | |
514 | return 0; | |
515 | } | |
516 | ||
68145d4c | 517 | int arch_reserve_stacks(void) |
1938f4a5 | 518 | { |
68145d4c AB |
519 | return 0; |
520 | } | |
8cae8a68 | 521 | |
68145d4c AB |
522 | static int reserve_stacks(void) |
523 | { | |
524 | /* make stack pointer 16-byte aligned */ | |
a0ba279a MY |
525 | gd->start_addr_sp -= 16; |
526 | gd->start_addr_sp &= ~0xf; | |
1938f4a5 SG |
527 | |
528 | /* | |
4c509343 | 529 | * let the architecture-specific code tailor gd->start_addr_sp and |
68145d4c | 530 | * gd->irq_sp |
1938f4a5 | 531 | */ |
68145d4c | 532 | return arch_reserve_stacks(); |
1938f4a5 SG |
533 | } |
534 | ||
535 | static int display_new_sp(void) | |
536 | { | |
a0ba279a | 537 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
538 | |
539 | return 0; | |
540 | } | |
541 | ||
e2099d78 VZ |
542 | #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ |
543 | defined(CONFIG_SH) | |
e4fef6cf SG |
544 | static int setup_board_part1(void) |
545 | { | |
546 | bd_t *bd = gd->bd; | |
547 | ||
548 | /* | |
549 | * Save local variables to board info struct | |
550 | */ | |
e4fef6cf SG |
551 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ |
552 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
553 | ||
554 | #ifdef CONFIG_SYS_SRAM_BASE | |
555 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
556 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
557 | #endif | |
558 | ||
58dac327 | 559 | #if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ |
e4fef6cf SG |
560 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
561 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ | |
562 | #endif | |
e310b93e | 563 | #if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) |
e4fef6cf SG |
564 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
565 | #endif | |
566 | #if defined(CONFIG_MPC83xx) | |
567 | bd->bi_immrbar = CONFIG_SYS_IMMR; | |
568 | #endif | |
e4fef6cf SG |
569 | |
570 | return 0; | |
571 | } | |
fb3db635 | 572 | #endif |
e4fef6cf | 573 | |
fb3db635 | 574 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
575 | static int setup_board_part2(void) |
576 | { | |
577 | bd_t *bd = gd->bd; | |
578 | ||
579 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ | |
580 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
581 | #if defined(CONFIG_CPM2) | |
582 | bd->bi_cpmfreq = gd->arch.cpm_clk; | |
583 | bd->bi_brgfreq = gd->arch.brg_clk; | |
584 | bd->bi_sccfreq = gd->arch.scc_clk; | |
585 | bd->bi_vco = gd->arch.vco_out; | |
586 | #endif /* CONFIG_CPM2 */ | |
587 | #if defined(CONFIG_MPC512X) | |
588 | bd->bi_ipsfreq = gd->arch.ips_clk; | |
589 | #endif /* CONFIG_MPC512X */ | |
590 | #if defined(CONFIG_MPC5xxx) | |
591 | bd->bi_ipbfreq = gd->arch.ipb_clk; | |
592 | bd->bi_pcifreq = gd->pci_clk; | |
593 | #endif /* CONFIG_MPC5xxx */ | |
1313db48 AW |
594 | #if defined(CONFIG_M68K) && defined(CONFIG_PCI) |
595 | bd->bi_pcifreq = gd->pci_clk; | |
596 | #endif | |
597 | #if defined(CONFIG_EXTRA_CLOCK) | |
598 | bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ | |
599 | bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ | |
600 | bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ | |
601 | #endif | |
e4fef6cf SG |
602 | |
603 | return 0; | |
604 | } | |
605 | #endif | |
606 | ||
1938f4a5 SG |
607 | #ifdef CONFIG_POST |
608 | static int init_post(void) | |
609 | { | |
610 | post_bootmode_init(); | |
611 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
612 | ||
613 | return 0; | |
614 | } | |
615 | #endif | |
616 | ||
1938f4a5 SG |
617 | static int reloc_fdt(void) |
618 | { | |
e9acb9ea | 619 | #ifndef CONFIG_OF_EMBED |
f05ad9ba SG |
620 | if (gd->flags & GD_FLG_SKIP_RELOC) |
621 | return 0; | |
1938f4a5 SG |
622 | if (gd->new_fdt) { |
623 | memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); | |
624 | gd->fdt_blob = gd->new_fdt; | |
625 | } | |
e9acb9ea | 626 | #endif |
1938f4a5 SG |
627 | |
628 | return 0; | |
629 | } | |
630 | ||
631 | static int setup_reloc(void) | |
632 | { | |
f05ad9ba SG |
633 | if (gd->flags & GD_FLG_SKIP_RELOC) { |
634 | debug("Skipping relocation due to flag\n"); | |
635 | return 0; | |
636 | } | |
637 | ||
d54d7eb9 | 638 | #ifdef CONFIG_SYS_TEXT_BASE |
a0ba279a | 639 | gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; |
e310b93e | 640 | #ifdef CONFIG_M68K |
641 | /* | |
642 | * On all ColdFire arch cpu, monitor code starts always | |
643 | * just after the default vector table location, so at 0x400 | |
644 | */ | |
645 | gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); | |
646 | #endif | |
d54d7eb9 | 647 | #endif |
1938f4a5 SG |
648 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
649 | ||
650 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); | |
a733b06b | 651 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", |
a0ba279a MY |
652 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), |
653 | gd->start_addr_sp); | |
1938f4a5 SG |
654 | |
655 | return 0; | |
656 | } | |
657 | ||
2a792753 | 658 | #ifdef CONFIG_OF_BOARD_FIXUP |
659 | static int fix_fdt(void) | |
660 | { | |
661 | return board_fix_fdt((void *)gd->fdt_blob); | |
662 | } | |
663 | #endif | |
664 | ||
1938f4a5 | 665 | /* ARM calls relocate_code from its crt0.S */ |
530f27ea SG |
666 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
667 | !CONFIG_IS_ENABLED(X86_64) | |
1938f4a5 SG |
668 | |
669 | static int jump_to_copy(void) | |
670 | { | |
f05ad9ba SG |
671 | if (gd->flags & GD_FLG_SKIP_RELOC) |
672 | return 0; | |
48a33806 SG |
673 | /* |
674 | * x86 is special, but in a nice way. It uses a trampoline which | |
675 | * enables the dcache if possible. | |
676 | * | |
677 | * For now, other archs use relocate_code(), which is implemented | |
678 | * similarly for all archs. When we do generic relocation, hopefully | |
679 | * we can make all archs enable the dcache prior to relocation. | |
680 | */ | |
3fb80163 | 681 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
682 | /* |
683 | * SDRAM and console are now initialised. The final stack can now | |
684 | * be setup in SDRAM. Code execution will continue in Flash, but | |
685 | * with the stack in SDRAM and Global Data in temporary memory | |
686 | * (CPU cache) | |
687 | */ | |
f0c7d9c7 | 688 | arch_setup_gd(gd->new_gd); |
48a33806 SG |
689 | board_init_f_r_trampoline(gd->start_addr_sp); |
690 | #else | |
a0ba279a | 691 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 692 | #endif |
1938f4a5 SG |
693 | |
694 | return 0; | |
695 | } | |
696 | #endif | |
697 | ||
698 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
699 | static int mark_bootstage(void) | |
700 | { | |
701 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
9854a874 SG |
706 | static int initf_console_record(void) |
707 | { | |
708 | #if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F_LEN) | |
709 | return console_record_init(); | |
710 | #else | |
711 | return 0; | |
712 | #endif | |
713 | } | |
714 | ||
ab7cd627 SG |
715 | static int initf_dm(void) |
716 | { | |
717 | #if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) | |
718 | int ret; | |
719 | ||
720 | ret = dm_init_and_scan(true); | |
721 | if (ret) | |
722 | return ret; | |
723 | #endif | |
1057e6cf SG |
724 | #ifdef CONFIG_TIMER_EARLY |
725 | ret = dm_timer_init(); | |
726 | if (ret) | |
727 | return ret; | |
728 | #endif | |
ab7cd627 SG |
729 | |
730 | return 0; | |
731 | } | |
732 | ||
146251f8 SG |
733 | /* Architecture-specific memory reservation */ |
734 | __weak int reserve_arch(void) | |
735 | { | |
736 | return 0; | |
737 | } | |
738 | ||
d4c671cc SG |
739 | __weak int arch_cpu_init_dm(void) |
740 | { | |
741 | return 0; | |
742 | } | |
743 | ||
4acff452 | 744 | static const init_fnc_t init_sequence_f[] = { |
1938f4a5 | 745 | setup_mon_len, |
b45122fd | 746 | #ifdef CONFIG_OF_CONTROL |
0879361f | 747 | fdtdec_setup, |
b45122fd | 748 | #endif |
d210718d | 749 | #ifdef CONFIG_TRACE |
71c52dba | 750 | trace_early_init, |
d210718d | 751 | #endif |
768e0f52 | 752 | initf_malloc, |
9854a874 | 753 | initf_console_record, |
671549e5 SG |
754 | #if defined(CONFIG_HAVE_FSP) |
755 | arch_fsp_init, | |
e4fef6cf | 756 | #endif |
1938f4a5 | 757 | arch_cpu_init, /* basic arch cpu dependent setup */ |
8ebf5069 | 758 | mach_cpu_init, /* SoC/machine dependent CPU setup */ |
3ea0953d | 759 | initf_dm, |
d4c671cc | 760 | arch_cpu_init_dm, |
67521957 | 761 | mark_bootstage, /* need timer, go after init dm */ |
1938f4a5 SG |
762 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
763 | board_early_init_f, | |
764 | #endif | |
727e94a4 | 765 | #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) |
c252c068 | 766 | /* get CPU and bus clocks according to the environment variable */ |
e4fef6cf | 767 | get_clocks, /* get CPU and bus clocks (etc.) */ |
1793e782 | 768 | #endif |
1938f4a5 | 769 | timer_init, /* initialize timer */ |
e4fef6cf SG |
770 | #if defined(CONFIG_BOARD_POSTCLK_INIT) |
771 | board_postclk_init, | |
1938f4a5 SG |
772 | #endif |
773 | env_init, /* initialize environment */ | |
774 | init_baud_rate, /* initialze baudrate settings */ | |
775 | serial_init, /* serial communications setup */ | |
776 | console_init_f, /* stage 1 init of console */ | |
777 | display_options, /* say that we are here */ | |
778 | display_text_info, /* show debugging info if required */ | |
76d1d02f SG |
779 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ |
780 | defined(CONFIG_X86) | |
e4fef6cf SG |
781 | checkcpu, |
782 | #endif | |
cc664000 | 783 | #if defined(CONFIG_DISPLAY_CPUINFO) |
1938f4a5 | 784 | print_cpuinfo, /* display cpu info (and speed) */ |
cc664000 | 785 | #endif |
1938f4a5 | 786 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
0365ffcc | 787 | show_board_info, |
e4fef6cf SG |
788 | #endif |
789 | INIT_FUNC_WATCHDOG_INIT | |
790 | #if defined(CONFIG_MISC_INIT_F) | |
791 | misc_init_f, | |
792 | #endif | |
793 | INIT_FUNC_WATCHDOG_RESET | |
ea818dbb | 794 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
795 | init_func_i2c, |
796 | #endif | |
797 | #if defined(CONFIG_HARD_SPI) | |
798 | init_func_spi, | |
1938f4a5 SG |
799 | #endif |
800 | announce_dram_init, | |
801 | /* TODO: unify all these dram functions? */ | |
2e88bb28 | 802 | #if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_NDS32) || \ |
e2099d78 VZ |
803 | defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) || \ |
804 | defined(CONFIG_SH) | |
1938f4a5 SG |
805 | dram_init, /* configure available RAM banks */ |
806 | #endif | |
e310b93e | 807 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
808 | init_func_ram, |
809 | #endif | |
810 | #ifdef CONFIG_POST | |
811 | post_init_f, | |
812 | #endif | |
813 | INIT_FUNC_WATCHDOG_RESET | |
814 | #if defined(CONFIG_SYS_DRAM_TEST) | |
815 | testdram, | |
816 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
817 | INIT_FUNC_WATCHDOG_RESET | |
818 | ||
1938f4a5 SG |
819 | #ifdef CONFIG_POST |
820 | init_post, | |
821 | #endif | |
e4fef6cf | 822 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
823 | /* |
824 | * Now that we have DRAM mapped and working, we can | |
825 | * relocate the code and continue running from DRAM. | |
826 | * | |
827 | * Reserve memory at end of RAM for (top down in that order): | |
828 | * - area that won't get touched by U-Boot and Linux (optional) | |
829 | * - kernel log buffer | |
830 | * - protected RAM | |
831 | * - LCD framebuffer | |
832 | * - monitor code | |
833 | * - board info struct | |
834 | */ | |
835 | setup_dest_addr, | |
b56db486 | 836 | #if defined(CONFIG_LOGBUFFER) |
1938f4a5 SG |
837 | reserve_logbuffer, |
838 | #endif | |
839 | #ifdef CONFIG_PRAM | |
840 | reserve_pram, | |
841 | #endif | |
842 | reserve_round_4k, | |
80d4bcd3 | 843 | #ifdef CONFIG_ARM |
1938f4a5 SG |
844 | reserve_mmu, |
845 | #endif | |
5a541945 | 846 | reserve_video, |
8703ef3f | 847 | reserve_trace, |
1938f4a5 SG |
848 | reserve_uboot, |
849 | reserve_malloc, | |
850 | reserve_board, | |
851 | setup_machine, | |
852 | reserve_global_data, | |
853 | reserve_fdt, | |
146251f8 | 854 | reserve_arch, |
1938f4a5 | 855 | reserve_stacks, |
76b00aca | 856 | dram_init_banksize, |
1938f4a5 | 857 | show_dram_config, |
e2099d78 VZ |
858 | #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ |
859 | defined(CONFIG_SH) | |
e4fef6cf | 860 | setup_board_part1, |
fb3db635 DS |
861 | #endif |
862 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) | |
e4fef6cf SG |
863 | INIT_FUNC_WATCHDOG_RESET |
864 | setup_board_part2, | |
865 | #endif | |
1938f4a5 | 866 | display_new_sp, |
e4fef6cf SG |
867 | #ifdef CONFIG_SYS_EXTBDINFO |
868 | setup_board_extra, | |
2a792753 | 869 | #endif |
870 | #ifdef CONFIG_OF_BOARD_FIXUP | |
871 | fix_fdt, | |
e4fef6cf SG |
872 | #endif |
873 | INIT_FUNC_WATCHDOG_RESET | |
1938f4a5 SG |
874 | reloc_fdt, |
875 | setup_reloc, | |
3fb80163 | 876 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
313aef37 | 877 | copy_uboot_to_ram, |
313aef37 | 878 | do_elf_reloc_fixups, |
6bda55a3 | 879 | clear_bss, |
313aef37 | 880 | #endif |
de5e5cea CZ |
881 | #if defined(CONFIG_XTENSA) |
882 | clear_bss, | |
883 | #endif | |
530f27ea SG |
884 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
885 | !CONFIG_IS_ENABLED(X86_64) | |
1938f4a5 SG |
886 | jump_to_copy, |
887 | #endif | |
888 | NULL, | |
889 | }; | |
890 | ||
891 | void board_init_f(ulong boot_flags) | |
892 | { | |
2a1680e3 YS |
893 | #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA |
894 | /* | |
fc0b5948 | 895 | * For some architectures, global data is initialized and used before |
2a1680e3 YS |
896 | * calling this function. The data should be preserved. For others, |
897 | * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack | |
898 | * here to host global data until relocation. | |
899 | */ | |
1938f4a5 SG |
900 | gd_t data; |
901 | ||
902 | gd = &data; | |
903 | ||
cce6be7f DF |
904 | /* |
905 | * Clear global data before it is accessed at debug print | |
906 | * in initcall_run_list. Otherwise the debug print probably | |
fc0b5948 | 907 | * get the wrong value of gd->have_console. |
cce6be7f | 908 | */ |
cce6be7f DF |
909 | zero_global_data(); |
910 | #endif | |
911 | ||
1938f4a5 | 912 | gd->flags = boot_flags; |
9aed5a27 | 913 | gd->have_console = 0; |
1938f4a5 SG |
914 | |
915 | if (initcall_run_list(init_sequence_f)) | |
916 | hang(); | |
917 | ||
9b217498 | 918 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
530f27ea | 919 | !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) |
1938f4a5 SG |
920 | /* NOTREACHED - jump_to_copy() does not return */ |
921 | hang(); | |
922 | #endif | |
923 | } | |
924 | ||
3fb80163 | 925 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
926 | /* |
927 | * For now this code is only used on x86. | |
928 | * | |
929 | * init_sequence_f_r is the list of init functions which are run when | |
930 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
931 | * The following limitations must be considered when implementing an | |
932 | * '_f_r' function: | |
933 | * - 'static' variables are read-only | |
934 | * - Global Data (gd->xxx) is read/write | |
935 | * | |
936 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
937 | * supported). It _should_, if possible, copy global data to RAM and | |
938 | * initialise the CPU caches (to speed up the relocation process) | |
939 | * | |
940 | * NOTE: At present only x86 uses this route, but it is intended that | |
941 | * all archs will move to this when generic relocation is implemented. | |
942 | */ | |
4acff452 | 943 | static const init_fnc_t init_sequence_f_r[] = { |
530f27ea | 944 | #if !CONFIG_IS_ENABLED(X86_64) |
48a33806 | 945 | init_cache_f_r, |
530f27ea | 946 | #endif |
48a33806 SG |
947 | |
948 | NULL, | |
949 | }; | |
950 | ||
951 | void board_init_f_r(void) | |
952 | { | |
953 | if (initcall_run_list(init_sequence_f_r)) | |
954 | hang(); | |
955 | ||
e4d6ab0c SG |
956 | /* |
957 | * The pre-relocation drivers may be using memory that has now gone | |
958 | * away. Mark serial as unavailable - this will fall back to the debug | |
959 | * UART if available. | |
960 | */ | |
961 | gd->flags &= ~GD_FLG_SERIAL_READY; | |
962 | ||
48a33806 SG |
963 | /* |
964 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
965 | * Transfer execution from Flash to RAM by calculating the address | |
966 | * of the in-RAM copy of board_init_r() and calling it | |
967 | */ | |
7bf9f20d | 968 | (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); |
48a33806 SG |
969 | |
970 | /* NOTREACHED - board_init_r() does not return */ | |
971 | hang(); | |
972 | } | |
5bcd19aa | 973 | #endif /* CONFIG_X86 */ |