]>
Commit | Line | Data |
---|---|---|
de941241 SG |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * Sukumar Ghorai <s-ghorai@ti.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation's version 2 of | |
12 | * the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <config.h> | |
26 | #include <common.h> | |
93bfd616 | 27 | #include <malloc.h> |
de941241 SG |
28 | #include <mmc.h> |
29 | #include <part.h> | |
30 | #include <i2c.h> | |
31 | #include <twl4030.h> | |
14fa2dd0 | 32 | #include <twl6030.h> |
cb199102 | 33 | #include <palmas.h> |
de941241 SG |
34 | #include <asm/io.h> |
35 | #include <asm/arch/mmc_host_def.h> | |
3b68939f RQ |
36 | #if !defined(CONFIG_SOC_KEYSTONE) |
37 | #include <asm/gpio.h> | |
96e0e7b3 | 38 | #include <asm/arch/sys_proto.h> |
3b68939f | 39 | #endif |
2a48b3a2 TR |
40 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
41 | #include <asm/arch/mux.h> | |
42 | #endif | |
a9d6a7e2 M |
43 | #include <dm.h> |
44 | ||
45 | DECLARE_GLOBAL_DATA_PTR; | |
de941241 | 46 | |
ab769f22 PA |
47 | /* simplify defines to OMAP_HSMMC_USE_GPIO */ |
48 | #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ | |
49 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) | |
50 | #define OMAP_HSMMC_USE_GPIO | |
51 | #else | |
52 | #undef OMAP_HSMMC_USE_GPIO | |
53 | #endif | |
54 | ||
25c719e2 GI |
55 | /* common definitions for all OMAPs */ |
56 | #define SYSCTL_SRC (1 << 25) | |
57 | #define SYSCTL_SRD (1 << 26) | |
58 | ||
3d673ffc JJH |
59 | struct omap_hsmmc_plat { |
60 | struct mmc_config cfg; | |
17c9a1c1 | 61 | struct mmc mmc; |
3d673ffc JJH |
62 | }; |
63 | ||
cc22b0c0 NK |
64 | struct omap_hsmmc_data { |
65 | struct hsmmc *base_addr; | |
3d673ffc | 66 | #ifndef CONFIG_DM_MMC |
93bfd616 | 67 | struct mmc_config cfg; |
3d673ffc | 68 | #endif |
ab769f22 | 69 | #ifdef OMAP_HSMMC_USE_GPIO |
a9d6a7e2 M |
70 | #ifdef CONFIG_DM_MMC |
71 | struct gpio_desc cd_gpio; /* Change Detect GPIO */ | |
72 | struct gpio_desc wp_gpio; /* Write Protect GPIO */ | |
73 | bool cd_inverted; | |
74 | #else | |
e874d5b0 | 75 | int cd_gpio; |
e3913f56 | 76 | int wp_gpio; |
ab769f22 | 77 | #endif |
a9d6a7e2 | 78 | #endif |
cc22b0c0 NK |
79 | }; |
80 | ||
eb9a28f6 NM |
81 | /* If we fail after 1 second wait, something is really bad */ |
82 | #define MAX_RETRY_MS 1000 | |
83 | ||
933efe64 S |
84 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); |
85 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, | |
86 | unsigned int siz); | |
14fa2dd0 | 87 | |
ae000e23 JJH |
88 | static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) |
89 | { | |
90 | #ifdef CONFIG_DM_MMC | |
91 | return dev_get_priv(mmc->dev); | |
92 | #else | |
93 | return (struct omap_hsmmc_data *)mmc->priv; | |
94 | #endif | |
3d673ffc JJH |
95 | } |
96 | static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc) | |
97 | { | |
98 | #ifdef CONFIG_DM_MMC | |
99 | struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev); | |
100 | return &plat->cfg; | |
101 | #else | |
102 | return &((struct omap_hsmmc_data *)mmc->priv)->cfg; | |
103 | #endif | |
ae000e23 JJH |
104 | } |
105 | ||
106 | #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC) | |
e874d5b0 NK |
107 | static int omap_mmc_setup_gpio_in(int gpio, const char *label) |
108 | { | |
5915a2ad | 109 | int ret; |
e874d5b0 | 110 | |
5915a2ad SG |
111 | #ifndef CONFIG_DM_GPIO |
112 | if (!gpio_is_valid(gpio)) | |
e874d5b0 | 113 | return -1; |
5915a2ad SG |
114 | #endif |
115 | ret = gpio_request(gpio, label); | |
116 | if (ret) | |
117 | return ret; | |
e874d5b0 | 118 | |
5915a2ad SG |
119 | ret = gpio_direction_input(gpio); |
120 | if (ret) | |
121 | return ret; | |
e874d5b0 NK |
122 | |
123 | return gpio; | |
124 | } | |
e874d5b0 NK |
125 | #endif |
126 | ||
750121c3 | 127 | static unsigned char mmc_board_init(struct mmc *mmc) |
de941241 | 128 | { |
de941241 | 129 | #if defined(CONFIG_OMAP34XX) |
3d673ffc | 130 | struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); |
de941241 SG |
131 | t2_t *t2_base = (t2_t *)T2_BASE; |
132 | struct prcm *prcm_base = (struct prcm *)PRCM_BASE; | |
b1e725f2 | 133 | u32 pbias_lite; |
6aca17c9 AF |
134 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
135 | u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL); | |
136 | #endif | |
de941241 | 137 | |
b1e725f2 GI |
138 | pbias_lite = readl(&t2_base->pbias_lite); |
139 | pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); | |
5bfdd1fc AA |
140 | #ifdef CONFIG_TARGET_OMAP3_CAIRO |
141 | /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ | |
142 | pbias_lite &= ~PBIASLITEVMODE0; | |
6aca17c9 AF |
143 | #endif |
144 | #ifdef CONFIG_MMC_OMAP36XX_PINS | |
145 | if (get_cpu_family() == CPU_OMAP36XX) { | |
146 | /* Disable extended drain IO before changing PBIAS */ | |
147 | wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ; | |
148 | writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL); | |
149 | } | |
5bfdd1fc | 150 | #endif |
b1e725f2 | 151 | writel(pbias_lite, &t2_base->pbias_lite); |
aac5450e | 152 | |
b1e725f2 | 153 | writel(pbias_lite | PBIASLITEPWRDNZ1 | |
de941241 SG |
154 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, |
155 | &t2_base->pbias_lite); | |
156 | ||
6aca17c9 AF |
157 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
158 | if (get_cpu_family() == CPU_OMAP36XX) | |
159 | /* Enable extended drain IO after changing PBIAS */ | |
160 | writel(wkup_ctrl | | |
161 | OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, | |
162 | OMAP34XX_CTRL_WKUP_CTRL); | |
163 | #endif | |
de941241 SG |
164 | writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, |
165 | &t2_base->devconf0); | |
166 | ||
167 | writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, | |
168 | &t2_base->devconf1); | |
169 | ||
bbbc1ae9 | 170 | /* Change from default of 52MHz to 26MHz if necessary */ |
3d673ffc | 171 | if (!(cfg->host_caps & MMC_MODE_HS_52MHz)) |
bbbc1ae9 JS |
172 | writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, |
173 | &t2_base->ctl_prog_io1); | |
174 | ||
de941241 SG |
175 | writel(readl(&prcm_base->fclken1_core) | |
176 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
177 | &prcm_base->fclken1_core); | |
178 | ||
179 | writel(readl(&prcm_base->iclken1_core) | | |
180 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
181 | &prcm_base->iclken1_core); | |
182 | #endif | |
183 | ||
b4b06006 | 184 | #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX) |
14fa2dd0 | 185 | /* PBIAS config needed for MMC1 only */ |
dc09127a | 186 | if (mmc_get_blk_desc(mmc)->devnum == 0) |
b4b06006 | 187 | vmmc_pbias_config(LDO_VOLT_3V0); |
dd23e59d | 188 | #endif |
de941241 SG |
189 | |
190 | return 0; | |
191 | } | |
192 | ||
933efe64 | 193 | void mmc_init_stream(struct hsmmc *mmc_base) |
de941241 | 194 | { |
eb9a28f6 | 195 | ulong start; |
de941241 SG |
196 | |
197 | writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); | |
198 | ||
199 | writel(MMC_CMD0, &mmc_base->cmd); | |
eb9a28f6 NM |
200 | start = get_timer(0); |
201 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
202 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
203 | printf("%s: timedout waiting for cc!\n", __func__); | |
204 | return; | |
205 | } | |
206 | } | |
de941241 SG |
207 | writel(CC_MASK, &mmc_base->stat) |
208 | ; | |
209 | writel(MMC_CMD0, &mmc_base->cmd) | |
210 | ; | |
eb9a28f6 NM |
211 | start = get_timer(0); |
212 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
213 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
214 | printf("%s: timedout waiting for cc2!\n", __func__); | |
215 | return; | |
216 | } | |
217 | } | |
de941241 SG |
218 | writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); |
219 | } | |
220 | ||
ab769f22 | 221 | static int omap_hsmmc_init_setup(struct mmc *mmc) |
de941241 | 222 | { |
ae000e23 | 223 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
cc22b0c0 | 224 | struct hsmmc *mmc_base; |
de941241 SG |
225 | unsigned int reg_val; |
226 | unsigned int dsor; | |
eb9a28f6 | 227 | ulong start; |
de941241 | 228 | |
ae000e23 | 229 | mmc_base = priv->base_addr; |
14fa2dd0 | 230 | mmc_board_init(mmc); |
de941241 SG |
231 | |
232 | writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, | |
233 | &mmc_base->sysconfig); | |
eb9a28f6 NM |
234 | start = get_timer(0); |
235 | while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { | |
236 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
237 | printf("%s: timedout waiting for cc2!\n", __func__); | |
915ffa52 | 238 | return -ETIMEDOUT; |
eb9a28f6 NM |
239 | } |
240 | } | |
de941241 | 241 | writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); |
eb9a28f6 NM |
242 | start = get_timer(0); |
243 | while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { | |
244 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
245 | printf("%s: timedout waiting for softresetall!\n", | |
246 | __func__); | |
915ffa52 | 247 | return -ETIMEDOUT; |
eb9a28f6 NM |
248 | } |
249 | } | |
de941241 SG |
250 | writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); |
251 | writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, | |
252 | &mmc_base->capa); | |
253 | ||
254 | reg_val = readl(&mmc_base->con) & RESERVED_MASK; | |
255 | ||
256 | writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | | |
257 | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | | |
258 | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); | |
259 | ||
260 | dsor = 240; | |
261 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
262 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
263 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
264 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
eb9a28f6 NM |
265 | start = get_timer(0); |
266 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
267 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
268 | printf("%s: timedout waiting for ics!\n", __func__); | |
915ffa52 | 269 | return -ETIMEDOUT; |
eb9a28f6 NM |
270 | } |
271 | } | |
de941241 SG |
272 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
273 | ||
274 | writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); | |
275 | ||
276 | writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | | |
277 | IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, | |
278 | &mmc_base->ie); | |
279 | ||
280 | mmc_init_stream(mmc_base); | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
25c719e2 GI |
285 | /* |
286 | * MMC controller internal finite state machine reset | |
287 | * | |
288 | * Used to reset command or data internal state machines, using respectively | |
289 | * SRC or SRD bit of SYSCTL register | |
290 | */ | |
291 | static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) | |
292 | { | |
293 | ulong start; | |
294 | ||
295 | mmc_reg_out(&mmc_base->sysctl, bit, bit); | |
296 | ||
61a6cc27 OT |
297 | /* |
298 | * CMD(DAT) lines reset procedures are slightly different | |
299 | * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). | |
300 | * According to OMAP3 TRM: | |
301 | * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it | |
302 | * returns to 0x0. | |
303 | * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset | |
304 | * procedure steps must be as follows: | |
305 | * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in | |
306 | * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). | |
307 | * 2. Poll the SRC(SRD) bit until it is set to 0x1. | |
308 | * 3. Wait until the SRC (SRD) bit returns to 0x0 | |
309 | * (reset procedure is completed). | |
310 | */ | |
311 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ | |
dce55b93 | 312 | defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) |
61a6cc27 OT |
313 | if (!(readl(&mmc_base->sysctl) & bit)) { |
314 | start = get_timer(0); | |
315 | while (!(readl(&mmc_base->sysctl) & bit)) { | |
316 | if (get_timer(0) - start > MAX_RETRY_MS) | |
317 | return; | |
318 | } | |
319 | } | |
320 | #endif | |
25c719e2 GI |
321 | start = get_timer(0); |
322 | while ((readl(&mmc_base->sysctl) & bit) != 0) { | |
323 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
324 | printf("%s: timedout waiting for sysctl %x to clear\n", | |
325 | __func__, bit); | |
326 | return; | |
327 | } | |
328 | } | |
329 | } | |
de941241 | 330 | |
ab769f22 | 331 | static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
de941241 SG |
332 | struct mmc_data *data) |
333 | { | |
ae000e23 | 334 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
cc22b0c0 | 335 | struct hsmmc *mmc_base; |
de941241 | 336 | unsigned int flags, mmc_stat; |
eb9a28f6 | 337 | ulong start; |
de941241 | 338 | |
ae000e23 | 339 | mmc_base = priv->base_addr; |
eb9a28f6 | 340 | start = get_timer(0); |
a7778f8f | 341 | while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { |
eb9a28f6 | 342 | if (get_timer(0) - start > MAX_RETRY_MS) { |
a7778f8f TR |
343 | printf("%s: timedout waiting on cmd inhibit to clear\n", |
344 | __func__); | |
915ffa52 | 345 | return -ETIMEDOUT; |
eb9a28f6 NM |
346 | } |
347 | } | |
de941241 | 348 | writel(0xFFFFFFFF, &mmc_base->stat); |
eb9a28f6 NM |
349 | start = get_timer(0); |
350 | while (readl(&mmc_base->stat)) { | |
351 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
15ceb1de GI |
352 | printf("%s: timedout waiting for STAT (%x) to clear\n", |
353 | __func__, readl(&mmc_base->stat)); | |
915ffa52 | 354 | return -ETIMEDOUT; |
eb9a28f6 NM |
355 | } |
356 | } | |
de941241 SG |
357 | /* |
358 | * CMDREG | |
359 | * CMDIDX[13:8] : Command index | |
360 | * DATAPRNT[5] : Data Present Select | |
361 | * ENCMDIDX[4] : Command Index Check Enable | |
362 | * ENCMDCRC[3] : Command CRC Check Enable | |
363 | * RSPTYP[1:0] | |
364 | * 00 = No Response | |
365 | * 01 = Length 136 | |
366 | * 10 = Length 48 | |
367 | * 11 = Length 48 Check busy after response | |
368 | */ | |
369 | /* Delay added before checking the status of frq change | |
370 | * retry not supported by mmc.c(core file) | |
371 | */ | |
372 | if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) | |
373 | udelay(50000); /* wait 50 ms */ | |
374 | ||
375 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) | |
376 | flags = 0; | |
377 | else if (cmd->resp_type & MMC_RSP_136) | |
378 | flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; | |
379 | else if (cmd->resp_type & MMC_RSP_BUSY) | |
380 | flags = RSP_TYPE_LGHT48B; | |
381 | else | |
382 | flags = RSP_TYPE_LGHT48; | |
383 | ||
384 | /* enable default flags */ | |
385 | flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | | |
386 | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); | |
387 | ||
388 | if (cmd->resp_type & MMC_RSP_CRC) | |
389 | flags |= CCCE_CHECK; | |
390 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
391 | flags |= CICE_CHECK; | |
392 | ||
393 | if (data) { | |
394 | if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || | |
395 | (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { | |
396 | flags |= (MSBS_MULTIBLK | BCE_ENABLE); | |
397 | data->blocksize = 512; | |
398 | writel(data->blocksize | (data->blocks << 16), | |
399 | &mmc_base->blk); | |
400 | } else | |
401 | writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); | |
402 | ||
403 | if (data->flags & MMC_DATA_READ) | |
404 | flags |= (DP_DATA | DDIR_READ); | |
405 | else | |
406 | flags |= (DP_DATA | DDIR_WRITE); | |
407 | } | |
408 | ||
409 | writel(cmd->cmdarg, &mmc_base->arg); | |
152ba363 | 410 | udelay(20); /* To fix "No status update" error on eMMC */ |
de941241 SG |
411 | writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); |
412 | ||
eb9a28f6 | 413 | start = get_timer(0); |
de941241 SG |
414 | do { |
415 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
416 | if (get_timer(0) - start > MAX_RETRY_MS) { |
417 | printf("%s : timeout: No status update\n", __func__); | |
915ffa52 | 418 | return -ETIMEDOUT; |
eb9a28f6 NM |
419 | } |
420 | } while (!mmc_stat); | |
de941241 | 421 | |
25c719e2 GI |
422 | if ((mmc_stat & IE_CTO) != 0) { |
423 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); | |
915ffa52 | 424 | return -ETIMEDOUT; |
25c719e2 | 425 | } else if ((mmc_stat & ERRI_MASK) != 0) |
de941241 SG |
426 | return -1; |
427 | ||
428 | if (mmc_stat & CC_MASK) { | |
429 | writel(CC_MASK, &mmc_base->stat); | |
430 | if (cmd->resp_type & MMC_RSP_PRESENT) { | |
431 | if (cmd->resp_type & MMC_RSP_136) { | |
432 | /* response type 2 */ | |
433 | cmd->response[3] = readl(&mmc_base->rsp10); | |
434 | cmd->response[2] = readl(&mmc_base->rsp32); | |
435 | cmd->response[1] = readl(&mmc_base->rsp54); | |
436 | cmd->response[0] = readl(&mmc_base->rsp76); | |
437 | } else | |
438 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
439 | cmd->response[0] = readl(&mmc_base->rsp10); | |
440 | } | |
441 | } | |
442 | ||
443 | if (data && (data->flags & MMC_DATA_READ)) { | |
444 | mmc_read_data(mmc_base, data->dest, | |
445 | data->blocksize * data->blocks); | |
446 | } else if (data && (data->flags & MMC_DATA_WRITE)) { | |
447 | mmc_write_data(mmc_base, data->src, | |
448 | data->blocksize * data->blocks); | |
449 | } | |
450 | return 0; | |
451 | } | |
452 | ||
933efe64 | 453 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) |
de941241 SG |
454 | { |
455 | unsigned int *output_buf = (unsigned int *)buf; | |
456 | unsigned int mmc_stat; | |
457 | unsigned int count; | |
458 | ||
459 | /* | |
460 | * Start Polled Read | |
461 | */ | |
462 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
463 | count /= 4; | |
464 | ||
465 | while (size) { | |
eb9a28f6 | 466 | ulong start = get_timer(0); |
de941241 SG |
467 | do { |
468 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
469 | if (get_timer(0) - start > MAX_RETRY_MS) { |
470 | printf("%s: timedout waiting for status!\n", | |
471 | __func__); | |
915ffa52 | 472 | return -ETIMEDOUT; |
eb9a28f6 | 473 | } |
de941241 SG |
474 | } while (mmc_stat == 0); |
475 | ||
25c719e2 GI |
476 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
477 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
478 | ||
de941241 SG |
479 | if ((mmc_stat & ERRI_MASK) != 0) |
480 | return 1; | |
481 | ||
482 | if (mmc_stat & BRR_MASK) { | |
483 | unsigned int k; | |
484 | ||
485 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
486 | &mmc_base->stat); | |
487 | for (k = 0; k < count; k++) { | |
488 | *output_buf = readl(&mmc_base->data); | |
489 | output_buf++; | |
490 | } | |
491 | size -= (count*4); | |
492 | } | |
493 | ||
494 | if (mmc_stat & BWR_MASK) | |
495 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
496 | &mmc_base->stat); | |
497 | ||
498 | if (mmc_stat & TC_MASK) { | |
499 | writel(readl(&mmc_base->stat) | TC_MASK, | |
500 | &mmc_base->stat); | |
501 | break; | |
502 | } | |
503 | } | |
504 | return 0; | |
505 | } | |
506 | ||
933efe64 S |
507 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, |
508 | unsigned int size) | |
de941241 SG |
509 | { |
510 | unsigned int *input_buf = (unsigned int *)buf; | |
511 | unsigned int mmc_stat; | |
512 | unsigned int count; | |
513 | ||
514 | /* | |
152ba363 | 515 | * Start Polled Write |
de941241 SG |
516 | */ |
517 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
518 | count /= 4; | |
519 | ||
520 | while (size) { | |
eb9a28f6 | 521 | ulong start = get_timer(0); |
de941241 SG |
522 | do { |
523 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
524 | if (get_timer(0) - start > MAX_RETRY_MS) { |
525 | printf("%s: timedout waiting for status!\n", | |
526 | __func__); | |
915ffa52 | 527 | return -ETIMEDOUT; |
eb9a28f6 | 528 | } |
de941241 SG |
529 | } while (mmc_stat == 0); |
530 | ||
25c719e2 GI |
531 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
532 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
533 | ||
de941241 SG |
534 | if ((mmc_stat & ERRI_MASK) != 0) |
535 | return 1; | |
536 | ||
537 | if (mmc_stat & BWR_MASK) { | |
538 | unsigned int k; | |
539 | ||
540 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
541 | &mmc_base->stat); | |
542 | for (k = 0; k < count; k++) { | |
543 | writel(*input_buf, &mmc_base->data); | |
544 | input_buf++; | |
545 | } | |
546 | size -= (count*4); | |
547 | } | |
548 | ||
549 | if (mmc_stat & BRR_MASK) | |
550 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
551 | &mmc_base->stat); | |
552 | ||
553 | if (mmc_stat & TC_MASK) { | |
554 | writel(readl(&mmc_base->stat) | TC_MASK, | |
555 | &mmc_base->stat); | |
556 | break; | |
557 | } | |
558 | } | |
559 | return 0; | |
560 | } | |
561 | ||
07b0b9c0 | 562 | static int omap_hsmmc_set_ios(struct mmc *mmc) |
de941241 | 563 | { |
ae000e23 | 564 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
cc22b0c0 | 565 | struct hsmmc *mmc_base; |
de941241 | 566 | unsigned int dsor = 0; |
eb9a28f6 | 567 | ulong start; |
de941241 | 568 | |
ae000e23 | 569 | mmc_base = priv->base_addr; |
de941241 SG |
570 | /* configue bus width */ |
571 | switch (mmc->bus_width) { | |
572 | case 8: | |
573 | writel(readl(&mmc_base->con) | DTW_8_BITMODE, | |
574 | &mmc_base->con); | |
575 | break; | |
576 | ||
577 | case 4: | |
578 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
579 | &mmc_base->con); | |
580 | writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, | |
581 | &mmc_base->hctl); | |
582 | break; | |
583 | ||
584 | case 1: | |
585 | default: | |
586 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
587 | &mmc_base->con); | |
588 | writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, | |
589 | &mmc_base->hctl); | |
590 | break; | |
591 | } | |
592 | ||
593 | /* configure clock with 96Mhz system clock. | |
594 | */ | |
595 | if (mmc->clock != 0) { | |
596 | dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); | |
597 | if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) | |
598 | dsor++; | |
599 | } | |
600 | ||
601 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
602 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
603 | ||
604 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
605 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
606 | ||
eb9a28f6 NM |
607 | start = get_timer(0); |
608 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
609 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
610 | printf("%s: timedout waiting for ics!\n", __func__); | |
07b0b9c0 | 611 | return -ETIMEDOUT; |
eb9a28f6 NM |
612 | } |
613 | } | |
de941241 | 614 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
07b0b9c0 JC |
615 | |
616 | return 0; | |
de941241 SG |
617 | } |
618 | ||
ab769f22 | 619 | #ifdef OMAP_HSMMC_USE_GPIO |
a9d6a7e2 M |
620 | #ifdef CONFIG_DM_MMC |
621 | static int omap_hsmmc_getcd(struct mmc *mmc) | |
622 | { | |
ae000e23 | 623 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
a9d6a7e2 M |
624 | int value; |
625 | ||
626 | value = dm_gpio_get_value(&priv->cd_gpio); | |
627 | /* if no CD return as 1 */ | |
628 | if (value < 0) | |
629 | return 1; | |
630 | ||
631 | if (priv->cd_inverted) | |
632 | return !value; | |
633 | return value; | |
634 | } | |
635 | ||
636 | static int omap_hsmmc_getwp(struct mmc *mmc) | |
637 | { | |
ae000e23 | 638 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
a9d6a7e2 M |
639 | int value; |
640 | ||
641 | value = dm_gpio_get_value(&priv->wp_gpio); | |
642 | /* if no WP return as 0 */ | |
643 | if (value < 0) | |
644 | return 0; | |
645 | return value; | |
646 | } | |
647 | #else | |
ab769f22 PA |
648 | static int omap_hsmmc_getcd(struct mmc *mmc) |
649 | { | |
ae000e23 | 650 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
ab769f22 PA |
651 | int cd_gpio; |
652 | ||
653 | /* if no CD return as 1 */ | |
ae000e23 | 654 | cd_gpio = priv->cd_gpio; |
ab769f22 PA |
655 | if (cd_gpio < 0) |
656 | return 1; | |
657 | ||
0b03a931 IG |
658 | /* NOTE: assumes card detect signal is active-low */ |
659 | return !gpio_get_value(cd_gpio); | |
ab769f22 PA |
660 | } |
661 | ||
662 | static int omap_hsmmc_getwp(struct mmc *mmc) | |
663 | { | |
ae000e23 | 664 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
ab769f22 PA |
665 | int wp_gpio; |
666 | ||
667 | /* if no WP return as 0 */ | |
ae000e23 | 668 | wp_gpio = priv->wp_gpio; |
ab769f22 PA |
669 | if (wp_gpio < 0) |
670 | return 0; | |
671 | ||
0b03a931 | 672 | /* NOTE: assumes write protect signal is active-high */ |
ab769f22 PA |
673 | return gpio_get_value(wp_gpio); |
674 | } | |
675 | #endif | |
a9d6a7e2 | 676 | #endif |
ab769f22 PA |
677 | |
678 | static const struct mmc_ops omap_hsmmc_ops = { | |
679 | .send_cmd = omap_hsmmc_send_cmd, | |
680 | .set_ios = omap_hsmmc_set_ios, | |
681 | .init = omap_hsmmc_init_setup, | |
682 | #ifdef OMAP_HSMMC_USE_GPIO | |
683 | .getcd = omap_hsmmc_getcd, | |
684 | .getwp = omap_hsmmc_getwp, | |
685 | #endif | |
686 | }; | |
687 | ||
a9d6a7e2 | 688 | #ifndef CONFIG_DM_MMC |
e3913f56 NK |
689 | int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, |
690 | int wp_gpio) | |
de941241 | 691 | { |
93bfd616 | 692 | struct mmc *mmc; |
ae000e23 | 693 | struct omap_hsmmc_data *priv; |
93bfd616 PA |
694 | struct mmc_config *cfg; |
695 | uint host_caps_val; | |
696 | ||
ae000e23 JJH |
697 | priv = malloc(sizeof(*priv)); |
698 | if (priv == NULL) | |
93bfd616 | 699 | return -1; |
de941241 | 700 | |
5a20397b | 701 | host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; |
de941241 SG |
702 | |
703 | switch (dev_index) { | |
704 | case 0: | |
ae000e23 | 705 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 | 706 | break; |
1037d585 | 707 | #ifdef OMAP_HSMMC2_BASE |
de941241 | 708 | case 1: |
ae000e23 | 709 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; |
152ba363 | 710 | #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ |
3891a54f | 711 | defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ |
3b68939f RQ |
712 | defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ |
713 | defined(CONFIG_HSMMC2_8BIT) | |
152ba363 LP |
714 | /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ |
715 | host_caps_val |= MMC_MODE_8BIT; | |
716 | #endif | |
de941241 | 717 | break; |
1037d585 TR |
718 | #endif |
719 | #ifdef OMAP_HSMMC3_BASE | |
de941241 | 720 | case 2: |
ae000e23 | 721 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; |
3891a54f | 722 | #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) |
152ba363 LP |
723 | /* Enable 8-bit interface for eMMC on DRA7XX */ |
724 | host_caps_val |= MMC_MODE_8BIT; | |
725 | #endif | |
de941241 | 726 | break; |
1037d585 | 727 | #endif |
de941241 | 728 | default: |
ae000e23 | 729 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 SG |
730 | return 1; |
731 | } | |
ab769f22 PA |
732 | #ifdef OMAP_HSMMC_USE_GPIO |
733 | /* on error gpio values are set to -1, which is what we want */ | |
ae000e23 JJH |
734 | priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); |
735 | priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); | |
ab769f22 | 736 | #endif |
173ddc5b | 737 | |
ae000e23 | 738 | cfg = &priv->cfg; |
de941241 | 739 | |
93bfd616 PA |
740 | cfg->name = "OMAP SD/MMC"; |
741 | cfg->ops = &omap_hsmmc_ops; | |
742 | ||
743 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
744 | cfg->host_caps = host_caps_val & ~host_caps_mask; | |
745 | ||
746 | cfg->f_min = 400000; | |
bbbc1ae9 JS |
747 | |
748 | if (f_max != 0) | |
93bfd616 | 749 | cfg->f_max = f_max; |
bbbc1ae9 | 750 | else { |
93bfd616 PA |
751 | if (cfg->host_caps & MMC_MODE_HS) { |
752 | if (cfg->host_caps & MMC_MODE_HS_52MHz) | |
753 | cfg->f_max = 52000000; | |
bbbc1ae9 | 754 | else |
93bfd616 | 755 | cfg->f_max = 26000000; |
bbbc1ae9 | 756 | } else |
93bfd616 | 757 | cfg->f_max = 20000000; |
bbbc1ae9 | 758 | } |
de941241 | 759 | |
93bfd616 | 760 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
8feafcc4 | 761 | |
4ca9244d JR |
762 | #if defined(CONFIG_OMAP34XX) |
763 | /* | |
764 | * Silicon revs 2.1 and older do not support multiblock transfers. | |
765 | */ | |
766 | if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) | |
93bfd616 | 767 | cfg->b_max = 1; |
4ca9244d | 768 | #endif |
ae000e23 | 769 | mmc = mmc_create(cfg, priv); |
93bfd616 PA |
770 | if (mmc == NULL) |
771 | return -1; | |
de941241 SG |
772 | |
773 | return 0; | |
774 | } | |
a9d6a7e2 M |
775 | #else |
776 | static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) | |
777 | { | |
778 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
3d673ffc JJH |
779 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); |
780 | struct mmc_config *cfg = &plat->cfg; | |
a9d6a7e2 | 781 | const void *fdt = gd->fdt_blob; |
e160f7d4 | 782 | int node = dev_of_offset(dev); |
a9d6a7e2 M |
783 | int val; |
784 | ||
4bc5e19e M |
785 | priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *), |
786 | MAP_NOCACHE); | |
a9d6a7e2 M |
787 | |
788 | cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; | |
789 | val = fdtdec_get_int(fdt, node, "bus-width", -1); | |
790 | if (val < 0) { | |
791 | printf("error: bus-width property missing\n"); | |
792 | return -ENOENT; | |
793 | } | |
794 | ||
795 | switch (val) { | |
796 | case 0x8: | |
797 | cfg->host_caps |= MMC_MODE_8BIT; | |
798 | case 0x4: | |
799 | cfg->host_caps |= MMC_MODE_4BIT; | |
800 | break; | |
801 | default: | |
802 | printf("error: invalid bus-width property\n"); | |
803 | return -ENOENT; | |
804 | } | |
805 | ||
806 | cfg->f_min = 400000; | |
807 | cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000); | |
808 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
809 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; | |
810 | ||
4de2de51 | 811 | #ifdef OMAP_HSMMC_USE_GPIO |
a9d6a7e2 | 812 | priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); |
4de2de51 | 813 | #endif |
a9d6a7e2 M |
814 | |
815 | return 0; | |
816 | } | |
817 | ||
17c9a1c1 JJH |
818 | #ifdef CONFIG_BLK |
819 | ||
820 | static int omap_hsmmc_bind(struct udevice *dev) | |
821 | { | |
822 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); | |
823 | ||
824 | return mmc_bind(dev, &plat->mmc, &plat->cfg); | |
825 | } | |
826 | #endif | |
a9d6a7e2 M |
827 | static int omap_hsmmc_probe(struct udevice *dev) |
828 | { | |
3d673ffc | 829 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); |
a9d6a7e2 M |
830 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
831 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
3d673ffc | 832 | struct mmc_config *cfg = &plat->cfg; |
a9d6a7e2 M |
833 | struct mmc *mmc; |
834 | ||
a9d6a7e2 M |
835 | cfg->name = "OMAP SD/MMC"; |
836 | cfg->ops = &omap_hsmmc_ops; | |
837 | ||
17c9a1c1 JJH |
838 | #ifdef CONFIG_BLK |
839 | mmc = &plat->mmc; | |
840 | #else | |
a9d6a7e2 M |
841 | mmc = mmc_create(cfg, priv); |
842 | if (mmc == NULL) | |
843 | return -1; | |
17c9a1c1 | 844 | #endif |
a9d6a7e2 | 845 | |
5cc6a245 M |
846 | #ifdef OMAP_HSMMC_USE_GPIO |
847 | gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); | |
848 | gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); | |
849 | #endif | |
850 | ||
cffe5d86 | 851 | mmc->dev = dev; |
a9d6a7e2 M |
852 | upriv->mmc = mmc; |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
857 | static const struct udevice_id omap_hsmmc_ids[] = { | |
858 | { .compatible = "ti,omap3-hsmmc" }, | |
859 | { .compatible = "ti,omap4-hsmmc" }, | |
860 | { .compatible = "ti,am33xx-hsmmc" }, | |
861 | { } | |
862 | }; | |
863 | ||
864 | U_BOOT_DRIVER(omap_hsmmc) = { | |
865 | .name = "omap_hsmmc", | |
866 | .id = UCLASS_MMC, | |
867 | .of_match = omap_hsmmc_ids, | |
868 | .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata, | |
17c9a1c1 JJH |
869 | #ifdef CONFIG_BLK |
870 | .bind = omap_hsmmc_bind, | |
871 | #endif | |
a9d6a7e2 M |
872 | .probe = omap_hsmmc_probe, |
873 | .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), | |
3d673ffc | 874 | .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat), |
a9d6a7e2 M |
875 | }; |
876 | #endif |