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0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
4 | * (C) Copyright 2008 Armadeus Systems nc | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <malloc.h> | |
26 | #include <net.h> | |
27 | #include <miiphy.h> | |
28 | #include "fec_mxc.h" | |
29 | ||
30 | #include <asm/arch/clock.h> | |
31 | #include <asm/arch/imx-regs.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/errno.h> | |
34 | ||
35 | DECLARE_GLOBAL_DATA_PTR; | |
36 | ||
37 | #ifndef CONFIG_MII | |
38 | #error "CONFIG_MII has to be defined!" | |
39 | #endif | |
40 | ||
5c1ad3e6 EN |
41 | #ifndef CONFIG_FEC_XCV_TYPE |
42 | #define CONFIG_FEC_XCV_TYPE MII100 | |
392b8502 MV |
43 | #endif |
44 | ||
be7e87e2 MV |
45 | /* |
46 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
47 | * sending and after receiving. | |
48 | */ | |
5c1ad3e6 EN |
49 | #ifdef CONFIG_MX28 |
50 | #define CONFIG_FEC_MXC_SWAP_PACKET | |
51 | #endif | |
52 | ||
53 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) | |
54 | ||
55 | /* Check various alignment issues at compile time */ | |
56 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) | |
57 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" | |
58 | #endif | |
59 | ||
60 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ | |
61 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) | |
62 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" | |
be7e87e2 MV |
63 | #endif |
64 | ||
0b23fb36 IY |
65 | #undef DEBUG |
66 | ||
67 | struct nbuf { | |
68 | uint8_t data[1500]; /**< actual data */ | |
69 | int length; /**< actual length */ | |
70 | int used; /**< buffer in use or not */ | |
71 | uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ | |
72 | }; | |
73 | ||
5c1ad3e6 | 74 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
75 | static void swap_packet(uint32_t *packet, int length) |
76 | { | |
77 | int i; | |
78 | ||
79 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
80 | packet[i] = __swab32(packet[i]); | |
81 | } | |
82 | #endif | |
83 | ||
0b23fb36 IY |
84 | /* |
85 | * MII-interface related functions | |
86 | */ | |
13947f43 TK |
87 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, |
88 | uint8_t regAddr) | |
0b23fb36 | 89 | { |
0b23fb36 IY |
90 | uint32_t reg; /* convenient holder for the PHY register */ |
91 | uint32_t phy; /* convenient holder for the PHY */ | |
92 | uint32_t start; | |
13947f43 | 93 | int val; |
0b23fb36 IY |
94 | |
95 | /* | |
96 | * reading from any PHY's register is done by properly | |
97 | * programming the FEC's MII data register. | |
98 | */ | |
d133b881 | 99 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
100 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; |
101 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
102 | ||
103 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 104 | phy | reg, ð->mii_data); |
0b23fb36 IY |
105 | |
106 | /* | |
107 | * wait for the related interrupt | |
108 | */ | |
a60d1e5b | 109 | start = get_timer(0); |
d133b881 | 110 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
111 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
112 | printf("Read MDIO failed...\n"); | |
113 | return -1; | |
114 | } | |
115 | } | |
116 | ||
117 | /* | |
118 | * clear mii interrupt bit | |
119 | */ | |
d133b881 | 120 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
121 | |
122 | /* | |
123 | * it's now safe to read the PHY's register | |
124 | */ | |
13947f43 TK |
125 | val = (unsigned short)readl(ð->mii_data); |
126 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, | |
127 | regAddr, val); | |
128 | return val; | |
0b23fb36 IY |
129 | } |
130 | ||
4294b248 SB |
131 | static void fec_mii_setspeed(struct fec_priv *fec) |
132 | { | |
133 | /* | |
134 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
135 | * and do not drop the Preamble. | |
136 | */ | |
137 | writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, | |
138 | &fec->eth->mii_speed); | |
13947f43 | 139 | debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed)); |
4294b248 | 140 | } |
0b23fb36 | 141 | |
13947f43 TK |
142 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, |
143 | uint8_t regAddr, uint16_t data) | |
144 | { | |
0b23fb36 IY |
145 | uint32_t reg; /* convenient holder for the PHY register */ |
146 | uint32_t phy; /* convenient holder for the PHY */ | |
147 | uint32_t start; | |
148 | ||
149 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; | |
150 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
151 | ||
152 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 153 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 IY |
154 | |
155 | /* | |
156 | * wait for the MII interrupt | |
157 | */ | |
a60d1e5b | 158 | start = get_timer(0); |
d133b881 | 159 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
160 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
161 | printf("Write MDIO failed...\n"); | |
162 | return -1; | |
163 | } | |
164 | } | |
165 | ||
166 | /* | |
167 | * clear MII interrupt bit | |
168 | */ | |
d133b881 | 169 | writel(FEC_IEVENT_MII, ð->ievent); |
13947f43 | 170 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, |
0b23fb36 IY |
171 | regAddr, data); |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
13947f43 TK |
176 | int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr) |
177 | { | |
178 | return fec_mdio_read(bus->priv, phyAddr, regAddr); | |
179 | } | |
180 | ||
181 | int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr, | |
182 | u16 data) | |
183 | { | |
184 | return fec_mdio_write(bus->priv, phyAddr, regAddr, data); | |
185 | } | |
186 | ||
187 | #ifndef CONFIG_PHYLIB | |
0b23fb36 IY |
188 | static int miiphy_restart_aneg(struct eth_device *dev) |
189 | { | |
b774fe9d SB |
190 | int ret = 0; |
191 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) | |
9e27e9dc | 192 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 193 | struct ethernet_regs *eth = fec->bus->priv; |
9e27e9dc | 194 | |
0b23fb36 IY |
195 | /* |
196 | * Wake up from sleep if necessary | |
197 | * Reset PHY, then delay 300ns | |
198 | */ | |
cb17b92d | 199 | #ifdef CONFIG_MX27 |
13947f43 | 200 | fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); |
cb17b92d | 201 | #endif |
13947f43 | 202 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
0b23fb36 IY |
203 | udelay(1000); |
204 | ||
205 | /* | |
206 | * Set the auto-negotiation advertisement register bits | |
207 | */ | |
13947f43 | 208 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
8ef583a0 MF |
209 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
210 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
13947f43 | 211 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
8ef583a0 | 212 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
213 | |
214 | if (fec->mii_postcall) | |
215 | ret = fec->mii_postcall(fec->phy_id); | |
216 | ||
b774fe9d | 217 | #endif |
2e5f4421 | 218 | return ret; |
0b23fb36 IY |
219 | } |
220 | ||
221 | static int miiphy_wait_aneg(struct eth_device *dev) | |
222 | { | |
223 | uint32_t start; | |
13947f43 | 224 | int status; |
9e27e9dc | 225 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 226 | struct ethernet_regs *eth = fec->bus->priv; |
0b23fb36 IY |
227 | |
228 | /* | |
229 | * Wait for AN completion | |
230 | */ | |
a60d1e5b | 231 | start = get_timer(0); |
0b23fb36 IY |
232 | do { |
233 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
234 | printf("%s: Autonegotiation timeout\n", dev->name); | |
235 | return -1; | |
236 | } | |
237 | ||
13947f43 TK |
238 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
239 | if (status < 0) { | |
240 | printf("%s: Autonegotiation failed. status: %d\n", | |
0b23fb36 IY |
241 | dev->name, status); |
242 | return -1; | |
243 | } | |
8ef583a0 | 244 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
245 | |
246 | return 0; | |
247 | } | |
13947f43 TK |
248 | #endif |
249 | ||
0b23fb36 IY |
250 | static int fec_rx_task_enable(struct fec_priv *fec) |
251 | { | |
252 | writel(1 << 24, &fec->eth->r_des_active); | |
253 | return 0; | |
254 | } | |
255 | ||
256 | static int fec_rx_task_disable(struct fec_priv *fec) | |
257 | { | |
258 | return 0; | |
259 | } | |
260 | ||
261 | static int fec_tx_task_enable(struct fec_priv *fec) | |
262 | { | |
263 | writel(1 << 24, &fec->eth->x_des_active); | |
264 | return 0; | |
265 | } | |
266 | ||
267 | static int fec_tx_task_disable(struct fec_priv *fec) | |
268 | { | |
269 | return 0; | |
270 | } | |
271 | ||
272 | /** | |
273 | * Initialize receive task's buffer descriptors | |
274 | * @param[in] fec all we know about the device yet | |
275 | * @param[in] count receive buffer count to be allocated | |
5c1ad3e6 | 276 | * @param[in] dsize desired size of each receive buffer |
0b23fb36 IY |
277 | * @return 0 on success |
278 | * | |
279 | * For this task we need additional memory for the data buffers. And each | |
280 | * data buffer requires some alignment. Thy must be aligned to a specific | |
5c1ad3e6 | 281 | * boundary each. |
0b23fb36 | 282 | */ |
5c1ad3e6 | 283 | static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
0b23fb36 | 284 | { |
5c1ad3e6 EN |
285 | uint32_t size; |
286 | int i; | |
287 | ||
0b23fb36 | 288 | /* |
5c1ad3e6 EN |
289 | * Allocate memory for the buffers. This allocation respects the |
290 | * alignment | |
0b23fb36 | 291 | */ |
5c1ad3e6 EN |
292 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
293 | for (i = 0; i < count; i++) { | |
294 | uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); | |
295 | if (data_ptr == 0) { | |
296 | uint8_t *data = memalign(ARCH_DMA_MINALIGN, | |
297 | size); | |
298 | if (!data) { | |
299 | printf("%s: error allocating rxbuf %d\n", | |
300 | __func__, i); | |
301 | goto err; | |
302 | } | |
303 | writel((uint32_t)data, &fec->rbd_base[i].data_pointer); | |
304 | } /* needs allocation */ | |
305 | writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status); | |
306 | writew(0, &fec->rbd_base[i].data_length); | |
307 | } | |
308 | ||
309 | /* Mark the last RBD to close the ring. */ | |
310 | writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status); | |
0b23fb36 IY |
311 | fec->rbd_index = 0; |
312 | ||
313 | return 0; | |
5c1ad3e6 EN |
314 | |
315 | err: | |
316 | for (; i >= 0; i--) { | |
317 | uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); | |
318 | free((void *)data_ptr); | |
319 | } | |
320 | ||
321 | return -ENOMEM; | |
0b23fb36 IY |
322 | } |
323 | ||
324 | /** | |
325 | * Initialize transmit task's buffer descriptors | |
326 | * @param[in] fec all we know about the device yet | |
327 | * | |
328 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
329 | * Note: There is a race condition in the hardware. When only one BD is in | |
330 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
331 | * This bit in combination with the READY bit results into double transmit | |
332 | * of each data buffer. It seems the state machine checks READY earlier then | |
333 | * resetting it after the first transfer. | |
334 | * Using two BDs solves this issue. | |
335 | */ | |
336 | static void fec_tbd_init(struct fec_priv *fec) | |
337 | { | |
5c1ad3e6 EN |
338 | unsigned addr = (unsigned)fec->tbd_base; |
339 | unsigned size = roundup(2 * sizeof(struct fec_bd), | |
340 | ARCH_DMA_MINALIGN); | |
0b23fb36 IY |
341 | writew(0x0000, &fec->tbd_base[0].status); |
342 | writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); | |
343 | fec->tbd_index = 0; | |
5c1ad3e6 | 344 | flush_dcache_range(addr, addr+size); |
0b23fb36 IY |
345 | } |
346 | ||
347 | /** | |
348 | * Mark the given read buffer descriptor as free | |
349 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
350 | * @param[in] pRbd buffer descriptor to mark free again | |
351 | */ | |
352 | static void fec_rbd_clean(int last, struct fec_bd *pRbd) | |
353 | { | |
5c1ad3e6 | 354 | unsigned short flags = FEC_RBD_EMPTY; |
0b23fb36 | 355 | if (last) |
5c1ad3e6 EN |
356 | flags |= FEC_RBD_WRAP; |
357 | writew(flags, &pRbd->status); | |
0b23fb36 IY |
358 | writew(0, &pRbd->data_length); |
359 | } | |
360 | ||
be252b65 FE |
361 | static int fec_get_hwaddr(struct eth_device *dev, int dev_id, |
362 | unsigned char *mac) | |
0b23fb36 | 363 | { |
be252b65 | 364 | imx_get_mac_from_fuse(dev_id, mac); |
2e236bf2 | 365 | return !is_valid_ether_addr(mac); |
0b23fb36 IY |
366 | } |
367 | ||
4294b248 | 368 | static int fec_set_hwaddr(struct eth_device *dev) |
0b23fb36 | 369 | { |
4294b248 | 370 | uchar *mac = dev->enetaddr; |
0b23fb36 IY |
371 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
372 | ||
373 | writel(0, &fec->eth->iaddr1); | |
374 | writel(0, &fec->eth->iaddr2); | |
375 | writel(0, &fec->eth->gaddr1); | |
376 | writel(0, &fec->eth->gaddr2); | |
377 | ||
378 | /* | |
379 | * Set physical address | |
380 | */ | |
381 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], | |
382 | &fec->eth->paddr1); | |
383 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); | |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
13947f43 TK |
388 | static void fec_eth_phy_config(struct eth_device *dev) |
389 | { | |
390 | #ifdef CONFIG_PHYLIB | |
391 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
392 | struct phy_device *phydev; | |
393 | ||
394 | phydev = phy_connect(fec->bus, fec->phy_id, dev, | |
395 | PHY_INTERFACE_MODE_RGMII); | |
396 | if (phydev) { | |
397 | fec->phydev = phydev; | |
398 | phy_config(phydev); | |
399 | } | |
400 | #endif | |
401 | } | |
402 | ||
a5990b26 MV |
403 | /* |
404 | * Do initial configuration of the FEC registers | |
405 | */ | |
406 | static void fec_reg_setup(struct fec_priv *fec) | |
407 | { | |
408 | uint32_t rcntrl; | |
409 | ||
410 | /* | |
411 | * Set interrupt mask register | |
412 | */ | |
413 | writel(0x00000000, &fec->eth->imask); | |
414 | ||
415 | /* | |
416 | * Clear FEC-Lite interrupt event register(IEVENT) | |
417 | */ | |
418 | writel(0xffffffff, &fec->eth->ievent); | |
419 | ||
420 | ||
421 | /* | |
422 | * Set FEC-Lite receive control register(R_CNTRL): | |
423 | */ | |
424 | ||
425 | /* Start with frame length = 1518, common for all modes. */ | |
426 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
427 | if (fec->xcv_type == SEVENWIRE) | |
428 | rcntrl |= FEC_RCNTRL_FCE; | |
429 | else if (fec->xcv_type == RGMII) | |
430 | rcntrl |= FEC_RCNTRL_RGMII; | |
431 | else if (fec->xcv_type == RMII) | |
432 | rcntrl |= FEC_RCNTRL_RMII; | |
433 | else /* MII mode */ | |
434 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
435 | ||
436 | writel(rcntrl, &fec->eth->r_cntrl); | |
437 | } | |
438 | ||
0b23fb36 IY |
439 | /** |
440 | * Start the FEC engine | |
441 | * @param[in] dev Our device to handle | |
442 | */ | |
443 | static int fec_open(struct eth_device *edev) | |
444 | { | |
445 | struct fec_priv *fec = (struct fec_priv *)edev->priv; | |
28774cba | 446 | int speed; |
5c1ad3e6 EN |
447 | uint32_t addr, size; |
448 | int i; | |
0b23fb36 IY |
449 | |
450 | debug("fec_open: fec_open(dev)\n"); | |
451 | /* full-duplex, heartbeat disabled */ | |
452 | writel(1 << 2, &fec->eth->x_cntrl); | |
453 | fec->rbd_index = 0; | |
454 | ||
5c1ad3e6 EN |
455 | /* Invalidate all descriptors */ |
456 | for (i = 0; i < FEC_RBD_NUM - 1; i++) | |
457 | fec_rbd_clean(0, &fec->rbd_base[i]); | |
458 | fec_rbd_clean(1, &fec->rbd_base[i]); | |
459 | ||
460 | /* Flush the descriptors into RAM */ | |
461 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
462 | ARCH_DMA_MINALIGN); | |
463 | addr = (uint32_t)fec->rbd_base; | |
464 | flush_dcache_range(addr, addr + size); | |
465 | ||
28774cba | 466 | #ifdef FEC_QUIRK_ENET_MAC |
2ef2b950 JL |
467 | /* Enable ENET HW endian SWAP */ |
468 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
469 | &fec->eth->ecntrl); | |
470 | /* Enable ENET store and forward mode */ | |
471 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
472 | &fec->eth->x_wmrk); | |
473 | #endif | |
0b23fb36 IY |
474 | /* |
475 | * Enable FEC-Lite controller | |
476 | */ | |
cb17b92d JR |
477 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
478 | &fec->eth->ecntrl); | |
96912453 | 479 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) |
740d6ae5 JR |
480 | udelay(100); |
481 | /* | |
482 | * setup the MII gasket for RMII mode | |
483 | */ | |
484 | ||
485 | /* disable the gasket */ | |
486 | writew(0, &fec->eth->miigsk_enr); | |
487 | ||
488 | /* wait for the gasket to be disabled */ | |
489 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
490 | udelay(2); | |
491 | ||
492 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
493 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
494 | ||
495 | /* re-enable the gasket */ | |
496 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
497 | ||
498 | /* wait until MII gasket is ready */ | |
499 | int max_loops = 10; | |
500 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
501 | if (--max_loops <= 0) { | |
502 | printf("WAIT for MII Gasket ready timed out\n"); | |
503 | break; | |
504 | } | |
505 | } | |
506 | #endif | |
0b23fb36 | 507 | |
13947f43 TK |
508 | #ifdef CONFIG_PHYLIB |
509 | if (!fec->phydev) | |
510 | fec_eth_phy_config(edev); | |
511 | if (fec->phydev) { | |
512 | /* Start up the PHY */ | |
513 | phy_startup(fec->phydev); | |
514 | speed = fec->phydev->speed; | |
515 | } else { | |
516 | speed = _100BASET; | |
517 | } | |
518 | #else | |
0b23fb36 | 519 | miiphy_wait_aneg(edev); |
28774cba | 520 | speed = miiphy_speed(edev->name, fec->phy_id); |
9e27e9dc | 521 | miiphy_duplex(edev->name, fec->phy_id); |
13947f43 | 522 | #endif |
0b23fb36 | 523 | |
28774cba TK |
524 | #ifdef FEC_QUIRK_ENET_MAC |
525 | { | |
526 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; | |
527 | u32 rcr = (readl(&fec->eth->r_cntrl) & | |
528 | ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | | |
529 | FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; | |
530 | if (speed == _1000BASET) | |
531 | ecr |= FEC_ECNTRL_SPEED; | |
532 | else if (speed != _100BASET) | |
533 | rcr |= FEC_RCNTRL_RMII_10T; | |
534 | writel(ecr, &fec->eth->ecntrl); | |
535 | writel(rcr, &fec->eth->r_cntrl); | |
536 | } | |
537 | #endif | |
538 | debug("%s:Speed=%i\n", __func__, speed); | |
539 | ||
0b23fb36 IY |
540 | /* |
541 | * Enable SmartDMA receive task | |
542 | */ | |
543 | fec_rx_task_enable(fec); | |
544 | ||
545 | udelay(100000); | |
546 | return 0; | |
547 | } | |
548 | ||
549 | static int fec_init(struct eth_device *dev, bd_t* bd) | |
550 | { | |
0b23fb36 | 551 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
9e27e9dc | 552 | uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; |
5c1ad3e6 EN |
553 | uint32_t size; |
554 | int i, ret; | |
0b23fb36 | 555 | |
e9319f11 JR |
556 | /* Initialize MAC address */ |
557 | fec_set_hwaddr(dev); | |
558 | ||
0b23fb36 | 559 | /* |
5c1ad3e6 EN |
560 | * Allocate transmit descriptors, there are two in total. This |
561 | * allocation respects cache alignment. | |
0b23fb36 | 562 | */ |
5c1ad3e6 EN |
563 | if (!fec->tbd_base) { |
564 | size = roundup(2 * sizeof(struct fec_bd), | |
565 | ARCH_DMA_MINALIGN); | |
566 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
567 | if (!fec->tbd_base) { | |
568 | ret = -ENOMEM; | |
569 | goto err1; | |
570 | } | |
571 | memset(fec->tbd_base, 0, size); | |
572 | fec_tbd_init(fec); | |
573 | flush_dcache_range((unsigned)fec->tbd_base, size); | |
0b23fb36 | 574 | } |
0b23fb36 | 575 | |
5c1ad3e6 EN |
576 | /* |
577 | * Allocate receive descriptors. This allocation respects cache | |
578 | * alignment. | |
579 | */ | |
580 | if (!fec->rbd_base) { | |
581 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
582 | ARCH_DMA_MINALIGN); | |
583 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
584 | if (!fec->rbd_base) { | |
585 | ret = -ENOMEM; | |
586 | goto err2; | |
587 | } | |
588 | memset(fec->rbd_base, 0, size); | |
589 | /* | |
590 | * Initialize RxBD ring | |
591 | */ | |
592 | if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { | |
593 | ret = -ENOMEM; | |
594 | goto err3; | |
595 | } | |
596 | flush_dcache_range((unsigned)fec->rbd_base, | |
597 | (unsigned)fec->rbd_base + size); | |
598 | } | |
0b23fb36 | 599 | |
a5990b26 | 600 | fec_reg_setup(fec); |
9eb3770b MV |
601 | |
602 | if (fec->xcv_type == MII10 || fec->xcv_type == MII100) | |
4294b248 | 603 | fec_mii_setspeed(fec); |
9eb3770b | 604 | |
0b23fb36 IY |
605 | /* |
606 | * Set Opcode/Pause Duration Register | |
607 | */ | |
608 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ | |
609 | writel(0x2, &fec->eth->x_wmrk); | |
610 | /* | |
611 | * Set multicast address filter | |
612 | */ | |
613 | writel(0x00000000, &fec->eth->gaddr1); | |
614 | writel(0x00000000, &fec->eth->gaddr2); | |
615 | ||
616 | ||
617 | /* clear MIB RAM */ | |
9e27e9dc MV |
618 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) |
619 | writel(0, i); | |
0b23fb36 IY |
620 | |
621 | /* FIFO receive start register */ | |
622 | writel(0x520, &fec->eth->r_fstart); | |
623 | ||
624 | /* size and address of each buffer */ | |
625 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
626 | writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); | |
627 | writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); | |
628 | ||
13947f43 | 629 | #ifndef CONFIG_PHYLIB |
0b23fb36 IY |
630 | if (fec->xcv_type != SEVENWIRE) |
631 | miiphy_restart_aneg(dev); | |
13947f43 | 632 | #endif |
0b23fb36 IY |
633 | fec_open(dev); |
634 | return 0; | |
5c1ad3e6 EN |
635 | |
636 | err3: | |
637 | free(fec->rbd_base); | |
638 | err2: | |
639 | free(fec->tbd_base); | |
640 | err1: | |
641 | return ret; | |
0b23fb36 IY |
642 | } |
643 | ||
644 | /** | |
645 | * Halt the FEC engine | |
646 | * @param[in] dev Our device to handle | |
647 | */ | |
648 | static void fec_halt(struct eth_device *dev) | |
649 | { | |
9e27e9dc | 650 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
0b23fb36 IY |
651 | int counter = 0xffff; |
652 | ||
653 | /* | |
654 | * issue graceful stop command to the FEC transmitter if necessary | |
655 | */ | |
cb17b92d | 656 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
0b23fb36 IY |
657 | &fec->eth->x_cntrl); |
658 | ||
659 | debug("eth_halt: wait for stop regs\n"); | |
660 | /* | |
661 | * wait for graceful stop to register | |
662 | */ | |
663 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) | |
cb17b92d | 664 | udelay(1); |
0b23fb36 IY |
665 | |
666 | /* | |
667 | * Disable SmartDMA tasks | |
668 | */ | |
669 | fec_tx_task_disable(fec); | |
670 | fec_rx_task_disable(fec); | |
671 | ||
672 | /* | |
673 | * Disable the Ethernet Controller | |
674 | * Note: this will also reset the BD index counter! | |
675 | */ | |
740d6ae5 JR |
676 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
677 | &fec->eth->ecntrl); | |
0b23fb36 IY |
678 | fec->rbd_index = 0; |
679 | fec->tbd_index = 0; | |
0b23fb36 IY |
680 | debug("eth_halt: done\n"); |
681 | } | |
682 | ||
683 | /** | |
684 | * Transmit one frame | |
685 | * @param[in] dev Our ethernet device to handle | |
686 | * @param[in] packet Pointer to the data to be transmitted | |
687 | * @param[in] length Data count in bytes | |
688 | * @return 0 on success | |
689 | */ | |
442dac4c | 690 | static int fec_send(struct eth_device *dev, void *packet, int length) |
0b23fb36 IY |
691 | { |
692 | unsigned int status; | |
5c1ad3e6 EN |
693 | uint32_t size; |
694 | uint32_t addr; | |
0b23fb36 IY |
695 | |
696 | /* | |
697 | * This routine transmits one frame. This routine only accepts | |
698 | * 6-byte Ethernet addresses. | |
699 | */ | |
700 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
701 | ||
702 | /* | |
703 | * Check for valid length of data. | |
704 | */ | |
705 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 706 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
707 | return -1; |
708 | } | |
709 | ||
710 | /* | |
5c1ad3e6 EN |
711 | * Setup the transmit buffer. We are always using the first buffer for |
712 | * transmission, the second will be empty and only used to stop the DMA | |
713 | * engine. We also flush the packet to RAM here to avoid cache trouble. | |
0b23fb36 | 714 | */ |
5c1ad3e6 | 715 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
716 | swap_packet((uint32_t *)packet, length); |
717 | #endif | |
5c1ad3e6 EN |
718 | |
719 | addr = (uint32_t)packet; | |
720 | size = roundup(length, ARCH_DMA_MINALIGN); | |
721 | flush_dcache_range(addr, addr + size); | |
722 | ||
0b23fb36 | 723 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
5c1ad3e6 EN |
724 | writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
725 | ||
0b23fb36 IY |
726 | /* |
727 | * update BD's status now | |
728 | * This block: | |
729 | * - is always the last in a chain (means no chain) | |
730 | * - should transmitt the CRC | |
731 | * - might be the last BD in the list, so the address counter should | |
732 | * wrap (-> keep the WRAP flag) | |
733 | */ | |
734 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
735 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
736 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
737 | ||
5c1ad3e6 EN |
738 | /* |
739 | * Flush data cache. This code flushes both TX descriptors to RAM. | |
740 | * After this code, the descriptors will be safely in RAM and we | |
741 | * can start DMA. | |
742 | */ | |
743 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
744 | addr = (uint32_t)fec->tbd_base; | |
745 | flush_dcache_range(addr, addr + size); | |
746 | ||
0b23fb36 IY |
747 | /* |
748 | * Enable SmartDMA transmit task | |
749 | */ | |
750 | fec_tx_task_enable(fec); | |
751 | ||
752 | /* | |
5c1ad3e6 EN |
753 | * Wait until frame is sent. On each turn of the wait cycle, we must |
754 | * invalidate data cache to see what's really in RAM. Also, we need | |
755 | * barrier here. | |
0b23fb36 | 756 | */ |
5c1ad3e6 | 757 | invalidate_dcache_range(addr, addr + size); |
0b23fb36 | 758 | while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { |
cb17b92d | 759 | udelay(1); |
5c1ad3e6 | 760 | invalidate_dcache_range(addr, addr + size); |
0b23fb36 | 761 | } |
5c1ad3e6 | 762 | |
0b23fb36 IY |
763 | debug("fec_send: status 0x%x index %d\n", |
764 | readw(&fec->tbd_base[fec->tbd_index].status), | |
765 | fec->tbd_index); | |
766 | /* for next transmission use the other buffer */ | |
767 | if (fec->tbd_index) | |
768 | fec->tbd_index = 0; | |
769 | else | |
770 | fec->tbd_index = 1; | |
771 | ||
772 | return 0; | |
773 | } | |
774 | ||
775 | /** | |
776 | * Pull one frame from the card | |
777 | * @param[in] dev Our ethernet device to handle | |
778 | * @return Length of packet read | |
779 | */ | |
780 | static int fec_recv(struct eth_device *dev) | |
781 | { | |
782 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
783 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; | |
784 | unsigned long ievent; | |
785 | int frame_length, len = 0; | |
786 | struct nbuf *frame; | |
787 | uint16_t bd_status; | |
5c1ad3e6 EN |
788 | uint32_t addr, size; |
789 | int i; | |
0b23fb36 IY |
790 | uchar buff[FEC_MAX_PKT_SIZE]; |
791 | ||
792 | /* | |
793 | * Check if any critical events have happened | |
794 | */ | |
795 | ievent = readl(&fec->eth->ievent); | |
796 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 797 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 IY |
798 | if (ievent & FEC_IEVENT_BABR) { |
799 | fec_halt(dev); | |
800 | fec_init(dev, fec->bd); | |
801 | printf("some error: 0x%08lx\n", ievent); | |
802 | return 0; | |
803 | } | |
804 | if (ievent & FEC_IEVENT_HBERR) { | |
805 | /* Heartbeat error */ | |
806 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
807 | &fec->eth->x_cntrl); | |
808 | } | |
809 | if (ievent & FEC_IEVENT_GRA) { | |
810 | /* Graceful stop complete */ | |
811 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
812 | fec_halt(dev); | |
813 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), | |
814 | &fec->eth->x_cntrl); | |
815 | fec_init(dev, fec->bd); | |
816 | } | |
817 | } | |
818 | ||
819 | /* | |
5c1ad3e6 EN |
820 | * Read the buffer status. Before the status can be read, the data cache |
821 | * must be invalidated, because the data in RAM might have been changed | |
822 | * by DMA. The descriptors are properly aligned to cachelines so there's | |
823 | * no need to worry they'd overlap. | |
824 | * | |
825 | * WARNING: By invalidating the descriptor here, we also invalidate | |
826 | * the descriptors surrounding this one. Therefore we can NOT change the | |
827 | * contents of this descriptor nor the surrounding ones. The problem is | |
828 | * that in order to mark the descriptor as processed, we need to change | |
829 | * the descriptor. The solution is to mark the whole cache line when all | |
830 | * descriptors in the cache line are processed. | |
0b23fb36 | 831 | */ |
5c1ad3e6 EN |
832 | addr = (uint32_t)rbd; |
833 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
834 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
835 | invalidate_dcache_range(addr, addr + size); | |
836 | ||
0b23fb36 IY |
837 | bd_status = readw(&rbd->status); |
838 | debug("fec_recv: status 0x%x\n", bd_status); | |
839 | ||
840 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
841 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
842 | ((readw(&rbd->data_length) - 4) > 14)) { | |
843 | /* | |
844 | * Get buffer address and size | |
845 | */ | |
846 | frame = (struct nbuf *)readl(&rbd->data_pointer); | |
847 | frame_length = readw(&rbd->data_length) - 4; | |
5c1ad3e6 EN |
848 | /* |
849 | * Invalidate data cache over the buffer | |
850 | */ | |
851 | addr = (uint32_t)frame; | |
852 | size = roundup(frame_length, ARCH_DMA_MINALIGN); | |
853 | invalidate_dcache_range(addr, addr + size); | |
854 | ||
0b23fb36 IY |
855 | /* |
856 | * Fill the buffer and pass it to upper layers | |
857 | */ | |
5c1ad3e6 | 858 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
859 | swap_packet((uint32_t *)frame->data, frame_length); |
860 | #endif | |
0b23fb36 IY |
861 | memcpy(buff, frame->data, frame_length); |
862 | NetReceive(buff, frame_length); | |
863 | len = frame_length; | |
864 | } else { | |
865 | if (bd_status & FEC_RBD_ERR) | |
866 | printf("error frame: 0x%08lx 0x%08x\n", | |
867 | (ulong)rbd->data_pointer, | |
868 | bd_status); | |
869 | } | |
5c1ad3e6 | 870 | |
0b23fb36 | 871 | /* |
5c1ad3e6 EN |
872 | * Free the current buffer, restart the engine and move forward |
873 | * to the next buffer. Here we check if the whole cacheline of | |
874 | * descriptors was already processed and if so, we mark it free | |
875 | * as whole. | |
0b23fb36 | 876 | */ |
5c1ad3e6 EN |
877 | size = RXDESC_PER_CACHELINE - 1; |
878 | if ((fec->rbd_index & size) == size) { | |
879 | i = fec->rbd_index - size; | |
880 | addr = (uint32_t)&fec->rbd_base[i]; | |
881 | for (; i <= fec->rbd_index ; i++) { | |
882 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), | |
883 | &fec->rbd_base[i]); | |
884 | } | |
885 | flush_dcache_range(addr, | |
886 | addr + ARCH_DMA_MINALIGN); | |
887 | } | |
888 | ||
0b23fb36 IY |
889 | fec_rx_task_enable(fec); |
890 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
891 | } | |
892 | debug("fec_recv: stop\n"); | |
893 | ||
894 | return len; | |
895 | } | |
896 | ||
9e27e9dc | 897 | static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) |
0b23fb36 | 898 | { |
0b23fb36 | 899 | struct eth_device *edev; |
9e27e9dc | 900 | struct fec_priv *fec; |
13947f43 | 901 | struct mii_dev *bus; |
0b23fb36 | 902 | unsigned char ethaddr[6]; |
e382fb48 MV |
903 | uint32_t start; |
904 | int ret = 0; | |
0b23fb36 IY |
905 | |
906 | /* create and fill edev struct */ | |
907 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
908 | if (!edev) { | |
9e27e9dc | 909 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
e382fb48 MV |
910 | ret = -ENOMEM; |
911 | goto err1; | |
9e27e9dc MV |
912 | } |
913 | ||
914 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); | |
915 | if (!fec) { | |
916 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); | |
e382fb48 MV |
917 | ret = -ENOMEM; |
918 | goto err2; | |
0b23fb36 | 919 | } |
9e27e9dc | 920 | |
de0b9576 | 921 | memset(edev, 0, sizeof(*edev)); |
9e27e9dc MV |
922 | memset(fec, 0, sizeof(*fec)); |
923 | ||
0b23fb36 IY |
924 | edev->priv = fec; |
925 | edev->init = fec_init; | |
926 | edev->send = fec_send; | |
927 | edev->recv = fec_recv; | |
928 | edev->halt = fec_halt; | |
fb57ec97 | 929 | edev->write_hwaddr = fec_set_hwaddr; |
0b23fb36 | 930 | |
9e27e9dc | 931 | fec->eth = (struct ethernet_regs *)base_addr; |
0b23fb36 IY |
932 | fec->bd = bd; |
933 | ||
392b8502 | 934 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
0b23fb36 IY |
935 | |
936 | /* Reset chip. */ | |
cb17b92d | 937 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
e382fb48 MV |
938 | start = get_timer(0); |
939 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
940 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
941 | printf("FEC MXC: Timeout reseting chip\n"); | |
942 | goto err3; | |
943 | } | |
0b23fb36 | 944 | udelay(10); |
e382fb48 | 945 | } |
0b23fb36 | 946 | |
a5990b26 | 947 | fec_reg_setup(fec); |
4294b248 | 948 | fec_mii_setspeed(fec); |
0b23fb36 | 949 | |
9e27e9dc MV |
950 | if (dev_id == -1) { |
951 | sprintf(edev->name, "FEC"); | |
952 | fec->dev_id = 0; | |
953 | } else { | |
954 | sprintf(edev->name, "FEC%i", dev_id); | |
955 | fec->dev_id = dev_id; | |
956 | } | |
957 | fec->phy_id = phy_id; | |
0b23fb36 | 958 | |
13947f43 TK |
959 | bus = mdio_alloc(); |
960 | if (!bus) { | |
961 | printf("mdio_alloc failed\n"); | |
962 | ret = -ENOMEM; | |
963 | goto err3; | |
964 | } | |
965 | bus->read = fec_phy_read; | |
966 | bus->write = fec_phy_write; | |
967 | sprintf(bus->name, edev->name); | |
5c1ad3e6 | 968 | #ifdef CONFIG_MX28 |
13947f43 TK |
969 | /* |
970 | * The i.MX28 has two ethernet interfaces, but they are not equal. | |
971 | * Only the first one can access the MDIO bus. | |
972 | */ | |
973 | bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE; | |
974 | #else | |
975 | bus->priv = fec->eth; | |
976 | #endif | |
977 | ret = mdio_register(bus); | |
978 | if (ret) { | |
979 | printf("mdio_register failed\n"); | |
980 | free(bus); | |
981 | ret = -ENOMEM; | |
982 | goto err3; | |
983 | } | |
984 | fec->bus = bus; | |
0b23fb36 IY |
985 | eth_register(edev); |
986 | ||
be252b65 FE |
987 | if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { |
988 | debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); | |
4294b248 | 989 | memcpy(edev->enetaddr, ethaddr, 6); |
0b23fb36 | 990 | } |
13947f43 TK |
991 | /* Configure phy */ |
992 | fec_eth_phy_config(edev); | |
e382fb48 MV |
993 | return ret; |
994 | ||
995 | err3: | |
996 | free(fec); | |
997 | err2: | |
998 | free(edev); | |
999 | err1: | |
1000 | return ret; | |
0b23fb36 IY |
1001 | } |
1002 | ||
5c1ad3e6 | 1003 | #ifndef CONFIG_FEC_MXC_MULTI |
0b23fb36 IY |
1004 | int fecmxc_initialize(bd_t *bd) |
1005 | { | |
1006 | int lout = 1; | |
1007 | ||
1008 | debug("eth_init: fec_probe(bd)\n"); | |
9e27e9dc MV |
1009 | lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); |
1010 | ||
1011 | return lout; | |
1012 | } | |
1013 | #endif | |
1014 | ||
1015 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) | |
1016 | { | |
1017 | int lout = 1; | |
1018 | ||
1019 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); | |
1020 | lout = fec_probe(bd, dev_id, phy_id, addr); | |
0b23fb36 IY |
1021 | |
1022 | return lout; | |
1023 | } | |
2e5f4421 | 1024 | |
13947f43 | 1025 | #ifndef CONFIG_PHYLIB |
2e5f4421 MV |
1026 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) |
1027 | { | |
1028 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
1029 | fec->mii_postcall = cb; | |
1030 | return 0; | |
1031 | } | |
13947f43 | 1032 | #endif |