[people/ms/u-boot.git] / include / configs / uniphier.h

/*
 * Copyright (C) 2012-2015 Panasonic Corporation
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* U-Boot - Common settings for UniPhier Family */

#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__

#define CONFIG_ARMV7_PSCI_1_0

#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10

/*-----------------------------------------------------------------------
 * MMU and Cache Setting
 *----------------------------------------------------------------------*/

/* Comment out the following to enable L1 cache */
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */

#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

#define CONFIG_TIMESTAMP

/* FLASH related */
#define CONFIG_MTD_DEVICE

#define CONFIG_SMC911X_32_BIT
/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
#define CONFIG_SMC911X_BASE	0

#ifdef CONFIG_MICRO_SUPPORT_CARD
#define CONFIG_SMC911X
#else
#define CONFIG_SYS_NO_FLASH
#endif

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI

#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MONITOR_BASE		0
#define CONFIG_SYS_MONITOR_LEN		0x00080000	/* 512KB */
#define CONFIG_SYS_FLASH_BASE		0

/*
 * flash_toggle does not work for our support card.
 * We need to use flash_status_poll.
 */
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1

/* serial console configuration */
#define CONFIG_BAUDRATE			115200

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_CONS_INDEX		1

/* #define CONFIG_ENV_IS_NOWHERE */
/* #define CONFIG_ENV_IS_IN_NAND */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET			0x80000
#define CONFIG_ENV_SIZE				0x2000
/* #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */

#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_SYS_MMC_ENV_PART		1

#ifdef CONFIG_ARM64
#define CPU_RELEASE_ADDR			0x80000000
#define COUNTER_FREQUENCY			50000000
#define CONFIG_GICV3
#define GICD_BASE				0x5fe00000
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define GICR_BASE				0x5fe40000
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define GICR_BASE				0x5fe80000
#endif
#else
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE			1000000
#endif


#define CONFIG_SYS_MAX_NAND_DEVICE			1
#define CONFIG_SYS_NAND_MAX_CHIPS			2
#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_NAND_DENALI_ECC_SIZE			1024

#ifdef CONFIG_ARCH_UNIPHIER_SLD3
#define CONFIG_SYS_NAND_REGS_BASE			0xf8100000
#define CONFIG_SYS_NAND_DATA_BASE			0xf8000000
#else
#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
#endif

#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)

#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS			0

/* USB */
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	4
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION

/* SD/MMC */
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_GENERIC_MMC

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)

/*
 * Network Configuration
 */
#define CONFIG_SERVERIP			192.168.11.1
#define CONFIG_IPADDR			192.168.11.10
#define CONFIG_GATEWAYIP		192.168.11.1
#define CONFIG_NETMASK			255.255.255.0

#define CONFIG_LOADADDR			0x84000000
#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/

#define CONFIG_BOOTCOMMAND		"run $bootmode"

#define CONFIG_ROOTPATH			"/nfs/root/path"
#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs $bootargs root=/dev/nfs rw "			\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
		"run __nfsboot"

#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE			"fitImage"
#define LINUXBOOT_ENV_SETTINGS \
	"fit_addr=0x00100000\0" \
	"fit_addr_r=0x84100000\0" \
	"fit_size=0x00f00000\0" \
	"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
		"bootm $fit_addr\0" \
	"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
		"bootm $fit_addr_r\0" \
	"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
		"bootm $fit_addr_r\0" \
	"__nfsboot=run tftpboot\0"
#else
#ifdef CONFIG_ARM64
#define CONFIG_BOOTFILE			"Image"
#define LINUXBOOT_CMD			"booti"
#define KERNEL_ADDR_R			"kernel_addr_r=0x80080000\0"
#define KERNEL_SIZE			"kernel_size=0x00c00000\0"
#define RAMDISK_ADDR			"ramdisk_addr=0x00e00000\0"
#else
#define CONFIG_BOOTFILE			"zImage"
#define LINUXBOOT_CMD			"bootz"
#define KERNEL_ADDR_R			"kernel_addr_r=0x80208000\0"
#define KERNEL_SIZE			"kernel_size=0x00800000\0"
#define RAMDISK_ADDR			"ramdisk_addr=0x00a00000\0"
#endif
#define LINUXBOOT_ENV_SETTINGS \
	"fdt_addr=0x00100000\0" \
	"fdt_addr_r=0x84100000\0" \
	"fdt_size=0x00008000\0" \
	"kernel_addr=0x00200000\0" \
	KERNEL_ADDR_R \
	KERNEL_SIZE \
	RAMDISK_ADDR \
	"ramdisk_addr_r=0x84a00000\0" \
	"ramdisk_size=0x00600000\0" \
	"ramdisk_file=rootfs.cpio.uboot\0" \
	"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
		LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
	"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
		"setexpr kernel_size $kernel_size / 4 &&" \
		"cp $kernel_addr $kernel_addr_r $kernel_size &&" \
		"setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
		"setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
		"run boot_common\0" \
	"nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
		"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
		"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
		"run boot_common\0" \
	"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
		"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
		"tftpboot $fdt_addr_r $fdt_file &&" \
		"run boot_common\0" \
	"__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
		"tftpboot $fdt_addr_r $fdt_file &&" \
		"setenv ramdisk_addr_r - &&" \
		"run boot_common\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"						\
	"verify=n\0"						\
	"nor_base=0x42000000\0"					\
	"sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&"	\
		"tftpboot $tmp_addr u-boot-spl.bin &&"		\
		"setexpr tmp_addr $nor_base + 0x60000 &&"	\
		"tftpboot $tmp_addr u-boot.bin\0"		\
	"emmcupdate=mmcsetn &&"					\
		"mmc partconf $mmc_first_dev 0 1 1 &&"		\
		"tftpboot u-boot-spl.bin &&"			\
		"mmc write $loadaddr 0 80 &&"			\
		"tftpboot u-boot.bin &&"			\
		"mmc write $loadaddr 80 780\0"			\
	"nandupdate=nand erase 0 0x00100000 &&"			\
		"tftpboot u-boot-spl.bin &&"			\
		"nand write $loadaddr 0 0x00010000 &&"		\
		"tftpboot u-boot.bin &&"			\
		"nand write $loadaddr 0x00010000 0x000f0000\0"	\
	LINUXBOOT_ENV_SETTINGS

#define CONFIG_SYS_BOOTMAPSZ			0x20000000

#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_NR_DRAM_BANKS		2
/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
#define CONFIG_SYS_MEM_TOP_HIDE		64

#if defined(CONFIG_ARM64)
#define CONFIG_SPL_TEXT_BASE		0x30000000
#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
	defined(CONFIG_ARCH_UNIPHIER_LD4) || \
	defined(CONFIG_ARCH_UNIPHIER_SLD8)
#define CONFIG_SPL_TEXT_BASE		0x00040000
#else
#define CONFIG_SPL_TEXT_BASE		0x00100000
#endif

#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define CONFIG_SPL_STACK		(0x30014c00)
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_STACK		(0x3001c000)
#else
#define CONFIG_SPL_STACK		(0x00100000)
#endif
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)

#define CONFIG_PANIC_HANG

#define CONFIG_SPL_FRAMEWORK
#ifdef CONFIG_ARM64
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#endif

#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x10000

/* subtract sizeof(struct image_header) */
#define CONFIG_SYS_UBOOT_BASE			(0x60000 - 0x40)

#define CONFIG_SPL_TARGET			"u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT		0x10000
#define CONFIG_SPL_MAX_SIZE			0x10000
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define CONFIG_SPL_BSS_START_ADDR		0x30012000
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_BSS_START_ADDR		0x30016000
#endif
#define CONFIG_SPL_BSS_MAX_SIZE			0x2000

#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
Commit	Line	Data
5894ca00	1	/*
e8a92932 MY	2	* Copyright (C) 2012-2015 Panasonic Corporation
	3	* Copyright (C) 2015-2016 Socionext Inc.
	4	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5894ca00 MY	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
a187559e	9	/* U-Boot - Common settings for UniPhier Family */
5894ca00 MY	10
	11	#ifndef __CONFIG_UNIPHIER_COMMON_H__
	12	#define __CONFIG_UNIPHIER_COMMON_H__
	13
928f3248	14	#define CONFIG_ARMV7_PSCI_1_0
e8a92932	15
233e42a9 MY	16	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
233e42a9 MY	17
5894ca00 MY	18	/*-----------------------------------------------------------------------
	19	* MMU and Cache Setting
	20	----------------------------------------------------------------------/
	21
	22	/* Comment out the following to enable L1 cache */
	23	/* #define CONFIG_SYS_ICACHE_OFF */
	24	/* #define CONFIG_SYS_DCACHE_OFF */
	25
5894ca00 MY	26	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	27
	28	#define CONFIG_TIMESTAMP
	29
	30	/* FLASH related */
	31	#define CONFIG_MTD_DEVICE
	32
f1d9a9ed MY	33	#define CONFIG_SMC911X_32_BIT
	34	/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
	35	#define CONFIG_SMC911X_BASE 0
	36
	37	#ifdef CONFIG_MICRO_SUPPORT_CARD
	38	#define CONFIG_SMC911X
	39	#else
f4c93a4f MY	40	#define CONFIG_SYS_NO_FLASH
f4c93a4f MY	41	#endif
5894ca00 MY	42
	43	#define CONFIG_FLASH_CFI_DRIVER
	44	#define CONFIG_SYS_FLASH_CFI
	45
	46	#define CONFIG_SYS_MAX_FLASH_SECT 256
	47	#define CONFIG_SYS_MONITOR_BASE 0
d085ecd6	48	#define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
5894ca00 MY	49	#define CONFIG_SYS_FLASH_BASE 0
	50
	51	/*
66deb91e	52	* flash_toggle does not work for our support card.
5894ca00 MY	53	* We need to use flash_status_poll.
	54	*/
	55	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
	56
	57	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	58
9879842c	59	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
5894ca00 MY	60
	61	/* serial console configuration */
	62	#define CONFIG_BAUDRATE 115200
	63
5894ca00 MY	64	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	65
	66	#define CONFIG_CMDLINE_EDITING /* add command line history */
5894ca00 MY	67	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	68	/* Print Buffer Size */
	69	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	70	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	71	/* Boot Argument Buffer Size */
	72	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	73
	74	#define CONFIG_CONS_INDEX 1
	75
aa8a9348	76	/* #define CONFIG_ENV_IS_NOWHERE */
5894ca00	77	/* #define CONFIG_ENV_IS_IN_NAND */
aa8a9348 MY	78	#define CONFIG_ENV_IS_IN_MMC
aa8a9348 MY	79	#define CONFIG_ENV_OFFSET 0x80000
5894ca00	80	#define CONFIG_ENV_SIZE 0x2000
5894ca00 MY	81	/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
5894ca00 MY	82
aa8a9348 MY	83	#define CONFIG_SYS_MMC_ENV_DEV 0
	84	#define CONFIG_SYS_MMC_ENV_PART 1
	85
9d0c2ceb	86	#ifdef CONFIG_ARM64
50862a51	87	#define CPU_RELEASE_ADDR 0x80000000
9d0c2ceb MY	88	#define COUNTER_FREQUENCY 50000000
	89	#define CONFIG_GICV3
	90	#define GICD_BASE 0x5fe00000
667dbcd0 MY	91	#if defined(CONFIG_ARCH_UNIPHIER_LD11)
	92	#define GICR_BASE 0x5fe40000
	93	#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
9d0c2ceb	94	#define GICR_BASE 0x5fe80000
667dbcd0	95	#endif
9d0c2ceb	96	#else
5894ca00 MY	97	/* Time clock 1MHz */
5894ca00 MY	98	#define CONFIG_SYS_TIMER_RATE 1000000
9d0c2ceb MY	99	#endif
9d0c2ceb MY	100
5894ca00	101
5894ca00 MY	102	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	103	#define CONFIG_SYS_NAND_MAX_CHIPS 2
	104	#define CONFIG_SYS_NAND_ONFI_DETECTION
	105
	106	#define CONFIG_NAND_DENALI_ECC_SIZE 1024
	107
ea65c980	108	#ifdef CONFIG_ARCH_UNIPHIER_SLD3
3365b4eb MY	109	#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
	110	#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
	111	#else
5894ca00 MY	112	#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
5894ca00 MY	113	#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
3365b4eb	114	#endif
5894ca00 MY	115
	116	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
	117
	118	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	119	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	120
495deb44	121	/* USB */
53c45d4e	122	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
495deb44 MY	123	#define CONFIG_FAT_WRITE
	124	#define CONFIG_DOS_PARTITION
	125
4aceb3f8	126	/* SD/MMC */
a55d9fee	127	#define CONFIG_SUPPORT_EMMC_BOOT
4aceb3f8 MY	128	#define CONFIG_GENERIC_MMC
4aceb3f8 MY	129
5894ca00 MY	130	/* memtest works on */
	131	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	132	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
	133
5894ca00 MY	134	/*
	135	* Network Configuration
	136	*/
5894ca00 MY	137	#define CONFIG_SERVERIP 192.168.11.1
	138	#define CONFIG_IPADDR 192.168.11.10
	139	#define CONFIG_GATEWAYIP 192.168.11.1
	140	#define CONFIG_NETMASK 255.255.255.0
	141
	142	#define CONFIG_LOADADDR 0x84000000
	143	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
5894ca00 MY	144
	145	#define CONFIG_CMDLINE_EDITING /* add command line history */
	146
	147	#define CONFIG_BOOTCOMMAND "run $bootmode"
	148
	149	#define CONFIG_ROOTPATH "/nfs/root/path"
	150	#define CONFIG_NFSBOOTCOMMAND \
	151	"setenv bootargs $bootargs root=/dev/nfs rw " \
	152	"nfsroot=$serverip:$rootpath " \
	153	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
d566f754	154	"run __nfsboot"
5894ca00	155
421376ae MY	156	#ifdef CONFIG_FIT
	157	#define CONFIG_BOOTFILE "fitImage"
	158	#define LINUXBOOT_ENV_SETTINGS \
	159	"fit_addr=0x00100000\0" \
	160	"fit_addr_r=0x84100000\0" \
	161	"fit_size=0x00f00000\0" \
5451b777	162	"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
421376ae	163	"bootm $fit_addr\0" \
5451b777	164	"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
e037db0c	165	"bootm $fit_addr_r\0" \
5451b777	166	"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
d566f754 MY	167	"bootm $fit_addr_r\0" \
d566f754 MY	168	"__nfsboot=run tftpboot\0"
421376ae	169	#else
9d0c2ceb	170	#ifdef CONFIG_ARM64
9d0c2ceb MY	171	#define CONFIG_BOOTFILE "Image"
	172	#define LINUXBOOT_CMD "booti"
	173	#define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0"
	174	#define KERNEL_SIZE "kernel_size=0x00c00000\0"
	175	#define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0"
	176	#else
89835b35	177	#define CONFIG_BOOTFILE "zImage"
9d0c2ceb MY	178	#define LINUXBOOT_CMD "bootz"
	179	#define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0"
	180	#define KERNEL_SIZE "kernel_size=0x00800000\0"
	181	#define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0"
	182	#endif
421376ae MY	183	#define LINUXBOOT_ENV_SETTINGS \
	184	"fdt_addr=0x00100000\0" \
	185	"fdt_addr_r=0x84100000\0" \
	186	"fdt_size=0x00008000\0" \
	187	"kernel_addr=0x00200000\0" \
9d0c2ceb MY	188	KERNEL_ADDR_R \
	189	KERNEL_SIZE \
	190	RAMDISK_ADDR \
421376ae MY	191	"ramdisk_addr_r=0x84a00000\0" \
421376ae MY	192	"ramdisk_size=0x00600000\0" \
e037db0c	193	"ramdisk_file=rootfs.cpio.uboot\0" \
cd5d9565	194	"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
9d0c2ceb	195	LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
cd5d9565	196	"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
b75e072c MY	197	"setexpr kernel_size $kernel_size / 4 &&" \
b75e072c MY	198	"cp $kernel_addr $kernel_addr_r $kernel_size &&" \
cd5d9565 MY	199	"setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
	200	"setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
	201	"run boot_common\0" \
	202	"nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
421376ae MY	203	"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
421376ae MY	204	"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
cd5d9565 MY	205	"run boot_common\0" \
cd5d9565 MY	206	"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
e037db0c MY	207	"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
e037db0c MY	208	"tftpboot $fdt_addr_r $fdt_file &&" \
d566f754 MY	209	"run boot_common\0" \
d566f754 MY	210	"__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
d566f754 MY	211	"tftpboot $fdt_addr_r $fdt_file &&" \
d566f754 MY	212	"setenv ramdisk_addr_r - &&" \
cd5d9565	213	"run boot_common\0"
421376ae MY	214	#endif
	215
	216	#define CONFIG_EXTRA_ENV_SETTINGS \
	217	"netdev=eth0\0" \
	218	"verify=n\0" \
90a6e929	219	"nor_base=0x42000000\0" \
61a4f5bd MY	220	"sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
	221	"tftpboot $tmp_addr u-boot-spl.bin &&" \
	222	"setexpr tmp_addr $nor_base + 0x60000 &&" \
	223	"tftpboot $tmp_addr u-boot.bin\0" \
c231c436 MY	224	"emmcupdate=mmcsetn &&" \
c231c436 MY	225	"mmc partconf $mmc_first_dev 0 1 1 &&" \
c231c436 MY	226	"tftpboot u-boot-spl.bin &&" \
c231c436 MY	227	"mmc write $loadaddr 0 80 &&" \
d085ecd6	228	"tftpboot u-boot.bin &&" \
c231c436	229	"mmc write $loadaddr 80 780\0" \
421376ae	230	"nandupdate=nand erase 0 0x00100000 &&" \
3cb9abc9	231	"tftpboot u-boot-spl.bin &&" \
421376ae	232	"nand write $loadaddr 0 0x00010000 &&" \
d085ecd6	233	"tftpboot u-boot.bin &&" \
421376ae	234	"nand write $loadaddr 0x00010000 0x000f0000\0" \
421376ae	235	LINUXBOOT_ENV_SETTINGS
5894ca00	236
17bd4a21 MY	237	#define CONFIG_SYS_BOOTMAPSZ 0x20000000
17bd4a21 MY	238
cf88affa	239	#define CONFIG_SYS_SDRAM_BASE 0x80000000
5894ca00	240	#define CONFIG_NR_DRAM_BANKS 2
23869698 MY	241	/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
23869698 MY	242	#define CONFIG_SYS_MEM_TOP_HIDE 64
5894ca00	243
9d0c2ceb MY	244	#if defined(CONFIG_ARM64)
	245	#define CONFIG_SPL_TEXT_BASE 0x30000000
	246	#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) \|\| \
	247	defined(CONFIG_ARCH_UNIPHIER_LD4) \|\| \
ea65c980	248	defined(CONFIG_ARCH_UNIPHIER_SLD8)
f5d0b9b2	249	#define CONFIG_SPL_TEXT_BASE 0x00040000
323d1f9d	250	#else
f5d0b9b2 MY	251	#define CONFIG_SPL_TEXT_BASE 0x00100000
	252	#endif
	253
667dbcd0 MY	254	#if defined(CONFIG_ARCH_UNIPHIER_LD11)
	255	#define CONFIG_SPL_STACK (0x30014c00)
	256	#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
9d0c2ceb MY	257	#define CONFIG_SPL_STACK (0x3001c000)
9d0c2ceb MY	258	#else
755c7d9a	259	#define CONFIG_SPL_STACK (0x00100000)
9d0c2ceb	260	#endif
8cddc279	261	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
5894ca00	262
a286039b MY	263	#define CONFIG_PANIC_HANG
a286039b MY	264
5894ca00	265	#define CONFIG_SPL_FRAMEWORK
adb3928f MY	266	#ifdef CONFIG_ARM64
adb3928f MY	267	#define CONFIG_SPL_BOARD_LOAD_IMAGE
9d0c2ceb	268	#endif
5894ca00	269
5894ca00 MY	270	#define CONFIG_SPL_BOARD_INIT
	271
	272	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
cbbc2d80	273
d085ecd6 MY	274	/* subtract sizeof(struct image_header) */
d085ecd6 MY	275	#define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40)
5894ca00	276
d085ecd6	277	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
6a3cffe8	278	#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
86c3345a	279	#define CONFIG_SPL_MAX_SIZE 0x10000
667dbcd0 MY	280	#if defined(CONFIG_ARCH_UNIPHIER_LD11)
	281	#define CONFIG_SPL_BSS_START_ADDR 0x30012000
	282	#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
9d0c2ceb	283	#define CONFIG_SPL_BSS_START_ADDR 0x30016000
667dbcd0	284	#endif
9d0c2ceb	285	#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
6a3cffe8	286
5894ca00	287	#endif /* __CONFIG_UNIPHIER_COMMON_H__ */