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KVM: VMX: Move skip_emulated_instruction out of nested_vmx_check_vmcs12
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
1767e931
PG		 39#include <linux/export.h>
40#include <linux/moduleparam.h>
0de10343 41#include <linux/mman.h>
2bacc55c 42#include <linux/highmem.h>
19de40a8 43#include <linux/iommu.h>
62c476c7 44#include <linux/intel-iommu.h>
c8076604 45#include <linux/cpufreq.h>
18863bdd 46#include <linux/user-return-notifier.h>
a983fb23 47#include <linux/srcu.h>
5a0e3ad6 48#include <linux/slab.h>
ff9d07a0 49#include <linux/perf_event.h>
7bee342a 50#include <linux/uaccess.h>
af585b92 51#include <linux/hash.h>
a1b60c1c 52#include <linux/pci.h>
16e8d74d
MT		 53#include <linux/timekeeper_internal.h>
54#include <linux/pvclock_gtod.h>
87276880
FW		 55#include <linux/kvm_irqfd.h>
56#include <linux/irqbypass.h>
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
043405e1 68
d1898b73
DH		 69#define CREATE_TRACE_POINTS
70#include "trace.h"
71
313a3dc7 72#define MAX_IO_MSRS 256
890ca9ae 73#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 74u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
75EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 76
0f65dd70
AK		 77#define emul_to_vcpu(ctxt) \
78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79
50a37eb4
JR		 80/* EFER defaults:
81 * - enable syscall per default because its emulated by KVM
82 * - enable LME and LMA per default on 64 bit KVM
83 */
84#ifdef CONFIG_X86_64
1260edbe
LJ		 85static
86u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 87#else
1260edbe 88static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 89#endif
313a3dc7 90
ba1389b7
AK		 91#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
92#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 93
c519265f
RK		 94#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 96
cb142eb7 97static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 98static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 99static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 100static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 101
893590c7 102struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 103EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 104
893590c7 105static bool __read_mostly ignore_msrs = 0;
476bc001 106module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 107
9ed96e87
MT		 108unsigned int min_timer_period_us = 500;
109module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
110
630994b3
MT		 111static bool __read_mostly kvmclock_periodic_sync = true;
112module_param(kvmclock_periodic_sync, bool, S_IRUGO);
113
893590c7 114bool __read_mostly kvm_has_tsc_control;
92a1f12d 115EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 116u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 117EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 118u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
119EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
120u64 __read_mostly kvm_max_tsc_scaling_ratio;
121EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 122u64 __read_mostly kvm_default_tsc_scaling_ratio;
123EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 124
cc578287 125/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 126static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 127module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
128
d0659d94 129/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 130unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 131module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
132
52004014
FW		 133static bool __read_mostly vector_hashing = true;
134module_param(vector_hashing, bool, S_IRUGO);
135
893590c7 136static bool __read_mostly backwards_tsc_observed = false;
16a96021 137
18863bdd
AK		 138#define KVM_NR_SHARED_MSRS 16
139
140struct kvm_shared_msrs_global {
141 int nr;
2bf78fa7 142 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 143};
144
145struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
2bf78fa7
SY		 148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 152};
153
154static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 155static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 156
417bc304 157struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 168 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 173 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 181 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 182 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
417bc304
HB		 193 { NULL }
194};
195
2acf923e
DC		 196u64 __read_mostly host_xcr0;
197
b6785def 198static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 199
af585b92
GN		 200static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
201{
202 int i;
203 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
204 vcpu->arch.apf.gfns[i] = ~0;
205}
206
18863bdd
AK		 207static void kvm_on_user_return(struct user_return_notifier *urn)
208{
209 unsigned slot;
18863bdd
AK		 210 struct kvm_shared_msrs *locals
211 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 212 struct kvm_shared_msr_values *values;
18863bdd
AK		 213
214 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 215 values = &locals->values[slot];
216 if (values->host != values->curr) {
217 wrmsrl(shared_msrs_global.msrs[slot], values->host);
218 values->curr = values->host;
18863bdd
AK		 219 }
220 }
221 locals->registered = false;
222 user_return_notifier_unregister(urn);
223}
224
2bf78fa7 225static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 226{
18863bdd 227 u64 value;
013f6a5d
MT		 228 unsigned int cpu = smp_processor_id();
229 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 230
2bf78fa7
SY		 231 /* only read, and nobody should modify it at this time,
232 * so don't need lock */
233 if (slot >= shared_msrs_global.nr) {
234 printk(KERN_ERR "kvm: invalid MSR slot!");
235 return;
236 }
237 rdmsrl_safe(msr, &value);
238 smsr->values[slot].host = value;
239 smsr->values[slot].curr = value;
240}
241
242void kvm_define_shared_msr(unsigned slot, u32 msr)
243{
0123be42 244 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 245 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 246 if (slot >= shared_msrs_global.nr)
247 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 248}
249EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
250
251static void kvm_shared_msr_cpu_online(void)
252{
253 unsigned i;
18863bdd
AK		 254
255 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 256 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 257}
258
8b3c3104 259int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 260{
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 263 int err;
18863bdd 264
2bf78fa7 265 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 266 return 0;
2bf78fa7 267 smsr->values[slot].curr = value;
8b3c3104
AH		 268 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
269 if (err)
270 return 1;
271
18863bdd
AK		 272 if (!smsr->registered) {
273 smsr->urn.on_user_return = kvm_on_user_return;
274 user_return_notifier_register(&smsr->urn);
275 smsr->registered = true;
276 }
8b3c3104 277 return 0;
18863bdd
AK		 278}
279EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
280
13a34e06 281static void drop_user_return_notifiers(void)
3548bab5 282{
013f6a5d
MT		 283 unsigned int cpu = smp_processor_id();
284 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 285
286 if (smsr->registered)
287 kvm_on_user_return(&smsr->urn);
288}
289
6866b83e
CO		 290u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
291{
8a5a87d9 292 return vcpu->arch.apic_base;
6866b83e
CO		 293}
294EXPORT_SYMBOL_GPL(kvm_get_apic_base);
295
58cb628d
JK		 296int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
297{
298 u64 old_state = vcpu->arch.apic_base &
299 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
300 u64 new_state = msr_info->data &
301 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
302 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
303 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
304
305 if (!msr_info->host_initiated &&
306 ((msr_info->data & reserved_bits) != 0 ||
307 new_state == X2APIC_ENABLE ||
308 (new_state == MSR_IA32_APICBASE_ENABLE &&
309 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
310 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
311 old_state == 0)))
312 return 1;
313
314 kvm_lapic_set_base(vcpu, msr_info->data);
315 return 0;
6866b83e
CO		 316}
317EXPORT_SYMBOL_GPL(kvm_set_apic_base);
318
2605fc21 319asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 320{
321 /* Fault while not rebooting. We want the trace. */
322 BUG();
323}
324EXPORT_SYMBOL_GPL(kvm_spurious_fault);
325
3fd28fce
ED		 326#define EXCPT_BENIGN 0
327#define EXCPT_CONTRIBUTORY 1
328#define EXCPT_PF 2
329
330static int exception_class(int vector)
331{
332 switch (vector) {
333 case PF_VECTOR:
334 return EXCPT_PF;
335 case DE_VECTOR:
336 case TS_VECTOR:
337 case NP_VECTOR:
338 case SS_VECTOR:
339 case GP_VECTOR:
340 return EXCPT_CONTRIBUTORY;
341 default:
342 break;
343 }
344 return EXCPT_BENIGN;
345}
346
d6e8c854
NA		 347#define EXCPT_FAULT 0
348#define EXCPT_TRAP 1
349#define EXCPT_ABORT 2
350#define EXCPT_INTERRUPT 3
351
352static int exception_type(int vector)
353{
354 unsigned int mask;
355
356 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
357 return EXCPT_INTERRUPT;
358
359 mask = 1 << vector;
360
361 /* #DB is trap, as instruction watchpoints are handled elsewhere */
362 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
363 return EXCPT_TRAP;
364
365 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
366 return EXCPT_ABORT;
367
368 /* Reserved exceptions will result in fault */
369 return EXCPT_FAULT;
370}
371
3fd28fce 372static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 373 unsigned nr, bool has_error, u32 error_code,
374 bool reinject)
3fd28fce
ED		 375{
376 u32 prev_nr;
377 int class1, class2;
378
3842d135
AK		 379 kvm_make_request(KVM_REQ_EVENT, vcpu);
380
3fd28fce
ED		 381 if (!vcpu->arch.exception.pending) {
382 queue:
3ffb2468
NA		 383 if (has_error && !is_protmode(vcpu))
384 has_error = false;
3fd28fce
ED		 385 vcpu->arch.exception.pending = true;
386 vcpu->arch.exception.has_error_code = has_error;
387 vcpu->arch.exception.nr = nr;
388 vcpu->arch.exception.error_code = error_code;
3f0fd292 389 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 390 return;
391 }
392
393 /* to check exception */
394 prev_nr = vcpu->arch.exception.nr;
395 if (prev_nr == DF_VECTOR) {
396 /* triple fault -> shutdown */
a8eeb04a 397 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 398 return;
399 }
400 class1 = exception_class(prev_nr);
401 class2 = exception_class(nr);
402 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
403 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
404 /* generate double fault per SDM Table 5-5 */
405 vcpu->arch.exception.pending = true;
406 vcpu->arch.exception.has_error_code = true;
407 vcpu->arch.exception.nr = DF_VECTOR;
408 vcpu->arch.exception.error_code = 0;
409 } else
410 /* replace previous exception with a new one in a hope
411 that instruction re-execution will regenerate lost
412 exception */
413 goto queue;
414}
415
298101da
AK		 416void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
417{
ce7ddec4 418 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 419}
420EXPORT_SYMBOL_GPL(kvm_queue_exception);
421
ce7ddec4
JR		 422void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
423{
424 kvm_multiple_exception(vcpu, nr, false, 0, true);
425}
426EXPORT_SYMBOL_GPL(kvm_requeue_exception);
427
db8fcefa 428void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 429{
db8fcefa
AP		 430 if (err)
431 kvm_inject_gp(vcpu, 0);
432 else
433 kvm_x86_ops->skip_emulated_instruction(vcpu);
434}
435EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 436
6389ee94 437void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 438{
439 ++vcpu->stat.pf_guest;
6389ee94
AK		 440 vcpu->arch.cr2 = fault->address;
441 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 442}
27d6c865 443EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 444
ef54bcfe 445static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 446{
6389ee94
AK		 447 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
448 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 449 else
6389ee94 450 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 451
452 return fault->nested_page_fault;
d4f8cf66
JR		 453}
454
3419ffc8
SY		 455void kvm_inject_nmi(struct kvm_vcpu *vcpu)
456{
7460fb4a
AK		 457 atomic_inc(&vcpu->arch.nmi_queued);
458 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 459}
460EXPORT_SYMBOL_GPL(kvm_inject_nmi);
461
298101da
AK		 462void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
463{
ce7ddec4 464 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 465}
466EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
467
ce7ddec4
JR		 468void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
469{
470 kvm_multiple_exception(vcpu, nr, true, error_code, true);
471}
472EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
473
0a79b009
AK		 474/*
475 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
476 * a #GP and return false.
477 */
478bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 479{
0a79b009
AK		 480 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
481 return true;
482 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
483 return false;
298101da 484}
0a79b009 485EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 486
16f8a6f9
NA		 487bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
488{
489 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
490 return true;
491
492 kvm_queue_exception(vcpu, UD_VECTOR);
493 return false;
494}
495EXPORT_SYMBOL_GPL(kvm_require_dr);
496
ec92fe44
JR		 497/*
498 * This function will be used to read from the physical memory of the currently
54bf36aa 499 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 500 * can read from guest physical or from the guest's guest physical memory.
501 */
502int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
503 gfn_t ngfn, void *data, int offset, int len,
504 u32 access)
505{
54987b7a 506 struct x86_exception exception;
ec92fe44
JR		 507 gfn_t real_gfn;
508 gpa_t ngpa;
509
510 ngpa = gfn_to_gpa(ngfn);
54987b7a 511 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 512 if (real_gfn == UNMAPPED_GVA)
513 return -EFAULT;
514
515 real_gfn = gpa_to_gfn(real_gfn);
516
54bf36aa 517 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 518}
519EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
520
69b0049a 521static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 522 void *data, int offset, int len, u32 access)
523{
524 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
525 data, offset, len, access);
526}
527
a03490ed
CO		 528/*
529 * Load the pae pdptrs. Return true is they are all valid.
530 */
ff03a073 531int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 532{
533 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
534 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
535 int i;
536 int ret;
ff03a073 537 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 538
ff03a073
JR		 539 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
540 offset * sizeof(u64), sizeof(pdpte),
541 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 542 if (ret < 0) {
543 ret = 0;
544 goto out;
545 }
546 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 547 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 548 (pdpte[i] &
549 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 550 ret = 0;
551 goto out;
552 }
553 }
554 ret = 1;
555
ff03a073 556 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 557 __set_bit(VCPU_EXREG_PDPTR,
558 (unsigned long *)&vcpu->arch.regs_avail);
559 __set_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 561out:
a03490ed
CO		 562
563 return ret;
564}
cc4b6871 565EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 566
d835dfec
AK		 567static bool pdptrs_changed(struct kvm_vcpu *vcpu)
568{
ff03a073 569 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 570 bool changed = true;
3d06b8bf
JR		 571 int offset;
572 gfn_t gfn;
d835dfec
AK		 573 int r;
574
575 if (is_long_mode(vcpu) || !is_pae(vcpu))
576 return false;
577
6de4f3ad
AK		 578 if (!test_bit(VCPU_EXREG_PDPTR,
579 (unsigned long *)&vcpu->arch.regs_avail))
580 return true;
581
9f8fe504
AK		 582 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
583 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 584 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
585 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 586 if (r < 0)
587 goto out;
ff03a073 588 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 589out:
d835dfec
AK		 590
591 return changed;
592}
593
49a9b07e 594int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 595{
aad82703 596 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 597 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 598
f9a48e6a
AK		 599 cr0 |= X86_CR0_ET;
600
ab344828 601#ifdef CONFIG_X86_64
0f12244f
GN		 602 if (cr0 & 0xffffffff00000000UL)
603 return 1;
ab344828
GN		 604#endif
605
606 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 607
0f12244f
GN		 608 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
609 return 1;
a03490ed 610
0f12244f
GN		 611 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
612 return 1;
a03490ed
CO		 613
614 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
615#ifdef CONFIG_X86_64
f6801dff 616 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 617 int cs_db, cs_l;
618
0f12244f
GN		 619 if (!is_pae(vcpu))
620 return 1;
a03490ed 621 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 622 if (cs_l)
623 return 1;
a03490ed
CO		 624 } else
625#endif
ff03a073 626 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 627 kvm_read_cr3(vcpu)))
0f12244f 628 return 1;
a03490ed
CO		 629 }
630
ad756a16
MJ		 631 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
632 return 1;
633
a03490ed 634 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 635
d170c419 636 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 637 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 638 kvm_async_pf_hash_reset(vcpu);
639 }
e5f3f027 640
aad82703
SY		 641 if ((cr0 ^ old_cr0) & update_bits)
642 kvm_mmu_reset_context(vcpu);
b18d5431 643
879ae188
LE		 644 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
645 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
646 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 647 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
648
0f12244f
GN		 649 return 0;
650}
2d3ad1f4 651EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 652
2d3ad1f4 653void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 654{
49a9b07e 655 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 656}
2d3ad1f4 657EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 658
42bdf991
MT		 659static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
660{
661 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
662 !vcpu->guest_xcr0_loaded) {
663 /* kvm_set_xcr() also depends on this */
664 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
665 vcpu->guest_xcr0_loaded = 1;
666 }
667}
668
669static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
670{
671 if (vcpu->guest_xcr0_loaded) {
672 if (vcpu->arch.xcr0 != host_xcr0)
673 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
674 vcpu->guest_xcr0_loaded = 0;
675 }
676}
677
69b0049a 678static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 679{
56c103ec
LJ		 680 u64 xcr0 = xcr;
681 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 682 u64 valid_bits;
2acf923e
DC		 683
684 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
685 if (index != XCR_XFEATURE_ENABLED_MASK)
686 return 1;
d91cab78 687 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 688 return 1;
d91cab78 689 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 690 return 1;
46c34cb0
PB		 691
692 /*
693 * Do not allow the guest to set bits that we do not support
694 * saving. However, xcr0 bit 0 is always set, even if the
695 * emulated CPU does not support XSAVE (see fx_init).
696 */
d91cab78 697 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 698 if (xcr0 & ~valid_bits)
2acf923e 699 return 1;
46c34cb0 700
d91cab78
DH		 701 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
702 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 703 return 1;
704
d91cab78
DH		 705 if (xcr0 & XFEATURE_MASK_AVX512) {
706 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 707 return 1;
d91cab78 708 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 709 return 1;
710 }
2acf923e 711 vcpu->arch.xcr0 = xcr0;
56c103ec 712
d91cab78 713 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 714 kvm_update_cpuid(vcpu);
2acf923e
DC		 715 return 0;
716}
717
718int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
719{
764bcbc5
Z		 720 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
721 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 722 kvm_inject_gp(vcpu, 0);
723 return 1;
724 }
725 return 0;
726}
727EXPORT_SYMBOL_GPL(kvm_set_xcr);
728
a83b29c6 729int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 730{
fc78f519 731 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 732 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 733 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 734
0f12244f
GN		 735 if (cr4 & CR4_RESERVED_BITS)
736 return 1;
a03490ed 737
2acf923e
DC		 738 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
739 return 1;
740
c68b734f
YW		 741 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
742 return 1;
743
97ec8c06
FW		 744 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
745 return 1;
746
afcbf13f 747 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 748 return 1;
749
b9baba86
HH		 750 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
751 return 1;
752
a03490ed 753 if (is_long_mode(vcpu)) {
0f12244f
GN		 754 if (!(cr4 & X86_CR4_PAE))
755 return 1;
a2edf57f
AK		 756 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
757 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 758 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
759 kvm_read_cr3(vcpu)))
0f12244f
GN		 760 return 1;
761
ad756a16
MJ		 762 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
763 if (!guest_cpuid_has_pcid(vcpu))
764 return 1;
765
766 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
767 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
768 return 1;
769 }
770
5e1746d6 771 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 772 return 1;
a03490ed 773
ad756a16
MJ		 774 if (((cr4 ^ old_cr4) & pdptr_bits) ||
775 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 776 kvm_mmu_reset_context(vcpu);
0f12244f 777
b9baba86 778 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 779 kvm_update_cpuid(vcpu);
2acf923e 780
0f12244f
GN		 781 return 0;
782}
2d3ad1f4 783EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 784
2390218b 785int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 786{
ac146235 787#ifdef CONFIG_X86_64
9d88fca7 788 cr3 &= ~CR3_PCID_INVD;
ac146235 789#endif
9d88fca7 790
9f8fe504 791 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 792 kvm_mmu_sync_roots(vcpu);
77c3913b 793 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 794 return 0;
d835dfec
AK		 795 }
796
a03490ed 797 if (is_long_mode(vcpu)) {
d9f89b88
JK		 798 if (cr3 & CR3_L_MODE_RESERVED_BITS)
799 return 1;
800 } else if (is_pae(vcpu) && is_paging(vcpu) &&
801 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 802 return 1;
a03490ed 803
0f12244f 804 vcpu->arch.cr3 = cr3;
aff48baa 805 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 806 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 807 return 0;
808}
2d3ad1f4 809EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 810
eea1cff9 811int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 812{
0f12244f
GN		 813 if (cr8 & CR8_RESERVED_BITS)
814 return 1;
35754c98 815 if (lapic_in_kernel(vcpu))
a03490ed
CO		 816 kvm_lapic_set_tpr(vcpu, cr8);
817 else
ad312c7c 818 vcpu->arch.cr8 = cr8;
0f12244f
GN		 819 return 0;
820}
2d3ad1f4 821EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 822
2d3ad1f4 823unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 824{
35754c98 825 if (lapic_in_kernel(vcpu))
a03490ed
CO		 826 return kvm_lapic_get_cr8(vcpu);
827 else
ad312c7c 828 return vcpu->arch.cr8;
a03490ed 829}
2d3ad1f4 830EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 831
ae561ede
NA		 832static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
833{
834 int i;
835
836 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
837 for (i = 0; i < KVM_NR_DB_REGS; i++)
838 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
839 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
840 }
841}
842
73aaf249
JK		 843static void kvm_update_dr6(struct kvm_vcpu *vcpu)
844{
845 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
846 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
847}
848
c8639010
JK		 849static void kvm_update_dr7(struct kvm_vcpu *vcpu)
850{
851 unsigned long dr7;
852
853 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
854 dr7 = vcpu->arch.guest_debug_dr7;
855 else
856 dr7 = vcpu->arch.dr7;
857 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 858 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
859 if (dr7 & DR7_BP_EN_MASK)
860 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 861}
862
6f43ed01
NA		 863static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
864{
865 u64 fixed = DR6_FIXED_1;
866
867 if (!guest_cpuid_has_rtm(vcpu))
868 fixed |= DR6_RTM;
869 return fixed;
870}
871
338dbc97 872static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 873{
874 switch (dr) {
875 case 0 ... 3:
876 vcpu->arch.db[dr] = val;
877 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
878 vcpu->arch.eff_db[dr] = val;
879 break;
880 case 4:
020df079
GN		 881 /* fall through */
882 case 6:
338dbc97
GN		 883 if (val & 0xffffffff00000000ULL)
884 return -1; /* #GP */
6f43ed01 885 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 886 kvm_update_dr6(vcpu);
020df079
GN		 887 break;
888 case 5:
020df079
GN		 889 /* fall through */
890 default: /* 7 */
338dbc97
GN		 891 if (val & 0xffffffff00000000ULL)
892 return -1; /* #GP */
020df079 893 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 894 kvm_update_dr7(vcpu);
020df079
GN		 895 break;
896 }
897
898 return 0;
899}
338dbc97
GN		 900
901int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
902{
16f8a6f9 903 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 904 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 905 return 1;
906 }
907 return 0;
338dbc97 908}
020df079
GN		 909EXPORT_SYMBOL_GPL(kvm_set_dr);
910
16f8a6f9 911int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 912{
913 switch (dr) {
914 case 0 ... 3:
915 *val = vcpu->arch.db[dr];
916 break;
917 case 4:
020df079
GN		 918 /* fall through */
919 case 6:
73aaf249
JK		 920 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
921 *val = vcpu->arch.dr6;
922 else
923 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 924 break;
925 case 5:
020df079
GN		 926 /* fall through */
927 default: /* 7 */
928 *val = vcpu->arch.dr7;
929 break;
930 }
338dbc97
GN		 931 return 0;
932}
020df079
GN		 933EXPORT_SYMBOL_GPL(kvm_get_dr);
934
022cd0e8
AK		 935bool kvm_rdpmc(struct kvm_vcpu *vcpu)
936{
937 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
938 u64 data;
939 int err;
940
c6702c9d 941 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 942 if (err)
943 return err;
944 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
945 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
946 return err;
947}
948EXPORT_SYMBOL_GPL(kvm_rdpmc);
949
043405e1
CO		 950/*
951 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
952 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
953 *
954 * This list is modified at module load time to reflect the
e3267cbb 955 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 956 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
957 * may depend on host virtualization features rather than host cpu features.
043405e1 958 */
e3267cbb 959
043405e1
CO		 960static u32 msrs_to_save[] = {
961 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 962 MSR_STAR,
043405e1
CO		 963#ifdef CONFIG_X86_64
964 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
965#endif
b3897a49 966 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 967 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 968};
969
970static unsigned num_msrs_to_save;
971
62ef68bb
PB		 972static u32 emulated_msrs[] = {
973 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
974 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
975 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
976 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 977 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
978 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 979 HV_X64_MSR_RESET,
11c4b1ca 980 HV_X64_MSR_VP_INDEX,
9eec50b8 981 HV_X64_MSR_VP_RUNTIME,
5c919412 982 HV_X64_MSR_SCONTROL,
1f4b34f8 983 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 984 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
985 MSR_KVM_PV_EOI_EN,
986
ba904635 987 MSR_IA32_TSC_ADJUST,
a3e06bbe 988 MSR_IA32_TSCDEADLINE,
043405e1 989 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 990 MSR_IA32_MCG_STATUS,
991 MSR_IA32_MCG_CTL,
c45dcc71 992 MSR_IA32_MCG_EXT_CTL,
64d60670 993 MSR_IA32_SMBASE,
043405e1
CO		 994};
995
62ef68bb
PB		 996static unsigned num_emulated_msrs;
997
384bb783 998bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 999{
b69e8cae 1000 if (efer & efer_reserved_bits)
384bb783 1001 return false;
15c4a640 1002
1b2fd70c
AG		 1003 if (efer & EFER_FFXSR) {
1004 struct kvm_cpuid_entry2 *feat;
1005
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1007 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1008 return false;
1b2fd70c
AG		 1009 }
1010
d8017474
AG		 1011 if (efer & EFER_SVME) {
1012 struct kvm_cpuid_entry2 *feat;
1013
1014 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1015 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1016 return false;
d8017474
AG		 1017 }
1018
384bb783
JK		 1019 return true;
1020}
1021EXPORT_SYMBOL_GPL(kvm_valid_efer);
1022
1023static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1024{
1025 u64 old_efer = vcpu->arch.efer;
1026
1027 if (!kvm_valid_efer(vcpu, efer))
1028 return 1;
1029
1030 if (is_paging(vcpu)
1031 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1032 return 1;
1033
15c4a640 1034 efer &= ~EFER_LMA;
f6801dff 1035 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1036
a3d204e2
SY		 1037 kvm_x86_ops->set_efer(vcpu, efer);
1038
aad82703
SY		 1039 /* Update reserved bits */
1040 if ((efer ^ old_efer) & EFER_NX)
1041 kvm_mmu_reset_context(vcpu);
1042
b69e8cae 1043 return 0;
15c4a640
CO		 1044}
1045
f2b4b7dd
JR		 1046void kvm_enable_efer_bits(u64 mask)
1047{
1048 efer_reserved_bits &= ~mask;
1049}
1050EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1051
15c4a640
CO		 1052/*
1053 * Writes msr value into into the appropriate "register".
1054 * Returns 0 on success, non-0 otherwise.
1055 * Assumes vcpu_load() was already called.
1056 */
8fe8ab46 1057int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1058{
854e8bb1
NA		 1059 switch (msr->index) {
1060 case MSR_FS_BASE:
1061 case MSR_GS_BASE:
1062 case MSR_KERNEL_GS_BASE:
1063 case MSR_CSTAR:
1064 case MSR_LSTAR:
1065 if (is_noncanonical_address(msr->data))
1066 return 1;
1067 break;
1068 case MSR_IA32_SYSENTER_EIP:
1069 case MSR_IA32_SYSENTER_ESP:
1070 /*
1071 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1072 * non-canonical address is written on Intel but not on
1073 * AMD (which ignores the top 32-bits, because it does
1074 * not implement 64-bit SYSENTER).
1075 *
1076 * 64-bit code should hence be able to write a non-canonical
1077 * value on AMD. Making the address canonical ensures that
1078 * vmentry does not fail on Intel after writing a non-canonical
1079 * value, and that something deterministic happens if the guest
1080 * invokes 64-bit SYSENTER.
1081 */
1082 msr->data = get_canonical(msr->data);
1083 }
8fe8ab46 1084 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1085}
854e8bb1 1086EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1087
313a3dc7
CO		 1088/*
1089 * Adapt set_msr() to msr_io()'s calling convention
1090 */
609e36d3
PB		 1091static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1092{
1093 struct msr_data msr;
1094 int r;
1095
1096 msr.index = index;
1097 msr.host_initiated = true;
1098 r = kvm_get_msr(vcpu, &msr);
1099 if (r)
1100 return r;
1101
1102 *data = msr.data;
1103 return 0;
1104}
1105
313a3dc7
CO		 1106static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1107{
8fe8ab46
WA		 1108 struct msr_data msr;
1109
1110 msr.data = *data;
1111 msr.index = index;
1112 msr.host_initiated = true;
1113 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1114}
1115
16e8d74d
MT		 1116#ifdef CONFIG_X86_64
1117struct pvclock_gtod_data {
1118 seqcount_t seq;
1119
1120 struct { /* extract of a clocksource struct */
1121 int vclock_mode;
1122 cycle_t cycle_last;
1123 cycle_t mask;
1124 u32 mult;
1125 u32 shift;
1126 } clock;
1127
cbcf2dd3
TG		 1128 u64 boot_ns;
1129 u64 nsec_base;
16e8d74d
MT		 1130};
1131
1132static struct pvclock_gtod_data pvclock_gtod_data;
1133
1134static void update_pvclock_gtod(struct timekeeper *tk)
1135{
1136 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1137 u64 boot_ns;
1138
876e7881 1139 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1140
1141 write_seqcount_begin(&vdata->seq);
1142
1143 /* copy pvclock gtod data */
876e7881
PZ		 1144 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1145 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1146 vdata->clock.mask = tk->tkr_mono.mask;
1147 vdata->clock.mult = tk->tkr_mono.mult;
1148 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1149
cbcf2dd3 1150 vdata->boot_ns = boot_ns;
876e7881 1151 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1152
1153 write_seqcount_end(&vdata->seq);
1154}
1155#endif
1156
bab5bb39
NK		 1157void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1158{
1159 /*
1160 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1161 * vcpu_enter_guest. This function is only called from
1162 * the physical CPU that is running vcpu.
1163 */
1164 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1165}
16e8d74d 1166
18068523
GOC		 1167static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1168{
9ed3c444
AK		 1169 int version;
1170 int r;
50d0a0f9 1171 struct pvclock_wall_clock wc;
87aeb54f 1172 struct timespec64 boot;
18068523
GOC		 1173
1174 if (!wall_clock)
1175 return;
1176
9ed3c444
AK		 1177 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1178 if (r)
1179 return;
1180
1181 if (version & 1)
1182 ++version; /* first time write, random junk */
1183
1184 ++version;
18068523 1185
1dab1345
NK		 1186 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1187 return;
18068523 1188
50d0a0f9
GH		 1189 /*
1190 * The guest calculates current wall clock time by adding
34c238a1 1191 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1192 * wall clock specified here. guest system time equals host
1193 * system time for us, thus we must fill in host boot time here.
1194 */
87aeb54f 1195 getboottime64(&boot);
50d0a0f9 1196
4b648665 1197 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1198 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1199 boot = timespec64_sub(boot, ts);
4b648665 1200 }
87aeb54f 1201 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1202 wc.nsec = boot.tv_nsec;
1203 wc.version = version;
18068523
GOC		 1204
1205 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1206
1207 version++;
1208 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1209}
1210
50d0a0f9
GH		 1211static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1212{
b51012de
PB		 1213 do_shl32_div32(dividend, divisor);
1214 return dividend;
50d0a0f9
GH		 1215}
1216
3ae13faa 1217static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1218 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1219{
5f4e3f88 1220 uint64_t scaled64;
50d0a0f9
GH		 1221 int32_t shift = 0;
1222 uint64_t tps64;
1223 uint32_t tps32;
1224
3ae13faa
PB		 1225 tps64 = base_hz;
1226 scaled64 = scaled_hz;
50933623 1227 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1228 tps64 >>= 1;
1229 shift--;
1230 }
1231
1232 tps32 = (uint32_t)tps64;
50933623
JK		 1233 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1234 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1235 scaled64 >>= 1;
1236 else
1237 tps32 <<= 1;
50d0a0f9
GH		 1238 shift++;
1239 }
1240
5f4e3f88
ZA		 1241 *pshift = shift;
1242 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1243
3ae13faa
PB		 1244 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1245 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1246}
1247
d828199e 1248#ifdef CONFIG_X86_64
16e8d74d 1249static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1250#endif
16e8d74d 1251
c8076604 1252static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1253static unsigned long max_tsc_khz;
c8076604 1254
cc578287 1255static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1256{
cc578287
ZA		 1257 u64 v = (u64)khz * (1000000 + ppm);
1258 do_div(v, 1000000);
1259 return v;
1e993611
JR		 1260}
1261
381d585c
HZ		 1262static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1263{
1264 u64 ratio;
1265
1266 /* Guest TSC same frequency as host TSC? */
1267 if (!scale) {
1268 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1269 return 0;
1270 }
1271
1272 /* TSC scaling supported? */
1273 if (!kvm_has_tsc_control) {
1274 if (user_tsc_khz > tsc_khz) {
1275 vcpu->arch.tsc_catchup = 1;
1276 vcpu->arch.tsc_always_catchup = 1;
1277 return 0;
1278 } else {
1279 WARN(1, "user requested TSC rate below hardware speed\n");
1280 return -1;
1281 }
1282 }
1283
1284 /* TSC scaling required - calculate ratio */
1285 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1286 user_tsc_khz, tsc_khz);
1287
1288 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1289 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1290 user_tsc_khz);
1291 return -1;
1292 }
1293
1294 vcpu->arch.tsc_scaling_ratio = ratio;
1295 return 0;
1296}
1297
4941b8cb 1298static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1299{
cc578287
ZA		 1300 u32 thresh_lo, thresh_hi;
1301 int use_scaling = 0;
217fc9cf 1302
03ba32ca 1303 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1304 if (user_tsc_khz == 0) {
ad721883
HZ		 1305 /* set tsc_scaling_ratio to a safe value */
1306 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1307 return -1;
ad721883 1308 }
03ba32ca 1309
c285545f 1310 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1311 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1312 &vcpu->arch.virtual_tsc_shift,
1313 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1314 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1315
1316 /*
1317 * Compute the variation in TSC rate which is acceptable
1318 * within the range of tolerance and decide if the
1319 * rate being applied is within that bounds of the hardware
1320 * rate. If so, no scaling or compensation need be done.
1321 */
1322 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1323 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1324 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1325 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1326 use_scaling = 1;
1327 }
4941b8cb 1328 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1329}
1330
1331static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1332{
e26101b1 1333 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1334 vcpu->arch.virtual_tsc_mult,
1335 vcpu->arch.virtual_tsc_shift);
e26101b1 1336 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1337 return tsc;
1338}
1339
69b0049a 1340static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1341{
1342#ifdef CONFIG_X86_64
1343 bool vcpus_matched;
b48aa97e
MT		 1344 struct kvm_arch *ka = &vcpu->kvm->arch;
1345 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1346
1347 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1348 atomic_read(&vcpu->kvm->online_vcpus));
1349
7f187922
MT		 1350 /*
1351 * Once the masterclock is enabled, always perform request in
1352 * order to update it.
1353 *
1354 * In order to enable masterclock, the host clocksource must be TSC
1355 * and the vcpus need to have matched TSCs. When that happens,
1356 * perform request to enable masterclock.
1357 */
1358 if (ka->use_master_clock ||
1359 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1360 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1361
1362 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1363 atomic_read(&vcpu->kvm->online_vcpus),
1364 ka->use_master_clock, gtod->clock.vclock_mode);
1365#endif
1366}
1367
ba904635
WA		 1368static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1369{
3e3f5026 1370 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1371 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1372}
1373
35181e86
HZ		 1374/*
1375 * Multiply tsc by a fixed point number represented by ratio.
1376 *
1377 * The most significant 64-N bits (mult) of ratio represent the
1378 * integral part of the fixed point number; the remaining N bits
1379 * (frac) represent the fractional part, ie. ratio represents a fixed
1380 * point number (mult + frac * 2^(-N)).
1381 *
1382 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1383 */
1384static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1385{
1386 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1387}
1388
1389u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1390{
1391 u64 _tsc = tsc;
1392 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1393
1394 if (ratio != kvm_default_tsc_scaling_ratio)
1395 _tsc = __scale_tsc(ratio, tsc);
1396
1397 return _tsc;
1398}
1399EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1400
07c1419a
HZ		 1401static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1402{
1403 u64 tsc;
1404
1405 tsc = kvm_scale_tsc(vcpu, rdtsc());
1406
1407 return target_tsc - tsc;
1408}
1409
4ba76538
HZ		 1410u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1411{
ea26e4ec 1412 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1413}
1414EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1415
a545ab6a
LC		 1416static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1417{
1418 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1419 vcpu->arch.tsc_offset = offset;
1420}
1421
8fe8ab46 1422void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1423{
1424 struct kvm *kvm = vcpu->kvm;
f38e098f 1425 u64 offset, ns, elapsed;
99e3e30a 1426 unsigned long flags;
02626b6a 1427 s64 usdiff;
b48aa97e 1428 bool matched;
0d3da0d2 1429 bool already_matched;
8fe8ab46 1430 u64 data = msr->data;
99e3e30a 1431
038f8c11 1432 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1433 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1434 ns = ktime_get_boot_ns();
f38e098f 1435 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1436
03ba32ca 1437 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1438 int faulted = 0;
1439
03ba32ca
MT		 1440 /* n.b - signed multiplication and division required */
1441 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1442#ifdef CONFIG_X86_64
03ba32ca 1443 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1444#else
03ba32ca 1445 /* do_div() only does unsigned */
8915aa27
MT		 1446 asm("1: idivl %[divisor]\n"
1447 "2: xor %%edx, %%edx\n"
1448 " movl $0, %[faulted]\n"
1449 "3:\n"
1450 ".section .fixup,\"ax\"\n"
1451 "4: movl $1, %[faulted]\n"
1452 " jmp 3b\n"
1453 ".previous\n"
1454
1455 _ASM_EXTABLE(1b, 4b)
1456
1457 : "=A"(usdiff), [faulted] "=r" (faulted)
1458 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1459
5d3cb0f6 1460#endif
03ba32ca
MT		 1461 do_div(elapsed, 1000);
1462 usdiff -= elapsed;
1463 if (usdiff < 0)
1464 usdiff = -usdiff;
8915aa27
MT		 1465
1466 /* idivl overflow => difference is larger than USEC_PER_SEC */
1467 if (faulted)
1468 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1469 } else
1470 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1471
1472 /*
5d3cb0f6
ZA		 1473 * Special case: TSC write with a small delta (1 second) of virtual
1474 * cycle time against real time is interpreted as an attempt to
1475 * synchronize the CPU.
1476 *
1477 * For a reliable TSC, we can match TSC offsets, and for an unstable
1478 * TSC, we add elapsed time in this computation. We could let the
1479 * compensation code attempt to catch up if we fall behind, but
1480 * it's better to try to match offsets from the beginning.
1481 */
02626b6a 1482 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1483 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1484 if (!check_tsc_unstable()) {
e26101b1 1485 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1486 pr_debug("kvm: matched tsc offset for %llu\n", data);
1487 } else {
857e4099 1488 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1489 data += delta;
07c1419a 1490 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1491 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1492 }
b48aa97e 1493 matched = true;
0d3da0d2 1494 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1495 } else {
1496 /*
1497 * We split periods of matched TSC writes into generations.
1498 * For each generation, we track the original measured
1499 * nanosecond time, offset, and write, so if TSCs are in
1500 * sync, we can match exact offset, and if not, we can match
4a969980 1501 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1502 *
1503 * These values are tracked in kvm->arch.cur_xxx variables.
1504 */
1505 kvm->arch.cur_tsc_generation++;
1506 kvm->arch.cur_tsc_nsec = ns;
1507 kvm->arch.cur_tsc_write = data;
1508 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1509 matched = false;
0d3da0d2 1510 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1511 kvm->arch.cur_tsc_generation, data);
f38e098f 1512 }
e26101b1
ZA		 1513
1514 /*
1515 * We also track th most recent recorded KHZ, write and time to
1516 * allow the matching interval to be extended at each write.
1517 */
f38e098f
ZA		 1518 kvm->arch.last_tsc_nsec = ns;
1519 kvm->arch.last_tsc_write = data;
5d3cb0f6 1520 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1521
b183aa58 1522 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1523
1524 /* Keep track of which generation this VCPU has synchronized to */
1525 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1526 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1527 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1528
ba904635
WA		 1529 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1530 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1531 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1532 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1533
1534 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1535 if (!matched) {
b48aa97e 1536 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1537 } else if (!already_matched) {
1538 kvm->arch.nr_vcpus_matched_tsc++;
1539 }
b48aa97e
MT		 1540
1541 kvm_track_tsc_matching(vcpu);
1542 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1543}
e26101b1 1544
99e3e30a
ZA		 1545EXPORT_SYMBOL_GPL(kvm_write_tsc);
1546
58ea6767
HZ		 1547static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1548 s64 adjustment)
1549{
ea26e4ec 1550 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1551}
1552
1553static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1554{
1555 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1556 WARN_ON(adjustment < 0);
1557 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1558 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1559}
1560
d828199e
MT		 1561#ifdef CONFIG_X86_64
1562
1563static cycle_t read_tsc(void)
1564{
03b9730b
AL		 1565 cycle_t ret = (cycle_t)rdtsc_ordered();
1566 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1567
1568 if (likely(ret >= last))
1569 return ret;
1570
1571 /*
1572 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1573 * predictable (it's just a function of time and the likely is
d828199e
MT		 1574 * very likely) and there's a data dependence, so force GCC
1575 * to generate a branch instead. I don't barrier() because
1576 * we don't actually need a barrier, and if this function
1577 * ever gets inlined it will generate worse code.
1578 */
1579 asm volatile ("");
1580 return last;
1581}
1582
1583static inline u64 vgettsc(cycle_t *cycle_now)
1584{
1585 long v;
1586 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1587
1588 *cycle_now = read_tsc();
1589
1590 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1591 return v * gtod->clock.mult;
1592}
1593
cbcf2dd3 1594static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1595{
cbcf2dd3 1596 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1597 unsigned long seq;
d828199e 1598 int mode;
cbcf2dd3 1599 u64 ns;
d828199e 1600
d828199e
MT		 1601 do {
1602 seq = read_seqcount_begin(&gtod->seq);
1603 mode = gtod->clock.vclock_mode;
cbcf2dd3 1604 ns = gtod->nsec_base;
d828199e
MT		 1605 ns += vgettsc(cycle_now);
1606 ns >>= gtod->clock.shift;
cbcf2dd3 1607 ns += gtod->boot_ns;
d828199e 1608 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1609 *t = ns;
d828199e
MT		 1610
1611 return mode;
1612}
1613
1614/* returns true if host is using tsc clocksource */
1615static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1616{
d828199e
MT		 1617 /* checked again under seqlock below */
1618 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1619 return false;
1620
cbcf2dd3 1621 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1622}
1623#endif
1624
1625/*
1626 *
b48aa97e
MT		 1627 * Assuming a stable TSC across physical CPUS, and a stable TSC
1628 * across virtual CPUs, the following condition is possible.
1629 * Each numbered line represents an event visible to both
d828199e
MT		 1630 * CPUs at the next numbered event.
1631 *
1632 * "timespecX" represents host monotonic time. "tscX" represents
1633 * RDTSC value.
1634 *
1635 * VCPU0 on CPU0 | VCPU1 on CPU1
1636 *
1637 * 1. read timespec0,tsc0
1638 * 2. | timespec1 = timespec0 + N
1639 * | tsc1 = tsc0 + M
1640 * 3. transition to guest | transition to guest
1641 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1642 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1643 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1644 *
1645 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1646 *
1647 * - ret0 < ret1
1648 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1649 * ...
1650 * - 0 < N - M => M < N
1651 *
1652 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1653 * always the case (the difference between two distinct xtime instances
1654 * might be smaller then the difference between corresponding TSC reads,
1655 * when updating guest vcpus pvclock areas).
1656 *
1657 * To avoid that problem, do not allow visibility of distinct
1658 * system_timestamp/tsc_timestamp values simultaneously: use a master
1659 * copy of host monotonic time values. Update that master copy
1660 * in lockstep.
1661 *
b48aa97e 1662 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1663 *
1664 */
1665
1666static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1667{
1668#ifdef CONFIG_X86_64
1669 struct kvm_arch *ka = &kvm->arch;
1670 int vclock_mode;
b48aa97e
MT		 1671 bool host_tsc_clocksource, vcpus_matched;
1672
1673 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1674 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1675
1676 /*
1677 * If the host uses TSC clock, then passthrough TSC as stable
1678 * to the guest.
1679 */
b48aa97e 1680 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1681 &ka->master_kernel_ns,
1682 &ka->master_cycle_now);
1683
16a96021 1684 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1685 && !backwards_tsc_observed
1686 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1687
d828199e
MT		 1688 if (ka->use_master_clock)
1689 atomic_set(&kvm_guest_has_master_clock, 1);
1690
1691 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1692 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1693 vcpus_matched);
d828199e
MT		 1694#endif
1695}
1696
2860c4b1
PB		 1697void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1698{
1699 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1700}
1701
2e762ff7
MT		 1702static void kvm_gen_update_masterclock(struct kvm *kvm)
1703{
1704#ifdef CONFIG_X86_64
1705 int i;
1706 struct kvm_vcpu *vcpu;
1707 struct kvm_arch *ka = &kvm->arch;
1708
1709 spin_lock(&ka->pvclock_gtod_sync_lock);
1710 kvm_make_mclock_inprogress_request(kvm);
1711 /* no guest entries from this point */
1712 pvclock_update_vm_gtod_copy(kvm);
1713
1714 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1715 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1716
1717 /* guest entries allowed */
1718 kvm_for_each_vcpu(i, vcpu, kvm)
1719 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1720
1721 spin_unlock(&ka->pvclock_gtod_sync_lock);
1722#endif
1723}
1724
108b249c
PB		 1725static u64 __get_kvmclock_ns(struct kvm *kvm)
1726{
1727 struct kvm_vcpu *vcpu = kvm_get_vcpu(kvm, 0);
1728 struct kvm_arch *ka = &kvm->arch;
1729 s64 ns;
1730
1731 if (vcpu->arch.hv_clock.flags & PVCLOCK_TSC_STABLE_BIT) {
1732 u64 tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1733 ns = __pvclock_read_cycles(&vcpu->arch.hv_clock, tsc);
1734 } else {
1735 ns = ktime_get_boot_ns() + ka->kvmclock_offset;
1736 }
1737
1738 return ns;
1739}
1740
1741u64 get_kvmclock_ns(struct kvm *kvm)
1742{
1743 unsigned long flags;
1744 s64 ns;
1745
1746 local_irq_save(flags);
1747 ns = __get_kvmclock_ns(kvm);
1748 local_irq_restore(flags);
1749
1750 return ns;
1751}
1752
0d6dd2ff
PB		 1753static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1754{
1755 struct kvm_vcpu_arch *vcpu = &v->arch;
1756 struct pvclock_vcpu_time_info guest_hv_clock;
1757
1758 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1759 &guest_hv_clock, sizeof(guest_hv_clock))))
1760 return;
1761
1762 /* This VCPU is paused, but it's legal for a guest to read another
1763 * VCPU's kvmclock, so we really have to follow the specification where
1764 * it says that version is odd if data is being modified, and even after
1765 * it is consistent.
1766 *
1767 * Version field updates must be kept separate. This is because
1768 * kvm_write_guest_cached might use a "rep movs" instruction, and
1769 * writes within a string instruction are weakly ordered. So there
1770 * are three writes overall.
1771 *
1772 * As a small optimization, only write the version field in the first
1773 * and third write. The vcpu->pv_time cache is still valid, because the
1774 * version field is the first in the struct.
1775 */
1776 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1777
1778 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1779 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1780 &vcpu->hv_clock,
1781 sizeof(vcpu->hv_clock.version));
1782
1783 smp_wmb();
1784
1785 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1786 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1787
1788 if (vcpu->pvclock_set_guest_stopped_request) {
1789 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1790 vcpu->pvclock_set_guest_stopped_request = false;
1791 }
1792
1793 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1794
1795 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1796 &vcpu->hv_clock,
1797 sizeof(vcpu->hv_clock));
1798
1799 smp_wmb();
1800
1801 vcpu->hv_clock.version++;
1802 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1803 &vcpu->hv_clock,
1804 sizeof(vcpu->hv_clock.version));
1805}
1806
34c238a1 1807static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1808{
78db6a50 1809 unsigned long flags, tgt_tsc_khz;
18068523 1810 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1811 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1812 s64 kernel_ns;
d828199e 1813 u64 tsc_timestamp, host_tsc;
51d59c6b 1814 u8 pvclock_flags;
d828199e
MT		 1815 bool use_master_clock;
1816
1817 kernel_ns = 0;
1818 host_tsc = 0;
18068523 1819
d828199e
MT		 1820 /*
1821 * If the host uses TSC clock, then passthrough TSC as stable
1822 * to the guest.
1823 */
1824 spin_lock(&ka->pvclock_gtod_sync_lock);
1825 use_master_clock = ka->use_master_clock;
1826 if (use_master_clock) {
1827 host_tsc = ka->master_cycle_now;
1828 kernel_ns = ka->master_kernel_ns;
1829 }
1830 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1831
1832 /* Keep irq disabled to prevent changes to the clock */
1833 local_irq_save(flags);
78db6a50
PB		 1834 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1835 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1836 local_irq_restore(flags);
1837 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1838 return 1;
1839 }
d828199e 1840 if (!use_master_clock) {
4ea1636b 1841 host_tsc = rdtsc();
108b249c 1842 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1843 }
1844
4ba76538 1845 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1846
c285545f
ZA		 1847 /*
1848 * We may have to catch up the TSC to match elapsed wall clock
1849 * time for two reasons, even if kvmclock is used.
1850 * 1) CPU could have been running below the maximum TSC rate
1851 * 2) Broken TSC compensation resets the base at each VCPU
1852 * entry to avoid unknown leaps of TSC even when running
1853 * again on the same CPU. This may cause apparent elapsed
1854 * time to disappear, and the guest to stand still or run
1855 * very slowly.
1856 */
1857 if (vcpu->tsc_catchup) {
1858 u64 tsc = compute_guest_tsc(v, kernel_ns);
1859 if (tsc > tsc_timestamp) {
f1e2b260 1860 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1861 tsc_timestamp = tsc;
1862 }
50d0a0f9
GH		 1863 }
1864
18068523
GOC		 1865 local_irq_restore(flags);
1866
0d6dd2ff 1867 /* With all the info we got, fill in the values */
18068523 1868
78db6a50
PB		 1869 if (kvm_has_tsc_control)
1870 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1871
1872 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1873 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1874 &vcpu->hv_clock.tsc_shift,
1875 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1876 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1877 }
1878
1d5f066e 1879 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1880 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1881 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1882
d828199e 1883 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1884 pvclock_flags = 0;
d828199e
MT		 1885 if (use_master_clock)
1886 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1887
78c0337a
MT		 1888 vcpu->hv_clock.flags = pvclock_flags;
1889
095cf55d
PB		 1890 if (vcpu->pv_time_enabled)
1891 kvm_setup_pvclock_page(v);
1892 if (v == kvm_get_vcpu(v->kvm, 0))
1893 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1894 return 0;
c8076604
GH		 1895}
1896
0061d53d
MT		 1897/*
1898 * kvmclock updates which are isolated to a given vcpu, such as
1899 * vcpu->cpu migration, should not allow system_timestamp from
1900 * the rest of the vcpus to remain static. Otherwise ntp frequency
1901 * correction applies to one vcpu's system_timestamp but not
1902 * the others.
1903 *
1904 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1905 * We need to rate-limit these requests though, as they can
1906 * considerably slow guests that have a large number of vcpus.
1907 * The time for a remote vcpu to update its kvmclock is bound
1908 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1909 */
1910
7e44e449
AJ		 1911#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1912
1913static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1914{
1915 int i;
7e44e449
AJ		 1916 struct delayed_work *dwork = to_delayed_work(work);
1917 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1918 kvmclock_update_work);
1919 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1920 struct kvm_vcpu *vcpu;
1921
1922 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1923 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1924 kvm_vcpu_kick(vcpu);
1925 }
1926}
1927
7e44e449
AJ		 1928static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1929{
1930 struct kvm *kvm = v->kvm;
1931
105b21bb 1932 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1933 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1934 KVMCLOCK_UPDATE_DELAY);
1935}
1936
332967a3
AJ		 1937#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1938
1939static void kvmclock_sync_fn(struct work_struct *work)
1940{
1941 struct delayed_work *dwork = to_delayed_work(work);
1942 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1943 kvmclock_sync_work);
1944 struct kvm *kvm = container_of(ka, struct kvm, arch);
1945
630994b3
MT		 1946 if (!kvmclock_periodic_sync)
1947 return;
1948
332967a3
AJ		 1949 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1950 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1951 KVMCLOCK_SYNC_PERIOD);
1952}
1953
890ca9ae 1954static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1955{
890ca9ae
HY		 1956 u64 mcg_cap = vcpu->arch.mcg_cap;
1957 unsigned bank_num = mcg_cap & 0xff;
1958
15c4a640 1959 switch (msr) {
15c4a640 1960 case MSR_IA32_MCG_STATUS:
890ca9ae 1961 vcpu->arch.mcg_status = data;
15c4a640 1962 break;
c7ac679c 1963 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1964 if (!(mcg_cap & MCG_CTL_P))
1965 return 1;
1966 if (data != 0 && data != ~(u64)0)
1967 return -1;
1968 vcpu->arch.mcg_ctl = data;
1969 break;
1970 default:
1971 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1972 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1973 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1974 /* only 0 or all 1s can be written to IA32_MCi_CTL
1975 * some Linux kernels though clear bit 10 in bank 4 to
1976 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1977 * this to avoid an uncatched #GP in the guest
1978 */
890ca9ae 1979 if ((offset & 0x3) == 0 &&
114be429 1980 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1981 return -1;
1982 vcpu->arch.mce_banks[offset] = data;
1983 break;
1984 }
1985 return 1;
1986 }
1987 return 0;
1988}
1989
ffde22ac
ES		 1990static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1991{
1992 struct kvm *kvm = vcpu->kvm;
1993 int lm = is_long_mode(vcpu);
1994 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1995 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1996 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1997 : kvm->arch.xen_hvm_config.blob_size_32;
1998 u32 page_num = data & ~PAGE_MASK;
1999 u64 page_addr = data & PAGE_MASK;
2000 u8 *page;
2001 int r;
2002
2003 r = -E2BIG;
2004 if (page_num >= blob_size)
2005 goto out;
2006 r = -ENOMEM;
ff5c2c03
SL		 2007 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2008 if (IS_ERR(page)) {
2009 r = PTR_ERR(page);
ffde22ac 2010 goto out;
ff5c2c03 2011 }
54bf36aa 2012 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2013 goto out_free;
2014 r = 0;
2015out_free:
2016 kfree(page);
2017out:
2018 return r;
2019}
2020
344d9588
GN		 2021static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2022{
2023 gpa_t gpa = data & ~0x3f;
2024
4a969980 2025 /* Bits 2:5 are reserved, Should be zero */
6adba527 2026 if (data & 0x3c)
344d9588
GN		 2027 return 1;
2028
2029 vcpu->arch.apf.msr_val = data;
2030
2031 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2032 kvm_clear_async_pf_completion_queue(vcpu);
2033 kvm_async_pf_hash_reset(vcpu);
2034 return 0;
2035 }
2036
8f964525
AH		 2037 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2038 sizeof(u32)))
344d9588
GN		 2039 return 1;
2040
6adba527 2041 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2042 kvm_async_pf_wakeup_all(vcpu);
2043 return 0;
2044}
2045
12f9a48f
GC		 2046static void kvmclock_reset(struct kvm_vcpu *vcpu)
2047{
0b79459b 2048 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2049}
2050
c9aaa895
GC		 2051static void record_steal_time(struct kvm_vcpu *vcpu)
2052{
2053 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2054 return;
2055
2056 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2057 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2058 return;
2059
35f3fae1
WL		 2060 if (vcpu->arch.st.steal.version & 1)
2061 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2062
2063 vcpu->arch.st.steal.version += 1;
2064
2065 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2066 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2067
2068 smp_wmb();
2069
c54cdf14
LC		 2070 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2071 vcpu->arch.st.last_steal;
2072 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2073
2074 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2075 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2076
2077 smp_wmb();
2078
2079 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2080
2081 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2082 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2083}
2084
8fe8ab46 2085int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2086{
5753785f 2087 bool pr = false;
8fe8ab46
WA		 2088 u32 msr = msr_info->index;
2089 u64 data = msr_info->data;
5753785f 2090
15c4a640 2091 switch (msr) {
2e32b719
BP		 2092 case MSR_AMD64_NB_CFG:
2093 case MSR_IA32_UCODE_REV:
2094 case MSR_IA32_UCODE_WRITE:
2095 case MSR_VM_HSAVE_PA:
2096 case MSR_AMD64_PATCH_LOADER:
2097 case MSR_AMD64_BU_CFG2:
2098 break;
2099
15c4a640 2100 case MSR_EFER:
b69e8cae 2101 return set_efer(vcpu, data);
8f1589d9
AP		 2102 case MSR_K7_HWCR:
2103 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2104 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2105 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2106 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2107 if (data != 0) {
a737f256
CD		 2108 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2109 data);
8f1589d9
AP		 2110 return 1;
2111 }
15c4a640 2112 break;
f7c6d140
AP		 2113 case MSR_FAM10H_MMIO_CONF_BASE:
2114 if (data != 0) {
a737f256
CD		 2115 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2116 "0x%llx\n", data);
f7c6d140
AP		 2117 return 1;
2118 }
15c4a640 2119 break;
b5e2fec0
AG		 2120 case MSR_IA32_DEBUGCTLMSR:
2121 if (!data) {
2122 /* We support the non-activated case already */
2123 break;
2124 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2125 /* Values other than LBR and BTF are vendor-specific,
2126 thus reserved and should throw a #GP */
2127 return 1;
2128 }
a737f256
CD		 2129 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2130 __func__, data);
b5e2fec0 2131 break;
9ba075a6 2132 case 0x200 ... 0x2ff:
ff53604b 2133 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2134 case MSR_IA32_APICBASE:
58cb628d 2135 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2136 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2137 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2138 case MSR_IA32_TSCDEADLINE:
2139 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2140 break;
ba904635
WA		 2141 case MSR_IA32_TSC_ADJUST:
2142 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2143 if (!msr_info->host_initiated) {
d913b904 2144 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2145 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2146 }
2147 vcpu->arch.ia32_tsc_adjust_msr = data;
2148 }
2149 break;
15c4a640 2150 case MSR_IA32_MISC_ENABLE:
ad312c7c 2151 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2152 break;
64d60670
PB		 2153 case MSR_IA32_SMBASE:
2154 if (!msr_info->host_initiated)
2155 return 1;
2156 vcpu->arch.smbase = data;
2157 break;
11c6bffa 2158 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2159 case MSR_KVM_WALL_CLOCK:
2160 vcpu->kvm->arch.wall_clock = data;
2161 kvm_write_wall_clock(vcpu->kvm, data);
2162 break;
11c6bffa 2163 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2164 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2165 struct kvm_arch *ka = &vcpu->kvm->arch;
2166
12f9a48f 2167 kvmclock_reset(vcpu);
18068523 2168
54750f2c
MT		 2169 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2170 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2171
2172 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2173 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2174 &vcpu->requests);
2175
2176 ka->boot_vcpu_runs_old_kvmclock = tmp;
2177 }
2178
18068523 2179 vcpu->arch.time = data;
0061d53d 2180 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2181
2182 /* we verify if the enable bit is set... */
2183 if (!(data & 1))
2184 break;
2185
0b79459b 2186 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2187 &vcpu->arch.pv_time, data & ~1ULL,
2188 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2189 vcpu->arch.pv_time_enabled = false;
2190 else
2191 vcpu->arch.pv_time_enabled = true;
32cad84f 2192
18068523
GOC		 2193 break;
2194 }
344d9588
GN		 2195 case MSR_KVM_ASYNC_PF_EN:
2196 if (kvm_pv_enable_async_pf(vcpu, data))
2197 return 1;
2198 break;
c9aaa895
GC		 2199 case MSR_KVM_STEAL_TIME:
2200
2201 if (unlikely(!sched_info_on()))
2202 return 1;
2203
2204 if (data & KVM_STEAL_RESERVED_MASK)
2205 return 1;
2206
2207 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2208 data & KVM_STEAL_VALID_BITS,
2209 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2210 return 1;
2211
2212 vcpu->arch.st.msr_val = data;
2213
2214 if (!(data & KVM_MSR_ENABLED))
2215 break;
2216
c9aaa895
GC		 2217 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2218
2219 break;
ae7a2a3f
MT		 2220 case MSR_KVM_PV_EOI_EN:
2221 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2222 return 1;
2223 break;
c9aaa895 2224
890ca9ae
HY		 2225 case MSR_IA32_MCG_CTL:
2226 case MSR_IA32_MCG_STATUS:
81760dcc 2227 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2228 return set_msr_mce(vcpu, msr, data);
71db6023 2229
6912ac32
WH		 2230 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2231 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2232 pr = true; /* fall through */
2233 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2234 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2235 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2236 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2237
2238 if (pr || data != 0)
a737f256
CD		 2239 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2240 "0x%x data 0x%llx\n", msr, data);
5753785f 2241 break;
84e0cefa
JS		 2242 case MSR_K7_CLK_CTL:
2243 /*
2244 * Ignore all writes to this no longer documented MSR.
2245 * Writes are only relevant for old K7 processors,
2246 * all pre-dating SVM, but a recommended workaround from
4a969980 2247 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2248 * affected processor models on the command line, hence
2249 * the need to ignore the workaround.
2250 */
2251 break;
55cd8e5a 2252 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2253 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2254 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2255 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2256 return kvm_hv_set_msr_common(vcpu, msr, data,
2257 msr_info->host_initiated);
91c9c3ed 2258 case MSR_IA32_BBL_CR_CTL3:
2259 /* Drop writes to this legacy MSR -- see rdmsr
2260 * counterpart for further detail.
2261 */
796f4687 2262 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2263 break;
2b036c6b
BO		 2264 case MSR_AMD64_OSVW_ID_LENGTH:
2265 if (!guest_cpuid_has_osvw(vcpu))
2266 return 1;
2267 vcpu->arch.osvw.length = data;
2268 break;
2269 case MSR_AMD64_OSVW_STATUS:
2270 if (!guest_cpuid_has_osvw(vcpu))
2271 return 1;
2272 vcpu->arch.osvw.status = data;
2273 break;
15c4a640 2274 default:
ffde22ac
ES		 2275 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2276 return xen_hvm_config(vcpu, data);
c6702c9d 2277 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2278 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2279 if (!ignore_msrs) {
ae0f5499 2280 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2281 msr, data);
ed85c068
AP		 2282 return 1;
2283 } else {
796f4687 2284 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2285 msr, data);
ed85c068
AP		 2286 break;
2287 }
15c4a640
CO		 2288 }
2289 return 0;
2290}
2291EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2292
2293
2294/*
2295 * Reads an msr value (of 'msr_index') into 'pdata'.
2296 * Returns 0 on success, non-0 otherwise.
2297 * Assumes vcpu_load() was already called.
2298 */
609e36d3 2299int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2300{
609e36d3 2301 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2302}
ff651cb6 2303EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2304
890ca9ae 2305static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2306{
2307 u64 data;
890ca9ae
HY		 2308 u64 mcg_cap = vcpu->arch.mcg_cap;
2309 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2310
2311 switch (msr) {
15c4a640
CO		 2312 case MSR_IA32_P5_MC_ADDR:
2313 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2314 data = 0;
2315 break;
15c4a640 2316 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2317 data = vcpu->arch.mcg_cap;
2318 break;
c7ac679c 2319 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2320 if (!(mcg_cap & MCG_CTL_P))
2321 return 1;
2322 data = vcpu->arch.mcg_ctl;
2323 break;
2324 case MSR_IA32_MCG_STATUS:
2325 data = vcpu->arch.mcg_status;
2326 break;
2327 default:
2328 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2329 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2330 u32 offset = msr - MSR_IA32_MC0_CTL;
2331 data = vcpu->arch.mce_banks[offset];
2332 break;
2333 }
2334 return 1;
2335 }
2336 *pdata = data;
2337 return 0;
2338}
2339
609e36d3 2340int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2341{
609e36d3 2342 switch (msr_info->index) {
890ca9ae 2343 case MSR_IA32_PLATFORM_ID:
15c4a640 2344 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2345 case MSR_IA32_DEBUGCTLMSR:
2346 case MSR_IA32_LASTBRANCHFROMIP:
2347 case MSR_IA32_LASTBRANCHTOIP:
2348 case MSR_IA32_LASTINTFROMIP:
2349 case MSR_IA32_LASTINTTOIP:
60af2ecd 2350 case MSR_K8_SYSCFG:
3afb1121
PB		 2351 case MSR_K8_TSEG_ADDR:
2352 case MSR_K8_TSEG_MASK:
60af2ecd 2353 case MSR_K7_HWCR:
61a6bd67 2354 case MSR_VM_HSAVE_PA:
1fdbd48c 2355 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2356 case MSR_AMD64_NB_CFG:
f7c6d140 2357 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2358 case MSR_AMD64_BU_CFG2:
0c2df2a1 2359 case MSR_IA32_PERF_CTL:
609e36d3 2360 msr_info->data = 0;
15c4a640 2361 break;
6912ac32
WH		 2362 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2363 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2364 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2365 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2366 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2367 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2368 msr_info->data = 0;
5753785f 2369 break;
742bc670 2370 case MSR_IA32_UCODE_REV:
609e36d3 2371 msr_info->data = 0x100000000ULL;
742bc670 2372 break;
9ba075a6 2373 case MSR_MTRRcap:
9ba075a6 2374 case 0x200 ... 0x2ff:
ff53604b 2375 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2376 case 0xcd: /* fsb frequency */
609e36d3 2377 msr_info->data = 3;
15c4a640 2378 break;
7b914098
JS		 2379 /*
2380 * MSR_EBC_FREQUENCY_ID
2381 * Conservative value valid for even the basic CPU models.
2382 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2383 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2384 * and 266MHz for model 3, or 4. Set Core Clock
2385 * Frequency to System Bus Frequency Ratio to 1 (bits
2386 * 31:24) even though these are only valid for CPU
2387 * models > 2, however guests may end up dividing or
2388 * multiplying by zero otherwise.
2389 */
2390 case MSR_EBC_FREQUENCY_ID:
609e36d3 2391 msr_info->data = 1 << 24;
7b914098 2392 break;
15c4a640 2393 case MSR_IA32_APICBASE:
609e36d3 2394 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2395 break;
0105d1a5 2396 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2397 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2398 break;
a3e06bbe 2399 case MSR_IA32_TSCDEADLINE:
609e36d3 2400 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2401 break;
ba904635 2402 case MSR_IA32_TSC_ADJUST:
609e36d3 2403 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2404 break;
15c4a640 2405 case MSR_IA32_MISC_ENABLE:
609e36d3 2406 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2407 break;
64d60670
PB		 2408 case MSR_IA32_SMBASE:
2409 if (!msr_info->host_initiated)
2410 return 1;
2411 msr_info->data = vcpu->arch.smbase;
15c4a640 2412 break;
847f0ad8
AG		 2413 case MSR_IA32_PERF_STATUS:
2414 /* TSC increment by tick */
609e36d3 2415 msr_info->data = 1000ULL;
847f0ad8 2416 /* CPU multiplier */
b0996ae4 2417 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2418 break;
15c4a640 2419 case MSR_EFER:
609e36d3 2420 msr_info->data = vcpu->arch.efer;
15c4a640 2421 break;
18068523 2422 case MSR_KVM_WALL_CLOCK:
11c6bffa 2423 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2424 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2425 break;
2426 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2427 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2428 msr_info->data = vcpu->arch.time;
18068523 2429 break;
344d9588 2430 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2431 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2432 break;
c9aaa895 2433 case MSR_KVM_STEAL_TIME:
609e36d3 2434 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2435 break;
1d92128f 2436 case MSR_KVM_PV_EOI_EN:
609e36d3 2437 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2438 break;
890ca9ae
HY		 2439 case MSR_IA32_P5_MC_ADDR:
2440 case MSR_IA32_P5_MC_TYPE:
2441 case MSR_IA32_MCG_CAP:
2442 case MSR_IA32_MCG_CTL:
2443 case MSR_IA32_MCG_STATUS:
81760dcc 2444 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2445 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2446 case MSR_K7_CLK_CTL:
2447 /*
2448 * Provide expected ramp-up count for K7. All other
2449 * are set to zero, indicating minimum divisors for
2450 * every field.
2451 *
2452 * This prevents guest kernels on AMD host with CPU
2453 * type 6, model 8 and higher from exploding due to
2454 * the rdmsr failing.
2455 */
609e36d3 2456 msr_info->data = 0x20000000;
84e0cefa 2457 break;
55cd8e5a 2458 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2459 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2460 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2461 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2462 return kvm_hv_get_msr_common(vcpu,
2463 msr_info->index, &msr_info->data);
55cd8e5a 2464 break;
91c9c3ed 2465 case MSR_IA32_BBL_CR_CTL3:
2466 /* This legacy MSR exists but isn't fully documented in current
2467 * silicon. It is however accessed by winxp in very narrow
2468 * scenarios where it sets bit #19, itself documented as
2469 * a "reserved" bit. Best effort attempt to source coherent
2470 * read data here should the balance of the register be
2471 * interpreted by the guest:
2472 *
2473 * L2 cache control register 3: 64GB range, 256KB size,
2474 * enabled, latency 0x1, configured
2475 */
609e36d3 2476 msr_info->data = 0xbe702111;
91c9c3ed 2477 break;
2b036c6b
BO		 2478 case MSR_AMD64_OSVW_ID_LENGTH:
2479 if (!guest_cpuid_has_osvw(vcpu))
2480 return 1;
609e36d3 2481 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2482 break;
2483 case MSR_AMD64_OSVW_STATUS:
2484 if (!guest_cpuid_has_osvw(vcpu))
2485 return 1;
609e36d3 2486 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2487 break;
15c4a640 2488 default:
c6702c9d 2489 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2490 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2491 if (!ignore_msrs) {
ae0f5499
BD		 2492 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2493 msr_info->index);
ed85c068
AP		 2494 return 1;
2495 } else {
609e36d3
PB		 2496 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2497 msr_info->data = 0;
ed85c068
AP		 2498 }
2499 break;
15c4a640 2500 }
15c4a640
CO		 2501 return 0;
2502}
2503EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2504
313a3dc7
CO		 2505/*
2506 * Read or write a bunch of msrs. All parameters are kernel addresses.
2507 *
2508 * @return number of msrs set successfully.
2509 */
2510static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2511 struct kvm_msr_entry *entries,
2512 int (*do_msr)(struct kvm_vcpu *vcpu,
2513 unsigned index, u64 *data))
2514{
f656ce01 2515 int i, idx;
313a3dc7 2516
f656ce01 2517 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2518 for (i = 0; i < msrs->nmsrs; ++i)
2519 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2520 break;
f656ce01 2521 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2522
313a3dc7
CO		 2523 return i;
2524}
2525
2526/*
2527 * Read or write a bunch of msrs. Parameters are user addresses.
2528 *
2529 * @return number of msrs set successfully.
2530 */
2531static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2532 int (*do_msr)(struct kvm_vcpu *vcpu,
2533 unsigned index, u64 *data),
2534 int writeback)
2535{
2536 struct kvm_msrs msrs;
2537 struct kvm_msr_entry *entries;
2538 int r, n;
2539 unsigned size;
2540
2541 r = -EFAULT;
2542 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2543 goto out;
2544
2545 r = -E2BIG;
2546 if (msrs.nmsrs >= MAX_IO_MSRS)
2547 goto out;
2548
313a3dc7 2549 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2550 entries = memdup_user(user_msrs->entries, size);
2551 if (IS_ERR(entries)) {
2552 r = PTR_ERR(entries);
313a3dc7 2553 goto out;
ff5c2c03 2554 }
313a3dc7
CO		 2555
2556 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2557 if (r < 0)
2558 goto out_free;
2559
2560 r = -EFAULT;
2561 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2562 goto out_free;
2563
2564 r = n;
2565
2566out_free:
7a73c028 2567 kfree(entries);
313a3dc7
CO		 2568out:
2569 return r;
2570}
2571
784aa3d7 2572int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2573{
2574 int r;
2575
2576 switch (ext) {
2577 case KVM_CAP_IRQCHIP:
2578 case KVM_CAP_HLT:
2579 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2580 case KVM_CAP_SET_TSS_ADDR:
07716717 2581 case KVM_CAP_EXT_CPUID:
9c15bb1d 2582 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2583 case KVM_CAP_CLOCKSOURCE:
7837699f 2584 case KVM_CAP_PIT:
a28e4f5a 2585 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2586 case KVM_CAP_MP_STATE:
ed848624 2587 case KVM_CAP_SYNC_MMU:
a355c85c 2588 case KVM_CAP_USER_NMI:
52d939a0 2589 case KVM_CAP_REINJECT_CONTROL:
4925663a 2590 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2591 case KVM_CAP_IOEVENTFD:
f848a5a8 2592 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2593 case KVM_CAP_PIT2:
e9f42757 2594 case KVM_CAP_PIT_STATE2:
b927a3ce 2595 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2596 case KVM_CAP_XEN_HVM:
afbcf7ab 2597 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2598 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2599 case KVM_CAP_HYPERV:
10388a07 2600 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2601 case KVM_CAP_HYPERV_SPIN:
5c919412 2602 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2603 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2604 case KVM_CAP_DEBUGREGS:
d2be1651 2605 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2606 case KVM_CAP_XSAVE:
344d9588 2607 case KVM_CAP_ASYNC_PF:
92a1f12d 2608 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2609 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2610 case KVM_CAP_READONLY_MEM:
5f66b620 2611 case KVM_CAP_HYPERV_TIME:
100943c5 2612 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2613 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2614 case KVM_CAP_ENABLE_CAP_VM:
2615 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2616 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2617 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2618#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2619 case KVM_CAP_ASSIGN_DEV_IRQ:
2620 case KVM_CAP_PCI_2_3:
2621#endif
018d00d2
ZX		 2622 r = 1;
2623 break;
6d396b55
PB		 2624 case KVM_CAP_X86_SMM:
2625 /* SMBASE is usually relocated above 1M on modern chipsets,
2626 * and SMM handlers might indeed rely on 4G segment limits,
2627 * so do not report SMM to be available if real mode is
2628 * emulated via vm86 mode. Still, do not go to great lengths
2629 * to avoid userspace's usage of the feature, because it is a
2630 * fringe case that is not enabled except via specific settings
2631 * of the module parameters.
2632 */
2633 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2634 break;
542472b5
LV		 2635 case KVM_CAP_COALESCED_MMIO:
2636 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2637 break;
774ead3a
AK		 2638 case KVM_CAP_VAPIC:
2639 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2640 break;
f725230a 2641 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2642 r = KVM_SOFT_MAX_VCPUS;
2643 break;
2644 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2645 r = KVM_MAX_VCPUS;
2646 break;
a988b910 2647 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2648 r = KVM_USER_MEM_SLOTS;
a988b910 2649 break;
a68a6a72
MT		 2650 case KVM_CAP_PV_MMU: /* obsolete */
2651 r = 0;
2f333bcb 2652 break;
4cee4b72 2653#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2654 case KVM_CAP_IOMMU:
a1b60c1c 2655 r = iommu_present(&pci_bus_type);
62c476c7 2656 break;
4cee4b72 2657#endif
890ca9ae
HY		 2658 case KVM_CAP_MCE:
2659 r = KVM_MAX_MCE_BANKS;
2660 break;
2d5b5a66 2661 case KVM_CAP_XCRS:
d366bf7e 2662 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2663 break;
92a1f12d
JR		 2664 case KVM_CAP_TSC_CONTROL:
2665 r = kvm_has_tsc_control;
2666 break;
37131313
RK		 2667 case KVM_CAP_X2APIC_API:
2668 r = KVM_X2APIC_API_VALID_FLAGS;
2669 break;
018d00d2
ZX		 2670 default:
2671 r = 0;
2672 break;
2673 }
2674 return r;
2675
2676}
2677
043405e1
CO		 2678long kvm_arch_dev_ioctl(struct file *filp,
2679 unsigned int ioctl, unsigned long arg)
2680{
2681 void __user *argp = (void __user *)arg;
2682 long r;
2683
2684 switch (ioctl) {
2685 case KVM_GET_MSR_INDEX_LIST: {
2686 struct kvm_msr_list __user *user_msr_list = argp;
2687 struct kvm_msr_list msr_list;
2688 unsigned n;
2689
2690 r = -EFAULT;
2691 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2692 goto out;
2693 n = msr_list.nmsrs;
62ef68bb 2694 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2695 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2696 goto out;
2697 r = -E2BIG;
e125e7b6 2698 if (n < msr_list.nmsrs)
043405e1
CO		 2699 goto out;
2700 r = -EFAULT;
2701 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2702 num_msrs_to_save * sizeof(u32)))
2703 goto out;
e125e7b6 2704 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2705 &emulated_msrs,
62ef68bb 2706 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2707 goto out;
2708 r = 0;
2709 break;
2710 }
9c15bb1d
BP		 2711 case KVM_GET_SUPPORTED_CPUID:
2712 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2713 struct kvm_cpuid2 __user *cpuid_arg = argp;
2714 struct kvm_cpuid2 cpuid;
2715
2716 r = -EFAULT;
2717 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2718 goto out;
9c15bb1d
BP		 2719
2720 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2721 ioctl);
674eea0f
AK		 2722 if (r)
2723 goto out;
2724
2725 r = -EFAULT;
2726 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2727 goto out;
2728 r = 0;
2729 break;
2730 }
890ca9ae 2731 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2732 r = -EFAULT;
c45dcc71
AR		 2733 if (copy_to_user(argp, &kvm_mce_cap_supported,
2734 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2735 goto out;
2736 r = 0;
2737 break;
2738 }
043405e1
CO		 2739 default:
2740 r = -EINVAL;
2741 }
2742out:
2743 return r;
2744}
2745
f5f48ee1
SY		 2746static void wbinvd_ipi(void *garbage)
2747{
2748 wbinvd();
2749}
2750
2751static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2752{
e0f0bbc5 2753 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2754}
2755
2860c4b1
PB		 2756static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2757{
2758 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2759}
2760
313a3dc7
CO		 2761void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2762{
f5f48ee1
SY		 2763 /* Address WBINVD may be executed by guest */
2764 if (need_emulate_wbinvd(vcpu)) {
2765 if (kvm_x86_ops->has_wbinvd_exit())
2766 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2767 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2768 smp_call_function_single(vcpu->cpu,
2769 wbinvd_ipi, NULL, 1);
2770 }
2771
313a3dc7 2772 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2773
0dd6a6ed
ZA		 2774 /* Apply any externally detected TSC adjustments (due to suspend) */
2775 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2776 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2777 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2778 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2779 }
8f6055cb 2780
48434c20 2781 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2782 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2783 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2784 if (tsc_delta < 0)
2785 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2786
c285545f 2787 if (check_tsc_unstable()) {
07c1419a 2788 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2789 vcpu->arch.last_guest_tsc);
a545ab6a 2790 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2791 vcpu->arch.tsc_catchup = 1;
c285545f 2792 }
e12c8f36
WL		 2793 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2794 kvm_x86_ops->set_hv_timer(vcpu,
498f8162 2795 kvm_get_lapic_target_expiration_tsc(vcpu)))
e12c8f36 2796 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2797 /*
2798 * On a host with synchronized TSC, there is no need to update
2799 * kvmclock on vcpu->cpu migration
2800 */
2801 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2802 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2803 if (vcpu->cpu != cpu)
2804 kvm_migrate_timers(vcpu);
e48672fa 2805 vcpu->cpu = cpu;
6b7d7e76 2806 }
c9aaa895 2807
c9aaa895 2808 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2809}
2810
2811void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2812{
02daab21 2813 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2814 kvm_put_guest_fpu(vcpu);
4ea1636b 2815 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2816}
2817
313a3dc7
CO		 2818static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2819 struct kvm_lapic_state *s)
2820{
d62caabb
AS		 2821 if (vcpu->arch.apicv_active)
2822 kvm_x86_ops->sync_pir_to_irr(vcpu);
2823
a92e2543 2824 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2825}
2826
2827static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2828 struct kvm_lapic_state *s)
2829{
a92e2543
RK		 2830 int r;
2831
2832 r = kvm_apic_set_state(vcpu, s);
2833 if (r)
2834 return r;
cb142eb7 2835 update_cr8_intercept(vcpu);
313a3dc7
CO		 2836
2837 return 0;
2838}
2839
127a457a
MG		 2840static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2841{
2842 return (!lapic_in_kernel(vcpu) ||
2843 kvm_apic_accept_pic_intr(vcpu));
2844}
2845
782d422b
MG		 2846/*
2847 * if userspace requested an interrupt window, check that the
2848 * interrupt window is open.
2849 *
2850 * No need to exit to userspace if we already have an interrupt queued.
2851 */
2852static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2853{
2854 return kvm_arch_interrupt_allowed(vcpu) &&
2855 !kvm_cpu_has_interrupt(vcpu) &&
2856 !kvm_event_needs_reinjection(vcpu) &&
2857 kvm_cpu_accept_dm_intr(vcpu);
2858}
2859
f77bc6a4
ZX		 2860static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2861 struct kvm_interrupt *irq)
2862{
02cdb50f 2863 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2864 return -EINVAL;
1c1a9ce9
SR		 2865
2866 if (!irqchip_in_kernel(vcpu->kvm)) {
2867 kvm_queue_interrupt(vcpu, irq->irq, false);
2868 kvm_make_request(KVM_REQ_EVENT, vcpu);
2869 return 0;
2870 }
2871
2872 /*
2873 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2874 * fail for in-kernel 8259.
2875 */
2876 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2877 return -ENXIO;
f77bc6a4 2878
1c1a9ce9
SR		 2879 if (vcpu->arch.pending_external_vector != -1)
2880 return -EEXIST;
f77bc6a4 2881
1c1a9ce9 2882 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2883 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2884 return 0;
2885}
2886
c4abb7c9
JK		 2887static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2888{
c4abb7c9 2889 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2890
2891 return 0;
2892}
2893
f077825a
PB		 2894static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2895{
64d60670
PB		 2896 kvm_make_request(KVM_REQ_SMI, vcpu);
2897
f077825a
PB		 2898 return 0;
2899}
2900
b209749f
AK		 2901static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2902 struct kvm_tpr_access_ctl *tac)
2903{
2904 if (tac->flags)
2905 return -EINVAL;
2906 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2907 return 0;
2908}
2909
890ca9ae
HY		 2910static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2911 u64 mcg_cap)
2912{
2913 int r;
2914 unsigned bank_num = mcg_cap & 0xff, bank;
2915
2916 r = -EINVAL;
a9e38c3e 2917 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2918 goto out;
c45dcc71 2919 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2920 goto out;
2921 r = 0;
2922 vcpu->arch.mcg_cap = mcg_cap;
2923 /* Init IA32_MCG_CTL to all 1s */
2924 if (mcg_cap & MCG_CTL_P)
2925 vcpu->arch.mcg_ctl = ~(u64)0;
2926 /* Init IA32_MCi_CTL to all 1s */
2927 for (bank = 0; bank < bank_num; bank++)
2928 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 2929
2930 if (kvm_x86_ops->setup_mce)
2931 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 2932out:
2933 return r;
2934}
2935
2936static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2937 struct kvm_x86_mce *mce)
2938{
2939 u64 mcg_cap = vcpu->arch.mcg_cap;
2940 unsigned bank_num = mcg_cap & 0xff;
2941 u64 *banks = vcpu->arch.mce_banks;
2942
2943 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2944 return -EINVAL;
2945 /*
2946 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2947 * reporting is disabled
2948 */
2949 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2950 vcpu->arch.mcg_ctl != ~(u64)0)
2951 return 0;
2952 banks += 4 * mce->bank;
2953 /*
2954 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2955 * reporting is disabled for the bank
2956 */
2957 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2958 return 0;
2959 if (mce->status & MCI_STATUS_UC) {
2960 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2961 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2962 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2963 return 0;
2964 }
2965 if (banks[1] & MCI_STATUS_VAL)
2966 mce->status |= MCI_STATUS_OVER;
2967 banks[2] = mce->addr;
2968 banks[3] = mce->misc;
2969 vcpu->arch.mcg_status = mce->mcg_status;
2970 banks[1] = mce->status;
2971 kvm_queue_exception(vcpu, MC_VECTOR);
2972 } else if (!(banks[1] & MCI_STATUS_VAL)
2973 || !(banks[1] & MCI_STATUS_UC)) {
2974 if (banks[1] & MCI_STATUS_VAL)
2975 mce->status |= MCI_STATUS_OVER;
2976 banks[2] = mce->addr;
2977 banks[3] = mce->misc;
2978 banks[1] = mce->status;
2979 } else
2980 banks[1] |= MCI_STATUS_OVER;
2981 return 0;
2982}
2983
3cfc3092
JK		 2984static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2985 struct kvm_vcpu_events *events)
2986{
7460fb4a 2987 process_nmi(vcpu);
03b82a30
JK		 2988 events->exception.injected =
2989 vcpu->arch.exception.pending &&
2990 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2991 events->exception.nr = vcpu->arch.exception.nr;
2992 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2993 events->exception.pad = 0;
3cfc3092
JK		 2994 events->exception.error_code = vcpu->arch.exception.error_code;
2995
03b82a30
JK		 2996 events->interrupt.injected =
2997 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2998 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2999 events->interrupt.soft = 0;
37ccdcbe 3000 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3001
3002 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3003 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3004 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3005 events->nmi.pad = 0;
3cfc3092 3006
66450a21 3007 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3008
f077825a
PB		 3009 events->smi.smm = is_smm(vcpu);
3010 events->smi.pending = vcpu->arch.smi_pending;
3011 events->smi.smm_inside_nmi =
3012 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3013 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3014
dab4b911 3015 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3016 | KVM_VCPUEVENT_VALID_SHADOW
3017 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3018 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3019}
3020
3021static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3022 struct kvm_vcpu_events *events)
3023{
dab4b911 3024 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3025 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3026 | KVM_VCPUEVENT_VALID_SHADOW
3027 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3028 return -EINVAL;
3029
78e546c8
PB		 3030 if (events->exception.injected &&
3031 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3032 return -EINVAL;
3033
7460fb4a 3034 process_nmi(vcpu);
3cfc3092
JK		 3035 vcpu->arch.exception.pending = events->exception.injected;
3036 vcpu->arch.exception.nr = events->exception.nr;
3037 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3038 vcpu->arch.exception.error_code = events->exception.error_code;
3039
3040 vcpu->arch.interrupt.pending = events->interrupt.injected;
3041 vcpu->arch.interrupt.nr = events->interrupt.nr;
3042 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3043 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3044 kvm_x86_ops->set_interrupt_shadow(vcpu,
3045 events->interrupt.shadow);
3cfc3092
JK		 3046
3047 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3048 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3049 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3050 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3051
66450a21 3052 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3053 lapic_in_kernel(vcpu))
66450a21 3054 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3055
f077825a
PB		 3056 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3057 if (events->smi.smm)
3058 vcpu->arch.hflags |= HF_SMM_MASK;
3059 else
3060 vcpu->arch.hflags &= ~HF_SMM_MASK;
3061 vcpu->arch.smi_pending = events->smi.pending;
3062 if (events->smi.smm_inside_nmi)
3063 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3064 else
3065 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3066 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3067 if (events->smi.latched_init)
3068 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3069 else
3070 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3071 }
3072 }
3073
3842d135
AK		 3074 kvm_make_request(KVM_REQ_EVENT, vcpu);
3075
3cfc3092
JK		 3076 return 0;
3077}
3078
a1efbe77
JK		 3079static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3080 struct kvm_debugregs *dbgregs)
3081{
73aaf249
JK		 3082 unsigned long val;
3083
a1efbe77 3084 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3085 kvm_get_dr(vcpu, 6, &val);
73aaf249 3086 dbgregs->dr6 = val;
a1efbe77
JK		 3087 dbgregs->dr7 = vcpu->arch.dr7;
3088 dbgregs->flags = 0;
97e69aa6 3089 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3090}
3091
3092static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3093 struct kvm_debugregs *dbgregs)
3094{
3095 if (dbgregs->flags)
3096 return -EINVAL;
3097
d14bdb55
PB		 3098 if (dbgregs->dr6 & ~0xffffffffull)
3099 return -EINVAL;
3100 if (dbgregs->dr7 & ~0xffffffffull)
3101 return -EINVAL;
3102
a1efbe77 3103 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3104 kvm_update_dr0123(vcpu);
a1efbe77 3105 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3106 kvm_update_dr6(vcpu);
a1efbe77 3107 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3108 kvm_update_dr7(vcpu);
a1efbe77 3109
a1efbe77
JK		 3110 return 0;
3111}
3112
df1daba7
PB		 3113#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3114
3115static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3116{
c47ada30 3117 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3118 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3119 u64 valid;
3120
3121 /*
3122 * Copy legacy XSAVE area, to avoid complications with CPUID
3123 * leaves 0 and 1 in the loop below.
3124 */
3125 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3126
3127 /* Set XSTATE_BV */
3128 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3129
3130 /*
3131 * Copy each region from the possibly compacted offset to the
3132 * non-compacted offset.
3133 */
d91cab78 3134 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3135 while (valid) {
3136 u64 feature = valid & -valid;
3137 int index = fls64(feature) - 1;
3138 void *src = get_xsave_addr(xsave, feature);
3139
3140 if (src) {
3141 u32 size, offset, ecx, edx;
3142 cpuid_count(XSTATE_CPUID, index,
3143 &size, &offset, &ecx, &edx);
3144 memcpy(dest + offset, src, size);
3145 }
3146
3147 valid -= feature;
3148 }
3149}
3150
3151static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3152{
c47ada30 3153 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3154 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3155 u64 valid;
3156
3157 /*
3158 * Copy legacy XSAVE area, to avoid complications with CPUID
3159 * leaves 0 and 1 in the loop below.
3160 */
3161 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3162
3163 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3164 xsave->header.xfeatures = xstate_bv;
782511b0 3165 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3166 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3167
3168 /*
3169 * Copy each region from the non-compacted offset to the
3170 * possibly compacted offset.
3171 */
d91cab78 3172 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3173 while (valid) {
3174 u64 feature = valid & -valid;
3175 int index = fls64(feature) - 1;
3176 void *dest = get_xsave_addr(xsave, feature);
3177
3178 if (dest) {
3179 u32 size, offset, ecx, edx;
3180 cpuid_count(XSTATE_CPUID, index,
3181 &size, &offset, &ecx, &edx);
3182 memcpy(dest, src + offset, size);
ee4100da 3183 }
df1daba7
PB		 3184
3185 valid -= feature;
3186 }
3187}
3188
2d5b5a66
SY		 3189static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3190 struct kvm_xsave *guest_xsave)
3191{
d366bf7e 3192 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3193 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3194 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3195 } else {
2d5b5a66 3196 memcpy(guest_xsave->region,
7366ed77 3197 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3198 sizeof(struct fxregs_state));
2d5b5a66 3199 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3200 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3201 }
3202}
3203
3204static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3205 struct kvm_xsave *guest_xsave)
3206{
3207 u64 xstate_bv =
3208 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3209
d366bf7e 3210 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3211 /*
3212 * Here we allow setting states that are not present in
3213 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3214 * with old userspace.
3215 */
4ff41732 3216 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3217 return -EINVAL;
df1daba7 3218 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3219 } else {
d91cab78 3220 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3221 return -EINVAL;
7366ed77 3222 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3223 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3224 }
3225 return 0;
3226}
3227
3228static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3229 struct kvm_xcrs *guest_xcrs)
3230{
d366bf7e 3231 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3232 guest_xcrs->nr_xcrs = 0;
3233 return;
3234 }
3235
3236 guest_xcrs->nr_xcrs = 1;
3237 guest_xcrs->flags = 0;
3238 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3239 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3240}
3241
3242static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3243 struct kvm_xcrs *guest_xcrs)
3244{
3245 int i, r = 0;
3246
d366bf7e 3247 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3248 return -EINVAL;
3249
3250 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3251 return -EINVAL;
3252
3253 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3254 /* Only support XCR0 currently */
c67a04cb 3255 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3256 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3257 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3258 break;
3259 }
3260 if (r)
3261 r = -EINVAL;
3262 return r;
3263}
3264
1c0b28c2
EM		 3265/*
3266 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3267 * stopped by the hypervisor. This function will be called from the host only.
3268 * EINVAL is returned when the host attempts to set the flag for a guest that
3269 * does not support pv clocks.
3270 */
3271static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3272{
0b79459b 3273 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3274 return -EINVAL;
51d59c6b 3275 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3276 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3277 return 0;
3278}
3279
5c919412
AS		 3280static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3281 struct kvm_enable_cap *cap)
3282{
3283 if (cap->flags)
3284 return -EINVAL;
3285
3286 switch (cap->cap) {
3287 case KVM_CAP_HYPERV_SYNIC:
3288 return kvm_hv_activate_synic(vcpu);
3289 default:
3290 return -EINVAL;
3291 }
3292}
3293
313a3dc7
CO		 3294long kvm_arch_vcpu_ioctl(struct file *filp,
3295 unsigned int ioctl, unsigned long arg)
3296{
3297 struct kvm_vcpu *vcpu = filp->private_data;
3298 void __user *argp = (void __user *)arg;
3299 int r;
d1ac91d8
AK		 3300 union {
3301 struct kvm_lapic_state *lapic;
3302 struct kvm_xsave *xsave;
3303 struct kvm_xcrs *xcrs;
3304 void *buffer;
3305 } u;
3306
3307 u.buffer = NULL;
313a3dc7
CO		 3308 switch (ioctl) {
3309 case KVM_GET_LAPIC: {
2204ae3c 3310 r = -EINVAL;
bce87cce 3311 if (!lapic_in_kernel(vcpu))
2204ae3c 3312 goto out;
d1ac91d8 3313 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3314
b772ff36 3315 r = -ENOMEM;
d1ac91d8 3316 if (!u.lapic)
b772ff36 3317 goto out;
d1ac91d8 3318 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3319 if (r)
3320 goto out;
3321 r = -EFAULT;
d1ac91d8 3322 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3323 goto out;
3324 r = 0;
3325 break;
3326 }
3327 case KVM_SET_LAPIC: {
2204ae3c 3328 r = -EINVAL;
bce87cce 3329 if (!lapic_in_kernel(vcpu))
2204ae3c 3330 goto out;
ff5c2c03 3331 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3332 if (IS_ERR(u.lapic))
3333 return PTR_ERR(u.lapic);
ff5c2c03 3334
d1ac91d8 3335 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3336 break;
3337 }
f77bc6a4
ZX		 3338 case KVM_INTERRUPT: {
3339 struct kvm_interrupt irq;
3340
3341 r = -EFAULT;
3342 if (copy_from_user(&irq, argp, sizeof irq))
3343 goto out;
3344 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3345 break;
3346 }
c4abb7c9
JK		 3347 case KVM_NMI: {
3348 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3349 break;
3350 }
f077825a
PB		 3351 case KVM_SMI: {
3352 r = kvm_vcpu_ioctl_smi(vcpu);
3353 break;
3354 }
313a3dc7
CO		 3355 case KVM_SET_CPUID: {
3356 struct kvm_cpuid __user *cpuid_arg = argp;
3357 struct kvm_cpuid cpuid;
3358
3359 r = -EFAULT;
3360 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3361 goto out;
3362 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3363 break;
3364 }
07716717
DK		 3365 case KVM_SET_CPUID2: {
3366 struct kvm_cpuid2 __user *cpuid_arg = argp;
3367 struct kvm_cpuid2 cpuid;
3368
3369 r = -EFAULT;
3370 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3371 goto out;
3372 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3373 cpuid_arg->entries);
07716717
DK		 3374 break;
3375 }
3376 case KVM_GET_CPUID2: {
3377 struct kvm_cpuid2 __user *cpuid_arg = argp;
3378 struct kvm_cpuid2 cpuid;
3379
3380 r = -EFAULT;
3381 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3382 goto out;
3383 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3384 cpuid_arg->entries);
07716717
DK		 3385 if (r)
3386 goto out;
3387 r = -EFAULT;
3388 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3389 goto out;
3390 r = 0;
3391 break;
3392 }
313a3dc7 3393 case KVM_GET_MSRS:
609e36d3 3394 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3395 break;
3396 case KVM_SET_MSRS:
3397 r = msr_io(vcpu, argp, do_set_msr, 0);
3398 break;
b209749f
AK		 3399 case KVM_TPR_ACCESS_REPORTING: {
3400 struct kvm_tpr_access_ctl tac;
3401
3402 r = -EFAULT;
3403 if (copy_from_user(&tac, argp, sizeof tac))
3404 goto out;
3405 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3406 if (r)
3407 goto out;
3408 r = -EFAULT;
3409 if (copy_to_user(argp, &tac, sizeof tac))
3410 goto out;
3411 r = 0;
3412 break;
3413 };
b93463aa
AK		 3414 case KVM_SET_VAPIC_ADDR: {
3415 struct kvm_vapic_addr va;
3416
3417 r = -EINVAL;
35754c98 3418 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3419 goto out;
3420 r = -EFAULT;
3421 if (copy_from_user(&va, argp, sizeof va))
3422 goto out;
fda4e2e8 3423 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3424 break;
3425 }
890ca9ae
HY		 3426 case KVM_X86_SETUP_MCE: {
3427 u64 mcg_cap;
3428
3429 r = -EFAULT;
3430 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3431 goto out;
3432 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3433 break;
3434 }
3435 case KVM_X86_SET_MCE: {
3436 struct kvm_x86_mce mce;
3437
3438 r = -EFAULT;
3439 if (copy_from_user(&mce, argp, sizeof mce))
3440 goto out;
3441 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3442 break;
3443 }
3cfc3092
JK		 3444 case KVM_GET_VCPU_EVENTS: {
3445 struct kvm_vcpu_events events;
3446
3447 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3448
3449 r = -EFAULT;
3450 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3451 break;
3452 r = 0;
3453 break;
3454 }
3455 case KVM_SET_VCPU_EVENTS: {
3456 struct kvm_vcpu_events events;
3457
3458 r = -EFAULT;
3459 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3460 break;
3461
3462 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3463 break;
3464 }
a1efbe77
JK		 3465 case KVM_GET_DEBUGREGS: {
3466 struct kvm_debugregs dbgregs;
3467
3468 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3469
3470 r = -EFAULT;
3471 if (copy_to_user(argp, &dbgregs,
3472 sizeof(struct kvm_debugregs)))
3473 break;
3474 r = 0;
3475 break;
3476 }
3477 case KVM_SET_DEBUGREGS: {
3478 struct kvm_debugregs dbgregs;
3479
3480 r = -EFAULT;
3481 if (copy_from_user(&dbgregs, argp,
3482 sizeof(struct kvm_debugregs)))
3483 break;
3484
3485 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3486 break;
3487 }
2d5b5a66 3488 case KVM_GET_XSAVE: {
d1ac91d8 3489 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3490 r = -ENOMEM;
d1ac91d8 3491 if (!u.xsave)
2d5b5a66
SY		 3492 break;
3493
d1ac91d8 3494 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3495
3496 r = -EFAULT;
d1ac91d8 3497 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3498 break;
3499 r = 0;
3500 break;
3501 }
3502 case KVM_SET_XSAVE: {
ff5c2c03 3503 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3504 if (IS_ERR(u.xsave))
3505 return PTR_ERR(u.xsave);
2d5b5a66 3506
d1ac91d8 3507 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3508 break;
3509 }
3510 case KVM_GET_XCRS: {
d1ac91d8 3511 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3512 r = -ENOMEM;
d1ac91d8 3513 if (!u.xcrs)
2d5b5a66
SY		 3514 break;
3515
d1ac91d8 3516 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3517
3518 r = -EFAULT;
d1ac91d8 3519 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3520 sizeof(struct kvm_xcrs)))
3521 break;
3522 r = 0;
3523 break;
3524 }
3525 case KVM_SET_XCRS: {
ff5c2c03 3526 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3527 if (IS_ERR(u.xcrs))
3528 return PTR_ERR(u.xcrs);
2d5b5a66 3529
d1ac91d8 3530 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3531 break;
3532 }
92a1f12d
JR		 3533 case KVM_SET_TSC_KHZ: {
3534 u32 user_tsc_khz;
3535
3536 r = -EINVAL;
92a1f12d
JR		 3537 user_tsc_khz = (u32)arg;
3538
3539 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3540 goto out;
3541
cc578287
ZA		 3542 if (user_tsc_khz == 0)
3543 user_tsc_khz = tsc_khz;
3544
381d585c
HZ		 3545 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3546 r = 0;
92a1f12d 3547
92a1f12d
JR		 3548 goto out;
3549 }
3550 case KVM_GET_TSC_KHZ: {
cc578287 3551 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3552 goto out;
3553 }
1c0b28c2
EM		 3554 case KVM_KVMCLOCK_CTRL: {
3555 r = kvm_set_guest_paused(vcpu);
3556 goto out;
3557 }
5c919412
AS		 3558 case KVM_ENABLE_CAP: {
3559 struct kvm_enable_cap cap;
3560
3561 r = -EFAULT;
3562 if (copy_from_user(&cap, argp, sizeof(cap)))
3563 goto out;
3564 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3565 break;
3566 }
313a3dc7
CO		 3567 default:
3568 r = -EINVAL;
3569 }
3570out:
d1ac91d8 3571 kfree(u.buffer);
313a3dc7
CO		 3572 return r;
3573}
3574
5b1c1493
CO		 3575int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3576{
3577 return VM_FAULT_SIGBUS;
3578}
3579
1fe779f8
CO		 3580static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3581{
3582 int ret;
3583
3584 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3585 return -EINVAL;
1fe779f8
CO		 3586 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3587 return ret;
3588}
3589
b927a3ce
SY		 3590static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3591 u64 ident_addr)
3592{
3593 kvm->arch.ept_identity_map_addr = ident_addr;
3594 return 0;
3595}
3596
1fe779f8
CO		 3597static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3598 u32 kvm_nr_mmu_pages)
3599{
3600 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3601 return -EINVAL;
3602
79fac95e 3603 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3604
3605 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3606 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3607
79fac95e 3608 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3609 return 0;
3610}
3611
3612static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3613{
39de71ec 3614 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3615}
3616
1fe779f8
CO		 3617static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3618{
3619 int r;
3620
3621 r = 0;
3622 switch (chip->chip_id) {
3623 case KVM_IRQCHIP_PIC_MASTER:
3624 memcpy(&chip->chip.pic,
3625 &pic_irqchip(kvm)->pics[0],
3626 sizeof(struct kvm_pic_state));
3627 break;
3628 case KVM_IRQCHIP_PIC_SLAVE:
3629 memcpy(&chip->chip.pic,
3630 &pic_irqchip(kvm)->pics[1],
3631 sizeof(struct kvm_pic_state));
3632 break;
3633 case KVM_IRQCHIP_IOAPIC:
eba0226b 3634 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3635 break;
3636 default:
3637 r = -EINVAL;
3638 break;
3639 }
3640 return r;
3641}
3642
3643static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3644{
3645 int r;
3646
3647 r = 0;
3648 switch (chip->chip_id) {
3649 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3650 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3651 memcpy(&pic_irqchip(kvm)->pics[0],
3652 &chip->chip.pic,
3653 sizeof(struct kvm_pic_state));
f4f51050 3654 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3655 break;
3656 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3657 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3658 memcpy(&pic_irqchip(kvm)->pics[1],
3659 &chip->chip.pic,
3660 sizeof(struct kvm_pic_state));
f4f51050 3661 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3662 break;
3663 case KVM_IRQCHIP_IOAPIC:
eba0226b 3664 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3665 break;
3666 default:
3667 r = -EINVAL;
3668 break;
3669 }
3670 kvm_pic_update_irq(pic_irqchip(kvm));
3671 return r;
3672}
3673
e0f63cb9
SY		 3674static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3675{
34f3941c
RK		 3676 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3677
3678 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3679
3680 mutex_lock(&kps->lock);
3681 memcpy(ps, &kps->channels, sizeof(*ps));
3682 mutex_unlock(&kps->lock);
2da29bcc 3683 return 0;
e0f63cb9
SY		 3684}
3685
3686static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3687{
0185604c 3688 int i;
09edea72
RK		 3689 struct kvm_pit *pit = kvm->arch.vpit;
3690
3691 mutex_lock(&pit->pit_state.lock);
34f3941c 3692 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3693 for (i = 0; i < 3; i++)
09edea72
RK		 3694 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3695 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3696 return 0;
e9f42757
BK		 3697}
3698
3699static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3700{
e9f42757
BK		 3701 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3702 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3703 sizeof(ps->channels));
3704 ps->flags = kvm->arch.vpit->pit_state.flags;
3705 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3706 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3707 return 0;
e9f42757
BK		 3708}
3709
3710static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3711{
2da29bcc 3712 int start = 0;
0185604c 3713 int i;
e9f42757 3714 u32 prev_legacy, cur_legacy;
09edea72
RK		 3715 struct kvm_pit *pit = kvm->arch.vpit;
3716
3717 mutex_lock(&pit->pit_state.lock);
3718 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3719 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3720 if (!prev_legacy && cur_legacy)
3721 start = 1;
09edea72
RK		 3722 memcpy(&pit->pit_state.channels, &ps->channels,
3723 sizeof(pit->pit_state.channels));
3724 pit->pit_state.flags = ps->flags;
0185604c 3725 for (i = 0; i < 3; i++)
09edea72 3726 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3727 start && i == 0);
09edea72 3728 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3729 return 0;
e0f63cb9
SY		 3730}
3731
52d939a0
MT		 3732static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3733 struct kvm_reinject_control *control)
3734{
71474e2f
RK		 3735 struct kvm_pit *pit = kvm->arch.vpit;
3736
3737 if (!pit)
52d939a0 3738 return -ENXIO;
b39c90b6 3739
71474e2f
RK		 3740 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3741 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3742 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3743 */
3744 mutex_lock(&pit->pit_state.lock);
3745 kvm_pit_set_reinject(pit, control->pit_reinject);
3746 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3747
52d939a0
MT		 3748 return 0;
3749}
3750
95d4c16c 3751/**
60c34612
TY		 3752 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3753 * @kvm: kvm instance
3754 * @log: slot id and address to which we copy the log
95d4c16c 3755 *
e108ff2f
PB		 3756 * Steps 1-4 below provide general overview of dirty page logging. See
3757 * kvm_get_dirty_log_protect() function description for additional details.
3758 *
3759 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3760 * always flush the TLB (step 4) even if previous step failed and the dirty
3761 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3762 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3763 * writes will be marked dirty for next log read.
95d4c16c 3764 *
60c34612
TY		 3765 * 1. Take a snapshot of the bit and clear it if needed.
3766 * 2. Write protect the corresponding page.
e108ff2f
PB		 3767 * 3. Copy the snapshot to the userspace.
3768 * 4. Flush TLB's if needed.
5bb064dc 3769 */
60c34612 3770int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3771{
60c34612 3772 bool is_dirty = false;
e108ff2f 3773 int r;
5bb064dc 3774
79fac95e 3775 mutex_lock(&kvm->slots_lock);
5bb064dc 3776
88178fd4
KH		 3777 /*
3778 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3779 */
3780 if (kvm_x86_ops->flush_log_dirty)
3781 kvm_x86_ops->flush_log_dirty(kvm);
3782
e108ff2f 3783 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3784
3785 /*
3786 * All the TLBs can be flushed out of mmu lock, see the comments in
3787 * kvm_mmu_slot_remove_write_access().
3788 */
e108ff2f 3789 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3790 if (is_dirty)
3791 kvm_flush_remote_tlbs(kvm);
3792
79fac95e 3793 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3794 return r;
3795}
3796
aa2fbe6d
YZ		 3797int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3798 bool line_status)
23d43cf9
CD		 3799{
3800 if (!irqchip_in_kernel(kvm))
3801 return -ENXIO;
3802
3803 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3804 irq_event->irq, irq_event->level,
3805 line_status);
23d43cf9
CD		 3806 return 0;
3807}
3808
90de4a18
NA		 3809static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3810 struct kvm_enable_cap *cap)
3811{
3812 int r;
3813
3814 if (cap->flags)
3815 return -EINVAL;
3816
3817 switch (cap->cap) {
3818 case KVM_CAP_DISABLE_QUIRKS:
3819 kvm->arch.disabled_quirks = cap->args[0];
3820 r = 0;
3821 break;
49df6397
SR		 3822 case KVM_CAP_SPLIT_IRQCHIP: {
3823 mutex_lock(&kvm->lock);
b053b2ae
SR		 3824 r = -EINVAL;
3825 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3826 goto split_irqchip_unlock;
49df6397
SR		 3827 r = -EEXIST;
3828 if (irqchip_in_kernel(kvm))
3829 goto split_irqchip_unlock;
557abc40 3830 if (kvm->created_vcpus)
49df6397
SR		 3831 goto split_irqchip_unlock;
3832 r = kvm_setup_empty_irq_routing(kvm);
3833 if (r)
3834 goto split_irqchip_unlock;
3835 /* Pairs with irqchip_in_kernel. */
3836 smp_wmb();
3837 kvm->arch.irqchip_split = true;
b053b2ae 3838 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3839 r = 0;
3840split_irqchip_unlock:
3841 mutex_unlock(&kvm->lock);
3842 break;
3843 }
37131313
RK		 3844 case KVM_CAP_X2APIC_API:
3845 r = -EINVAL;
3846 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3847 break;
3848
3849 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3850 kvm->arch.x2apic_format = true;
c519265f
RK		 3851 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3852 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3853
3854 r = 0;
3855 break;
90de4a18
NA		 3856 default:
3857 r = -EINVAL;
3858 break;
3859 }
3860 return r;
3861}
3862
1fe779f8
CO		 3863long kvm_arch_vm_ioctl(struct file *filp,
3864 unsigned int ioctl, unsigned long arg)
3865{
3866 struct kvm *kvm = filp->private_data;
3867 void __user *argp = (void __user *)arg;
367e1319 3868 int r = -ENOTTY;
f0d66275
DH		 3869 /*
3870 * This union makes it completely explicit to gcc-3.x
3871 * that these two variables' stack usage should be
3872 * combined, not added together.
3873 */
3874 union {
3875 struct kvm_pit_state ps;
e9f42757 3876 struct kvm_pit_state2 ps2;
c5ff41ce 3877 struct kvm_pit_config pit_config;
f0d66275 3878 } u;
1fe779f8
CO		 3879
3880 switch (ioctl) {
3881 case KVM_SET_TSS_ADDR:
3882 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3883 break;
b927a3ce
SY		 3884 case KVM_SET_IDENTITY_MAP_ADDR: {
3885 u64 ident_addr;
3886
3887 r = -EFAULT;
3888 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3889 goto out;
3890 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3891 break;
3892 }
1fe779f8
CO		 3893 case KVM_SET_NR_MMU_PAGES:
3894 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3895 break;
3896 case KVM_GET_NR_MMU_PAGES:
3897 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3898 break;
3ddea128
MT		 3899 case KVM_CREATE_IRQCHIP: {
3900 struct kvm_pic *vpic;
3901
3902 mutex_lock(&kvm->lock);
3903 r = -EEXIST;
3904 if (kvm->arch.vpic)
3905 goto create_irqchip_unlock;
3e515705 3906 r = -EINVAL;
557abc40 3907 if (kvm->created_vcpus)
3e515705 3908 goto create_irqchip_unlock;
1fe779f8 3909 r = -ENOMEM;
3ddea128
MT		 3910 vpic = kvm_create_pic(kvm);
3911 if (vpic) {
1fe779f8
CO		 3912 r = kvm_ioapic_init(kvm);
3913 if (r) {
175504cd 3914 mutex_lock(&kvm->slots_lock);
71ba994c 3915 kvm_destroy_pic(vpic);
175504cd 3916 mutex_unlock(&kvm->slots_lock);
3ddea128 3917 goto create_irqchip_unlock;
1fe779f8
CO		 3918 }
3919 } else
3ddea128 3920 goto create_irqchip_unlock;
399ec807
AK		 3921 r = kvm_setup_default_irq_routing(kvm);
3922 if (r) {
175504cd 3923 mutex_lock(&kvm->slots_lock);
3ddea128 3924 mutex_lock(&kvm->irq_lock);
72bb2fcd 3925 kvm_ioapic_destroy(kvm);
71ba994c 3926 kvm_destroy_pic(vpic);
3ddea128 3927 mutex_unlock(&kvm->irq_lock);
175504cd 3928 mutex_unlock(&kvm->slots_lock);
71ba994c 3929 goto create_irqchip_unlock;
399ec807 3930 }
71ba994c
PB		 3931 /* Write kvm->irq_routing before kvm->arch.vpic. */
3932 smp_wmb();
3933 kvm->arch.vpic = vpic;
3ddea128
MT		 3934 create_irqchip_unlock:
3935 mutex_unlock(&kvm->lock);
1fe779f8 3936 break;
3ddea128 3937 }
7837699f 3938 case KVM_CREATE_PIT:
c5ff41ce
JK		 3939 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3940 goto create_pit;
3941 case KVM_CREATE_PIT2:
3942 r = -EFAULT;
3943 if (copy_from_user(&u.pit_config, argp,
3944 sizeof(struct kvm_pit_config)))
3945 goto out;
3946 create_pit:
250715a6 3947 mutex_lock(&kvm->lock);
269e05e4
AK		 3948 r = -EEXIST;
3949 if (kvm->arch.vpit)
3950 goto create_pit_unlock;
7837699f 3951 r = -ENOMEM;
c5ff41ce 3952 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3953 if (kvm->arch.vpit)
3954 r = 0;
269e05e4 3955 create_pit_unlock:
250715a6 3956 mutex_unlock(&kvm->lock);
7837699f 3957 break;
1fe779f8
CO		 3958 case KVM_GET_IRQCHIP: {
3959 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3960 struct kvm_irqchip *chip;
1fe779f8 3961
ff5c2c03
SL		 3962 chip = memdup_user(argp, sizeof(*chip));
3963 if (IS_ERR(chip)) {
3964 r = PTR_ERR(chip);
1fe779f8 3965 goto out;
ff5c2c03
SL		 3966 }
3967
1fe779f8 3968 r = -ENXIO;
49df6397 3969 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3970 goto get_irqchip_out;
3971 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3972 if (r)
f0d66275 3973 goto get_irqchip_out;
1fe779f8 3974 r = -EFAULT;
f0d66275
DH		 3975 if (copy_to_user(argp, chip, sizeof *chip))
3976 goto get_irqchip_out;
1fe779f8 3977 r = 0;
f0d66275
DH		 3978 get_irqchip_out:
3979 kfree(chip);
1fe779f8
CO		 3980 break;
3981 }
3982 case KVM_SET_IRQCHIP: {
3983 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3984 struct kvm_irqchip *chip;
1fe779f8 3985
ff5c2c03
SL		 3986 chip = memdup_user(argp, sizeof(*chip));
3987 if (IS_ERR(chip)) {
3988 r = PTR_ERR(chip);
1fe779f8 3989 goto out;
ff5c2c03
SL		 3990 }
3991
1fe779f8 3992 r = -ENXIO;
49df6397 3993 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3994 goto set_irqchip_out;
3995 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3996 if (r)
f0d66275 3997 goto set_irqchip_out;
1fe779f8 3998 r = 0;
f0d66275
DH		 3999 set_irqchip_out:
4000 kfree(chip);
1fe779f8
CO		 4001 break;
4002 }
e0f63cb9 4003 case KVM_GET_PIT: {
e0f63cb9 4004 r = -EFAULT;
f0d66275 4005 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4006 goto out;
4007 r = -ENXIO;
4008 if (!kvm->arch.vpit)
4009 goto out;
f0d66275 4010 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4011 if (r)
4012 goto out;
4013 r = -EFAULT;
f0d66275 4014 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4015 goto out;
4016 r = 0;
4017 break;
4018 }
4019 case KVM_SET_PIT: {
e0f63cb9 4020 r = -EFAULT;
f0d66275 4021 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4022 goto out;
4023 r = -ENXIO;
4024 if (!kvm->arch.vpit)
4025 goto out;
f0d66275 4026 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4027 break;
4028 }
e9f42757
BK		 4029 case KVM_GET_PIT2: {
4030 r = -ENXIO;
4031 if (!kvm->arch.vpit)
4032 goto out;
4033 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4034 if (r)
4035 goto out;
4036 r = -EFAULT;
4037 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4038 goto out;
4039 r = 0;
4040 break;
4041 }
4042 case KVM_SET_PIT2: {
4043 r = -EFAULT;
4044 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4045 goto out;
4046 r = -ENXIO;
4047 if (!kvm->arch.vpit)
4048 goto out;
4049 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4050 break;
4051 }
52d939a0
MT		 4052 case KVM_REINJECT_CONTROL: {
4053 struct kvm_reinject_control control;
4054 r = -EFAULT;
4055 if (copy_from_user(&control, argp, sizeof(control)))
4056 goto out;
4057 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4058 break;
4059 }
d71ba788
PB		 4060 case KVM_SET_BOOT_CPU_ID:
4061 r = 0;
4062 mutex_lock(&kvm->lock);
557abc40 4063 if (kvm->created_vcpus)
d71ba788
PB		 4064 r = -EBUSY;
4065 else
4066 kvm->arch.bsp_vcpu_id = arg;
4067 mutex_unlock(&kvm->lock);
4068 break;
ffde22ac
ES		 4069 case KVM_XEN_HVM_CONFIG: {
4070 r = -EFAULT;
4071 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4072 sizeof(struct kvm_xen_hvm_config)))
4073 goto out;
4074 r = -EINVAL;
4075 if (kvm->arch.xen_hvm_config.flags)
4076 goto out;
4077 r = 0;
4078 break;
4079 }
afbcf7ab 4080 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4081 struct kvm_clock_data user_ns;
4082 u64 now_ns;
afbcf7ab
GC		 4083
4084 r = -EFAULT;
4085 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4086 goto out;
4087
4088 r = -EINVAL;
4089 if (user_ns.flags)
4090 goto out;
4091
4092 r = 0;
395c6b0a 4093 local_irq_disable();
108b249c
PB		 4094 now_ns = __get_kvmclock_ns(kvm);
4095 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
395c6b0a 4096 local_irq_enable();
2e762ff7 4097 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4098 break;
4099 }
4100 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4101 struct kvm_clock_data user_ns;
4102 u64 now_ns;
4103
108b249c
PB		 4104 now_ns = get_kvmclock_ns(kvm);
4105 user_ns.clock = now_ns;
afbcf7ab 4106 user_ns.flags = 0;
97e69aa6 4107 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4108
4109 r = -EFAULT;
4110 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4111 goto out;
4112 r = 0;
4113 break;
4114 }
90de4a18
NA		 4115 case KVM_ENABLE_CAP: {
4116 struct kvm_enable_cap cap;
afbcf7ab 4117
90de4a18
NA		 4118 r = -EFAULT;
4119 if (copy_from_user(&cap, argp, sizeof(cap)))
4120 goto out;
4121 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4122 break;
4123 }
1fe779f8 4124 default:
c274e03a 4125 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4126 }
4127out:
4128 return r;
4129}
4130
a16b043c 4131static void kvm_init_msr_list(void)
043405e1
CO		 4132{
4133 u32 dummy[2];
4134 unsigned i, j;
4135
62ef68bb 4136 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4137 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4138 continue;
93c4adc7
PB		 4139
4140 /*
4141 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4142 * to the guests in some cases.
93c4adc7
PB		 4143 */
4144 switch (msrs_to_save[i]) {
4145 case MSR_IA32_BNDCFGS:
4146 if (!kvm_x86_ops->mpx_supported())
4147 continue;
4148 break;
9dbe6cf9
PB		 4149 case MSR_TSC_AUX:
4150 if (!kvm_x86_ops->rdtscp_supported())
4151 continue;
4152 break;
93c4adc7
PB		 4153 default:
4154 break;
4155 }
4156
043405e1
CO		 4157 if (j < i)
4158 msrs_to_save[j] = msrs_to_save[i];
4159 j++;
4160 }
4161 num_msrs_to_save = j;
62ef68bb
PB		 4162
4163 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4164 switch (emulated_msrs[i]) {
6d396b55
PB		 4165 case MSR_IA32_SMBASE:
4166 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4167 continue;
4168 break;
62ef68bb
PB		 4169 default:
4170 break;
4171 }
4172
4173 if (j < i)
4174 emulated_msrs[j] = emulated_msrs[i];
4175 j++;
4176 }
4177 num_emulated_msrs = j;
043405e1
CO		 4178}
4179
bda9020e
MT		 4180static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4181 const void *v)
bbd9b64e 4182{
70252a10
AK		 4183 int handled = 0;
4184 int n;
4185
4186 do {
4187 n = min(len, 8);
bce87cce 4188 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4189 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4190 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4191 break;
4192 handled += n;
4193 addr += n;
4194 len -= n;
4195 v += n;
4196 } while (len);
bbd9b64e 4197
70252a10 4198 return handled;
bbd9b64e
CO		 4199}
4200
bda9020e 4201static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4202{
70252a10
AK		 4203 int handled = 0;
4204 int n;
4205
4206 do {
4207 n = min(len, 8);
bce87cce 4208 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4209 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4210 addr, n, v))
4211 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4212 break;
4213 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4214 handled += n;
4215 addr += n;
4216 len -= n;
4217 v += n;
4218 } while (len);
bbd9b64e 4219
70252a10 4220 return handled;
bbd9b64e
CO		 4221}
4222
2dafc6c2
GN		 4223static void kvm_set_segment(struct kvm_vcpu *vcpu,
4224 struct kvm_segment *var, int seg)
4225{
4226 kvm_x86_ops->set_segment(vcpu, var, seg);
4227}
4228
4229void kvm_get_segment(struct kvm_vcpu *vcpu,
4230 struct kvm_segment *var, int seg)
4231{
4232 kvm_x86_ops->get_segment(vcpu, var, seg);
4233}
4234
54987b7a
PB		 4235gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4236 struct x86_exception *exception)
02f59dc9
JR		 4237{
4238 gpa_t t_gpa;
02f59dc9
JR		 4239
4240 BUG_ON(!mmu_is_nested(vcpu));
4241
4242 /* NPT walks are always user-walks */
4243 access |= PFERR_USER_MASK;
54987b7a 4244 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4245
4246 return t_gpa;
4247}
4248
ab9ae313
AK		 4249gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4250 struct x86_exception *exception)
1871c602
GN		 4251{
4252 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4253 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4254}
4255
ab9ae313
AK		 4256 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4257 struct x86_exception *exception)
1871c602
GN		 4258{
4259 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4260 access |= PFERR_FETCH_MASK;
ab9ae313 4261 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4262}
4263
ab9ae313
AK		 4264gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4265 struct x86_exception *exception)
1871c602
GN		 4266{
4267 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4268 access |= PFERR_WRITE_MASK;
ab9ae313 4269 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4270}
4271
4272/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4273gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4274 struct x86_exception *exception)
1871c602 4275{
ab9ae313 4276 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4277}
4278
4279static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4280 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4281 struct x86_exception *exception)
bbd9b64e
CO		 4282{
4283 void *data = val;
10589a46 4284 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4285
4286 while (bytes) {
14dfe855 4287 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4288 exception);
bbd9b64e 4289 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4290 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4291 int ret;
4292
bcc55cba 4293 if (gpa == UNMAPPED_GVA)
ab9ae313 4294 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4295 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4296 offset, toread);
10589a46 4297 if (ret < 0) {
c3cd7ffa 4298 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4299 goto out;
4300 }
bbd9b64e 4301
77c2002e
IE		 4302 bytes -= toread;
4303 data += toread;
4304 addr += toread;
bbd9b64e 4305 }
10589a46 4306out:
10589a46 4307 return r;
bbd9b64e 4308}
77c2002e 4309
1871c602 4310/* used for instruction fetching */
0f65dd70
AK		 4311static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4312 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4313 struct x86_exception *exception)
1871c602 4314{
0f65dd70 4315 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4316 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4317 unsigned offset;
4318 int ret;
0f65dd70 4319
44583cba
PB		 4320 /* Inline kvm_read_guest_virt_helper for speed. */
4321 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4322 exception);
4323 if (unlikely(gpa == UNMAPPED_GVA))
4324 return X86EMUL_PROPAGATE_FAULT;
4325
4326 offset = addr & (PAGE_SIZE-1);
4327 if (WARN_ON(offset + bytes > PAGE_SIZE))
4328 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4329 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4330 offset, bytes);
44583cba
PB		 4331 if (unlikely(ret < 0))
4332 return X86EMUL_IO_NEEDED;
4333
4334 return X86EMUL_CONTINUE;
1871c602
GN		 4335}
4336
064aea77 4337int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4338 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4339 struct x86_exception *exception)
1871c602 4340{
0f65dd70 4341 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4342 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4343
1871c602 4344 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4345 exception);
1871c602 4346}
064aea77 4347EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4348
0f65dd70
AK		 4349static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4350 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4351 struct x86_exception *exception)
1871c602 4352{
0f65dd70 4353 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4354 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4355}
4356
7a036a6f
RK		 4357static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4358 unsigned long addr, void *val, unsigned int bytes)
4359{
4360 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4361 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4362
4363 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4364}
4365
6a4d7550 4366int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4367 gva_t addr, void *val,
2dafc6c2 4368 unsigned int bytes,
bcc55cba 4369 struct x86_exception *exception)
77c2002e 4370{
0f65dd70 4371 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4372 void *data = val;
4373 int r = X86EMUL_CONTINUE;
4374
4375 while (bytes) {
14dfe855
JR		 4376 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4377 PFERR_WRITE_MASK,
ab9ae313 4378 exception);
77c2002e
IE		 4379 unsigned offset = addr & (PAGE_SIZE-1);
4380 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4381 int ret;
4382
bcc55cba 4383 if (gpa == UNMAPPED_GVA)
ab9ae313 4384 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4385 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4386 if (ret < 0) {
c3cd7ffa 4387 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4388 goto out;
4389 }
4390
4391 bytes -= towrite;
4392 data += towrite;
4393 addr += towrite;
4394 }
4395out:
4396 return r;
4397}
6a4d7550 4398EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4399
af7cc7d1
XG		 4400static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4401 gpa_t *gpa, struct x86_exception *exception,
4402 bool write)
4403{
97d64b78
AK		 4404 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4405 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4406
be94f6b7
HH		 4407 /*
4408 * currently PKRU is only applied to ept enabled guest so
4409 * there is no pkey in EPT page table for L1 guest or EPT
4410 * shadow page table for L2 guest.
4411 */
97d64b78 4412 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4413 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4414 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4415 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4416 (gva & (PAGE_SIZE - 1));
4f022648 4417 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4418 return 1;
4419 }
4420
af7cc7d1
XG		 4421 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4422
4423 if (*gpa == UNMAPPED_GVA)
4424 return -1;
4425
4426 /* For APIC access vmexit */
4427 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4428 return 1;
4429
4f022648
XG		 4430 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4431 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4432 return 1;
4f022648 4433 }
bebb106a 4434
af7cc7d1
XG		 4435 return 0;
4436}
4437
3200f405 4438int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4439 const void *val, int bytes)
bbd9b64e
CO		 4440{
4441 int ret;
4442
54bf36aa 4443 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4444 if (ret < 0)
bbd9b64e 4445 return 0;
0eb05bf2 4446 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4447 return 1;
4448}
4449
77d197b2
XG		 4450struct read_write_emulator_ops {
4451 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4452 int bytes);
4453 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4454 void *val, int bytes);
4455 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4456 int bytes, void *val);
4457 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4458 void *val, int bytes);
4459 bool write;
4460};
4461
4462static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4463{
4464 if (vcpu->mmio_read_completed) {
77d197b2 4465 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4466 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4467 vcpu->mmio_read_completed = 0;
4468 return 1;
4469 }
4470
4471 return 0;
4472}
4473
4474static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4475 void *val, int bytes)
4476{
54bf36aa 4477 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4478}
4479
4480static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4481 void *val, int bytes)
4482{
4483 return emulator_write_phys(vcpu, gpa, val, bytes);
4484}
4485
4486static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4487{
4488 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4489 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4490}
4491
4492static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4493 void *val, int bytes)
4494{
4495 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4496 return X86EMUL_IO_NEEDED;
4497}
4498
4499static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4500 void *val, int bytes)
4501{
f78146b0
AK		 4502 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4503
87da7e66 4504 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4505 return X86EMUL_CONTINUE;
4506}
4507
0fbe9b0b 4508static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4509 .read_write_prepare = read_prepare,
4510 .read_write_emulate = read_emulate,
4511 .read_write_mmio = vcpu_mmio_read,
4512 .read_write_exit_mmio = read_exit_mmio,
4513};
4514
0fbe9b0b 4515static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4516 .read_write_emulate = write_emulate,
4517 .read_write_mmio = write_mmio,
4518 .read_write_exit_mmio = write_exit_mmio,
4519 .write = true,
4520};
4521
22388a3c
XG		 4522static int emulator_read_write_onepage(unsigned long addr, void *val,
4523 unsigned int bytes,
4524 struct x86_exception *exception,
4525 struct kvm_vcpu *vcpu,
0fbe9b0b 4526 const struct read_write_emulator_ops *ops)
bbd9b64e 4527{
af7cc7d1
XG		 4528 gpa_t gpa;
4529 int handled, ret;
22388a3c 4530 bool write = ops->write;
f78146b0 4531 struct kvm_mmio_fragment *frag;
10589a46 4532
22388a3c 4533 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4534
af7cc7d1 4535 if (ret < 0)
bbd9b64e 4536 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4537
4538 /* For APIC access vmexit */
af7cc7d1 4539 if (ret)
bbd9b64e
CO		 4540 goto mmio;
4541
22388a3c 4542 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4543 return X86EMUL_CONTINUE;
4544
4545mmio:
4546 /*
4547 * Is this MMIO handled locally?
4548 */
22388a3c 4549 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4550 if (handled == bytes)
bbd9b64e 4551 return X86EMUL_CONTINUE;
bbd9b64e 4552
70252a10
AK		 4553 gpa += handled;
4554 bytes -= handled;
4555 val += handled;
4556
87da7e66
XG		 4557 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4558 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4559 frag->gpa = gpa;
4560 frag->data = val;
4561 frag->len = bytes;
f78146b0 4562 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4563}
4564
52eb5a6d
XL		 4565static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4566 unsigned long addr,
22388a3c
XG		 4567 void *val, unsigned int bytes,
4568 struct x86_exception *exception,
0fbe9b0b 4569 const struct read_write_emulator_ops *ops)
bbd9b64e 4570{
0f65dd70 4571 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4572 gpa_t gpa;
4573 int rc;
4574
4575 if (ops->read_write_prepare &&
4576 ops->read_write_prepare(vcpu, val, bytes))
4577 return X86EMUL_CONTINUE;
4578
4579 vcpu->mmio_nr_fragments = 0;
0f65dd70 4580
bbd9b64e
CO		 4581 /* Crossing a page boundary? */
4582 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4583 int now;
bbd9b64e
CO		 4584
4585 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4586 rc = emulator_read_write_onepage(addr, val, now, exception,
4587 vcpu, ops);
4588
bbd9b64e
CO		 4589 if (rc != X86EMUL_CONTINUE)
4590 return rc;
4591 addr += now;
bac15531
NA		 4592 if (ctxt->mode != X86EMUL_MODE_PROT64)
4593 addr = (u32)addr;
bbd9b64e
CO		 4594 val += now;
4595 bytes -= now;
4596 }
22388a3c 4597
f78146b0
AK		 4598 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4599 vcpu, ops);
4600 if (rc != X86EMUL_CONTINUE)
4601 return rc;
4602
4603 if (!vcpu->mmio_nr_fragments)
4604 return rc;
4605
4606 gpa = vcpu->mmio_fragments[0].gpa;
4607
4608 vcpu->mmio_needed = 1;
4609 vcpu->mmio_cur_fragment = 0;
4610
87da7e66 4611 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4612 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4613 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4614 vcpu->run->mmio.phys_addr = gpa;
4615
4616 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4617}
4618
4619static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4620 unsigned long addr,
4621 void *val,
4622 unsigned int bytes,
4623 struct x86_exception *exception)
4624{
4625 return emulator_read_write(ctxt, addr, val, bytes,
4626 exception, &read_emultor);
4627}
4628
52eb5a6d 4629static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4630 unsigned long addr,
4631 const void *val,
4632 unsigned int bytes,
4633 struct x86_exception *exception)
4634{
4635 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4636 exception, &write_emultor);
bbd9b64e 4637}
bbd9b64e 4638
daea3e73
AK		 4639#define CMPXCHG_TYPE(t, ptr, old, new) \
4640 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4641
4642#ifdef CONFIG_X86_64
4643# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4644#else
4645# define CMPXCHG64(ptr, old, new) \
9749a6c0 4646 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4647#endif
4648
0f65dd70
AK		 4649static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4650 unsigned long addr,
bbd9b64e
CO		 4651 const void *old,
4652 const void *new,
4653 unsigned int bytes,
0f65dd70 4654 struct x86_exception *exception)
bbd9b64e 4655{
0f65dd70 4656 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4657 gpa_t gpa;
4658 struct page *page;
4659 char *kaddr;
4660 bool exchanged;
2bacc55c 4661
daea3e73
AK		 4662 /* guests cmpxchg8b have to be emulated atomically */
4663 if (bytes > 8 || (bytes & (bytes - 1)))
4664 goto emul_write;
10589a46 4665
daea3e73 4666 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4667
daea3e73
AK		 4668 if (gpa == UNMAPPED_GVA ||
4669 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4670 goto emul_write;
2bacc55c 4671
daea3e73
AK		 4672 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4673 goto emul_write;
72dc67a6 4674
54bf36aa 4675 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4676 if (is_error_page(page))
c19b8bd6 4677 goto emul_write;
72dc67a6 4678
8fd75e12 4679 kaddr = kmap_atomic(page);
daea3e73
AK		 4680 kaddr += offset_in_page(gpa);
4681 switch (bytes) {
4682 case 1:
4683 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4684 break;
4685 case 2:
4686 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4687 break;
4688 case 4:
4689 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4690 break;
4691 case 8:
4692 exchanged = CMPXCHG64(kaddr, old, new);
4693 break;
4694 default:
4695 BUG();
2bacc55c 4696 }
8fd75e12 4697 kunmap_atomic(kaddr);
daea3e73
AK		 4698 kvm_release_page_dirty(page);
4699
4700 if (!exchanged)
4701 return X86EMUL_CMPXCHG_FAILED;
4702
54bf36aa 4703 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4704 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4705
4706 return X86EMUL_CONTINUE;
4a5f48f6 4707
3200f405 4708emul_write:
daea3e73 4709 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4710
0f65dd70 4711 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4712}
4713
cf8f70bf
GN		 4714static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4715{
4716 /* TODO: String I/O for in kernel device */
4717 int r;
4718
4719 if (vcpu->arch.pio.in)
e32edf4f 4720 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4721 vcpu->arch.pio.size, pd);
4722 else
e32edf4f 4723 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4724 vcpu->arch.pio.port, vcpu->arch.pio.size,
4725 pd);
4726 return r;
4727}
4728
6f6fbe98
XG		 4729static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4730 unsigned short port, void *val,
4731 unsigned int count, bool in)
cf8f70bf 4732{
cf8f70bf 4733 vcpu->arch.pio.port = port;
6f6fbe98 4734 vcpu->arch.pio.in = in;
7972995b 4735 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4736 vcpu->arch.pio.size = size;
4737
4738 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4739 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4740 return 1;
4741 }
4742
4743 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4744 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4745 vcpu->run->io.size = size;
4746 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4747 vcpu->run->io.count = count;
4748 vcpu->run->io.port = port;
4749
4750 return 0;
4751}
4752
6f6fbe98
XG		 4753static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4754 int size, unsigned short port, void *val,
4755 unsigned int count)
cf8f70bf 4756{
ca1d4a9e 4757 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4758 int ret;
ca1d4a9e 4759
6f6fbe98
XG		 4760 if (vcpu->arch.pio.count)
4761 goto data_avail;
cf8f70bf 4762
6f6fbe98
XG		 4763 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4764 if (ret) {
4765data_avail:
4766 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4767 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4768 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4769 return 1;
4770 }
4771
cf8f70bf
GN		 4772 return 0;
4773}
4774
6f6fbe98
XG		 4775static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4776 int size, unsigned short port,
4777 const void *val, unsigned int count)
4778{
4779 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4780
4781 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4782 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4783 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4784}
4785
bbd9b64e
CO		 4786static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4787{
4788 return kvm_x86_ops->get_segment_base(vcpu, seg);
4789}
4790
3cb16fe7 4791static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4792{
3cb16fe7 4793 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4794}
4795
ae6a2375 4796static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4797{
4798 if (!need_emulate_wbinvd(vcpu))
4799 return X86EMUL_CONTINUE;
4800
4801 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4802 int cpu = get_cpu();
4803
4804 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4805 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4806 wbinvd_ipi, NULL, 1);
2eec7343 4807 put_cpu();
f5f48ee1 4808 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4809 } else
4810 wbinvd();
f5f48ee1
SY		 4811 return X86EMUL_CONTINUE;
4812}
5cb56059
JS		 4813
4814int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4815{
4816 kvm_x86_ops->skip_emulated_instruction(vcpu);
4817 return kvm_emulate_wbinvd_noskip(vcpu);
4818}
f5f48ee1
SY		 4819EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4820
5cb56059
JS		 4821
4822
bcaf5cc5
AK		 4823static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4824{
5cb56059 4825 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4826}
4827
52eb5a6d
XL		 4828static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4829 unsigned long *dest)
bbd9b64e 4830{
16f8a6f9 4831 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4832}
4833
52eb5a6d
XL		 4834static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4835 unsigned long value)
bbd9b64e 4836{
338dbc97 4837
717746e3 4838 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4839}
4840
52a46617 4841static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4842{
52a46617 4843 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4844}
4845
717746e3 4846static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4847{
717746e3 4848 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4849 unsigned long value;
4850
4851 switch (cr) {
4852 case 0:
4853 value = kvm_read_cr0(vcpu);
4854 break;
4855 case 2:
4856 value = vcpu->arch.cr2;
4857 break;
4858 case 3:
9f8fe504 4859 value = kvm_read_cr3(vcpu);
52a46617
GN		 4860 break;
4861 case 4:
4862 value = kvm_read_cr4(vcpu);
4863 break;
4864 case 8:
4865 value = kvm_get_cr8(vcpu);
4866 break;
4867 default:
a737f256 4868 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4869 return 0;
4870 }
4871
4872 return value;
4873}
4874
717746e3 4875static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4876{
717746e3 4877 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4878 int res = 0;
4879
52a46617
GN		 4880 switch (cr) {
4881 case 0:
49a9b07e 4882 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4883 break;
4884 case 2:
4885 vcpu->arch.cr2 = val;
4886 break;
4887 case 3:
2390218b 4888 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4889 break;
4890 case 4:
a83b29c6 4891 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4892 break;
4893 case 8:
eea1cff9 4894 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4895 break;
4896 default:
a737f256 4897 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4898 res = -1;
52a46617 4899 }
0f12244f
GN		 4900
4901 return res;
52a46617
GN		 4902}
4903
717746e3 4904static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4905{
717746e3 4906 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4907}
4908
4bff1e86 4909static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4910{
4bff1e86 4911 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4912}
4913
4bff1e86 4914static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4915{
4bff1e86 4916 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4917}
4918
1ac9d0cf
AK		 4919static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4920{
4921 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4922}
4923
4924static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4925{
4926 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4927}
4928
4bff1e86
AK		 4929static unsigned long emulator_get_cached_segment_base(
4930 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4931{
4bff1e86 4932 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4933}
4934
1aa36616
AK		 4935static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4936 struct desc_struct *desc, u32 *base3,
4937 int seg)
2dafc6c2
GN		 4938{
4939 struct kvm_segment var;
4940
4bff1e86 4941 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4942 *selector = var.selector;
2dafc6c2 4943
378a8b09
GN		 4944 if (var.unusable) {
4945 memset(desc, 0, sizeof(*desc));
2dafc6c2 4946 return false;
378a8b09 4947 }
2dafc6c2
GN		 4948
4949 if (var.g)
4950 var.limit >>= 12;
4951 set_desc_limit(desc, var.limit);
4952 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4953#ifdef CONFIG_X86_64
4954 if (base3)
4955 *base3 = var.base >> 32;
4956#endif
2dafc6c2
GN		 4957 desc->type = var.type;
4958 desc->s = var.s;
4959 desc->dpl = var.dpl;
4960 desc->p = var.present;
4961 desc->avl = var.avl;
4962 desc->l = var.l;
4963 desc->d = var.db;
4964 desc->g = var.g;
4965
4966 return true;
4967}
4968
1aa36616
AK		 4969static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4970 struct desc_struct *desc, u32 base3,
4971 int seg)
2dafc6c2 4972{
4bff1e86 4973 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4974 struct kvm_segment var;
4975
1aa36616 4976 var.selector = selector;
2dafc6c2 4977 var.base = get_desc_base(desc);
5601d05b
GN		 4978#ifdef CONFIG_X86_64
4979 var.base |= ((u64)base3) << 32;
4980#endif
2dafc6c2
GN		 4981 var.limit = get_desc_limit(desc);
4982 if (desc->g)
4983 var.limit = (var.limit << 12) | 0xfff;
4984 var.type = desc->type;
2dafc6c2
GN		 4985 var.dpl = desc->dpl;
4986 var.db = desc->d;
4987 var.s = desc->s;
4988 var.l = desc->l;
4989 var.g = desc->g;
4990 var.avl = desc->avl;
4991 var.present = desc->p;
4992 var.unusable = !var.present;
4993 var.padding = 0;
4994
4995 kvm_set_segment(vcpu, &var, seg);
4996 return;
4997}
4998
717746e3
AK		 4999static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5000 u32 msr_index, u64 *pdata)
5001{
609e36d3
PB		 5002 struct msr_data msr;
5003 int r;
5004
5005 msr.index = msr_index;
5006 msr.host_initiated = false;
5007 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5008 if (r)
5009 return r;
5010
5011 *pdata = msr.data;
5012 return 0;
717746e3
AK		 5013}
5014
5015static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5016 u32 msr_index, u64 data)
5017{
8fe8ab46
WA		 5018 struct msr_data msr;
5019
5020 msr.data = data;
5021 msr.index = msr_index;
5022 msr.host_initiated = false;
5023 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5024}
5025
64d60670
PB		 5026static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5027{
5028 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5029
5030 return vcpu->arch.smbase;
5031}
5032
5033static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5034{
5035 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5036
5037 vcpu->arch.smbase = smbase;
5038}
5039
67f4d428
NA		 5040static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5041 u32 pmc)
5042{
c6702c9d 5043 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5044}
5045
222d21aa
AK		 5046static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5047 u32 pmc, u64 *pdata)
5048{
c6702c9d 5049 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5050}
5051
6c3287f7
AK		 5052static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5053{
5054 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5055}
5056
5037f6f3
AK		 5057static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5058{
5059 preempt_disable();
5197b808 5060 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5061 /*
5062 * CR0.TS may reference the host fpu state, not the guest fpu state,
5063 * so it may be clear at this point.
5064 */
5065 clts();
5066}
5067
5068static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5069{
5070 preempt_enable();
5071}
5072
2953538e 5073static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5074 struct x86_instruction_info *info,
c4f035c6
AK		 5075 enum x86_intercept_stage stage)
5076{
2953538e 5077 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5078}
5079
0017f93a 5080static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5081 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5082{
0017f93a 5083 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5084}
5085
dd856efa
AK		 5086static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5087{
5088 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5089}
5090
5091static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5092{
5093 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5094}
5095
801806d9
NA		 5096static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5097{
5098 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5099}
5100
0225fb50 5101static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5102 .read_gpr = emulator_read_gpr,
5103 .write_gpr = emulator_write_gpr,
1871c602 5104 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5105 .write_std = kvm_write_guest_virt_system,
7a036a6f 5106 .read_phys = kvm_read_guest_phys_system,
1871c602 5107 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5108 .read_emulated = emulator_read_emulated,
5109 .write_emulated = emulator_write_emulated,
5110 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5111 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5112 .pio_in_emulated = emulator_pio_in_emulated,
5113 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5114 .get_segment = emulator_get_segment,
5115 .set_segment = emulator_set_segment,
5951c442 5116 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5117 .get_gdt = emulator_get_gdt,
160ce1f1 5118 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5119 .set_gdt = emulator_set_gdt,
5120 .set_idt = emulator_set_idt,
52a46617
GN		 5121 .get_cr = emulator_get_cr,
5122 .set_cr = emulator_set_cr,
9c537244 5123 .cpl = emulator_get_cpl,
35aa5375
GN		 5124 .get_dr = emulator_get_dr,
5125 .set_dr = emulator_set_dr,
64d60670
PB		 5126 .get_smbase = emulator_get_smbase,
5127 .set_smbase = emulator_set_smbase,
717746e3
AK		 5128 .set_msr = emulator_set_msr,
5129 .get_msr = emulator_get_msr,
67f4d428 5130 .check_pmc = emulator_check_pmc,
222d21aa 5131 .read_pmc = emulator_read_pmc,
6c3287f7 5132 .halt = emulator_halt,
bcaf5cc5 5133 .wbinvd = emulator_wbinvd,
d6aa1000 5134 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5135 .get_fpu = emulator_get_fpu,
5136 .put_fpu = emulator_put_fpu,
c4f035c6 5137 .intercept = emulator_intercept,
bdb42f5a 5138 .get_cpuid = emulator_get_cpuid,
801806d9 5139 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5140};
5141
95cb2295
GN		 5142static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5143{
37ccdcbe 5144 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5145 /*
5146 * an sti; sti; sequence only disable interrupts for the first
5147 * instruction. So, if the last instruction, be it emulated or
5148 * not, left the system with the INT_STI flag enabled, it
5149 * means that the last instruction is an sti. We should not
5150 * leave the flag on in this case. The same goes for mov ss
5151 */
37ccdcbe
PB		 5152 if (int_shadow & mask)
5153 mask = 0;
6addfc42 5154 if (unlikely(int_shadow || mask)) {
95cb2295 5155 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5156 if (!mask)
5157 kvm_make_request(KVM_REQ_EVENT, vcpu);
5158 }
95cb2295
GN		 5159}
5160
ef54bcfe 5161static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5162{
5163 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5164 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5165 return kvm_propagate_fault(vcpu, &ctxt->exception);
5166
5167 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5168 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5169 ctxt->exception.error_code);
54b8486f 5170 else
da9cb575 5171 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5172 return false;
54b8486f
GN		 5173}
5174
8ec4722d
MG		 5175static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5176{
adf52235 5177 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5178 int cs_db, cs_l;
5179
8ec4722d
MG		 5180 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5181
adf52235
TY		 5182 ctxt->eflags = kvm_get_rflags(vcpu);
5183 ctxt->eip = kvm_rip_read(vcpu);
5184 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5185 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5186 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5187 cs_db ? X86EMUL_MODE_PROT32 :
5188 X86EMUL_MODE_PROT16;
a584539b 5189 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5190 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5191 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5192 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5193
dd856efa 5194 init_decode_cache(ctxt);
7ae441ea 5195 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5196}
5197
71f9833b 5198int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5199{
9d74191a 5200 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5201 int ret;
5202
5203 init_emulate_ctxt(vcpu);
5204
9dac77fa
AK		 5205 ctxt->op_bytes = 2;
5206 ctxt->ad_bytes = 2;
5207 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5208 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5209
5210 if (ret != X86EMUL_CONTINUE)
5211 return EMULATE_FAIL;
5212
9dac77fa 5213 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5214 kvm_rip_write(vcpu, ctxt->eip);
5215 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5216
5217 if (irq == NMI_VECTOR)
7460fb4a 5218 vcpu->arch.nmi_pending = 0;
63995653
MG		 5219 else
5220 vcpu->arch.interrupt.pending = false;
5221
5222 return EMULATE_DONE;
5223}
5224EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5225
6d77dbfc
GN		 5226static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5227{
fc3a9157
JR		 5228 int r = EMULATE_DONE;
5229
6d77dbfc
GN		 5230 ++vcpu->stat.insn_emulation_fail;
5231 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5232 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5233 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5234 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5235 vcpu->run->internal.ndata = 0;
5236 r = EMULATE_FAIL;
5237 }
6d77dbfc 5238 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5239
5240 return r;
6d77dbfc
GN		 5241}
5242
93c05d3e 5243static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5244 bool write_fault_to_shadow_pgtable,
5245 int emulation_type)
a6f177ef 5246{
95b3cf69 5247 gpa_t gpa = cr2;
ba049e93 5248 kvm_pfn_t pfn;
a6f177ef 5249
991eebf9
GN		 5250 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5251 return false;
5252
95b3cf69
XG		 5253 if (!vcpu->arch.mmu.direct_map) {
5254 /*
5255 * Write permission should be allowed since only
5256 * write access need to be emulated.
5257 */
5258 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5259
95b3cf69
XG		 5260 /*
5261 * If the mapping is invalid in guest, let cpu retry
5262 * it to generate fault.
5263 */
5264 if (gpa == UNMAPPED_GVA)
5265 return true;
5266 }
a6f177ef 5267
8e3d9d06
XG		 5268 /*
5269 * Do not retry the unhandleable instruction if it faults on the
5270 * readonly host memory, otherwise it will goto a infinite loop:
5271 * retry instruction -> write #PF -> emulation fail -> retry
5272 * instruction -> ...
5273 */
5274 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5275
5276 /*
5277 * If the instruction failed on the error pfn, it can not be fixed,
5278 * report the error to userspace.
5279 */
5280 if (is_error_noslot_pfn(pfn))
5281 return false;
5282
5283 kvm_release_pfn_clean(pfn);
5284
5285 /* The instructions are well-emulated on direct mmu. */
5286 if (vcpu->arch.mmu.direct_map) {
5287 unsigned int indirect_shadow_pages;
5288
5289 spin_lock(&vcpu->kvm->mmu_lock);
5290 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5291 spin_unlock(&vcpu->kvm->mmu_lock);
5292
5293 if (indirect_shadow_pages)
5294 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5295
a6f177ef 5296 return true;
8e3d9d06 5297 }
a6f177ef 5298
95b3cf69
XG		 5299 /*
5300 * if emulation was due to access to shadowed page table
5301 * and it failed try to unshadow page and re-enter the
5302 * guest to let CPU execute the instruction.
5303 */
5304 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5305
5306 /*
5307 * If the access faults on its page table, it can not
5308 * be fixed by unprotecting shadow page and it should
5309 * be reported to userspace.
5310 */
5311 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5312}
5313
1cb3f3ae
XG		 5314static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5315 unsigned long cr2, int emulation_type)
5316{
5317 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5318 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5319
5320 last_retry_eip = vcpu->arch.last_retry_eip;
5321 last_retry_addr = vcpu->arch.last_retry_addr;
5322
5323 /*
5324 * If the emulation is caused by #PF and it is non-page_table
5325 * writing instruction, it means the VM-EXIT is caused by shadow
5326 * page protected, we can zap the shadow page and retry this
5327 * instruction directly.
5328 *
5329 * Note: if the guest uses a non-page-table modifying instruction
5330 * on the PDE that points to the instruction, then we will unmap
5331 * the instruction and go to an infinite loop. So, we cache the
5332 * last retried eip and the last fault address, if we meet the eip
5333 * and the address again, we can break out of the potential infinite
5334 * loop.
5335 */
5336 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5337
5338 if (!(emulation_type & EMULTYPE_RETRY))
5339 return false;
5340
5341 if (x86_page_table_writing_insn(ctxt))
5342 return false;
5343
5344 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5345 return false;
5346
5347 vcpu->arch.last_retry_eip = ctxt->eip;
5348 vcpu->arch.last_retry_addr = cr2;
5349
5350 if (!vcpu->arch.mmu.direct_map)
5351 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5352
22368028 5353 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5354
5355 return true;
5356}
5357
716d51ab
GN		 5358static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5359static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5360
64d60670 5361static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5362{
64d60670 5363 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5364 /* This is a good place to trace that we are exiting SMM. */
5365 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5366
c43203ca
PB		 5367 /* Process a latched INIT or SMI, if any. */
5368 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5369 }
699023e2
PB		 5370
5371 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5372}
5373
5374static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5375{
5376 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5377
a584539b 5378 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5379
5380 if (changed & HF_SMM_MASK)
5381 kvm_smm_changed(vcpu);
a584539b
PB		 5382}
5383
4a1e10d5
PB		 5384static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5385 unsigned long *db)
5386{
5387 u32 dr6 = 0;
5388 int i;
5389 u32 enable, rwlen;
5390
5391 enable = dr7;
5392 rwlen = dr7 >> 16;
5393 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5394 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5395 dr6 |= (1 << i);
5396 return dr6;
5397}
5398
6addfc42 5399static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5400{
5401 struct kvm_run *kvm_run = vcpu->run;
5402
5403 /*
6addfc42
PB		 5404 * rflags is the old, "raw" value of the flags. The new value has
5405 * not been saved yet.
663f4c61
PB		 5406 *
5407 * This is correct even for TF set by the guest, because "the
5408 * processor will not generate this exception after the instruction
5409 * that sets the TF flag".
5410 */
663f4c61
PB		 5411 if (unlikely(rflags & X86_EFLAGS_TF)) {
5412 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5413 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5414 DR6_RTM;
663f4c61
PB		 5415 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5416 kvm_run->debug.arch.exception = DB_VECTOR;
5417 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5418 *r = EMULATE_USER_EXIT;
5419 } else {
5420 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5421 /*
5422 * "Certain debug exceptions may clear bit 0-3. The
5423 * remaining contents of the DR6 register are never
5424 * cleared by the processor".
5425 */
5426 vcpu->arch.dr6 &= ~15;
6f43ed01 5427 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5428 kvm_queue_exception(vcpu, DB_VECTOR);
5429 }
5430 }
5431}
5432
4a1e10d5
PB		 5433static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5434{
4a1e10d5
PB		 5435 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5436 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5437 struct kvm_run *kvm_run = vcpu->run;
5438 unsigned long eip = kvm_get_linear_rip(vcpu);
5439 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5440 vcpu->arch.guest_debug_dr7,
5441 vcpu->arch.eff_db);
5442
5443 if (dr6 != 0) {
6f43ed01 5444 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5445 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5446 kvm_run->debug.arch.exception = DB_VECTOR;
5447 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5448 *r = EMULATE_USER_EXIT;
5449 return true;
5450 }
5451 }
5452
4161a569
NA		 5453 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5454 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5455 unsigned long eip = kvm_get_linear_rip(vcpu);
5456 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5457 vcpu->arch.dr7,
5458 vcpu->arch.db);
5459
5460 if (dr6 != 0) {
5461 vcpu->arch.dr6 &= ~15;
6f43ed01 5462 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5463 kvm_queue_exception(vcpu, DB_VECTOR);
5464 *r = EMULATE_DONE;
5465 return true;
5466 }
5467 }
5468
5469 return false;
5470}
5471
51d8b661
AP		 5472int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5473 unsigned long cr2,
dc25e89e
AP		 5474 int emulation_type,
5475 void *insn,
5476 int insn_len)
bbd9b64e 5477{
95cb2295 5478 int r;
9d74191a 5479 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5480 bool writeback = true;
93c05d3e 5481 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5482
93c05d3e
XG		 5483 /*
5484 * Clear write_fault_to_shadow_pgtable here to ensure it is
5485 * never reused.
5486 */
5487 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5488 kvm_clear_exception_queue(vcpu);
8d7d8102 5489
571008da 5490 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5491 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5492
5493 /*
5494 * We will reenter on the same instruction since
5495 * we do not set complete_userspace_io. This does not
5496 * handle watchpoints yet, those would be handled in
5497 * the emulate_ops.
5498 */
5499 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5500 return r;
5501
9d74191a
TY		 5502 ctxt->interruptibility = 0;
5503 ctxt->have_exception = false;
e0ad0b47 5504 ctxt->exception.vector = -1;
9d74191a 5505 ctxt->perm_ok = false;
bbd9b64e 5506
b51e974f 5507 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5508
9d74191a 5509 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5510
e46479f8 5511 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5512 ++vcpu->stat.insn_emulation;
1d2887e2 5513 if (r != EMULATION_OK) {
4005996e
AK		 5514 if (emulation_type & EMULTYPE_TRAP_UD)
5515 return EMULATE_FAIL;
991eebf9
GN		 5516 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5517 emulation_type))
bbd9b64e 5518 return EMULATE_DONE;
6d77dbfc
GN		 5519 if (emulation_type & EMULTYPE_SKIP)
5520 return EMULATE_FAIL;
5521 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5522 }
5523 }
5524
ba8afb6b 5525 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5526 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5527 if (ctxt->eflags & X86_EFLAGS_RF)
5528 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5529 return EMULATE_DONE;
5530 }
5531
1cb3f3ae
XG		 5532 if (retry_instruction(ctxt, cr2, emulation_type))
5533 return EMULATE_DONE;
5534
7ae441ea 5535 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5536 changes registers values during IO operation */
7ae441ea
GN		 5537 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5538 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5539 emulator_invalidate_register_cache(ctxt);
7ae441ea 5540 }
4d2179e1 5541
5cd21917 5542restart:
9d74191a 5543 r = x86_emulate_insn(ctxt);
bbd9b64e 5544
775fde86
JR		 5545 if (r == EMULATION_INTERCEPTED)
5546 return EMULATE_DONE;
5547
d2ddd1c4 5548 if (r == EMULATION_FAILED) {
991eebf9
GN		 5549 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5550 emulation_type))
c3cd7ffa
GN		 5551 return EMULATE_DONE;
5552
6d77dbfc 5553 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5554 }
5555
9d74191a 5556 if (ctxt->have_exception) {
d2ddd1c4 5557 r = EMULATE_DONE;
ef54bcfe
PB		 5558 if (inject_emulated_exception(vcpu))
5559 return r;
d2ddd1c4 5560 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5561 if (!vcpu->arch.pio.in) {
5562 /* FIXME: return into emulator if single-stepping. */
3457e419 5563 vcpu->arch.pio.count = 0;
0912c977 5564 } else {
7ae441ea 5565 writeback = false;
716d51ab
GN		 5566 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5567 }
ac0a48c3 5568 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5569 } else if (vcpu->mmio_needed) {
5570 if (!vcpu->mmio_is_write)
5571 writeback = false;
ac0a48c3 5572 r = EMULATE_USER_EXIT;
716d51ab 5573 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5574 } else if (r == EMULATION_RESTART)
5cd21917 5575 goto restart;
d2ddd1c4
GN		 5576 else
5577 r = EMULATE_DONE;
f850e2e6 5578
7ae441ea 5579 if (writeback) {
6addfc42 5580 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5581 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5582 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5583 if (vcpu->arch.hflags != ctxt->emul_flags)
5584 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5585 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5586 if (r == EMULATE_DONE)
6addfc42 5587 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5588 if (!ctxt->have_exception ||
5589 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5590 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5591
5592 /*
5593 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5594 * do nothing, and it will be requested again as soon as
5595 * the shadow expires. But we still need to check here,
5596 * because POPF has no interrupt shadow.
5597 */
5598 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5599 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5600 } else
5601 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5602
5603 return r;
de7d789a 5604}
51d8b661 5605EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5606
cf8f70bf 5607int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5608{
cf8f70bf 5609 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5610 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5611 size, port, &val, 1);
cf8f70bf 5612 /* do not return to emulator after return from userspace */
7972995b 5613 vcpu->arch.pio.count = 0;
de7d789a
CO		 5614 return ret;
5615}
cf8f70bf 5616EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5617
8370c3d0
TL		 5618static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5619{
5620 unsigned long val;
5621
5622 /* We should only ever be called with arch.pio.count equal to 1 */
5623 BUG_ON(vcpu->arch.pio.count != 1);
5624
5625 /* For size less than 4 we merge, else we zero extend */
5626 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5627 : 0;
5628
5629 /*
5630 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5631 * the copy and tracing
5632 */
5633 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5634 vcpu->arch.pio.port, &val, 1);
5635 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5636
5637 return 1;
5638}
5639
5640int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5641{
5642 unsigned long val;
5643 int ret;
5644
5645 /* For size less than 4 we merge, else we zero extend */
5646 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5647
5648 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5649 &val, 1);
5650 if (ret) {
5651 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5652 return ret;
5653 }
5654
5655 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5656
5657 return 0;
5658}
5659EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5660
251a5fd6 5661static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5662{
0a3aee0d 5663 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5664 return 0;
8cfdc000
ZA		 5665}
5666
5667static void tsc_khz_changed(void *data)
c8076604 5668{
8cfdc000
ZA		 5669 struct cpufreq_freqs *freq = data;
5670 unsigned long khz = 0;
5671
5672 if (data)
5673 khz = freq->new;
5674 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5675 khz = cpufreq_quick_get(raw_smp_processor_id());
5676 if (!khz)
5677 khz = tsc_khz;
0a3aee0d 5678 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5679}
5680
c8076604
GH		 5681static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5682 void *data)
5683{
5684 struct cpufreq_freqs *freq = data;
5685 struct kvm *kvm;
5686 struct kvm_vcpu *vcpu;
5687 int i, send_ipi = 0;
5688
8cfdc000
ZA		 5689 /*
5690 * We allow guests to temporarily run on slowing clocks,
5691 * provided we notify them after, or to run on accelerating
5692 * clocks, provided we notify them before. Thus time never
5693 * goes backwards.
5694 *
5695 * However, we have a problem. We can't atomically update
5696 * the frequency of a given CPU from this function; it is
5697 * merely a notifier, which can be called from any CPU.
5698 * Changing the TSC frequency at arbitrary points in time
5699 * requires a recomputation of local variables related to
5700 * the TSC for each VCPU. We must flag these local variables
5701 * to be updated and be sure the update takes place with the
5702 * new frequency before any guests proceed.
5703 *
5704 * Unfortunately, the combination of hotplug CPU and frequency
5705 * change creates an intractable locking scenario; the order
5706 * of when these callouts happen is undefined with respect to
5707 * CPU hotplug, and they can race with each other. As such,
5708 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5709 * undefined; you can actually have a CPU frequency change take
5710 * place in between the computation of X and the setting of the
5711 * variable. To protect against this problem, all updates of
5712 * the per_cpu tsc_khz variable are done in an interrupt
5713 * protected IPI, and all callers wishing to update the value
5714 * must wait for a synchronous IPI to complete (which is trivial
5715 * if the caller is on the CPU already). This establishes the
5716 * necessary total order on variable updates.
5717 *
5718 * Note that because a guest time update may take place
5719 * anytime after the setting of the VCPU's request bit, the
5720 * correct TSC value must be set before the request. However,
5721 * to ensure the update actually makes it to any guest which
5722 * starts running in hardware virtualization between the set
5723 * and the acquisition of the spinlock, we must also ping the
5724 * CPU after setting the request bit.
5725 *
5726 */
5727
c8076604
GH		 5728 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5729 return 0;
5730 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5731 return 0;
8cfdc000
ZA		 5732
5733 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5734
2f303b74 5735 spin_lock(&kvm_lock);
c8076604 5736 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5737 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5738 if (vcpu->cpu != freq->cpu)
5739 continue;
c285545f 5740 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5741 if (vcpu->cpu != smp_processor_id())
8cfdc000 5742 send_ipi = 1;
c8076604
GH		 5743 }
5744 }
2f303b74 5745 spin_unlock(&kvm_lock);
c8076604
GH		 5746
5747 if (freq->old < freq->new && send_ipi) {
5748 /*
5749 * We upscale the frequency. Must make the guest
5750 * doesn't see old kvmclock values while running with
5751 * the new frequency, otherwise we risk the guest sees
5752 * time go backwards.
5753 *
5754 * In case we update the frequency for another cpu
5755 * (which might be in guest context) send an interrupt
5756 * to kick the cpu out of guest context. Next time
5757 * guest context is entered kvmclock will be updated,
5758 * so the guest will not see stale values.
5759 */
8cfdc000 5760 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5761 }
5762 return 0;
5763}
5764
5765static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5766 .notifier_call = kvmclock_cpufreq_notifier
5767};
5768
251a5fd6 5769static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5770{
251a5fd6
SAS		 5771 tsc_khz_changed(NULL);
5772 return 0;
8cfdc000
ZA		 5773}
5774
b820cc0c
ZA		 5775static void kvm_timer_init(void)
5776{
c285545f 5777 max_tsc_khz = tsc_khz;
460dd42e 5778
b820cc0c 5779 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5780#ifdef CONFIG_CPU_FREQ
5781 struct cpufreq_policy policy;
758f588d
BP		 5782 int cpu;
5783
c285545f 5784 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5785 cpu = get_cpu();
5786 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5787 if (policy.cpuinfo.max_freq)
5788 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5789 put_cpu();
c285545f 5790#endif
b820cc0c
ZA		 5791 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5792 CPUFREQ_TRANSITION_NOTIFIER);
5793 }
c285545f 5794 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5795
251a5fd6
SAS		 5796 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "AP_X86_KVM_CLK_ONLINE",
5797 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5798}
5799
ff9d07a0
ZY		 5800static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5801
f5132b01 5802int kvm_is_in_guest(void)
ff9d07a0 5803{
086c9855 5804 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5805}
5806
5807static int kvm_is_user_mode(void)
5808{
5809 int user_mode = 3;
dcf46b94 5810
086c9855
AS		 5811 if (__this_cpu_read(current_vcpu))
5812 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5813
ff9d07a0
ZY		 5814 return user_mode != 0;
5815}
5816
5817static unsigned long kvm_get_guest_ip(void)
5818{
5819 unsigned long ip = 0;
dcf46b94 5820
086c9855
AS		 5821 if (__this_cpu_read(current_vcpu))
5822 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5823
ff9d07a0
ZY		 5824 return ip;
5825}
5826
5827static struct perf_guest_info_callbacks kvm_guest_cbs = {
5828 .is_in_guest = kvm_is_in_guest,
5829 .is_user_mode = kvm_is_user_mode,
5830 .get_guest_ip = kvm_get_guest_ip,
5831};
5832
5833void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5834{
086c9855 5835 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5836}
5837EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5838
5839void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5840{
086c9855 5841 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5842}
5843EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5844
ce88decf
XG		 5845static void kvm_set_mmio_spte_mask(void)
5846{
5847 u64 mask;
5848 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5849
5850 /*
5851 * Set the reserved bits and the present bit of an paging-structure
5852 * entry to generate page fault with PFER.RSV = 1.
5853 */
885032b9 5854 /* Mask the reserved physical address bits. */
d1431483 5855 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5856
5857 /* Bit 62 is always reserved for 32bit host. */
5858 mask |= 0x3ull << 62;
5859
5860 /* Set the present bit. */
ce88decf
XG		 5861 mask |= 1ull;
5862
5863#ifdef CONFIG_X86_64
5864 /*
5865 * If reserved bit is not supported, clear the present bit to disable
5866 * mmio page fault.
5867 */
5868 if (maxphyaddr == 52)
5869 mask &= ~1ull;
5870#endif
5871
5872 kvm_mmu_set_mmio_spte_mask(mask);
5873}
5874
16e8d74d
MT		 5875#ifdef CONFIG_X86_64
5876static void pvclock_gtod_update_fn(struct work_struct *work)
5877{
d828199e
MT		 5878 struct kvm *kvm;
5879
5880 struct kvm_vcpu *vcpu;
5881 int i;
5882
2f303b74 5883 spin_lock(&kvm_lock);
d828199e
MT		 5884 list_for_each_entry(kvm, &vm_list, vm_list)
5885 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5886 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5887 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5888 spin_unlock(&kvm_lock);
16e8d74d
MT		 5889}
5890
5891static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5892
5893/*
5894 * Notification about pvclock gtod data update.
5895 */
5896static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5897 void *priv)
5898{
5899 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5900 struct timekeeper *tk = priv;
5901
5902 update_pvclock_gtod(tk);
5903
5904 /* disable master clock if host does not trust, or does not
5905 * use, TSC clocksource
5906 */
5907 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5908 atomic_read(&kvm_guest_has_master_clock) != 0)
5909 queue_work(system_long_wq, &pvclock_gtod_work);
5910
5911 return 0;
5912}
5913
5914static struct notifier_block pvclock_gtod_notifier = {
5915 .notifier_call = pvclock_gtod_notify,
5916};
5917#endif
5918
f8c16bba 5919int kvm_arch_init(void *opaque)
043405e1 5920{
b820cc0c 5921 int r;
6b61edf7 5922 struct kvm_x86_ops *ops = opaque;
f8c16bba 5923
f8c16bba
ZX		 5924 if (kvm_x86_ops) {
5925 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5926 r = -EEXIST;
5927 goto out;
f8c16bba
ZX		 5928 }
5929
5930 if (!ops->cpu_has_kvm_support()) {
5931 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5932 r = -EOPNOTSUPP;
5933 goto out;
f8c16bba
ZX		 5934 }
5935 if (ops->disabled_by_bios()) {
5936 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5937 r = -EOPNOTSUPP;
5938 goto out;
f8c16bba
ZX		 5939 }
5940
013f6a5d
MT		 5941 r = -ENOMEM;
5942 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5943 if (!shared_msrs) {
5944 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5945 goto out;
5946 }
5947
97db56ce
AK		 5948 r = kvm_mmu_module_init();
5949 if (r)
013f6a5d 5950 goto out_free_percpu;
97db56ce 5951
ce88decf 5952 kvm_set_mmio_spte_mask();
97db56ce 5953
f8c16bba 5954 kvm_x86_ops = ops;
920c8377 5955
7b52345e 5956 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8
BD		 5957 PT_DIRTY_MASK, PT64_NX_MASK, 0,
5958 PT_PRESENT_MASK);
b820cc0c 5959 kvm_timer_init();
c8076604 5960
ff9d07a0
ZY		 5961 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5962
d366bf7e 5963 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 5964 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5965
c5cc421b 5966 kvm_lapic_init();
16e8d74d
MT		 5967#ifdef CONFIG_X86_64
5968 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5969#endif
5970
f8c16bba 5971 return 0;
56c6d28a 5972
013f6a5d
MT		 5973out_free_percpu:
5974 free_percpu(shared_msrs);
56c6d28a 5975out:
56c6d28a 5976 return r;
043405e1 5977}
8776e519 5978
f8c16bba
ZX		 5979void kvm_arch_exit(void)
5980{
ff9d07a0
ZY		 5981 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5982
888d256e
JK		 5983 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5984 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5985 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 5986 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 5987#ifdef CONFIG_X86_64
5988 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5989#endif
f8c16bba 5990 kvm_x86_ops = NULL;
56c6d28a 5991 kvm_mmu_module_exit();
013f6a5d 5992 free_percpu(shared_msrs);
56c6d28a 5993}
f8c16bba 5994
5cb56059 5995int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5996{
5997 ++vcpu->stat.halt_exits;
35754c98 5998 if (lapic_in_kernel(vcpu)) {
a4535290 5999 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6000 return 1;
6001 } else {
6002 vcpu->run->exit_reason = KVM_EXIT_HLT;
6003 return 0;
6004 }
6005}
5cb56059
JS		 6006EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6007
6008int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6009{
6010 kvm_x86_ops->skip_emulated_instruction(vcpu);
6011 return kvm_vcpu_halt(vcpu);
6012}
8776e519
HB		 6013EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6014
6aef266c
SV		 6015/*
6016 * kvm_pv_kick_cpu_op: Kick a vcpu.
6017 *
6018 * @apicid - apicid of vcpu to be kicked.
6019 */
6020static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6021{
24d2166b 6022 struct kvm_lapic_irq lapic_irq;
6aef266c 6023
24d2166b
R		 6024 lapic_irq.shorthand = 0;
6025 lapic_irq.dest_mode = 0;
6026 lapic_irq.dest_id = apicid;
93bbf0b8 6027 lapic_irq.msi_redir_hint = false;
6aef266c 6028
24d2166b 6029 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6030 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6031}
6032
d62caabb
AS		 6033void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6034{
6035 vcpu->arch.apicv_active = false;
6036 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6037}
6038
8776e519
HB		 6039int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6040{
6041 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 6042 int op_64_bit, r = 1;
8776e519 6043
5cb56059
JS		 6044 kvm_x86_ops->skip_emulated_instruction(vcpu);
6045
55cd8e5a
GN		 6046 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6047 return kvm_hv_hypercall(vcpu);
6048
5fdbf976
MT		 6049 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6050 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6051 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6052 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6053 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6054
229456fc 6055 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6056
a449c7aa
NA		 6057 op_64_bit = is_64_bit_mode(vcpu);
6058 if (!op_64_bit) {
8776e519
HB		 6059 nr &= 0xFFFFFFFF;
6060 a0 &= 0xFFFFFFFF;
6061 a1 &= 0xFFFFFFFF;
6062 a2 &= 0xFFFFFFFF;
6063 a3 &= 0xFFFFFFFF;
6064 }
6065
07708c4a
JK		 6066 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6067 ret = -KVM_EPERM;
6068 goto out;
6069 }
6070
8776e519 6071 switch (nr) {
b93463aa
AK		 6072 case KVM_HC_VAPIC_POLL_IRQ:
6073 ret = 0;
6074 break;
6aef266c
SV		 6075 case KVM_HC_KICK_CPU:
6076 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6077 ret = 0;
6078 break;
8776e519
HB		 6079 default:
6080 ret = -KVM_ENOSYS;
6081 break;
6082 }
07708c4a 6083out:
a449c7aa
NA		 6084 if (!op_64_bit)
6085 ret = (u32)ret;
5fdbf976 6086 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6087 ++vcpu->stat.hypercalls;
2f333bcb 6088 return r;
8776e519
HB		 6089}
6090EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6091
b6785def 6092static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6093{
d6aa1000 6094 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6095 char instruction[3];
5fdbf976 6096 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6097
8776e519 6098 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6099
9d74191a 6100 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6101}
6102
851ba692 6103static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6104{
782d422b
MG		 6105 return vcpu->run->request_interrupt_window &&
6106 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6107}
6108
851ba692 6109static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6110{
851ba692
AK		 6111 struct kvm_run *kvm_run = vcpu->run;
6112
91586a3b 6113 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6114 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6115 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6116 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6117 kvm_run->ready_for_interrupt_injection =
6118 pic_in_kernel(vcpu->kvm) ||
782d422b 6119 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6120}
6121
95ba8273
GN		 6122static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6123{
6124 int max_irr, tpr;
6125
6126 if (!kvm_x86_ops->update_cr8_intercept)
6127 return;
6128
bce87cce 6129 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6130 return;
6131
d62caabb
AS		 6132 if (vcpu->arch.apicv_active)
6133 return;
6134
8db3baa2
GN		 6135 if (!vcpu->arch.apic->vapic_addr)
6136 max_irr = kvm_lapic_find_highest_irr(vcpu);
6137 else
6138 max_irr = -1;
95ba8273
GN		 6139
6140 if (max_irr != -1)
6141 max_irr >>= 4;
6142
6143 tpr = kvm_lapic_get_cr8(vcpu);
6144
6145 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6146}
6147
b6b8a145 6148static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6149{
b6b8a145
JK		 6150 int r;
6151
95ba8273 6152 /* try to reinject previous events if any */
b59bb7bd 6153 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6154 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6155 vcpu->arch.exception.has_error_code,
6156 vcpu->arch.exception.error_code);
d6e8c854
NA		 6157
6158 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6159 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6160 X86_EFLAGS_RF);
6161
6bdf0662
NA		 6162 if (vcpu->arch.exception.nr == DB_VECTOR &&
6163 (vcpu->arch.dr7 & DR7_GD)) {
6164 vcpu->arch.dr7 &= ~DR7_GD;
6165 kvm_update_dr7(vcpu);
6166 }
6167
b59bb7bd
GN		 6168 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6169 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6170 vcpu->arch.exception.error_code,
6171 vcpu->arch.exception.reinject);
b6b8a145 6172 return 0;
b59bb7bd
GN		 6173 }
6174
95ba8273
GN		 6175 if (vcpu->arch.nmi_injected) {
6176 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6177 return 0;
95ba8273
GN		 6178 }
6179
6180 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6181 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6182 return 0;
6183 }
6184
6185 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6186 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6187 if (r != 0)
6188 return r;
95ba8273
GN		 6189 }
6190
6191 /* try to inject new event if pending */
c43203ca
PB		 6192 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6193 vcpu->arch.smi_pending = false;
ee2cd4b7 6194 enter_smm(vcpu);
c43203ca 6195 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6196 --vcpu->arch.nmi_pending;
6197 vcpu->arch.nmi_injected = true;
6198 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6199 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6200 /*
6201 * Because interrupts can be injected asynchronously, we are
6202 * calling check_nested_events again here to avoid a race condition.
6203 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6204 * proposal and current concerns. Perhaps we should be setting
6205 * KVM_REQ_EVENT only on certain events and not unconditionally?
6206 */
6207 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6208 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6209 if (r != 0)
6210 return r;
6211 }
95ba8273 6212 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6213 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6214 false);
6215 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6216 }
6217 }
ee2cd4b7 6218
b6b8a145 6219 return 0;
95ba8273
GN		 6220}
6221
7460fb4a
AK		 6222static void process_nmi(struct kvm_vcpu *vcpu)
6223{
6224 unsigned limit = 2;
6225
6226 /*
6227 * x86 is limited to one NMI running, and one NMI pending after it.
6228 * If an NMI is already in progress, limit further NMIs to just one.
6229 * Otherwise, allow two (and we'll inject the first one immediately).
6230 */
6231 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6232 limit = 1;
6233
6234 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6235 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6236 kvm_make_request(KVM_REQ_EVENT, vcpu);
6237}
6238
660a5d51
PB		 6239#define put_smstate(type, buf, offset, val) \
6240 *(type *)((buf) + (offset) - 0x7e00) = val
6241
ee2cd4b7 6242static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6243{
6244 u32 flags = 0;
6245 flags |= seg->g << 23;
6246 flags |= seg->db << 22;
6247 flags |= seg->l << 21;
6248 flags |= seg->avl << 20;
6249 flags |= seg->present << 15;
6250 flags |= seg->dpl << 13;
6251 flags |= seg->s << 12;
6252 flags |= seg->type << 8;
6253 return flags;
6254}
6255
ee2cd4b7 6256static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6257{
6258 struct kvm_segment seg;
6259 int offset;
6260
6261 kvm_get_segment(vcpu, &seg, n);
6262 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6263
6264 if (n < 3)
6265 offset = 0x7f84 + n * 12;
6266 else
6267 offset = 0x7f2c + (n - 3) * 12;
6268
6269 put_smstate(u32, buf, offset + 8, seg.base);
6270 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6271 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6272}
6273
efbb288a 6274#ifdef CONFIG_X86_64
ee2cd4b7 6275static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6276{
6277 struct kvm_segment seg;
6278 int offset;
6279 u16 flags;
6280
6281 kvm_get_segment(vcpu, &seg, n);
6282 offset = 0x7e00 + n * 16;
6283
ee2cd4b7 6284 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6285 put_smstate(u16, buf, offset, seg.selector);
6286 put_smstate(u16, buf, offset + 2, flags);
6287 put_smstate(u32, buf, offset + 4, seg.limit);
6288 put_smstate(u64, buf, offset + 8, seg.base);
6289}
efbb288a 6290#endif
660a5d51 6291
ee2cd4b7 6292static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6293{
6294 struct desc_ptr dt;
6295 struct kvm_segment seg;
6296 unsigned long val;
6297 int i;
6298
6299 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6300 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6301 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6302 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6303
6304 for (i = 0; i < 8; i++)
6305 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6306
6307 kvm_get_dr(vcpu, 6, &val);
6308 put_smstate(u32, buf, 0x7fcc, (u32)val);
6309 kvm_get_dr(vcpu, 7, &val);
6310 put_smstate(u32, buf, 0x7fc8, (u32)val);
6311
6312 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6313 put_smstate(u32, buf, 0x7fc4, seg.selector);
6314 put_smstate(u32, buf, 0x7f64, seg.base);
6315 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6316 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6317
6318 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6319 put_smstate(u32, buf, 0x7fc0, seg.selector);
6320 put_smstate(u32, buf, 0x7f80, seg.base);
6321 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6322 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6323
6324 kvm_x86_ops->get_gdt(vcpu, &dt);
6325 put_smstate(u32, buf, 0x7f74, dt.address);
6326 put_smstate(u32, buf, 0x7f70, dt.size);
6327
6328 kvm_x86_ops->get_idt(vcpu, &dt);
6329 put_smstate(u32, buf, 0x7f58, dt.address);
6330 put_smstate(u32, buf, 0x7f54, dt.size);
6331
6332 for (i = 0; i < 6; i++)
ee2cd4b7 6333 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6334
6335 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6336
6337 /* revision id */
6338 put_smstate(u32, buf, 0x7efc, 0x00020000);
6339 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6340}
6341
ee2cd4b7 6342static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6343{
6344#ifdef CONFIG_X86_64
6345 struct desc_ptr dt;
6346 struct kvm_segment seg;
6347 unsigned long val;
6348 int i;
6349
6350 for (i = 0; i < 16; i++)
6351 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6352
6353 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6354 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6355
6356 kvm_get_dr(vcpu, 6, &val);
6357 put_smstate(u64, buf, 0x7f68, val);
6358 kvm_get_dr(vcpu, 7, &val);
6359 put_smstate(u64, buf, 0x7f60, val);
6360
6361 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6362 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6363 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6364
6365 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6366
6367 /* revision id */
6368 put_smstate(u32, buf, 0x7efc, 0x00020064);
6369
6370 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6371
6372 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6373 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6374 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6375 put_smstate(u32, buf, 0x7e94, seg.limit);
6376 put_smstate(u64, buf, 0x7e98, seg.base);
6377
6378 kvm_x86_ops->get_idt(vcpu, &dt);
6379 put_smstate(u32, buf, 0x7e84, dt.size);
6380 put_smstate(u64, buf, 0x7e88, dt.address);
6381
6382 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6383 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6384 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6385 put_smstate(u32, buf, 0x7e74, seg.limit);
6386 put_smstate(u64, buf, 0x7e78, seg.base);
6387
6388 kvm_x86_ops->get_gdt(vcpu, &dt);
6389 put_smstate(u32, buf, 0x7e64, dt.size);
6390 put_smstate(u64, buf, 0x7e68, dt.address);
6391
6392 for (i = 0; i < 6; i++)
ee2cd4b7 6393 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6394#else
6395 WARN_ON_ONCE(1);
6396#endif
6397}
6398
ee2cd4b7 6399static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6400{
660a5d51 6401 struct kvm_segment cs, ds;
18c3626e 6402 struct desc_ptr dt;
660a5d51
PB		 6403 char buf[512];
6404 u32 cr0;
6405
660a5d51
PB		 6406 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6407 vcpu->arch.hflags |= HF_SMM_MASK;
6408 memset(buf, 0, 512);
6409 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6410 enter_smm_save_state_64(vcpu, buf);
660a5d51 6411 else
ee2cd4b7 6412 enter_smm_save_state_32(vcpu, buf);
660a5d51 6413
54bf36aa 6414 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6415
6416 if (kvm_x86_ops->get_nmi_mask(vcpu))
6417 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6418 else
6419 kvm_x86_ops->set_nmi_mask(vcpu, true);
6420
6421 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6422 kvm_rip_write(vcpu, 0x8000);
6423
6424 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6425 kvm_x86_ops->set_cr0(vcpu, cr0);
6426 vcpu->arch.cr0 = cr0;
6427
6428 kvm_x86_ops->set_cr4(vcpu, 0);
6429
18c3626e
PB		 6430 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6431 dt.address = dt.size = 0;
6432 kvm_x86_ops->set_idt(vcpu, &dt);
6433
660a5d51
PB		 6434 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6435
6436 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6437 cs.base = vcpu->arch.smbase;
6438
6439 ds.selector = 0;
6440 ds.base = 0;
6441
6442 cs.limit = ds.limit = 0xffffffff;
6443 cs.type = ds.type = 0x3;
6444 cs.dpl = ds.dpl = 0;
6445 cs.db = ds.db = 0;
6446 cs.s = ds.s = 1;
6447 cs.l = ds.l = 0;
6448 cs.g = ds.g = 1;
6449 cs.avl = ds.avl = 0;
6450 cs.present = ds.present = 1;
6451 cs.unusable = ds.unusable = 0;
6452 cs.padding = ds.padding = 0;
6453
6454 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6455 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6456 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6457 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6458 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6459 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6460
6461 if (guest_cpuid_has_longmode(vcpu))
6462 kvm_x86_ops->set_efer(vcpu, 0);
6463
6464 kvm_update_cpuid(vcpu);
6465 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6466}
6467
ee2cd4b7 6468static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6469{
6470 vcpu->arch.smi_pending = true;
6471 kvm_make_request(KVM_REQ_EVENT, vcpu);
6472}
6473
2860c4b1
PB		 6474void kvm_make_scan_ioapic_request(struct kvm *kvm)
6475{
6476 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6477}
6478
3d81bc7e 6479static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6480{
5c919412
AS		 6481 u64 eoi_exit_bitmap[4];
6482
3d81bc7e
YZ		 6483 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6484 return;
c7c9c56c 6485
6308630b 6486 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6487
b053b2ae 6488 if (irqchip_split(vcpu->kvm))
6308630b 6489 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6490 else {
d62caabb
AS		 6491 if (vcpu->arch.apicv_active)
6492 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6493 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6494 }
5c919412
AS		 6495 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6496 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6497 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6498}
6499
a70656b6
RK		 6500static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6501{
6502 ++vcpu->stat.tlb_flush;
6503 kvm_x86_ops->tlb_flush(vcpu);
6504}
6505
4256f43f
TC		 6506void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6507{
c24ae0dc
TC		 6508 struct page *page = NULL;
6509
35754c98 6510 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6511 return;
6512
4256f43f
TC		 6513 if (!kvm_x86_ops->set_apic_access_page_addr)
6514 return;
6515
c24ae0dc 6516 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6517 if (is_error_page(page))
6518 return;
c24ae0dc
TC		 6519 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6520
6521 /*
6522 * Do not pin apic access page in memory, the MMU notifier
6523 * will call us again if it is migrated or swapped out.
6524 */
6525 put_page(page);
4256f43f
TC		 6526}
6527EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6528
fe71557a
TC		 6529void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6530 unsigned long address)
6531{
c24ae0dc
TC		 6532 /*
6533 * The physical address of apic access page is stored in the VMCS.
6534 * Update it when it becomes invalid.
6535 */
6536 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6537 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6538}
6539
9357d939 6540/*
362c698f 6541 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6542 * exiting to the userspace. Otherwise, the value will be returned to the
6543 * userspace.
6544 */
851ba692 6545static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6546{
6547 int r;
62a193ed
MG		 6548 bool req_int_win =
6549 dm_request_for_irq_injection(vcpu) &&
6550 kvm_cpu_accept_dm_intr(vcpu);
6551
730dca42 6552 bool req_immediate_exit = false;
b6c7a5dc 6553
3e007509 6554 if (vcpu->requests) {
a8eeb04a 6555 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6556 kvm_mmu_unload(vcpu);
a8eeb04a 6557 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6558 __kvm_migrate_timers(vcpu);
d828199e
MT		 6559 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6560 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6561 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6562 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6563 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6564 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6565 if (unlikely(r))
6566 goto out;
6567 }
a8eeb04a 6568 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6569 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6570 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6571 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6572 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6573 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6574 r = 0;
6575 goto out;
6576 }
a8eeb04a 6577 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6578 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6579 r = 0;
6580 goto out;
6581 }
a8eeb04a 6582 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6583 vcpu->fpu_active = 0;
6584 kvm_x86_ops->fpu_deactivate(vcpu);
6585 }
af585b92
GN		 6586 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6587 /* Page is swapped out. Do synthetic halt */
6588 vcpu->arch.apf.halted = true;
6589 r = 1;
6590 goto out;
6591 }
c9aaa895
GC		 6592 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6593 record_steal_time(vcpu);
64d60670
PB		 6594 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6595 process_smi(vcpu);
7460fb4a
AK		 6596 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6597 process_nmi(vcpu);
f5132b01 6598 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6599 kvm_pmu_handle_event(vcpu);
f5132b01 6600 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6601 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6602 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6603 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6604 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6605 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6606 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6607 vcpu->run->eoi.vector =
6608 vcpu->arch.pending_ioapic_eoi;
6609 r = 0;
6610 goto out;
6611 }
6612 }
3d81bc7e
YZ		 6613 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6614 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6615 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6616 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6617 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6618 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6619 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6620 r = 0;
6621 goto out;
6622 }
e516cebb
AS		 6623 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6624 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6625 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6626 r = 0;
6627 goto out;
6628 }
db397571
AS		 6629 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6630 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6631 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6632 r = 0;
6633 goto out;
6634 }
f3b138c5
AS		 6635
6636 /*
6637 * KVM_REQ_HV_STIMER has to be processed after
6638 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6639 * depend on the guest clock being up-to-date
6640 */
1f4b34f8
AS		 6641 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6642 kvm_hv_process_stimers(vcpu);
2f52d58c 6643 }
b93463aa 6644
bf9f6ac8
FW		 6645 /*
6646 * KVM_REQ_EVENT is not set when posted interrupts are set by
6647 * VT-d hardware, so we have to update RVI unconditionally.
6648 */
6649 if (kvm_lapic_enabled(vcpu)) {
6650 /*
6651 * Update architecture specific hints for APIC
6652 * virtual interrupt delivery.
6653 */
d62caabb 6654 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6655 kvm_x86_ops->hwapic_irr_update(vcpu,
6656 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6657 }
b93463aa 6658
b463a6f7 6659 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6660 kvm_apic_accept_events(vcpu);
6661 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6662 r = 1;
6663 goto out;
6664 }
6665
b6b8a145
JK		 6666 if (inject_pending_event(vcpu, req_int_win) != 0)
6667 req_immediate_exit = true;
321c5658 6668 else {
c43203ca
PB		 6669 /* Enable NMI/IRQ window open exits if needed.
6670 *
6671 * SMIs have two cases: 1) they can be nested, and
6672 * then there is nothing to do here because RSM will
6673 * cause a vmexit anyway; 2) or the SMI can be pending
6674 * because inject_pending_event has completed the
6675 * injection of an IRQ or NMI from the previous vmexit,
6676 * and then we request an immediate exit to inject the SMI.
6677 */
6678 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6679 req_immediate_exit = true;
321c5658
YS		 6680 if (vcpu->arch.nmi_pending)
6681 kvm_x86_ops->enable_nmi_window(vcpu);
6682 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6683 kvm_x86_ops->enable_irq_window(vcpu);
6684 }
b463a6f7
AK		 6685
6686 if (kvm_lapic_enabled(vcpu)) {
6687 update_cr8_intercept(vcpu);
6688 kvm_lapic_sync_to_vapic(vcpu);
6689 }
6690 }
6691
d8368af8
AK		 6692 r = kvm_mmu_reload(vcpu);
6693 if (unlikely(r)) {
d905c069 6694 goto cancel_injection;
d8368af8
AK		 6695 }
6696
b6c7a5dc
HB		 6697 preempt_disable();
6698
6699 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6700 if (vcpu->fpu_active)
6701 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6702 vcpu->mode = IN_GUEST_MODE;
6703
01b71917
MT		 6704 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6705
0f127d12
LT		 6706 /*
6707 * We should set ->mode before check ->requests,
6708 * Please see the comment in kvm_make_all_cpus_request.
6709 * This also orders the write to mode from any reads
6710 * to the page tables done while the VCPU is running.
6711 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6712 */
01b71917 6713 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6714
d94e1dc9 6715 local_irq_disable();
32f88400 6716
6b7e2d09 6717 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6718 || need_resched() || signal_pending(current)) {
6b7e2d09 6719 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6720 smp_wmb();
6c142801
AK		 6721 local_irq_enable();
6722 preempt_enable();
01b71917 6723 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6724 r = 1;
d905c069 6725 goto cancel_injection;
6c142801
AK		 6726 }
6727
fc5b7f3b
DM		 6728 kvm_load_guest_xcr0(vcpu);
6729
c43203ca
PB		 6730 if (req_immediate_exit) {
6731 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6732 smp_send_reschedule(vcpu->cpu);
c43203ca 6733 }
d6185f20 6734
8b89fe1f
PB		 6735 trace_kvm_entry(vcpu->vcpu_id);
6736 wait_lapic_expire(vcpu);
6edaa530 6737 guest_enter_irqoff();
b6c7a5dc 6738
42dbaa5a 6739 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6740 set_debugreg(0, 7);
6741 set_debugreg(vcpu->arch.eff_db[0], 0);
6742 set_debugreg(vcpu->arch.eff_db[1], 1);
6743 set_debugreg(vcpu->arch.eff_db[2], 2);
6744 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6745 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6746 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6747 }
b6c7a5dc 6748
851ba692 6749 kvm_x86_ops->run(vcpu);
b6c7a5dc 6750
c77fb5fe
PB		 6751 /*
6752 * Do this here before restoring debug registers on the host. And
6753 * since we do this before handling the vmexit, a DR access vmexit
6754 * can (a) read the correct value of the debug registers, (b) set
6755 * KVM_DEBUGREG_WONT_EXIT again.
6756 */
6757 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6758 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6759 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6760 kvm_update_dr0123(vcpu);
6761 kvm_update_dr6(vcpu);
6762 kvm_update_dr7(vcpu);
6763 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6764 }
6765
24f1e32c
FW		 6766 /*
6767 * If the guest has used debug registers, at least dr7
6768 * will be disabled while returning to the host.
6769 * If we don't have active breakpoints in the host, we don't
6770 * care about the messed up debug address registers. But if
6771 * we have some of them active, restore the old state.
6772 */
59d8eb53 6773 if (hw_breakpoint_active())
24f1e32c 6774 hw_breakpoint_restore();
42dbaa5a 6775
4ba76538 6776 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6777
6b7e2d09 6778 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6779 smp_wmb();
a547c6db 6780
fc5b7f3b
DM		 6781 kvm_put_guest_xcr0(vcpu);
6782
a547c6db 6783 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6784
6785 ++vcpu->stat.exits;
6786
f2485b3e 6787 guest_exit_irqoff();
b6c7a5dc 6788
f2485b3e 6789 local_irq_enable();
b6c7a5dc
HB		 6790 preempt_enable();
6791
f656ce01 6792 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6793
b6c7a5dc
HB		 6794 /*
6795 * Profile KVM exit RIPs:
6796 */
6797 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6798 unsigned long rip = kvm_rip_read(vcpu);
6799 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6800 }
6801
cc578287
ZA		 6802 if (unlikely(vcpu->arch.tsc_always_catchup))
6803 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6804
5cfb1d5a
MT		 6805 if (vcpu->arch.apic_attention)
6806 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6807
851ba692 6808 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6809 return r;
6810
6811cancel_injection:
6812 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6813 if (unlikely(vcpu->arch.apic_attention))
6814 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6815out:
6816 return r;
6817}
b6c7a5dc 6818
362c698f
PB		 6819static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6820{
bf9f6ac8
FW		 6821 if (!kvm_arch_vcpu_runnable(vcpu) &&
6822 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6823 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6824 kvm_vcpu_block(vcpu);
6825 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6826
6827 if (kvm_x86_ops->post_block)
6828 kvm_x86_ops->post_block(vcpu);
6829
9c8fd1ba
PB		 6830 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6831 return 1;
6832 }
362c698f
PB		 6833
6834 kvm_apic_accept_events(vcpu);
6835 switch(vcpu->arch.mp_state) {
6836 case KVM_MP_STATE_HALTED:
6837 vcpu->arch.pv.pv_unhalted = false;
6838 vcpu->arch.mp_state =
6839 KVM_MP_STATE_RUNNABLE;
6840 case KVM_MP_STATE_RUNNABLE:
6841 vcpu->arch.apf.halted = false;
6842 break;
6843 case KVM_MP_STATE_INIT_RECEIVED:
6844 break;
6845 default:
6846 return -EINTR;
6847 break;
6848 }
6849 return 1;
6850}
09cec754 6851
5d9bc648
PB		 6852static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6853{
6854 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6855 !vcpu->arch.apf.halted);
6856}
6857
362c698f 6858static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6859{
6860 int r;
f656ce01 6861 struct kvm *kvm = vcpu->kvm;
d7690175 6862
f656ce01 6863 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6864
362c698f 6865 for (;;) {
58f800d5 6866 if (kvm_vcpu_running(vcpu)) {
851ba692 6867 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6868 } else {
362c698f 6869 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6870 }
6871
09cec754
GN		 6872 if (r <= 0)
6873 break;
6874
6875 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6876 if (kvm_cpu_has_pending_timer(vcpu))
6877 kvm_inject_pending_timer_irqs(vcpu);
6878
782d422b
MG		 6879 if (dm_request_for_irq_injection(vcpu) &&
6880 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6881 r = 0;
6882 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6883 ++vcpu->stat.request_irq_exits;
362c698f 6884 break;
09cec754 6885 }
af585b92
GN		 6886
6887 kvm_check_async_pf_completion(vcpu);
6888
09cec754
GN		 6889 if (signal_pending(current)) {
6890 r = -EINTR;
851ba692 6891 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6892 ++vcpu->stat.signal_exits;
362c698f 6893 break;
09cec754
GN		 6894 }
6895 if (need_resched()) {
f656ce01 6896 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6897 cond_resched();
f656ce01 6898 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6899 }
b6c7a5dc
HB		 6900 }
6901
f656ce01 6902 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6903
6904 return r;
6905}
6906
716d51ab
GN		 6907static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6908{
6909 int r;
6910 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6911 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6912 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6913 if (r != EMULATE_DONE)
6914 return 0;
6915 return 1;
6916}
6917
6918static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6919{
6920 BUG_ON(!vcpu->arch.pio.count);
6921
6922 return complete_emulated_io(vcpu);
6923}
6924
f78146b0
AK		 6925/*
6926 * Implements the following, as a state machine:
6927 *
6928 * read:
6929 * for each fragment
87da7e66
XG		 6930 * for each mmio piece in the fragment
6931 * write gpa, len
6932 * exit
6933 * copy data
f78146b0
AK		 6934 * execute insn
6935 *
6936 * write:
6937 * for each fragment
87da7e66
XG		 6938 * for each mmio piece in the fragment
6939 * write gpa, len
6940 * copy data
6941 * exit
f78146b0 6942 */
716d51ab 6943static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6944{
6945 struct kvm_run *run = vcpu->run;
f78146b0 6946 struct kvm_mmio_fragment *frag;
87da7e66 6947 unsigned len;
5287f194 6948
716d51ab 6949 BUG_ON(!vcpu->mmio_needed);
5287f194 6950
716d51ab 6951 /* Complete previous fragment */
87da7e66
XG		 6952 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6953 len = min(8u, frag->len);
716d51ab 6954 if (!vcpu->mmio_is_write)
87da7e66
XG		 6955 memcpy(frag->data, run->mmio.data, len);
6956
6957 if (frag->len <= 8) {
6958 /* Switch to the next fragment. */
6959 frag++;
6960 vcpu->mmio_cur_fragment++;
6961 } else {
6962 /* Go forward to the next mmio piece. */
6963 frag->data += len;
6964 frag->gpa += len;
6965 frag->len -= len;
6966 }
6967
a08d3b3b 6968 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6969 vcpu->mmio_needed = 0;
0912c977
PB		 6970
6971 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6972 if (vcpu->mmio_is_write)
716d51ab
GN		 6973 return 1;
6974 vcpu->mmio_read_completed = 1;
6975 return complete_emulated_io(vcpu);
6976 }
87da7e66 6977
716d51ab
GN		 6978 run->exit_reason = KVM_EXIT_MMIO;
6979 run->mmio.phys_addr = frag->gpa;
6980 if (vcpu->mmio_is_write)
87da7e66
XG		 6981 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6982 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6983 run->mmio.is_write = vcpu->mmio_is_write;
6984 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6985 return 0;
5287f194
AK		 6986}
6987
716d51ab 6988
b6c7a5dc
HB		 6989int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6990{
c5bedc68 6991 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6992 int r;
6993 sigset_t sigsaved;
6994
c4d72e2d 6995 fpu__activate_curr(fpu);
e5c30142 6996
ac9f6dc0
AK		 6997 if (vcpu->sigset_active)
6998 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6999
a4535290 7000 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7001 kvm_vcpu_block(vcpu);
66450a21 7002 kvm_apic_accept_events(vcpu);
d7690175 7003 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 7004 r = -EAGAIN;
7005 goto out;
b6c7a5dc
HB		 7006 }
7007
b6c7a5dc 7008 /* re-sync apic's tpr */
35754c98 7009 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7010 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7011 r = -EINVAL;
7012 goto out;
7013 }
7014 }
b6c7a5dc 7015
716d51ab
GN		 7016 if (unlikely(vcpu->arch.complete_userspace_io)) {
7017 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7018 vcpu->arch.complete_userspace_io = NULL;
7019 r = cui(vcpu);
7020 if (r <= 0)
7021 goto out;
7022 } else
7023 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7024
362c698f 7025 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7026
7027out:
f1d86e46 7028 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7029 if (vcpu->sigset_active)
7030 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7031
b6c7a5dc
HB		 7032 return r;
7033}
7034
7035int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7036{
7ae441ea
GN		 7037 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7038 /*
7039 * We are here if userspace calls get_regs() in the middle of
7040 * instruction emulation. Registers state needs to be copied
4a969980 7041 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7042 * that usually, but some bad designed PV devices (vmware
7043 * backdoor interface) need this to work
7044 */
dd856efa 7045 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7046 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7047 }
5fdbf976
MT		 7048 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7049 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7050 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7051 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7052 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7053 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7054 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7055 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7056#ifdef CONFIG_X86_64
5fdbf976
MT		 7057 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7058 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7059 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7060 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7061 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7062 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7063 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7064 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7065#endif
7066
5fdbf976 7067 regs->rip = kvm_rip_read(vcpu);
91586a3b 7068 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7069
b6c7a5dc
HB		 7070 return 0;
7071}
7072
7073int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7074{
7ae441ea
GN		 7075 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7076 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7077
5fdbf976
MT		 7078 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7079 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7080 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7081 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7082 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7083 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7084 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7085 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7086#ifdef CONFIG_X86_64
5fdbf976
MT		 7087 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7088 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7089 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7090 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7091 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7092 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7093 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7094 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7095#endif
7096
5fdbf976 7097 kvm_rip_write(vcpu, regs->rip);
91586a3b 7098 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7099
b4f14abd
JK		 7100 vcpu->arch.exception.pending = false;
7101
3842d135
AK		 7102 kvm_make_request(KVM_REQ_EVENT, vcpu);
7103
b6c7a5dc
HB		 7104 return 0;
7105}
7106
b6c7a5dc
HB		 7107void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7108{
7109 struct kvm_segment cs;
7110
3e6e0aab 7111 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7112 *db = cs.db;
7113 *l = cs.l;
7114}
7115EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7116
7117int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7118 struct kvm_sregs *sregs)
7119{
89a27f4d 7120 struct desc_ptr dt;
b6c7a5dc 7121
3e6e0aab
GT		 7122 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7123 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7124 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7125 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7126 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7127 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7128
3e6e0aab
GT		 7129 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7130 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7131
7132 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7133 sregs->idt.limit = dt.size;
7134 sregs->idt.base = dt.address;
b6c7a5dc 7135 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7136 sregs->gdt.limit = dt.size;
7137 sregs->gdt.base = dt.address;
b6c7a5dc 7138
4d4ec087 7139 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7140 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7141 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7142 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7143 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7144 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7145 sregs->apic_base = kvm_get_apic_base(vcpu);
7146
923c61bb 7147 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7148
36752c9b 7149 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7150 set_bit(vcpu->arch.interrupt.nr,
7151 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7152
b6c7a5dc
HB		 7153 return 0;
7154}
7155
62d9f0db
MT		 7156int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7157 struct kvm_mp_state *mp_state)
7158{
66450a21 7159 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7160 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7161 vcpu->arch.pv.pv_unhalted)
7162 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7163 else
7164 mp_state->mp_state = vcpu->arch.mp_state;
7165
62d9f0db
MT		 7166 return 0;
7167}
7168
7169int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7170 struct kvm_mp_state *mp_state)
7171{
bce87cce 7172 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7173 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7174 return -EINVAL;
7175
7176 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7177 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7178 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7179 } else
7180 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7181 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7182 return 0;
7183}
7184
7f3d35fd
KW		 7185int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7186 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7187{
9d74191a 7188 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7189 int ret;
e01c2426 7190
8ec4722d 7191 init_emulate_ctxt(vcpu);
c697518a 7192
7f3d35fd 7193 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7194 has_error_code, error_code);
c697518a 7195
c697518a 7196 if (ret)
19d04437 7197 return EMULATE_FAIL;
37817f29 7198
9d74191a
TY		 7199 kvm_rip_write(vcpu, ctxt->eip);
7200 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7201 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7202 return EMULATE_DONE;
37817f29
IE		 7203}
7204EXPORT_SYMBOL_GPL(kvm_task_switch);
7205
b6c7a5dc
HB		 7206int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7207 struct kvm_sregs *sregs)
7208{
58cb628d 7209 struct msr_data apic_base_msr;
b6c7a5dc 7210 int mmu_reset_needed = 0;
63f42e02 7211 int pending_vec, max_bits, idx;
89a27f4d 7212 struct desc_ptr dt;
b6c7a5dc 7213
6d1068b3
PM		 7214 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7215 return -EINVAL;
7216
89a27f4d
GN		 7217 dt.size = sregs->idt.limit;
7218 dt.address = sregs->idt.base;
b6c7a5dc 7219 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7220 dt.size = sregs->gdt.limit;
7221 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7222 kvm_x86_ops->set_gdt(vcpu, &dt);
7223
ad312c7c 7224 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7225 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7226 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7227 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7228
2d3ad1f4 7229 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7230
f6801dff 7231 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7232 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7233 apic_base_msr.data = sregs->apic_base;
7234 apic_base_msr.host_initiated = true;
7235 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7236
4d4ec087 7237 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7238 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7239 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7240
fc78f519 7241 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7242 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7243 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7244 kvm_update_cpuid(vcpu);
63f42e02
XG		 7245
7246 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7247 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7248 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7249 mmu_reset_needed = 1;
7250 }
63f42e02 7251 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7252
7253 if (mmu_reset_needed)
7254 kvm_mmu_reset_context(vcpu);
7255
a50abc3b 7256 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7257 pending_vec = find_first_bit(
7258 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7259 if (pending_vec < max_bits) {
66fd3f7f 7260 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7261 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7262 }
7263
3e6e0aab
GT		 7264 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7265 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7266 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7267 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7268 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7269 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7270
3e6e0aab
GT		 7271 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7272 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7273
5f0269f5
ME		 7274 update_cr8_intercept(vcpu);
7275
9c3e4aab 7276 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7277 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7278 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7279 !is_protmode(vcpu))
9c3e4aab
MT		 7280 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7281
3842d135
AK		 7282 kvm_make_request(KVM_REQ_EVENT, vcpu);
7283
b6c7a5dc
HB		 7284 return 0;
7285}
7286
d0bfb940
JK		 7287int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7288 struct kvm_guest_debug *dbg)
b6c7a5dc 7289{
355be0b9 7290 unsigned long rflags;
ae675ef0 7291 int i, r;
b6c7a5dc 7292
4f926bf2
JK		 7293 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7294 r = -EBUSY;
7295 if (vcpu->arch.exception.pending)
2122ff5e 7296 goto out;
4f926bf2
JK		 7297 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7298 kvm_queue_exception(vcpu, DB_VECTOR);
7299 else
7300 kvm_queue_exception(vcpu, BP_VECTOR);
7301 }
7302
91586a3b
JK		 7303 /*
7304 * Read rflags as long as potentially injected trace flags are still
7305 * filtered out.
7306 */
7307 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7308
7309 vcpu->guest_debug = dbg->control;
7310 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7311 vcpu->guest_debug = 0;
7312
7313 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7314 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7315 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7316 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7317 } else {
7318 for (i = 0; i < KVM_NR_DB_REGS; i++)
7319 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7320 }
c8639010 7321 kvm_update_dr7(vcpu);
ae675ef0 7322
f92653ee
JK		 7323 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7324 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7325 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7326
91586a3b
JK		 7327 /*
7328 * Trigger an rflags update that will inject or remove the trace
7329 * flags.
7330 */
7331 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7332
a96036b8 7333 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7334
4f926bf2 7335 r = 0;
d0bfb940 7336
2122ff5e 7337out:
b6c7a5dc
HB		 7338
7339 return r;
7340}
7341
8b006791
ZX		 7342/*
7343 * Translate a guest virtual address to a guest physical address.
7344 */
7345int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7346 struct kvm_translation *tr)
7347{
7348 unsigned long vaddr = tr->linear_address;
7349 gpa_t gpa;
f656ce01 7350 int idx;
8b006791 7351
f656ce01 7352 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7353 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7354 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7355 tr->physical_address = gpa;
7356 tr->valid = gpa != UNMAPPED_GVA;
7357 tr->writeable = 1;
7358 tr->usermode = 0;
8b006791
ZX		 7359
7360 return 0;
7361}
7362
d0752060
HB		 7363int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7364{
c47ada30 7365 struct fxregs_state *fxsave =
7366ed77 7366 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7367
d0752060
HB		 7368 memcpy(fpu->fpr, fxsave->st_space, 128);
7369 fpu->fcw = fxsave->cwd;
7370 fpu->fsw = fxsave->swd;
7371 fpu->ftwx = fxsave->twd;
7372 fpu->last_opcode = fxsave->fop;
7373 fpu->last_ip = fxsave->rip;
7374 fpu->last_dp = fxsave->rdp;
7375 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7376
d0752060
HB		 7377 return 0;
7378}
7379
7380int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7381{
c47ada30 7382 struct fxregs_state *fxsave =
7366ed77 7383 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7384
d0752060
HB		 7385 memcpy(fxsave->st_space, fpu->fpr, 128);
7386 fxsave->cwd = fpu->fcw;
7387 fxsave->swd = fpu->fsw;
7388 fxsave->twd = fpu->ftwx;
7389 fxsave->fop = fpu->last_opcode;
7390 fxsave->rip = fpu->last_ip;
7391 fxsave->rdp = fpu->last_dp;
7392 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7393
d0752060
HB		 7394 return 0;
7395}
7396
0ee6a517 7397static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7398{
bf935b0b 7399 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7400 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7401 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7402 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7403
2acf923e
DC		 7404 /*
7405 * Ensure guest xcr0 is valid for loading
7406 */
d91cab78 7407 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7408
ad312c7c 7409 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7410}
d0752060
HB		 7411
7412void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7413{
2608d7a1 7414 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7415 return;
7416
2acf923e
DC		 7417 /*
7418 * Restore all possible states in the guest,
7419 * and assume host would use all available bits.
7420 * Guest xcr0 would be loaded later.
7421 */
d0752060 7422 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7423 __kernel_fpu_begin();
003e2e8b 7424 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7425 trace_kvm_fpu(1);
d0752060 7426}
d0752060
HB		 7427
7428void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7429{
653f52c3
RR		 7430 if (!vcpu->guest_fpu_loaded) {
7431 vcpu->fpu_counter = 0;
d0752060 7432 return;
653f52c3 7433 }
d0752060
HB		 7434
7435 vcpu->guest_fpu_loaded = 0;
4f836347 7436 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7437 __kernel_fpu_end();
f096ed85 7438 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7439 /*
7440 * If using eager FPU mode, or if the guest is a frequent user
7441 * of the FPU, just leave the FPU active for next time.
7442 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7443 * the FPU in bursts will revert to loading it on demand.
7444 */
5a5fbdc0 7445 if (!use_eager_fpu()) {
653f52c3
RR		 7446 if (++vcpu->fpu_counter < 5)
7447 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7448 }
0c04851c 7449 trace_kvm_fpu(0);
d0752060 7450}
e9b11c17
ZX		 7451
7452void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7453{
bd768e14
IY		 7454 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7455
12f9a48f 7456 kvmclock_reset(vcpu);
7f1ea208 7457
e9b11c17 7458 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7459 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7460}
7461
7462struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7463 unsigned int id)
7464{
c447e76b
LL		 7465 struct kvm_vcpu *vcpu;
7466
6755bae8
ZA		 7467 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7468 printk_once(KERN_WARNING
7469 "kvm: SMP vm created on host with unstable TSC; "
7470 "guest TSC will not be reliable\n");
c447e76b
LL		 7471
7472 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7473
c447e76b 7474 return vcpu;
26e5215f 7475}
e9b11c17 7476
26e5215f
AK		 7477int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7478{
7479 int r;
e9b11c17 7480
19efffa2 7481 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7482 r = vcpu_load(vcpu);
7483 if (r)
7484 return r;
d28bc9dd 7485 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7486 kvm_mmu_setup(vcpu);
e9b11c17 7487 vcpu_put(vcpu);
26e5215f 7488 return r;
e9b11c17
ZX		 7489}
7490
31928aa5 7491void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7492{
8fe8ab46 7493 struct msr_data msr;
332967a3 7494 struct kvm *kvm = vcpu->kvm;
42897d86 7495
31928aa5
DD		 7496 if (vcpu_load(vcpu))
7497 return;
8fe8ab46
WA		 7498 msr.data = 0x0;
7499 msr.index = MSR_IA32_TSC;
7500 msr.host_initiated = true;
7501 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7502 vcpu_put(vcpu);
7503
630994b3
MT		 7504 if (!kvmclock_periodic_sync)
7505 return;
7506
332967a3
AJ		 7507 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7508 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7509}
7510
d40ccc62 7511void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7512{
9fc77441 7513 int r;
344d9588
GN		 7514 vcpu->arch.apf.msr_val = 0;
7515
9fc77441
MT		 7516 r = vcpu_load(vcpu);
7517 BUG_ON(r);
e9b11c17
ZX		 7518 kvm_mmu_unload(vcpu);
7519 vcpu_put(vcpu);
7520
7521 kvm_x86_ops->vcpu_free(vcpu);
7522}
7523
d28bc9dd 7524void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7525{
e69fab5d
PB		 7526 vcpu->arch.hflags = 0;
7527
c43203ca 7528 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7529 atomic_set(&vcpu->arch.nmi_queued, 0);
7530 vcpu->arch.nmi_pending = 0;
448fa4a9 7531 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7532 kvm_clear_interrupt_queue(vcpu);
7533 kvm_clear_exception_queue(vcpu);
448fa4a9 7534
42dbaa5a 7535 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7536 kvm_update_dr0123(vcpu);
6f43ed01 7537 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7538 kvm_update_dr6(vcpu);
42dbaa5a 7539 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7540 kvm_update_dr7(vcpu);
42dbaa5a 7541
1119022c
NA		 7542 vcpu->arch.cr2 = 0;
7543
3842d135 7544 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7545 vcpu->arch.apf.msr_val = 0;
c9aaa895 7546 vcpu->arch.st.msr_val = 0;
3842d135 7547
12f9a48f
GC		 7548 kvmclock_reset(vcpu);
7549
af585b92
GN		 7550 kvm_clear_async_pf_completion_queue(vcpu);
7551 kvm_async_pf_hash_reset(vcpu);
7552 vcpu->arch.apf.halted = false;
3842d135 7553
64d60670 7554 if (!init_event) {
d28bc9dd 7555 kvm_pmu_reset(vcpu);
64d60670
PB		 7556 vcpu->arch.smbase = 0x30000;
7557 }
f5132b01 7558
66f7b72e
JS		 7559 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7560 vcpu->arch.regs_avail = ~0;
7561 vcpu->arch.regs_dirty = ~0;
7562
d28bc9dd 7563 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7564}
7565
2b4a273b 7566void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7567{
7568 struct kvm_segment cs;
7569
7570 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7571 cs.selector = vector << 8;
7572 cs.base = vector << 12;
7573 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7574 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7575}
7576
13a34e06 7577int kvm_arch_hardware_enable(void)
e9b11c17 7578{
ca84d1a2
ZA		 7579 struct kvm *kvm;
7580 struct kvm_vcpu *vcpu;
7581 int i;
0dd6a6ed
ZA		 7582 int ret;
7583 u64 local_tsc;
7584 u64 max_tsc = 0;
7585 bool stable, backwards_tsc = false;
18863bdd
AK		 7586
7587 kvm_shared_msr_cpu_online();
13a34e06 7588 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7589 if (ret != 0)
7590 return ret;
7591
4ea1636b 7592 local_tsc = rdtsc();
0dd6a6ed
ZA		 7593 stable = !check_tsc_unstable();
7594 list_for_each_entry(kvm, &vm_list, vm_list) {
7595 kvm_for_each_vcpu(i, vcpu, kvm) {
7596 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7597 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7598 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7599 backwards_tsc = true;
7600 if (vcpu->arch.last_host_tsc > max_tsc)
7601 max_tsc = vcpu->arch.last_host_tsc;
7602 }
7603 }
7604 }
7605
7606 /*
7607 * Sometimes, even reliable TSCs go backwards. This happens on
7608 * platforms that reset TSC during suspend or hibernate actions, but
7609 * maintain synchronization. We must compensate. Fortunately, we can
7610 * detect that condition here, which happens early in CPU bringup,
7611 * before any KVM threads can be running. Unfortunately, we can't
7612 * bring the TSCs fully up to date with real time, as we aren't yet far
7613 * enough into CPU bringup that we know how much real time has actually
108b249c 7614 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7615 * variables that haven't been updated yet.
7616 *
7617 * So we simply find the maximum observed TSC above, then record the
7618 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7619 * the adjustment will be applied. Note that we accumulate
7620 * adjustments, in case multiple suspend cycles happen before some VCPU
7621 * gets a chance to run again. In the event that no KVM threads get a
7622 * chance to run, we will miss the entire elapsed period, as we'll have
7623 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7624 * loose cycle time. This isn't too big a deal, since the loss will be
7625 * uniform across all VCPUs (not to mention the scenario is extremely
7626 * unlikely). It is possible that a second hibernate recovery happens
7627 * much faster than a first, causing the observed TSC here to be
7628 * smaller; this would require additional padding adjustment, which is
7629 * why we set last_host_tsc to the local tsc observed here.
7630 *
7631 * N.B. - this code below runs only on platforms with reliable TSC,
7632 * as that is the only way backwards_tsc is set above. Also note
7633 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7634 * have the same delta_cyc adjustment applied if backwards_tsc
7635 * is detected. Note further, this adjustment is only done once,
7636 * as we reset last_host_tsc on all VCPUs to stop this from being
7637 * called multiple times (one for each physical CPU bringup).
7638 *
4a969980 7639 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7640 * will be compensated by the logic in vcpu_load, which sets the TSC to
7641 * catchup mode. This will catchup all VCPUs to real time, but cannot
7642 * guarantee that they stay in perfect synchronization.
7643 */
7644 if (backwards_tsc) {
7645 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7646 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7647 list_for_each_entry(kvm, &vm_list, vm_list) {
7648 kvm_for_each_vcpu(i, vcpu, kvm) {
7649 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7650 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7651 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7652 }
7653
7654 /*
7655 * We have to disable TSC offset matching.. if you were
7656 * booting a VM while issuing an S4 host suspend....
7657 * you may have some problem. Solving this issue is
7658 * left as an exercise to the reader.
7659 */
7660 kvm->arch.last_tsc_nsec = 0;
7661 kvm->arch.last_tsc_write = 0;
7662 }
7663
7664 }
7665 return 0;
e9b11c17
ZX		 7666}
7667
13a34e06 7668void kvm_arch_hardware_disable(void)
e9b11c17 7669{
13a34e06
RK		 7670 kvm_x86_ops->hardware_disable();
7671 drop_user_return_notifiers();
e9b11c17
ZX		 7672}
7673
7674int kvm_arch_hardware_setup(void)
7675{
9e9c3fe4
NA		 7676 int r;
7677
7678 r = kvm_x86_ops->hardware_setup();
7679 if (r != 0)
7680 return r;
7681
35181e86
HZ		 7682 if (kvm_has_tsc_control) {
7683 /*
7684 * Make sure the user can only configure tsc_khz values that
7685 * fit into a signed integer.
7686 * A min value is not calculated needed because it will always
7687 * be 1 on all machines.
7688 */
7689 u64 max = min(0x7fffffffULL,
7690 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7691 kvm_max_guest_tsc_khz = max;
7692
ad721883 7693 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7694 }
ad721883 7695
9e9c3fe4
NA		 7696 kvm_init_msr_list();
7697 return 0;
e9b11c17
ZX		 7698}
7699
7700void kvm_arch_hardware_unsetup(void)
7701{
7702 kvm_x86_ops->hardware_unsetup();
7703}
7704
7705void kvm_arch_check_processor_compat(void *rtn)
7706{
7707 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7708}
7709
7710bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7711{
7712 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7713}
7714EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7715
7716bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7717{
7718 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7719}
7720
54e9818f 7721struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7722EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7723
e9b11c17
ZX		 7724int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7725{
7726 struct page *page;
7727 struct kvm *kvm;
7728 int r;
7729
7730 BUG_ON(vcpu->kvm == NULL);
7731 kvm = vcpu->kvm;
7732
d62caabb 7733 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7734 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7735 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7736 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7737 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7738 else
a4535290 7739 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7740
7741 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7742 if (!page) {
7743 r = -ENOMEM;
7744 goto fail;
7745 }
ad312c7c 7746 vcpu->arch.pio_data = page_address(page);
e9b11c17 7747
cc578287 7748 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7749
e9b11c17
ZX		 7750 r = kvm_mmu_create(vcpu);
7751 if (r < 0)
7752 goto fail_free_pio_data;
7753
7754 if (irqchip_in_kernel(kvm)) {
7755 r = kvm_create_lapic(vcpu);
7756 if (r < 0)
7757 goto fail_mmu_destroy;
54e9818f
GN		 7758 } else
7759 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7760
890ca9ae
HY		 7761 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7762 GFP_KERNEL);
7763 if (!vcpu->arch.mce_banks) {
7764 r = -ENOMEM;
443c39bc 7765 goto fail_free_lapic;
890ca9ae
HY		 7766 }
7767 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7768
f1797359
WY		 7769 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7770 r = -ENOMEM;
f5f48ee1 7771 goto fail_free_mce_banks;
f1797359 7772 }
f5f48ee1 7773
0ee6a517 7774 fx_init(vcpu);
66f7b72e 7775
ba904635 7776 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7777 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7778
7779 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7780 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7781
5a4f55cd
EK		 7782 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7783
74545705
RK		 7784 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7785
af585b92 7786 kvm_async_pf_hash_reset(vcpu);
f5132b01 7787 kvm_pmu_init(vcpu);
af585b92 7788
1c1a9ce9
SR		 7789 vcpu->arch.pending_external_vector = -1;
7790
5c919412
AS		 7791 kvm_hv_vcpu_init(vcpu);
7792
e9b11c17 7793 return 0;
0ee6a517 7794
f5f48ee1
SY		 7795fail_free_mce_banks:
7796 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7797fail_free_lapic:
7798 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7799fail_mmu_destroy:
7800 kvm_mmu_destroy(vcpu);
7801fail_free_pio_data:
ad312c7c 7802 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7803fail:
7804 return r;
7805}
7806
7807void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7808{
f656ce01
MT		 7809 int idx;
7810
1f4b34f8 7811 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7812 kvm_pmu_destroy(vcpu);
36cb93fd 7813 kfree(vcpu->arch.mce_banks);
e9b11c17 7814 kvm_free_lapic(vcpu);
f656ce01 7815 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7816 kvm_mmu_destroy(vcpu);
f656ce01 7817 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7818 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7819 if (!lapic_in_kernel(vcpu))
54e9818f 7820 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7821}
d19a9cd2 7822
e790d9ef
RK		 7823void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7824{
ae97a3b8 7825 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7826}
7827
e08b9637 7828int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7829{
e08b9637
CO		 7830 if (type)
7831 return -EINVAL;
7832
6ef768fa 7833 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7834 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7835 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7836 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7837 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7838
5550af4d
SY		 7839 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7840 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7841 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7842 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7843 &kvm->arch.irq_sources_bitmap);
5550af4d 7844
038f8c11 7845 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7846 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7847 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7848
108b249c 7849 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 7850 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7851
7e44e449 7852 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7853 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7854
0eb05bf2 7855 kvm_page_track_init(kvm);
13d268ca 7856 kvm_mmu_init_vm(kvm);
0eb05bf2 7857
03543133
SS		 7858 if (kvm_x86_ops->vm_init)
7859 return kvm_x86_ops->vm_init(kvm);
7860
d89f5eff 7861 return 0;
d19a9cd2
ZX		 7862}
7863
7864static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7865{
9fc77441
MT		 7866 int r;
7867 r = vcpu_load(vcpu);
7868 BUG_ON(r);
d19a9cd2
ZX		 7869 kvm_mmu_unload(vcpu);
7870 vcpu_put(vcpu);
7871}
7872
7873static void kvm_free_vcpus(struct kvm *kvm)
7874{
7875 unsigned int i;
988a2cae 7876 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7877
7878 /*
7879 * Unpin any mmu pages first.
7880 */
af585b92
GN		 7881 kvm_for_each_vcpu(i, vcpu, kvm) {
7882 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7883 kvm_unload_vcpu_mmu(vcpu);
af585b92 7884 }
988a2cae
GN		 7885 kvm_for_each_vcpu(i, vcpu, kvm)
7886 kvm_arch_vcpu_free(vcpu);
7887
7888 mutex_lock(&kvm->lock);
7889 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7890 kvm->vcpus[i] = NULL;
d19a9cd2 7891
988a2cae
GN		 7892 atomic_set(&kvm->online_vcpus, 0);
7893 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7894}
7895
ad8ba2cd
SY		 7896void kvm_arch_sync_events(struct kvm *kvm)
7897{
332967a3 7898 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7899 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7900 kvm_free_all_assigned_devices(kvm);
aea924f6 7901 kvm_free_pit(kvm);
ad8ba2cd
SY		 7902}
7903
1d8007bd 7904int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7905{
7906 int i, r;
25188b99 7907 unsigned long hva;
f0d648bd
PB		 7908 struct kvm_memslots *slots = kvm_memslots(kvm);
7909 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7910
7911 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7912 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7913 return -EINVAL;
9da0e4d5 7914
f0d648bd
PB		 7915 slot = id_to_memslot(slots, id);
7916 if (size) {
b21629da 7917 if (slot->npages)
f0d648bd
PB		 7918 return -EEXIST;
7919
7920 /*
7921 * MAP_SHARED to prevent internal slot pages from being moved
7922 * by fork()/COW.
7923 */
7924 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7925 MAP_SHARED | MAP_ANONYMOUS, 0);
7926 if (IS_ERR((void *)hva))
7927 return PTR_ERR((void *)hva);
7928 } else {
7929 if (!slot->npages)
7930 return 0;
7931
7932 hva = 0;
7933 }
7934
7935 old = *slot;
9da0e4d5 7936 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7937 struct kvm_userspace_memory_region m;
9da0e4d5 7938
1d8007bd
PB		 7939 m.slot = id | (i << 16);
7940 m.flags = 0;
7941 m.guest_phys_addr = gpa;
f0d648bd 7942 m.userspace_addr = hva;
1d8007bd 7943 m.memory_size = size;
9da0e4d5
PB		 7944 r = __kvm_set_memory_region(kvm, &m);
7945 if (r < 0)
7946 return r;
7947 }
7948
f0d648bd
PB		 7949 if (!size) {
7950 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7951 WARN_ON(r < 0);
7952 }
7953
9da0e4d5
PB		 7954 return 0;
7955}
7956EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7957
1d8007bd 7958int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7959{
7960 int r;
7961
7962 mutex_lock(&kvm->slots_lock);
1d8007bd 7963 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7964 mutex_unlock(&kvm->slots_lock);
7965
7966 return r;
7967}
7968EXPORT_SYMBOL_GPL(x86_set_memory_region);
7969
d19a9cd2
ZX		 7970void kvm_arch_destroy_vm(struct kvm *kvm)
7971{
27469d29
AH		 7972 if (current->mm == kvm->mm) {
7973 /*
7974 * Free memory regions allocated on behalf of userspace,
7975 * unless the the memory map has changed due to process exit
7976 * or fd copying.
7977 */
1d8007bd
PB		 7978 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7979 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7980 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7981 }
03543133
SS		 7982 if (kvm_x86_ops->vm_destroy)
7983 kvm_x86_ops->vm_destroy(kvm);
6eb55818 7984 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7985 kfree(kvm->arch.vpic);
7986 kfree(kvm->arch.vioapic);
d19a9cd2 7987 kvm_free_vcpus(kvm);
af1bae54 7988 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7989 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7990}
0de10343 7991
5587027c 7992void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7993 struct kvm_memory_slot *dont)
7994{
7995 int i;
7996
d89cc617
TY		 7997 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7998 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7999 kvfree(free->arch.rmap[i]);
d89cc617 8000 free->arch.rmap[i] = NULL;
77d11309 8001 }
d89cc617
TY		 8002 if (i == 0)
8003 continue;
8004
8005 if (!dont || free->arch.lpage_info[i - 1] !=
8006 dont->arch.lpage_info[i - 1]) {
548ef284 8007 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8008 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8009 }
8010 }
21ebbeda
XG		 8011
8012 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8013}
8014
5587027c
AK		 8015int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8016 unsigned long npages)
db3fe4eb
TY		 8017{
8018 int i;
8019
d89cc617 8020 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8021 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8022 unsigned long ugfn;
8023 int lpages;
d89cc617 8024 int level = i + 1;
db3fe4eb
TY		 8025
8026 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8027 slot->base_gfn, level) + 1;
8028
d89cc617
TY		 8029 slot->arch.rmap[i] =
8030 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8031 if (!slot->arch.rmap[i])
77d11309 8032 goto out_free;
d89cc617
TY		 8033 if (i == 0)
8034 continue;
77d11309 8035
92f94f1e
XG		 8036 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8037 if (!linfo)
db3fe4eb
TY		 8038 goto out_free;
8039
92f94f1e
XG		 8040 slot->arch.lpage_info[i - 1] = linfo;
8041
db3fe4eb 8042 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8043 linfo[0].disallow_lpage = 1;
db3fe4eb 8044 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8045 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8046 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8047 /*
8048 * If the gfn and userspace address are not aligned wrt each
8049 * other, or if explicitly asked to, disable large page
8050 * support for this slot
8051 */
8052 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8053 !kvm_largepages_enabled()) {
8054 unsigned long j;
8055
8056 for (j = 0; j < lpages; ++j)
92f94f1e 8057 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8058 }
8059 }
8060
21ebbeda
XG		 8061 if (kvm_page_track_create_memslot(slot, npages))
8062 goto out_free;
8063
db3fe4eb
TY		 8064 return 0;
8065
8066out_free:
d89cc617 8067 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8068 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8069 slot->arch.rmap[i] = NULL;
8070 if (i == 0)
8071 continue;
8072
548ef284 8073 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8074 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8075 }
8076 return -ENOMEM;
8077}
8078
15f46015 8079void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8080{
e6dff7d1
TY		 8081 /*
8082 * memslots->generation has been incremented.
8083 * mmio generation may have reached its maximum value.
8084 */
54bf36aa 8085 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8086}
8087
f7784b8e
MT		 8088int kvm_arch_prepare_memory_region(struct kvm *kvm,
8089 struct kvm_memory_slot *memslot,
09170a49 8090 const struct kvm_userspace_memory_region *mem,
7b6195a9 8091 enum kvm_mr_change change)
0de10343 8092{
f7784b8e
MT		 8093 return 0;
8094}
8095
88178fd4
KH		 8096static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8097 struct kvm_memory_slot *new)
8098{
8099 /* Still write protect RO slot */
8100 if (new->flags & KVM_MEM_READONLY) {
8101 kvm_mmu_slot_remove_write_access(kvm, new);
8102 return;
8103 }
8104
8105 /*
8106 * Call kvm_x86_ops dirty logging hooks when they are valid.
8107 *
8108 * kvm_x86_ops->slot_disable_log_dirty is called when:
8109 *
8110 * - KVM_MR_CREATE with dirty logging is disabled
8111 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8112 *
8113 * The reason is, in case of PML, we need to set D-bit for any slots
8114 * with dirty logging disabled in order to eliminate unnecessary GPA
8115 * logging in PML buffer (and potential PML buffer full VMEXT). This
8116 * guarantees leaving PML enabled during guest's lifetime won't have
8117 * any additonal overhead from PML when guest is running with dirty
8118 * logging disabled for memory slots.
8119 *
8120 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8121 * to dirty logging mode.
8122 *
8123 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8124 *
8125 * In case of write protect:
8126 *
8127 * Write protect all pages for dirty logging.
8128 *
8129 * All the sptes including the large sptes which point to this
8130 * slot are set to readonly. We can not create any new large
8131 * spte on this slot until the end of the logging.
8132 *
8133 * See the comments in fast_page_fault().
8134 */
8135 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8136 if (kvm_x86_ops->slot_enable_log_dirty)
8137 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8138 else
8139 kvm_mmu_slot_remove_write_access(kvm, new);
8140 } else {
8141 if (kvm_x86_ops->slot_disable_log_dirty)
8142 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8143 }
8144}
8145
f7784b8e 8146void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8147 const struct kvm_userspace_memory_region *mem,
8482644a 8148 const struct kvm_memory_slot *old,
f36f3f28 8149 const struct kvm_memory_slot *new,
8482644a 8150 enum kvm_mr_change change)
f7784b8e 8151{
8482644a 8152 int nr_mmu_pages = 0;
f7784b8e 8153
48c0e4e9
XG		 8154 if (!kvm->arch.n_requested_mmu_pages)
8155 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8156
48c0e4e9 8157 if (nr_mmu_pages)
0de10343 8158 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8159
3ea3b7fa
WL		 8160 /*
8161 * Dirty logging tracks sptes in 4k granularity, meaning that large
8162 * sptes have to be split. If live migration is successful, the guest
8163 * in the source machine will be destroyed and large sptes will be
8164 * created in the destination. However, if the guest continues to run
8165 * in the source machine (for example if live migration fails), small
8166 * sptes will remain around and cause bad performance.
8167 *
8168 * Scan sptes if dirty logging has been stopped, dropping those
8169 * which can be collapsed into a single large-page spte. Later
8170 * page faults will create the large-page sptes.
8171 */
8172 if ((change != KVM_MR_DELETE) &&
8173 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8174 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8175 kvm_mmu_zap_collapsible_sptes(kvm, new);
8176
c972f3b1 8177 /*
88178fd4 8178 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8179 *
88178fd4
KH		 8180 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8181 * been zapped so no dirty logging staff is needed for old slot. For
8182 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8183 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8184 *
8185 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8186 */
88178fd4 8187 if (change != KVM_MR_DELETE)
f36f3f28 8188 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8189}
1d737c8a 8190
2df72e9b 8191void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8192{
6ca18b69 8193 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8194}
8195
2df72e9b
MT		 8196void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8197 struct kvm_memory_slot *slot)
8198{
b5f5fdca 8199 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8200}
8201
5d9bc648
PB		 8202static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8203{
8204 if (!list_empty_careful(&vcpu->async_pf.done))
8205 return true;
8206
8207 if (kvm_apic_has_events(vcpu))
8208 return true;
8209
8210 if (vcpu->arch.pv.pv_unhalted)
8211 return true;
8212
8213 if (atomic_read(&vcpu->arch.nmi_queued))
8214 return true;
8215
73917739
PB		 8216 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8217 return true;
8218
5d9bc648
PB		 8219 if (kvm_arch_interrupt_allowed(vcpu) &&
8220 kvm_cpu_has_interrupt(vcpu))
8221 return true;
8222
1f4b34f8
AS		 8223 if (kvm_hv_has_stimer_pending(vcpu))
8224 return true;
8225
5d9bc648
PB		 8226 return false;
8227}
8228
1d737c8a
ZX		 8229int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8230{
b6b8a145
JK		 8231 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8232 kvm_x86_ops->check_nested_events(vcpu, false);
8233
5d9bc648 8234 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8235}
5736199a 8236
b6d33834 8237int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8238{
b6d33834 8239 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8240}
78646121
GN		 8241
8242int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8243{
8244 return kvm_x86_ops->interrupt_allowed(vcpu);
8245}
229456fc 8246
82b32774 8247unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8248{
82b32774
NA		 8249 if (is_64_bit_mode(vcpu))
8250 return kvm_rip_read(vcpu);
8251 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8252 kvm_rip_read(vcpu));
8253}
8254EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8255
82b32774
NA		 8256bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8257{
8258 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8259}
8260EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8261
94fe45da
JK		 8262unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8263{
8264 unsigned long rflags;
8265
8266 rflags = kvm_x86_ops->get_rflags(vcpu);
8267 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8268 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8269 return rflags;
8270}
8271EXPORT_SYMBOL_GPL(kvm_get_rflags);
8272
6addfc42 8273static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8274{
8275 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8276 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8277 rflags |= X86_EFLAGS_TF;
94fe45da 8278 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8279}
8280
8281void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8282{
8283 __kvm_set_rflags(vcpu, rflags);
3842d135 8284 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8285}
8286EXPORT_SYMBOL_GPL(kvm_set_rflags);
8287
56028d08
GN		 8288void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8289{
8290 int r;
8291
fb67e14f 8292 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8293 work->wakeup_all)
56028d08
GN		 8294 return;
8295
8296 r = kvm_mmu_reload(vcpu);
8297 if (unlikely(r))
8298 return;
8299
fb67e14f
XG		 8300 if (!vcpu->arch.mmu.direct_map &&
8301 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8302 return;
8303
56028d08
GN		 8304 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8305}
8306
af585b92
GN		 8307static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8308{
8309 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8310}
8311
8312static inline u32 kvm_async_pf_next_probe(u32 key)
8313{
8314 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8315}
8316
8317static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8318{
8319 u32 key = kvm_async_pf_hash_fn(gfn);
8320
8321 while (vcpu->arch.apf.gfns[key] != ~0)
8322 key = kvm_async_pf_next_probe(key);
8323
8324 vcpu->arch.apf.gfns[key] = gfn;
8325}
8326
8327static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8328{
8329 int i;
8330 u32 key = kvm_async_pf_hash_fn(gfn);
8331
8332 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8333 (vcpu->arch.apf.gfns[key] != gfn &&
8334 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8335 key = kvm_async_pf_next_probe(key);
8336
8337 return key;
8338}
8339
8340bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8341{
8342 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8343}
8344
8345static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8346{
8347 u32 i, j, k;
8348
8349 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8350 while (true) {
8351 vcpu->arch.apf.gfns[i] = ~0;
8352 do {
8353 j = kvm_async_pf_next_probe(j);
8354 if (vcpu->arch.apf.gfns[j] == ~0)
8355 return;
8356 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8357 /*
8358 * k lies cyclically in ]i,j]
8359 * | i.k.j |
8360 * |....j i.k.| or |.k..j i...|
8361 */
8362 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8363 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8364 i = j;
8365 }
8366}
8367
7c90705b
GN		 8368static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8369{
8370
8371 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8372 sizeof(val));
8373}
8374
af585b92
GN		 8375void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8376 struct kvm_async_pf *work)
8377{
6389ee94
AK		 8378 struct x86_exception fault;
8379
7c90705b 8380 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8381 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8382
8383 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8384 (vcpu->arch.apf.send_user_only &&
8385 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8386 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8387 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8388 fault.vector = PF_VECTOR;
8389 fault.error_code_valid = true;
8390 fault.error_code = 0;
8391 fault.nested_page_fault = false;
8392 fault.address = work->arch.token;
8393 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8394 }
af585b92
GN		 8395}
8396
8397void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8398 struct kvm_async_pf *work)
8399{
6389ee94
AK		 8400 struct x86_exception fault;
8401
7c90705b 8402 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8403 if (work->wakeup_all)
7c90705b
GN		 8404 work->arch.token = ~0; /* broadcast wakeup */
8405 else
8406 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8407
8408 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8409 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8410 fault.vector = PF_VECTOR;
8411 fault.error_code_valid = true;
8412 fault.error_code = 0;
8413 fault.nested_page_fault = false;
8414 fault.address = work->arch.token;
8415 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8416 }
e6d53e3b 8417 vcpu->arch.apf.halted = false;
a4fa1635 8418 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8419}
8420
8421bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8422{
8423 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8424 return true;
8425 else
8426 return !kvm_event_needs_reinjection(vcpu) &&
8427 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8428}
8429
5544eb9b
PB		 8430void kvm_arch_start_assignment(struct kvm *kvm)
8431{
8432 atomic_inc(&kvm->arch.assigned_device_count);
8433}
8434EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8435
8436void kvm_arch_end_assignment(struct kvm *kvm)
8437{
8438 atomic_dec(&kvm->arch.assigned_device_count);
8439}
8440EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8441
8442bool kvm_arch_has_assigned_device(struct kvm *kvm)
8443{
8444 return atomic_read(&kvm->arch.assigned_device_count);
8445}
8446EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8447
e0f0bbc5
AW		 8448void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8449{
8450 atomic_inc(&kvm->arch.noncoherent_dma_count);
8451}
8452EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8453
8454void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8455{
8456 atomic_dec(&kvm->arch.noncoherent_dma_count);
8457}
8458EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8459
8460bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8461{
8462 return atomic_read(&kvm->arch.noncoherent_dma_count);
8463}
8464EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8465
14717e20
AW		 8466bool kvm_arch_has_irq_bypass(void)
8467{
8468 return kvm_x86_ops->update_pi_irte != NULL;
8469}
8470
87276880
FW		 8471int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8472 struct irq_bypass_producer *prod)
8473{
8474 struct kvm_kernel_irqfd *irqfd =
8475 container_of(cons, struct kvm_kernel_irqfd, consumer);
8476
14717e20 8477 irqfd->producer = prod;
87276880 8478
14717e20
AW		 8479 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8480 prod->irq, irqfd->gsi, 1);
87276880
FW		 8481}
8482
8483void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8484 struct irq_bypass_producer *prod)
8485{
8486 int ret;
8487 struct kvm_kernel_irqfd *irqfd =
8488 container_of(cons, struct kvm_kernel_irqfd, consumer);
8489
87276880
FW		 8490 WARN_ON(irqfd->producer != prod);
8491 irqfd->producer = NULL;
8492
8493 /*
8494 * When producer of consumer is unregistered, we change back to
8495 * remapped mode, so we can re-use the current implementation
bb3541f1 8496 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8497 * int this case doesn't want to receive the interrupts.
8498 */
8499 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8500 if (ret)
8501 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8502 " fails: %d\n", irqfd->consumer.token, ret);
8503}
8504
8505int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8506 uint32_t guest_irq, bool set)
8507{
8508 if (!kvm_x86_ops->update_pi_irte)
8509 return -EINVAL;
8510
8511 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8512}
8513
52004014
FW		 8514bool kvm_vector_hashing_enabled(void)
8515{
8516 return vector_hashing;
8517}
8518EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8519
229456fc 8520EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8521EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8522EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8523EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8524EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8525EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8526EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8527EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8528EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8529EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8530EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8531EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8532EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8533EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8534EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8535EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8536EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8537EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8538EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git