[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

2020-02-11  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
	fucompi): Drop ShortForm from operand-less templates.
	* i386-tbl.h: Re-generate.

2020-02-11  Alan Modra  <amodra@gmail.com>

	* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
	* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
	* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
	* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
	* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.

2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (print_insn_cde): Define 'V' parse character.
	(cde_opcodes): Add VCX* instructions.

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (struct cdeopcode32): New.
	(CDE_OPCODE): New macro.
	(cde_opcodes): New disassembly table.
	(regnames): New option to table.
	(cde_coprocs): New global variable.
	(print_insn_cde): New
	(print_insn_thumb32): Use print_insn_cde.
	(parse_arm_disassembler_options): Parse coprocN args.

2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/25516
	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	with ISA64.
	* i386-opc.h (AMD64): Removed.
	(Intel64): Likewose.
	(AMD64): New.
	(INTEL64): Likewise.
	(INTEL64ONLY): Likewise.
	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	* i386-opc.tbl (Amd64): New.
	(Intel64): Likewise.
	(Intel64Only): Likewise.
	Replace AMD64 with Amd64.  Update sysenter/sysenter with
	Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
	* i386-tbl.h: Regenerated.

2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25469
	* z80-dis.c: Add support for GBZ80 opcodes.

2020-02-04  Alan Modra  <amodra@gmail.com>

	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.

2020-02-03  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-02-01  Alan Modra  <amodra@gmail.com>

	* frv-ibld.c: Regenerate.

2020-01-31  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
	(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
	(OP_E_memory): Replace xmm_mdq_mode case label by
	vex_scalar_w_dq_mode one.
	* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.

2020-01-31  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
	(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
	vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
	(intel_operand_size): Drop vex_w_dq_mode case label.

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.

2020-01-30  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c: Regenerate.

2020-01-30  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
	(dis386): Use them to replace C2/C3 table entries.
	(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
	* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
	ones. Use Size64 instead of DefaultSize on Intel64 ones.
	* i386-tbl.h: Re-generate.

2020-01-30  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
	forms.
	(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
	DefaultSize.
	* i386-tbl.h: Re-generate.

2020-01-30  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_dp): Make unsigned.

2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
	    Jan Beulich  <jbeulich@suse.com>

	PR binutils/25445
	* i386-dis.c (MOVSXD_Fixup): New function.
	(movsxd_mode): New enum.
	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	(intel_operand_size): Handle movsxd_mode.
	(OP_E_register): Likewise.
	(OP_G): Likewise.
	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	register on movsxd.  Add movsxd with 16-bit destination register
	for AMD64 and Intel64 ISAs.
	* i386-tbl.h: Regenerated.

2020-01-27  Tamar Christina  <tamar.christina@arm.com>

	PR 25403
	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	* aarch64-asm-2.c: Regenerate
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2020-01-21  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (sysret): Drop DefaultSize.
	* i386-tbl.h: Re-generate.

2020-01-21  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
	Dword.
	(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
	* i386-tbl.h: Re-generate.

2020-01-20  Nick Clifton  <nickc@redhat.com>

	* po/de.po: Updated German translation.
	* po/pt_BR.po: Updated Brazilian Portuguese translation.
	* po/uk.po: Updated Ukranian translation.

2020-01-20  Alan Modra  <amodra@gmail.com>

	* hppa-dis.c (fput_const): Remove useless cast.

2020-01-20  Alan Modra  <amodra@gmail.com>

	* arm-dis.c (print_insn_arm): Wrap 'T' value.

2020-01-18  Nick Clifton  <nickc@redhat.com>

	* configure: Regenerate.
	* po/opcodes.pot: Regenerate.

2020-01-18  Nick Clifton  <nickc@redhat.com>

	Binutils 2.34 branch created.

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* opintl.h: Fix spelling error (seperate).

2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add {vex} pseudo prefix.
	* i386-tbl.h: Regenerated.

2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: Drop stale comment from XOP section.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
	(extractps): Add VexWIG to SSE2AVX forms.
	* i386-tbl.h: Re-generate.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
	Size64 from and use VexW1 on SSE2AVX forms.
	(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
	VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
	* i386-tbl.h: Re-generate.

2020-01-15  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_version): Make unsigned long.
	(optab, optab_special, registernames): New file scope vars.
	(tic4x_print_register): Set up registernames rather than
	malloc'd registertable.
	(tic4x_disassemble): Delete optable and optable_special.  Use
	optab and optab_special instead.  Throw away old optab,
	optab_special and registernames when info->mach changes.

2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25377
	* z80-dis.c (suffix): Use .db instruction to generate double
	prefix.

2020-01-14  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
	values to unsigned before shifting.

2020-01-13  Thomas Troeger  <tstroege@gmx.de>

	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	flow instructions.
	(print_insn_thumb16, print_insn_thumb32): Likewise.
	(print_insn): Initialize the insn info.
	* i386-dis.c (print_insn): Initialize the insn info fields, and
	detect jumps.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

	* arc-opc.c (C_NE): Make it required.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

        * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	reserved register name.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
	result of wasm_read_leb128 in a uint64_t and check that bits
	are not lost when copying to other locals.  Use uint32_t for
	most locals.  Use PRId64 when printing int64_t.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c: Formatting.
	* score7-dis.c: Formatting.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c (print_insn_score48): Use unsigned variables for
	unsigned values.  Don't left shift negative values.
	(print_insn_score32): Likewise.
	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_print_register): Remove dead code.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* fr30-ibld.c: Regenerate.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* xgate-dis.c (print_insn): Don't left shift signed value.
	(ripBits): Formatting, use 1u.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	and XRREG value earlier to avoid a shift with negative exponent.
	* m10200-dis.c (disassemble): Similarly.

2020-01-09  Nick Clifton  <nickc@redhat.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use correct cast.

2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use character constant when checking
	opcode byte value.

2020-01-09  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (SEP_Fixup): New.
	(SEP): Define.
	(dis386_twobyte): Use it for sysenter/sysexit.
	(enum x86_64_isa): Change amd64 enumerator to value 1.
	(OP_J): Compare isa64 against intel64 instead of amd64.
	* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
	forms.
	* i386-tbl.h: Re-generate.

2020-01-08  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c: Include libiberty.h
	(instr_data_s): Make max_fetched unsigned.
	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	Don't exceed byte_info bounds.
	(output_instr): Make num_bytes unsigned.
	(unpack_instr): Likewise for nibl_count and loop.
	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	idx unsigned.
	* z8k-opc.h: Regenerate.

2020-01-07  Shahab Vahedi  <shahab@synopsys.com>

	* arc-tbl.h (llock): Use 'LLOCK' as class.
	(llockd): Likewise.
	(scond): Use 'SCOND' as class.
	(scondd): Likewise.
	(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
	(scondd): Likewise.

2020-01-06  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-01-06  Alan Modra  <amodra@gmail.com>

	PR 25344
	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	Peek at next byte to prevent recursion on repeated prefix bytes.
	Ensure uninitialised "mybuf" is not accessed.
	(print_insn_z80): Don't zero n_fetch and n_used here,..
	(print_insn_z80_buf): ..do it here instead.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* m32r-ibld.c: Regenerate.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* crx-dis.c (match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* d30v-dis.c (print_insn): Avoid signed overflow in left shift.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Use
	SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
	forms of SUDOT and USDOT.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
	uzip{1,2}.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
	FMMLA encoding.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>

	* z80-dis.c: Add support for eZ80 and Z80 instructions.

2020-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2019
\f
Copyright (C) 2020 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
1e05b5c4 JB	1	2020-02-11 Jan Beulich <jbeulich@suse.com>
	2
	3	* i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
	4	fucompi): Drop ShortForm from operand-less templates.
	5	* i386-tbl.h: Re-generate.
	6
2f5dd314 AM	7	2020-02-11 Alan Modra <amodra@gmail.com>
	8
	9	* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
	10	* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
	11	* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
	12	* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
	13	* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
	14
5aae9ae9 MM	15	2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
	16
	17	* arm-dis.c (print_insn_cde): Define 'V' parse character.
	18	(cde_opcodes): Add VCX* instructions.
	19
4934a27c MM	20	2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
	21	Matthew Malcomson <matthew.malcomson@arm.com>
	22
	23	* arm-dis.c (struct cdeopcode32): New.
	24	(CDE_OPCODE): New macro.
	25	(cde_opcodes): New disassembly table.
	26	(regnames): New option to table.
	27	(cde_coprocs): New global variable.
	28	(print_insn_cde): New
	29	(print_insn_thumb32): Use print_insn_cde.
	30	(parse_arm_disassembler_options): Parse coprocN args.
	31
4b5aaf5f L	32	2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
	33
	34	PR gas/25516
	35	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	36	with ISA64.
	37	* i386-opc.h (AMD64): Removed.
	38	(Intel64): Likewose.
	39	(AMD64): New.
	40	(INTEL64): Likewise.
	41	(INTEL64ONLY): Likewise.
	42	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	43	* i386-opc.tbl (Amd64): New.
	44	(Intel64): Likewise.
	45	(Intel64Only): Likewise.
	46	Replace AMD64 with Amd64. Update sysenter/sysenter with
	47	Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
	48	* i386-tbl.h: Regenerated.
	49
9fc0b501 SB	50	2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
	51
	52	PR 25469
	53	* z80-dis.c: Add support for GBZ80 opcodes.
	54
c5d7be0c AM	55	2020-02-04 Alan Modra <amodra@gmail.com>
	56
	57	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
	58
44e4546f AM	59	2020-02-03 Alan Modra <amodra@gmail.com>
	60
	61	* m32c-ibld.c: Regenerate.
	62
b2b1453a AM	63	2020-02-01 Alan Modra <amodra@gmail.com>
	64
	65	* frv-ibld.c: Regenerate.
	66
4102be5c JB	67	2020-01-31 Jan Beulich <jbeulich@suse.com>
	68
	69	* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
	70	(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
	71	(OP_E_memory): Replace xmm_mdq_mode case label by
	72	vex_scalar_w_dq_mode one.
	73	* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
	74
825bd36c JB	75	2020-01-31 Jan Beulich <jbeulich@suse.com>
	76
	77	* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
	78	(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
	79	vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
	80	(intel_operand_size): Drop vex_w_dq_mode case label.
	81
c3036ed0 RS	82	2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
	83
	84	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	85	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
	86
0c115f84 AM	87	2020-01-30 Alan Modra <amodra@gmail.com>
	88
	89	* m32c-ibld.c: Regenerate.
	90
bd434cc4 JM	91	2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
	92
	93	* bpf-opc.c: Regenerate.
	94
aeab2b26 JB	95	2020-01-30 Jan Beulich <jbeulich@suse.com>
	96
	97	* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
	98	(dis386): Use them to replace C2/C3 table entries.
	99	(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
	100	* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
	101	ones. Use Size64 instead of DefaultSize on Intel64 ones.
	102	* i386-tbl.h: Re-generate.
	103
62b3f548 JB	104	2020-01-30 Jan Beulich <jbeulich@suse.com>
	105
	106	* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
	107	forms.
	108	(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
	109	DefaultSize.
	110	* i386-tbl.h: Re-generate.
	111
1bd8ae10 AM	112	2020-01-30 Alan Modra <amodra@gmail.com>
	113
	114	* tic4x-dis.c (tic4x_dp): Make unsigned.
	115
bc31405e L	116	2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
	117	Jan Beulich <jbeulich@suse.com>
	118
	119	PR binutils/25445
	120	* i386-dis.c (MOVSXD_Fixup): New function.
	121	(movsxd_mode): New enum.
	122	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	123	(intel_operand_size): Handle movsxd_mode.
	124	(OP_E_register): Likewise.
	125	(OP_G): Likewise.
	126	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	127	register on movsxd. Add movsxd with 16-bit destination register
	128	for AMD64 and Intel64 ISAs.
	129	* i386-tbl.h: Regenerated.
	130
7568c93b TC	131	2020-01-27 Tamar Christina <tamar.christina@arm.com>
	132
	133	PR 25403
	134	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	135	* aarch64-asm-2.c: Regenerate
	136	* aarch64-dis-2.c: Likewise.
	137	* aarch64-opc-2.c: Likewise.
	138
c006a730 JB	139	2020-01-21 Jan Beulich <jbeulich@suse.com>
	140
	141	* i386-opc.tbl (sysret): Drop DefaultSize.
	142	* i386-tbl.h: Re-generate.
	143
c906a69a JB	144	2020-01-21 Jan Beulich <jbeulich@suse.com>
	145
	146	* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
	147	Dword.
	148	(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
	149	* i386-tbl.h: Re-generate.
	150
26916852 NC	151	2020-01-20 Nick Clifton <nickc@redhat.com>
	152
	153	* po/de.po: Updated German translation.
	154	* po/pt_BR.po: Updated Brazilian Portuguese translation.
	155	* po/uk.po: Updated Ukranian translation.
	156
4d6cbb64 AM	157	2020-01-20 Alan Modra <amodra@gmail.com>
	158
	159	* hppa-dis.c (fput_const): Remove useless cast.
	160
2bddb71a AM	161	2020-01-20 Alan Modra <amodra@gmail.com>
	162
	163	* arm-dis.c (print_insn_arm): Wrap 'T' value.
	164
1b1bb2c6 NC	165	2020-01-18 Nick Clifton <nickc@redhat.com>
	166
	167	* configure: Regenerate.
	168	* po/opcodes.pot: Regenerate.
	169
ae774686 NC	170	2020-01-18 Nick Clifton <nickc@redhat.com>
	171
	172	Binutils 2.34 branch created.
	173
07f1f3aa CB	174	2020-01-17 Christian Biesinger <cbiesinger@google.com>
	175
	176	* opintl.h: Fix spelling error (seperate).
	177
42e04b36 L	178	2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
	179
	180	* i386-opc.tbl: Add {vex} pseudo prefix.
	181	* i386-tbl.h: Regenerated.
	182
2da2eaf4 AV	183	2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
	184
	185	PR 25376
	186	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	187	(neon_opcodes): Likewise.
	188	(select_arm_features): Make sure we enable MVE bits when selecting
	189	armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
	190	any architecture.
	191
d0849eed JB	192	2020-01-16 Jan Beulich <jbeulich@suse.com>
	193
	194	* i386-opc.tbl: Drop stale comment from XOP section.
	195
9cf70a44 JB	196	2020-01-16 Jan Beulich <jbeulich@suse.com>
	197
	198	* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
	199	(extractps): Add VexWIG to SSE2AVX forms.
	200	* i386-tbl.h: Re-generate.
	201
4814632e JB	202	2020-01-16 Jan Beulich <jbeulich@suse.com>
	203
	204	* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
	205	Size64 from and use VexW1 on SSE2AVX forms.
	206	(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
	207	VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
	208	* i386-tbl.h: Re-generate.
	209
aad09917 AM	210	2020-01-15 Alan Modra <amodra@gmail.com>
	211
	212	* tic4x-dis.c (tic4x_version): Make unsigned long.
	213	(optab, optab_special, registernames): New file scope vars.
	214	(tic4x_print_register): Set up registernames rather than
	215	malloc'd registertable.
	216	(tic4x_disassemble): Delete optable and optable_special. Use
	217	optab and optab_special instead. Throw away old optab,
	218	optab_special and registernames when info->mach changes.
	219
7a6bf3be SB	220	2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
	221
	222	PR 25377
	223	* z80-dis.c (suffix): Use .db instruction to generate double
	224	prefix.
	225
ca1eaac0 AM	226	2020-01-14 Alan Modra <amodra@gmail.com>
	227
	228	* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
	229	values to unsigned before shifting.
	230
1d67fe3b TT	231	2020-01-13 Thomas Troeger <tstroege@gmx.de>
	232
	233	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	234	flow instructions.
	235	(print_insn_thumb16, print_insn_thumb32): Likewise.
	236	(print_insn): Initialize the insn info.
	237	* i386-dis.c (print_insn): Initialize the insn info fields, and
	238	detect jumps.
	239
5e4f7e05 CZ	240	2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
	241
	242	* arc-opc.c (C_NE): Make it required.
	243
b9fe6b8a CZ	244	2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
	245
	246	* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	247	reserved register name.
	248
90dee485 AM	249	2020-01-13 Alan Modra <amodra@gmail.com>
	250
	251	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	252	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
	253
febda64f AM	254	2020-01-13 Alan Modra <amodra@gmail.com>
	255
	256	* wasm32-dis.c (print_insn_wasm32): Localise variables. Store
	257	result of wasm_read_leb128 in a uint64_t and check that bits
	258	are not lost when copying to other locals. Use uint32_t for
	259	most locals. Use PRId64 when printing int64_t.
	260
df08b588 AM	261	2020-01-13 Alan Modra <amodra@gmail.com>
	262
	263	* score-dis.c: Formatting.
	264	* score7-dis.c: Formatting.
	265
b2c759ce AM	266	2020-01-13 Alan Modra <amodra@gmail.com>
	267
	268	* score-dis.c (print_insn_score48): Use unsigned variables for
	269	unsigned values. Don't left shift negative values.
	270	(print_insn_score32): Likewise.
	271	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
	272
5496abe1 AM	273	2020-01-13 Alan Modra <amodra@gmail.com>
	274
	275	* tic4x-dis.c (tic4x_print_register): Remove dead code.
	276
202e762b AM	277	2020-01-13 Alan Modra <amodra@gmail.com>
	278
	279	* fr30-ibld.c: Regenerate.
	280
7ef412cf AM	281	2020-01-13 Alan Modra <amodra@gmail.com>
	282
	283	* xgate-dis.c (print_insn): Don't left shift signed value.
	284	(ripBits): Formatting, use 1u.
	285
7f578b95 AM	286	2020-01-10 Alan Modra <amodra@gmail.com>
	287
	288	* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	289	* tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
	290
441af85b AM	291	2020-01-10 Alan Modra <amodra@gmail.com>
	292
	293	* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	294	and XRREG value earlier to avoid a shift with negative exponent.
	295	* m10200-dis.c (disassemble): Similarly.
	296
bce58db4 NC	297	2020-01-09 Nick Clifton <nickc@redhat.com>
	298
	299	PR 25224
	300	* z80-dis.c (ld_ii_ii): Use correct cast.
	301
40c75bc8 SB	302	2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
	303
	304	PR 25224
	305	* z80-dis.c (ld_ii_ii): Use character constant when checking
	306	opcode byte value.
	307
d835a58b JB	308	2020-01-09 Jan Beulich <jbeulich@suse.com>
	309
	310	* i386-dis.c (SEP_Fixup): New.
	311	(SEP): Define.
	312	(dis386_twobyte): Use it for sysenter/sysexit.
	313	(enum x86_64_isa): Change amd64 enumerator to value 1.
	314	(OP_J): Compare isa64 against intel64 instead of amd64.
	315	* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
	316	forms.
	317	* i386-tbl.h: Re-generate.
	318
030a2e78 AM	319	2020-01-08 Alan Modra <amodra@gmail.com>
	320
	321	* z8k-dis.c: Include libiberty.h
	322	(instr_data_s): Make max_fetched unsigned.
	323	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	324	Don't exceed byte_info bounds.
	325	(output_instr): Make num_bytes unsigned.
	326	(unpack_instr): Likewise for nibl_count and loop.
	327	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	328	idx unsigned.
	329	* z8k-opc.h: Regenerate.
	330
bb82aefe SV	331	2020-01-07 Shahab Vahedi <shahab@synopsys.com>
	332
	333	* arc-tbl.h (llock): Use 'LLOCK' as class.
	334	(llockd): Likewise.
	335	(scond): Use 'SCOND' as class.
	336	(scondd): Likewise.
	337	(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
	338	(scondd): Likewise.
	339
cc6aa1a6 AM	340	2020-01-06 Alan Modra <amodra@gmail.com>
	341
	342	* m32c-ibld.c: Regenerate.
	343
660e62b1 AM	344	2020-01-06 Alan Modra <amodra@gmail.com>
	345
	346	PR 25344
	347	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	348	Peek at next byte to prevent recursion on repeated prefix bytes.
	349	Ensure uninitialised "mybuf" is not accessed.
	350	(print_insn_z80): Don't zero n_fetch and n_used here,..
	351	(print_insn_z80_buf): ..do it here instead.
	352
c9ae58fe AM	353	2020-01-04 Alan Modra <amodra@gmail.com>
	354
	355	* m32r-ibld.c: Regenerate.
	356
5f57d4ec AM	357	2020-01-04 Alan Modra <amodra@gmail.com>
	358
	359	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
	360
2c5c1196 AM	361	2020-01-04 Alan Modra <amodra@gmail.com>
	362
	363	* crx-dis.c (match_opcode): Avoid shift left of signed value.
	364
2e98c6c5 AM	365	2020-01-04 Alan Modra <amodra@gmail.com>
	366
	367	* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
	368
567dfba2 JB	369	2020-01-03 Jan Beulich <jbeulich@suse.com>
567dfba2 JB	370
5437a02a JB	371	* aarch64-tbl.h (aarch64_opcode_table): Use
	372	SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
	373
	374	2020-01-03 Jan Beulich <jbeulich@suse.com>
	375
	376	* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2 JB	377	forms of SUDOT and USDOT.
567dfba2 JB	378
8c45011a JB	379	2020-01-03 Jan Beulich <jbeulich@suse.com>
8c45011a JB	380
5437a02a	381	* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a JB	382	uzip{1,2}.
	383	* opcodes/aarch64-dis-2.c: Re-generate.
	384
f4950f76 JB	385	2020-01-03 Jan Beulich <jbeulich@suse.com>
f4950f76 JB	386
5437a02a	387	* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76 JB	388	FMMLA encoding.
	389	* opcodes/aarch64-dis-2.c: Re-generate.
	390
6655dba2 SB	391	2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
	392
	393	* z80-dis.c: Add support for eZ80 and Z80 instructions.
	394
b14ce8bf AM	395	2020-01-01 Alan Modra <amodra@gmail.com>
	396
	397	Update year range in copyright notice of all files.
	398
0b114740	399	For older changes see ChangeLog-2019
3499769a	400	\f
0b114740	401	Copyright (C) 2020 Free Software Foundation, Inc.
3499769a AM	402
	403	Copying and distribution of this file, with or without modification,
	404	are permitted in any medium without royalty provided the copyright
	405	notice and this notice are preserved.
	406
	407	Local Variables:
	408	mode: change-log
	409	left-margin: 8
	410	fill-column: 74
	411	version-control: never
	412	End: