]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/mips/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
*** empty log message ***
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
1c47a468
CD		 12002-02-27 Chris Demetriou <cgd@broadcom.com>
2
3 * mips.igen (do_load_left, do_load_right): Move to be immediately
4 following do_load.
5 (do_store_left, do_store_right): Move to be immediately following
6 do_store.
7
603a98e7
CD		 82002-02-27 Chris Demetriou <cgd@broadcom.com>
9
10 * mips.igen (mipsV): New model name. Also, add it to
11 all instructions and functions where it is appropriate.
12
c5d00cc7
CD		 132002-02-18 Chris Demetriou <cgd@broadcom.com>
14
15 * mips.igen: For all functions and instructions, list model
16 names that support that instruction one per line.
17
074e9cb8
CD		 182002-02-11 Chris Demetriou <cgd@broadcom.com>
19
20 * mips.igen: Add some additional comments about supported
21 models, and about which instructions go where.
22 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
23 order as is used in the rest of the file.
24
9805e229
CD		 252002-02-11 Chris Demetriou <cgd@broadcom.com>
26
27 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
28 indicating that ALU32_END or ALU64_END are there to check
29 for overflow.
30 (DADD): Likewise, but also remove previous comment about
31 overflow checking.
32
f701dad2
CD		 332002-02-10 Chris Demetriou <cgd@broadcom.com>
34
35 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
36 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
37 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
38 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
39 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
40 fields (i.e., add and move commas) so that they more closely
41 match the MIPS ISA documentation opcode partitioning.
42
432002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 44
45 * mips.igen (ADDI): Print immediate value.
46 (BREAK): Print code.
47 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
48 (SLL): Print "nop" specially, and don't run the code
49 that does the shift for the "nop" case.
50
9e52972e
FF		 512001-11-17 Fred Fish <fnf@redhat.com>
52
53 * sim-main.h (float_operation): Move enum declaration outside
54 of _sim_cpu struct declaration.
55
c0efbca4
JB		 562001-04-12 Jim Blandy <jimb@redhat.com>
57
58 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
59 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
60 set of the FCSR.
61 * sim-main.h (COCIDX): Remove definition; this isn't supported by
62 PENDING_FILL, and you can get the intended effect gracefully by
63 calling PENDING_SCHED directly.
64
fb891446
BE		 652001-02-23 Ben Elliston <bje@redhat.com>
66
67 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
68 already defined elsewhere.
69
8030f857
BE		 702001-02-19 Ben Elliston <bje@redhat.com>
71
72 * sim-main.h (sim_monitor): Return an int.
73 * interp.c (sim_monitor): Add return values.
74 (signal_exception): Handle error conditions from sim_monitor.
75
56b48a7a
CD		 762001-02-08 Ben Elliston <bje@redhat.com>
77
78 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
79 (store_memory): Likewise, pass cia to sim_core_write*.
80
d3ee60d9
FCE		 812000-10-19 Frank Ch. Eigler <fche@redhat.com>
82
83 On advice from Chris G. Demetriou <cgd@sibyte.com>:
84 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
85
071da002
AC		 86Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
87
88 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
89 * Makefile.in: Don't delete *.igen when cleaning directory.
90
a28c02cd
AC		 91Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
92
93 * m16.igen (break): Call SignalException not sim_engine_halt.
94
80ee11fa
AC		 95Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
96
97 From Jason Eckhardt:
98 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
99
673388c0
AC		 100Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
101
102 * mips.igen (MxC1, DMxC1): Fix printf formatting.
103
4c0deff4
NC		 1042000-05-24 Michael Hayes <mhayes@cygnus.com>
105
106 * mips.igen (do_dmultx): Fix typo.
107
eb2d80b4
AC		 108Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
109
110 * configure: Regenerated to track ../common/aclocal.m4 changes.
111
dd37a34b
AC		 112Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
113
114 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
115
4c0deff4
NC		 1162000-04-12 Frank Ch. Eigler <fche@redhat.com>
117
118 * sim-main.h (GPR_CLEAR): Define macro.
119
e30db738
AC		 120Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
121
122 * interp.c (decode_coproc): Output long using %lx and not %s.
123
cb7450ea
FCE		 1242000-03-21 Frank Ch. Eigler <fche@redhat.com>
125
126 * interp.c (sim_open): Sort & extend dummy memory regions for
127 --board=jmr3904 for eCos.
128
a3027dd7
FCE		 1292000-03-02 Frank Ch. Eigler <fche@redhat.com>
130
131 * configure: Regenerated.
132
133Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
134
135 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
136 calls, conditional on the simulator being in verbose mode.
137
dfcd3bfb
JM		 138Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
139
140 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
141 cache don't get ReservedInstruction traps.
142
c2d11a7d
JM		 1431999-11-29 Mark Salter <msalter@cygnus.com>
144
145 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
146 to clear status bits in sdisr register. This is how the hardware works.
147
148 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
149 being used by cygmon.
150
4ce44c66
JM		 1511999-11-11 Andrew Haley <aph@cygnus.com>
152
153 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
154 instructions.
155
cff3e48b
JM		 156Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
157
158 * mips.igen (MULT): Correct previous mis-applied patch.
159
d4f3574e
SS		 160Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
161
162 * mips.igen (delayslot32): Handle sequence like
163 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
164 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
165 (MULT): Actually pass the third register...
166
1671999-09-03 Mark Salter <msalter@cygnus.com>
168
169 * interp.c (sim_open): Added more memory aliases for additional
170 hardware being touched by cygmon on jmr3904 board.
171
172Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
173
174 * configure: Regenerated to track ../common/aclocal.m4 changes.
175
a0b3c4fd
JM		 176Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
177
178 * interp.c (sim_store_register): Handle case where client - GDB -
179 specifies that a 4 byte register is 8 bytes in size.
180 (sim_fetch_register): Ditto.
181
adf40b2e
JM		 1821999-07-14 Frank Ch. Eigler <fche@cygnus.com>
183
184 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
185 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
186 (idt_monitor_base): Base address for IDT monitor traps.
187 (pmon_monitor_base): Ditto for PMON.
188 (lsipmon_monitor_base): Ditto for LSI PMON.
189 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
190 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
191 (sim_firmware_command): New function.
192 (mips_option_handler): Call it for OPTION_FIRMWARE.
193 (sim_open): Allocate memory for idt_monitor region. If "--board"
194 option was given, add no monitor by default. Add BREAK hooks only if
195 monitors are also there.
196
43e526b9
JM		 197Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
198
199 * interp.c (sim_monitor): Flush output before reading input.
200
201Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
202
203 * tconfig.in (SIM_HANDLES_LMA): Always define.
204
205Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
206
207 From Mark Salter <msalter@cygnus.com>:
208 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
209 (sim_open): Add setup for BSP board.
210
9846de1b
JM		 211Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
212
213 * mips.igen (MULT, MULTU): Add syntax for two operand version.
214 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
215 them as unimplemented.
216
cd0fc7c3
SS		 2171999-05-08 Felix Lee <flee@cygnus.com>
218
219 * configure: Regenerated to track ../common/aclocal.m4 changes.
220
7a292a7a
SS		 2211999-04-21 Frank Ch. Eigler <fche@cygnus.com>
222
223 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
224
225Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
226
227 * configure.in: Any mips64vr5*-*-* target should have
228 -DTARGET_ENABLE_FR=1.
229 (default_endian): Any mips64vr*el-*-* target should default to
230 LITTLE_ENDIAN.
231 * configure: Re-generate.
232
2331999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
234
235 * mips.igen (ldl): Extend from _16_, not 32.
236
237Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
238
239 * interp.c (sim_store_register): Force registers written to by GDB
240 into an un-interpreted state.
241
c906108c
SS		 2421999-02-05 Frank Ch. Eigler <fche@cygnus.com>
243
244 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
245 CPU, start periodic background I/O polls.
246 (tx3904sio_poll): New function: periodic I/O poller.
247
2481998-12-30 Frank Ch. Eigler <fche@cygnus.com>
249
250 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
251
252Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
253
254 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
255 case statement.
256
2571998-12-29 Frank Ch. Eigler <fche@cygnus.com>
258
259 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
260 (load_word): Call SIM_CORE_SIGNAL hook on error.
261 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
262 starting. For exception dispatching, pass PC instead of NULL_CIA.
263 (decode_coproc): Use COP0_BADVADDR to store faulting address.
264 * sim-main.h (COP0_BADVADDR): Define.
265 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
266 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
267 (_sim_cpu): Add exc_* fields to store register value snapshots.
268 * mips.igen (*): Replace memory-related SignalException* calls
269 with references to SIM_CORE_SIGNAL hook.
270
271 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
272 fix.
273 * sim-main.c (*): Minor warning cleanups.
274
2751998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
276
277 * m16.igen (DADDIU5): Correct type-o.
278
279Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
280
281 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
282 variables.
283
284Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
285
286 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
287 to include path.
288 (interp.o): Add dependency on itable.h
289 (oengine.c, gencode): Delete remaining references.
290 (BUILT_SRC_FROM_GEN): Clean up.
291
2921998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
293
294 * vr4run.c: New.
295 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
296 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
297 tmp-run-hack) : New.
298 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
299 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
300 Drop the "64" qualifier to get the HACK generator working.
301 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
302 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
303 qualifier to get the hack generator working.
304 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
305 (DSLL): Use do_dsll.
306 (DSLLV): Use do_dsllv.
307 (DSRA): Use do_dsra.
308 (DSRL): Use do_dsrl.
309 (DSRLV): Use do_dsrlv.
310 (BC1): Move *vr4100 to get the HACK generator working.
311 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
312 get the HACK generator working.
313 (MACC) Rename to get the HACK generator working.
314 (DMACC,MACCS,DMACCS): Add the 64.
315
3161998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
317
318 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
319 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
320
3211998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
322
323 * mips/interp.c (DEBUG): Cleanups.
324
3251998-12-10 Frank Ch. Eigler <fche@cygnus.com>
326
327 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
328 (tx3904sio_tickle): fflush after a stdout character output.
329
3301998-12-03 Frank Ch. Eigler <fche@cygnus.com>
331
332 * interp.c (sim_close): Uninstall modules.
333
334Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
335
336 * sim-main.h, interp.c (sim_monitor): Change to global
337 function.
338
339Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
340
341 * configure.in (vr4100): Only include vr4100 instructions in
342 simulator.
343 * configure: Re-generate.
344 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
345
346Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
347
348 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
349 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
350 true alternative.
351
352 * configure.in (sim_default_gen, sim_use_gen): Replace with
353 sim_gen.
354 (--enable-sim-igen): Delete config option. Always using IGEN.
355 * configure: Re-generate.
356
357 * Makefile.in (gencode): Kill, kill, kill.
358 * gencode.c: Ditto.
359
360Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
361
362 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
363 bit mips16 igen simulator.
364 * configure: Re-generate.
365
366 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
367 as part of vr4100 ISA.
368 * vr.igen: Mark all instructions as 64 bit only.
369
370Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
371
372 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
373 Pacify GCC.
374
375Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
376
377 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
378 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
379 * configure: Re-generate.
380
381 * m16.igen (BREAK): Define breakpoint instruction.
382 (JALX32): Mark instruction as mips16 and not r3900.
383 * mips.igen (C.cond.fmt): Fix typo in instruction format.
384
385 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
386
387Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
388
389 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
390 insn as a debug breakpoint.
391
392 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
393 pending.slot_size.
394 (PENDING_SCHED): Clean up trace statement.
395 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
396 (PENDING_FILL): Delay write by only one cycle.
397 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
398
399 * sim-main.c (pending_tick): Clean up trace statements. Add trace
400 of pending writes.
401 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
402 32 & 64.
403 (pending_tick): Move incrementing of index to FOR statement.
404 (pending_tick): Only update PENDING_OUT after a write has occured.
405
406 * configure.in: Add explicit mips-lsi-* target. Use gencode to
407 build simulator.
408 * configure: Re-generate.
409
410 * interp.c (sim_engine_run OLD): Delete explicit call to
411 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
412
413Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
414
415 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
416 interrupt level number to match changed SignalExceptionInterrupt
417 macro.
418
419Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
420
421 * interp.c: #include "itable.h" if WITH_IGEN.
422 (get_insn_name): New function.
423 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
424 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
425
426Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
427
428 * configure: Rebuilt to inhale new common/aclocal.m4.
429
430Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
431
432 * dv-tx3904sio.c: Include sim-assert.h.
433
434Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
435
436 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
437 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
438 Reorganize target-specific sim-hardware checks.
439 * configure: rebuilt.
440 * interp.c (sim_open): For tx39 target boards, set
441 OPERATING_ENVIRONMENT, add tx3904sio devices.
442 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
443 ROM executables. Install dv-sockser into sim-modules list.
444
445 * dv-tx3904irc.c: Compiler warning clean-up.
446 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
447 frequent hw-trace messages.
448
449Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
450
451 * vr.igen (MulAcc): Identify as a vr4100 specific function.
452
453Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
454
455 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
456
457 * vr.igen: New file.
458 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
459 * mips.igen: Define vr4100 model. Include vr.igen.
460Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
461
462 * mips.igen (check_mf_hilo): Correct check.
463
464Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
465
466 * sim-main.h (interrupt_event): Add prototype.
467
468 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
469 register_ptr, register_value.
470 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
471
472 * sim-main.h (tracefh): Make extern.
473
474Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
475
476 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
477 Reduce unnecessarily high timer event frequency.
478 * dv-tx3904cpu.c: Ditto for interrupt event.
479
480Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
481
482 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
483 to allay warnings.
484 (interrupt_event): Made non-static.
485
486 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
487 interchange of configuration values for external vs. internal
488 clock dividers.
489
490Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
491
492 * mips.igen (BREAK): Moved code to here for
493 simulator-reserved break instructions.
494 * gencode.c (build_instruction): Ditto.
495 * interp.c (signal_exception): Code moved from here. Non-
496 reserved instructions now use exception vector, rather
497 than halting sim.
498 * sim-main.h: Moved magic constants to here.
499
500Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
501
502 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
503 register upon non-zero interrupt event level, clear upon zero
504 event value.
505 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
506 by passing zero event value.
507 (*_io_{read,write}_buffer): Endianness fixes.
508 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
509 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
510
511 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
512 serial I/O and timer module at base address 0xFFFF0000.
513
514Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
515
516 * mips.igen (SWC1) : Correct the handling of ReverseEndian
517 and BigEndianCPU.
518
519Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
520
521 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
522 parts.
523 * configure: Update.
524
525Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
526
527 * dv-tx3904tmr.c: New file - implements tx3904 timer.
528 * dv-tx3904{irc,cpu}.c: Mild reformatting.
529 * configure.in: Include tx3904tmr in hw_device list.
530 * configure: Rebuilt.
531 * interp.c (sim_open): Instantiate three timer instances.
532 Fix address typo of tx3904irc instance.
533
534Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
535
536 * interp.c (signal_exception): SystemCall exception now uses
537 the exception vector.
538
539Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
540
541 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
542 to allay warnings.
543
544Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
545
546 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
547
548Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
549
550 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
551
552 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
553 sim-main.h. Declare a struct hw_descriptor instead of struct
554 hw_device_descriptor.
555
556Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
557
558 * mips.igen (do_store_left, do_load_left): Compute nr of left and
559 right bits and then re-align left hand bytes to correct byte
560 lanes. Fix incorrect computation in do_store_left when loading
561 bytes from second word.
562
563Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
564
565 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
566 * interp.c (sim_open): Only create a device tree when HW is
567 enabled.
568
569 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
570 * interp.c (signal_exception): Ditto.
571
572Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
573
574 * gencode.c: Mark BEGEZALL as LIKELY.
575
576Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
577
578 * sim-main.h (ALU32_END): Sign extend 32 bit results.
579 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
580
581Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
582
583 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
584 modules. Recognize TX39 target with "mips*tx39" pattern.
585 * configure: Rebuilt.
586 * sim-main.h (*): Added many macros defining bits in
587 TX39 control registers.
588 (SignalInterrupt): Send actual PC instead of NULL.
589 (SignalNMIReset): New exception type.
590 * interp.c (board): New variable for future use to identify
591 a particular board being simulated.
592 (mips_option_handler,mips_options): Added "--board" option.
593 (interrupt_event): Send actual PC.
594 (sim_open): Make memory layout conditional on board setting.
595 (signal_exception): Initial implementation of hardware interrupt
596 handling. Accept another break instruction variant for simulator
597 exit.
598 (decode_coproc): Implement RFE instruction for TX39.
599 (mips.igen): Decode RFE instruction as such.
600 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
601 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
602 bbegin to implement memory map.
603 * dv-tx3904cpu.c: New file.
604 * dv-tx3904irc.c: New file.
605
606Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
607
608 * mips.igen (check_mt_hilo): Create a separate r3900 version.
609
610Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
611
612 * tx.igen (madd,maddu): Replace calls to check_op_hilo
613 with calls to check_div_hilo.
614
615Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
616
617 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
618 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
619 Add special r3900 version of do_mult_hilo.
620 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
621 with calls to check_mult_hilo.
622 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
623 with calls to check_div_hilo.
624
625Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
626
627 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
628 Document a replacement.
629
630Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
631
632 * interp.c (sim_monitor): Make mon_printf work.
633
634Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
635
636 * sim-main.h (INSN_NAME): New arg `cpu'.
637
638Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
639
640 * configure: Regenerated to track ../common/aclocal.m4 changes.
641
642Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
643
644 * configure: Regenerated to track ../common/aclocal.m4 changes.
645 * config.in: Ditto.
646
647Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
648
649 * acconfig.h: New file.
650 * configure.in: Reverted change of Apr 24; use sinclude again.
651
652Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
653
654 * configure: Regenerated to track ../common/aclocal.m4 changes.
655 * config.in: Ditto.
656
657Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
658
659 * configure.in: Don't call sinclude.
660
661Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
662
663 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
664
665Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
666
667 * mips.igen (ERET): Implement.
668
669 * interp.c (decode_coproc): Return sign-extended EPC.
670
671 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
672
673 * interp.c (signal_exception): Do not ignore Trap.
674 (signal_exception): On TRAP, restart at exception address.
675 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
676 (signal_exception): Update.
677 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
678 so that TRAP instructions are caught.
679
680Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
681
682 * sim-main.h (struct hilo_access, struct hilo_history): Define,
683 contains HI/LO access history.
684 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
685 (HIACCESS, LOACCESS): Delete, replace with
686 (HIHISTORY, LOHISTORY): New macros.
687 (CHECKHILO): Delete all, moved to mips.igen
688
689 * gencode.c (build_instruction): Do not generate checks for
690 correct HI/LO register usage.
691
692 * interp.c (old_engine_run): Delete checks for correct HI/LO
693 register usage.
694
695 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
696 check_mf_cycles): New functions.
697 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
698 do_divu, domultx, do_mult, do_multu): Use.
699
700 * tx.igen ("madd", "maddu"): Use.
701
702Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
703
704 * mips.igen (DSRAV): Use function do_dsrav.
705 (SRAV): Use new function do_srav.
706
707 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
708 (B): Sign extend 11 bit immediate.
709 (EXT-B*): Shift 16 bit immediate left by 1.
710 (ADDIU*): Don't sign extend immediate value.
711
712Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
713
714 * m16run.c (sim_engine_run): Restore CIA after handling an event.
715
716 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
717 functions.
718
719 * mips.igen (delayslot32, nullify_next_insn): New functions.
720 (m16.igen): Always include.
721 (do_*): Add more tracing.
722
723 * m16.igen (delayslot16): Add NIA argument, could be called by a
724 32 bit MIPS16 instruction.
725
726 * interp.c (ifetch16): Move function from here.
727 * sim-main.c (ifetch16): To here.
728
729 * sim-main.c (ifetch16, ifetch32): Update to match current
730 implementations of LH, LW.
731 (signal_exception): Don't print out incorrect hex value of illegal
732 instruction.
733
734Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
735
736 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
737 instruction.
738
739 * m16.igen: Implement MIPS16 instructions.
740
741 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
742 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
743 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
744 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
745 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
746 bodies of corresponding code from 32 bit insn to these. Also used
747 by MIPS16 versions of functions.
748
749 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
750 (IMEM16): Drop NR argument from macro.
751
752Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
753
754 * Makefile.in (SIM_OBJS): Add sim-main.o.
755
756 * sim-main.h (address_translation, load_memory, store_memory,
757 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
758 as INLINE_SIM_MAIN.
759 (pr_addr, pr_uword64): Declare.
760 (sim-main.c): Include when H_REVEALS_MODULE_P.
761
762 * interp.c (address_translation, load_memory, store_memory,
763 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
764 from here.
765 * sim-main.c: To here. Fix compilation problems.
766
767 * configure.in: Enable inlining.
768 * configure: Re-config.
769
770Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
771
772 * configure: Regenerated to track ../common/aclocal.m4 changes.
773
774Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
775
776 * mips.igen: Include tx.igen.
777 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
778 * tx.igen: New file, contains MADD and MADDU.
779
780 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
781 the hardwired constant `7'.
782 (store_memory): Ditto.
783 (LOADDRMASK): Move definition to sim-main.h.
784
785 mips.igen (MTC0): Enable for r3900.
786 (ADDU): Add trace.
787
788 mips.igen (do_load_byte): Delete.
789 (do_load, do_store, do_load_left, do_load_write, do_store_left,
790 do_store_right): New functions.
791 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
792
793 configure.in: Let the tx39 use igen again.
794 configure: Update.
795
796Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
797
798 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
799 not an address sized quantity. Return zero for cache sizes.
800
801Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
802
803 * mips.igen (r3900): r3900 does not support 64 bit integer
804 operations.
805
806Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
807
808 * configure.in (mipstx39*-*-*): Use gencode simulator rather
809 than igen one.
810 * configure : Rebuild.
811
812Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
813
814 * configure: Regenerated to track ../common/aclocal.m4 changes.
815
816Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
817
818 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
819
820Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
821
822 * configure: Regenerated to track ../common/aclocal.m4 changes.
823 * config.in: Regenerated to track ../common/aclocal.m4 changes.
824
825Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
826
827 * configure: Regenerated to track ../common/aclocal.m4 changes.
828
829Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
830
831 * interp.c (Max, Min): Comment out functions. Not yet used.
832
833Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
834
835 * configure: Regenerated to track ../common/aclocal.m4 changes.
836
837Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
838
839 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
840 configurable settings for stand-alone simulator.
841
842 * configure.in: Added X11 search, just in case.
843
844 * configure: Regenerated.
845
846Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
847
848 * interp.c (sim_write, sim_read, load_memory, store_memory):
849 Replace sim_core_*_map with read_map, write_map, exec_map resp.
850
851Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
852
853 * sim-main.h (GETFCC): Return an unsigned value.
854
855Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
856
857 * mips.igen (DIV): Fix check for -1 / MIN_INT.
858 (DADD): Result destination is RD not RT.
859
860Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
861
862 * sim-main.h (HIACCESS, LOACCESS): Always define.
863
864 * mdmx.igen (Maxi, Mini): Rename Max, Min.
865
866 * interp.c (sim_info): Delete.
867
868Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
869
870 * interp.c (DECLARE_OPTION_HANDLER): Use it.
871 (mips_option_handler): New argument `cpu'.
872 (sim_open): Update call to sim_add_option_table.
873
874Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
875
876 * mips.igen (CxC1): Add tracing.
877
878Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
879
880 * sim-main.h (Max, Min): Declare.
881
882 * interp.c (Max, Min): New functions.
883
884 * mips.igen (BC1): Add tracing.
885
886Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
887
888 * interp.c Added memory map for stack in vr4100
889
890Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
891
892 * interp.c (load_memory): Add missing "break"'s.
893
894Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
895
896 * interp.c (sim_store_register, sim_fetch_register): Pass in
897 length parameter. Return -1.
898
899Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
900
901 * interp.c: Added hardware init hook, fixed warnings.
902
903Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
904
905 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
906
907Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
908
909 * interp.c (ifetch16): New function.
910
911 * sim-main.h (IMEM32): Rename IMEM.
912 (IMEM16_IMMED): Define.
913 (IMEM16): Define.
914 (DELAY_SLOT): Update.
915
916 * m16run.c (sim_engine_run): New file.
917
918 * m16.igen: All instructions except LB.
919 (LB): Call do_load_byte.
920 * mips.igen (do_load_byte): New function.
921 (LB): Call do_load_byte.
922
923 * mips.igen: Move spec for insn bit size and high bit from here.
924 * Makefile.in (tmp-igen, tmp-m16): To here.
925
926 * m16.dc: New file, decode mips16 instructions.
927
928 * Makefile.in (SIM_NO_ALL): Define.
929 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
930
931Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
932
933 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
934 point unit to 32 bit registers.
935 * configure: Re-generate.
936
937Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
938
939 * configure.in (sim_use_gen): Make IGEN the default simulator
940 generator for generic 32 and 64 bit mips targets.
941 * configure: Re-generate.
942
943Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
944
945 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
946 bitsize.
947
948 * interp.c (sim_fetch_register, sim_store_register): Read/write
949 FGR from correct location.
950 (sim_open): Set size of FGR's according to
951 WITH_TARGET_FLOATING_POINT_BITSIZE.
952
953 * sim-main.h (FGR): Store floating point registers in a separate
954 array.
955
956Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
957
958 * configure: Regenerated to track ../common/aclocal.m4 changes.
959
960Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
961
962 * interp.c (ColdReset): Call PENDING_INVALIDATE.
963
964 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
965
966 * interp.c (pending_tick): New function. Deliver pending writes.
967
968 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
969 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
970 it can handle mixed sized quantites and single bits.
971
972Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
973
974 * interp.c (oengine.h): Do not include when building with IGEN.
975 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
976 (sim_info): Ditto for PROCESSOR_64BIT.
977 (sim_monitor): Replace ut_reg with unsigned_word.
978 (*): Ditto for t_reg.
979 (LOADDRMASK): Define.
980 (sim_open): Remove defunct check that host FP is IEEE compliant,
981 using software to emulate floating point.
982 (value_fpr, ...): Always compile, was conditional on HASFPU.
983
984Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
985
986 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
987 size.
988
989 * interp.c (SD, CPU): Define.
990 (mips_option_handler): Set flags in each CPU.
991 (interrupt_event): Assume CPU 0 is the one being iterrupted.
992 (sim_close): Do not clear STATE, deleted anyway.
993 (sim_write, sim_read): Assume CPU zero's vm should be used for
994 data transfers.
995 (sim_create_inferior): Set the PC for all processors.
996 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
997 argument.
998 (mips16_entry): Pass correct nr of args to store_word, load_word.
999 (ColdReset): Cold reset all cpu's.
1000 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1001 (sim_monitor, load_memory, store_memory, signal_exception): Use
1002 `CPU' instead of STATE_CPU.
1003
1004
1005 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1006 SD or CPU_.
1007
1008 * sim-main.h (signal_exception): Add sim_cpu arg.
1009 (SignalException*): Pass both SD and CPU to signal_exception.
1010 * interp.c (signal_exception): Update.
1011
1012 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1013 Ditto
1014 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1015 address_translation): Ditto
1016 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1017
1018Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1019
1020 * configure: Regenerated to track ../common/aclocal.m4 changes.
1021
1022Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1023
1024 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1025
1026 * mips.igen (model): Map processor names onto BFD name.
1027
1028 * sim-main.h (CPU_CIA): Delete.
1029 (SET_CIA, GET_CIA): Define
1030
1031Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1032
1033 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1034 regiser.
1035
1036 * configure.in (default_endian): Configure a big-endian simulator
1037 by default.
1038 * configure: Re-generate.
1039
1040Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1041
1042 * configure: Regenerated to track ../common/aclocal.m4 changes.
1043
1044Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1045
1046 * interp.c (sim_monitor): Handle Densan monitor outbyte
1047 and inbyte functions.
1048
10491997-12-29 Felix Lee <flee@cygnus.com>
1050
1051 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1052
1053Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1054
1055 * Makefile.in (tmp-igen): Arrange for $zero to always be
1056 reset to zero after every instruction.
1057
1058Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1059
1060 * configure: Regenerated to track ../common/aclocal.m4 changes.
1061 * config.in: Ditto.
1062
1063Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1064
1065 * mips.igen (MSUB): Fix to work like MADD.
1066 * gencode.c (MSUB): Similarly.
1067
1068Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1069
1070 * configure: Regenerated to track ../common/aclocal.m4 changes.
1071
1072Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1073
1074 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1075
1076Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1077
1078 * sim-main.h (sim-fpu.h): Include.
1079
1080 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1081 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1082 using host independant sim_fpu module.
1083
1084Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1085
1086 * interp.c (signal_exception): Report internal errors with SIGABRT
1087 not SIGQUIT.
1088
1089 * sim-main.h (C0_CONFIG): New register.
1090 (signal.h): No longer include.
1091
1092 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1093
1094Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1095
1096 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1097
1098Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1099
1100 * mips.igen: Tag vr5000 instructions.
1101 (ANDI): Was missing mipsIV model, fix assembler syntax.
1102 (do_c_cond_fmt): New function.
1103 (C.cond.fmt): Handle mips I-III which do not support CC field
1104 separatly.
1105 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1106 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1107 in IV3.2 spec.
1108 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1109 vr5000 which saves LO in a GPR separatly.
1110
1111 * configure.in (enable-sim-igen): For vr5000, select vr5000
1112 specific instructions.
1113 * configure: Re-generate.
1114
1115Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1116
1117 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1118
1119 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1120 fmt_uninterpreted_64 bit cases to switch. Convert to
1121 fmt_formatted,
1122
1123 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1124
1125 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1126 as specified in IV3.2 spec.
1127 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1128
1129Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1130
1131 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1132 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1133 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1134 PENDING_FILL versions of instructions. Simplify.
1135 (X): New function.
1136 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1137 instructions.
1138 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1139 a signed value.
1140 (MTHI, MFHI): Disable code checking HI-LO.
1141
1142 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1143 global.
1144 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1145
1146Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1147
1148 * gencode.c (build_mips16_operands): Replace IPC with cia.
1149
1150 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1151 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1152 IPC to `cia'.
1153 (UndefinedResult): Replace function with macro/function
1154 combination.
1155 (sim_engine_run): Don't save PC in IPC.
1156
1157 * sim-main.h (IPC): Delete.
1158
1159
1160 * interp.c (signal_exception, store_word, load_word,
1161 address_translation, load_memory, store_memory, cache_op,
1162 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1163 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1164 current instruction address - cia - argument.
1165 (sim_read, sim_write): Call address_translation directly.
1166 (sim_engine_run): Rename variable vaddr to cia.
1167 (signal_exception): Pass cia to sim_monitor
1168
1169 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1170 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1171 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1172
1173 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1174 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1175 SIM_ASSERT.
1176
1177 * interp.c (signal_exception): Pass restart address to
1178 sim_engine_restart.
1179
1180 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1181 idecode.o): Add dependency.
1182
1183 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1184 Delete definitions
1185 (DELAY_SLOT): Update NIA not PC with branch address.
1186 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1187
1188 * mips.igen: Use CIA not PC in branch calculations.
1189 (illegal): Call SignalException.
1190 (BEQ, ADDIU): Fix assembler.
1191
1192Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1193
1194 * m16.igen (JALX): Was missing.
1195
1196 * configure.in (enable-sim-igen): New configuration option.
1197 * configure: Re-generate.
1198
1199 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1200
1201 * interp.c (load_memory, store_memory): Delete parameter RAW.
1202 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1203 bypassing {load,store}_memory.
1204
1205 * sim-main.h (ByteSwapMem): Delete definition.
1206
1207 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1208
1209 * interp.c (sim_do_command, sim_commands): Delete mips specific
1210 commands. Handled by module sim-options.
1211
1212 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1213 (WITH_MODULO_MEMORY): Define.
1214
1215 * interp.c (sim_info): Delete code printing memory size.
1216
1217 * interp.c (mips_size): Nee sim_size, delete function.
1218 (power2): Delete.
1219 (monitor, monitor_base, monitor_size): Delete global variables.
1220 (sim_open, sim_close): Delete code creating monitor and other
1221 memory regions. Use sim-memopts module, via sim_do_commandf, to
1222 manage memory regions.
1223 (load_memory, store_memory): Use sim-core for memory model.
1224
1225 * interp.c (address_translation): Delete all memory map code
1226 except line forcing 32 bit addresses.
1227
1228Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1229
1230 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1231 trace options.
1232
1233 * interp.c (logfh, logfile): Delete globals.
1234 (sim_open, sim_close): Delete code opening & closing log file.
1235 (mips_option_handler): Delete -l and -n options.
1236 (OPTION mips_options): Ditto.
1237
1238 * interp.c (OPTION mips_options): Rename option trace to dinero.
1239 (mips_option_handler): Update.
1240
1241Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1242
1243 * interp.c (fetch_str): New function.
1244 (sim_monitor): Rewrite using sim_read & sim_write.
1245 (sim_open): Check magic number.
1246 (sim_open): Write monitor vectors into memory using sim_write.
1247 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1248 (sim_read, sim_write): Simplify - transfer data one byte at a
1249 time.
1250 (load_memory, store_memory): Clarify meaning of parameter RAW.
1251
1252 * sim-main.h (isHOST): Defete definition.
1253 (isTARGET): Mark as depreciated.
1254 (address_translation): Delete parameter HOST.
1255
1256 * interp.c (address_translation): Delete parameter HOST.
1257
1258Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1259
1260 * mips.igen:
1261
1262 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1263 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1264
1265Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1266
1267 * mips.igen: Add model filter field to records.
1268
1269Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1270
1271 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1272
1273 interp.c (sim_engine_run): Do not compile function sim_engine_run
1274 when WITH_IGEN == 1.
1275
1276 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1277 target architecture.
1278
1279 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1280 igen. Replace with configuration variables sim_igen_flags /
1281 sim_m16_flags.
1282
1283 * m16.igen: New file. Copy mips16 insns here.
1284 * mips.igen: From here.
1285
1286Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1287
1288 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1289 to top.
1290 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1291
1292Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1293
1294 * gencode.c (build_instruction): Follow sim_write's lead in using
1295 BigEndianMem instead of !ByteSwapMem.
1296
1297Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1298
1299 * configure.in (sim_gen): Dependent on target, select type of
1300 generator. Always select old style generator.
1301
1302 configure: Re-generate.
1303
1304 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1305 targets.
1306 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1307 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1308 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1309 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1310 SIM_@sim_gen@_*, set by autoconf.
1311
1312Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1313
1314 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1315
1316 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1317 CURRENT_FLOATING_POINT instead.
1318
1319 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1320 (address_translation): Raise exception InstructionFetch when
1321 translation fails and isINSTRUCTION.
1322
1323 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1324 sim_engine_run): Change type of of vaddr and paddr to
1325 address_word.
1326 (address_translation, prefetch, load_memory, store_memory,
1327 cache_op): Change type of vAddr and pAddr to address_word.
1328
1329 * gencode.c (build_instruction): Change type of vaddr and paddr to
1330 address_word.
1331
1332Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1333
1334 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1335 macro to obtain result of ALU op.
1336
1337Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1338
1339 * interp.c (sim_info): Call profile_print.
1340
1341Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1342
1343 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1344
1345 * sim-main.h (WITH_PROFILE): Do not define, defined in
1346 common/sim-config.h. Use sim-profile module.
1347 (simPROFILE): Delete defintion.
1348
1349 * interp.c (PROFILE): Delete definition.
1350 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1351 (sim_close): Delete code writing profile histogram.
1352 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1353 Delete.
1354 (sim_engine_run): Delete code profiling the PC.
1355
1356Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1357
1358 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1359
1360 * interp.c (sim_monitor): Make register pointers of type
1361 unsigned_word*.
1362
1363 * sim-main.h: Make registers of type unsigned_word not
1364 signed_word.
1365
1366Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1367
1368 * interp.c (sync_operation): Rename from SyncOperation, make
1369 global, add SD argument.
1370 (prefetch): Rename from Prefetch, make global, add SD argument.
1371 (decode_coproc): Make global.
1372
1373 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1374
1375 * gencode.c (build_instruction): Generate DecodeCoproc not
1376 decode_coproc calls.
1377
1378 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1379 (SizeFGR): Move to sim-main.h
1380 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1381 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1382 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1383 sim-main.h.
1384 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1385 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1386 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1387 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1388 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1389 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1390
1391 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1392 exception.
1393 (sim-alu.h): Include.
1394 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1395 (sim_cia): Typedef to instruction_address.
1396
1397Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1398
1399 * Makefile.in (interp.o): Rename generated file engine.c to
1400 oengine.c.
1401
1402 * interp.c: Update.
1403
1404Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1405
1406 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1407
1408Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1409
1410 * gencode.c (build_instruction): For "FPSQRT", output correct
1411 number of arguments to Recip.
1412
1413Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1414
1415 * Makefile.in (interp.o): Depends on sim-main.h
1416
1417 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1418
1419 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1420 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1421 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1422 STATE, DSSTATE): Define
1423 (GPR, FGRIDX, ..): Define.
1424
1425 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1426 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1427 (GPR, FGRIDX, ...): Delete macros.
1428
1429 * interp.c: Update names to match defines from sim-main.h
1430
1431Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1432
1433 * interp.c (sim_monitor): Add SD argument.
1434 (sim_warning): Delete. Replace calls with calls to
1435 sim_io_eprintf.
1436 (sim_error): Delete. Replace calls with sim_io_error.
1437 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1438 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1439 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1440 argument.
1441 (mips_size): Rename from sim_size. Add SD argument.
1442
1443 * interp.c (simulator): Delete global variable.
1444 (callback): Delete global variable.
1445 (mips_option_handler, sim_open, sim_write, sim_read,
1446 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1447 sim_size,sim_monitor): Use sim_io_* not callback->*.
1448 (sim_open): ZALLOC simulator struct.
1449 (PROFILE): Do not define.
1450
1451Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1452
1453 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1454 support.h with corresponding code.
1455
1456 * sim-main.h (word64, uword64), support.h: Move definition to
1457 sim-main.h.
1458 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1459
1460 * support.h: Delete
1461 * Makefile.in: Update dependencies
1462 * interp.c: Do not include.
1463
1464Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1465
1466 * interp.c (address_translation, load_memory, store_memory,
1467 cache_op): Rename to from AddressTranslation et.al., make global,
1468 add SD argument
1469
1470 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1471 CacheOp): Define.
1472
1473 * interp.c (SignalException): Rename to signal_exception, make
1474 global.
1475
1476 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1477
1478 * sim-main.h (SignalException, SignalExceptionInterrupt,
1479 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1480 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1481 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1482 Define.
1483
1484 * interp.c, support.h: Use.
1485
1486Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1487
1488 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1489 to value_fpr / store_fpr. Add SD argument.
1490 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1491 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1492
1493 * sim-main.h (ValueFPR, StoreFPR): Define.
1494
1495Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1496
1497 * interp.c (sim_engine_run): Check consistency between configure
1498 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1499 and HASFPU.
1500
1501 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1502 (mips_fpu): Configure WITH_FLOATING_POINT.
1503 (mips_endian): Configure WITH_TARGET_ENDIAN.
1504 * configure: Update.
1505
1506Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1507
1508 * configure: Regenerated to track ../common/aclocal.m4 changes.
1509
1510Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1511
1512 * configure: Regenerated.
1513
1514Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1515
1516 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1517
1518Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1519
1520 * gencode.c (print_igen_insn_models): Assume certain architectures
1521 include all mips* instructions.
1522 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1523 instruction.
1524
1525 * Makefile.in (tmp.igen): Add target. Generate igen input from
1526 gencode file.
1527
1528 * gencode.c (FEATURE_IGEN): Define.
1529 (main): Add --igen option. Generate output in igen format.
1530 (process_instructions): Format output according to igen option.
1531 (print_igen_insn_format): New function.
1532 (print_igen_insn_models): New function.
1533 (process_instructions): Only issue warnings and ignore
1534 instructions when no FEATURE_IGEN.
1535
1536Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1537
1538 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1539 MIPS targets.
1540
1541Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1542
1543 * configure: Regenerated to track ../common/aclocal.m4 changes.
1544
1545Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1546
1547 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1548 SIM_RESERVED_BITS): Delete, moved to common.
1549 (SIM_EXTRA_CFLAGS): Update.
1550
1551Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1552
1553 * configure.in: Configure non-strict memory alignment.
1554 * configure: Regenerated to track ../common/aclocal.m4 changes.
1555
1556Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1557
1558 * configure: Regenerated to track ../common/aclocal.m4 changes.
1559
1560Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1561
1562 * gencode.c (SDBBP,DERET): Added (3900) insns.
1563 (RFE): Turn on for 3900.
1564 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1565 (dsstate): Made global.
1566 (SUBTARGET_R3900): Added.
1567 (CANCELDELAYSLOT): New.
1568 (SignalException): Ignore SystemCall rather than ignore and
1569 terminate. Add DebugBreakPoint handling.
1570 (decode_coproc): New insns RFE, DERET; and new registers Debug
1571 and DEPC protected by SUBTARGET_R3900.
1572 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1573 bits explicitly.
1574 * Makefile.in,configure.in: Add mips subtarget option.
1575 * configure: Update.
1576
1577Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1578
1579 * gencode.c: Add r3900 (tx39).
1580
1581
1582Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1583
1584 * gencode.c (build_instruction): Don't need to subtract 4 for
1585 JALR, just 2.
1586
1587Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1588
1589 * interp.c: Correct some HASFPU problems.
1590
1591Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1592
1593 * configure: Regenerated to track ../common/aclocal.m4 changes.
1594
1595Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1596
1597 * interp.c (mips_options): Fix samples option short form, should
1598 be `x'.
1599
1600Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1601
1602 * interp.c (sim_info): Enable info code. Was just returning.
1603
1604Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1605
1606 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1607 MFC0.
1608
1609Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1610
1611 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1612 constants.
1613 (build_instruction): Ditto for LL.
1614
1615Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1616
1617 * configure: Regenerated to track ../common/aclocal.m4 changes.
1618
1619Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1620
1621 * configure: Regenerated to track ../common/aclocal.m4 changes.
1622 * config.in: Ditto.
1623
1624Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1625
1626 * interp.c (sim_open): Add call to sim_analyze_program, update
1627 call to sim_config.
1628
1629Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1630
1631 * interp.c (sim_kill): Delete.
1632 (sim_create_inferior): Add ABFD argument. Set PC from same.
1633 (sim_load): Move code initializing trap handlers from here.
1634 (sim_open): To here.
1635 (sim_load): Delete, use sim-hload.c.
1636
1637 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1638
1639Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1640
1641 * configure: Regenerated to track ../common/aclocal.m4 changes.
1642 * config.in: Ditto.
1643
1644Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1645
1646 * interp.c (sim_open): Add ABFD argument.
1647 (sim_load): Move call to sim_config from here.
1648 (sim_open): To here. Check return status.
1649
1650Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1651
1652 * gencode.c (build_instruction): Two arg MADD should
1653 not assign result to $0.
1654
1655Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1656
1657 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1658 * sim/mips/configure.in: Regenerate.
1659
1660Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1661
1662 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1663 signed8, unsigned8 et.al. types.
1664
1665 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1666 hosts when selecting subreg.
1667
1668Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1669
1670 * interp.c (sim_engine_run): Reset the ZERO register to zero
1671 regardless of FEATURE_WARN_ZERO.
1672 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1673
1674Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1675
1676 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1677 (SignalException): For BreakPoints ignore any mode bits and just
1678 save the PC.
1679 (SignalException): Always set the CAUSE register.
1680
1681Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1682
1683 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1684 exception has been taken.
1685
1686 * interp.c: Implement the ERET and mt/f sr instructions.
1687
1688Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1689
1690 * interp.c (SignalException): Don't bother restarting an
1691 interrupt.
1692
1693Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1694
1695 * interp.c (SignalException): Really take an interrupt.
1696 (interrupt_event): Only deliver interrupts when enabled.
1697
1698Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1699
1700 * interp.c (sim_info): Only print info when verbose.
1701 (sim_info) Use sim_io_printf for output.
1702
1703Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1704
1705 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1706 mips architectures.
1707
1708Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1709
1710 * interp.c (sim_do_command): Check for common commands if a
1711 simulator specific command fails.
1712
1713Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1714
1715 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1716 and simBE when DEBUG is defined.
1717
1718Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1719
1720 * interp.c (interrupt_event): New function. Pass exception event
1721 onto exception handler.
1722
1723 * configure.in: Check for stdlib.h.
1724 * configure: Regenerate.
1725
1726 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1727 variable declaration.
1728 (build_instruction): Initialize memval1.
1729 (build_instruction): Add UNUSED attribute to byte, bigend,
1730 reverse.
1731 (build_operands): Ditto.
1732
1733 * interp.c: Fix GCC warnings.
1734 (sim_get_quit_code): Delete.
1735
1736 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1737 * Makefile.in: Ditto.
1738 * configure: Re-generate.
1739
1740 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1741
1742Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1743
1744 * interp.c (mips_option_handler): New function parse argumes using
1745 sim-options.
1746 (myname): Replace with STATE_MY_NAME.
1747 (sim_open): Delete check for host endianness - performed by
1748 sim_config.
1749 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1750 (sim_open): Move much of the initialization from here.
1751 (sim_load): To here. After the image has been loaded and
1752 endianness set.
1753 (sim_open): Move ColdReset from here.
1754 (sim_create_inferior): To here.
1755 (sim_open): Make FP check less dependant on host endianness.
1756
1757 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1758 run.
1759 * interp.c (sim_set_callbacks): Delete.
1760
1761 * interp.c (membank, membank_base, membank_size): Replace with
1762 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1763 (sim_open): Remove call to callback->init. gdb/run do this.
1764
1765 * interp.c: Update
1766
1767 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1768
1769 * interp.c (big_endian_p): Delete, replaced by
1770 current_target_byte_order.
1771
1772Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1773
1774 * interp.c (host_read_long, host_read_word, host_swap_word,
1775 host_swap_long): Delete. Using common sim-endian.
1776 (sim_fetch_register, sim_store_register): Use H2T.
1777 (pipeline_ticks): Delete. Handled by sim-events.
1778 (sim_info): Update.
1779 (sim_engine_run): Update.
1780
1781Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1782
1783 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1784 reason from here.
1785 (SignalException): To here. Signal using sim_engine_halt.
1786 (sim_stop_reason): Delete, moved to common.
1787
1788Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1789
1790 * interp.c (sim_open): Add callback argument.
1791 (sim_set_callbacks): Delete SIM_DESC argument.
1792 (sim_size): Ditto.
1793
1794Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1795
1796 * Makefile.in (SIM_OBJS): Add common modules.
1797
1798 * interp.c (sim_set_callbacks): Also set SD callback.
1799 (set_endianness, xfer_*, swap_*): Delete.
1800 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1801 Change to functions using sim-endian macros.
1802 (control_c, sim_stop): Delete, use common version.
1803 (simulate): Convert into.
1804 (sim_engine_run): This function.
1805 (sim_resume): Delete.
1806
1807 * interp.c (simulation): New variable - the simulator object.
1808 (sim_kind): Delete global - merged into simulation.
1809 (sim_load): Cleanup. Move PC assignment from here.
1810 (sim_create_inferior): To here.
1811
1812 * sim-main.h: New file.
1813 * interp.c (sim-main.h): Include.
1814
1815Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1816
1817 * configure: Regenerated to track ../common/aclocal.m4 changes.
1818
1819Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1820
1821 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1822
1823Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1824
1825 * gencode.c (build_instruction): DIV instructions: check
1826 for division by zero and integer overflow before using
1827 host's division operation.
1828
1829Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1830
1831 * Makefile.in (SIM_OBJS): Add sim-load.o.
1832 * interp.c: #include bfd.h.
1833 (target_byte_order): Delete.
1834 (sim_kind, myname, big_endian_p): New static locals.
1835 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1836 after argument parsing. Recognize -E arg, set endianness accordingly.
1837 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1838 load file into simulator. Set PC from bfd.
1839 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1840 (set_endianness): Use big_endian_p instead of target_byte_order.
1841
1842Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1843
1844 * interp.c (sim_size): Delete prototype - conflicts with
1845 definition in remote-sim.h. Correct definition.
1846
1847Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1848
1849 * configure: Regenerated to track ../common/aclocal.m4 changes.
1850 * config.in: Ditto.
1851
1852Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1853
1854 * interp.c (sim_open): New arg `kind'.
1855
1856 * configure: Regenerated to track ../common/aclocal.m4 changes.
1857
1858Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1859
1860 * configure: Regenerated to track ../common/aclocal.m4 changes.
1861
1862Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1863
1864 * interp.c (sim_open): Set optind to 0 before calling getopt.
1865
1866Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1867
1868 * configure: Regenerated to track ../common/aclocal.m4 changes.
1869
1870Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1871
1872 * interp.c : Replace uses of pr_addr with pr_uword64
1873 where the bit length is always 64 independent of SIM_ADDR.
1874 (pr_uword64) : added.
1875
1876Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1877
1878 * configure: Re-generate.
1879
1880Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1881
1882 * configure: Regenerate to track ../common/aclocal.m4 changes.
1883
1884Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1885
1886 * interp.c (sim_open): New SIM_DESC result. Argument is now
1887 in argv form.
1888 (other sim_*): New SIM_DESC argument.
1889
1890Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1891
1892 * interp.c: Fix printing of addresses for non-64-bit targets.
1893 (pr_addr): Add function to print address based on size.
1894
1895Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1896
1897 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1898
1899Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1900
1901 * gencode.c (build_mips16_operands): Correct computation of base
1902 address for extended PC relative instruction.
1903
1904Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1905
1906 * interp.c (mips16_entry): Add support for floating point cases.
1907 (SignalException): Pass floating point cases to mips16_entry.
1908 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1909 registers.
1910 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1911 or fmt_word.
1912 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1913 and then set the state to fmt_uninterpreted.
1914 (COP_SW): Temporarily set the state to fmt_word while calling
1915 ValueFPR.
1916
1917Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1918
1919 * gencode.c (build_instruction): The high order may be set in the
1920 comparison flags at any ISA level, not just ISA 4.
1921
1922Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1923
1924 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1925 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1926 * configure.in: sinclude ../common/aclocal.m4.
1927 * configure: Regenerated.
1928
1929Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1930
1931 * configure: Rebuild after change to aclocal.m4.
1932
1933Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1934
1935 * configure configure.in Makefile.in: Update to new configure
1936 scheme which is more compatible with WinGDB builds.
1937 * configure.in: Improve comment on how to run autoconf.
1938 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1939 * Makefile.in: Use autoconf substitution to install common
1940 makefile fragment.
1941
1942Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1943
1944 * gencode.c (build_instruction): Use BigEndianCPU instead of
1945 ByteSwapMem.
1946
1947Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1948
1949 * interp.c (sim_monitor): Make output to stdout visible in
1950 wingdb's I/O log window.
1951
1952Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1953
1954 * support.h: Undo previous change to SIGTRAP
1955 and SIGQUIT values.
1956
1957Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1958
1959 * interp.c (store_word, load_word): New static functions.
1960 (mips16_entry): New static function.
1961 (SignalException): Look for mips16 entry and exit instructions.
1962 (simulate): Use the correct index when setting fpr_state after
1963 doing a pending move.
1964
1965Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1966
1967 * interp.c: Fix byte-swapping code throughout to work on
1968 both little- and big-endian hosts.
1969
1970Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1971
1972 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1973 with gdb/config/i386/xm-windows.h.
1974
1975Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1976
1977 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1978 that messes up arithmetic shifts.
1979
1980Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1981
1982 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1983 SIGTRAP and SIGQUIT for _WIN32.
1984
1985Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1986
1987 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1988 force a 64 bit multiplication.
1989 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1990 destination register is 0, since that is the default mips16 nop
1991 instruction.
1992
1993Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1994
1995 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1996 (build_endian_shift): Don't check proc64.
1997 (build_instruction): Always set memval to uword64. Cast op2 to
1998 uword64 when shifting it left in memory instructions. Always use
1999 the same code for stores--don't special case proc64.
2000
2001 * gencode.c (build_mips16_operands): Fix base PC value for PC
2002 relative operands.
2003 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2004 jal instruction.
2005 * interp.c (simJALDELAYSLOT): Define.
2006 (JALDELAYSLOT): Define.
2007 (INDELAYSLOT, INJALDELAYSLOT): Define.
2008 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2009
2010Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2011
2012 * interp.c (sim_open): add flush_cache as a PMON routine
2013 (sim_monitor): handle flush_cache by ignoring it
2014
2015Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2016
2017 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2018 BigEndianMem.
2019 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2020 (BigEndianMem): Rename to ByteSwapMem and change sense.
2021 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2022 BigEndianMem references to !ByteSwapMem.
2023 (set_endianness): New function, with prototype.
2024 (sim_open): Call set_endianness.
2025 (sim_info): Use simBE instead of BigEndianMem.
2026 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2027 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2028 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2029 ifdefs, keeping the prototype declaration.
2030 (swap_word): Rewrite correctly.
2031 (ColdReset): Delete references to CONFIG. Delete endianness related
2032 code; moved to set_endianness.
2033
2034Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2035
2036 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2037 * interp.c (CHECKHILO): Define away.
2038 (simSIGINT): New macro.
2039 (membank_size): Increase from 1MB to 2MB.
2040 (control_c): New function.
2041 (sim_resume): Rename parameter signal to signal_number. Add local
2042 variable prev. Call signal before and after simulate.
2043 (sim_stop_reason): Add simSIGINT support.
2044 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2045 functions always.
2046 (sim_warning): Delete call to SignalException. Do call printf_filtered
2047 if logfh is NULL.
2048 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2049 a call to sim_warning.
2050
2051Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2052
2053 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2054 16 bit instructions.
2055
2056Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2057
2058 Add support for mips16 (16 bit MIPS implementation):
2059 * gencode.c (inst_type): Add mips16 instruction encoding types.
2060 (GETDATASIZEINSN): Define.
2061 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2062 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2063 mtlo.
2064 (MIPS16_DECODE): New table, for mips16 instructions.
2065 (bitmap_val): New static function.
2066 (struct mips16_op): Define.
2067 (mips16_op_table): New table, for mips16 operands.
2068 (build_mips16_operands): New static function.
2069 (process_instructions): If PC is odd, decode a mips16
2070 instruction. Break out instruction handling into new
2071 build_instruction function.
2072 (build_instruction): New static function, broken out of
2073 process_instructions. Check modifiers rather than flags for SHIFT
2074 bit count and m[ft]{hi,lo} direction.
2075 (usage): Pass program name to fprintf.
2076 (main): Remove unused variable this_option_optind. Change
2077 ``*loptarg++'' to ``loptarg++''.
2078 (my_strtoul): Parenthesize && within ||.
2079 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2080 (simulate): If PC is odd, fetch a 16 bit instruction, and
2081 increment PC by 2 rather than 4.
2082 * configure.in: Add case for mips16*-*-*.
2083 * configure: Rebuild.
2084
2085Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2086
2087 * interp.c: Allow -t to enable tracing in standalone simulator.
2088 Fix garbage output in trace file and error messages.
2089
2090Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2091
2092 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2093 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2094 * configure.in: Simplify using macros in ../common/aclocal.m4.
2095 * configure: Regenerated.
2096 * tconfig.in: New file.
2097
2098Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2099
2100 * interp.c: Fix bugs in 64-bit port.
2101 Use ansi function declarations for msvc compiler.
2102 Initialize and test file pointer in trace code.
2103 Prevent duplicate definition of LAST_EMED_REGNUM.
2104
2105Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2106
2107 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2108
2109Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2110
2111 * interp.c (SignalException): Check for explicit terminating
2112 breakpoint value.
2113 * gencode.c: Pass instruction value through SignalException()
2114 calls for Trap, Breakpoint and Syscall.
2115
2116Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2117
2118 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2119 only used on those hosts that provide it.
2120 * configure.in: Add sqrt() to list of functions to be checked for.
2121 * config.in: Re-generated.
2122 * configure: Re-generated.
2123
2124Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2125
2126 * gencode.c (process_instructions): Call build_endian_shift when
2127 expanding STORE RIGHT, to fix swr.
2128 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2129 clear the high bits.
2130 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2131 Fix float to int conversions to produce signed values.
2132
2133Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2134
2135 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2136 (process_instructions): Correct handling of nor instruction.
2137 Correct shift count for 32 bit shift instructions. Correct sign
2138 extension for arithmetic shifts to not shift the number of bits in
2139 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2140 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2141 Fix madd.
2142 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2143 It's OK to have a mult follow a mult. What's not OK is to have a
2144 mult follow an mfhi.
2145 (Convert): Comment out incorrect rounding code.
2146
2147Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2148
2149 * interp.c (sim_monitor): Improved monitor printf
2150 simulation. Tidied up simulator warnings, and added "--log" option
2151 for directing warning message output.
2152 * gencode.c: Use sim_warning() rather than WARNING macro.
2153
2154Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2155
2156 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2157 getopt1.o, rather than on gencode.c. Link objects together.
2158 Don't link against -liberty.
2159 (gencode.o, getopt.o, getopt1.o): New targets.
2160 * gencode.c: Include <ctype.h> and "ansidecl.h".
2161 (AND): Undefine after including "ansidecl.h".
2162 (ULONG_MAX): Define if not defined.
2163 (OP_*): Don't define macros; now defined in opcode/mips.h.
2164 (main): Call my_strtoul rather than strtoul.
2165 (my_strtoul): New static function.
2166
2167Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2168
2169 * gencode.c (process_instructions): Generate word64 and uword64
2170 instead of `long long' and `unsigned long long' data types.
2171 * interp.c: #include sysdep.h to get signals, and define default
2172 for SIGBUS.
2173 * (Convert): Work around for Visual-C++ compiler bug with type
2174 conversion.
2175 * support.h: Make things compile under Visual-C++ by using
2176 __int64 instead of `long long'. Change many refs to long long
2177 into word64/uword64 typedefs.
2178
2179Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2180
2181 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2182 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2183 (docdir): Removed.
2184 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2185 (AC_PROG_INSTALL): Added.
2186 (AC_PROG_CC): Moved to before configure.host call.
2187 * configure: Rebuilt.
2188
2189Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2190
2191 * configure.in: Define @SIMCONF@ depending on mips target.
2192 * configure: Rebuild.
2193 * Makefile.in (run): Add @SIMCONF@ to control simulator
2194 construction.
2195 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2196 * interp.c: Remove some debugging, provide more detailed error
2197 messages, update memory accesses to use LOADDRMASK.
2198
2199Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2200
2201 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2202 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2203 stamp-h.
2204 * configure: Rebuild.
2205 * config.in: New file, generated by autoheader.
2206 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2207 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2208 HAVE_ANINT and HAVE_AINT, as appropriate.
2209 * Makefile.in (run): Use @LIBS@ rather than -lm.
2210 (interp.o): Depend upon config.h.
2211 (Makefile): Just rebuild Makefile.
2212 (clean): Remove stamp-h.
2213 (mostlyclean): Make the same as clean, not as distclean.
2214 (config.h, stamp-h): New targets.
2215
2216Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2217
2218 * interp.c (ColdReset): Fix boolean test. Make all simulator
2219 globals static.
2220
2221Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2222
2223 * interp.c (xfer_direct_word, xfer_direct_long,
2224 swap_direct_word, swap_direct_long, xfer_big_word,
2225 xfer_big_long, xfer_little_word, xfer_little_long,
2226 swap_word,swap_long): Added.
2227 * interp.c (ColdReset): Provide function indirection to
2228 host<->simulated_target transfer routines.
2229 * interp.c (sim_store_register, sim_fetch_register): Updated to
2230 make use of indirected transfer routines.
2231
2232Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2233
2234 * gencode.c (process_instructions): Ensure FP ABS instruction
2235 recognised.
2236 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2237 system call support.
2238
2239Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2240
2241 * interp.c (sim_do_command): Complain if callback structure not
2242 initialised.
2243
2244Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2245
2246 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2247 support for Sun hosts.
2248 * Makefile.in (gencode): Ensure the host compiler and libraries
2249 used for cross-hosted build.
2250
2251Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2252
2253 * interp.c, gencode.c: Some more (TODO) tidying.
2254
2255Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2256
2257 * gencode.c, interp.c: Replaced explicit long long references with
2258 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2259 * support.h (SET64LO, SET64HI): Macros added.
2260
2261Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2262
2263 * configure: Regenerate with autoconf 2.7.
2264
2265Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2266
2267 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2268 * support.h: Remove superfluous "1" from #if.
2269 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2270
2271Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2272
2273 * interp.c (StoreFPR): Control UndefinedResult() call on
2274 WARN_RESULT manifest.
2275
2276Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2277
2278 * gencode.c: Tidied instruction decoding, and added FP instruction
2279 support.
2280
2281 * interp.c: Added dineroIII, and BSD profiling support. Also
2282 run-time FP handling.
2283
2284Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2285
2286 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2287 gencode.c, interp.c, support.h: created.
A mirror of the official binutils-gdb repository