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KVM: x86: do not scan IRR twice on APICv vmentry
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
1767e931
PG		 39#include <linux/export.h>
40#include <linux/moduleparam.h>
0de10343 41#include <linux/mman.h>
2bacc55c 42#include <linux/highmem.h>
19de40a8 43#include <linux/iommu.h>
62c476c7 44#include <linux/intel-iommu.h>
c8076604 45#include <linux/cpufreq.h>
18863bdd 46#include <linux/user-return-notifier.h>
a983fb23 47#include <linux/srcu.h>
5a0e3ad6 48#include <linux/slab.h>
ff9d07a0 49#include <linux/perf_event.h>
7bee342a 50#include <linux/uaccess.h>
af585b92 51#include <linux/hash.h>
a1b60c1c 52#include <linux/pci.h>
16e8d74d
MT		 53#include <linux/timekeeper_internal.h>
54#include <linux/pvclock_gtod.h>
87276880
FW		 55#include <linux/kvm_irqfd.h>
56#include <linux/irqbypass.h>
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
043405e1 68
d1898b73
DH		 69#define CREATE_TRACE_POINTS
70#include "trace.h"
71
313a3dc7 72#define MAX_IO_MSRS 256
890ca9ae 73#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 74u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
75EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 76
0f65dd70
AK		 77#define emul_to_vcpu(ctxt) \
78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79
50a37eb4
JR		 80/* EFER defaults:
81 * - enable syscall per default because its emulated by KVM
82 * - enable LME and LMA per default on 64 bit KVM
83 */
84#ifdef CONFIG_X86_64
1260edbe
LJ		 85static
86u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 87#else
1260edbe 88static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 89#endif
313a3dc7 90
ba1389b7
AK		 91#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
92#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 93
c519265f
RK		 94#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 96
cb142eb7 97static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 98static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 99static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 100static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 101
893590c7 102struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 103EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 104
893590c7 105static bool __read_mostly ignore_msrs = 0;
476bc001 106module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 107
9ed96e87
MT		 108unsigned int min_timer_period_us = 500;
109module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
110
630994b3
MT		 111static bool __read_mostly kvmclock_periodic_sync = true;
112module_param(kvmclock_periodic_sync, bool, S_IRUGO);
113
893590c7 114bool __read_mostly kvm_has_tsc_control;
92a1f12d 115EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 116u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 117EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 118u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
119EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
120u64 __read_mostly kvm_max_tsc_scaling_ratio;
121EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 122u64 __read_mostly kvm_default_tsc_scaling_ratio;
123EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 124
cc578287 125/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 126static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 127module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
128
d0659d94 129/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 130unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 131module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
132
52004014
FW		 133static bool __read_mostly vector_hashing = true;
134module_param(vector_hashing, bool, S_IRUGO);
135
893590c7 136static bool __read_mostly backwards_tsc_observed = false;
16a96021 137
18863bdd
AK		 138#define KVM_NR_SHARED_MSRS 16
139
140struct kvm_shared_msrs_global {
141 int nr;
2bf78fa7 142 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 143};
144
145struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
2bf78fa7
SY		 148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 152};
153
154static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 155static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 156
417bc304 157struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 168 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 173 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 181 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 182 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 183 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 184 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
185 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
186 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
187 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
188 { "mmu_flooded", VM_STAT(mmu_flooded) },
189 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 190 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 191 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 192 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 193 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 194 { "max_mmu_page_hash_collisions",
195 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 196 { NULL }
197};
198
2acf923e
DC		 199u64 __read_mostly host_xcr0;
200
b6785def 201static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 202
af585b92
GN		 203static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
204{
205 int i;
206 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
207 vcpu->arch.apf.gfns[i] = ~0;
208}
209
18863bdd
AK		 210static void kvm_on_user_return(struct user_return_notifier *urn)
211{
212 unsigned slot;
18863bdd
AK		 213 struct kvm_shared_msrs *locals
214 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 215 struct kvm_shared_msr_values *values;
1650b4eb
IA		 216 unsigned long flags;
217
218 /*
219 * Disabling irqs at this point since the following code could be
220 * interrupted and executed through kvm_arch_hardware_disable()
221 */
222 local_irq_save(flags);
223 if (locals->registered) {
224 locals->registered = false;
225 user_return_notifier_unregister(urn);
226 }
227 local_irq_restore(flags);
18863bdd 228 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 229 values = &locals->values[slot];
230 if (values->host != values->curr) {
231 wrmsrl(shared_msrs_global.msrs[slot], values->host);
232 values->curr = values->host;
18863bdd
AK		 233 }
234 }
18863bdd
AK		 235}
236
2bf78fa7 237static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 238{
18863bdd 239 u64 value;
013f6a5d
MT		 240 unsigned int cpu = smp_processor_id();
241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 242
2bf78fa7
SY		 243 /* only read, and nobody should modify it at this time,
244 * so don't need lock */
245 if (slot >= shared_msrs_global.nr) {
246 printk(KERN_ERR "kvm: invalid MSR slot!");
247 return;
248 }
249 rdmsrl_safe(msr, &value);
250 smsr->values[slot].host = value;
251 smsr->values[slot].curr = value;
252}
253
254void kvm_define_shared_msr(unsigned slot, u32 msr)
255{
0123be42 256 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 257 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 258 if (slot >= shared_msrs_global.nr)
259 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 260}
261EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
262
263static void kvm_shared_msr_cpu_online(void)
264{
265 unsigned i;
18863bdd
AK		 266
267 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 268 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 269}
270
8b3c3104 271int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 272{
013f6a5d
MT		 273 unsigned int cpu = smp_processor_id();
274 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 275 int err;
18863bdd 276
2bf78fa7 277 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 278 return 0;
2bf78fa7 279 smsr->values[slot].curr = value;
8b3c3104
AH		 280 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
281 if (err)
282 return 1;
283
18863bdd
AK		 284 if (!smsr->registered) {
285 smsr->urn.on_user_return = kvm_on_user_return;
286 user_return_notifier_register(&smsr->urn);
287 smsr->registered = true;
288 }
8b3c3104 289 return 0;
18863bdd
AK		 290}
291EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
292
13a34e06 293static void drop_user_return_notifiers(void)
3548bab5 294{
013f6a5d
MT		 295 unsigned int cpu = smp_processor_id();
296 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 297
298 if (smsr->registered)
299 kvm_on_user_return(&smsr->urn);
300}
301
6866b83e
CO		 302u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
303{
8a5a87d9 304 return vcpu->arch.apic_base;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_get_apic_base);
307
58cb628d
JK		 308int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
309{
310 u64 old_state = vcpu->arch.apic_base &
311 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
312 u64 new_state = msr_info->data &
313 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
314 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
315 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
316
317 if (!msr_info->host_initiated &&
318 ((msr_info->data & reserved_bits) != 0 ||
319 new_state == X2APIC_ENABLE ||
320 (new_state == MSR_IA32_APICBASE_ENABLE &&
321 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
322 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
323 old_state == 0)))
324 return 1;
325
326 kvm_lapic_set_base(vcpu, msr_info->data);
327 return 0;
6866b83e
CO		 328}
329EXPORT_SYMBOL_GPL(kvm_set_apic_base);
330
2605fc21 331asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 332{
333 /* Fault while not rebooting. We want the trace. */
334 BUG();
335}
336EXPORT_SYMBOL_GPL(kvm_spurious_fault);
337
3fd28fce
ED		 338#define EXCPT_BENIGN 0
339#define EXCPT_CONTRIBUTORY 1
340#define EXCPT_PF 2
341
342static int exception_class(int vector)
343{
344 switch (vector) {
345 case PF_VECTOR:
346 return EXCPT_PF;
347 case DE_VECTOR:
348 case TS_VECTOR:
349 case NP_VECTOR:
350 case SS_VECTOR:
351 case GP_VECTOR:
352 return EXCPT_CONTRIBUTORY;
353 default:
354 break;
355 }
356 return EXCPT_BENIGN;
357}
358
d6e8c854
NA		 359#define EXCPT_FAULT 0
360#define EXCPT_TRAP 1
361#define EXCPT_ABORT 2
362#define EXCPT_INTERRUPT 3
363
364static int exception_type(int vector)
365{
366 unsigned int mask;
367
368 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
369 return EXCPT_INTERRUPT;
370
371 mask = 1 << vector;
372
373 /* #DB is trap, as instruction watchpoints are handled elsewhere */
374 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
375 return EXCPT_TRAP;
376
377 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
378 return EXCPT_ABORT;
379
380 /* Reserved exceptions will result in fault */
381 return EXCPT_FAULT;
382}
383
3fd28fce 384static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 385 unsigned nr, bool has_error, u32 error_code,
386 bool reinject)
3fd28fce
ED		 387{
388 u32 prev_nr;
389 int class1, class2;
390
3842d135
AK		 391 kvm_make_request(KVM_REQ_EVENT, vcpu);
392
3fd28fce
ED		 393 if (!vcpu->arch.exception.pending) {
394 queue:
3ffb2468
NA		 395 if (has_error && !is_protmode(vcpu))
396 has_error = false;
3fd28fce
ED		 397 vcpu->arch.exception.pending = true;
398 vcpu->arch.exception.has_error_code = has_error;
399 vcpu->arch.exception.nr = nr;
400 vcpu->arch.exception.error_code = error_code;
3f0fd292 401 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 402 return;
403 }
404
405 /* to check exception */
406 prev_nr = vcpu->arch.exception.nr;
407 if (prev_nr == DF_VECTOR) {
408 /* triple fault -> shutdown */
a8eeb04a 409 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 410 return;
411 }
412 class1 = exception_class(prev_nr);
413 class2 = exception_class(nr);
414 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
415 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
416 /* generate double fault per SDM Table 5-5 */
417 vcpu->arch.exception.pending = true;
418 vcpu->arch.exception.has_error_code = true;
419 vcpu->arch.exception.nr = DF_VECTOR;
420 vcpu->arch.exception.error_code = 0;
421 } else
422 /* replace previous exception with a new one in a hope
423 that instruction re-execution will regenerate lost
424 exception */
425 goto queue;
426}
427
298101da
AK		 428void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
429{
ce7ddec4 430 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 431}
432EXPORT_SYMBOL_GPL(kvm_queue_exception);
433
ce7ddec4
JR		 434void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
435{
436 kvm_multiple_exception(vcpu, nr, false, 0, true);
437}
438EXPORT_SYMBOL_GPL(kvm_requeue_exception);
439
6affcbed 440int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 441{
db8fcefa
AP		 442 if (err)
443 kvm_inject_gp(vcpu, 0);
444 else
6affcbed
KH		 445 return kvm_skip_emulated_instruction(vcpu);
446
447 return 1;
db8fcefa
AP		 448}
449EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 450
6389ee94 451void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 452{
453 ++vcpu->stat.pf_guest;
6389ee94
AK		 454 vcpu->arch.cr2 = fault->address;
455 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 456}
27d6c865 457EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 458
ef54bcfe 459static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 460{
6389ee94
AK		 461 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
462 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 463 else
6389ee94 464 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 465
466 return fault->nested_page_fault;
d4f8cf66
JR		 467}
468
3419ffc8
SY		 469void kvm_inject_nmi(struct kvm_vcpu *vcpu)
470{
7460fb4a
AK		 471 atomic_inc(&vcpu->arch.nmi_queued);
472 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 473}
474EXPORT_SYMBOL_GPL(kvm_inject_nmi);
475
298101da
AK		 476void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
477{
ce7ddec4 478 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 479}
480EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
481
ce7ddec4
JR		 482void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
483{
484 kvm_multiple_exception(vcpu, nr, true, error_code, true);
485}
486EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
487
0a79b009
AK		 488/*
489 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
490 * a #GP and return false.
491 */
492bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 493{
0a79b009
AK		 494 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
495 return true;
496 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
497 return false;
298101da 498}
0a79b009 499EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 500
16f8a6f9
NA		 501bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
502{
503 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
504 return true;
505
506 kvm_queue_exception(vcpu, UD_VECTOR);
507 return false;
508}
509EXPORT_SYMBOL_GPL(kvm_require_dr);
510
ec92fe44
JR		 511/*
512 * This function will be used to read from the physical memory of the currently
54bf36aa 513 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 514 * can read from guest physical or from the guest's guest physical memory.
515 */
516int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
517 gfn_t ngfn, void *data, int offset, int len,
518 u32 access)
519{
54987b7a 520 struct x86_exception exception;
ec92fe44
JR		 521 gfn_t real_gfn;
522 gpa_t ngpa;
523
524 ngpa = gfn_to_gpa(ngfn);
54987b7a 525 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 526 if (real_gfn == UNMAPPED_GVA)
527 return -EFAULT;
528
529 real_gfn = gpa_to_gfn(real_gfn);
530
54bf36aa 531 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 532}
533EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
534
69b0049a 535static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 536 void *data, int offset, int len, u32 access)
537{
538 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
539 data, offset, len, access);
540}
541
a03490ed
CO		 542/*
543 * Load the pae pdptrs. Return true is they are all valid.
544 */
ff03a073 545int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 546{
547 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
548 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
549 int i;
550 int ret;
ff03a073 551 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 552
ff03a073
JR		 553 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
554 offset * sizeof(u64), sizeof(pdpte),
555 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 556 if (ret < 0) {
557 ret = 0;
558 goto out;
559 }
560 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 561 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 562 (pdpte[i] &
563 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 564 ret = 0;
565 goto out;
566 }
567 }
568 ret = 1;
569
ff03a073 570 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 571 __set_bit(VCPU_EXREG_PDPTR,
572 (unsigned long *)&vcpu->arch.regs_avail);
573 __set_bit(VCPU_EXREG_PDPTR,
574 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 575out:
a03490ed
CO		 576
577 return ret;
578}
cc4b6871 579EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 580
9ed38ffa 581bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 582{
ff03a073 583 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 584 bool changed = true;
3d06b8bf
JR		 585 int offset;
586 gfn_t gfn;
d835dfec
AK		 587 int r;
588
589 if (is_long_mode(vcpu) || !is_pae(vcpu))
590 return false;
591
6de4f3ad
AK		 592 if (!test_bit(VCPU_EXREG_PDPTR,
593 (unsigned long *)&vcpu->arch.regs_avail))
594 return true;
595
9f8fe504
AK		 596 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
597 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 598 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
599 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 600 if (r < 0)
601 goto out;
ff03a073 602 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 603out:
d835dfec
AK		 604
605 return changed;
606}
9ed38ffa 607EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 608
49a9b07e 609int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 610{
aad82703 611 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 612 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 613
f9a48e6a
AK		 614 cr0 |= X86_CR0_ET;
615
ab344828 616#ifdef CONFIG_X86_64
0f12244f
GN		 617 if (cr0 & 0xffffffff00000000UL)
618 return 1;
ab344828
GN		 619#endif
620
621 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 622
0f12244f
GN		 623 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
624 return 1;
a03490ed 625
0f12244f
GN		 626 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
627 return 1;
a03490ed
CO		 628
629 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
630#ifdef CONFIG_X86_64
f6801dff 631 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 632 int cs_db, cs_l;
633
0f12244f
GN		 634 if (!is_pae(vcpu))
635 return 1;
a03490ed 636 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 637 if (cs_l)
638 return 1;
a03490ed
CO		 639 } else
640#endif
ff03a073 641 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 642 kvm_read_cr3(vcpu)))
0f12244f 643 return 1;
a03490ed
CO		 644 }
645
ad756a16
MJ		 646 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
647 return 1;
648
a03490ed 649 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 650
d170c419 651 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 652 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 653 kvm_async_pf_hash_reset(vcpu);
654 }
e5f3f027 655
aad82703
SY		 656 if ((cr0 ^ old_cr0) & update_bits)
657 kvm_mmu_reset_context(vcpu);
b18d5431 658
879ae188
LE		 659 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
660 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
661 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 662 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
663
0f12244f
GN		 664 return 0;
665}
2d3ad1f4 666EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 667
2d3ad1f4 668void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 669{
49a9b07e 670 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 671}
2d3ad1f4 672EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 673
42bdf991
MT		 674static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
675{
676 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
677 !vcpu->guest_xcr0_loaded) {
678 /* kvm_set_xcr() also depends on this */
679 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
680 vcpu->guest_xcr0_loaded = 1;
681 }
682}
683
684static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
685{
686 if (vcpu->guest_xcr0_loaded) {
687 if (vcpu->arch.xcr0 != host_xcr0)
688 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
689 vcpu->guest_xcr0_loaded = 0;
690 }
691}
692
69b0049a 693static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 694{
56c103ec
LJ		 695 u64 xcr0 = xcr;
696 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 697 u64 valid_bits;
2acf923e
DC		 698
699 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
700 if (index != XCR_XFEATURE_ENABLED_MASK)
701 return 1;
d91cab78 702 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 703 return 1;
d91cab78 704 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 705 return 1;
46c34cb0
PB		 706
707 /*
708 * Do not allow the guest to set bits that we do not support
709 * saving. However, xcr0 bit 0 is always set, even if the
710 * emulated CPU does not support XSAVE (see fx_init).
711 */
d91cab78 712 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 713 if (xcr0 & ~valid_bits)
2acf923e 714 return 1;
46c34cb0 715
d91cab78
DH		 716 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
717 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 718 return 1;
719
d91cab78
DH		 720 if (xcr0 & XFEATURE_MASK_AVX512) {
721 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 722 return 1;
d91cab78 723 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 724 return 1;
725 }
2acf923e 726 vcpu->arch.xcr0 = xcr0;
56c103ec 727
d91cab78 728 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 729 kvm_update_cpuid(vcpu);
2acf923e
DC		 730 return 0;
731}
732
733int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
734{
764bcbc5
Z		 735 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
736 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 737 kvm_inject_gp(vcpu, 0);
738 return 1;
739 }
740 return 0;
741}
742EXPORT_SYMBOL_GPL(kvm_set_xcr);
743
a83b29c6 744int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 745{
fc78f519 746 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 747 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 748 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 749
0f12244f
GN		 750 if (cr4 & CR4_RESERVED_BITS)
751 return 1;
a03490ed 752
2acf923e
DC		 753 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
754 return 1;
755
c68b734f
YW		 756 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
757 return 1;
758
97ec8c06
FW		 759 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
760 return 1;
761
afcbf13f 762 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 763 return 1;
764
b9baba86
HH		 765 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
766 return 1;
767
a03490ed 768 if (is_long_mode(vcpu)) {
0f12244f
GN		 769 if (!(cr4 & X86_CR4_PAE))
770 return 1;
a2edf57f
AK		 771 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
772 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 773 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
774 kvm_read_cr3(vcpu)))
0f12244f
GN		 775 return 1;
776
ad756a16
MJ		 777 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
778 if (!guest_cpuid_has_pcid(vcpu))
779 return 1;
780
781 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
782 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
783 return 1;
784 }
785
5e1746d6 786 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 787 return 1;
a03490ed 788
ad756a16
MJ		 789 if (((cr4 ^ old_cr4) & pdptr_bits) ||
790 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 791 kvm_mmu_reset_context(vcpu);
0f12244f 792
b9baba86 793 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 794 kvm_update_cpuid(vcpu);
2acf923e 795
0f12244f
GN		 796 return 0;
797}
2d3ad1f4 798EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 799
2390218b 800int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 801{
ac146235 802#ifdef CONFIG_X86_64
9d88fca7 803 cr3 &= ~CR3_PCID_INVD;
ac146235 804#endif
9d88fca7 805
9f8fe504 806 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 807 kvm_mmu_sync_roots(vcpu);
77c3913b 808 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 809 return 0;
d835dfec
AK		 810 }
811
a03490ed 812 if (is_long_mode(vcpu)) {
d9f89b88
JK		 813 if (cr3 & CR3_L_MODE_RESERVED_BITS)
814 return 1;
815 } else if (is_pae(vcpu) && is_paging(vcpu) &&
816 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 817 return 1;
a03490ed 818
0f12244f 819 vcpu->arch.cr3 = cr3;
aff48baa 820 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 821 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 822 return 0;
823}
2d3ad1f4 824EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 825
eea1cff9 826int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 827{
0f12244f
GN		 828 if (cr8 & CR8_RESERVED_BITS)
829 return 1;
35754c98 830 if (lapic_in_kernel(vcpu))
a03490ed
CO		 831 kvm_lapic_set_tpr(vcpu, cr8);
832 else
ad312c7c 833 vcpu->arch.cr8 = cr8;
0f12244f
GN		 834 return 0;
835}
2d3ad1f4 836EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 837
2d3ad1f4 838unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 839{
35754c98 840 if (lapic_in_kernel(vcpu))
a03490ed
CO		 841 return kvm_lapic_get_cr8(vcpu);
842 else
ad312c7c 843 return vcpu->arch.cr8;
a03490ed 844}
2d3ad1f4 845EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 846
ae561ede
NA		 847static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
848{
849 int i;
850
851 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
852 for (i = 0; i < KVM_NR_DB_REGS; i++)
853 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
854 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
855 }
856}
857
73aaf249
JK		 858static void kvm_update_dr6(struct kvm_vcpu *vcpu)
859{
860 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
861 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
862}
863
c8639010
JK		 864static void kvm_update_dr7(struct kvm_vcpu *vcpu)
865{
866 unsigned long dr7;
867
868 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
869 dr7 = vcpu->arch.guest_debug_dr7;
870 else
871 dr7 = vcpu->arch.dr7;
872 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 873 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
874 if (dr7 & DR7_BP_EN_MASK)
875 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 876}
877
6f43ed01
NA		 878static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
879{
880 u64 fixed = DR6_FIXED_1;
881
882 if (!guest_cpuid_has_rtm(vcpu))
883 fixed |= DR6_RTM;
884 return fixed;
885}
886
338dbc97 887static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 888{
889 switch (dr) {
890 case 0 ... 3:
891 vcpu->arch.db[dr] = val;
892 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
893 vcpu->arch.eff_db[dr] = val;
894 break;
895 case 4:
020df079
GN		 896 /* fall through */
897 case 6:
338dbc97
GN		 898 if (val & 0xffffffff00000000ULL)
899 return -1; /* #GP */
6f43ed01 900 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 901 kvm_update_dr6(vcpu);
020df079
GN		 902 break;
903 case 5:
020df079
GN		 904 /* fall through */
905 default: /* 7 */
338dbc97
GN		 906 if (val & 0xffffffff00000000ULL)
907 return -1; /* #GP */
020df079 908 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 909 kvm_update_dr7(vcpu);
020df079
GN		 910 break;
911 }
912
913 return 0;
914}
338dbc97
GN		 915
916int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
917{
16f8a6f9 918 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 919 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 920 return 1;
921 }
922 return 0;
338dbc97 923}
020df079
GN		 924EXPORT_SYMBOL_GPL(kvm_set_dr);
925
16f8a6f9 926int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 927{
928 switch (dr) {
929 case 0 ... 3:
930 *val = vcpu->arch.db[dr];
931 break;
932 case 4:
020df079
GN		 933 /* fall through */
934 case 6:
73aaf249
JK		 935 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
936 *val = vcpu->arch.dr6;
937 else
938 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 939 break;
940 case 5:
020df079
GN		 941 /* fall through */
942 default: /* 7 */
943 *val = vcpu->arch.dr7;
944 break;
945 }
338dbc97
GN		 946 return 0;
947}
020df079
GN		 948EXPORT_SYMBOL_GPL(kvm_get_dr);
949
022cd0e8
AK		 950bool kvm_rdpmc(struct kvm_vcpu *vcpu)
951{
952 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
953 u64 data;
954 int err;
955
c6702c9d 956 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 957 if (err)
958 return err;
959 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
960 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
961 return err;
962}
963EXPORT_SYMBOL_GPL(kvm_rdpmc);
964
043405e1
CO		 965/*
966 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
967 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
968 *
969 * This list is modified at module load time to reflect the
e3267cbb 970 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 971 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
972 * may depend on host virtualization features rather than host cpu features.
043405e1 973 */
e3267cbb 974
043405e1
CO		 975static u32 msrs_to_save[] = {
976 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 977 MSR_STAR,
043405e1
CO		 978#ifdef CONFIG_X86_64
979 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
980#endif
b3897a49 981 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 982 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 983};
984
985static unsigned num_msrs_to_save;
986
62ef68bb
PB		 987static u32 emulated_msrs[] = {
988 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
989 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
990 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
991 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 992 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
993 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 994 HV_X64_MSR_RESET,
11c4b1ca 995 HV_X64_MSR_VP_INDEX,
9eec50b8 996 HV_X64_MSR_VP_RUNTIME,
5c919412 997 HV_X64_MSR_SCONTROL,
1f4b34f8 998 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 999 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1000 MSR_KVM_PV_EOI_EN,
1001
ba904635 1002 MSR_IA32_TSC_ADJUST,
a3e06bbe 1003 MSR_IA32_TSCDEADLINE,
043405e1 1004 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1005 MSR_IA32_MCG_STATUS,
1006 MSR_IA32_MCG_CTL,
c45dcc71 1007 MSR_IA32_MCG_EXT_CTL,
64d60670 1008 MSR_IA32_SMBASE,
043405e1
CO		 1009};
1010
62ef68bb
PB		 1011static unsigned num_emulated_msrs;
1012
384bb783 1013bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1014{
b69e8cae 1015 if (efer & efer_reserved_bits)
384bb783 1016 return false;
15c4a640 1017
1b2fd70c
AG		 1018 if (efer & EFER_FFXSR) {
1019 struct kvm_cpuid_entry2 *feat;
1020
1021 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1022 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1023 return false;
1b2fd70c
AG		 1024 }
1025
d8017474
AG		 1026 if (efer & EFER_SVME) {
1027 struct kvm_cpuid_entry2 *feat;
1028
1029 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1030 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1031 return false;
d8017474
AG		 1032 }
1033
384bb783
JK		 1034 return true;
1035}
1036EXPORT_SYMBOL_GPL(kvm_valid_efer);
1037
1038static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1039{
1040 u64 old_efer = vcpu->arch.efer;
1041
1042 if (!kvm_valid_efer(vcpu, efer))
1043 return 1;
1044
1045 if (is_paging(vcpu)
1046 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1047 return 1;
1048
15c4a640 1049 efer &= ~EFER_LMA;
f6801dff 1050 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1051
a3d204e2
SY		 1052 kvm_x86_ops->set_efer(vcpu, efer);
1053
aad82703
SY		 1054 /* Update reserved bits */
1055 if ((efer ^ old_efer) & EFER_NX)
1056 kvm_mmu_reset_context(vcpu);
1057
b69e8cae 1058 return 0;
15c4a640
CO		 1059}
1060
f2b4b7dd
JR		 1061void kvm_enable_efer_bits(u64 mask)
1062{
1063 efer_reserved_bits &= ~mask;
1064}
1065EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1066
15c4a640
CO		 1067/*
1068 * Writes msr value into into the appropriate "register".
1069 * Returns 0 on success, non-0 otherwise.
1070 * Assumes vcpu_load() was already called.
1071 */
8fe8ab46 1072int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1073{
854e8bb1
NA		 1074 switch (msr->index) {
1075 case MSR_FS_BASE:
1076 case MSR_GS_BASE:
1077 case MSR_KERNEL_GS_BASE:
1078 case MSR_CSTAR:
1079 case MSR_LSTAR:
1080 if (is_noncanonical_address(msr->data))
1081 return 1;
1082 break;
1083 case MSR_IA32_SYSENTER_EIP:
1084 case MSR_IA32_SYSENTER_ESP:
1085 /*
1086 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1087 * non-canonical address is written on Intel but not on
1088 * AMD (which ignores the top 32-bits, because it does
1089 * not implement 64-bit SYSENTER).
1090 *
1091 * 64-bit code should hence be able to write a non-canonical
1092 * value on AMD. Making the address canonical ensures that
1093 * vmentry does not fail on Intel after writing a non-canonical
1094 * value, and that something deterministic happens if the guest
1095 * invokes 64-bit SYSENTER.
1096 */
1097 msr->data = get_canonical(msr->data);
1098 }
8fe8ab46 1099 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1100}
854e8bb1 1101EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1102
313a3dc7
CO		 1103/*
1104 * Adapt set_msr() to msr_io()'s calling convention
1105 */
609e36d3
PB		 1106static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1107{
1108 struct msr_data msr;
1109 int r;
1110
1111 msr.index = index;
1112 msr.host_initiated = true;
1113 r = kvm_get_msr(vcpu, &msr);
1114 if (r)
1115 return r;
1116
1117 *data = msr.data;
1118 return 0;
1119}
1120
313a3dc7
CO		 1121static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1122{
8fe8ab46
WA		 1123 struct msr_data msr;
1124
1125 msr.data = *data;
1126 msr.index = index;
1127 msr.host_initiated = true;
1128 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1129}
1130
16e8d74d
MT		 1131#ifdef CONFIG_X86_64
1132struct pvclock_gtod_data {
1133 seqcount_t seq;
1134
1135 struct { /* extract of a clocksource struct */
1136 int vclock_mode;
a5a1d1c2
TG		 1137 u64 cycle_last;
1138 u64 mask;
16e8d74d
MT		 1139 u32 mult;
1140 u32 shift;
1141 } clock;
1142
cbcf2dd3
TG		 1143 u64 boot_ns;
1144 u64 nsec_base;
55dd00a7 1145 u64 wall_time_sec;
16e8d74d
MT		 1146};
1147
1148static struct pvclock_gtod_data pvclock_gtod_data;
1149
1150static void update_pvclock_gtod(struct timekeeper *tk)
1151{
1152 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1153 u64 boot_ns;
1154
876e7881 1155 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1156
1157 write_seqcount_begin(&vdata->seq);
1158
1159 /* copy pvclock gtod data */
876e7881
PZ		 1160 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1161 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1162 vdata->clock.mask = tk->tkr_mono.mask;
1163 vdata->clock.mult = tk->tkr_mono.mult;
1164 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1165
cbcf2dd3 1166 vdata->boot_ns = boot_ns;
876e7881 1167 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1168
55dd00a7
MT		 1169 vdata->wall_time_sec = tk->xtime_sec;
1170
16e8d74d
MT		 1171 write_seqcount_end(&vdata->seq);
1172}
1173#endif
1174
bab5bb39
NK		 1175void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1176{
1177 /*
1178 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1179 * vcpu_enter_guest. This function is only called from
1180 * the physical CPU that is running vcpu.
1181 */
1182 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1183}
16e8d74d 1184
18068523
GOC		 1185static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1186{
9ed3c444
AK		 1187 int version;
1188 int r;
50d0a0f9 1189 struct pvclock_wall_clock wc;
87aeb54f 1190 struct timespec64 boot;
18068523
GOC		 1191
1192 if (!wall_clock)
1193 return;
1194
9ed3c444
AK		 1195 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1196 if (r)
1197 return;
1198
1199 if (version & 1)
1200 ++version; /* first time write, random junk */
1201
1202 ++version;
18068523 1203
1dab1345
NK		 1204 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1205 return;
18068523 1206
50d0a0f9
GH		 1207 /*
1208 * The guest calculates current wall clock time by adding
34c238a1 1209 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1210 * wall clock specified here. guest system time equals host
1211 * system time for us, thus we must fill in host boot time here.
1212 */
87aeb54f 1213 getboottime64(&boot);
50d0a0f9 1214
4b648665 1215 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1216 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1217 boot = timespec64_sub(boot, ts);
4b648665 1218 }
87aeb54f 1219 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1220 wc.nsec = boot.tv_nsec;
1221 wc.version = version;
18068523
GOC		 1222
1223 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1224
1225 version++;
1226 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1227}
1228
50d0a0f9
GH		 1229static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1230{
b51012de
PB		 1231 do_shl32_div32(dividend, divisor);
1232 return dividend;
50d0a0f9
GH		 1233}
1234
3ae13faa 1235static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1236 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1237{
5f4e3f88 1238 uint64_t scaled64;
50d0a0f9
GH		 1239 int32_t shift = 0;
1240 uint64_t tps64;
1241 uint32_t tps32;
1242
3ae13faa
PB		 1243 tps64 = base_hz;
1244 scaled64 = scaled_hz;
50933623 1245 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1246 tps64 >>= 1;
1247 shift--;
1248 }
1249
1250 tps32 = (uint32_t)tps64;
50933623
JK		 1251 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1252 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1253 scaled64 >>= 1;
1254 else
1255 tps32 <<= 1;
50d0a0f9
GH		 1256 shift++;
1257 }
1258
5f4e3f88
ZA		 1259 *pshift = shift;
1260 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1261
3ae13faa
PB		 1262 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1263 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1264}
1265
d828199e 1266#ifdef CONFIG_X86_64
16e8d74d 1267static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1268#endif
16e8d74d 1269
c8076604 1270static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1271static unsigned long max_tsc_khz;
c8076604 1272
cc578287 1273static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1274{
cc578287
ZA		 1275 u64 v = (u64)khz * (1000000 + ppm);
1276 do_div(v, 1000000);
1277 return v;
1e993611
JR		 1278}
1279
381d585c
HZ		 1280static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1281{
1282 u64 ratio;
1283
1284 /* Guest TSC same frequency as host TSC? */
1285 if (!scale) {
1286 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1287 return 0;
1288 }
1289
1290 /* TSC scaling supported? */
1291 if (!kvm_has_tsc_control) {
1292 if (user_tsc_khz > tsc_khz) {
1293 vcpu->arch.tsc_catchup = 1;
1294 vcpu->arch.tsc_always_catchup = 1;
1295 return 0;
1296 } else {
1297 WARN(1, "user requested TSC rate below hardware speed\n");
1298 return -1;
1299 }
1300 }
1301
1302 /* TSC scaling required - calculate ratio */
1303 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1304 user_tsc_khz, tsc_khz);
1305
1306 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1307 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1308 user_tsc_khz);
1309 return -1;
1310 }
1311
1312 vcpu->arch.tsc_scaling_ratio = ratio;
1313 return 0;
1314}
1315
4941b8cb 1316static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1317{
cc578287
ZA		 1318 u32 thresh_lo, thresh_hi;
1319 int use_scaling = 0;
217fc9cf 1320
03ba32ca 1321 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1322 if (user_tsc_khz == 0) {
ad721883
HZ		 1323 /* set tsc_scaling_ratio to a safe value */
1324 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1325 return -1;
ad721883 1326 }
03ba32ca 1327
c285545f 1328 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1329 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1330 &vcpu->arch.virtual_tsc_shift,
1331 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1332 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1333
1334 /*
1335 * Compute the variation in TSC rate which is acceptable
1336 * within the range of tolerance and decide if the
1337 * rate being applied is within that bounds of the hardware
1338 * rate. If so, no scaling or compensation need be done.
1339 */
1340 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1341 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1342 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1343 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1344 use_scaling = 1;
1345 }
4941b8cb 1346 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1347}
1348
1349static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1350{
e26101b1 1351 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1352 vcpu->arch.virtual_tsc_mult,
1353 vcpu->arch.virtual_tsc_shift);
e26101b1 1354 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1355 return tsc;
1356}
1357
69b0049a 1358static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1359{
1360#ifdef CONFIG_X86_64
1361 bool vcpus_matched;
b48aa97e
MT		 1362 struct kvm_arch *ka = &vcpu->kvm->arch;
1363 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1364
1365 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1366 atomic_read(&vcpu->kvm->online_vcpus));
1367
7f187922
MT		 1368 /*
1369 * Once the masterclock is enabled, always perform request in
1370 * order to update it.
1371 *
1372 * In order to enable masterclock, the host clocksource must be TSC
1373 * and the vcpus need to have matched TSCs. When that happens,
1374 * perform request to enable masterclock.
1375 */
1376 if (ka->use_master_clock ||
1377 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1378 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1379
1380 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1381 atomic_read(&vcpu->kvm->online_vcpus),
1382 ka->use_master_clock, gtod->clock.vclock_mode);
1383#endif
1384}
1385
ba904635
WA		 1386static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1387{
3e3f5026 1388 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1389 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1390}
1391
35181e86
HZ		 1392/*
1393 * Multiply tsc by a fixed point number represented by ratio.
1394 *
1395 * The most significant 64-N bits (mult) of ratio represent the
1396 * integral part of the fixed point number; the remaining N bits
1397 * (frac) represent the fractional part, ie. ratio represents a fixed
1398 * point number (mult + frac * 2^(-N)).
1399 *
1400 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1401 */
1402static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1403{
1404 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1405}
1406
1407u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1408{
1409 u64 _tsc = tsc;
1410 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1411
1412 if (ratio != kvm_default_tsc_scaling_ratio)
1413 _tsc = __scale_tsc(ratio, tsc);
1414
1415 return _tsc;
1416}
1417EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1418
07c1419a
HZ		 1419static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1420{
1421 u64 tsc;
1422
1423 tsc = kvm_scale_tsc(vcpu, rdtsc());
1424
1425 return target_tsc - tsc;
1426}
1427
4ba76538
HZ		 1428u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1429{
ea26e4ec 1430 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1431}
1432EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1433
a545ab6a
LC		 1434static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1435{
1436 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1437 vcpu->arch.tsc_offset = offset;
1438}
1439
8fe8ab46 1440void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1441{
1442 struct kvm *kvm = vcpu->kvm;
f38e098f 1443 u64 offset, ns, elapsed;
99e3e30a 1444 unsigned long flags;
02626b6a 1445 s64 usdiff;
b48aa97e 1446 bool matched;
0d3da0d2 1447 bool already_matched;
8fe8ab46 1448 u64 data = msr->data;
99e3e30a 1449
038f8c11 1450 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1451 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1452 ns = ktime_get_boot_ns();
f38e098f 1453 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1454
03ba32ca 1455 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1456 int faulted = 0;
1457
03ba32ca
MT		 1458 /* n.b - signed multiplication and division required */
1459 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1460#ifdef CONFIG_X86_64
03ba32ca 1461 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1462#else
03ba32ca 1463 /* do_div() only does unsigned */
8915aa27
MT		 1464 asm("1: idivl %[divisor]\n"
1465 "2: xor %%edx, %%edx\n"
1466 " movl $0, %[faulted]\n"
1467 "3:\n"
1468 ".section .fixup,\"ax\"\n"
1469 "4: movl $1, %[faulted]\n"
1470 " jmp 3b\n"
1471 ".previous\n"
1472
1473 _ASM_EXTABLE(1b, 4b)
1474
1475 : "=A"(usdiff), [faulted] "=r" (faulted)
1476 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1477
5d3cb0f6 1478#endif
03ba32ca
MT		 1479 do_div(elapsed, 1000);
1480 usdiff -= elapsed;
1481 if (usdiff < 0)
1482 usdiff = -usdiff;
8915aa27
MT		 1483
1484 /* idivl overflow => difference is larger than USEC_PER_SEC */
1485 if (faulted)
1486 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1487 } else
1488 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1489
1490 /*
5d3cb0f6
ZA		 1491 * Special case: TSC write with a small delta (1 second) of virtual
1492 * cycle time against real time is interpreted as an attempt to
1493 * synchronize the CPU.
1494 *
1495 * For a reliable TSC, we can match TSC offsets, and for an unstable
1496 * TSC, we add elapsed time in this computation. We could let the
1497 * compensation code attempt to catch up if we fall behind, but
1498 * it's better to try to match offsets from the beginning.
1499 */
02626b6a 1500 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1501 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1502 if (!check_tsc_unstable()) {
e26101b1 1503 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1504 pr_debug("kvm: matched tsc offset for %llu\n", data);
1505 } else {
857e4099 1506 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1507 data += delta;
07c1419a 1508 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1509 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1510 }
b48aa97e 1511 matched = true;
0d3da0d2 1512 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1513 } else {
1514 /*
1515 * We split periods of matched TSC writes into generations.
1516 * For each generation, we track the original measured
1517 * nanosecond time, offset, and write, so if TSCs are in
1518 * sync, we can match exact offset, and if not, we can match
4a969980 1519 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1520 *
1521 * These values are tracked in kvm->arch.cur_xxx variables.
1522 */
1523 kvm->arch.cur_tsc_generation++;
1524 kvm->arch.cur_tsc_nsec = ns;
1525 kvm->arch.cur_tsc_write = data;
1526 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1527 matched = false;
0d3da0d2 1528 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1529 kvm->arch.cur_tsc_generation, data);
f38e098f 1530 }
e26101b1
ZA		 1531
1532 /*
1533 * We also track th most recent recorded KHZ, write and time to
1534 * allow the matching interval to be extended at each write.
1535 */
f38e098f
ZA		 1536 kvm->arch.last_tsc_nsec = ns;
1537 kvm->arch.last_tsc_write = data;
5d3cb0f6 1538 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1539
b183aa58 1540 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1541
1542 /* Keep track of which generation this VCPU has synchronized to */
1543 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1544 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1545 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1546
ba904635
WA		 1547 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1548 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1549 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1550 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1551
1552 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1553 if (!matched) {
b48aa97e 1554 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1555 } else if (!already_matched) {
1556 kvm->arch.nr_vcpus_matched_tsc++;
1557 }
b48aa97e
MT		 1558
1559 kvm_track_tsc_matching(vcpu);
1560 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1561}
e26101b1 1562
99e3e30a
ZA		 1563EXPORT_SYMBOL_GPL(kvm_write_tsc);
1564
58ea6767
HZ		 1565static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1566 s64 adjustment)
1567{
ea26e4ec 1568 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1569}
1570
1571static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1572{
1573 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1574 WARN_ON(adjustment < 0);
1575 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1576 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1577}
1578
d828199e
MT		 1579#ifdef CONFIG_X86_64
1580
a5a1d1c2 1581static u64 read_tsc(void)
d828199e 1582{
a5a1d1c2 1583 u64 ret = (u64)rdtsc_ordered();
03b9730b 1584 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1585
1586 if (likely(ret >= last))
1587 return ret;
1588
1589 /*
1590 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1591 * predictable (it's just a function of time and the likely is
d828199e
MT		 1592 * very likely) and there's a data dependence, so force GCC
1593 * to generate a branch instead. I don't barrier() because
1594 * we don't actually need a barrier, and if this function
1595 * ever gets inlined it will generate worse code.
1596 */
1597 asm volatile ("");
1598 return last;
1599}
1600
a5a1d1c2 1601static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1602{
1603 long v;
1604 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1605
1606 *cycle_now = read_tsc();
1607
1608 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1609 return v * gtod->clock.mult;
1610}
1611
a5a1d1c2 1612static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1613{
cbcf2dd3 1614 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1615 unsigned long seq;
d828199e 1616 int mode;
cbcf2dd3 1617 u64 ns;
d828199e 1618
d828199e
MT		 1619 do {
1620 seq = read_seqcount_begin(&gtod->seq);
1621 mode = gtod->clock.vclock_mode;
cbcf2dd3 1622 ns = gtod->nsec_base;
d828199e
MT		 1623 ns += vgettsc(cycle_now);
1624 ns >>= gtod->clock.shift;
cbcf2dd3 1625 ns += gtod->boot_ns;
d828199e 1626 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1627 *t = ns;
d828199e
MT		 1628
1629 return mode;
1630}
1631
55dd00a7
MT		 1632static int do_realtime(struct timespec *ts, u64 *cycle_now)
1633{
1634 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1635 unsigned long seq;
1636 int mode;
1637 u64 ns;
1638
1639 do {
1640 seq = read_seqcount_begin(&gtod->seq);
1641 mode = gtod->clock.vclock_mode;
1642 ts->tv_sec = gtod->wall_time_sec;
1643 ns = gtod->nsec_base;
1644 ns += vgettsc(cycle_now);
1645 ns >>= gtod->clock.shift;
1646 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1647
1648 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1649 ts->tv_nsec = ns;
1650
1651 return mode;
1652}
1653
d828199e 1654/* returns true if host is using tsc clocksource */
a5a1d1c2 1655static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1656{
d828199e
MT		 1657 /* checked again under seqlock below */
1658 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1659 return false;
1660
cbcf2dd3 1661 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1662}
55dd00a7
MT		 1663
1664/* returns true if host is using tsc clocksource */
1665static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1666 u64 *cycle_now)
1667{
1668 /* checked again under seqlock below */
1669 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1670 return false;
1671
1672 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1673}
d828199e
MT		 1674#endif
1675
1676/*
1677 *
b48aa97e
MT		 1678 * Assuming a stable TSC across physical CPUS, and a stable TSC
1679 * across virtual CPUs, the following condition is possible.
1680 * Each numbered line represents an event visible to both
d828199e
MT		 1681 * CPUs at the next numbered event.
1682 *
1683 * "timespecX" represents host monotonic time. "tscX" represents
1684 * RDTSC value.
1685 *
1686 * VCPU0 on CPU0 | VCPU1 on CPU1
1687 *
1688 * 1. read timespec0,tsc0
1689 * 2. | timespec1 = timespec0 + N
1690 * | tsc1 = tsc0 + M
1691 * 3. transition to guest | transition to guest
1692 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1693 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1694 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1695 *
1696 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1697 *
1698 * - ret0 < ret1
1699 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1700 * ...
1701 * - 0 < N - M => M < N
1702 *
1703 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1704 * always the case (the difference between two distinct xtime instances
1705 * might be smaller then the difference between corresponding TSC reads,
1706 * when updating guest vcpus pvclock areas).
1707 *
1708 * To avoid that problem, do not allow visibility of distinct
1709 * system_timestamp/tsc_timestamp values simultaneously: use a master
1710 * copy of host monotonic time values. Update that master copy
1711 * in lockstep.
1712 *
b48aa97e 1713 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1714 *
1715 */
1716
1717static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1718{
1719#ifdef CONFIG_X86_64
1720 struct kvm_arch *ka = &kvm->arch;
1721 int vclock_mode;
b48aa97e
MT		 1722 bool host_tsc_clocksource, vcpus_matched;
1723
1724 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1725 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1726
1727 /*
1728 * If the host uses TSC clock, then passthrough TSC as stable
1729 * to the guest.
1730 */
b48aa97e 1731 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1732 &ka->master_kernel_ns,
1733 &ka->master_cycle_now);
1734
16a96021 1735 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1736 && !backwards_tsc_observed
1737 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1738
d828199e
MT		 1739 if (ka->use_master_clock)
1740 atomic_set(&kvm_guest_has_master_clock, 1);
1741
1742 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1743 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1744 vcpus_matched);
d828199e
MT		 1745#endif
1746}
1747
2860c4b1
PB		 1748void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1749{
1750 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1751}
1752
2e762ff7
MT		 1753static void kvm_gen_update_masterclock(struct kvm *kvm)
1754{
1755#ifdef CONFIG_X86_64
1756 int i;
1757 struct kvm_vcpu *vcpu;
1758 struct kvm_arch *ka = &kvm->arch;
1759
1760 spin_lock(&ka->pvclock_gtod_sync_lock);
1761 kvm_make_mclock_inprogress_request(kvm);
1762 /* no guest entries from this point */
1763 pvclock_update_vm_gtod_copy(kvm);
1764
1765 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1766 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1767
1768 /* guest entries allowed */
1769 kvm_for_each_vcpu(i, vcpu, kvm)
1770 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1771
1772 spin_unlock(&ka->pvclock_gtod_sync_lock);
1773#endif
1774}
1775
108b249c
PB		 1776static u64 __get_kvmclock_ns(struct kvm *kvm)
1777{
108b249c 1778 struct kvm_arch *ka = &kvm->arch;
8b953440 1779 struct pvclock_vcpu_time_info hv_clock;
108b249c 1780
8b953440
PB		 1781 spin_lock(&ka->pvclock_gtod_sync_lock);
1782 if (!ka->use_master_clock) {
1783 spin_unlock(&ka->pvclock_gtod_sync_lock);
1784 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1785 }
1786
8b953440
PB		 1787 hv_clock.tsc_timestamp = ka->master_cycle_now;
1788 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1789 spin_unlock(&ka->pvclock_gtod_sync_lock);
1790
1791 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1792 &hv_clock.tsc_shift,
1793 &hv_clock.tsc_to_system_mul);
1794 return __pvclock_read_cycles(&hv_clock, rdtsc());
108b249c
PB		 1795}
1796
1797u64 get_kvmclock_ns(struct kvm *kvm)
1798{
1799 unsigned long flags;
1800 s64 ns;
1801
1802 local_irq_save(flags);
1803 ns = __get_kvmclock_ns(kvm);
1804 local_irq_restore(flags);
1805
1806 return ns;
1807}
1808
0d6dd2ff
PB		 1809static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1810{
1811 struct kvm_vcpu_arch *vcpu = &v->arch;
1812 struct pvclock_vcpu_time_info guest_hv_clock;
1813
1814 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1815 &guest_hv_clock, sizeof(guest_hv_clock))))
1816 return;
1817
1818 /* This VCPU is paused, but it's legal for a guest to read another
1819 * VCPU's kvmclock, so we really have to follow the specification where
1820 * it says that version is odd if data is being modified, and even after
1821 * it is consistent.
1822 *
1823 * Version field updates must be kept separate. This is because
1824 * kvm_write_guest_cached might use a "rep movs" instruction, and
1825 * writes within a string instruction are weakly ordered. So there
1826 * are three writes overall.
1827 *
1828 * As a small optimization, only write the version field in the first
1829 * and third write. The vcpu->pv_time cache is still valid, because the
1830 * version field is the first in the struct.
1831 */
1832 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1833
1834 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1835 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1836 &vcpu->hv_clock,
1837 sizeof(vcpu->hv_clock.version));
1838
1839 smp_wmb();
1840
1841 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1842 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1843
1844 if (vcpu->pvclock_set_guest_stopped_request) {
1845 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1846 vcpu->pvclock_set_guest_stopped_request = false;
1847 }
1848
1849 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1850
1851 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1852 &vcpu->hv_clock,
1853 sizeof(vcpu->hv_clock));
1854
1855 smp_wmb();
1856
1857 vcpu->hv_clock.version++;
1858 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1859 &vcpu->hv_clock,
1860 sizeof(vcpu->hv_clock.version));
1861}
1862
34c238a1 1863static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1864{
78db6a50 1865 unsigned long flags, tgt_tsc_khz;
18068523 1866 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1867 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1868 s64 kernel_ns;
d828199e 1869 u64 tsc_timestamp, host_tsc;
51d59c6b 1870 u8 pvclock_flags;
d828199e
MT		 1871 bool use_master_clock;
1872
1873 kernel_ns = 0;
1874 host_tsc = 0;
18068523 1875
d828199e
MT		 1876 /*
1877 * If the host uses TSC clock, then passthrough TSC as stable
1878 * to the guest.
1879 */
1880 spin_lock(&ka->pvclock_gtod_sync_lock);
1881 use_master_clock = ka->use_master_clock;
1882 if (use_master_clock) {
1883 host_tsc = ka->master_cycle_now;
1884 kernel_ns = ka->master_kernel_ns;
1885 }
1886 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1887
1888 /* Keep irq disabled to prevent changes to the clock */
1889 local_irq_save(flags);
78db6a50
PB		 1890 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1891 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1892 local_irq_restore(flags);
1893 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1894 return 1;
1895 }
d828199e 1896 if (!use_master_clock) {
4ea1636b 1897 host_tsc = rdtsc();
108b249c 1898 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1899 }
1900
4ba76538 1901 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1902
c285545f
ZA		 1903 /*
1904 * We may have to catch up the TSC to match elapsed wall clock
1905 * time for two reasons, even if kvmclock is used.
1906 * 1) CPU could have been running below the maximum TSC rate
1907 * 2) Broken TSC compensation resets the base at each VCPU
1908 * entry to avoid unknown leaps of TSC even when running
1909 * again on the same CPU. This may cause apparent elapsed
1910 * time to disappear, and the guest to stand still or run
1911 * very slowly.
1912 */
1913 if (vcpu->tsc_catchup) {
1914 u64 tsc = compute_guest_tsc(v, kernel_ns);
1915 if (tsc > tsc_timestamp) {
f1e2b260 1916 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1917 tsc_timestamp = tsc;
1918 }
50d0a0f9
GH		 1919 }
1920
18068523
GOC		 1921 local_irq_restore(flags);
1922
0d6dd2ff 1923 /* With all the info we got, fill in the values */
18068523 1924
78db6a50
PB		 1925 if (kvm_has_tsc_control)
1926 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1927
1928 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1929 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1930 &vcpu->hv_clock.tsc_shift,
1931 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1932 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1933 }
1934
1d5f066e 1935 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1936 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1937 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1938
d828199e 1939 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1940 pvclock_flags = 0;
d828199e
MT		 1941 if (use_master_clock)
1942 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1943
78c0337a
MT		 1944 vcpu->hv_clock.flags = pvclock_flags;
1945
095cf55d
PB		 1946 if (vcpu->pv_time_enabled)
1947 kvm_setup_pvclock_page(v);
1948 if (v == kvm_get_vcpu(v->kvm, 0))
1949 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1950 return 0;
c8076604
GH		 1951}
1952
0061d53d
MT		 1953/*
1954 * kvmclock updates which are isolated to a given vcpu, such as
1955 * vcpu->cpu migration, should not allow system_timestamp from
1956 * the rest of the vcpus to remain static. Otherwise ntp frequency
1957 * correction applies to one vcpu's system_timestamp but not
1958 * the others.
1959 *
1960 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1961 * We need to rate-limit these requests though, as they can
1962 * considerably slow guests that have a large number of vcpus.
1963 * The time for a remote vcpu to update its kvmclock is bound
1964 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1965 */
1966
7e44e449
AJ		 1967#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1968
1969static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1970{
1971 int i;
7e44e449
AJ		 1972 struct delayed_work *dwork = to_delayed_work(work);
1973 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1974 kvmclock_update_work);
1975 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1976 struct kvm_vcpu *vcpu;
1977
1978 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1979 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1980 kvm_vcpu_kick(vcpu);
1981 }
1982}
1983
7e44e449
AJ		 1984static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1985{
1986 struct kvm *kvm = v->kvm;
1987
105b21bb 1988 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1989 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1990 KVMCLOCK_UPDATE_DELAY);
1991}
1992
332967a3
AJ		 1993#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1994
1995static void kvmclock_sync_fn(struct work_struct *work)
1996{
1997 struct delayed_work *dwork = to_delayed_work(work);
1998 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1999 kvmclock_sync_work);
2000 struct kvm *kvm = container_of(ka, struct kvm, arch);
2001
630994b3
MT		 2002 if (!kvmclock_periodic_sync)
2003 return;
2004
332967a3
AJ		 2005 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2006 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2007 KVMCLOCK_SYNC_PERIOD);
2008}
2009
890ca9ae 2010static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 2011{
890ca9ae
HY		 2012 u64 mcg_cap = vcpu->arch.mcg_cap;
2013 unsigned bank_num = mcg_cap & 0xff;
2014
15c4a640 2015 switch (msr) {
15c4a640 2016 case MSR_IA32_MCG_STATUS:
890ca9ae 2017 vcpu->arch.mcg_status = data;
15c4a640 2018 break;
c7ac679c 2019 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2020 if (!(mcg_cap & MCG_CTL_P))
2021 return 1;
2022 if (data != 0 && data != ~(u64)0)
2023 return -1;
2024 vcpu->arch.mcg_ctl = data;
2025 break;
2026 default:
2027 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2028 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2029 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2030 /* only 0 or all 1s can be written to IA32_MCi_CTL
2031 * some Linux kernels though clear bit 10 in bank 4 to
2032 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2033 * this to avoid an uncatched #GP in the guest
2034 */
890ca9ae 2035 if ((offset & 0x3) == 0 &&
114be429 2036 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2037 return -1;
2038 vcpu->arch.mce_banks[offset] = data;
2039 break;
2040 }
2041 return 1;
2042 }
2043 return 0;
2044}
2045
ffde22ac
ES		 2046static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2047{
2048 struct kvm *kvm = vcpu->kvm;
2049 int lm = is_long_mode(vcpu);
2050 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2051 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2052 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2053 : kvm->arch.xen_hvm_config.blob_size_32;
2054 u32 page_num = data & ~PAGE_MASK;
2055 u64 page_addr = data & PAGE_MASK;
2056 u8 *page;
2057 int r;
2058
2059 r = -E2BIG;
2060 if (page_num >= blob_size)
2061 goto out;
2062 r = -ENOMEM;
ff5c2c03
SL		 2063 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2064 if (IS_ERR(page)) {
2065 r = PTR_ERR(page);
ffde22ac 2066 goto out;
ff5c2c03 2067 }
54bf36aa 2068 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2069 goto out_free;
2070 r = 0;
2071out_free:
2072 kfree(page);
2073out:
2074 return r;
2075}
2076
344d9588
GN		 2077static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2078{
2079 gpa_t gpa = data & ~0x3f;
2080
4a969980 2081 /* Bits 2:5 are reserved, Should be zero */
6adba527 2082 if (data & 0x3c)
344d9588
GN		 2083 return 1;
2084
2085 vcpu->arch.apf.msr_val = data;
2086
2087 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2088 kvm_clear_async_pf_completion_queue(vcpu);
2089 kvm_async_pf_hash_reset(vcpu);
2090 return 0;
2091 }
2092
8f964525
AH		 2093 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2094 sizeof(u32)))
344d9588
GN		 2095 return 1;
2096
6adba527 2097 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2098 kvm_async_pf_wakeup_all(vcpu);
2099 return 0;
2100}
2101
12f9a48f
GC		 2102static void kvmclock_reset(struct kvm_vcpu *vcpu)
2103{
0b79459b 2104 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2105}
2106
c9aaa895
GC		 2107static void record_steal_time(struct kvm_vcpu *vcpu)
2108{
2109 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2110 return;
2111
2112 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2113 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2114 return;
2115
0b9f6c46
PX		 2116 vcpu->arch.st.steal.preempted = 0;
2117
35f3fae1
WL		 2118 if (vcpu->arch.st.steal.version & 1)
2119 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2120
2121 vcpu->arch.st.steal.version += 1;
2122
2123 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2124 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2125
2126 smp_wmb();
2127
c54cdf14
LC		 2128 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2129 vcpu->arch.st.last_steal;
2130 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2131
2132 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2133 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2134
2135 smp_wmb();
2136
2137 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2138
2139 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2140 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2141}
2142
8fe8ab46 2143int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2144{
5753785f 2145 bool pr = false;
8fe8ab46
WA		 2146 u32 msr = msr_info->index;
2147 u64 data = msr_info->data;
5753785f 2148
15c4a640 2149 switch (msr) {
2e32b719
BP		 2150 case MSR_AMD64_NB_CFG:
2151 case MSR_IA32_UCODE_REV:
2152 case MSR_IA32_UCODE_WRITE:
2153 case MSR_VM_HSAVE_PA:
2154 case MSR_AMD64_PATCH_LOADER:
2155 case MSR_AMD64_BU_CFG2:
2156 break;
2157
15c4a640 2158 case MSR_EFER:
b69e8cae 2159 return set_efer(vcpu, data);
8f1589d9
AP		 2160 case MSR_K7_HWCR:
2161 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2162 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2163 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2164 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2165 if (data != 0) {
a737f256
CD		 2166 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2167 data);
8f1589d9
AP		 2168 return 1;
2169 }
15c4a640 2170 break;
f7c6d140
AP		 2171 case MSR_FAM10H_MMIO_CONF_BASE:
2172 if (data != 0) {
a737f256
CD		 2173 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2174 "0x%llx\n", data);
f7c6d140
AP		 2175 return 1;
2176 }
15c4a640 2177 break;
b5e2fec0
AG		 2178 case MSR_IA32_DEBUGCTLMSR:
2179 if (!data) {
2180 /* We support the non-activated case already */
2181 break;
2182 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2183 /* Values other than LBR and BTF are vendor-specific,
2184 thus reserved and should throw a #GP */
2185 return 1;
2186 }
a737f256
CD		 2187 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2188 __func__, data);
b5e2fec0 2189 break;
9ba075a6 2190 case 0x200 ... 0x2ff:
ff53604b 2191 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2192 case MSR_IA32_APICBASE:
58cb628d 2193 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2194 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2195 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2196 case MSR_IA32_TSCDEADLINE:
2197 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2198 break;
ba904635
WA		 2199 case MSR_IA32_TSC_ADJUST:
2200 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2201 if (!msr_info->host_initiated) {
d913b904 2202 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2203 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2204 }
2205 vcpu->arch.ia32_tsc_adjust_msr = data;
2206 }
2207 break;
15c4a640 2208 case MSR_IA32_MISC_ENABLE:
ad312c7c 2209 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2210 break;
64d60670
PB		 2211 case MSR_IA32_SMBASE:
2212 if (!msr_info->host_initiated)
2213 return 1;
2214 vcpu->arch.smbase = data;
2215 break;
11c6bffa 2216 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2217 case MSR_KVM_WALL_CLOCK:
2218 vcpu->kvm->arch.wall_clock = data;
2219 kvm_write_wall_clock(vcpu->kvm, data);
2220 break;
11c6bffa 2221 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2222 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2223 struct kvm_arch *ka = &vcpu->kvm->arch;
2224
12f9a48f 2225 kvmclock_reset(vcpu);
18068523 2226
54750f2c
MT		 2227 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2228 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2229
2230 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2231 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2232 &vcpu->requests);
2233
2234 ka->boot_vcpu_runs_old_kvmclock = tmp;
2235 }
2236
18068523 2237 vcpu->arch.time = data;
0061d53d 2238 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2239
2240 /* we verify if the enable bit is set... */
2241 if (!(data & 1))
2242 break;
2243
0b79459b 2244 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2245 &vcpu->arch.pv_time, data & ~1ULL,
2246 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2247 vcpu->arch.pv_time_enabled = false;
2248 else
2249 vcpu->arch.pv_time_enabled = true;
32cad84f 2250
18068523
GOC		 2251 break;
2252 }
344d9588
GN		 2253 case MSR_KVM_ASYNC_PF_EN:
2254 if (kvm_pv_enable_async_pf(vcpu, data))
2255 return 1;
2256 break;
c9aaa895
GC		 2257 case MSR_KVM_STEAL_TIME:
2258
2259 if (unlikely(!sched_info_on()))
2260 return 1;
2261
2262 if (data & KVM_STEAL_RESERVED_MASK)
2263 return 1;
2264
2265 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2266 data & KVM_STEAL_VALID_BITS,
2267 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2268 return 1;
2269
2270 vcpu->arch.st.msr_val = data;
2271
2272 if (!(data & KVM_MSR_ENABLED))
2273 break;
2274
c9aaa895
GC		 2275 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2276
2277 break;
ae7a2a3f
MT		 2278 case MSR_KVM_PV_EOI_EN:
2279 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2280 return 1;
2281 break;
c9aaa895 2282
890ca9ae
HY		 2283 case MSR_IA32_MCG_CTL:
2284 case MSR_IA32_MCG_STATUS:
81760dcc 2285 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2286 return set_msr_mce(vcpu, msr, data);
71db6023 2287
6912ac32
WH		 2288 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2289 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2290 pr = true; /* fall through */
2291 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2292 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2293 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2294 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2295
2296 if (pr || data != 0)
a737f256
CD		 2297 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2298 "0x%x data 0x%llx\n", msr, data);
5753785f 2299 break;
84e0cefa
JS		 2300 case MSR_K7_CLK_CTL:
2301 /*
2302 * Ignore all writes to this no longer documented MSR.
2303 * Writes are only relevant for old K7 processors,
2304 * all pre-dating SVM, but a recommended workaround from
4a969980 2305 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2306 * affected processor models on the command line, hence
2307 * the need to ignore the workaround.
2308 */
2309 break;
55cd8e5a 2310 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2311 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2312 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2313 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2314 return kvm_hv_set_msr_common(vcpu, msr, data,
2315 msr_info->host_initiated);
91c9c3ed 2316 case MSR_IA32_BBL_CR_CTL3:
2317 /* Drop writes to this legacy MSR -- see rdmsr
2318 * counterpart for further detail.
2319 */
796f4687 2320 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2321 break;
2b036c6b
BO		 2322 case MSR_AMD64_OSVW_ID_LENGTH:
2323 if (!guest_cpuid_has_osvw(vcpu))
2324 return 1;
2325 vcpu->arch.osvw.length = data;
2326 break;
2327 case MSR_AMD64_OSVW_STATUS:
2328 if (!guest_cpuid_has_osvw(vcpu))
2329 return 1;
2330 vcpu->arch.osvw.status = data;
2331 break;
15c4a640 2332 default:
ffde22ac
ES		 2333 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2334 return xen_hvm_config(vcpu, data);
c6702c9d 2335 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2336 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2337 if (!ignore_msrs) {
ae0f5499 2338 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2339 msr, data);
ed85c068
AP		 2340 return 1;
2341 } else {
796f4687 2342 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2343 msr, data);
ed85c068
AP		 2344 break;
2345 }
15c4a640
CO		 2346 }
2347 return 0;
2348}
2349EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2350
2351
2352/*
2353 * Reads an msr value (of 'msr_index') into 'pdata'.
2354 * Returns 0 on success, non-0 otherwise.
2355 * Assumes vcpu_load() was already called.
2356 */
609e36d3 2357int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2358{
609e36d3 2359 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2360}
ff651cb6 2361EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2362
890ca9ae 2363static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2364{
2365 u64 data;
890ca9ae
HY		 2366 u64 mcg_cap = vcpu->arch.mcg_cap;
2367 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2368
2369 switch (msr) {
15c4a640
CO		 2370 case MSR_IA32_P5_MC_ADDR:
2371 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2372 data = 0;
2373 break;
15c4a640 2374 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2375 data = vcpu->arch.mcg_cap;
2376 break;
c7ac679c 2377 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2378 if (!(mcg_cap & MCG_CTL_P))
2379 return 1;
2380 data = vcpu->arch.mcg_ctl;
2381 break;
2382 case MSR_IA32_MCG_STATUS:
2383 data = vcpu->arch.mcg_status;
2384 break;
2385 default:
2386 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2387 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2388 u32 offset = msr - MSR_IA32_MC0_CTL;
2389 data = vcpu->arch.mce_banks[offset];
2390 break;
2391 }
2392 return 1;
2393 }
2394 *pdata = data;
2395 return 0;
2396}
2397
609e36d3 2398int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2399{
609e36d3 2400 switch (msr_info->index) {
890ca9ae 2401 case MSR_IA32_PLATFORM_ID:
15c4a640 2402 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2403 case MSR_IA32_DEBUGCTLMSR:
2404 case MSR_IA32_LASTBRANCHFROMIP:
2405 case MSR_IA32_LASTBRANCHTOIP:
2406 case MSR_IA32_LASTINTFROMIP:
2407 case MSR_IA32_LASTINTTOIP:
60af2ecd 2408 case MSR_K8_SYSCFG:
3afb1121
PB		 2409 case MSR_K8_TSEG_ADDR:
2410 case MSR_K8_TSEG_MASK:
60af2ecd 2411 case MSR_K7_HWCR:
61a6bd67 2412 case MSR_VM_HSAVE_PA:
1fdbd48c 2413 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2414 case MSR_AMD64_NB_CFG:
f7c6d140 2415 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2416 case MSR_AMD64_BU_CFG2:
0c2df2a1 2417 case MSR_IA32_PERF_CTL:
609e36d3 2418 msr_info->data = 0;
15c4a640 2419 break;
6912ac32
WH		 2420 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2421 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2422 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2423 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2424 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2425 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2426 msr_info->data = 0;
5753785f 2427 break;
742bc670 2428 case MSR_IA32_UCODE_REV:
609e36d3 2429 msr_info->data = 0x100000000ULL;
742bc670 2430 break;
9ba075a6 2431 case MSR_MTRRcap:
9ba075a6 2432 case 0x200 ... 0x2ff:
ff53604b 2433 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2434 case 0xcd: /* fsb frequency */
609e36d3 2435 msr_info->data = 3;
15c4a640 2436 break;
7b914098
JS		 2437 /*
2438 * MSR_EBC_FREQUENCY_ID
2439 * Conservative value valid for even the basic CPU models.
2440 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2441 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2442 * and 266MHz for model 3, or 4. Set Core Clock
2443 * Frequency to System Bus Frequency Ratio to 1 (bits
2444 * 31:24) even though these are only valid for CPU
2445 * models > 2, however guests may end up dividing or
2446 * multiplying by zero otherwise.
2447 */
2448 case MSR_EBC_FREQUENCY_ID:
609e36d3 2449 msr_info->data = 1 << 24;
7b914098 2450 break;
15c4a640 2451 case MSR_IA32_APICBASE:
609e36d3 2452 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2453 break;
0105d1a5 2454 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2455 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2456 break;
a3e06bbe 2457 case MSR_IA32_TSCDEADLINE:
609e36d3 2458 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2459 break;
ba904635 2460 case MSR_IA32_TSC_ADJUST:
609e36d3 2461 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2462 break;
15c4a640 2463 case MSR_IA32_MISC_ENABLE:
609e36d3 2464 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2465 break;
64d60670
PB		 2466 case MSR_IA32_SMBASE:
2467 if (!msr_info->host_initiated)
2468 return 1;
2469 msr_info->data = vcpu->arch.smbase;
15c4a640 2470 break;
847f0ad8
AG		 2471 case MSR_IA32_PERF_STATUS:
2472 /* TSC increment by tick */
609e36d3 2473 msr_info->data = 1000ULL;
847f0ad8 2474 /* CPU multiplier */
b0996ae4 2475 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2476 break;
15c4a640 2477 case MSR_EFER:
609e36d3 2478 msr_info->data = vcpu->arch.efer;
15c4a640 2479 break;
18068523 2480 case MSR_KVM_WALL_CLOCK:
11c6bffa 2481 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2482 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2483 break;
2484 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2485 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2486 msr_info->data = vcpu->arch.time;
18068523 2487 break;
344d9588 2488 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2489 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2490 break;
c9aaa895 2491 case MSR_KVM_STEAL_TIME:
609e36d3 2492 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2493 break;
1d92128f 2494 case MSR_KVM_PV_EOI_EN:
609e36d3 2495 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2496 break;
890ca9ae
HY		 2497 case MSR_IA32_P5_MC_ADDR:
2498 case MSR_IA32_P5_MC_TYPE:
2499 case MSR_IA32_MCG_CAP:
2500 case MSR_IA32_MCG_CTL:
2501 case MSR_IA32_MCG_STATUS:
81760dcc 2502 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2503 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2504 case MSR_K7_CLK_CTL:
2505 /*
2506 * Provide expected ramp-up count for K7. All other
2507 * are set to zero, indicating minimum divisors for
2508 * every field.
2509 *
2510 * This prevents guest kernels on AMD host with CPU
2511 * type 6, model 8 and higher from exploding due to
2512 * the rdmsr failing.
2513 */
609e36d3 2514 msr_info->data = 0x20000000;
84e0cefa 2515 break;
55cd8e5a 2516 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2517 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2518 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2519 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2520 return kvm_hv_get_msr_common(vcpu,
2521 msr_info->index, &msr_info->data);
55cd8e5a 2522 break;
91c9c3ed 2523 case MSR_IA32_BBL_CR_CTL3:
2524 /* This legacy MSR exists but isn't fully documented in current
2525 * silicon. It is however accessed by winxp in very narrow
2526 * scenarios where it sets bit #19, itself documented as
2527 * a "reserved" bit. Best effort attempt to source coherent
2528 * read data here should the balance of the register be
2529 * interpreted by the guest:
2530 *
2531 * L2 cache control register 3: 64GB range, 256KB size,
2532 * enabled, latency 0x1, configured
2533 */
609e36d3 2534 msr_info->data = 0xbe702111;
91c9c3ed 2535 break;
2b036c6b
BO		 2536 case MSR_AMD64_OSVW_ID_LENGTH:
2537 if (!guest_cpuid_has_osvw(vcpu))
2538 return 1;
609e36d3 2539 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2540 break;
2541 case MSR_AMD64_OSVW_STATUS:
2542 if (!guest_cpuid_has_osvw(vcpu))
2543 return 1;
609e36d3 2544 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2545 break;
15c4a640 2546 default:
c6702c9d 2547 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2548 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2549 if (!ignore_msrs) {
ae0f5499
BD		 2550 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2551 msr_info->index);
ed85c068
AP		 2552 return 1;
2553 } else {
609e36d3
PB		 2554 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2555 msr_info->data = 0;
ed85c068
AP		 2556 }
2557 break;
15c4a640 2558 }
15c4a640
CO		 2559 return 0;
2560}
2561EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2562
313a3dc7
CO		 2563/*
2564 * Read or write a bunch of msrs. All parameters are kernel addresses.
2565 *
2566 * @return number of msrs set successfully.
2567 */
2568static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2569 struct kvm_msr_entry *entries,
2570 int (*do_msr)(struct kvm_vcpu *vcpu,
2571 unsigned index, u64 *data))
2572{
f656ce01 2573 int i, idx;
313a3dc7 2574
f656ce01 2575 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2576 for (i = 0; i < msrs->nmsrs; ++i)
2577 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2578 break;
f656ce01 2579 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2580
313a3dc7
CO		 2581 return i;
2582}
2583
2584/*
2585 * Read or write a bunch of msrs. Parameters are user addresses.
2586 *
2587 * @return number of msrs set successfully.
2588 */
2589static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2590 int (*do_msr)(struct kvm_vcpu *vcpu,
2591 unsigned index, u64 *data),
2592 int writeback)
2593{
2594 struct kvm_msrs msrs;
2595 struct kvm_msr_entry *entries;
2596 int r, n;
2597 unsigned size;
2598
2599 r = -EFAULT;
2600 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2601 goto out;
2602
2603 r = -E2BIG;
2604 if (msrs.nmsrs >= MAX_IO_MSRS)
2605 goto out;
2606
313a3dc7 2607 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2608 entries = memdup_user(user_msrs->entries, size);
2609 if (IS_ERR(entries)) {
2610 r = PTR_ERR(entries);
313a3dc7 2611 goto out;
ff5c2c03 2612 }
313a3dc7
CO		 2613
2614 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2615 if (r < 0)
2616 goto out_free;
2617
2618 r = -EFAULT;
2619 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2620 goto out_free;
2621
2622 r = n;
2623
2624out_free:
7a73c028 2625 kfree(entries);
313a3dc7
CO		 2626out:
2627 return r;
2628}
2629
784aa3d7 2630int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2631{
2632 int r;
2633
2634 switch (ext) {
2635 case KVM_CAP_IRQCHIP:
2636 case KVM_CAP_HLT:
2637 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2638 case KVM_CAP_SET_TSS_ADDR:
07716717 2639 case KVM_CAP_EXT_CPUID:
9c15bb1d 2640 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2641 case KVM_CAP_CLOCKSOURCE:
7837699f 2642 case KVM_CAP_PIT:
a28e4f5a 2643 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2644 case KVM_CAP_MP_STATE:
ed848624 2645 case KVM_CAP_SYNC_MMU:
a355c85c 2646 case KVM_CAP_USER_NMI:
52d939a0 2647 case KVM_CAP_REINJECT_CONTROL:
4925663a 2648 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2649 case KVM_CAP_IOEVENTFD:
f848a5a8 2650 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2651 case KVM_CAP_PIT2:
e9f42757 2652 case KVM_CAP_PIT_STATE2:
b927a3ce 2653 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2654 case KVM_CAP_XEN_HVM:
3cfc3092 2655 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2656 case KVM_CAP_HYPERV:
10388a07 2657 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2658 case KVM_CAP_HYPERV_SPIN:
5c919412 2659 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2660 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2661 case KVM_CAP_DEBUGREGS:
d2be1651 2662 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2663 case KVM_CAP_XSAVE:
344d9588 2664 case KVM_CAP_ASYNC_PF:
92a1f12d 2665 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2666 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2667 case KVM_CAP_READONLY_MEM:
5f66b620 2668 case KVM_CAP_HYPERV_TIME:
100943c5 2669 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2670 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2671 case KVM_CAP_ENABLE_CAP_VM:
2672 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2673 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2674 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2675#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2676 case KVM_CAP_ASSIGN_DEV_IRQ:
2677 case KVM_CAP_PCI_2_3:
2678#endif
018d00d2
ZX		 2679 r = 1;
2680 break;
e3fd9a93
PB		 2681 case KVM_CAP_ADJUST_CLOCK:
2682 r = KVM_CLOCK_TSC_STABLE;
2683 break;
6d396b55
PB		 2684 case KVM_CAP_X86_SMM:
2685 /* SMBASE is usually relocated above 1M on modern chipsets,
2686 * and SMM handlers might indeed rely on 4G segment limits,
2687 * so do not report SMM to be available if real mode is
2688 * emulated via vm86 mode. Still, do not go to great lengths
2689 * to avoid userspace's usage of the feature, because it is a
2690 * fringe case that is not enabled except via specific settings
2691 * of the module parameters.
2692 */
2693 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2694 break;
542472b5
LV		 2695 case KVM_CAP_COALESCED_MMIO:
2696 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2697 break;
774ead3a
AK		 2698 case KVM_CAP_VAPIC:
2699 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2700 break;
f725230a 2701 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2702 r = KVM_SOFT_MAX_VCPUS;
2703 break;
2704 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2705 r = KVM_MAX_VCPUS;
2706 break;
a988b910 2707 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2708 r = KVM_USER_MEM_SLOTS;
a988b910 2709 break;
a68a6a72
MT		 2710 case KVM_CAP_PV_MMU: /* obsolete */
2711 r = 0;
2f333bcb 2712 break;
4cee4b72 2713#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2714 case KVM_CAP_IOMMU:
a1b60c1c 2715 r = iommu_present(&pci_bus_type);
62c476c7 2716 break;
4cee4b72 2717#endif
890ca9ae
HY		 2718 case KVM_CAP_MCE:
2719 r = KVM_MAX_MCE_BANKS;
2720 break;
2d5b5a66 2721 case KVM_CAP_XCRS:
d366bf7e 2722 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2723 break;
92a1f12d
JR		 2724 case KVM_CAP_TSC_CONTROL:
2725 r = kvm_has_tsc_control;
2726 break;
37131313
RK		 2727 case KVM_CAP_X2APIC_API:
2728 r = KVM_X2APIC_API_VALID_FLAGS;
2729 break;
018d00d2
ZX		 2730 default:
2731 r = 0;
2732 break;
2733 }
2734 return r;
2735
2736}
2737
043405e1
CO		 2738long kvm_arch_dev_ioctl(struct file *filp,
2739 unsigned int ioctl, unsigned long arg)
2740{
2741 void __user *argp = (void __user *)arg;
2742 long r;
2743
2744 switch (ioctl) {
2745 case KVM_GET_MSR_INDEX_LIST: {
2746 struct kvm_msr_list __user *user_msr_list = argp;
2747 struct kvm_msr_list msr_list;
2748 unsigned n;
2749
2750 r = -EFAULT;
2751 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2752 goto out;
2753 n = msr_list.nmsrs;
62ef68bb 2754 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2755 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2756 goto out;
2757 r = -E2BIG;
e125e7b6 2758 if (n < msr_list.nmsrs)
043405e1
CO		 2759 goto out;
2760 r = -EFAULT;
2761 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2762 num_msrs_to_save * sizeof(u32)))
2763 goto out;
e125e7b6 2764 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2765 &emulated_msrs,
62ef68bb 2766 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2767 goto out;
2768 r = 0;
2769 break;
2770 }
9c15bb1d
BP		 2771 case KVM_GET_SUPPORTED_CPUID:
2772 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2773 struct kvm_cpuid2 __user *cpuid_arg = argp;
2774 struct kvm_cpuid2 cpuid;
2775
2776 r = -EFAULT;
2777 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2778 goto out;
9c15bb1d
BP		 2779
2780 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2781 ioctl);
674eea0f
AK		 2782 if (r)
2783 goto out;
2784
2785 r = -EFAULT;
2786 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2787 goto out;
2788 r = 0;
2789 break;
2790 }
890ca9ae 2791 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2792 r = -EFAULT;
c45dcc71
AR		 2793 if (copy_to_user(argp, &kvm_mce_cap_supported,
2794 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2795 goto out;
2796 r = 0;
2797 break;
2798 }
043405e1
CO		 2799 default:
2800 r = -EINVAL;
2801 }
2802out:
2803 return r;
2804}
2805
f5f48ee1
SY		 2806static void wbinvd_ipi(void *garbage)
2807{
2808 wbinvd();
2809}
2810
2811static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2812{
e0f0bbc5 2813 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2814}
2815
2860c4b1
PB		 2816static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2817{
2818 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2819}
2820
313a3dc7
CO		 2821void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2822{
f5f48ee1
SY		 2823 /* Address WBINVD may be executed by guest */
2824 if (need_emulate_wbinvd(vcpu)) {
2825 if (kvm_x86_ops->has_wbinvd_exit())
2826 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2827 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2828 smp_call_function_single(vcpu->cpu,
2829 wbinvd_ipi, NULL, 1);
2830 }
2831
313a3dc7 2832 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2833
0dd6a6ed
ZA		 2834 /* Apply any externally detected TSC adjustments (due to suspend) */
2835 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2836 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2837 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2838 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2839 }
8f6055cb 2840
48434c20 2841 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2842 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2843 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2844 if (tsc_delta < 0)
2845 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2846
c285545f 2847 if (check_tsc_unstable()) {
07c1419a 2848 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2849 vcpu->arch.last_guest_tsc);
a545ab6a 2850 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2851 vcpu->arch.tsc_catchup = 1;
c285545f 2852 }
e12c8f36
WL		 2853 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2854 kvm_x86_ops->set_hv_timer(vcpu,
498f8162 2855 kvm_get_lapic_target_expiration_tsc(vcpu)))
e12c8f36 2856 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2857 /*
2858 * On a host with synchronized TSC, there is no need to update
2859 * kvmclock on vcpu->cpu migration
2860 */
2861 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2862 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2863 if (vcpu->cpu != cpu)
2864 kvm_migrate_timers(vcpu);
e48672fa 2865 vcpu->cpu = cpu;
6b7d7e76 2866 }
c9aaa895 2867
c9aaa895 2868 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2869}
2870
0b9f6c46
PX		 2871static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2872{
2873 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2874 return;
2875
2876 vcpu->arch.st.steal.preempted = 1;
2877
2878 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
2879 &vcpu->arch.st.steal.preempted,
2880 offsetof(struct kvm_steal_time, preempted),
2881 sizeof(vcpu->arch.st.steal.preempted));
2882}
2883
313a3dc7
CO		 2884void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2885{
cc0d907c 2886 int idx;
931f261b
AA		 2887 /*
2888 * Disable page faults because we're in atomic context here.
2889 * kvm_write_guest_offset_cached() would call might_fault()
2890 * that relies on pagefault_disable() to tell if there's a
2891 * bug. NOTE: the write to guest memory may not go through if
2892 * during postcopy live migration or if there's heavy guest
2893 * paging.
2894 */
2895 pagefault_disable();
cc0d907c
AA		 2896 /*
2897 * kvm_memslots() will be called by
2898 * kvm_write_guest_offset_cached() so take the srcu lock.
2899 */
2900 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2901 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2902 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2903 pagefault_enable();
02daab21 2904 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2905 kvm_put_guest_fpu(vcpu);
4ea1636b 2906 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2907}
2908
313a3dc7
CO		 2909static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2910 struct kvm_lapic_state *s)
2911{
76dfafd5 2912 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2913 kvm_x86_ops->sync_pir_to_irr(vcpu);
2914
a92e2543 2915 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2916}
2917
2918static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2919 struct kvm_lapic_state *s)
2920{
a92e2543
RK		 2921 int r;
2922
2923 r = kvm_apic_set_state(vcpu, s);
2924 if (r)
2925 return r;
cb142eb7 2926 update_cr8_intercept(vcpu);
313a3dc7
CO		 2927
2928 return 0;
2929}
2930
127a457a
MG		 2931static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2932{
2933 return (!lapic_in_kernel(vcpu) ||
2934 kvm_apic_accept_pic_intr(vcpu));
2935}
2936
782d422b
MG		 2937/*
2938 * if userspace requested an interrupt window, check that the
2939 * interrupt window is open.
2940 *
2941 * No need to exit to userspace if we already have an interrupt queued.
2942 */
2943static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2944{
2945 return kvm_arch_interrupt_allowed(vcpu) &&
2946 !kvm_cpu_has_interrupt(vcpu) &&
2947 !kvm_event_needs_reinjection(vcpu) &&
2948 kvm_cpu_accept_dm_intr(vcpu);
2949}
2950
f77bc6a4
ZX		 2951static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2952 struct kvm_interrupt *irq)
2953{
02cdb50f 2954 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2955 return -EINVAL;
1c1a9ce9
SR		 2956
2957 if (!irqchip_in_kernel(vcpu->kvm)) {
2958 kvm_queue_interrupt(vcpu, irq->irq, false);
2959 kvm_make_request(KVM_REQ_EVENT, vcpu);
2960 return 0;
2961 }
2962
2963 /*
2964 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2965 * fail for in-kernel 8259.
2966 */
2967 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2968 return -ENXIO;
f77bc6a4 2969
1c1a9ce9
SR		 2970 if (vcpu->arch.pending_external_vector != -1)
2971 return -EEXIST;
f77bc6a4 2972
1c1a9ce9 2973 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2974 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2975 return 0;
2976}
2977
c4abb7c9
JK		 2978static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2979{
c4abb7c9 2980 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2981
2982 return 0;
2983}
2984
f077825a
PB		 2985static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2986{
64d60670
PB		 2987 kvm_make_request(KVM_REQ_SMI, vcpu);
2988
f077825a
PB		 2989 return 0;
2990}
2991
b209749f
AK		 2992static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2993 struct kvm_tpr_access_ctl *tac)
2994{
2995 if (tac->flags)
2996 return -EINVAL;
2997 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2998 return 0;
2999}
3000
890ca9ae
HY		 3001static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3002 u64 mcg_cap)
3003{
3004 int r;
3005 unsigned bank_num = mcg_cap & 0xff, bank;
3006
3007 r = -EINVAL;
a9e38c3e 3008 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3009 goto out;
c45dcc71 3010 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3011 goto out;
3012 r = 0;
3013 vcpu->arch.mcg_cap = mcg_cap;
3014 /* Init IA32_MCG_CTL to all 1s */
3015 if (mcg_cap & MCG_CTL_P)
3016 vcpu->arch.mcg_ctl = ~(u64)0;
3017 /* Init IA32_MCi_CTL to all 1s */
3018 for (bank = 0; bank < bank_num; bank++)
3019 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3020
3021 if (kvm_x86_ops->setup_mce)
3022 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3023out:
3024 return r;
3025}
3026
3027static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3028 struct kvm_x86_mce *mce)
3029{
3030 u64 mcg_cap = vcpu->arch.mcg_cap;
3031 unsigned bank_num = mcg_cap & 0xff;
3032 u64 *banks = vcpu->arch.mce_banks;
3033
3034 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3035 return -EINVAL;
3036 /*
3037 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3038 * reporting is disabled
3039 */
3040 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3041 vcpu->arch.mcg_ctl != ~(u64)0)
3042 return 0;
3043 banks += 4 * mce->bank;
3044 /*
3045 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3046 * reporting is disabled for the bank
3047 */
3048 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3049 return 0;
3050 if (mce->status & MCI_STATUS_UC) {
3051 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3052 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3053 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3054 return 0;
3055 }
3056 if (banks[1] & MCI_STATUS_VAL)
3057 mce->status |= MCI_STATUS_OVER;
3058 banks[2] = mce->addr;
3059 banks[3] = mce->misc;
3060 vcpu->arch.mcg_status = mce->mcg_status;
3061 banks[1] = mce->status;
3062 kvm_queue_exception(vcpu, MC_VECTOR);
3063 } else if (!(banks[1] & MCI_STATUS_VAL)
3064 || !(banks[1] & MCI_STATUS_UC)) {
3065 if (banks[1] & MCI_STATUS_VAL)
3066 mce->status |= MCI_STATUS_OVER;
3067 banks[2] = mce->addr;
3068 banks[3] = mce->misc;
3069 banks[1] = mce->status;
3070 } else
3071 banks[1] |= MCI_STATUS_OVER;
3072 return 0;
3073}
3074
3cfc3092
JK		 3075static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3076 struct kvm_vcpu_events *events)
3077{
7460fb4a 3078 process_nmi(vcpu);
03b82a30
JK		 3079 events->exception.injected =
3080 vcpu->arch.exception.pending &&
3081 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3082 events->exception.nr = vcpu->arch.exception.nr;
3083 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3084 events->exception.pad = 0;
3cfc3092
JK		 3085 events->exception.error_code = vcpu->arch.exception.error_code;
3086
03b82a30
JK		 3087 events->interrupt.injected =
3088 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3089 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3090 events->interrupt.soft = 0;
37ccdcbe 3091 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3092
3093 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3094 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3095 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3096 events->nmi.pad = 0;
3cfc3092 3097
66450a21 3098 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3099
f077825a
PB		 3100 events->smi.smm = is_smm(vcpu);
3101 events->smi.pending = vcpu->arch.smi_pending;
3102 events->smi.smm_inside_nmi =
3103 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3104 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3105
dab4b911 3106 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3107 | KVM_VCPUEVENT_VALID_SHADOW
3108 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3109 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3110}
3111
6ef4e07e
XG		 3112static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3113
3cfc3092
JK		 3114static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3115 struct kvm_vcpu_events *events)
3116{
dab4b911 3117 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3118 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3119 | KVM_VCPUEVENT_VALID_SHADOW
3120 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3121 return -EINVAL;
3122
78e546c8
PB		 3123 if (events->exception.injected &&
3124 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3125 return -EINVAL;
3126
7460fb4a 3127 process_nmi(vcpu);
3cfc3092
JK		 3128 vcpu->arch.exception.pending = events->exception.injected;
3129 vcpu->arch.exception.nr = events->exception.nr;
3130 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3131 vcpu->arch.exception.error_code = events->exception.error_code;
3132
3133 vcpu->arch.interrupt.pending = events->interrupt.injected;
3134 vcpu->arch.interrupt.nr = events->interrupt.nr;
3135 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3136 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3137 kvm_x86_ops->set_interrupt_shadow(vcpu,
3138 events->interrupt.shadow);
3cfc3092
JK		 3139
3140 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3141 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3142 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3143 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3144
66450a21 3145 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3146 lapic_in_kernel(vcpu))
66450a21 3147 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3148
f077825a 3149 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3150 u32 hflags = vcpu->arch.hflags;
f077825a 3151 if (events->smi.smm)
6ef4e07e 3152 hflags |= HF_SMM_MASK;
f077825a 3153 else
6ef4e07e
XG		 3154 hflags &= ~HF_SMM_MASK;
3155 kvm_set_hflags(vcpu, hflags);
3156
f077825a
PB		 3157 vcpu->arch.smi_pending = events->smi.pending;
3158 if (events->smi.smm_inside_nmi)
3159 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3160 else
3161 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3162 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3163 if (events->smi.latched_init)
3164 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3165 else
3166 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3167 }
3168 }
3169
3842d135
AK		 3170 kvm_make_request(KVM_REQ_EVENT, vcpu);
3171
3cfc3092
JK		 3172 return 0;
3173}
3174
a1efbe77
JK		 3175static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3176 struct kvm_debugregs *dbgregs)
3177{
73aaf249
JK		 3178 unsigned long val;
3179
a1efbe77 3180 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3181 kvm_get_dr(vcpu, 6, &val);
73aaf249 3182 dbgregs->dr6 = val;
a1efbe77
JK		 3183 dbgregs->dr7 = vcpu->arch.dr7;
3184 dbgregs->flags = 0;
97e69aa6 3185 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3186}
3187
3188static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3189 struct kvm_debugregs *dbgregs)
3190{
3191 if (dbgregs->flags)
3192 return -EINVAL;
3193
d14bdb55
PB		 3194 if (dbgregs->dr6 & ~0xffffffffull)
3195 return -EINVAL;
3196 if (dbgregs->dr7 & ~0xffffffffull)
3197 return -EINVAL;
3198
a1efbe77 3199 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3200 kvm_update_dr0123(vcpu);
a1efbe77 3201 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3202 kvm_update_dr6(vcpu);
a1efbe77 3203 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3204 kvm_update_dr7(vcpu);
a1efbe77 3205
a1efbe77
JK		 3206 return 0;
3207}
3208
df1daba7
PB		 3209#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3210
3211static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3212{
c47ada30 3213 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3214 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3215 u64 valid;
3216
3217 /*
3218 * Copy legacy XSAVE area, to avoid complications with CPUID
3219 * leaves 0 and 1 in the loop below.
3220 */
3221 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3222
3223 /* Set XSTATE_BV */
3224 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3225
3226 /*
3227 * Copy each region from the possibly compacted offset to the
3228 * non-compacted offset.
3229 */
d91cab78 3230 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3231 while (valid) {
3232 u64 feature = valid & -valid;
3233 int index = fls64(feature) - 1;
3234 void *src = get_xsave_addr(xsave, feature);
3235
3236 if (src) {
3237 u32 size, offset, ecx, edx;
3238 cpuid_count(XSTATE_CPUID, index,
3239 &size, &offset, &ecx, &edx);
3240 memcpy(dest + offset, src, size);
3241 }
3242
3243 valid -= feature;
3244 }
3245}
3246
3247static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3248{
c47ada30 3249 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3250 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3251 u64 valid;
3252
3253 /*
3254 * Copy legacy XSAVE area, to avoid complications with CPUID
3255 * leaves 0 and 1 in the loop below.
3256 */
3257 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3258
3259 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3260 xsave->header.xfeatures = xstate_bv;
782511b0 3261 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3262 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3263
3264 /*
3265 * Copy each region from the non-compacted offset to the
3266 * possibly compacted offset.
3267 */
d91cab78 3268 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3269 while (valid) {
3270 u64 feature = valid & -valid;
3271 int index = fls64(feature) - 1;
3272 void *dest = get_xsave_addr(xsave, feature);
3273
3274 if (dest) {
3275 u32 size, offset, ecx, edx;
3276 cpuid_count(XSTATE_CPUID, index,
3277 &size, &offset, &ecx, &edx);
3278 memcpy(dest, src + offset, size);
ee4100da 3279 }
df1daba7
PB		 3280
3281 valid -= feature;
3282 }
3283}
3284
2d5b5a66
SY		 3285static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3286 struct kvm_xsave *guest_xsave)
3287{
d366bf7e 3288 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3289 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3290 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3291 } else {
2d5b5a66 3292 memcpy(guest_xsave->region,
7366ed77 3293 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3294 sizeof(struct fxregs_state));
2d5b5a66 3295 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3296 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3297 }
3298}
3299
3300static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3301 struct kvm_xsave *guest_xsave)
3302{
3303 u64 xstate_bv =
3304 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3305
d366bf7e 3306 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3307 /*
3308 * Here we allow setting states that are not present in
3309 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3310 * with old userspace.
3311 */
4ff41732 3312 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3313 return -EINVAL;
df1daba7 3314 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3315 } else {
d91cab78 3316 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3317 return -EINVAL;
7366ed77 3318 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3319 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3320 }
3321 return 0;
3322}
3323
3324static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3325 struct kvm_xcrs *guest_xcrs)
3326{
d366bf7e 3327 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3328 guest_xcrs->nr_xcrs = 0;
3329 return;
3330 }
3331
3332 guest_xcrs->nr_xcrs = 1;
3333 guest_xcrs->flags = 0;
3334 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3335 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3336}
3337
3338static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3339 struct kvm_xcrs *guest_xcrs)
3340{
3341 int i, r = 0;
3342
d366bf7e 3343 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3344 return -EINVAL;
3345
3346 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3347 return -EINVAL;
3348
3349 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3350 /* Only support XCR0 currently */
c67a04cb 3351 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3352 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3353 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3354 break;
3355 }
3356 if (r)
3357 r = -EINVAL;
3358 return r;
3359}
3360
1c0b28c2
EM		 3361/*
3362 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3363 * stopped by the hypervisor. This function will be called from the host only.
3364 * EINVAL is returned when the host attempts to set the flag for a guest that
3365 * does not support pv clocks.
3366 */
3367static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3368{
0b79459b 3369 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3370 return -EINVAL;
51d59c6b 3371 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3372 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3373 return 0;
3374}
3375
5c919412
AS		 3376static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3377 struct kvm_enable_cap *cap)
3378{
3379 if (cap->flags)
3380 return -EINVAL;
3381
3382 switch (cap->cap) {
3383 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3384 if (!irqchip_in_kernel(vcpu->kvm))
3385 return -EINVAL;
5c919412
AS		 3386 return kvm_hv_activate_synic(vcpu);
3387 default:
3388 return -EINVAL;
3389 }
3390}
3391
313a3dc7
CO		 3392long kvm_arch_vcpu_ioctl(struct file *filp,
3393 unsigned int ioctl, unsigned long arg)
3394{
3395 struct kvm_vcpu *vcpu = filp->private_data;
3396 void __user *argp = (void __user *)arg;
3397 int r;
d1ac91d8
AK		 3398 union {
3399 struct kvm_lapic_state *lapic;
3400 struct kvm_xsave *xsave;
3401 struct kvm_xcrs *xcrs;
3402 void *buffer;
3403 } u;
3404
3405 u.buffer = NULL;
313a3dc7
CO		 3406 switch (ioctl) {
3407 case KVM_GET_LAPIC: {
2204ae3c 3408 r = -EINVAL;
bce87cce 3409 if (!lapic_in_kernel(vcpu))
2204ae3c 3410 goto out;
d1ac91d8 3411 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3412
b772ff36 3413 r = -ENOMEM;
d1ac91d8 3414 if (!u.lapic)
b772ff36 3415 goto out;
d1ac91d8 3416 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3417 if (r)
3418 goto out;
3419 r = -EFAULT;
d1ac91d8 3420 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3421 goto out;
3422 r = 0;
3423 break;
3424 }
3425 case KVM_SET_LAPIC: {
2204ae3c 3426 r = -EINVAL;
bce87cce 3427 if (!lapic_in_kernel(vcpu))
2204ae3c 3428 goto out;
ff5c2c03 3429 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3430 if (IS_ERR(u.lapic))
3431 return PTR_ERR(u.lapic);
ff5c2c03 3432
d1ac91d8 3433 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3434 break;
3435 }
f77bc6a4
ZX		 3436 case KVM_INTERRUPT: {
3437 struct kvm_interrupt irq;
3438
3439 r = -EFAULT;
3440 if (copy_from_user(&irq, argp, sizeof irq))
3441 goto out;
3442 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3443 break;
3444 }
c4abb7c9
JK		 3445 case KVM_NMI: {
3446 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3447 break;
3448 }
f077825a
PB		 3449 case KVM_SMI: {
3450 r = kvm_vcpu_ioctl_smi(vcpu);
3451 break;
3452 }
313a3dc7
CO		 3453 case KVM_SET_CPUID: {
3454 struct kvm_cpuid __user *cpuid_arg = argp;
3455 struct kvm_cpuid cpuid;
3456
3457 r = -EFAULT;
3458 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3459 goto out;
3460 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3461 break;
3462 }
07716717
DK		 3463 case KVM_SET_CPUID2: {
3464 struct kvm_cpuid2 __user *cpuid_arg = argp;
3465 struct kvm_cpuid2 cpuid;
3466
3467 r = -EFAULT;
3468 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3469 goto out;
3470 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3471 cpuid_arg->entries);
07716717
DK		 3472 break;
3473 }
3474 case KVM_GET_CPUID2: {
3475 struct kvm_cpuid2 __user *cpuid_arg = argp;
3476 struct kvm_cpuid2 cpuid;
3477
3478 r = -EFAULT;
3479 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3480 goto out;
3481 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3482 cpuid_arg->entries);
07716717
DK		 3483 if (r)
3484 goto out;
3485 r = -EFAULT;
3486 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3487 goto out;
3488 r = 0;
3489 break;
3490 }
313a3dc7 3491 case KVM_GET_MSRS:
609e36d3 3492 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3493 break;
3494 case KVM_SET_MSRS:
3495 r = msr_io(vcpu, argp, do_set_msr, 0);
3496 break;
b209749f
AK		 3497 case KVM_TPR_ACCESS_REPORTING: {
3498 struct kvm_tpr_access_ctl tac;
3499
3500 r = -EFAULT;
3501 if (copy_from_user(&tac, argp, sizeof tac))
3502 goto out;
3503 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3504 if (r)
3505 goto out;
3506 r = -EFAULT;
3507 if (copy_to_user(argp, &tac, sizeof tac))
3508 goto out;
3509 r = 0;
3510 break;
3511 };
b93463aa
AK		 3512 case KVM_SET_VAPIC_ADDR: {
3513 struct kvm_vapic_addr va;
7301d6ab 3514 int idx;
b93463aa
AK		 3515
3516 r = -EINVAL;
35754c98 3517 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3518 goto out;
3519 r = -EFAULT;
3520 if (copy_from_user(&va, argp, sizeof va))
3521 goto out;
7301d6ab 3522 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3523 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3524 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3525 break;
3526 }
890ca9ae
HY		 3527 case KVM_X86_SETUP_MCE: {
3528 u64 mcg_cap;
3529
3530 r = -EFAULT;
3531 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3532 goto out;
3533 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3534 break;
3535 }
3536 case KVM_X86_SET_MCE: {
3537 struct kvm_x86_mce mce;
3538
3539 r = -EFAULT;
3540 if (copy_from_user(&mce, argp, sizeof mce))
3541 goto out;
3542 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3543 break;
3544 }
3cfc3092
JK		 3545 case KVM_GET_VCPU_EVENTS: {
3546 struct kvm_vcpu_events events;
3547
3548 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3549
3550 r = -EFAULT;
3551 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3552 break;
3553 r = 0;
3554 break;
3555 }
3556 case KVM_SET_VCPU_EVENTS: {
3557 struct kvm_vcpu_events events;
3558
3559 r = -EFAULT;
3560 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3561 break;
3562
3563 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3564 break;
3565 }
a1efbe77
JK		 3566 case KVM_GET_DEBUGREGS: {
3567 struct kvm_debugregs dbgregs;
3568
3569 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3570
3571 r = -EFAULT;
3572 if (copy_to_user(argp, &dbgregs,
3573 sizeof(struct kvm_debugregs)))
3574 break;
3575 r = 0;
3576 break;
3577 }
3578 case KVM_SET_DEBUGREGS: {
3579 struct kvm_debugregs dbgregs;
3580
3581 r = -EFAULT;
3582 if (copy_from_user(&dbgregs, argp,
3583 sizeof(struct kvm_debugregs)))
3584 break;
3585
3586 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3587 break;
3588 }
2d5b5a66 3589 case KVM_GET_XSAVE: {
d1ac91d8 3590 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3591 r = -ENOMEM;
d1ac91d8 3592 if (!u.xsave)
2d5b5a66
SY		 3593 break;
3594
d1ac91d8 3595 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3596
3597 r = -EFAULT;
d1ac91d8 3598 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3599 break;
3600 r = 0;
3601 break;
3602 }
3603 case KVM_SET_XSAVE: {
ff5c2c03 3604 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3605 if (IS_ERR(u.xsave))
3606 return PTR_ERR(u.xsave);
2d5b5a66 3607
d1ac91d8 3608 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3609 break;
3610 }
3611 case KVM_GET_XCRS: {
d1ac91d8 3612 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3613 r = -ENOMEM;
d1ac91d8 3614 if (!u.xcrs)
2d5b5a66
SY		 3615 break;
3616
d1ac91d8 3617 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3618
3619 r = -EFAULT;
d1ac91d8 3620 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3621 sizeof(struct kvm_xcrs)))
3622 break;
3623 r = 0;
3624 break;
3625 }
3626 case KVM_SET_XCRS: {
ff5c2c03 3627 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3628 if (IS_ERR(u.xcrs))
3629 return PTR_ERR(u.xcrs);
2d5b5a66 3630
d1ac91d8 3631 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3632 break;
3633 }
92a1f12d
JR		 3634 case KVM_SET_TSC_KHZ: {
3635 u32 user_tsc_khz;
3636
3637 r = -EINVAL;
92a1f12d
JR		 3638 user_tsc_khz = (u32)arg;
3639
3640 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3641 goto out;
3642
cc578287
ZA		 3643 if (user_tsc_khz == 0)
3644 user_tsc_khz = tsc_khz;
3645
381d585c
HZ		 3646 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3647 r = 0;
92a1f12d 3648
92a1f12d
JR		 3649 goto out;
3650 }
3651 case KVM_GET_TSC_KHZ: {
cc578287 3652 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3653 goto out;
3654 }
1c0b28c2
EM		 3655 case KVM_KVMCLOCK_CTRL: {
3656 r = kvm_set_guest_paused(vcpu);
3657 goto out;
3658 }
5c919412
AS		 3659 case KVM_ENABLE_CAP: {
3660 struct kvm_enable_cap cap;
3661
3662 r = -EFAULT;
3663 if (copy_from_user(&cap, argp, sizeof(cap)))
3664 goto out;
3665 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3666 break;
3667 }
313a3dc7
CO		 3668 default:
3669 r = -EINVAL;
3670 }
3671out:
d1ac91d8 3672 kfree(u.buffer);
313a3dc7
CO		 3673 return r;
3674}
3675
5b1c1493
CO		 3676int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3677{
3678 return VM_FAULT_SIGBUS;
3679}
3680
1fe779f8
CO		 3681static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3682{
3683 int ret;
3684
3685 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3686 return -EINVAL;
1fe779f8
CO		 3687 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3688 return ret;
3689}
3690
b927a3ce
SY		 3691static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3692 u64 ident_addr)
3693{
3694 kvm->arch.ept_identity_map_addr = ident_addr;
3695 return 0;
3696}
3697
1fe779f8
CO		 3698static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3699 u32 kvm_nr_mmu_pages)
3700{
3701 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3702 return -EINVAL;
3703
79fac95e 3704 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3705
3706 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3707 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3708
79fac95e 3709 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3710 return 0;
3711}
3712
3713static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3714{
39de71ec 3715 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3716}
3717
1fe779f8
CO		 3718static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3719{
3720 int r;
3721
3722 r = 0;
3723 switch (chip->chip_id) {
3724 case KVM_IRQCHIP_PIC_MASTER:
3725 memcpy(&chip->chip.pic,
3726 &pic_irqchip(kvm)->pics[0],
3727 sizeof(struct kvm_pic_state));
3728 break;
3729 case KVM_IRQCHIP_PIC_SLAVE:
3730 memcpy(&chip->chip.pic,
3731 &pic_irqchip(kvm)->pics[1],
3732 sizeof(struct kvm_pic_state));
3733 break;
3734 case KVM_IRQCHIP_IOAPIC:
eba0226b 3735 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3736 break;
3737 default:
3738 r = -EINVAL;
3739 break;
3740 }
3741 return r;
3742}
3743
3744static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3745{
3746 int r;
3747
3748 r = 0;
3749 switch (chip->chip_id) {
3750 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3751 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3752 memcpy(&pic_irqchip(kvm)->pics[0],
3753 &chip->chip.pic,
3754 sizeof(struct kvm_pic_state));
f4f51050 3755 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3756 break;
3757 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3758 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3759 memcpy(&pic_irqchip(kvm)->pics[1],
3760 &chip->chip.pic,
3761 sizeof(struct kvm_pic_state));
f4f51050 3762 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3763 break;
3764 case KVM_IRQCHIP_IOAPIC:
eba0226b 3765 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3766 break;
3767 default:
3768 r = -EINVAL;
3769 break;
3770 }
3771 kvm_pic_update_irq(pic_irqchip(kvm));
3772 return r;
3773}
3774
e0f63cb9
SY		 3775static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3776{
34f3941c
RK		 3777 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3778
3779 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3780
3781 mutex_lock(&kps->lock);
3782 memcpy(ps, &kps->channels, sizeof(*ps));
3783 mutex_unlock(&kps->lock);
2da29bcc 3784 return 0;
e0f63cb9
SY		 3785}
3786
3787static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3788{
0185604c 3789 int i;
09edea72
RK		 3790 struct kvm_pit *pit = kvm->arch.vpit;
3791
3792 mutex_lock(&pit->pit_state.lock);
34f3941c 3793 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3794 for (i = 0; i < 3; i++)
09edea72
RK		 3795 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3796 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3797 return 0;
e9f42757
BK		 3798}
3799
3800static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3801{
e9f42757
BK		 3802 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3803 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3804 sizeof(ps->channels));
3805 ps->flags = kvm->arch.vpit->pit_state.flags;
3806 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3807 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3808 return 0;
e9f42757
BK		 3809}
3810
3811static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3812{
2da29bcc 3813 int start = 0;
0185604c 3814 int i;
e9f42757 3815 u32 prev_legacy, cur_legacy;
09edea72
RK		 3816 struct kvm_pit *pit = kvm->arch.vpit;
3817
3818 mutex_lock(&pit->pit_state.lock);
3819 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3820 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3821 if (!prev_legacy && cur_legacy)
3822 start = 1;
09edea72
RK		 3823 memcpy(&pit->pit_state.channels, &ps->channels,
3824 sizeof(pit->pit_state.channels));
3825 pit->pit_state.flags = ps->flags;
0185604c 3826 for (i = 0; i < 3; i++)
09edea72 3827 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3828 start && i == 0);
09edea72 3829 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3830 return 0;
e0f63cb9
SY		 3831}
3832
52d939a0
MT		 3833static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3834 struct kvm_reinject_control *control)
3835{
71474e2f
RK		 3836 struct kvm_pit *pit = kvm->arch.vpit;
3837
3838 if (!pit)
52d939a0 3839 return -ENXIO;
b39c90b6 3840
71474e2f
RK		 3841 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3842 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3843 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3844 */
3845 mutex_lock(&pit->pit_state.lock);
3846 kvm_pit_set_reinject(pit, control->pit_reinject);
3847 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3848
52d939a0
MT		 3849 return 0;
3850}
3851
95d4c16c 3852/**
60c34612
TY		 3853 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3854 * @kvm: kvm instance
3855 * @log: slot id and address to which we copy the log
95d4c16c 3856 *
e108ff2f
PB		 3857 * Steps 1-4 below provide general overview of dirty page logging. See
3858 * kvm_get_dirty_log_protect() function description for additional details.
3859 *
3860 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3861 * always flush the TLB (step 4) even if previous step failed and the dirty
3862 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3863 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3864 * writes will be marked dirty for next log read.
95d4c16c 3865 *
60c34612
TY		 3866 * 1. Take a snapshot of the bit and clear it if needed.
3867 * 2. Write protect the corresponding page.
e108ff2f
PB		 3868 * 3. Copy the snapshot to the userspace.
3869 * 4. Flush TLB's if needed.
5bb064dc 3870 */
60c34612 3871int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3872{
60c34612 3873 bool is_dirty = false;
e108ff2f 3874 int r;
5bb064dc 3875
79fac95e 3876 mutex_lock(&kvm->slots_lock);
5bb064dc 3877
88178fd4
KH		 3878 /*
3879 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3880 */
3881 if (kvm_x86_ops->flush_log_dirty)
3882 kvm_x86_ops->flush_log_dirty(kvm);
3883
e108ff2f 3884 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3885
3886 /*
3887 * All the TLBs can be flushed out of mmu lock, see the comments in
3888 * kvm_mmu_slot_remove_write_access().
3889 */
e108ff2f 3890 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3891 if (is_dirty)
3892 kvm_flush_remote_tlbs(kvm);
3893
79fac95e 3894 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3895 return r;
3896}
3897
aa2fbe6d
YZ		 3898int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3899 bool line_status)
23d43cf9
CD		 3900{
3901 if (!irqchip_in_kernel(kvm))
3902 return -ENXIO;
3903
3904 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3905 irq_event->irq, irq_event->level,
3906 line_status);
23d43cf9
CD		 3907 return 0;
3908}
3909
90de4a18
NA		 3910static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3911 struct kvm_enable_cap *cap)
3912{
3913 int r;
3914
3915 if (cap->flags)
3916 return -EINVAL;
3917
3918 switch (cap->cap) {
3919 case KVM_CAP_DISABLE_QUIRKS:
3920 kvm->arch.disabled_quirks = cap->args[0];
3921 r = 0;
3922 break;
49df6397
SR		 3923 case KVM_CAP_SPLIT_IRQCHIP: {
3924 mutex_lock(&kvm->lock);
b053b2ae
SR		 3925 r = -EINVAL;
3926 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3927 goto split_irqchip_unlock;
49df6397
SR		 3928 r = -EEXIST;
3929 if (irqchip_in_kernel(kvm))
3930 goto split_irqchip_unlock;
557abc40 3931 if (kvm->created_vcpus)
49df6397
SR		 3932 goto split_irqchip_unlock;
3933 r = kvm_setup_empty_irq_routing(kvm);
3934 if (r)
3935 goto split_irqchip_unlock;
3936 /* Pairs with irqchip_in_kernel. */
3937 smp_wmb();
49776faf 3938 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3939 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3940 r = 0;
3941split_irqchip_unlock:
3942 mutex_unlock(&kvm->lock);
3943 break;
3944 }
37131313
RK		 3945 case KVM_CAP_X2APIC_API:
3946 r = -EINVAL;
3947 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3948 break;
3949
3950 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3951 kvm->arch.x2apic_format = true;
c519265f
RK		 3952 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3953 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3954
3955 r = 0;
3956 break;
90de4a18
NA		 3957 default:
3958 r = -EINVAL;
3959 break;
3960 }
3961 return r;
3962}
3963
1fe779f8
CO		 3964long kvm_arch_vm_ioctl(struct file *filp,
3965 unsigned int ioctl, unsigned long arg)
3966{
3967 struct kvm *kvm = filp->private_data;
3968 void __user *argp = (void __user *)arg;
367e1319 3969 int r = -ENOTTY;
f0d66275
DH		 3970 /*
3971 * This union makes it completely explicit to gcc-3.x
3972 * that these two variables' stack usage should be
3973 * combined, not added together.
3974 */
3975 union {
3976 struct kvm_pit_state ps;
e9f42757 3977 struct kvm_pit_state2 ps2;
c5ff41ce 3978 struct kvm_pit_config pit_config;
f0d66275 3979 } u;
1fe779f8
CO		 3980
3981 switch (ioctl) {
3982 case KVM_SET_TSS_ADDR:
3983 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3984 break;
b927a3ce
SY		 3985 case KVM_SET_IDENTITY_MAP_ADDR: {
3986 u64 ident_addr;
3987
3988 r = -EFAULT;
3989 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3990 goto out;
3991 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3992 break;
3993 }
1fe779f8
CO		 3994 case KVM_SET_NR_MMU_PAGES:
3995 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3996 break;
3997 case KVM_GET_NR_MMU_PAGES:
3998 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3999 break;
3ddea128 4000 case KVM_CREATE_IRQCHIP: {
3ddea128 4001 mutex_lock(&kvm->lock);
09941366 4002
3ddea128 4003 r = -EEXIST;
35e6eaa3 4004 if (irqchip_in_kernel(kvm))
3ddea128 4005 goto create_irqchip_unlock;
09941366 4006
3e515705 4007 r = -EINVAL;
557abc40 4008 if (kvm->created_vcpus)
3e515705 4009 goto create_irqchip_unlock;
09941366
RK		 4010
4011 r = kvm_pic_init(kvm);
4012 if (r)
3ddea128 4013 goto create_irqchip_unlock;
09941366
RK		 4014
4015 r = kvm_ioapic_init(kvm);
4016 if (r) {
4017 mutex_lock(&kvm->slots_lock);
4018 kvm_pic_destroy(kvm);
4019 mutex_unlock(&kvm->slots_lock);
4020 goto create_irqchip_unlock;
4021 }
4022
399ec807
AK		 4023 r = kvm_setup_default_irq_routing(kvm);
4024 if (r) {
175504cd 4025 mutex_lock(&kvm->slots_lock);
3ddea128 4026 mutex_lock(&kvm->irq_lock);
72bb2fcd 4027 kvm_ioapic_destroy(kvm);
09941366 4028 kvm_pic_destroy(kvm);
3ddea128 4029 mutex_unlock(&kvm->irq_lock);
175504cd 4030 mutex_unlock(&kvm->slots_lock);
71ba994c 4031 goto create_irqchip_unlock;
399ec807 4032 }
49776faf 4033 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4034 smp_wmb();
49776faf 4035 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4036 create_irqchip_unlock:
4037 mutex_unlock(&kvm->lock);
1fe779f8 4038 break;
3ddea128 4039 }
7837699f 4040 case KVM_CREATE_PIT:
c5ff41ce
JK		 4041 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4042 goto create_pit;
4043 case KVM_CREATE_PIT2:
4044 r = -EFAULT;
4045 if (copy_from_user(&u.pit_config, argp,
4046 sizeof(struct kvm_pit_config)))
4047 goto out;
4048 create_pit:
250715a6 4049 mutex_lock(&kvm->lock);
269e05e4
AK		 4050 r = -EEXIST;
4051 if (kvm->arch.vpit)
4052 goto create_pit_unlock;
7837699f 4053 r = -ENOMEM;
c5ff41ce 4054 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4055 if (kvm->arch.vpit)
4056 r = 0;
269e05e4 4057 create_pit_unlock:
250715a6 4058 mutex_unlock(&kvm->lock);
7837699f 4059 break;
1fe779f8
CO		 4060 case KVM_GET_IRQCHIP: {
4061 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4062 struct kvm_irqchip *chip;
1fe779f8 4063
ff5c2c03
SL		 4064 chip = memdup_user(argp, sizeof(*chip));
4065 if (IS_ERR(chip)) {
4066 r = PTR_ERR(chip);
1fe779f8 4067 goto out;
ff5c2c03
SL		 4068 }
4069
1fe779f8 4070 r = -ENXIO;
826da321 4071 if (!irqchip_kernel(kvm))
f0d66275
DH		 4072 goto get_irqchip_out;
4073 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4074 if (r)
f0d66275 4075 goto get_irqchip_out;
1fe779f8 4076 r = -EFAULT;
f0d66275
DH		 4077 if (copy_to_user(argp, chip, sizeof *chip))
4078 goto get_irqchip_out;
1fe779f8 4079 r = 0;
f0d66275
DH		 4080 get_irqchip_out:
4081 kfree(chip);
1fe779f8
CO		 4082 break;
4083 }
4084 case KVM_SET_IRQCHIP: {
4085 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4086 struct kvm_irqchip *chip;
1fe779f8 4087
ff5c2c03
SL		 4088 chip = memdup_user(argp, sizeof(*chip));
4089 if (IS_ERR(chip)) {
4090 r = PTR_ERR(chip);
1fe779f8 4091 goto out;
ff5c2c03
SL		 4092 }
4093
1fe779f8 4094 r = -ENXIO;
826da321 4095 if (!irqchip_kernel(kvm))
f0d66275
DH		 4096 goto set_irqchip_out;
4097 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4098 if (r)
f0d66275 4099 goto set_irqchip_out;
1fe779f8 4100 r = 0;
f0d66275
DH		 4101 set_irqchip_out:
4102 kfree(chip);
1fe779f8
CO		 4103 break;
4104 }
e0f63cb9 4105 case KVM_GET_PIT: {
e0f63cb9 4106 r = -EFAULT;
f0d66275 4107 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4108 goto out;
4109 r = -ENXIO;
4110 if (!kvm->arch.vpit)
4111 goto out;
f0d66275 4112 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4113 if (r)
4114 goto out;
4115 r = -EFAULT;
f0d66275 4116 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4117 goto out;
4118 r = 0;
4119 break;
4120 }
4121 case KVM_SET_PIT: {
e0f63cb9 4122 r = -EFAULT;
f0d66275 4123 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4124 goto out;
4125 r = -ENXIO;
4126 if (!kvm->arch.vpit)
4127 goto out;
f0d66275 4128 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4129 break;
4130 }
e9f42757
BK		 4131 case KVM_GET_PIT2: {
4132 r = -ENXIO;
4133 if (!kvm->arch.vpit)
4134 goto out;
4135 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4136 if (r)
4137 goto out;
4138 r = -EFAULT;
4139 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4140 goto out;
4141 r = 0;
4142 break;
4143 }
4144 case KVM_SET_PIT2: {
4145 r = -EFAULT;
4146 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4147 goto out;
4148 r = -ENXIO;
4149 if (!kvm->arch.vpit)
4150 goto out;
4151 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4152 break;
4153 }
52d939a0
MT		 4154 case KVM_REINJECT_CONTROL: {
4155 struct kvm_reinject_control control;
4156 r = -EFAULT;
4157 if (copy_from_user(&control, argp, sizeof(control)))
4158 goto out;
4159 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4160 break;
4161 }
d71ba788
PB		 4162 case KVM_SET_BOOT_CPU_ID:
4163 r = 0;
4164 mutex_lock(&kvm->lock);
557abc40 4165 if (kvm->created_vcpus)
d71ba788
PB		 4166 r = -EBUSY;
4167 else
4168 kvm->arch.bsp_vcpu_id = arg;
4169 mutex_unlock(&kvm->lock);
4170 break;
ffde22ac
ES		 4171 case KVM_XEN_HVM_CONFIG: {
4172 r = -EFAULT;
4173 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4174 sizeof(struct kvm_xen_hvm_config)))
4175 goto out;
4176 r = -EINVAL;
4177 if (kvm->arch.xen_hvm_config.flags)
4178 goto out;
4179 r = 0;
4180 break;
4181 }
afbcf7ab 4182 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4183 struct kvm_clock_data user_ns;
4184 u64 now_ns;
afbcf7ab
GC		 4185
4186 r = -EFAULT;
4187 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4188 goto out;
4189
4190 r = -EINVAL;
4191 if (user_ns.flags)
4192 goto out;
4193
4194 r = 0;
395c6b0a 4195 local_irq_disable();
108b249c
PB		 4196 now_ns = __get_kvmclock_ns(kvm);
4197 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
395c6b0a 4198 local_irq_enable();
2e762ff7 4199 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4200 break;
4201 }
4202 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4203 struct kvm_clock_data user_ns;
4204 u64 now_ns;
4205
e3fd9a93
PB		 4206 local_irq_disable();
4207 now_ns = __get_kvmclock_ns(kvm);
108b249c 4208 user_ns.clock = now_ns;
e3fd9a93
PB		 4209 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4210 local_irq_enable();
97e69aa6 4211 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4212
4213 r = -EFAULT;
4214 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4215 goto out;
4216 r = 0;
4217 break;
4218 }
90de4a18
NA		 4219 case KVM_ENABLE_CAP: {
4220 struct kvm_enable_cap cap;
afbcf7ab 4221
90de4a18
NA		 4222 r = -EFAULT;
4223 if (copy_from_user(&cap, argp, sizeof(cap)))
4224 goto out;
4225 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4226 break;
4227 }
1fe779f8 4228 default:
c274e03a 4229 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4230 }
4231out:
4232 return r;
4233}
4234
a16b043c 4235static void kvm_init_msr_list(void)
043405e1
CO		 4236{
4237 u32 dummy[2];
4238 unsigned i, j;
4239
62ef68bb 4240 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4241 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4242 continue;
93c4adc7
PB		 4243
4244 /*
4245 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4246 * to the guests in some cases.
93c4adc7
PB		 4247 */
4248 switch (msrs_to_save[i]) {
4249 case MSR_IA32_BNDCFGS:
4250 if (!kvm_x86_ops->mpx_supported())
4251 continue;
4252 break;
9dbe6cf9
PB		 4253 case MSR_TSC_AUX:
4254 if (!kvm_x86_ops->rdtscp_supported())
4255 continue;
4256 break;
93c4adc7
PB		 4257 default:
4258 break;
4259 }
4260
043405e1
CO		 4261 if (j < i)
4262 msrs_to_save[j] = msrs_to_save[i];
4263 j++;
4264 }
4265 num_msrs_to_save = j;
62ef68bb
PB		 4266
4267 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4268 switch (emulated_msrs[i]) {
6d396b55
PB		 4269 case MSR_IA32_SMBASE:
4270 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4271 continue;
4272 break;
62ef68bb
PB		 4273 default:
4274 break;
4275 }
4276
4277 if (j < i)
4278 emulated_msrs[j] = emulated_msrs[i];
4279 j++;
4280 }
4281 num_emulated_msrs = j;
043405e1
CO		 4282}
4283
bda9020e
MT		 4284static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4285 const void *v)
bbd9b64e 4286{
70252a10
AK		 4287 int handled = 0;
4288 int n;
4289
4290 do {
4291 n = min(len, 8);
bce87cce 4292 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4293 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4294 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4295 break;
4296 handled += n;
4297 addr += n;
4298 len -= n;
4299 v += n;
4300 } while (len);
bbd9b64e 4301
70252a10 4302 return handled;
bbd9b64e
CO		 4303}
4304
bda9020e 4305static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4306{
70252a10
AK		 4307 int handled = 0;
4308 int n;
4309
4310 do {
4311 n = min(len, 8);
bce87cce 4312 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4313 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4314 addr, n, v))
4315 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4316 break;
4317 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4318 handled += n;
4319 addr += n;
4320 len -= n;
4321 v += n;
4322 } while (len);
bbd9b64e 4323
70252a10 4324 return handled;
bbd9b64e
CO		 4325}
4326
2dafc6c2
GN		 4327static void kvm_set_segment(struct kvm_vcpu *vcpu,
4328 struct kvm_segment *var, int seg)
4329{
4330 kvm_x86_ops->set_segment(vcpu, var, seg);
4331}
4332
4333void kvm_get_segment(struct kvm_vcpu *vcpu,
4334 struct kvm_segment *var, int seg)
4335{
4336 kvm_x86_ops->get_segment(vcpu, var, seg);
4337}
4338
54987b7a
PB		 4339gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4340 struct x86_exception *exception)
02f59dc9
JR		 4341{
4342 gpa_t t_gpa;
02f59dc9
JR		 4343
4344 BUG_ON(!mmu_is_nested(vcpu));
4345
4346 /* NPT walks are always user-walks */
4347 access |= PFERR_USER_MASK;
54987b7a 4348 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4349
4350 return t_gpa;
4351}
4352
ab9ae313
AK		 4353gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4354 struct x86_exception *exception)
1871c602
GN		 4355{
4356 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4357 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4358}
4359
ab9ae313
AK		 4360 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4361 struct x86_exception *exception)
1871c602
GN		 4362{
4363 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4364 access |= PFERR_FETCH_MASK;
ab9ae313 4365 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4366}
4367
ab9ae313
AK		 4368gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4369 struct x86_exception *exception)
1871c602
GN		 4370{
4371 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4372 access |= PFERR_WRITE_MASK;
ab9ae313 4373 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4374}
4375
4376/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4377gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4378 struct x86_exception *exception)
1871c602 4379{
ab9ae313 4380 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4381}
4382
4383static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4384 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4385 struct x86_exception *exception)
bbd9b64e
CO		 4386{
4387 void *data = val;
10589a46 4388 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4389
4390 while (bytes) {
14dfe855 4391 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4392 exception);
bbd9b64e 4393 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4394 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4395 int ret;
4396
bcc55cba 4397 if (gpa == UNMAPPED_GVA)
ab9ae313 4398 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4399 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4400 offset, toread);
10589a46 4401 if (ret < 0) {
c3cd7ffa 4402 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4403 goto out;
4404 }
bbd9b64e 4405
77c2002e
IE		 4406 bytes -= toread;
4407 data += toread;
4408 addr += toread;
bbd9b64e 4409 }
10589a46 4410out:
10589a46 4411 return r;
bbd9b64e 4412}
77c2002e 4413
1871c602 4414/* used for instruction fetching */
0f65dd70
AK		 4415static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4416 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4417 struct x86_exception *exception)
1871c602 4418{
0f65dd70 4419 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4420 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4421 unsigned offset;
4422 int ret;
0f65dd70 4423
44583cba
PB		 4424 /* Inline kvm_read_guest_virt_helper for speed. */
4425 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4426 exception);
4427 if (unlikely(gpa == UNMAPPED_GVA))
4428 return X86EMUL_PROPAGATE_FAULT;
4429
4430 offset = addr & (PAGE_SIZE-1);
4431 if (WARN_ON(offset + bytes > PAGE_SIZE))
4432 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4433 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4434 offset, bytes);
44583cba
PB		 4435 if (unlikely(ret < 0))
4436 return X86EMUL_IO_NEEDED;
4437
4438 return X86EMUL_CONTINUE;
1871c602
GN		 4439}
4440
064aea77 4441int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4442 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4443 struct x86_exception *exception)
1871c602 4444{
0f65dd70 4445 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4446 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4447
1871c602 4448 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4449 exception);
1871c602 4450}
064aea77 4451EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4452
0f65dd70
AK		 4453static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4454 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4455 struct x86_exception *exception)
1871c602 4456{
0f65dd70 4457 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4458 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4459}
4460
7a036a6f
RK		 4461static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4462 unsigned long addr, void *val, unsigned int bytes)
4463{
4464 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4465 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4466
4467 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4468}
4469
6a4d7550 4470int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4471 gva_t addr, void *val,
2dafc6c2 4472 unsigned int bytes,
bcc55cba 4473 struct x86_exception *exception)
77c2002e 4474{
0f65dd70 4475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4476 void *data = val;
4477 int r = X86EMUL_CONTINUE;
4478
4479 while (bytes) {
14dfe855
JR		 4480 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4481 PFERR_WRITE_MASK,
ab9ae313 4482 exception);
77c2002e
IE		 4483 unsigned offset = addr & (PAGE_SIZE-1);
4484 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4485 int ret;
4486
bcc55cba 4487 if (gpa == UNMAPPED_GVA)
ab9ae313 4488 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4489 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4490 if (ret < 0) {
c3cd7ffa 4491 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4492 goto out;
4493 }
4494
4495 bytes -= towrite;
4496 data += towrite;
4497 addr += towrite;
4498 }
4499out:
4500 return r;
4501}
6a4d7550 4502EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4503
0f89b207
TL		 4504static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4505 gpa_t gpa, bool write)
4506{
4507 /* For APIC access vmexit */
4508 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4509 return 1;
4510
4511 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4512 trace_vcpu_match_mmio(gva, gpa, write, true);
4513 return 1;
4514 }
4515
4516 return 0;
4517}
4518
af7cc7d1
XG		 4519static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4520 gpa_t *gpa, struct x86_exception *exception,
4521 bool write)
4522{
97d64b78
AK		 4523 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4524 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4525
be94f6b7
HH		 4526 /*
4527 * currently PKRU is only applied to ept enabled guest so
4528 * there is no pkey in EPT page table for L1 guest or EPT
4529 * shadow page table for L2 guest.
4530 */
97d64b78 4531 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4532 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4533 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4534 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4535 (gva & (PAGE_SIZE - 1));
4f022648 4536 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4537 return 1;
4538 }
4539
af7cc7d1
XG		 4540 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4541
4542 if (*gpa == UNMAPPED_GVA)
4543 return -1;
4544
0f89b207 4545 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4546}
4547
3200f405 4548int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4549 const void *val, int bytes)
bbd9b64e
CO		 4550{
4551 int ret;
4552
54bf36aa 4553 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4554 if (ret < 0)
bbd9b64e 4555 return 0;
0eb05bf2 4556 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4557 return 1;
4558}
4559
77d197b2
XG		 4560struct read_write_emulator_ops {
4561 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4562 int bytes);
4563 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4564 void *val, int bytes);
4565 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4566 int bytes, void *val);
4567 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4568 void *val, int bytes);
4569 bool write;
4570};
4571
4572static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4573{
4574 if (vcpu->mmio_read_completed) {
77d197b2 4575 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4576 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4577 vcpu->mmio_read_completed = 0;
4578 return 1;
4579 }
4580
4581 return 0;
4582}
4583
4584static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4585 void *val, int bytes)
4586{
54bf36aa 4587 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4588}
4589
4590static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4591 void *val, int bytes)
4592{
4593 return emulator_write_phys(vcpu, gpa, val, bytes);
4594}
4595
4596static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4597{
4598 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4599 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4600}
4601
4602static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4603 void *val, int bytes)
4604{
4605 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4606 return X86EMUL_IO_NEEDED;
4607}
4608
4609static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4610 void *val, int bytes)
4611{
f78146b0
AK		 4612 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4613
87da7e66 4614 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4615 return X86EMUL_CONTINUE;
4616}
4617
0fbe9b0b 4618static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4619 .read_write_prepare = read_prepare,
4620 .read_write_emulate = read_emulate,
4621 .read_write_mmio = vcpu_mmio_read,
4622 .read_write_exit_mmio = read_exit_mmio,
4623};
4624
0fbe9b0b 4625static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4626 .read_write_emulate = write_emulate,
4627 .read_write_mmio = write_mmio,
4628 .read_write_exit_mmio = write_exit_mmio,
4629 .write = true,
4630};
4631
22388a3c
XG		 4632static int emulator_read_write_onepage(unsigned long addr, void *val,
4633 unsigned int bytes,
4634 struct x86_exception *exception,
4635 struct kvm_vcpu *vcpu,
0fbe9b0b 4636 const struct read_write_emulator_ops *ops)
bbd9b64e 4637{
af7cc7d1
XG		 4638 gpa_t gpa;
4639 int handled, ret;
22388a3c 4640 bool write = ops->write;
f78146b0 4641 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4642 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4643
4644 /*
4645 * If the exit was due to a NPF we may already have a GPA.
4646 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4647 * Note, this cannot be used on string operations since string
4648 * operation using rep will only have the initial GPA from the NPF
4649 * occurred.
4650 */
4651 if (vcpu->arch.gpa_available &&
4652 emulator_can_use_gpa(ctxt) &&
4653 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4654 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4655 gpa = exception->address;
4656 goto mmio;
4657 }
10589a46 4658
22388a3c 4659 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4660
af7cc7d1 4661 if (ret < 0)
bbd9b64e 4662 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4663
4664 /* For APIC access vmexit */
af7cc7d1 4665 if (ret)
bbd9b64e
CO		 4666 goto mmio;
4667
22388a3c 4668 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4669 return X86EMUL_CONTINUE;
4670
4671mmio:
4672 /*
4673 * Is this MMIO handled locally?
4674 */
22388a3c 4675 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4676 if (handled == bytes)
bbd9b64e 4677 return X86EMUL_CONTINUE;
bbd9b64e 4678
70252a10
AK		 4679 gpa += handled;
4680 bytes -= handled;
4681 val += handled;
4682
87da7e66
XG		 4683 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4684 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4685 frag->gpa = gpa;
4686 frag->data = val;
4687 frag->len = bytes;
f78146b0 4688 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4689}
4690
52eb5a6d
XL		 4691static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4692 unsigned long addr,
22388a3c
XG		 4693 void *val, unsigned int bytes,
4694 struct x86_exception *exception,
0fbe9b0b 4695 const struct read_write_emulator_ops *ops)
bbd9b64e 4696{
0f65dd70 4697 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4698 gpa_t gpa;
4699 int rc;
4700
4701 if (ops->read_write_prepare &&
4702 ops->read_write_prepare(vcpu, val, bytes))
4703 return X86EMUL_CONTINUE;
4704
4705 vcpu->mmio_nr_fragments = 0;
0f65dd70 4706
bbd9b64e
CO		 4707 /* Crossing a page boundary? */
4708 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4709 int now;
bbd9b64e
CO		 4710
4711 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4712 rc = emulator_read_write_onepage(addr, val, now, exception,
4713 vcpu, ops);
4714
bbd9b64e
CO		 4715 if (rc != X86EMUL_CONTINUE)
4716 return rc;
4717 addr += now;
bac15531
NA		 4718 if (ctxt->mode != X86EMUL_MODE_PROT64)
4719 addr = (u32)addr;
bbd9b64e
CO		 4720 val += now;
4721 bytes -= now;
4722 }
22388a3c 4723
f78146b0
AK		 4724 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4725 vcpu, ops);
4726 if (rc != X86EMUL_CONTINUE)
4727 return rc;
4728
4729 if (!vcpu->mmio_nr_fragments)
4730 return rc;
4731
4732 gpa = vcpu->mmio_fragments[0].gpa;
4733
4734 vcpu->mmio_needed = 1;
4735 vcpu->mmio_cur_fragment = 0;
4736
87da7e66 4737 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4738 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4739 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4740 vcpu->run->mmio.phys_addr = gpa;
4741
4742 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4743}
4744
4745static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4746 unsigned long addr,
4747 void *val,
4748 unsigned int bytes,
4749 struct x86_exception *exception)
4750{
4751 return emulator_read_write(ctxt, addr, val, bytes,
4752 exception, &read_emultor);
4753}
4754
52eb5a6d 4755static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4756 unsigned long addr,
4757 const void *val,
4758 unsigned int bytes,
4759 struct x86_exception *exception)
4760{
4761 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4762 exception, &write_emultor);
bbd9b64e 4763}
bbd9b64e 4764
daea3e73
AK		 4765#define CMPXCHG_TYPE(t, ptr, old, new) \
4766 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4767
4768#ifdef CONFIG_X86_64
4769# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4770#else
4771# define CMPXCHG64(ptr, old, new) \
9749a6c0 4772 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4773#endif
4774
0f65dd70
AK		 4775static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4776 unsigned long addr,
bbd9b64e
CO		 4777 const void *old,
4778 const void *new,
4779 unsigned int bytes,
0f65dd70 4780 struct x86_exception *exception)
bbd9b64e 4781{
0f65dd70 4782 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4783 gpa_t gpa;
4784 struct page *page;
4785 char *kaddr;
4786 bool exchanged;
2bacc55c 4787
daea3e73
AK		 4788 /* guests cmpxchg8b have to be emulated atomically */
4789 if (bytes > 8 || (bytes & (bytes - 1)))
4790 goto emul_write;
10589a46 4791
daea3e73 4792 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4793
daea3e73
AK		 4794 if (gpa == UNMAPPED_GVA ||
4795 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4796 goto emul_write;
2bacc55c 4797
daea3e73
AK		 4798 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4799 goto emul_write;
72dc67a6 4800
54bf36aa 4801 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4802 if (is_error_page(page))
c19b8bd6 4803 goto emul_write;
72dc67a6 4804
8fd75e12 4805 kaddr = kmap_atomic(page);
daea3e73
AK		 4806 kaddr += offset_in_page(gpa);
4807 switch (bytes) {
4808 case 1:
4809 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4810 break;
4811 case 2:
4812 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4813 break;
4814 case 4:
4815 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4816 break;
4817 case 8:
4818 exchanged = CMPXCHG64(kaddr, old, new);
4819 break;
4820 default:
4821 BUG();
2bacc55c 4822 }
8fd75e12 4823 kunmap_atomic(kaddr);
daea3e73
AK		 4824 kvm_release_page_dirty(page);
4825
4826 if (!exchanged)
4827 return X86EMUL_CMPXCHG_FAILED;
4828
54bf36aa 4829 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4830 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4831
4832 return X86EMUL_CONTINUE;
4a5f48f6 4833
3200f405 4834emul_write:
daea3e73 4835 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4836
0f65dd70 4837 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4838}
4839
cf8f70bf
GN		 4840static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4841{
4842 /* TODO: String I/O for in kernel device */
4843 int r;
4844
4845 if (vcpu->arch.pio.in)
e32edf4f 4846 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4847 vcpu->arch.pio.size, pd);
4848 else
e32edf4f 4849 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4850 vcpu->arch.pio.port, vcpu->arch.pio.size,
4851 pd);
4852 return r;
4853}
4854
6f6fbe98
XG		 4855static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4856 unsigned short port, void *val,
4857 unsigned int count, bool in)
cf8f70bf 4858{
cf8f70bf 4859 vcpu->arch.pio.port = port;
6f6fbe98 4860 vcpu->arch.pio.in = in;
7972995b 4861 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4862 vcpu->arch.pio.size = size;
4863
4864 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4865 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4866 return 1;
4867 }
4868
4869 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4870 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4871 vcpu->run->io.size = size;
4872 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4873 vcpu->run->io.count = count;
4874 vcpu->run->io.port = port;
4875
4876 return 0;
4877}
4878
6f6fbe98
XG		 4879static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4880 int size, unsigned short port, void *val,
4881 unsigned int count)
cf8f70bf 4882{
ca1d4a9e 4883 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4884 int ret;
ca1d4a9e 4885
6f6fbe98
XG		 4886 if (vcpu->arch.pio.count)
4887 goto data_avail;
cf8f70bf 4888
6f6fbe98
XG		 4889 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4890 if (ret) {
4891data_avail:
4892 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4893 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4894 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4895 return 1;
4896 }
4897
cf8f70bf
GN		 4898 return 0;
4899}
4900
6f6fbe98
XG		 4901static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4902 int size, unsigned short port,
4903 const void *val, unsigned int count)
4904{
4905 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4906
4907 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4908 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4909 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4910}
4911
bbd9b64e
CO		 4912static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4913{
4914 return kvm_x86_ops->get_segment_base(vcpu, seg);
4915}
4916
3cb16fe7 4917static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4918{
3cb16fe7 4919 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4920}
4921
ae6a2375 4922static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4923{
4924 if (!need_emulate_wbinvd(vcpu))
4925 return X86EMUL_CONTINUE;
4926
4927 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4928 int cpu = get_cpu();
4929
4930 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4931 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4932 wbinvd_ipi, NULL, 1);
2eec7343 4933 put_cpu();
f5f48ee1 4934 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4935 } else
4936 wbinvd();
f5f48ee1
SY		 4937 return X86EMUL_CONTINUE;
4938}
5cb56059
JS		 4939
4940int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4941{
6affcbed
KH		 4942 kvm_emulate_wbinvd_noskip(vcpu);
4943 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4944}
f5f48ee1
SY		 4945EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4946
5cb56059
JS		 4947
4948
bcaf5cc5
AK		 4949static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4950{
5cb56059 4951 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4952}
4953
52eb5a6d
XL		 4954static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4955 unsigned long *dest)
bbd9b64e 4956{
16f8a6f9 4957 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4958}
4959
52eb5a6d
XL		 4960static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4961 unsigned long value)
bbd9b64e 4962{
338dbc97 4963
717746e3 4964 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4965}
4966
52a46617 4967static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4968{
52a46617 4969 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4970}
4971
717746e3 4972static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4973{
717746e3 4974 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4975 unsigned long value;
4976
4977 switch (cr) {
4978 case 0:
4979 value = kvm_read_cr0(vcpu);
4980 break;
4981 case 2:
4982 value = vcpu->arch.cr2;
4983 break;
4984 case 3:
9f8fe504 4985 value = kvm_read_cr3(vcpu);
52a46617
GN		 4986 break;
4987 case 4:
4988 value = kvm_read_cr4(vcpu);
4989 break;
4990 case 8:
4991 value = kvm_get_cr8(vcpu);
4992 break;
4993 default:
a737f256 4994 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4995 return 0;
4996 }
4997
4998 return value;
4999}
5000
717746e3 5001static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5002{
717746e3 5003 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5004 int res = 0;
5005
52a46617
GN		 5006 switch (cr) {
5007 case 0:
49a9b07e 5008 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5009 break;
5010 case 2:
5011 vcpu->arch.cr2 = val;
5012 break;
5013 case 3:
2390218b 5014 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5015 break;
5016 case 4:
a83b29c6 5017 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5018 break;
5019 case 8:
eea1cff9 5020 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5021 break;
5022 default:
a737f256 5023 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5024 res = -1;
52a46617 5025 }
0f12244f
GN		 5026
5027 return res;
52a46617
GN		 5028}
5029
717746e3 5030static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5031{
717746e3 5032 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5033}
5034
4bff1e86 5035static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5036{
4bff1e86 5037 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5038}
5039
4bff1e86 5040static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5041{
4bff1e86 5042 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5043}
5044
1ac9d0cf
AK		 5045static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5046{
5047 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5048}
5049
5050static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5051{
5052 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5053}
5054
4bff1e86
AK		 5055static unsigned long emulator_get_cached_segment_base(
5056 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5057{
4bff1e86 5058 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5059}
5060
1aa36616
AK		 5061static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5062 struct desc_struct *desc, u32 *base3,
5063 int seg)
2dafc6c2
GN		 5064{
5065 struct kvm_segment var;
5066
4bff1e86 5067 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5068 *selector = var.selector;
2dafc6c2 5069
378a8b09
GN		 5070 if (var.unusable) {
5071 memset(desc, 0, sizeof(*desc));
2dafc6c2 5072 return false;
378a8b09 5073 }
2dafc6c2
GN		 5074
5075 if (var.g)
5076 var.limit >>= 12;
5077 set_desc_limit(desc, var.limit);
5078 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5079#ifdef CONFIG_X86_64
5080 if (base3)
5081 *base3 = var.base >> 32;
5082#endif
2dafc6c2
GN		 5083 desc->type = var.type;
5084 desc->s = var.s;
5085 desc->dpl = var.dpl;
5086 desc->p = var.present;
5087 desc->avl = var.avl;
5088 desc->l = var.l;
5089 desc->d = var.db;
5090 desc->g = var.g;
5091
5092 return true;
5093}
5094
1aa36616
AK		 5095static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5096 struct desc_struct *desc, u32 base3,
5097 int seg)
2dafc6c2 5098{
4bff1e86 5099 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5100 struct kvm_segment var;
5101
1aa36616 5102 var.selector = selector;
2dafc6c2 5103 var.base = get_desc_base(desc);
5601d05b
GN		 5104#ifdef CONFIG_X86_64
5105 var.base |= ((u64)base3) << 32;
5106#endif
2dafc6c2
GN		 5107 var.limit = get_desc_limit(desc);
5108 if (desc->g)
5109 var.limit = (var.limit << 12) | 0xfff;
5110 var.type = desc->type;
2dafc6c2
GN		 5111 var.dpl = desc->dpl;
5112 var.db = desc->d;
5113 var.s = desc->s;
5114 var.l = desc->l;
5115 var.g = desc->g;
5116 var.avl = desc->avl;
5117 var.present = desc->p;
5118 var.unusable = !var.present;
5119 var.padding = 0;
5120
5121 kvm_set_segment(vcpu, &var, seg);
5122 return;
5123}
5124
717746e3
AK		 5125static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5126 u32 msr_index, u64 *pdata)
5127{
609e36d3
PB		 5128 struct msr_data msr;
5129 int r;
5130
5131 msr.index = msr_index;
5132 msr.host_initiated = false;
5133 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5134 if (r)
5135 return r;
5136
5137 *pdata = msr.data;
5138 return 0;
717746e3
AK		 5139}
5140
5141static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5142 u32 msr_index, u64 data)
5143{
8fe8ab46
WA		 5144 struct msr_data msr;
5145
5146 msr.data = data;
5147 msr.index = msr_index;
5148 msr.host_initiated = false;
5149 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5150}
5151
64d60670
PB		 5152static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5153{
5154 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5155
5156 return vcpu->arch.smbase;
5157}
5158
5159static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5160{
5161 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5162
5163 vcpu->arch.smbase = smbase;
5164}
5165
67f4d428
NA		 5166static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5167 u32 pmc)
5168{
c6702c9d 5169 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5170}
5171
222d21aa
AK		 5172static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5173 u32 pmc, u64 *pdata)
5174{
c6702c9d 5175 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5176}
5177
6c3287f7
AK		 5178static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5179{
5180 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5181}
5182
5037f6f3
AK		 5183static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5184{
5185 preempt_disable();
5197b808 5186 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5187}
5188
5189static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5190{
5191 preempt_enable();
5192}
5193
2953538e 5194static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5195 struct x86_instruction_info *info,
c4f035c6
AK		 5196 enum x86_intercept_stage stage)
5197{
2953538e 5198 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5199}
5200
0017f93a 5201static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5202 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5203{
0017f93a 5204 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5205}
5206
dd856efa
AK		 5207static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5208{
5209 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5210}
5211
5212static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5213{
5214 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5215}
5216
801806d9
NA		 5217static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5218{
5219 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5220}
5221
0225fb50 5222static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5223 .read_gpr = emulator_read_gpr,
5224 .write_gpr = emulator_write_gpr,
1871c602 5225 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5226 .write_std = kvm_write_guest_virt_system,
7a036a6f 5227 .read_phys = kvm_read_guest_phys_system,
1871c602 5228 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5229 .read_emulated = emulator_read_emulated,
5230 .write_emulated = emulator_write_emulated,
5231 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5232 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5233 .pio_in_emulated = emulator_pio_in_emulated,
5234 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5235 .get_segment = emulator_get_segment,
5236 .set_segment = emulator_set_segment,
5951c442 5237 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5238 .get_gdt = emulator_get_gdt,
160ce1f1 5239 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5240 .set_gdt = emulator_set_gdt,
5241 .set_idt = emulator_set_idt,
52a46617
GN		 5242 .get_cr = emulator_get_cr,
5243 .set_cr = emulator_set_cr,
9c537244 5244 .cpl = emulator_get_cpl,
35aa5375
GN		 5245 .get_dr = emulator_get_dr,
5246 .set_dr = emulator_set_dr,
64d60670
PB		 5247 .get_smbase = emulator_get_smbase,
5248 .set_smbase = emulator_set_smbase,
717746e3
AK		 5249 .set_msr = emulator_set_msr,
5250 .get_msr = emulator_get_msr,
67f4d428 5251 .check_pmc = emulator_check_pmc,
222d21aa 5252 .read_pmc = emulator_read_pmc,
6c3287f7 5253 .halt = emulator_halt,
bcaf5cc5 5254 .wbinvd = emulator_wbinvd,
d6aa1000 5255 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5256 .get_fpu = emulator_get_fpu,
5257 .put_fpu = emulator_put_fpu,
c4f035c6 5258 .intercept = emulator_intercept,
bdb42f5a 5259 .get_cpuid = emulator_get_cpuid,
801806d9 5260 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5261};
5262
95cb2295
GN		 5263static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5264{
37ccdcbe 5265 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5266 /*
5267 * an sti; sti; sequence only disable interrupts for the first
5268 * instruction. So, if the last instruction, be it emulated or
5269 * not, left the system with the INT_STI flag enabled, it
5270 * means that the last instruction is an sti. We should not
5271 * leave the flag on in this case. The same goes for mov ss
5272 */
37ccdcbe
PB		 5273 if (int_shadow & mask)
5274 mask = 0;
6addfc42 5275 if (unlikely(int_shadow || mask)) {
95cb2295 5276 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5277 if (!mask)
5278 kvm_make_request(KVM_REQ_EVENT, vcpu);
5279 }
95cb2295
GN		 5280}
5281
ef54bcfe 5282static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5283{
5284 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5285 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5286 return kvm_propagate_fault(vcpu, &ctxt->exception);
5287
5288 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5289 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5290 ctxt->exception.error_code);
54b8486f 5291 else
da9cb575 5292 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5293 return false;
54b8486f
GN		 5294}
5295
8ec4722d
MG		 5296static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5297{
adf52235 5298 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5299 int cs_db, cs_l;
5300
8ec4722d
MG		 5301 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5302
adf52235
TY		 5303 ctxt->eflags = kvm_get_rflags(vcpu);
5304 ctxt->eip = kvm_rip_read(vcpu);
5305 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5306 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5307 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5308 cs_db ? X86EMUL_MODE_PROT32 :
5309 X86EMUL_MODE_PROT16;
a584539b 5310 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5311 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5312 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5313 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5314
dd856efa 5315 init_decode_cache(ctxt);
7ae441ea 5316 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5317}
5318
71f9833b 5319int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5320{
9d74191a 5321 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5322 int ret;
5323
5324 init_emulate_ctxt(vcpu);
5325
9dac77fa
AK		 5326 ctxt->op_bytes = 2;
5327 ctxt->ad_bytes = 2;
5328 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5329 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5330
5331 if (ret != X86EMUL_CONTINUE)
5332 return EMULATE_FAIL;
5333
9dac77fa 5334 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5335 kvm_rip_write(vcpu, ctxt->eip);
5336 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5337
5338 if (irq == NMI_VECTOR)
7460fb4a 5339 vcpu->arch.nmi_pending = 0;
63995653
MG		 5340 else
5341 vcpu->arch.interrupt.pending = false;
5342
5343 return EMULATE_DONE;
5344}
5345EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5346
6d77dbfc
GN		 5347static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5348{
fc3a9157
JR		 5349 int r = EMULATE_DONE;
5350
6d77dbfc
GN		 5351 ++vcpu->stat.insn_emulation_fail;
5352 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5353 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5354 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5355 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5356 vcpu->run->internal.ndata = 0;
5357 r = EMULATE_FAIL;
5358 }
6d77dbfc 5359 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5360
5361 return r;
6d77dbfc
GN		 5362}
5363
93c05d3e 5364static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5365 bool write_fault_to_shadow_pgtable,
5366 int emulation_type)
a6f177ef 5367{
95b3cf69 5368 gpa_t gpa = cr2;
ba049e93 5369 kvm_pfn_t pfn;
a6f177ef 5370
991eebf9
GN		 5371 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5372 return false;
5373
95b3cf69
XG		 5374 if (!vcpu->arch.mmu.direct_map) {
5375 /*
5376 * Write permission should be allowed since only
5377 * write access need to be emulated.
5378 */
5379 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5380
95b3cf69
XG		 5381 /*
5382 * If the mapping is invalid in guest, let cpu retry
5383 * it to generate fault.
5384 */
5385 if (gpa == UNMAPPED_GVA)
5386 return true;
5387 }
a6f177ef 5388
8e3d9d06
XG		 5389 /*
5390 * Do not retry the unhandleable instruction if it faults on the
5391 * readonly host memory, otherwise it will goto a infinite loop:
5392 * retry instruction -> write #PF -> emulation fail -> retry
5393 * instruction -> ...
5394 */
5395 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5396
5397 /*
5398 * If the instruction failed on the error pfn, it can not be fixed,
5399 * report the error to userspace.
5400 */
5401 if (is_error_noslot_pfn(pfn))
5402 return false;
5403
5404 kvm_release_pfn_clean(pfn);
5405
5406 /* The instructions are well-emulated on direct mmu. */
5407 if (vcpu->arch.mmu.direct_map) {
5408 unsigned int indirect_shadow_pages;
5409
5410 spin_lock(&vcpu->kvm->mmu_lock);
5411 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5412 spin_unlock(&vcpu->kvm->mmu_lock);
5413
5414 if (indirect_shadow_pages)
5415 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5416
a6f177ef 5417 return true;
8e3d9d06 5418 }
a6f177ef 5419
95b3cf69
XG		 5420 /*
5421 * if emulation was due to access to shadowed page table
5422 * and it failed try to unshadow page and re-enter the
5423 * guest to let CPU execute the instruction.
5424 */
5425 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5426
5427 /*
5428 * If the access faults on its page table, it can not
5429 * be fixed by unprotecting shadow page and it should
5430 * be reported to userspace.
5431 */
5432 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5433}
5434
1cb3f3ae
XG		 5435static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5436 unsigned long cr2, int emulation_type)
5437{
5438 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5439 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5440
5441 last_retry_eip = vcpu->arch.last_retry_eip;
5442 last_retry_addr = vcpu->arch.last_retry_addr;
5443
5444 /*
5445 * If the emulation is caused by #PF and it is non-page_table
5446 * writing instruction, it means the VM-EXIT is caused by shadow
5447 * page protected, we can zap the shadow page and retry this
5448 * instruction directly.
5449 *
5450 * Note: if the guest uses a non-page-table modifying instruction
5451 * on the PDE that points to the instruction, then we will unmap
5452 * the instruction and go to an infinite loop. So, we cache the
5453 * last retried eip and the last fault address, if we meet the eip
5454 * and the address again, we can break out of the potential infinite
5455 * loop.
5456 */
5457 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5458
5459 if (!(emulation_type & EMULTYPE_RETRY))
5460 return false;
5461
5462 if (x86_page_table_writing_insn(ctxt))
5463 return false;
5464
5465 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5466 return false;
5467
5468 vcpu->arch.last_retry_eip = ctxt->eip;
5469 vcpu->arch.last_retry_addr = cr2;
5470
5471 if (!vcpu->arch.mmu.direct_map)
5472 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5473
22368028 5474 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5475
5476 return true;
5477}
5478
716d51ab
GN		 5479static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5480static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5481
64d60670 5482static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5483{
64d60670 5484 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5485 /* This is a good place to trace that we are exiting SMM. */
5486 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5487
c43203ca
PB		 5488 /* Process a latched INIT or SMI, if any. */
5489 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5490 }
699023e2
PB		 5491
5492 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5493}
5494
5495static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5496{
5497 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5498
a584539b 5499 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5500
5501 if (changed & HF_SMM_MASK)
5502 kvm_smm_changed(vcpu);
a584539b
PB		 5503}
5504
4a1e10d5
PB		 5505static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5506 unsigned long *db)
5507{
5508 u32 dr6 = 0;
5509 int i;
5510 u32 enable, rwlen;
5511
5512 enable = dr7;
5513 rwlen = dr7 >> 16;
5514 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5515 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5516 dr6 |= (1 << i);
5517 return dr6;
5518}
5519
6addfc42 5520static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5521{
5522 struct kvm_run *kvm_run = vcpu->run;
5523
5524 /*
6addfc42
PB		 5525 * rflags is the old, "raw" value of the flags. The new value has
5526 * not been saved yet.
663f4c61
PB		 5527 *
5528 * This is correct even for TF set by the guest, because "the
5529 * processor will not generate this exception after the instruction
5530 * that sets the TF flag".
5531 */
663f4c61
PB		 5532 if (unlikely(rflags & X86_EFLAGS_TF)) {
5533 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5534 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5535 DR6_RTM;
663f4c61
PB		 5536 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5537 kvm_run->debug.arch.exception = DB_VECTOR;
5538 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5539 *r = EMULATE_USER_EXIT;
5540 } else {
663f4c61
PB		 5541 /*
5542 * "Certain debug exceptions may clear bit 0-3. The
5543 * remaining contents of the DR6 register are never
5544 * cleared by the processor".
5545 */
5546 vcpu->arch.dr6 &= ~15;
6f43ed01 5547 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5548 kvm_queue_exception(vcpu, DB_VECTOR);
5549 }
5550 }
5551}
5552
6affcbed
KH		 5553int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5554{
5555 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5556 int r = EMULATE_DONE;
5557
5558 kvm_x86_ops->skip_emulated_instruction(vcpu);
5559 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5560 return r == EMULATE_DONE;
5561}
5562EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5563
4a1e10d5
PB		 5564static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5565{
4a1e10d5
PB		 5566 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5567 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5568 struct kvm_run *kvm_run = vcpu->run;
5569 unsigned long eip = kvm_get_linear_rip(vcpu);
5570 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5571 vcpu->arch.guest_debug_dr7,
5572 vcpu->arch.eff_db);
5573
5574 if (dr6 != 0) {
6f43ed01 5575 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5576 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5577 kvm_run->debug.arch.exception = DB_VECTOR;
5578 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5579 *r = EMULATE_USER_EXIT;
5580 return true;
5581 }
5582 }
5583
4161a569
NA		 5584 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5585 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5586 unsigned long eip = kvm_get_linear_rip(vcpu);
5587 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5588 vcpu->arch.dr7,
5589 vcpu->arch.db);
5590
5591 if (dr6 != 0) {
5592 vcpu->arch.dr6 &= ~15;
6f43ed01 5593 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5594 kvm_queue_exception(vcpu, DB_VECTOR);
5595 *r = EMULATE_DONE;
5596 return true;
5597 }
5598 }
5599
5600 return false;
5601}
5602
51d8b661
AP		 5603int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5604 unsigned long cr2,
dc25e89e
AP		 5605 int emulation_type,
5606 void *insn,
5607 int insn_len)
bbd9b64e 5608{
95cb2295 5609 int r;
9d74191a 5610 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5611 bool writeback = true;
93c05d3e 5612 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5613
93c05d3e
XG		 5614 /*
5615 * Clear write_fault_to_shadow_pgtable here to ensure it is
5616 * never reused.
5617 */
5618 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5619 kvm_clear_exception_queue(vcpu);
8d7d8102 5620
571008da 5621 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5622 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5623
5624 /*
5625 * We will reenter on the same instruction since
5626 * we do not set complete_userspace_io. This does not
5627 * handle watchpoints yet, those would be handled in
5628 * the emulate_ops.
5629 */
5630 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5631 return r;
5632
9d74191a
TY		 5633 ctxt->interruptibility = 0;
5634 ctxt->have_exception = false;
e0ad0b47 5635 ctxt->exception.vector = -1;
9d74191a 5636 ctxt->perm_ok = false;
bbd9b64e 5637
b51e974f 5638 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5639
9d74191a 5640 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5641
e46479f8 5642 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5643 ++vcpu->stat.insn_emulation;
1d2887e2 5644 if (r != EMULATION_OK) {
4005996e
AK		 5645 if (emulation_type & EMULTYPE_TRAP_UD)
5646 return EMULATE_FAIL;
991eebf9
GN		 5647 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5648 emulation_type))
bbd9b64e 5649 return EMULATE_DONE;
6d77dbfc
GN		 5650 if (emulation_type & EMULTYPE_SKIP)
5651 return EMULATE_FAIL;
5652 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5653 }
5654 }
5655
ba8afb6b 5656 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5657 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5658 if (ctxt->eflags & X86_EFLAGS_RF)
5659 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5660 return EMULATE_DONE;
5661 }
5662
1cb3f3ae
XG		 5663 if (retry_instruction(ctxt, cr2, emulation_type))
5664 return EMULATE_DONE;
5665
7ae441ea 5666 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5667 changes registers values during IO operation */
7ae441ea
GN		 5668 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5669 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5670 emulator_invalidate_register_cache(ctxt);
7ae441ea 5671 }
4d2179e1 5672
5cd21917 5673restart:
0f89b207
TL		 5674 /* Save the faulting GPA (cr2) in the address field */
5675 ctxt->exception.address = cr2;
5676
9d74191a 5677 r = x86_emulate_insn(ctxt);
bbd9b64e 5678
775fde86
JR		 5679 if (r == EMULATION_INTERCEPTED)
5680 return EMULATE_DONE;
5681
d2ddd1c4 5682 if (r == EMULATION_FAILED) {
991eebf9
GN		 5683 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5684 emulation_type))
c3cd7ffa
GN		 5685 return EMULATE_DONE;
5686
6d77dbfc 5687 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5688 }
5689
9d74191a 5690 if (ctxt->have_exception) {
d2ddd1c4 5691 r = EMULATE_DONE;
ef54bcfe
PB		 5692 if (inject_emulated_exception(vcpu))
5693 return r;
d2ddd1c4 5694 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5695 if (!vcpu->arch.pio.in) {
5696 /* FIXME: return into emulator if single-stepping. */
3457e419 5697 vcpu->arch.pio.count = 0;
0912c977 5698 } else {
7ae441ea 5699 writeback = false;
716d51ab
GN		 5700 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5701 }
ac0a48c3 5702 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5703 } else if (vcpu->mmio_needed) {
5704 if (!vcpu->mmio_is_write)
5705 writeback = false;
ac0a48c3 5706 r = EMULATE_USER_EXIT;
716d51ab 5707 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5708 } else if (r == EMULATION_RESTART)
5cd21917 5709 goto restart;
d2ddd1c4
GN		 5710 else
5711 r = EMULATE_DONE;
f850e2e6 5712
7ae441ea 5713 if (writeback) {
6addfc42 5714 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5715 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5716 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5717 if (vcpu->arch.hflags != ctxt->emul_flags)
5718 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5719 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5720 if (r == EMULATE_DONE)
6addfc42 5721 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5722 if (!ctxt->have_exception ||
5723 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5724 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5725
5726 /*
5727 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5728 * do nothing, and it will be requested again as soon as
5729 * the shadow expires. But we still need to check here,
5730 * because POPF has no interrupt shadow.
5731 */
5732 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5733 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5734 } else
5735 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5736
5737 return r;
de7d789a 5738}
51d8b661 5739EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5740
cf8f70bf 5741int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5742{
cf8f70bf 5743 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5744 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5745 size, port, &val, 1);
cf8f70bf 5746 /* do not return to emulator after return from userspace */
7972995b 5747 vcpu->arch.pio.count = 0;
de7d789a
CO		 5748 return ret;
5749}
cf8f70bf 5750EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5751
8370c3d0
TL		 5752static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5753{
5754 unsigned long val;
5755
5756 /* We should only ever be called with arch.pio.count equal to 1 */
5757 BUG_ON(vcpu->arch.pio.count != 1);
5758
5759 /* For size less than 4 we merge, else we zero extend */
5760 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5761 : 0;
5762
5763 /*
5764 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5765 * the copy and tracing
5766 */
5767 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5768 vcpu->arch.pio.port, &val, 1);
5769 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5770
5771 return 1;
5772}
5773
5774int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5775{
5776 unsigned long val;
5777 int ret;
5778
5779 /* For size less than 4 we merge, else we zero extend */
5780 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5781
5782 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5783 &val, 1);
5784 if (ret) {
5785 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5786 return ret;
5787 }
5788
5789 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5790
5791 return 0;
5792}
5793EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5794
251a5fd6 5795static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5796{
0a3aee0d 5797 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5798 return 0;
8cfdc000
ZA		 5799}
5800
5801static void tsc_khz_changed(void *data)
c8076604 5802{
8cfdc000
ZA		 5803 struct cpufreq_freqs *freq = data;
5804 unsigned long khz = 0;
5805
5806 if (data)
5807 khz = freq->new;
5808 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5809 khz = cpufreq_quick_get(raw_smp_processor_id());
5810 if (!khz)
5811 khz = tsc_khz;
0a3aee0d 5812 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5813}
5814
c8076604
GH		 5815static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5816 void *data)
5817{
5818 struct cpufreq_freqs *freq = data;
5819 struct kvm *kvm;
5820 struct kvm_vcpu *vcpu;
5821 int i, send_ipi = 0;
5822
8cfdc000
ZA		 5823 /*
5824 * We allow guests to temporarily run on slowing clocks,
5825 * provided we notify them after, or to run on accelerating
5826 * clocks, provided we notify them before. Thus time never
5827 * goes backwards.
5828 *
5829 * However, we have a problem. We can't atomically update
5830 * the frequency of a given CPU from this function; it is
5831 * merely a notifier, which can be called from any CPU.
5832 * Changing the TSC frequency at arbitrary points in time
5833 * requires a recomputation of local variables related to
5834 * the TSC for each VCPU. We must flag these local variables
5835 * to be updated and be sure the update takes place with the
5836 * new frequency before any guests proceed.
5837 *
5838 * Unfortunately, the combination of hotplug CPU and frequency
5839 * change creates an intractable locking scenario; the order
5840 * of when these callouts happen is undefined with respect to
5841 * CPU hotplug, and they can race with each other. As such,
5842 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5843 * undefined; you can actually have a CPU frequency change take
5844 * place in between the computation of X and the setting of the
5845 * variable. To protect against this problem, all updates of
5846 * the per_cpu tsc_khz variable are done in an interrupt
5847 * protected IPI, and all callers wishing to update the value
5848 * must wait for a synchronous IPI to complete (which is trivial
5849 * if the caller is on the CPU already). This establishes the
5850 * necessary total order on variable updates.
5851 *
5852 * Note that because a guest time update may take place
5853 * anytime after the setting of the VCPU's request bit, the
5854 * correct TSC value must be set before the request. However,
5855 * to ensure the update actually makes it to any guest which
5856 * starts running in hardware virtualization between the set
5857 * and the acquisition of the spinlock, we must also ping the
5858 * CPU after setting the request bit.
5859 *
5860 */
5861
c8076604
GH		 5862 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5863 return 0;
5864 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5865 return 0;
8cfdc000
ZA		 5866
5867 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5868
2f303b74 5869 spin_lock(&kvm_lock);
c8076604 5870 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5871 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5872 if (vcpu->cpu != freq->cpu)
5873 continue;
c285545f 5874 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5875 if (vcpu->cpu != smp_processor_id())
8cfdc000 5876 send_ipi = 1;
c8076604
GH		 5877 }
5878 }
2f303b74 5879 spin_unlock(&kvm_lock);
c8076604
GH		 5880
5881 if (freq->old < freq->new && send_ipi) {
5882 /*
5883 * We upscale the frequency. Must make the guest
5884 * doesn't see old kvmclock values while running with
5885 * the new frequency, otherwise we risk the guest sees
5886 * time go backwards.
5887 *
5888 * In case we update the frequency for another cpu
5889 * (which might be in guest context) send an interrupt
5890 * to kick the cpu out of guest context. Next time
5891 * guest context is entered kvmclock will be updated,
5892 * so the guest will not see stale values.
5893 */
8cfdc000 5894 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5895 }
5896 return 0;
5897}
5898
5899static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5900 .notifier_call = kvmclock_cpufreq_notifier
5901};
5902
251a5fd6 5903static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5904{
251a5fd6
SAS		 5905 tsc_khz_changed(NULL);
5906 return 0;
8cfdc000
ZA		 5907}
5908
b820cc0c
ZA		 5909static void kvm_timer_init(void)
5910{
c285545f 5911 max_tsc_khz = tsc_khz;
460dd42e 5912
b820cc0c 5913 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5914#ifdef CONFIG_CPU_FREQ
5915 struct cpufreq_policy policy;
758f588d
BP		 5916 int cpu;
5917
c285545f 5918 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5919 cpu = get_cpu();
5920 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5921 if (policy.cpuinfo.max_freq)
5922 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5923 put_cpu();
c285545f 5924#endif
b820cc0c
ZA		 5925 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5926 CPUFREQ_TRANSITION_NOTIFIER);
5927 }
c285545f 5928 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5929
73c1b41e 5930 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5931 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5932}
5933
ff9d07a0
ZY		 5934static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5935
f5132b01 5936int kvm_is_in_guest(void)
ff9d07a0 5937{
086c9855 5938 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5939}
5940
5941static int kvm_is_user_mode(void)
5942{
5943 int user_mode = 3;
dcf46b94 5944
086c9855
AS		 5945 if (__this_cpu_read(current_vcpu))
5946 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5947
ff9d07a0
ZY		 5948 return user_mode != 0;
5949}
5950
5951static unsigned long kvm_get_guest_ip(void)
5952{
5953 unsigned long ip = 0;
dcf46b94 5954
086c9855
AS		 5955 if (__this_cpu_read(current_vcpu))
5956 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5957
ff9d07a0
ZY		 5958 return ip;
5959}
5960
5961static struct perf_guest_info_callbacks kvm_guest_cbs = {
5962 .is_in_guest = kvm_is_in_guest,
5963 .is_user_mode = kvm_is_user_mode,
5964 .get_guest_ip = kvm_get_guest_ip,
5965};
5966
5967void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5968{
086c9855 5969 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5970}
5971EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5972
5973void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5974{
086c9855 5975 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5976}
5977EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5978
ce88decf
XG		 5979static void kvm_set_mmio_spte_mask(void)
5980{
5981 u64 mask;
5982 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5983
5984 /*
5985 * Set the reserved bits and the present bit of an paging-structure
5986 * entry to generate page fault with PFER.RSV = 1.
5987 */
885032b9 5988 /* Mask the reserved physical address bits. */
d1431483 5989 mask = rsvd_bits(maxphyaddr, 51);
885032b9 5990
885032b9 5991 /* Set the present bit. */
ce88decf
XG		 5992 mask |= 1ull;
5993
5994#ifdef CONFIG_X86_64
5995 /*
5996 * If reserved bit is not supported, clear the present bit to disable
5997 * mmio page fault.
5998 */
5999 if (maxphyaddr == 52)
6000 mask &= ~1ull;
6001#endif
6002
6003 kvm_mmu_set_mmio_spte_mask(mask);
6004}
6005
16e8d74d
MT		 6006#ifdef CONFIG_X86_64
6007static void pvclock_gtod_update_fn(struct work_struct *work)
6008{
d828199e
MT		 6009 struct kvm *kvm;
6010
6011 struct kvm_vcpu *vcpu;
6012 int i;
6013
2f303b74 6014 spin_lock(&kvm_lock);
d828199e
MT		 6015 list_for_each_entry(kvm, &vm_list, vm_list)
6016 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6017 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6018 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6019 spin_unlock(&kvm_lock);
16e8d74d
MT		 6020}
6021
6022static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6023
6024/*
6025 * Notification about pvclock gtod data update.
6026 */
6027static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6028 void *priv)
6029{
6030 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6031 struct timekeeper *tk = priv;
6032
6033 update_pvclock_gtod(tk);
6034
6035 /* disable master clock if host does not trust, or does not
6036 * use, TSC clocksource
6037 */
6038 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6039 atomic_read(&kvm_guest_has_master_clock) != 0)
6040 queue_work(system_long_wq, &pvclock_gtod_work);
6041
6042 return 0;
6043}
6044
6045static struct notifier_block pvclock_gtod_notifier = {
6046 .notifier_call = pvclock_gtod_notify,
6047};
6048#endif
6049
f8c16bba 6050int kvm_arch_init(void *opaque)
043405e1 6051{
b820cc0c 6052 int r;
6b61edf7 6053 struct kvm_x86_ops *ops = opaque;
f8c16bba 6054
f8c16bba
ZX		 6055 if (kvm_x86_ops) {
6056 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6057 r = -EEXIST;
6058 goto out;
f8c16bba
ZX		 6059 }
6060
6061 if (!ops->cpu_has_kvm_support()) {
6062 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6063 r = -EOPNOTSUPP;
6064 goto out;
f8c16bba
ZX		 6065 }
6066 if (ops->disabled_by_bios()) {
6067 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6068 r = -EOPNOTSUPP;
6069 goto out;
f8c16bba
ZX		 6070 }
6071
013f6a5d
MT		 6072 r = -ENOMEM;
6073 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6074 if (!shared_msrs) {
6075 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6076 goto out;
6077 }
6078
97db56ce
AK		 6079 r = kvm_mmu_module_init();
6080 if (r)
013f6a5d 6081 goto out_free_percpu;
97db56ce 6082
ce88decf 6083 kvm_set_mmio_spte_mask();
97db56ce 6084
f8c16bba 6085 kvm_x86_ops = ops;
920c8377 6086
7b52345e 6087 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6088 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6089 PT_PRESENT_MASK, 0);
b820cc0c 6090 kvm_timer_init();
c8076604 6091
ff9d07a0
ZY		 6092 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6093
d366bf7e 6094 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6095 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6096
c5cc421b 6097 kvm_lapic_init();
16e8d74d
MT		 6098#ifdef CONFIG_X86_64
6099 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6100#endif
6101
f8c16bba 6102 return 0;
56c6d28a 6103
013f6a5d
MT		 6104out_free_percpu:
6105 free_percpu(shared_msrs);
56c6d28a 6106out:
56c6d28a 6107 return r;
043405e1 6108}
8776e519 6109
f8c16bba
ZX		 6110void kvm_arch_exit(void)
6111{
cef84c30 6112 kvm_lapic_exit();
ff9d07a0
ZY		 6113 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6114
888d256e
JK		 6115 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6116 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6117 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6118 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6119#ifdef CONFIG_X86_64
6120 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6121#endif
f8c16bba 6122 kvm_x86_ops = NULL;
56c6d28a 6123 kvm_mmu_module_exit();
013f6a5d 6124 free_percpu(shared_msrs);
56c6d28a 6125}
f8c16bba 6126
5cb56059 6127int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6128{
6129 ++vcpu->stat.halt_exits;
35754c98 6130 if (lapic_in_kernel(vcpu)) {
a4535290 6131 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6132 return 1;
6133 } else {
6134 vcpu->run->exit_reason = KVM_EXIT_HLT;
6135 return 0;
6136 }
6137}
5cb56059
JS		 6138EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6139
6140int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6141{
6affcbed
KH		 6142 int ret = kvm_skip_emulated_instruction(vcpu);
6143 /*
6144 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6145 * KVM_EXIT_DEBUG here.
6146 */
6147 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6148}
8776e519
HB		 6149EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6150
8ef81a9a 6151#ifdef CONFIG_X86_64
55dd00a7
MT		 6152static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6153 unsigned long clock_type)
6154{
6155 struct kvm_clock_pairing clock_pairing;
6156 struct timespec ts;
80fbd89c 6157 u64 cycle;
55dd00a7
MT		 6158 int ret;
6159
6160 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6161 return -KVM_EOPNOTSUPP;
6162
6163 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6164 return -KVM_EOPNOTSUPP;
6165
6166 clock_pairing.sec = ts.tv_sec;
6167 clock_pairing.nsec = ts.tv_nsec;
6168 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6169 clock_pairing.flags = 0;
6170
6171 ret = 0;
6172 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6173 sizeof(struct kvm_clock_pairing)))
6174 ret = -KVM_EFAULT;
6175
6176 return ret;
6177}
8ef81a9a 6178#endif
55dd00a7 6179
6aef266c
SV		 6180/*
6181 * kvm_pv_kick_cpu_op: Kick a vcpu.
6182 *
6183 * @apicid - apicid of vcpu to be kicked.
6184 */
6185static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6186{
24d2166b 6187 struct kvm_lapic_irq lapic_irq;
6aef266c 6188
24d2166b
R		 6189 lapic_irq.shorthand = 0;
6190 lapic_irq.dest_mode = 0;
6191 lapic_irq.dest_id = apicid;
93bbf0b8 6192 lapic_irq.msi_redir_hint = false;
6aef266c 6193
24d2166b 6194 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6195 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6196}
6197
d62caabb
AS		 6198void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6199{
6200 vcpu->arch.apicv_active = false;
6201 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6202}
6203
8776e519
HB		 6204int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6205{
6206 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6207 int op_64_bit, r;
8776e519 6208
6affcbed 6209 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6210
55cd8e5a
GN		 6211 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6212 return kvm_hv_hypercall(vcpu);
6213
5fdbf976
MT		 6214 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6215 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6216 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6217 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6218 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6219
229456fc 6220 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6221
a449c7aa
NA		 6222 op_64_bit = is_64_bit_mode(vcpu);
6223 if (!op_64_bit) {
8776e519
HB		 6224 nr &= 0xFFFFFFFF;
6225 a0 &= 0xFFFFFFFF;
6226 a1 &= 0xFFFFFFFF;
6227 a2 &= 0xFFFFFFFF;
6228 a3 &= 0xFFFFFFFF;
6229 }
6230
07708c4a
JK		 6231 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6232 ret = -KVM_EPERM;
6233 goto out;
6234 }
6235
8776e519 6236 switch (nr) {
b93463aa
AK		 6237 case KVM_HC_VAPIC_POLL_IRQ:
6238 ret = 0;
6239 break;
6aef266c
SV		 6240 case KVM_HC_KICK_CPU:
6241 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6242 ret = 0;
6243 break;
8ef81a9a 6244#ifdef CONFIG_X86_64
55dd00a7
MT		 6245 case KVM_HC_CLOCK_PAIRING:
6246 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6247 break;
8ef81a9a 6248#endif
8776e519
HB		 6249 default:
6250 ret = -KVM_ENOSYS;
6251 break;
6252 }
07708c4a 6253out:
a449c7aa
NA		 6254 if (!op_64_bit)
6255 ret = (u32)ret;
5fdbf976 6256 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6257 ++vcpu->stat.hypercalls;
2f333bcb 6258 return r;
8776e519
HB		 6259}
6260EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6261
b6785def 6262static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6263{
d6aa1000 6264 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6265 char instruction[3];
5fdbf976 6266 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6267
8776e519 6268 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6269
ce2e852e
DV		 6270 return emulator_write_emulated(ctxt, rip, instruction, 3,
6271 &ctxt->exception);
8776e519
HB		 6272}
6273
851ba692 6274static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6275{
782d422b
MG		 6276 return vcpu->run->request_interrupt_window &&
6277 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6278}
6279
851ba692 6280static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6281{
851ba692
AK		 6282 struct kvm_run *kvm_run = vcpu->run;
6283
91586a3b 6284 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6285 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6286 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6287 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6288 kvm_run->ready_for_interrupt_injection =
6289 pic_in_kernel(vcpu->kvm) ||
782d422b 6290 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6291}
6292
95ba8273
GN		 6293static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6294{
6295 int max_irr, tpr;
6296
6297 if (!kvm_x86_ops->update_cr8_intercept)
6298 return;
6299
bce87cce 6300 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6301 return;
6302
d62caabb
AS		 6303 if (vcpu->arch.apicv_active)
6304 return;
6305
8db3baa2
GN		 6306 if (!vcpu->arch.apic->vapic_addr)
6307 max_irr = kvm_lapic_find_highest_irr(vcpu);
6308 else
6309 max_irr = -1;
95ba8273
GN		 6310
6311 if (max_irr != -1)
6312 max_irr >>= 4;
6313
6314 tpr = kvm_lapic_get_cr8(vcpu);
6315
6316 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6317}
6318
b6b8a145 6319static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6320{
b6b8a145
JK		 6321 int r;
6322
95ba8273 6323 /* try to reinject previous events if any */
b59bb7bd 6324 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6325 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6326 vcpu->arch.exception.has_error_code,
6327 vcpu->arch.exception.error_code);
d6e8c854
NA		 6328
6329 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6330 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6331 X86_EFLAGS_RF);
6332
6bdf0662
NA		 6333 if (vcpu->arch.exception.nr == DB_VECTOR &&
6334 (vcpu->arch.dr7 & DR7_GD)) {
6335 vcpu->arch.dr7 &= ~DR7_GD;
6336 kvm_update_dr7(vcpu);
6337 }
6338
b59bb7bd
GN		 6339 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6340 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6341 vcpu->arch.exception.error_code,
6342 vcpu->arch.exception.reinject);
b6b8a145 6343 return 0;
b59bb7bd
GN		 6344 }
6345
95ba8273
GN		 6346 if (vcpu->arch.nmi_injected) {
6347 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6348 return 0;
95ba8273
GN		 6349 }
6350
6351 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6352 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6353 return 0;
6354 }
6355
6356 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6357 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6358 if (r != 0)
6359 return r;
95ba8273
GN		 6360 }
6361
6362 /* try to inject new event if pending */
c43203ca
PB		 6363 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6364 vcpu->arch.smi_pending = false;
ee2cd4b7 6365 enter_smm(vcpu);
c43203ca 6366 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6367 --vcpu->arch.nmi_pending;
6368 vcpu->arch.nmi_injected = true;
6369 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6370 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6371 /*
6372 * Because interrupts can be injected asynchronously, we are
6373 * calling check_nested_events again here to avoid a race condition.
6374 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6375 * proposal and current concerns. Perhaps we should be setting
6376 * KVM_REQ_EVENT only on certain events and not unconditionally?
6377 */
6378 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6379 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6380 if (r != 0)
6381 return r;
6382 }
95ba8273 6383 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6384 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6385 false);
6386 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6387 }
6388 }
ee2cd4b7 6389
b6b8a145 6390 return 0;
95ba8273
GN		 6391}
6392
7460fb4a
AK		 6393static void process_nmi(struct kvm_vcpu *vcpu)
6394{
6395 unsigned limit = 2;
6396
6397 /*
6398 * x86 is limited to one NMI running, and one NMI pending after it.
6399 * If an NMI is already in progress, limit further NMIs to just one.
6400 * Otherwise, allow two (and we'll inject the first one immediately).
6401 */
6402 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6403 limit = 1;
6404
6405 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6406 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6407 kvm_make_request(KVM_REQ_EVENT, vcpu);
6408}
6409
660a5d51
PB		 6410#define put_smstate(type, buf, offset, val) \
6411 *(type *)((buf) + (offset) - 0x7e00) = val
6412
ee2cd4b7 6413static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6414{
6415 u32 flags = 0;
6416 flags |= seg->g << 23;
6417 flags |= seg->db << 22;
6418 flags |= seg->l << 21;
6419 flags |= seg->avl << 20;
6420 flags |= seg->present << 15;
6421 flags |= seg->dpl << 13;
6422 flags |= seg->s << 12;
6423 flags |= seg->type << 8;
6424 return flags;
6425}
6426
ee2cd4b7 6427static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6428{
6429 struct kvm_segment seg;
6430 int offset;
6431
6432 kvm_get_segment(vcpu, &seg, n);
6433 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6434
6435 if (n < 3)
6436 offset = 0x7f84 + n * 12;
6437 else
6438 offset = 0x7f2c + (n - 3) * 12;
6439
6440 put_smstate(u32, buf, offset + 8, seg.base);
6441 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6442 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6443}
6444
efbb288a 6445#ifdef CONFIG_X86_64
ee2cd4b7 6446static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6447{
6448 struct kvm_segment seg;
6449 int offset;
6450 u16 flags;
6451
6452 kvm_get_segment(vcpu, &seg, n);
6453 offset = 0x7e00 + n * 16;
6454
ee2cd4b7 6455 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6456 put_smstate(u16, buf, offset, seg.selector);
6457 put_smstate(u16, buf, offset + 2, flags);
6458 put_smstate(u32, buf, offset + 4, seg.limit);
6459 put_smstate(u64, buf, offset + 8, seg.base);
6460}
efbb288a 6461#endif
660a5d51 6462
ee2cd4b7 6463static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6464{
6465 struct desc_ptr dt;
6466 struct kvm_segment seg;
6467 unsigned long val;
6468 int i;
6469
6470 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6471 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6472 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6473 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6474
6475 for (i = 0; i < 8; i++)
6476 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6477
6478 kvm_get_dr(vcpu, 6, &val);
6479 put_smstate(u32, buf, 0x7fcc, (u32)val);
6480 kvm_get_dr(vcpu, 7, &val);
6481 put_smstate(u32, buf, 0x7fc8, (u32)val);
6482
6483 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6484 put_smstate(u32, buf, 0x7fc4, seg.selector);
6485 put_smstate(u32, buf, 0x7f64, seg.base);
6486 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6487 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6488
6489 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6490 put_smstate(u32, buf, 0x7fc0, seg.selector);
6491 put_smstate(u32, buf, 0x7f80, seg.base);
6492 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6493 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6494
6495 kvm_x86_ops->get_gdt(vcpu, &dt);
6496 put_smstate(u32, buf, 0x7f74, dt.address);
6497 put_smstate(u32, buf, 0x7f70, dt.size);
6498
6499 kvm_x86_ops->get_idt(vcpu, &dt);
6500 put_smstate(u32, buf, 0x7f58, dt.address);
6501 put_smstate(u32, buf, 0x7f54, dt.size);
6502
6503 for (i = 0; i < 6; i++)
ee2cd4b7 6504 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6505
6506 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6507
6508 /* revision id */
6509 put_smstate(u32, buf, 0x7efc, 0x00020000);
6510 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6511}
6512
ee2cd4b7 6513static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6514{
6515#ifdef CONFIG_X86_64
6516 struct desc_ptr dt;
6517 struct kvm_segment seg;
6518 unsigned long val;
6519 int i;
6520
6521 for (i = 0; i < 16; i++)
6522 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6523
6524 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6525 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6526
6527 kvm_get_dr(vcpu, 6, &val);
6528 put_smstate(u64, buf, 0x7f68, val);
6529 kvm_get_dr(vcpu, 7, &val);
6530 put_smstate(u64, buf, 0x7f60, val);
6531
6532 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6533 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6534 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6535
6536 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6537
6538 /* revision id */
6539 put_smstate(u32, buf, 0x7efc, 0x00020064);
6540
6541 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6542
6543 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6544 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6545 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6546 put_smstate(u32, buf, 0x7e94, seg.limit);
6547 put_smstate(u64, buf, 0x7e98, seg.base);
6548
6549 kvm_x86_ops->get_idt(vcpu, &dt);
6550 put_smstate(u32, buf, 0x7e84, dt.size);
6551 put_smstate(u64, buf, 0x7e88, dt.address);
6552
6553 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6554 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6555 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6556 put_smstate(u32, buf, 0x7e74, seg.limit);
6557 put_smstate(u64, buf, 0x7e78, seg.base);
6558
6559 kvm_x86_ops->get_gdt(vcpu, &dt);
6560 put_smstate(u32, buf, 0x7e64, dt.size);
6561 put_smstate(u64, buf, 0x7e68, dt.address);
6562
6563 for (i = 0; i < 6; i++)
ee2cd4b7 6564 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6565#else
6566 WARN_ON_ONCE(1);
6567#endif
6568}
6569
ee2cd4b7 6570static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6571{
660a5d51 6572 struct kvm_segment cs, ds;
18c3626e 6573 struct desc_ptr dt;
660a5d51
PB		 6574 char buf[512];
6575 u32 cr0;
6576
660a5d51
PB		 6577 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6578 vcpu->arch.hflags |= HF_SMM_MASK;
6579 memset(buf, 0, 512);
6580 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6581 enter_smm_save_state_64(vcpu, buf);
660a5d51 6582 else
ee2cd4b7 6583 enter_smm_save_state_32(vcpu, buf);
660a5d51 6584
54bf36aa 6585 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6586
6587 if (kvm_x86_ops->get_nmi_mask(vcpu))
6588 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6589 else
6590 kvm_x86_ops->set_nmi_mask(vcpu, true);
6591
6592 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6593 kvm_rip_write(vcpu, 0x8000);
6594
6595 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6596 kvm_x86_ops->set_cr0(vcpu, cr0);
6597 vcpu->arch.cr0 = cr0;
6598
6599 kvm_x86_ops->set_cr4(vcpu, 0);
6600
18c3626e
PB		 6601 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6602 dt.address = dt.size = 0;
6603 kvm_x86_ops->set_idt(vcpu, &dt);
6604
660a5d51
PB		 6605 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6606
6607 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6608 cs.base = vcpu->arch.smbase;
6609
6610 ds.selector = 0;
6611 ds.base = 0;
6612
6613 cs.limit = ds.limit = 0xffffffff;
6614 cs.type = ds.type = 0x3;
6615 cs.dpl = ds.dpl = 0;
6616 cs.db = ds.db = 0;
6617 cs.s = ds.s = 1;
6618 cs.l = ds.l = 0;
6619 cs.g = ds.g = 1;
6620 cs.avl = ds.avl = 0;
6621 cs.present = ds.present = 1;
6622 cs.unusable = ds.unusable = 0;
6623 cs.padding = ds.padding = 0;
6624
6625 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6626 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6627 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6628 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6629 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6630 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6631
6632 if (guest_cpuid_has_longmode(vcpu))
6633 kvm_x86_ops->set_efer(vcpu, 0);
6634
6635 kvm_update_cpuid(vcpu);
6636 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6637}
6638
ee2cd4b7 6639static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6640{
6641 vcpu->arch.smi_pending = true;
6642 kvm_make_request(KVM_REQ_EVENT, vcpu);
6643}
6644
2860c4b1
PB		 6645void kvm_make_scan_ioapic_request(struct kvm *kvm)
6646{
6647 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6648}
6649
3d81bc7e 6650static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6651{
5c919412
AS		 6652 u64 eoi_exit_bitmap[4];
6653
3d81bc7e
YZ		 6654 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6655 return;
c7c9c56c 6656
6308630b 6657 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6658
b053b2ae 6659 if (irqchip_split(vcpu->kvm))
6308630b 6660 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6661 else {
76dfafd5 6662 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6663 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6664 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6665 }
5c919412
AS		 6666 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6667 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6668 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6669}
6670
a70656b6
RK		 6671static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6672{
6673 ++vcpu->stat.tlb_flush;
6674 kvm_x86_ops->tlb_flush(vcpu);
6675}
6676
4256f43f
TC		 6677void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6678{
c24ae0dc
TC		 6679 struct page *page = NULL;
6680
35754c98 6681 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6682 return;
6683
4256f43f
TC		 6684 if (!kvm_x86_ops->set_apic_access_page_addr)
6685 return;
6686
c24ae0dc 6687 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6688 if (is_error_page(page))
6689 return;
c24ae0dc
TC		 6690 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6691
6692 /*
6693 * Do not pin apic access page in memory, the MMU notifier
6694 * will call us again if it is migrated or swapped out.
6695 */
6696 put_page(page);
4256f43f
TC		 6697}
6698EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6699
fe71557a
TC		 6700void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6701 unsigned long address)
6702{
c24ae0dc
TC		 6703 /*
6704 * The physical address of apic access page is stored in the VMCS.
6705 * Update it when it becomes invalid.
6706 */
6707 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6708 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6709}
6710
9357d939 6711/*
362c698f 6712 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6713 * exiting to the userspace. Otherwise, the value will be returned to the
6714 * userspace.
6715 */
851ba692 6716static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6717{
6718 int r;
62a193ed
MG		 6719 bool req_int_win =
6720 dm_request_for_irq_injection(vcpu) &&
6721 kvm_cpu_accept_dm_intr(vcpu);
6722
730dca42 6723 bool req_immediate_exit = false;
b6c7a5dc 6724
3e007509 6725 if (vcpu->requests) {
a8eeb04a 6726 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6727 kvm_mmu_unload(vcpu);
a8eeb04a 6728 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6729 __kvm_migrate_timers(vcpu);
d828199e
MT		 6730 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6731 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6732 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6733 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6734 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6735 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6736 if (unlikely(r))
6737 goto out;
6738 }
a8eeb04a 6739 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6740 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6741 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6742 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6743 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6744 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6745 r = 0;
6746 goto out;
6747 }
a8eeb04a 6748 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6749 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6750 r = 0;
6751 goto out;
6752 }
a8eeb04a 6753 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6754 vcpu->fpu_active = 0;
6755 kvm_x86_ops->fpu_deactivate(vcpu);
6756 }
af585b92
GN		 6757 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6758 /* Page is swapped out. Do synthetic halt */
6759 vcpu->arch.apf.halted = true;
6760 r = 1;
6761 goto out;
6762 }
c9aaa895
GC		 6763 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6764 record_steal_time(vcpu);
64d60670
PB		 6765 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6766 process_smi(vcpu);
7460fb4a
AK		 6767 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6768 process_nmi(vcpu);
f5132b01 6769 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6770 kvm_pmu_handle_event(vcpu);
f5132b01 6771 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6772 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6773 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6774 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6775 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6776 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6777 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6778 vcpu->run->eoi.vector =
6779 vcpu->arch.pending_ioapic_eoi;
6780 r = 0;
6781 goto out;
6782 }
6783 }
3d81bc7e
YZ		 6784 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6785 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6786 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6787 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6788 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6789 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6790 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6791 r = 0;
6792 goto out;
6793 }
e516cebb
AS		 6794 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6795 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6796 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6797 r = 0;
6798 goto out;
6799 }
db397571
AS		 6800 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6801 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6802 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6803 r = 0;
6804 goto out;
6805 }
f3b138c5
AS		 6806
6807 /*
6808 * KVM_REQ_HV_STIMER has to be processed after
6809 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6810 * depend on the guest clock being up-to-date
6811 */
1f4b34f8
AS		 6812 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6813 kvm_hv_process_stimers(vcpu);
2f52d58c 6814 }
b93463aa 6815
bf9f6ac8
FW		 6816 /*
6817 * KVM_REQ_EVENT is not set when posted interrupts are set by
6818 * VT-d hardware, so we have to update RVI unconditionally.
6819 */
6820 if (kvm_lapic_enabled(vcpu)) {
6821 /*
6822 * Update architecture specific hints for APIC
6823 * virtual interrupt delivery.
6824 */
76dfafd5 6825 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
3d92789f 6826 kvm_x86_ops->sync_pir_to_irr(vcpu);
2f52d58c 6827 }
b93463aa 6828
b463a6f7 6829 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6830 ++vcpu->stat.req_event;
66450a21
JK		 6831 kvm_apic_accept_events(vcpu);
6832 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6833 r = 1;
6834 goto out;
6835 }
6836
b6b8a145
JK		 6837 if (inject_pending_event(vcpu, req_int_win) != 0)
6838 req_immediate_exit = true;
321c5658 6839 else {
c43203ca
PB		 6840 /* Enable NMI/IRQ window open exits if needed.
6841 *
6842 * SMIs have two cases: 1) they can be nested, and
6843 * then there is nothing to do here because RSM will
6844 * cause a vmexit anyway; 2) or the SMI can be pending
6845 * because inject_pending_event has completed the
6846 * injection of an IRQ or NMI from the previous vmexit,
6847 * and then we request an immediate exit to inject the SMI.
6848 */
6849 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6850 req_immediate_exit = true;
321c5658
YS		 6851 if (vcpu->arch.nmi_pending)
6852 kvm_x86_ops->enable_nmi_window(vcpu);
6853 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6854 kvm_x86_ops->enable_irq_window(vcpu);
6855 }
b463a6f7
AK		 6856
6857 if (kvm_lapic_enabled(vcpu)) {
6858 update_cr8_intercept(vcpu);
6859 kvm_lapic_sync_to_vapic(vcpu);
6860 }
6861 }
6862
d8368af8
AK		 6863 r = kvm_mmu_reload(vcpu);
6864 if (unlikely(r)) {
d905c069 6865 goto cancel_injection;
d8368af8
AK		 6866 }
6867
b6c7a5dc
HB		 6868 preempt_disable();
6869
6870 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6871 if (vcpu->fpu_active)
6872 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6873 vcpu->mode = IN_GUEST_MODE;
6874
01b71917
MT		 6875 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6876
0f127d12
LT		 6877 /*
6878 * We should set ->mode before check ->requests,
6879 * Please see the comment in kvm_make_all_cpus_request.
6880 * This also orders the write to mode from any reads
6881 * to the page tables done while the VCPU is running.
6882 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6883 */
01b71917 6884 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6885
d94e1dc9 6886 local_irq_disable();
32f88400 6887
6b7e2d09 6888 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6889 || need_resched() || signal_pending(current)) {
6b7e2d09 6890 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6891 smp_wmb();
6c142801
AK		 6892 local_irq_enable();
6893 preempt_enable();
01b71917 6894 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6895 r = 1;
d905c069 6896 goto cancel_injection;
6c142801
AK		 6897 }
6898
fc5b7f3b
DM		 6899 kvm_load_guest_xcr0(vcpu);
6900
c43203ca
PB		 6901 if (req_immediate_exit) {
6902 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6903 smp_send_reschedule(vcpu->cpu);
c43203ca 6904 }
d6185f20 6905
8b89fe1f
PB		 6906 trace_kvm_entry(vcpu->vcpu_id);
6907 wait_lapic_expire(vcpu);
6edaa530 6908 guest_enter_irqoff();
b6c7a5dc 6909
42dbaa5a 6910 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6911 set_debugreg(0, 7);
6912 set_debugreg(vcpu->arch.eff_db[0], 0);
6913 set_debugreg(vcpu->arch.eff_db[1], 1);
6914 set_debugreg(vcpu->arch.eff_db[2], 2);
6915 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6916 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6917 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6918 }
b6c7a5dc 6919
851ba692 6920 kvm_x86_ops->run(vcpu);
b6c7a5dc 6921
c77fb5fe
PB		 6922 /*
6923 * Do this here before restoring debug registers on the host. And
6924 * since we do this before handling the vmexit, a DR access vmexit
6925 * can (a) read the correct value of the debug registers, (b) set
6926 * KVM_DEBUGREG_WONT_EXIT again.
6927 */
6928 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6929 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6930 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6931 kvm_update_dr0123(vcpu);
6932 kvm_update_dr6(vcpu);
6933 kvm_update_dr7(vcpu);
6934 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6935 }
6936
24f1e32c
FW		 6937 /*
6938 * If the guest has used debug registers, at least dr7
6939 * will be disabled while returning to the host.
6940 * If we don't have active breakpoints in the host, we don't
6941 * care about the messed up debug address registers. But if
6942 * we have some of them active, restore the old state.
6943 */
59d8eb53 6944 if (hw_breakpoint_active())
24f1e32c 6945 hw_breakpoint_restore();
42dbaa5a 6946
4ba76538 6947 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6948
6b7e2d09 6949 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6950 smp_wmb();
a547c6db 6951
fc5b7f3b
DM		 6952 kvm_put_guest_xcr0(vcpu);
6953
a547c6db 6954 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6955
6956 ++vcpu->stat.exits;
6957
f2485b3e 6958 guest_exit_irqoff();
b6c7a5dc 6959
f2485b3e 6960 local_irq_enable();
b6c7a5dc
HB		 6961 preempt_enable();
6962
f656ce01 6963 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6964
b6c7a5dc
HB		 6965 /*
6966 * Profile KVM exit RIPs:
6967 */
6968 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6969 unsigned long rip = kvm_rip_read(vcpu);
6970 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6971 }
6972
cc578287
ZA		 6973 if (unlikely(vcpu->arch.tsc_always_catchup))
6974 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6975
5cfb1d5a
MT		 6976 if (vcpu->arch.apic_attention)
6977 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6978
851ba692 6979 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6980 return r;
6981
6982cancel_injection:
6983 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6984 if (unlikely(vcpu->arch.apic_attention))
6985 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6986out:
6987 return r;
6988}
b6c7a5dc 6989
362c698f
PB		 6990static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6991{
bf9f6ac8
FW		 6992 if (!kvm_arch_vcpu_runnable(vcpu) &&
6993 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6994 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6995 kvm_vcpu_block(vcpu);
6996 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6997
6998 if (kvm_x86_ops->post_block)
6999 kvm_x86_ops->post_block(vcpu);
7000
9c8fd1ba
PB		 7001 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7002 return 1;
7003 }
362c698f
PB		 7004
7005 kvm_apic_accept_events(vcpu);
7006 switch(vcpu->arch.mp_state) {
7007 case KVM_MP_STATE_HALTED:
7008 vcpu->arch.pv.pv_unhalted = false;
7009 vcpu->arch.mp_state =
7010 KVM_MP_STATE_RUNNABLE;
7011 case KVM_MP_STATE_RUNNABLE:
7012 vcpu->arch.apf.halted = false;
7013 break;
7014 case KVM_MP_STATE_INIT_RECEIVED:
7015 break;
7016 default:
7017 return -EINTR;
7018 break;
7019 }
7020 return 1;
7021}
09cec754 7022
5d9bc648
PB		 7023static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7024{
0ad3bed6
PB		 7025 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7026 kvm_x86_ops->check_nested_events(vcpu, false);
7027
5d9bc648
PB		 7028 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7029 !vcpu->arch.apf.halted);
7030}
7031
362c698f 7032static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7033{
7034 int r;
f656ce01 7035 struct kvm *kvm = vcpu->kvm;
d7690175 7036
f656ce01 7037 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7038
362c698f 7039 for (;;) {
58f800d5 7040 if (kvm_vcpu_running(vcpu)) {
851ba692 7041 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7042 } else {
362c698f 7043 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7044 }
7045
09cec754
GN		 7046 if (r <= 0)
7047 break;
7048
7049 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
7050 if (kvm_cpu_has_pending_timer(vcpu))
7051 kvm_inject_pending_timer_irqs(vcpu);
7052
782d422b
MG		 7053 if (dm_request_for_irq_injection(vcpu) &&
7054 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7055 r = 0;
7056 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7057 ++vcpu->stat.request_irq_exits;
362c698f 7058 break;
09cec754 7059 }
af585b92
GN		 7060
7061 kvm_check_async_pf_completion(vcpu);
7062
09cec754
GN		 7063 if (signal_pending(current)) {
7064 r = -EINTR;
851ba692 7065 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7066 ++vcpu->stat.signal_exits;
362c698f 7067 break;
09cec754
GN		 7068 }
7069 if (need_resched()) {
f656ce01 7070 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7071 cond_resched();
f656ce01 7072 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7073 }
b6c7a5dc
HB		 7074 }
7075
f656ce01 7076 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7077
7078 return r;
7079}
7080
716d51ab
GN		 7081static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7082{
7083 int r;
7084 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7085 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7086 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7087 if (r != EMULATE_DONE)
7088 return 0;
7089 return 1;
7090}
7091
7092static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7093{
7094 BUG_ON(!vcpu->arch.pio.count);
7095
7096 return complete_emulated_io(vcpu);
7097}
7098
f78146b0
AK		 7099/*
7100 * Implements the following, as a state machine:
7101 *
7102 * read:
7103 * for each fragment
87da7e66
XG		 7104 * for each mmio piece in the fragment
7105 * write gpa, len
7106 * exit
7107 * copy data
f78146b0
AK		 7108 * execute insn
7109 *
7110 * write:
7111 * for each fragment
87da7e66
XG		 7112 * for each mmio piece in the fragment
7113 * write gpa, len
7114 * copy data
7115 * exit
f78146b0 7116 */
716d51ab 7117static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7118{
7119 struct kvm_run *run = vcpu->run;
f78146b0 7120 struct kvm_mmio_fragment *frag;
87da7e66 7121 unsigned len;
5287f194 7122
716d51ab 7123 BUG_ON(!vcpu->mmio_needed);
5287f194 7124
716d51ab 7125 /* Complete previous fragment */
87da7e66
XG		 7126 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7127 len = min(8u, frag->len);
716d51ab 7128 if (!vcpu->mmio_is_write)
87da7e66
XG		 7129 memcpy(frag->data, run->mmio.data, len);
7130
7131 if (frag->len <= 8) {
7132 /* Switch to the next fragment. */
7133 frag++;
7134 vcpu->mmio_cur_fragment++;
7135 } else {
7136 /* Go forward to the next mmio piece. */
7137 frag->data += len;
7138 frag->gpa += len;
7139 frag->len -= len;
7140 }
7141
a08d3b3b 7142 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7143 vcpu->mmio_needed = 0;
0912c977
PB		 7144
7145 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7146 if (vcpu->mmio_is_write)
716d51ab
GN		 7147 return 1;
7148 vcpu->mmio_read_completed = 1;
7149 return complete_emulated_io(vcpu);
7150 }
87da7e66 7151
716d51ab
GN		 7152 run->exit_reason = KVM_EXIT_MMIO;
7153 run->mmio.phys_addr = frag->gpa;
7154 if (vcpu->mmio_is_write)
87da7e66
XG		 7155 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7156 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7157 run->mmio.is_write = vcpu->mmio_is_write;
7158 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7159 return 0;
5287f194
AK		 7160}
7161
716d51ab 7162
b6c7a5dc
HB		 7163int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7164{
c5bedc68 7165 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7166 int r;
7167 sigset_t sigsaved;
7168
c4d72e2d 7169 fpu__activate_curr(fpu);
e5c30142 7170
ac9f6dc0
AK		 7171 if (vcpu->sigset_active)
7172 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7173
a4535290 7174 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7175 kvm_vcpu_block(vcpu);
66450a21 7176 kvm_apic_accept_events(vcpu);
d7690175 7177 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 7178 r = -EAGAIN;
7179 goto out;
b6c7a5dc
HB		 7180 }
7181
b6c7a5dc 7182 /* re-sync apic's tpr */
35754c98 7183 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7184 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7185 r = -EINVAL;
7186 goto out;
7187 }
7188 }
b6c7a5dc 7189
716d51ab
GN		 7190 if (unlikely(vcpu->arch.complete_userspace_io)) {
7191 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7192 vcpu->arch.complete_userspace_io = NULL;
7193 r = cui(vcpu);
7194 if (r <= 0)
7195 goto out;
7196 } else
7197 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7198
362c698f 7199 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7200
7201out:
f1d86e46 7202 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7203 if (vcpu->sigset_active)
7204 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7205
b6c7a5dc
HB		 7206 return r;
7207}
7208
7209int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7210{
7ae441ea
GN		 7211 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7212 /*
7213 * We are here if userspace calls get_regs() in the middle of
7214 * instruction emulation. Registers state needs to be copied
4a969980 7215 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7216 * that usually, but some bad designed PV devices (vmware
7217 * backdoor interface) need this to work
7218 */
dd856efa 7219 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7220 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7221 }
5fdbf976
MT		 7222 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7223 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7224 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7225 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7226 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7227 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7228 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7229 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7230#ifdef CONFIG_X86_64
5fdbf976
MT		 7231 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7232 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7233 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7234 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7235 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7236 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7237 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7238 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7239#endif
7240
5fdbf976 7241 regs->rip = kvm_rip_read(vcpu);
91586a3b 7242 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7243
b6c7a5dc
HB		 7244 return 0;
7245}
7246
7247int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7248{
7ae441ea
GN		 7249 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7250 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7251
5fdbf976
MT		 7252 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7253 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7254 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7255 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7256 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7257 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7258 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7259 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7260#ifdef CONFIG_X86_64
5fdbf976
MT		 7261 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7262 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7263 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7264 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7265 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7266 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7267 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7268 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7269#endif
7270
5fdbf976 7271 kvm_rip_write(vcpu, regs->rip);
91586a3b 7272 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7273
b4f14abd
JK		 7274 vcpu->arch.exception.pending = false;
7275
3842d135
AK		 7276 kvm_make_request(KVM_REQ_EVENT, vcpu);
7277
b6c7a5dc
HB		 7278 return 0;
7279}
7280
b6c7a5dc
HB		 7281void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7282{
7283 struct kvm_segment cs;
7284
3e6e0aab 7285 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7286 *db = cs.db;
7287 *l = cs.l;
7288}
7289EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7290
7291int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7292 struct kvm_sregs *sregs)
7293{
89a27f4d 7294 struct desc_ptr dt;
b6c7a5dc 7295
3e6e0aab
GT		 7296 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7297 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7298 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7299 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7300 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7301 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7302
3e6e0aab
GT		 7303 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7304 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7305
7306 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7307 sregs->idt.limit = dt.size;
7308 sregs->idt.base = dt.address;
b6c7a5dc 7309 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7310 sregs->gdt.limit = dt.size;
7311 sregs->gdt.base = dt.address;
b6c7a5dc 7312
4d4ec087 7313 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7314 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7315 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7316 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7317 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7318 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7319 sregs->apic_base = kvm_get_apic_base(vcpu);
7320
923c61bb 7321 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7322
36752c9b 7323 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7324 set_bit(vcpu->arch.interrupt.nr,
7325 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7326
b6c7a5dc
HB		 7327 return 0;
7328}
7329
62d9f0db
MT		 7330int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7331 struct kvm_mp_state *mp_state)
7332{
66450a21 7333 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7334 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7335 vcpu->arch.pv.pv_unhalted)
7336 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7337 else
7338 mp_state->mp_state = vcpu->arch.mp_state;
7339
62d9f0db
MT		 7340 return 0;
7341}
7342
7343int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7344 struct kvm_mp_state *mp_state)
7345{
bce87cce 7346 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7347 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7348 return -EINVAL;
7349
7350 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7351 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7352 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7353 } else
7354 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7355 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7356 return 0;
7357}
7358
7f3d35fd
KW		 7359int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7360 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7361{
9d74191a 7362 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7363 int ret;
e01c2426 7364
8ec4722d 7365 init_emulate_ctxt(vcpu);
c697518a 7366
7f3d35fd 7367 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7368 has_error_code, error_code);
c697518a 7369
c697518a 7370 if (ret)
19d04437 7371 return EMULATE_FAIL;
37817f29 7372
9d74191a
TY		 7373 kvm_rip_write(vcpu, ctxt->eip);
7374 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7375 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7376 return EMULATE_DONE;
37817f29
IE		 7377}
7378EXPORT_SYMBOL_GPL(kvm_task_switch);
7379
b6c7a5dc
HB		 7380int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7381 struct kvm_sregs *sregs)
7382{
58cb628d 7383 struct msr_data apic_base_msr;
b6c7a5dc 7384 int mmu_reset_needed = 0;
63f42e02 7385 int pending_vec, max_bits, idx;
89a27f4d 7386 struct desc_ptr dt;
b6c7a5dc 7387
6d1068b3
PM		 7388 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7389 return -EINVAL;
7390
89a27f4d
GN		 7391 dt.size = sregs->idt.limit;
7392 dt.address = sregs->idt.base;
b6c7a5dc 7393 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7394 dt.size = sregs->gdt.limit;
7395 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7396 kvm_x86_ops->set_gdt(vcpu, &dt);
7397
ad312c7c 7398 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7399 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7400 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7401 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7402
2d3ad1f4 7403 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7404
f6801dff 7405 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7406 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7407 apic_base_msr.data = sregs->apic_base;
7408 apic_base_msr.host_initiated = true;
7409 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7410
4d4ec087 7411 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7412 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7413 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7414
fc78f519 7415 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7416 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7417 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7418 kvm_update_cpuid(vcpu);
63f42e02
XG		 7419
7420 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7421 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7422 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7423 mmu_reset_needed = 1;
7424 }
63f42e02 7425 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7426
7427 if (mmu_reset_needed)
7428 kvm_mmu_reset_context(vcpu);
7429
a50abc3b 7430 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7431 pending_vec = find_first_bit(
7432 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7433 if (pending_vec < max_bits) {
66fd3f7f 7434 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7435 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7436 }
7437
3e6e0aab
GT		 7438 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7439 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7440 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7441 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7442 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7443 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7444
3e6e0aab
GT		 7445 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7446 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7447
5f0269f5
ME		 7448 update_cr8_intercept(vcpu);
7449
9c3e4aab 7450 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7451 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7452 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7453 !is_protmode(vcpu))
9c3e4aab
MT		 7454 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7455
3842d135
AK		 7456 kvm_make_request(KVM_REQ_EVENT, vcpu);
7457
b6c7a5dc
HB		 7458 return 0;
7459}
7460
d0bfb940
JK		 7461int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7462 struct kvm_guest_debug *dbg)
b6c7a5dc 7463{
355be0b9 7464 unsigned long rflags;
ae675ef0 7465 int i, r;
b6c7a5dc 7466
4f926bf2
JK		 7467 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7468 r = -EBUSY;
7469 if (vcpu->arch.exception.pending)
2122ff5e 7470 goto out;
4f926bf2
JK		 7471 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7472 kvm_queue_exception(vcpu, DB_VECTOR);
7473 else
7474 kvm_queue_exception(vcpu, BP_VECTOR);
7475 }
7476
91586a3b
JK		 7477 /*
7478 * Read rflags as long as potentially injected trace flags are still
7479 * filtered out.
7480 */
7481 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7482
7483 vcpu->guest_debug = dbg->control;
7484 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7485 vcpu->guest_debug = 0;
7486
7487 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7488 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7489 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7490 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7491 } else {
7492 for (i = 0; i < KVM_NR_DB_REGS; i++)
7493 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7494 }
c8639010 7495 kvm_update_dr7(vcpu);
ae675ef0 7496
f92653ee
JK		 7497 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7498 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7499 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7500
91586a3b
JK		 7501 /*
7502 * Trigger an rflags update that will inject or remove the trace
7503 * flags.
7504 */
7505 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7506
a96036b8 7507 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7508
4f926bf2 7509 r = 0;
d0bfb940 7510
2122ff5e 7511out:
b6c7a5dc
HB		 7512
7513 return r;
7514}
7515
8b006791
ZX		 7516/*
7517 * Translate a guest virtual address to a guest physical address.
7518 */
7519int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7520 struct kvm_translation *tr)
7521{
7522 unsigned long vaddr = tr->linear_address;
7523 gpa_t gpa;
f656ce01 7524 int idx;
8b006791 7525
f656ce01 7526 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7527 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7528 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7529 tr->physical_address = gpa;
7530 tr->valid = gpa != UNMAPPED_GVA;
7531 tr->writeable = 1;
7532 tr->usermode = 0;
8b006791
ZX		 7533
7534 return 0;
7535}
7536
d0752060
HB		 7537int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7538{
c47ada30 7539 struct fxregs_state *fxsave =
7366ed77 7540 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7541
d0752060
HB		 7542 memcpy(fpu->fpr, fxsave->st_space, 128);
7543 fpu->fcw = fxsave->cwd;
7544 fpu->fsw = fxsave->swd;
7545 fpu->ftwx = fxsave->twd;
7546 fpu->last_opcode = fxsave->fop;
7547 fpu->last_ip = fxsave->rip;
7548 fpu->last_dp = fxsave->rdp;
7549 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7550
d0752060
HB		 7551 return 0;
7552}
7553
7554int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7555{
c47ada30 7556 struct fxregs_state *fxsave =
7366ed77 7557 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7558
d0752060
HB		 7559 memcpy(fxsave->st_space, fpu->fpr, 128);
7560 fxsave->cwd = fpu->fcw;
7561 fxsave->swd = fpu->fsw;
7562 fxsave->twd = fpu->ftwx;
7563 fxsave->fop = fpu->last_opcode;
7564 fxsave->rip = fpu->last_ip;
7565 fxsave->rdp = fpu->last_dp;
7566 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7567
d0752060
HB		 7568 return 0;
7569}
7570
0ee6a517 7571static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7572{
bf935b0b 7573 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7574 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7575 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7576 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7577
2acf923e
DC		 7578 /*
7579 * Ensure guest xcr0 is valid for loading
7580 */
d91cab78 7581 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7582
ad312c7c 7583 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7584}
d0752060
HB		 7585
7586void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7587{
2608d7a1 7588 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7589 return;
7590
2acf923e
DC		 7591 /*
7592 * Restore all possible states in the guest,
7593 * and assume host would use all available bits.
7594 * Guest xcr0 would be loaded later.
7595 */
d0752060 7596 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7597 __kernel_fpu_begin();
003e2e8b 7598 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7599 trace_kvm_fpu(1);
d0752060 7600}
d0752060
HB		 7601
7602void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7603{
3d42de25 7604 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7605 return;
7606
7607 vcpu->guest_fpu_loaded = 0;
4f836347 7608 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7609 __kernel_fpu_end();
f096ed85 7610 ++vcpu->stat.fpu_reload;
0c04851c 7611 trace_kvm_fpu(0);
d0752060 7612}
e9b11c17
ZX		 7613
7614void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7615{
bd768e14
IY		 7616 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7617
12f9a48f 7618 kvmclock_reset(vcpu);
7f1ea208 7619
e9b11c17 7620 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7621 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7622}
7623
7624struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7625 unsigned int id)
7626{
c447e76b
LL		 7627 struct kvm_vcpu *vcpu;
7628
6755bae8
ZA		 7629 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7630 printk_once(KERN_WARNING
7631 "kvm: SMP vm created on host with unstable TSC; "
7632 "guest TSC will not be reliable\n");
c447e76b
LL		 7633
7634 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7635
c447e76b 7636 return vcpu;
26e5215f 7637}
e9b11c17 7638
26e5215f
AK		 7639int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7640{
7641 int r;
e9b11c17 7642
19efffa2 7643 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7644 r = vcpu_load(vcpu);
7645 if (r)
7646 return r;
d28bc9dd 7647 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7648 kvm_mmu_setup(vcpu);
e9b11c17 7649 vcpu_put(vcpu);
26e5215f 7650 return r;
e9b11c17
ZX		 7651}
7652
31928aa5 7653void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7654{
8fe8ab46 7655 struct msr_data msr;
332967a3 7656 struct kvm *kvm = vcpu->kvm;
42897d86 7657
31928aa5
DD		 7658 if (vcpu_load(vcpu))
7659 return;
8fe8ab46
WA		 7660 msr.data = 0x0;
7661 msr.index = MSR_IA32_TSC;
7662 msr.host_initiated = true;
7663 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7664 vcpu_put(vcpu);
7665
630994b3
MT		 7666 if (!kvmclock_periodic_sync)
7667 return;
7668
332967a3
AJ		 7669 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7670 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7671}
7672
d40ccc62 7673void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7674{
9fc77441 7675 int r;
344d9588
GN		 7676 vcpu->arch.apf.msr_val = 0;
7677
9fc77441
MT		 7678 r = vcpu_load(vcpu);
7679 BUG_ON(r);
e9b11c17
ZX		 7680 kvm_mmu_unload(vcpu);
7681 vcpu_put(vcpu);
7682
7683 kvm_x86_ops->vcpu_free(vcpu);
7684}
7685
d28bc9dd 7686void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7687{
e69fab5d
PB		 7688 vcpu->arch.hflags = 0;
7689
c43203ca 7690 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7691 atomic_set(&vcpu->arch.nmi_queued, 0);
7692 vcpu->arch.nmi_pending = 0;
448fa4a9 7693 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7694 kvm_clear_interrupt_queue(vcpu);
7695 kvm_clear_exception_queue(vcpu);
448fa4a9 7696
42dbaa5a 7697 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7698 kvm_update_dr0123(vcpu);
6f43ed01 7699 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7700 kvm_update_dr6(vcpu);
42dbaa5a 7701 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7702 kvm_update_dr7(vcpu);
42dbaa5a 7703
1119022c
NA		 7704 vcpu->arch.cr2 = 0;
7705
3842d135 7706 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7707 vcpu->arch.apf.msr_val = 0;
c9aaa895 7708 vcpu->arch.st.msr_val = 0;
3842d135 7709
12f9a48f
GC		 7710 kvmclock_reset(vcpu);
7711
af585b92
GN		 7712 kvm_clear_async_pf_completion_queue(vcpu);
7713 kvm_async_pf_hash_reset(vcpu);
7714 vcpu->arch.apf.halted = false;
3842d135 7715
64d60670 7716 if (!init_event) {
d28bc9dd 7717 kvm_pmu_reset(vcpu);
64d60670
PB		 7718 vcpu->arch.smbase = 0x30000;
7719 }
f5132b01 7720
66f7b72e
JS		 7721 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7722 vcpu->arch.regs_avail = ~0;
7723 vcpu->arch.regs_dirty = ~0;
7724
d28bc9dd 7725 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7726}
7727
2b4a273b 7728void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7729{
7730 struct kvm_segment cs;
7731
7732 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7733 cs.selector = vector << 8;
7734 cs.base = vector << 12;
7735 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7736 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7737}
7738
13a34e06 7739int kvm_arch_hardware_enable(void)
e9b11c17 7740{
ca84d1a2
ZA		 7741 struct kvm *kvm;
7742 struct kvm_vcpu *vcpu;
7743 int i;
0dd6a6ed
ZA		 7744 int ret;
7745 u64 local_tsc;
7746 u64 max_tsc = 0;
7747 bool stable, backwards_tsc = false;
18863bdd
AK		 7748
7749 kvm_shared_msr_cpu_online();
13a34e06 7750 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7751 if (ret != 0)
7752 return ret;
7753
4ea1636b 7754 local_tsc = rdtsc();
0dd6a6ed
ZA		 7755 stable = !check_tsc_unstable();
7756 list_for_each_entry(kvm, &vm_list, vm_list) {
7757 kvm_for_each_vcpu(i, vcpu, kvm) {
7758 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7759 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7760 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7761 backwards_tsc = true;
7762 if (vcpu->arch.last_host_tsc > max_tsc)
7763 max_tsc = vcpu->arch.last_host_tsc;
7764 }
7765 }
7766 }
7767
7768 /*
7769 * Sometimes, even reliable TSCs go backwards. This happens on
7770 * platforms that reset TSC during suspend or hibernate actions, but
7771 * maintain synchronization. We must compensate. Fortunately, we can
7772 * detect that condition here, which happens early in CPU bringup,
7773 * before any KVM threads can be running. Unfortunately, we can't
7774 * bring the TSCs fully up to date with real time, as we aren't yet far
7775 * enough into CPU bringup that we know how much real time has actually
108b249c 7776 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7777 * variables that haven't been updated yet.
7778 *
7779 * So we simply find the maximum observed TSC above, then record the
7780 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7781 * the adjustment will be applied. Note that we accumulate
7782 * adjustments, in case multiple suspend cycles happen before some VCPU
7783 * gets a chance to run again. In the event that no KVM threads get a
7784 * chance to run, we will miss the entire elapsed period, as we'll have
7785 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7786 * loose cycle time. This isn't too big a deal, since the loss will be
7787 * uniform across all VCPUs (not to mention the scenario is extremely
7788 * unlikely). It is possible that a second hibernate recovery happens
7789 * much faster than a first, causing the observed TSC here to be
7790 * smaller; this would require additional padding adjustment, which is
7791 * why we set last_host_tsc to the local tsc observed here.
7792 *
7793 * N.B. - this code below runs only on platforms with reliable TSC,
7794 * as that is the only way backwards_tsc is set above. Also note
7795 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7796 * have the same delta_cyc adjustment applied if backwards_tsc
7797 * is detected. Note further, this adjustment is only done once,
7798 * as we reset last_host_tsc on all VCPUs to stop this from being
7799 * called multiple times (one for each physical CPU bringup).
7800 *
4a969980 7801 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7802 * will be compensated by the logic in vcpu_load, which sets the TSC to
7803 * catchup mode. This will catchup all VCPUs to real time, but cannot
7804 * guarantee that they stay in perfect synchronization.
7805 */
7806 if (backwards_tsc) {
7807 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7808 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7809 list_for_each_entry(kvm, &vm_list, vm_list) {
7810 kvm_for_each_vcpu(i, vcpu, kvm) {
7811 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7812 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7813 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7814 }
7815
7816 /*
7817 * We have to disable TSC offset matching.. if you were
7818 * booting a VM while issuing an S4 host suspend....
7819 * you may have some problem. Solving this issue is
7820 * left as an exercise to the reader.
7821 */
7822 kvm->arch.last_tsc_nsec = 0;
7823 kvm->arch.last_tsc_write = 0;
7824 }
7825
7826 }
7827 return 0;
e9b11c17
ZX		 7828}
7829
13a34e06 7830void kvm_arch_hardware_disable(void)
e9b11c17 7831{
13a34e06
RK		 7832 kvm_x86_ops->hardware_disable();
7833 drop_user_return_notifiers();
e9b11c17
ZX		 7834}
7835
7836int kvm_arch_hardware_setup(void)
7837{
9e9c3fe4
NA		 7838 int r;
7839
7840 r = kvm_x86_ops->hardware_setup();
7841 if (r != 0)
7842 return r;
7843
35181e86
HZ		 7844 if (kvm_has_tsc_control) {
7845 /*
7846 * Make sure the user can only configure tsc_khz values that
7847 * fit into a signed integer.
7848 * A min value is not calculated needed because it will always
7849 * be 1 on all machines.
7850 */
7851 u64 max = min(0x7fffffffULL,
7852 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7853 kvm_max_guest_tsc_khz = max;
7854
ad721883 7855 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7856 }
ad721883 7857
9e9c3fe4
NA		 7858 kvm_init_msr_list();
7859 return 0;
e9b11c17
ZX		 7860}
7861
7862void kvm_arch_hardware_unsetup(void)
7863{
7864 kvm_x86_ops->hardware_unsetup();
7865}
7866
7867void kvm_arch_check_processor_compat(void *rtn)
7868{
7869 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7870}
7871
7872bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7873{
7874 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7875}
7876EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7877
7878bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7879{
7880 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7881}
7882
54e9818f 7883struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7884EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7885
e9b11c17
ZX		 7886int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7887{
7888 struct page *page;
7889 struct kvm *kvm;
7890 int r;
7891
7892 BUG_ON(vcpu->kvm == NULL);
7893 kvm = vcpu->kvm;
7894
d62caabb 7895 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7896 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7897 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7898 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7899 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7900 else
a4535290 7901 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7902
7903 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7904 if (!page) {
7905 r = -ENOMEM;
7906 goto fail;
7907 }
ad312c7c 7908 vcpu->arch.pio_data = page_address(page);
e9b11c17 7909
cc578287 7910 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7911
e9b11c17
ZX		 7912 r = kvm_mmu_create(vcpu);
7913 if (r < 0)
7914 goto fail_free_pio_data;
7915
7916 if (irqchip_in_kernel(kvm)) {
7917 r = kvm_create_lapic(vcpu);
7918 if (r < 0)
7919 goto fail_mmu_destroy;
54e9818f
GN		 7920 } else
7921 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7922
890ca9ae
HY		 7923 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7924 GFP_KERNEL);
7925 if (!vcpu->arch.mce_banks) {
7926 r = -ENOMEM;
443c39bc 7927 goto fail_free_lapic;
890ca9ae
HY		 7928 }
7929 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7930
f1797359
WY		 7931 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7932 r = -ENOMEM;
f5f48ee1 7933 goto fail_free_mce_banks;
f1797359 7934 }
f5f48ee1 7935
0ee6a517 7936 fx_init(vcpu);
66f7b72e 7937
ba904635 7938 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7939 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7940
7941 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7942 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7943
5a4f55cd
EK		 7944 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7945
74545705
RK		 7946 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7947
af585b92 7948 kvm_async_pf_hash_reset(vcpu);
f5132b01 7949 kvm_pmu_init(vcpu);
af585b92 7950
1c1a9ce9
SR		 7951 vcpu->arch.pending_external_vector = -1;
7952
5c919412
AS		 7953 kvm_hv_vcpu_init(vcpu);
7954
e9b11c17 7955 return 0;
0ee6a517 7956
f5f48ee1
SY		 7957fail_free_mce_banks:
7958 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7959fail_free_lapic:
7960 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7961fail_mmu_destroy:
7962 kvm_mmu_destroy(vcpu);
7963fail_free_pio_data:
ad312c7c 7964 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7965fail:
7966 return r;
7967}
7968
7969void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7970{
f656ce01
MT		 7971 int idx;
7972
1f4b34f8 7973 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7974 kvm_pmu_destroy(vcpu);
36cb93fd 7975 kfree(vcpu->arch.mce_banks);
e9b11c17 7976 kvm_free_lapic(vcpu);
f656ce01 7977 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7978 kvm_mmu_destroy(vcpu);
f656ce01 7979 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7980 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7981 if (!lapic_in_kernel(vcpu))
54e9818f 7982 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7983}
d19a9cd2 7984
e790d9ef
RK		 7985void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7986{
ae97a3b8 7987 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7988}
7989
e08b9637 7990int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7991{
e08b9637
CO		 7992 if (type)
7993 return -EINVAL;
7994
6ef768fa 7995 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7996 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7997 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7998 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7999 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8000
5550af4d
SY		 8001 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8002 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8003 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8004 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8005 &kvm->arch.irq_sources_bitmap);
5550af4d 8006
038f8c11 8007 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8008 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8009 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8010 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8011
108b249c 8012 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8013 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8014
7e44e449 8015 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8016 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8017
0eb05bf2 8018 kvm_page_track_init(kvm);
13d268ca 8019 kvm_mmu_init_vm(kvm);
0eb05bf2 8020
03543133
SS		 8021 if (kvm_x86_ops->vm_init)
8022 return kvm_x86_ops->vm_init(kvm);
8023
d89f5eff 8024 return 0;
d19a9cd2
ZX		 8025}
8026
8027static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8028{
9fc77441
MT		 8029 int r;
8030 r = vcpu_load(vcpu);
8031 BUG_ON(r);
d19a9cd2
ZX		 8032 kvm_mmu_unload(vcpu);
8033 vcpu_put(vcpu);
8034}
8035
8036static void kvm_free_vcpus(struct kvm *kvm)
8037{
8038 unsigned int i;
988a2cae 8039 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8040
8041 /*
8042 * Unpin any mmu pages first.
8043 */
af585b92
GN		 8044 kvm_for_each_vcpu(i, vcpu, kvm) {
8045 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8046 kvm_unload_vcpu_mmu(vcpu);
af585b92 8047 }
988a2cae
GN		 8048 kvm_for_each_vcpu(i, vcpu, kvm)
8049 kvm_arch_vcpu_free(vcpu);
8050
8051 mutex_lock(&kvm->lock);
8052 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8053 kvm->vcpus[i] = NULL;
d19a9cd2 8054
988a2cae
GN		 8055 atomic_set(&kvm->online_vcpus, 0);
8056 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8057}
8058
ad8ba2cd
SY		 8059void kvm_arch_sync_events(struct kvm *kvm)
8060{
332967a3 8061 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8062 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 8063 kvm_free_all_assigned_devices(kvm);
aea924f6 8064 kvm_free_pit(kvm);
ad8ba2cd
SY		 8065}
8066
1d8007bd 8067int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8068{
8069 int i, r;
25188b99 8070 unsigned long hva;
f0d648bd
PB		 8071 struct kvm_memslots *slots = kvm_memslots(kvm);
8072 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8073
8074 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8075 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8076 return -EINVAL;
9da0e4d5 8077
f0d648bd
PB		 8078 slot = id_to_memslot(slots, id);
8079 if (size) {
b21629da 8080 if (slot->npages)
f0d648bd
PB		 8081 return -EEXIST;
8082
8083 /*
8084 * MAP_SHARED to prevent internal slot pages from being moved
8085 * by fork()/COW.
8086 */
8087 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8088 MAP_SHARED | MAP_ANONYMOUS, 0);
8089 if (IS_ERR((void *)hva))
8090 return PTR_ERR((void *)hva);
8091 } else {
8092 if (!slot->npages)
8093 return 0;
8094
8095 hva = 0;
8096 }
8097
8098 old = *slot;
9da0e4d5 8099 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8100 struct kvm_userspace_memory_region m;
9da0e4d5 8101
1d8007bd
PB		 8102 m.slot = id | (i << 16);
8103 m.flags = 0;
8104 m.guest_phys_addr = gpa;
f0d648bd 8105 m.userspace_addr = hva;
1d8007bd 8106 m.memory_size = size;
9da0e4d5
PB		 8107 r = __kvm_set_memory_region(kvm, &m);
8108 if (r < 0)
8109 return r;
8110 }
8111
f0d648bd
PB		 8112 if (!size) {
8113 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8114 WARN_ON(r < 0);
8115 }
8116
9da0e4d5
PB		 8117 return 0;
8118}
8119EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8120
1d8007bd 8121int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8122{
8123 int r;
8124
8125 mutex_lock(&kvm->slots_lock);
1d8007bd 8126 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8127 mutex_unlock(&kvm->slots_lock);
8128
8129 return r;
8130}
8131EXPORT_SYMBOL_GPL(x86_set_memory_region);
8132
d19a9cd2
ZX		 8133void kvm_arch_destroy_vm(struct kvm *kvm)
8134{
27469d29
AH		 8135 if (current->mm == kvm->mm) {
8136 /*
8137 * Free memory regions allocated on behalf of userspace,
8138 * unless the the memory map has changed due to process exit
8139 * or fd copying.
8140 */
1d8007bd
PB		 8141 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8142 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8143 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8144 }
03543133
SS		 8145 if (kvm_x86_ops->vm_destroy)
8146 kvm_x86_ops->vm_destroy(kvm);
6eb55818 8147 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 8148 kfree(kvm->arch.vpic);
8149 kfree(kvm->arch.vioapic);
d19a9cd2 8150 kvm_free_vcpus(kvm);
af1bae54 8151 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8152 kvm_mmu_uninit_vm(kvm);
d19a9cd2 8153}
0de10343 8154
5587027c 8155void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8156 struct kvm_memory_slot *dont)
8157{
8158 int i;
8159
d89cc617
TY		 8160 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8161 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8162 kvfree(free->arch.rmap[i]);
d89cc617 8163 free->arch.rmap[i] = NULL;
77d11309 8164 }
d89cc617
TY		 8165 if (i == 0)
8166 continue;
8167
8168 if (!dont || free->arch.lpage_info[i - 1] !=
8169 dont->arch.lpage_info[i - 1]) {
548ef284 8170 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8171 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8172 }
8173 }
21ebbeda
XG		 8174
8175 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8176}
8177
5587027c
AK		 8178int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8179 unsigned long npages)
db3fe4eb
TY		 8180{
8181 int i;
8182
d89cc617 8183 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8184 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8185 unsigned long ugfn;
8186 int lpages;
d89cc617 8187 int level = i + 1;
db3fe4eb
TY		 8188
8189 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8190 slot->base_gfn, level) + 1;
8191
d89cc617
TY		 8192 slot->arch.rmap[i] =
8193 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8194 if (!slot->arch.rmap[i])
77d11309 8195 goto out_free;
d89cc617
TY		 8196 if (i == 0)
8197 continue;
77d11309 8198
92f94f1e
XG		 8199 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8200 if (!linfo)
db3fe4eb
TY		 8201 goto out_free;
8202
92f94f1e
XG		 8203 slot->arch.lpage_info[i - 1] = linfo;
8204
db3fe4eb 8205 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8206 linfo[0].disallow_lpage = 1;
db3fe4eb 8207 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8208 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8209 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8210 /*
8211 * If the gfn and userspace address are not aligned wrt each
8212 * other, or if explicitly asked to, disable large page
8213 * support for this slot
8214 */
8215 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8216 !kvm_largepages_enabled()) {
8217 unsigned long j;
8218
8219 for (j = 0; j < lpages; ++j)
92f94f1e 8220 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8221 }
8222 }
8223
21ebbeda
XG		 8224 if (kvm_page_track_create_memslot(slot, npages))
8225 goto out_free;
8226
db3fe4eb
TY		 8227 return 0;
8228
8229out_free:
d89cc617 8230 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8231 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8232 slot->arch.rmap[i] = NULL;
8233 if (i == 0)
8234 continue;
8235
548ef284 8236 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8237 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8238 }
8239 return -ENOMEM;
8240}
8241
15f46015 8242void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8243{
e6dff7d1
TY		 8244 /*
8245 * memslots->generation has been incremented.
8246 * mmio generation may have reached its maximum value.
8247 */
54bf36aa 8248 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8249}
8250
f7784b8e
MT		 8251int kvm_arch_prepare_memory_region(struct kvm *kvm,
8252 struct kvm_memory_slot *memslot,
09170a49 8253 const struct kvm_userspace_memory_region *mem,
7b6195a9 8254 enum kvm_mr_change change)
0de10343 8255{
f7784b8e
MT		 8256 return 0;
8257}
8258
88178fd4
KH		 8259static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8260 struct kvm_memory_slot *new)
8261{
8262 /* Still write protect RO slot */
8263 if (new->flags & KVM_MEM_READONLY) {
8264 kvm_mmu_slot_remove_write_access(kvm, new);
8265 return;
8266 }
8267
8268 /*
8269 * Call kvm_x86_ops dirty logging hooks when they are valid.
8270 *
8271 * kvm_x86_ops->slot_disable_log_dirty is called when:
8272 *
8273 * - KVM_MR_CREATE with dirty logging is disabled
8274 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8275 *
8276 * The reason is, in case of PML, we need to set D-bit for any slots
8277 * with dirty logging disabled in order to eliminate unnecessary GPA
8278 * logging in PML buffer (and potential PML buffer full VMEXT). This
8279 * guarantees leaving PML enabled during guest's lifetime won't have
8280 * any additonal overhead from PML when guest is running with dirty
8281 * logging disabled for memory slots.
8282 *
8283 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8284 * to dirty logging mode.
8285 *
8286 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8287 *
8288 * In case of write protect:
8289 *
8290 * Write protect all pages for dirty logging.
8291 *
8292 * All the sptes including the large sptes which point to this
8293 * slot are set to readonly. We can not create any new large
8294 * spte on this slot until the end of the logging.
8295 *
8296 * See the comments in fast_page_fault().
8297 */
8298 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8299 if (kvm_x86_ops->slot_enable_log_dirty)
8300 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8301 else
8302 kvm_mmu_slot_remove_write_access(kvm, new);
8303 } else {
8304 if (kvm_x86_ops->slot_disable_log_dirty)
8305 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8306 }
8307}
8308
f7784b8e 8309void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8310 const struct kvm_userspace_memory_region *mem,
8482644a 8311 const struct kvm_memory_slot *old,
f36f3f28 8312 const struct kvm_memory_slot *new,
8482644a 8313 enum kvm_mr_change change)
f7784b8e 8314{
8482644a 8315 int nr_mmu_pages = 0;
f7784b8e 8316
48c0e4e9
XG		 8317 if (!kvm->arch.n_requested_mmu_pages)
8318 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8319
48c0e4e9 8320 if (nr_mmu_pages)
0de10343 8321 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8322
3ea3b7fa
WL		 8323 /*
8324 * Dirty logging tracks sptes in 4k granularity, meaning that large
8325 * sptes have to be split. If live migration is successful, the guest
8326 * in the source machine will be destroyed and large sptes will be
8327 * created in the destination. However, if the guest continues to run
8328 * in the source machine (for example if live migration fails), small
8329 * sptes will remain around and cause bad performance.
8330 *
8331 * Scan sptes if dirty logging has been stopped, dropping those
8332 * which can be collapsed into a single large-page spte. Later
8333 * page faults will create the large-page sptes.
8334 */
8335 if ((change != KVM_MR_DELETE) &&
8336 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8337 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8338 kvm_mmu_zap_collapsible_sptes(kvm, new);
8339
c972f3b1 8340 /*
88178fd4 8341 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8342 *
88178fd4
KH		 8343 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8344 * been zapped so no dirty logging staff is needed for old slot. For
8345 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8346 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8347 *
8348 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8349 */
88178fd4 8350 if (change != KVM_MR_DELETE)
f36f3f28 8351 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8352}
1d737c8a 8353
2df72e9b 8354void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8355{
6ca18b69 8356 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8357}
8358
2df72e9b
MT		 8359void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8360 struct kvm_memory_slot *slot)
8361{
ae7cd873 8362 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8363}
8364
5d9bc648
PB		 8365static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8366{
8367 if (!list_empty_careful(&vcpu->async_pf.done))
8368 return true;
8369
8370 if (kvm_apic_has_events(vcpu))
8371 return true;
8372
8373 if (vcpu->arch.pv.pv_unhalted)
8374 return true;
8375
8376 if (atomic_read(&vcpu->arch.nmi_queued))
8377 return true;
8378
73917739
PB		 8379 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8380 return true;
8381
5d9bc648
PB		 8382 if (kvm_arch_interrupt_allowed(vcpu) &&
8383 kvm_cpu_has_interrupt(vcpu))
8384 return true;
8385
1f4b34f8
AS		 8386 if (kvm_hv_has_stimer_pending(vcpu))
8387 return true;
8388
5d9bc648
PB		 8389 return false;
8390}
8391
1d737c8a
ZX		 8392int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8393{
5d9bc648 8394 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8395}
5736199a 8396
b6d33834 8397int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8398{
b6d33834 8399 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8400}
78646121
GN		 8401
8402int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8403{
8404 return kvm_x86_ops->interrupt_allowed(vcpu);
8405}
229456fc 8406
82b32774 8407unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8408{
82b32774
NA		 8409 if (is_64_bit_mode(vcpu))
8410 return kvm_rip_read(vcpu);
8411 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8412 kvm_rip_read(vcpu));
8413}
8414EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8415
82b32774
NA		 8416bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8417{
8418 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8419}
8420EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8421
94fe45da
JK		 8422unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8423{
8424 unsigned long rflags;
8425
8426 rflags = kvm_x86_ops->get_rflags(vcpu);
8427 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8428 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8429 return rflags;
8430}
8431EXPORT_SYMBOL_GPL(kvm_get_rflags);
8432
6addfc42 8433static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8434{
8435 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8436 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8437 rflags |= X86_EFLAGS_TF;
94fe45da 8438 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8439}
8440
8441void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8442{
8443 __kvm_set_rflags(vcpu, rflags);
3842d135 8444 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8445}
8446EXPORT_SYMBOL_GPL(kvm_set_rflags);
8447
56028d08
GN		 8448void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8449{
8450 int r;
8451
fb67e14f 8452 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8453 work->wakeup_all)
56028d08
GN		 8454 return;
8455
8456 r = kvm_mmu_reload(vcpu);
8457 if (unlikely(r))
8458 return;
8459
fb67e14f
XG		 8460 if (!vcpu->arch.mmu.direct_map &&
8461 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8462 return;
8463
56028d08
GN		 8464 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8465}
8466
af585b92
GN		 8467static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8468{
8469 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8470}
8471
8472static inline u32 kvm_async_pf_next_probe(u32 key)
8473{
8474 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8475}
8476
8477static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8478{
8479 u32 key = kvm_async_pf_hash_fn(gfn);
8480
8481 while (vcpu->arch.apf.gfns[key] != ~0)
8482 key = kvm_async_pf_next_probe(key);
8483
8484 vcpu->arch.apf.gfns[key] = gfn;
8485}
8486
8487static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8488{
8489 int i;
8490 u32 key = kvm_async_pf_hash_fn(gfn);
8491
8492 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8493 (vcpu->arch.apf.gfns[key] != gfn &&
8494 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8495 key = kvm_async_pf_next_probe(key);
8496
8497 return key;
8498}
8499
8500bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8501{
8502 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8503}
8504
8505static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8506{
8507 u32 i, j, k;
8508
8509 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8510 while (true) {
8511 vcpu->arch.apf.gfns[i] = ~0;
8512 do {
8513 j = kvm_async_pf_next_probe(j);
8514 if (vcpu->arch.apf.gfns[j] == ~0)
8515 return;
8516 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8517 /*
8518 * k lies cyclically in ]i,j]
8519 * | i.k.j |
8520 * |....j i.k.| or |.k..j i...|
8521 */
8522 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8523 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8524 i = j;
8525 }
8526}
8527
7c90705b
GN		 8528static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8529{
8530
8531 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8532 sizeof(val));
8533}
8534
af585b92
GN		 8535void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8536 struct kvm_async_pf *work)
8537{
6389ee94
AK		 8538 struct x86_exception fault;
8539
7c90705b 8540 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8541 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8542
8543 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8544 (vcpu->arch.apf.send_user_only &&
8545 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8546 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8547 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8548 fault.vector = PF_VECTOR;
8549 fault.error_code_valid = true;
8550 fault.error_code = 0;
8551 fault.nested_page_fault = false;
8552 fault.address = work->arch.token;
8553 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8554 }
af585b92
GN		 8555}
8556
8557void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8558 struct kvm_async_pf *work)
8559{
6389ee94
AK		 8560 struct x86_exception fault;
8561
7c90705b 8562 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8563 if (work->wakeup_all)
7c90705b
GN		 8564 work->arch.token = ~0; /* broadcast wakeup */
8565 else
8566 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8567
8568 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8569 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8570 fault.vector = PF_VECTOR;
8571 fault.error_code_valid = true;
8572 fault.error_code = 0;
8573 fault.nested_page_fault = false;
8574 fault.address = work->arch.token;
8575 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8576 }
e6d53e3b 8577 vcpu->arch.apf.halted = false;
a4fa1635 8578 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8579}
8580
8581bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8582{
8583 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8584 return true;
8585 else
8586 return !kvm_event_needs_reinjection(vcpu) &&
8587 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8588}
8589
5544eb9b
PB		 8590void kvm_arch_start_assignment(struct kvm *kvm)
8591{
8592 atomic_inc(&kvm->arch.assigned_device_count);
8593}
8594EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8595
8596void kvm_arch_end_assignment(struct kvm *kvm)
8597{
8598 atomic_dec(&kvm->arch.assigned_device_count);
8599}
8600EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8601
8602bool kvm_arch_has_assigned_device(struct kvm *kvm)
8603{
8604 return atomic_read(&kvm->arch.assigned_device_count);
8605}
8606EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8607
e0f0bbc5
AW		 8608void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8609{
8610 atomic_inc(&kvm->arch.noncoherent_dma_count);
8611}
8612EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8613
8614void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8615{
8616 atomic_dec(&kvm->arch.noncoherent_dma_count);
8617}
8618EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8619
8620bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8621{
8622 return atomic_read(&kvm->arch.noncoherent_dma_count);
8623}
8624EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8625
14717e20
AW		 8626bool kvm_arch_has_irq_bypass(void)
8627{
8628 return kvm_x86_ops->update_pi_irte != NULL;
8629}
8630
87276880
FW		 8631int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8632 struct irq_bypass_producer *prod)
8633{
8634 struct kvm_kernel_irqfd *irqfd =
8635 container_of(cons, struct kvm_kernel_irqfd, consumer);
8636
14717e20 8637 irqfd->producer = prod;
87276880 8638
14717e20
AW		 8639 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8640 prod->irq, irqfd->gsi, 1);
87276880
FW		 8641}
8642
8643void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8644 struct irq_bypass_producer *prod)
8645{
8646 int ret;
8647 struct kvm_kernel_irqfd *irqfd =
8648 container_of(cons, struct kvm_kernel_irqfd, consumer);
8649
87276880
FW		 8650 WARN_ON(irqfd->producer != prod);
8651 irqfd->producer = NULL;
8652
8653 /*
8654 * When producer of consumer is unregistered, we change back to
8655 * remapped mode, so we can re-use the current implementation
bb3541f1 8656 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8657 * int this case doesn't want to receive the interrupts.
8658 */
8659 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8660 if (ret)
8661 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8662 " fails: %d\n", irqfd->consumer.token, ret);
8663}
8664
8665int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8666 uint32_t guest_irq, bool set)
8667{
8668 if (!kvm_x86_ops->update_pi_irte)
8669 return -EINVAL;
8670
8671 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8672}
8673
52004014
FW		 8674bool kvm_vector_hashing_enabled(void)
8675{
8676 return vector_hashing;
8677}
8678EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8679
229456fc 8680EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8681EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8682EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8683EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8684EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8685EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8686EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8687EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8688EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8689EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8690EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8691EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8692EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8693EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8694EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8695EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8696EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8697EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8698EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git