]> git.ipfire.org Git - thirdparty/kernel/stable.git/blame - arch/x86/kvm/x86.c
projects / thirdparty / kernel / stable.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: remaster kvm_write_tsc code
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
893590c7 137static bool __read_mostly backwards_tsc_observed = false;
16a96021 138
18863bdd
AK		 139#define KVM_NR_SHARED_MSRS 16
140
141struct kvm_shared_msrs_global {
142 int nr;
2bf78fa7 143 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 144};
145
146struct kvm_shared_msrs {
147 struct user_return_notifier urn;
148 bool registered;
2bf78fa7
SY		 149 struct kvm_shared_msr_values {
150 u64 host;
151 u64 curr;
152 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 153};
154
155static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 156static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 157
417bc304 158struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 159 { "pf_fixed", VCPU_STAT(pf_fixed) },
160 { "pf_guest", VCPU_STAT(pf_guest) },
161 { "tlb_flush", VCPU_STAT(tlb_flush) },
162 { "invlpg", VCPU_STAT(invlpg) },
163 { "exits", VCPU_STAT(exits) },
164 { "io_exits", VCPU_STAT(io_exits) },
165 { "mmio_exits", VCPU_STAT(mmio_exits) },
166 { "signal_exits", VCPU_STAT(signal_exits) },
167 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 168 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 169 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 170 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 171 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 172 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 173 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 174 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 175 { "request_irq", VCPU_STAT(request_irq_exits) },
176 { "irq_exits", VCPU_STAT(irq_exits) },
177 { "host_state_reload", VCPU_STAT(host_state_reload) },
178 { "efer_reload", VCPU_STAT(efer_reload) },
179 { "fpu_reload", VCPU_STAT(fpu_reload) },
180 { "insn_emulation", VCPU_STAT(insn_emulation) },
181 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 182 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 183 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 184 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 185 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
186 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
187 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
188 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
189 { "mmu_flooded", VM_STAT(mmu_flooded) },
190 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 191 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 192 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 193 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 194 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 195 { "max_mmu_page_hash_collisions",
196 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 197 { NULL }
198};
199
2acf923e
DC		 200u64 __read_mostly host_xcr0;
201
b6785def 202static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 203
af585b92
GN		 204static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
205{
206 int i;
207 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
208 vcpu->arch.apf.gfns[i] = ~0;
209}
210
18863bdd
AK		 211static void kvm_on_user_return(struct user_return_notifier *urn)
212{
213 unsigned slot;
18863bdd
AK		 214 struct kvm_shared_msrs *locals
215 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 216 struct kvm_shared_msr_values *values;
1650b4eb
IA		 217 unsigned long flags;
218
219 /*
220 * Disabling irqs at this point since the following code could be
221 * interrupted and executed through kvm_arch_hardware_disable()
222 */
223 local_irq_save(flags);
224 if (locals->registered) {
225 locals->registered = false;
226 user_return_notifier_unregister(urn);
227 }
228 local_irq_restore(flags);
18863bdd 229 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 230 values = &locals->values[slot];
231 if (values->host != values->curr) {
232 wrmsrl(shared_msrs_global.msrs[slot], values->host);
233 values->curr = values->host;
18863bdd
AK		 234 }
235 }
18863bdd
AK		 236}
237
2bf78fa7 238static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 239{
18863bdd 240 u64 value;
013f6a5d
MT		 241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 243
2bf78fa7
SY		 244 /* only read, and nobody should modify it at this time,
245 * so don't need lock */
246 if (slot >= shared_msrs_global.nr) {
247 printk(KERN_ERR "kvm: invalid MSR slot!");
248 return;
249 }
250 rdmsrl_safe(msr, &value);
251 smsr->values[slot].host = value;
252 smsr->values[slot].curr = value;
253}
254
255void kvm_define_shared_msr(unsigned slot, u32 msr)
256{
0123be42 257 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 258 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 259 if (slot >= shared_msrs_global.nr)
260 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 261}
262EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
263
264static void kvm_shared_msr_cpu_online(void)
265{
266 unsigned i;
18863bdd
AK		 267
268 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 269 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 270}
271
8b3c3104 272int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 273{
013f6a5d
MT		 274 unsigned int cpu = smp_processor_id();
275 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 276 int err;
18863bdd 277
2bf78fa7 278 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 279 return 0;
2bf78fa7 280 smsr->values[slot].curr = value;
8b3c3104
AH		 281 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
282 if (err)
283 return 1;
284
18863bdd
AK		 285 if (!smsr->registered) {
286 smsr->urn.on_user_return = kvm_on_user_return;
287 user_return_notifier_register(&smsr->urn);
288 smsr->registered = true;
289 }
8b3c3104 290 return 0;
18863bdd
AK		 291}
292EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
293
13a34e06 294static void drop_user_return_notifiers(void)
3548bab5 295{
013f6a5d
MT		 296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 298
299 if (smsr->registered)
300 kvm_on_user_return(&smsr->urn);
301}
302
6866b83e
CO		 303u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
304{
8a5a87d9 305 return vcpu->arch.apic_base;
6866b83e
CO		 306}
307EXPORT_SYMBOL_GPL(kvm_get_apic_base);
308
58cb628d
JK		 309int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
310{
311 u64 old_state = vcpu->arch.apic_base &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 new_state = msr_info->data &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
316 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
317
318 if (!msr_info->host_initiated &&
319 ((msr_info->data & reserved_bits) != 0 ||
320 new_state == X2APIC_ENABLE ||
321 (new_state == MSR_IA32_APICBASE_ENABLE &&
322 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
323 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
324 old_state == 0)))
325 return 1;
326
327 kvm_lapic_set_base(vcpu, msr_info->data);
328 return 0;
6866b83e
CO		 329}
330EXPORT_SYMBOL_GPL(kvm_set_apic_base);
331
2605fc21 332asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 333{
334 /* Fault while not rebooting. We want the trace. */
335 BUG();
336}
337EXPORT_SYMBOL_GPL(kvm_spurious_fault);
338
3fd28fce
ED		 339#define EXCPT_BENIGN 0
340#define EXCPT_CONTRIBUTORY 1
341#define EXCPT_PF 2
342
343static int exception_class(int vector)
344{
345 switch (vector) {
346 case PF_VECTOR:
347 return EXCPT_PF;
348 case DE_VECTOR:
349 case TS_VECTOR:
350 case NP_VECTOR:
351 case SS_VECTOR:
352 case GP_VECTOR:
353 return EXCPT_CONTRIBUTORY;
354 default:
355 break;
356 }
357 return EXCPT_BENIGN;
358}
359
d6e8c854
NA		 360#define EXCPT_FAULT 0
361#define EXCPT_TRAP 1
362#define EXCPT_ABORT 2
363#define EXCPT_INTERRUPT 3
364
365static int exception_type(int vector)
366{
367 unsigned int mask;
368
369 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
370 return EXCPT_INTERRUPT;
371
372 mask = 1 << vector;
373
374 /* #DB is trap, as instruction watchpoints are handled elsewhere */
375 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
376 return EXCPT_TRAP;
377
378 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
379 return EXCPT_ABORT;
380
381 /* Reserved exceptions will result in fault */
382 return EXCPT_FAULT;
383}
384
3fd28fce 385static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 386 unsigned nr, bool has_error, u32 error_code,
387 bool reinject)
3fd28fce
ED		 388{
389 u32 prev_nr;
390 int class1, class2;
391
3842d135
AK		 392 kvm_make_request(KVM_REQ_EVENT, vcpu);
393
3fd28fce
ED		 394 if (!vcpu->arch.exception.pending) {
395 queue:
3ffb2468
NA		 396 if (has_error && !is_protmode(vcpu))
397 has_error = false;
3fd28fce
ED		 398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = has_error;
400 vcpu->arch.exception.nr = nr;
401 vcpu->arch.exception.error_code = error_code;
3f0fd292 402 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 403 return;
404 }
405
406 /* to check exception */
407 prev_nr = vcpu->arch.exception.nr;
408 if (prev_nr == DF_VECTOR) {
409 /* triple fault -> shutdown */
a8eeb04a 410 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 411 return;
412 }
413 class1 = exception_class(prev_nr);
414 class2 = exception_class(nr);
415 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
416 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
417 /* generate double fault per SDM Table 5-5 */
418 vcpu->arch.exception.pending = true;
419 vcpu->arch.exception.has_error_code = true;
420 vcpu->arch.exception.nr = DF_VECTOR;
421 vcpu->arch.exception.error_code = 0;
422 } else
423 /* replace previous exception with a new one in a hope
424 that instruction re-execution will regenerate lost
425 exception */
426 goto queue;
427}
428
298101da
AK		 429void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
430{
ce7ddec4 431 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 432}
433EXPORT_SYMBOL_GPL(kvm_queue_exception);
434
ce7ddec4
JR		 435void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
436{
437 kvm_multiple_exception(vcpu, nr, false, 0, true);
438}
439EXPORT_SYMBOL_GPL(kvm_requeue_exception);
440
6affcbed 441int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 442{
db8fcefa
AP		 443 if (err)
444 kvm_inject_gp(vcpu, 0);
445 else
6affcbed
KH		 446 return kvm_skip_emulated_instruction(vcpu);
447
448 return 1;
db8fcefa
AP		 449}
450EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 451
6389ee94 452void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 453{
454 ++vcpu->stat.pf_guest;
6389ee94
AK		 455 vcpu->arch.cr2 = fault->address;
456 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 457}
27d6c865 458EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 459
ef54bcfe 460static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 461{
6389ee94
AK		 462 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
463 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 464 else
6389ee94 465 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 466
467 return fault->nested_page_fault;
d4f8cf66
JR		 468}
469
3419ffc8
SY		 470void kvm_inject_nmi(struct kvm_vcpu *vcpu)
471{
7460fb4a
AK		 472 atomic_inc(&vcpu->arch.nmi_queued);
473 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 474}
475EXPORT_SYMBOL_GPL(kvm_inject_nmi);
476
298101da
AK		 477void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
478{
ce7ddec4 479 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 480}
481EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
482
ce7ddec4
JR		 483void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
484{
485 kvm_multiple_exception(vcpu, nr, true, error_code, true);
486}
487EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
488
0a79b009
AK		 489/*
490 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
491 * a #GP and return false.
492 */
493bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 494{
0a79b009
AK		 495 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
496 return true;
497 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
498 return false;
298101da 499}
0a79b009 500EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 501
16f8a6f9
NA		 502bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
503{
504 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
505 return true;
506
507 kvm_queue_exception(vcpu, UD_VECTOR);
508 return false;
509}
510EXPORT_SYMBOL_GPL(kvm_require_dr);
511
ec92fe44
JR		 512/*
513 * This function will be used to read from the physical memory of the currently
54bf36aa 514 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 515 * can read from guest physical or from the guest's guest physical memory.
516 */
517int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
518 gfn_t ngfn, void *data, int offset, int len,
519 u32 access)
520{
54987b7a 521 struct x86_exception exception;
ec92fe44
JR		 522 gfn_t real_gfn;
523 gpa_t ngpa;
524
525 ngpa = gfn_to_gpa(ngfn);
54987b7a 526 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 527 if (real_gfn == UNMAPPED_GVA)
528 return -EFAULT;
529
530 real_gfn = gpa_to_gfn(real_gfn);
531
54bf36aa 532 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 533}
534EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
535
69b0049a 536static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 537 void *data, int offset, int len, u32 access)
538{
539 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
540 data, offset, len, access);
541}
542
a03490ed
CO		 543/*
544 * Load the pae pdptrs. Return true is they are all valid.
545 */
ff03a073 546int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 547{
548 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
549 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
550 int i;
551 int ret;
ff03a073 552 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 553
ff03a073
JR		 554 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
555 offset * sizeof(u64), sizeof(pdpte),
556 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 557 if (ret < 0) {
558 ret = 0;
559 goto out;
560 }
561 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 562 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 563 (pdpte[i] &
564 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 565 ret = 0;
566 goto out;
567 }
568 }
569 ret = 1;
570
ff03a073 571 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 572 __set_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_avail);
574 __set_bit(VCPU_EXREG_PDPTR,
575 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 576out:
a03490ed
CO		 577
578 return ret;
579}
cc4b6871 580EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 581
9ed38ffa 582bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 583{
ff03a073 584 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 585 bool changed = true;
3d06b8bf
JR		 586 int offset;
587 gfn_t gfn;
d835dfec
AK		 588 int r;
589
590 if (is_long_mode(vcpu) || !is_pae(vcpu))
591 return false;
592
6de4f3ad
AK		 593 if (!test_bit(VCPU_EXREG_PDPTR,
594 (unsigned long *)&vcpu->arch.regs_avail))
595 return true;
596
9f8fe504
AK		 597 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
598 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 599 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
600 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 601 if (r < 0)
602 goto out;
ff03a073 603 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 604out:
d835dfec
AK		 605
606 return changed;
607}
9ed38ffa 608EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 609
49a9b07e 610int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 611{
aad82703 612 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 613 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 614
f9a48e6a
AK		 615 cr0 |= X86_CR0_ET;
616
ab344828 617#ifdef CONFIG_X86_64
0f12244f
GN		 618 if (cr0 & 0xffffffff00000000UL)
619 return 1;
ab344828
GN		 620#endif
621
622 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 623
0f12244f
GN		 624 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
625 return 1;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
628 return 1;
a03490ed
CO		 629
630 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
631#ifdef CONFIG_X86_64
f6801dff 632 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 633 int cs_db, cs_l;
634
0f12244f
GN		 635 if (!is_pae(vcpu))
636 return 1;
a03490ed 637 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 638 if (cs_l)
639 return 1;
a03490ed
CO		 640 } else
641#endif
ff03a073 642 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 643 kvm_read_cr3(vcpu)))
0f12244f 644 return 1;
a03490ed
CO		 645 }
646
ad756a16
MJ		 647 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
648 return 1;
649
a03490ed 650 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 651
d170c419 652 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 653 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 654 kvm_async_pf_hash_reset(vcpu);
655 }
e5f3f027 656
aad82703
SY		 657 if ((cr0 ^ old_cr0) & update_bits)
658 kvm_mmu_reset_context(vcpu);
b18d5431 659
879ae188
LE		 660 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
661 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
662 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 663 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
664
0f12244f
GN		 665 return 0;
666}
2d3ad1f4 667EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 668
2d3ad1f4 669void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 670{
49a9b07e 671 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 672}
2d3ad1f4 673EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 674
42bdf991
MT		 675static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
676{
677 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
678 !vcpu->guest_xcr0_loaded) {
679 /* kvm_set_xcr() also depends on this */
680 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
681 vcpu->guest_xcr0_loaded = 1;
682 }
683}
684
685static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
686{
687 if (vcpu->guest_xcr0_loaded) {
688 if (vcpu->arch.xcr0 != host_xcr0)
689 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
690 vcpu->guest_xcr0_loaded = 0;
691 }
692}
693
69b0049a 694static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 695{
56c103ec
LJ		 696 u64 xcr0 = xcr;
697 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 698 u64 valid_bits;
2acf923e
DC		 699
700 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
701 if (index != XCR_XFEATURE_ENABLED_MASK)
702 return 1;
d91cab78 703 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 704 return 1;
d91cab78 705 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 706 return 1;
46c34cb0
PB		 707
708 /*
709 * Do not allow the guest to set bits that we do not support
710 * saving. However, xcr0 bit 0 is always set, even if the
711 * emulated CPU does not support XSAVE (see fx_init).
712 */
d91cab78 713 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 714 if (xcr0 & ~valid_bits)
2acf923e 715 return 1;
46c34cb0 716
d91cab78
DH		 717 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
718 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 719 return 1;
720
d91cab78
DH		 721 if (xcr0 & XFEATURE_MASK_AVX512) {
722 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 723 return 1;
d91cab78 724 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 725 return 1;
726 }
2acf923e 727 vcpu->arch.xcr0 = xcr0;
56c103ec 728
d91cab78 729 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 730 kvm_update_cpuid(vcpu);
2acf923e
DC		 731 return 0;
732}
733
734int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
735{
764bcbc5
Z		 736 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
737 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 738 kvm_inject_gp(vcpu, 0);
739 return 1;
740 }
741 return 0;
742}
743EXPORT_SYMBOL_GPL(kvm_set_xcr);
744
a83b29c6 745int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 746{
fc78f519 747 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 748 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 749 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 750
0f12244f
GN		 751 if (cr4 & CR4_RESERVED_BITS)
752 return 1;
a03490ed 753
2acf923e
DC		 754 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
755 return 1;
756
c68b734f
YW		 757 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
758 return 1;
759
97ec8c06
FW		 760 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
761 return 1;
762
afcbf13f 763 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 764 return 1;
765
b9baba86
HH		 766 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
767 return 1;
768
a03490ed 769 if (is_long_mode(vcpu)) {
0f12244f
GN		 770 if (!(cr4 & X86_CR4_PAE))
771 return 1;
a2edf57f
AK		 772 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
773 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 774 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
775 kvm_read_cr3(vcpu)))
0f12244f
GN		 776 return 1;
777
ad756a16
MJ		 778 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
779 if (!guest_cpuid_has_pcid(vcpu))
780 return 1;
781
782 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
783 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
784 return 1;
785 }
786
5e1746d6 787 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 788 return 1;
a03490ed 789
ad756a16
MJ		 790 if (((cr4 ^ old_cr4) & pdptr_bits) ||
791 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 792 kvm_mmu_reset_context(vcpu);
0f12244f 793
b9baba86 794 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 795 kvm_update_cpuid(vcpu);
2acf923e 796
0f12244f
GN		 797 return 0;
798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 800
2390218b 801int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 802{
ac146235 803#ifdef CONFIG_X86_64
9d88fca7 804 cr3 &= ~CR3_PCID_INVD;
ac146235 805#endif
9d88fca7 806
9f8fe504 807 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 808 kvm_mmu_sync_roots(vcpu);
77c3913b 809 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 810 return 0;
d835dfec
AK		 811 }
812
a03490ed 813 if (is_long_mode(vcpu)) {
d9f89b88
JK		 814 if (cr3 & CR3_L_MODE_RESERVED_BITS)
815 return 1;
816 } else if (is_pae(vcpu) && is_paging(vcpu) &&
817 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 818 return 1;
a03490ed 819
0f12244f 820 vcpu->arch.cr3 = cr3;
aff48baa 821 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 822 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 823 return 0;
824}
2d3ad1f4 825EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 826
eea1cff9 827int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 828{
0f12244f
GN		 829 if (cr8 & CR8_RESERVED_BITS)
830 return 1;
35754c98 831 if (lapic_in_kernel(vcpu))
a03490ed
CO		 832 kvm_lapic_set_tpr(vcpu, cr8);
833 else
ad312c7c 834 vcpu->arch.cr8 = cr8;
0f12244f
GN		 835 return 0;
836}
2d3ad1f4 837EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 838
2d3ad1f4 839unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 840{
35754c98 841 if (lapic_in_kernel(vcpu))
a03490ed
CO		 842 return kvm_lapic_get_cr8(vcpu);
843 else
ad312c7c 844 return vcpu->arch.cr8;
a03490ed 845}
2d3ad1f4 846EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 847
ae561ede
NA		 848static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
849{
850 int i;
851
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
853 for (i = 0; i < KVM_NR_DB_REGS; i++)
854 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
855 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
856 }
857}
858
73aaf249
JK		 859static void kvm_update_dr6(struct kvm_vcpu *vcpu)
860{
861 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
862 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
863}
864
c8639010
JK		 865static void kvm_update_dr7(struct kvm_vcpu *vcpu)
866{
867 unsigned long dr7;
868
869 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
870 dr7 = vcpu->arch.guest_debug_dr7;
871 else
872 dr7 = vcpu->arch.dr7;
873 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 874 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
875 if (dr7 & DR7_BP_EN_MASK)
876 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 877}
878
6f43ed01
NA		 879static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
880{
881 u64 fixed = DR6_FIXED_1;
882
883 if (!guest_cpuid_has_rtm(vcpu))
884 fixed |= DR6_RTM;
885 return fixed;
886}
887
338dbc97 888static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 889{
890 switch (dr) {
891 case 0 ... 3:
892 vcpu->arch.db[dr] = val;
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 vcpu->arch.eff_db[dr] = val;
895 break;
896 case 4:
020df079
GN		 897 /* fall through */
898 case 6:
338dbc97
GN		 899 if (val & 0xffffffff00000000ULL)
900 return -1; /* #GP */
6f43ed01 901 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 902 kvm_update_dr6(vcpu);
020df079
GN		 903 break;
904 case 5:
020df079
GN		 905 /* fall through */
906 default: /* 7 */
338dbc97
GN		 907 if (val & 0xffffffff00000000ULL)
908 return -1; /* #GP */
020df079 909 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 910 kvm_update_dr7(vcpu);
020df079
GN		 911 break;
912 }
913
914 return 0;
915}
338dbc97
GN		 916
917int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
918{
16f8a6f9 919 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 920 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 921 return 1;
922 }
923 return 0;
338dbc97 924}
020df079
GN		 925EXPORT_SYMBOL_GPL(kvm_set_dr);
926
16f8a6f9 927int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 928{
929 switch (dr) {
930 case 0 ... 3:
931 *val = vcpu->arch.db[dr];
932 break;
933 case 4:
020df079
GN		 934 /* fall through */
935 case 6:
73aaf249
JK		 936 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
937 *val = vcpu->arch.dr6;
938 else
939 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 940 break;
941 case 5:
020df079
GN		 942 /* fall through */
943 default: /* 7 */
944 *val = vcpu->arch.dr7;
945 break;
946 }
338dbc97
GN		 947 return 0;
948}
020df079
GN		 949EXPORT_SYMBOL_GPL(kvm_get_dr);
950
022cd0e8
AK		 951bool kvm_rdpmc(struct kvm_vcpu *vcpu)
952{
953 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
954 u64 data;
955 int err;
956
c6702c9d 957 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 958 if (err)
959 return err;
960 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
961 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
962 return err;
963}
964EXPORT_SYMBOL_GPL(kvm_rdpmc);
965
043405e1
CO		 966/*
967 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
968 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
969 *
970 * This list is modified at module load time to reflect the
e3267cbb 971 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 972 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
973 * may depend on host virtualization features rather than host cpu features.
043405e1 974 */
e3267cbb 975
043405e1
CO		 976static u32 msrs_to_save[] = {
977 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 978 MSR_STAR,
043405e1
CO		 979#ifdef CONFIG_X86_64
980 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
981#endif
b3897a49 982 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 983 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 984};
985
986static unsigned num_msrs_to_save;
987
62ef68bb
PB		 988static u32 emulated_msrs[] = {
989 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
990 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
991 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
992 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 993 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
994 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 995 HV_X64_MSR_RESET,
11c4b1ca 996 HV_X64_MSR_VP_INDEX,
9eec50b8 997 HV_X64_MSR_VP_RUNTIME,
5c919412 998 HV_X64_MSR_SCONTROL,
1f4b34f8 999 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1000 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1001 MSR_KVM_PV_EOI_EN,
1002
ba904635 1003 MSR_IA32_TSC_ADJUST,
a3e06bbe 1004 MSR_IA32_TSCDEADLINE,
043405e1 1005 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1006 MSR_IA32_MCG_STATUS,
1007 MSR_IA32_MCG_CTL,
c45dcc71 1008 MSR_IA32_MCG_EXT_CTL,
64d60670 1009 MSR_IA32_SMBASE,
043405e1
CO		 1010};
1011
62ef68bb
PB		 1012static unsigned num_emulated_msrs;
1013
384bb783 1014bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1015{
b69e8cae 1016 if (efer & efer_reserved_bits)
384bb783 1017 return false;
15c4a640 1018
1b2fd70c
AG		 1019 if (efer & EFER_FFXSR) {
1020 struct kvm_cpuid_entry2 *feat;
1021
1022 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1023 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1024 return false;
1b2fd70c
AG		 1025 }
1026
d8017474
AG		 1027 if (efer & EFER_SVME) {
1028 struct kvm_cpuid_entry2 *feat;
1029
1030 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1031 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1032 return false;
d8017474
AG		 1033 }
1034
384bb783
JK		 1035 return true;
1036}
1037EXPORT_SYMBOL_GPL(kvm_valid_efer);
1038
1039static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1040{
1041 u64 old_efer = vcpu->arch.efer;
1042
1043 if (!kvm_valid_efer(vcpu, efer))
1044 return 1;
1045
1046 if (is_paging(vcpu)
1047 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1048 return 1;
1049
15c4a640 1050 efer &= ~EFER_LMA;
f6801dff 1051 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1052
a3d204e2
SY		 1053 kvm_x86_ops->set_efer(vcpu, efer);
1054
aad82703
SY		 1055 /* Update reserved bits */
1056 if ((efer ^ old_efer) & EFER_NX)
1057 kvm_mmu_reset_context(vcpu);
1058
b69e8cae 1059 return 0;
15c4a640
CO		 1060}
1061
f2b4b7dd
JR		 1062void kvm_enable_efer_bits(u64 mask)
1063{
1064 efer_reserved_bits &= ~mask;
1065}
1066EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1067
15c4a640
CO		 1068/*
1069 * Writes msr value into into the appropriate "register".
1070 * Returns 0 on success, non-0 otherwise.
1071 * Assumes vcpu_load() was already called.
1072 */
8fe8ab46 1073int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1074{
854e8bb1
NA		 1075 switch (msr->index) {
1076 case MSR_FS_BASE:
1077 case MSR_GS_BASE:
1078 case MSR_KERNEL_GS_BASE:
1079 case MSR_CSTAR:
1080 case MSR_LSTAR:
1081 if (is_noncanonical_address(msr->data))
1082 return 1;
1083 break;
1084 case MSR_IA32_SYSENTER_EIP:
1085 case MSR_IA32_SYSENTER_ESP:
1086 /*
1087 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1088 * non-canonical address is written on Intel but not on
1089 * AMD (which ignores the top 32-bits, because it does
1090 * not implement 64-bit SYSENTER).
1091 *
1092 * 64-bit code should hence be able to write a non-canonical
1093 * value on AMD. Making the address canonical ensures that
1094 * vmentry does not fail on Intel after writing a non-canonical
1095 * value, and that something deterministic happens if the guest
1096 * invokes 64-bit SYSENTER.
1097 */
1098 msr->data = get_canonical(msr->data);
1099 }
8fe8ab46 1100 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1101}
854e8bb1 1102EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1103
313a3dc7
CO		 1104/*
1105 * Adapt set_msr() to msr_io()'s calling convention
1106 */
609e36d3
PB		 1107static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1108{
1109 struct msr_data msr;
1110 int r;
1111
1112 msr.index = index;
1113 msr.host_initiated = true;
1114 r = kvm_get_msr(vcpu, &msr);
1115 if (r)
1116 return r;
1117
1118 *data = msr.data;
1119 return 0;
1120}
1121
313a3dc7
CO		 1122static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1123{
8fe8ab46
WA		 1124 struct msr_data msr;
1125
1126 msr.data = *data;
1127 msr.index = index;
1128 msr.host_initiated = true;
1129 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1130}
1131
16e8d74d
MT		 1132#ifdef CONFIG_X86_64
1133struct pvclock_gtod_data {
1134 seqcount_t seq;
1135
1136 struct { /* extract of a clocksource struct */
1137 int vclock_mode;
a5a1d1c2
TG		 1138 u64 cycle_last;
1139 u64 mask;
16e8d74d
MT		 1140 u32 mult;
1141 u32 shift;
1142 } clock;
1143
cbcf2dd3
TG		 1144 u64 boot_ns;
1145 u64 nsec_base;
55dd00a7 1146 u64 wall_time_sec;
16e8d74d
MT		 1147};
1148
1149static struct pvclock_gtod_data pvclock_gtod_data;
1150
1151static void update_pvclock_gtod(struct timekeeper *tk)
1152{
1153 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1154 u64 boot_ns;
1155
876e7881 1156 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1157
1158 write_seqcount_begin(&vdata->seq);
1159
1160 /* copy pvclock gtod data */
876e7881
PZ		 1161 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1162 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1163 vdata->clock.mask = tk->tkr_mono.mask;
1164 vdata->clock.mult = tk->tkr_mono.mult;
1165 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1166
cbcf2dd3 1167 vdata->boot_ns = boot_ns;
876e7881 1168 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1169
55dd00a7
MT		 1170 vdata->wall_time_sec = tk->xtime_sec;
1171
16e8d74d
MT		 1172 write_seqcount_end(&vdata->seq);
1173}
1174#endif
1175
bab5bb39
NK		 1176void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1177{
1178 /*
1179 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1180 * vcpu_enter_guest. This function is only called from
1181 * the physical CPU that is running vcpu.
1182 */
1183 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1184}
16e8d74d 1185
18068523
GOC		 1186static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1187{
9ed3c444
AK		 1188 int version;
1189 int r;
50d0a0f9 1190 struct pvclock_wall_clock wc;
87aeb54f 1191 struct timespec64 boot;
18068523
GOC		 1192
1193 if (!wall_clock)
1194 return;
1195
9ed3c444
AK		 1196 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1197 if (r)
1198 return;
1199
1200 if (version & 1)
1201 ++version; /* first time write, random junk */
1202
1203 ++version;
18068523 1204
1dab1345
NK		 1205 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1206 return;
18068523 1207
50d0a0f9
GH		 1208 /*
1209 * The guest calculates current wall clock time by adding
34c238a1 1210 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1211 * wall clock specified here. guest system time equals host
1212 * system time for us, thus we must fill in host boot time here.
1213 */
87aeb54f 1214 getboottime64(&boot);
50d0a0f9 1215
4b648665 1216 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1217 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1218 boot = timespec64_sub(boot, ts);
4b648665 1219 }
87aeb54f 1220 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1221 wc.nsec = boot.tv_nsec;
1222 wc.version = version;
18068523
GOC		 1223
1224 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1225
1226 version++;
1227 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1228}
1229
50d0a0f9
GH		 1230static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1231{
b51012de
PB		 1232 do_shl32_div32(dividend, divisor);
1233 return dividend;
50d0a0f9
GH		 1234}
1235
3ae13faa 1236static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1237 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1238{
5f4e3f88 1239 uint64_t scaled64;
50d0a0f9
GH		 1240 int32_t shift = 0;
1241 uint64_t tps64;
1242 uint32_t tps32;
1243
3ae13faa
PB		 1244 tps64 = base_hz;
1245 scaled64 = scaled_hz;
50933623 1246 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1247 tps64 >>= 1;
1248 shift--;
1249 }
1250
1251 tps32 = (uint32_t)tps64;
50933623
JK		 1252 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1253 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1254 scaled64 >>= 1;
1255 else
1256 tps32 <<= 1;
50d0a0f9
GH		 1257 shift++;
1258 }
1259
5f4e3f88
ZA		 1260 *pshift = shift;
1261 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1262
3ae13faa
PB		 1263 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1264 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1265}
1266
d828199e 1267#ifdef CONFIG_X86_64
16e8d74d 1268static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1269#endif
16e8d74d 1270
c8076604 1271static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1272static unsigned long max_tsc_khz;
c8076604 1273
cc578287 1274static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1275{
cc578287
ZA		 1276 u64 v = (u64)khz * (1000000 + ppm);
1277 do_div(v, 1000000);
1278 return v;
1e993611
JR		 1279}
1280
381d585c
HZ		 1281static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1282{
1283 u64 ratio;
1284
1285 /* Guest TSC same frequency as host TSC? */
1286 if (!scale) {
1287 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1288 return 0;
1289 }
1290
1291 /* TSC scaling supported? */
1292 if (!kvm_has_tsc_control) {
1293 if (user_tsc_khz > tsc_khz) {
1294 vcpu->arch.tsc_catchup = 1;
1295 vcpu->arch.tsc_always_catchup = 1;
1296 return 0;
1297 } else {
1298 WARN(1, "user requested TSC rate below hardware speed\n");
1299 return -1;
1300 }
1301 }
1302
1303 /* TSC scaling required - calculate ratio */
1304 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1305 user_tsc_khz, tsc_khz);
1306
1307 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1308 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1309 user_tsc_khz);
1310 return -1;
1311 }
1312
1313 vcpu->arch.tsc_scaling_ratio = ratio;
1314 return 0;
1315}
1316
4941b8cb 1317static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1318{
cc578287
ZA		 1319 u32 thresh_lo, thresh_hi;
1320 int use_scaling = 0;
217fc9cf 1321
03ba32ca 1322 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1323 if (user_tsc_khz == 0) {
ad721883
HZ		 1324 /* set tsc_scaling_ratio to a safe value */
1325 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1326 return -1;
ad721883 1327 }
03ba32ca 1328
c285545f 1329 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1330 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1331 &vcpu->arch.virtual_tsc_shift,
1332 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1333 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1334
1335 /*
1336 * Compute the variation in TSC rate which is acceptable
1337 * within the range of tolerance and decide if the
1338 * rate being applied is within that bounds of the hardware
1339 * rate. If so, no scaling or compensation need be done.
1340 */
1341 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1342 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1343 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1344 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1345 use_scaling = 1;
1346 }
4941b8cb 1347 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1348}
1349
1350static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1351{
e26101b1 1352 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1353 vcpu->arch.virtual_tsc_mult,
1354 vcpu->arch.virtual_tsc_shift);
e26101b1 1355 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1356 return tsc;
1357}
1358
69b0049a 1359static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1360{
1361#ifdef CONFIG_X86_64
1362 bool vcpus_matched;
b48aa97e
MT		 1363 struct kvm_arch *ka = &vcpu->kvm->arch;
1364 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1365
1366 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1367 atomic_read(&vcpu->kvm->online_vcpus));
1368
7f187922
MT		 1369 /*
1370 * Once the masterclock is enabled, always perform request in
1371 * order to update it.
1372 *
1373 * In order to enable masterclock, the host clocksource must be TSC
1374 * and the vcpus need to have matched TSCs. When that happens,
1375 * perform request to enable masterclock.
1376 */
1377 if (ka->use_master_clock ||
1378 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1379 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1380
1381 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1382 atomic_read(&vcpu->kvm->online_vcpus),
1383 ka->use_master_clock, gtod->clock.vclock_mode);
1384#endif
1385}
1386
ba904635
WA		 1387static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1388{
3e3f5026 1389 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1390 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1391}
1392
35181e86
HZ		 1393/*
1394 * Multiply tsc by a fixed point number represented by ratio.
1395 *
1396 * The most significant 64-N bits (mult) of ratio represent the
1397 * integral part of the fixed point number; the remaining N bits
1398 * (frac) represent the fractional part, ie. ratio represents a fixed
1399 * point number (mult + frac * 2^(-N)).
1400 *
1401 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1402 */
1403static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1404{
1405 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1406}
1407
1408u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1409{
1410 u64 _tsc = tsc;
1411 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1412
1413 if (ratio != kvm_default_tsc_scaling_ratio)
1414 _tsc = __scale_tsc(ratio, tsc);
1415
1416 return _tsc;
1417}
1418EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1419
07c1419a
HZ		 1420static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1421{
1422 u64 tsc;
1423
1424 tsc = kvm_scale_tsc(vcpu, rdtsc());
1425
1426 return target_tsc - tsc;
1427}
1428
4ba76538
HZ		 1429u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1430{
ea26e4ec 1431 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1432}
1433EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1434
a545ab6a
LC		 1435static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1436{
1437 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1438 vcpu->arch.tsc_offset = offset;
1439}
1440
8fe8ab46 1441void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1442{
1443 struct kvm *kvm = vcpu->kvm;
f38e098f 1444 u64 offset, ns, elapsed;
99e3e30a 1445 unsigned long flags;
b48aa97e 1446 bool matched;
0d3da0d2 1447 bool already_matched;
8fe8ab46 1448 u64 data = msr->data;
c5e8ec8e 1449 bool synchronizing = false;
99e3e30a 1450
038f8c11 1451 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1452 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1453 ns = ktime_get_boot_ns();
f38e098f 1454 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1455
03ba32ca 1456 if (vcpu->arch.virtual_tsc_khz) {
c5e8ec8e
DP		 1457 u64 tsc_exp = kvm->arch.last_tsc_write +
1458 nsec_to_cycles(vcpu, elapsed);
1459 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1460 /*
1461 * Special case: TSC write with a small delta (1 second)
1462 * of virtual cycle time against real time is
1463 * interpreted as an attempt to synchronize the CPU.
1464 */
1465 synchronizing = data < tsc_exp + tsc_hz &&
1466 data + tsc_hz > tsc_exp;
1467 }
f38e098f
ZA		 1468
1469 /*
5d3cb0f6
ZA		 1470 * For a reliable TSC, we can match TSC offsets, and for an unstable
1471 * TSC, we add elapsed time in this computation. We could let the
1472 * compensation code attempt to catch up if we fall behind, but
1473 * it's better to try to match offsets from the beginning.
1474 */
c5e8ec8e 1475 if (synchronizing &&
5d3cb0f6 1476 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1477 if (!check_tsc_unstable()) {
e26101b1 1478 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1479 pr_debug("kvm: matched tsc offset for %llu\n", data);
1480 } else {
857e4099 1481 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1482 data += delta;
07c1419a 1483 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1484 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1485 }
b48aa97e 1486 matched = true;
0d3da0d2 1487 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1488 } else {
1489 /*
1490 * We split periods of matched TSC writes into generations.
1491 * For each generation, we track the original measured
1492 * nanosecond time, offset, and write, so if TSCs are in
1493 * sync, we can match exact offset, and if not, we can match
4a969980 1494 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1495 *
1496 * These values are tracked in kvm->arch.cur_xxx variables.
1497 */
1498 kvm->arch.cur_tsc_generation++;
1499 kvm->arch.cur_tsc_nsec = ns;
1500 kvm->arch.cur_tsc_write = data;
1501 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1502 matched = false;
0d3da0d2 1503 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1504 kvm->arch.cur_tsc_generation, data);
f38e098f 1505 }
e26101b1
ZA		 1506
1507 /*
1508 * We also track th most recent recorded KHZ, write and time to
1509 * allow the matching interval to be extended at each write.
1510 */
f38e098f
ZA		 1511 kvm->arch.last_tsc_nsec = ns;
1512 kvm->arch.last_tsc_write = data;
5d3cb0f6 1513 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1514
b183aa58 1515 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1516
1517 /* Keep track of which generation this VCPU has synchronized to */
1518 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1519 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1520 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1521
ba904635
WA		 1522 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1523 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1524 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1525 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1526
1527 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1528 if (!matched) {
b48aa97e 1529 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1530 } else if (!already_matched) {
1531 kvm->arch.nr_vcpus_matched_tsc++;
1532 }
b48aa97e
MT		 1533
1534 kvm_track_tsc_matching(vcpu);
1535 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1536}
e26101b1 1537
99e3e30a
ZA		 1538EXPORT_SYMBOL_GPL(kvm_write_tsc);
1539
58ea6767
HZ		 1540static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1541 s64 adjustment)
1542{
ea26e4ec 1543 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1544}
1545
1546static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1547{
1548 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1549 WARN_ON(adjustment < 0);
1550 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1551 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1552}
1553
d828199e
MT		 1554#ifdef CONFIG_X86_64
1555
a5a1d1c2 1556static u64 read_tsc(void)
d828199e 1557{
a5a1d1c2 1558 u64 ret = (u64)rdtsc_ordered();
03b9730b 1559 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1560
1561 if (likely(ret >= last))
1562 return ret;
1563
1564 /*
1565 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1566 * predictable (it's just a function of time and the likely is
d828199e
MT		 1567 * very likely) and there's a data dependence, so force GCC
1568 * to generate a branch instead. I don't barrier() because
1569 * we don't actually need a barrier, and if this function
1570 * ever gets inlined it will generate worse code.
1571 */
1572 asm volatile ("");
1573 return last;
1574}
1575
a5a1d1c2 1576static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1577{
1578 long v;
1579 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1580
1581 *cycle_now = read_tsc();
1582
1583 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1584 return v * gtod->clock.mult;
1585}
1586
a5a1d1c2 1587static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1588{
cbcf2dd3 1589 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1590 unsigned long seq;
d828199e 1591 int mode;
cbcf2dd3 1592 u64 ns;
d828199e 1593
d828199e
MT		 1594 do {
1595 seq = read_seqcount_begin(&gtod->seq);
1596 mode = gtod->clock.vclock_mode;
cbcf2dd3 1597 ns = gtod->nsec_base;
d828199e
MT		 1598 ns += vgettsc(cycle_now);
1599 ns >>= gtod->clock.shift;
cbcf2dd3 1600 ns += gtod->boot_ns;
d828199e 1601 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1602 *t = ns;
d828199e
MT		 1603
1604 return mode;
1605}
1606
55dd00a7
MT		 1607static int do_realtime(struct timespec *ts, u64 *cycle_now)
1608{
1609 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1610 unsigned long seq;
1611 int mode;
1612 u64 ns;
1613
1614 do {
1615 seq = read_seqcount_begin(&gtod->seq);
1616 mode = gtod->clock.vclock_mode;
1617 ts->tv_sec = gtod->wall_time_sec;
1618 ns = gtod->nsec_base;
1619 ns += vgettsc(cycle_now);
1620 ns >>= gtod->clock.shift;
1621 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1622
1623 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1624 ts->tv_nsec = ns;
1625
1626 return mode;
1627}
1628
d828199e 1629/* returns true if host is using tsc clocksource */
a5a1d1c2 1630static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1631{
d828199e
MT		 1632 /* checked again under seqlock below */
1633 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1634 return false;
1635
cbcf2dd3 1636 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1637}
55dd00a7
MT		 1638
1639/* returns true if host is using tsc clocksource */
1640static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1641 u64 *cycle_now)
1642{
1643 /* checked again under seqlock below */
1644 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1645 return false;
1646
1647 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1648}
d828199e
MT		 1649#endif
1650
1651/*
1652 *
b48aa97e
MT		 1653 * Assuming a stable TSC across physical CPUS, and a stable TSC
1654 * across virtual CPUs, the following condition is possible.
1655 * Each numbered line represents an event visible to both
d828199e
MT		 1656 * CPUs at the next numbered event.
1657 *
1658 * "timespecX" represents host monotonic time. "tscX" represents
1659 * RDTSC value.
1660 *
1661 * VCPU0 on CPU0 | VCPU1 on CPU1
1662 *
1663 * 1. read timespec0,tsc0
1664 * 2. | timespec1 = timespec0 + N
1665 * | tsc1 = tsc0 + M
1666 * 3. transition to guest | transition to guest
1667 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1668 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1669 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1670 *
1671 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1672 *
1673 * - ret0 < ret1
1674 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1675 * ...
1676 * - 0 < N - M => M < N
1677 *
1678 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1679 * always the case (the difference between two distinct xtime instances
1680 * might be smaller then the difference between corresponding TSC reads,
1681 * when updating guest vcpus pvclock areas).
1682 *
1683 * To avoid that problem, do not allow visibility of distinct
1684 * system_timestamp/tsc_timestamp values simultaneously: use a master
1685 * copy of host monotonic time values. Update that master copy
1686 * in lockstep.
1687 *
b48aa97e 1688 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1689 *
1690 */
1691
1692static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1693{
1694#ifdef CONFIG_X86_64
1695 struct kvm_arch *ka = &kvm->arch;
1696 int vclock_mode;
b48aa97e
MT		 1697 bool host_tsc_clocksource, vcpus_matched;
1698
1699 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1700 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1701
1702 /*
1703 * If the host uses TSC clock, then passthrough TSC as stable
1704 * to the guest.
1705 */
b48aa97e 1706 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1707 &ka->master_kernel_ns,
1708 &ka->master_cycle_now);
1709
16a96021 1710 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1711 && !backwards_tsc_observed
1712 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1713
d828199e
MT		 1714 if (ka->use_master_clock)
1715 atomic_set(&kvm_guest_has_master_clock, 1);
1716
1717 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1718 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1719 vcpus_matched);
d828199e
MT		 1720#endif
1721}
1722
2860c4b1
PB		 1723void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1724{
1725 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1726}
1727
2e762ff7
MT		 1728static void kvm_gen_update_masterclock(struct kvm *kvm)
1729{
1730#ifdef CONFIG_X86_64
1731 int i;
1732 struct kvm_vcpu *vcpu;
1733 struct kvm_arch *ka = &kvm->arch;
1734
1735 spin_lock(&ka->pvclock_gtod_sync_lock);
1736 kvm_make_mclock_inprogress_request(kvm);
1737 /* no guest entries from this point */
1738 pvclock_update_vm_gtod_copy(kvm);
1739
1740 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1741 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1742
1743 /* guest entries allowed */
1744 kvm_for_each_vcpu(i, vcpu, kvm)
1745 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1746
1747 spin_unlock(&ka->pvclock_gtod_sync_lock);
1748#endif
1749}
1750
108b249c
PB		 1751static u64 __get_kvmclock_ns(struct kvm *kvm)
1752{
108b249c 1753 struct kvm_arch *ka = &kvm->arch;
8b953440 1754 struct pvclock_vcpu_time_info hv_clock;
108b249c 1755
8b953440
PB		 1756 spin_lock(&ka->pvclock_gtod_sync_lock);
1757 if (!ka->use_master_clock) {
1758 spin_unlock(&ka->pvclock_gtod_sync_lock);
1759 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1760 }
1761
8b953440
PB		 1762 hv_clock.tsc_timestamp = ka->master_cycle_now;
1763 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1764 spin_unlock(&ka->pvclock_gtod_sync_lock);
1765
1766 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1767 &hv_clock.tsc_shift,
1768 &hv_clock.tsc_to_system_mul);
1769 return __pvclock_read_cycles(&hv_clock, rdtsc());
108b249c
PB		 1770}
1771
1772u64 get_kvmclock_ns(struct kvm *kvm)
1773{
1774 unsigned long flags;
1775 s64 ns;
1776
1777 local_irq_save(flags);
1778 ns = __get_kvmclock_ns(kvm);
1779 local_irq_restore(flags);
1780
1781 return ns;
1782}
1783
0d6dd2ff
PB		 1784static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1785{
1786 struct kvm_vcpu_arch *vcpu = &v->arch;
1787 struct pvclock_vcpu_time_info guest_hv_clock;
1788
bbd64115 1789 if (unlikely(kvm_vcpu_read_guest_cached(v, &vcpu->pv_time,
0d6dd2ff
PB		 1790 &guest_hv_clock, sizeof(guest_hv_clock))))
1791 return;
1792
1793 /* This VCPU is paused, but it's legal for a guest to read another
1794 * VCPU's kvmclock, so we really have to follow the specification where
1795 * it says that version is odd if data is being modified, and even after
1796 * it is consistent.
1797 *
1798 * Version field updates must be kept separate. This is because
1799 * kvm_write_guest_cached might use a "rep movs" instruction, and
1800 * writes within a string instruction are weakly ordered. So there
1801 * are three writes overall.
1802 *
1803 * As a small optimization, only write the version field in the first
1804 * and third write. The vcpu->pv_time cache is still valid, because the
1805 * version field is the first in the struct.
1806 */
1807 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1808
1809 vcpu->hv_clock.version = guest_hv_clock.version + 1;
bbd64115
CL		 1810 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1811 &vcpu->hv_clock,
1812 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1813
1814 smp_wmb();
1815
1816 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1817 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1818
1819 if (vcpu->pvclock_set_guest_stopped_request) {
1820 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1821 vcpu->pvclock_set_guest_stopped_request = false;
1822 }
1823
1824 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1825
bbd64115
CL		 1826 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1827 &vcpu->hv_clock,
1828 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1829
1830 smp_wmb();
1831
1832 vcpu->hv_clock.version++;
bbd64115
CL		 1833 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1834 &vcpu->hv_clock,
1835 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1836}
1837
34c238a1 1838static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1839{
78db6a50 1840 unsigned long flags, tgt_tsc_khz;
18068523 1841 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1842 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1843 s64 kernel_ns;
d828199e 1844 u64 tsc_timestamp, host_tsc;
51d59c6b 1845 u8 pvclock_flags;
d828199e
MT		 1846 bool use_master_clock;
1847
1848 kernel_ns = 0;
1849 host_tsc = 0;
18068523 1850
d828199e
MT		 1851 /*
1852 * If the host uses TSC clock, then passthrough TSC as stable
1853 * to the guest.
1854 */
1855 spin_lock(&ka->pvclock_gtod_sync_lock);
1856 use_master_clock = ka->use_master_clock;
1857 if (use_master_clock) {
1858 host_tsc = ka->master_cycle_now;
1859 kernel_ns = ka->master_kernel_ns;
1860 }
1861 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1862
1863 /* Keep irq disabled to prevent changes to the clock */
1864 local_irq_save(flags);
78db6a50
PB		 1865 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1866 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1867 local_irq_restore(flags);
1868 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1869 return 1;
1870 }
d828199e 1871 if (!use_master_clock) {
4ea1636b 1872 host_tsc = rdtsc();
108b249c 1873 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1874 }
1875
4ba76538 1876 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1877
c285545f
ZA		 1878 /*
1879 * We may have to catch up the TSC to match elapsed wall clock
1880 * time for two reasons, even if kvmclock is used.
1881 * 1) CPU could have been running below the maximum TSC rate
1882 * 2) Broken TSC compensation resets the base at each VCPU
1883 * entry to avoid unknown leaps of TSC even when running
1884 * again on the same CPU. This may cause apparent elapsed
1885 * time to disappear, and the guest to stand still or run
1886 * very slowly.
1887 */
1888 if (vcpu->tsc_catchup) {
1889 u64 tsc = compute_guest_tsc(v, kernel_ns);
1890 if (tsc > tsc_timestamp) {
f1e2b260 1891 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1892 tsc_timestamp = tsc;
1893 }
50d0a0f9
GH		 1894 }
1895
18068523
GOC		 1896 local_irq_restore(flags);
1897
0d6dd2ff 1898 /* With all the info we got, fill in the values */
18068523 1899
78db6a50
PB		 1900 if (kvm_has_tsc_control)
1901 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1902
1903 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1904 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1905 &vcpu->hv_clock.tsc_shift,
1906 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1907 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1908 }
1909
1d5f066e 1910 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1911 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1912 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1913
d828199e 1914 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1915 pvclock_flags = 0;
d828199e
MT		 1916 if (use_master_clock)
1917 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1918
78c0337a
MT		 1919 vcpu->hv_clock.flags = pvclock_flags;
1920
095cf55d
PB		 1921 if (vcpu->pv_time_enabled)
1922 kvm_setup_pvclock_page(v);
1923 if (v == kvm_get_vcpu(v->kvm, 0))
1924 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1925 return 0;
c8076604
GH		 1926}
1927
0061d53d
MT		 1928/*
1929 * kvmclock updates which are isolated to a given vcpu, such as
1930 * vcpu->cpu migration, should not allow system_timestamp from
1931 * the rest of the vcpus to remain static. Otherwise ntp frequency
1932 * correction applies to one vcpu's system_timestamp but not
1933 * the others.
1934 *
1935 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1936 * We need to rate-limit these requests though, as they can
1937 * considerably slow guests that have a large number of vcpus.
1938 * The time for a remote vcpu to update its kvmclock is bound
1939 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1940 */
1941
7e44e449
AJ		 1942#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1943
1944static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1945{
1946 int i;
7e44e449
AJ		 1947 struct delayed_work *dwork = to_delayed_work(work);
1948 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1949 kvmclock_update_work);
1950 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1951 struct kvm_vcpu *vcpu;
1952
1953 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1954 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1955 kvm_vcpu_kick(vcpu);
1956 }
1957}
1958
7e44e449
AJ		 1959static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1960{
1961 struct kvm *kvm = v->kvm;
1962
105b21bb 1963 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1964 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1965 KVMCLOCK_UPDATE_DELAY);
1966}
1967
332967a3
AJ		 1968#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1969
1970static void kvmclock_sync_fn(struct work_struct *work)
1971{
1972 struct delayed_work *dwork = to_delayed_work(work);
1973 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1974 kvmclock_sync_work);
1975 struct kvm *kvm = container_of(ka, struct kvm, arch);
1976
630994b3
MT		 1977 if (!kvmclock_periodic_sync)
1978 return;
1979
332967a3
AJ		 1980 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1981 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1982 KVMCLOCK_SYNC_PERIOD);
1983}
1984
890ca9ae 1985static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1986{
890ca9ae
HY		 1987 u64 mcg_cap = vcpu->arch.mcg_cap;
1988 unsigned bank_num = mcg_cap & 0xff;
1989
15c4a640 1990 switch (msr) {
15c4a640 1991 case MSR_IA32_MCG_STATUS:
890ca9ae 1992 vcpu->arch.mcg_status = data;
15c4a640 1993 break;
c7ac679c 1994 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1995 if (!(mcg_cap & MCG_CTL_P))
1996 return 1;
1997 if (data != 0 && data != ~(u64)0)
1998 return -1;
1999 vcpu->arch.mcg_ctl = data;
2000 break;
2001 default:
2002 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2003 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2004 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2005 /* only 0 or all 1s can be written to IA32_MCi_CTL
2006 * some Linux kernels though clear bit 10 in bank 4 to
2007 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2008 * this to avoid an uncatched #GP in the guest
2009 */
890ca9ae 2010 if ((offset & 0x3) == 0 &&
114be429 2011 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2012 return -1;
2013 vcpu->arch.mce_banks[offset] = data;
2014 break;
2015 }
2016 return 1;
2017 }
2018 return 0;
2019}
2020
ffde22ac
ES		 2021static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2022{
2023 struct kvm *kvm = vcpu->kvm;
2024 int lm = is_long_mode(vcpu);
2025 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2026 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2027 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2028 : kvm->arch.xen_hvm_config.blob_size_32;
2029 u32 page_num = data & ~PAGE_MASK;
2030 u64 page_addr = data & PAGE_MASK;
2031 u8 *page;
2032 int r;
2033
2034 r = -E2BIG;
2035 if (page_num >= blob_size)
2036 goto out;
2037 r = -ENOMEM;
ff5c2c03
SL		 2038 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2039 if (IS_ERR(page)) {
2040 r = PTR_ERR(page);
ffde22ac 2041 goto out;
ff5c2c03 2042 }
54bf36aa 2043 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2044 goto out_free;
2045 r = 0;
2046out_free:
2047 kfree(page);
2048out:
2049 return r;
2050}
2051
344d9588
GN		 2052static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2053{
2054 gpa_t gpa = data & ~0x3f;
2055
4a969980 2056 /* Bits 2:5 are reserved, Should be zero */
6adba527 2057 if (data & 0x3c)
344d9588
GN		 2058 return 1;
2059
2060 vcpu->arch.apf.msr_val = data;
2061
2062 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2063 kvm_clear_async_pf_completion_queue(vcpu);
2064 kvm_async_pf_hash_reset(vcpu);
2065 return 0;
2066 }
2067
bbd64115 2068 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.apf.data, gpa,
8f964525 2069 sizeof(u32)))
344d9588
GN		 2070 return 1;
2071
6adba527 2072 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2073 kvm_async_pf_wakeup_all(vcpu);
2074 return 0;
2075}
2076
12f9a48f
GC		 2077static void kvmclock_reset(struct kvm_vcpu *vcpu)
2078{
0b79459b 2079 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2080}
2081
c9aaa895
GC		 2082static void record_steal_time(struct kvm_vcpu *vcpu)
2083{
2084 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2085 return;
2086
bbd64115 2087 if (unlikely(kvm_vcpu_read_guest_cached(vcpu, &vcpu->arch.st.stime,
c9aaa895
GC		 2088 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2089 return;
2090
0b9f6c46
PX		 2091 vcpu->arch.st.steal.preempted = 0;
2092
35f3fae1
WL		 2093 if (vcpu->arch.st.steal.version & 1)
2094 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2095
2096 vcpu->arch.st.steal.version += 1;
2097
bbd64115 2098 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
35f3fae1
WL		 2099 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2100
2101 smp_wmb();
2102
c54cdf14
LC		 2103 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2104 vcpu->arch.st.last_steal;
2105 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2106
bbd64115 2107 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
35f3fae1
WL		 2108 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2109
2110 smp_wmb();
2111
2112 vcpu->arch.st.steal.version += 1;
c9aaa895 2113
bbd64115 2114 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
c9aaa895
GC		 2115 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2116}
2117
8fe8ab46 2118int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2119{
5753785f 2120 bool pr = false;
8fe8ab46
WA		 2121 u32 msr = msr_info->index;
2122 u64 data = msr_info->data;
5753785f 2123
15c4a640 2124 switch (msr) {
2e32b719
BP		 2125 case MSR_AMD64_NB_CFG:
2126 case MSR_IA32_UCODE_REV:
2127 case MSR_IA32_UCODE_WRITE:
2128 case MSR_VM_HSAVE_PA:
2129 case MSR_AMD64_PATCH_LOADER:
2130 case MSR_AMD64_BU_CFG2:
2131 break;
2132
15c4a640 2133 case MSR_EFER:
b69e8cae 2134 return set_efer(vcpu, data);
8f1589d9
AP		 2135 case MSR_K7_HWCR:
2136 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2137 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2138 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2139 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2140 if (data != 0) {
a737f256
CD		 2141 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2142 data);
8f1589d9
AP		 2143 return 1;
2144 }
15c4a640 2145 break;
f7c6d140
AP		 2146 case MSR_FAM10H_MMIO_CONF_BASE:
2147 if (data != 0) {
a737f256
CD		 2148 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2149 "0x%llx\n", data);
f7c6d140
AP		 2150 return 1;
2151 }
15c4a640 2152 break;
b5e2fec0
AG		 2153 case MSR_IA32_DEBUGCTLMSR:
2154 if (!data) {
2155 /* We support the non-activated case already */
2156 break;
2157 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2158 /* Values other than LBR and BTF are vendor-specific,
2159 thus reserved and should throw a #GP */
2160 return 1;
2161 }
a737f256
CD		 2162 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2163 __func__, data);
b5e2fec0 2164 break;
9ba075a6 2165 case 0x200 ... 0x2ff:
ff53604b 2166 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2167 case MSR_IA32_APICBASE:
58cb628d 2168 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2169 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2170 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2171 case MSR_IA32_TSCDEADLINE:
2172 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2173 break;
ba904635
WA		 2174 case MSR_IA32_TSC_ADJUST:
2175 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2176 if (!msr_info->host_initiated) {
d913b904 2177 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2178 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2179 }
2180 vcpu->arch.ia32_tsc_adjust_msr = data;
2181 }
2182 break;
15c4a640 2183 case MSR_IA32_MISC_ENABLE:
ad312c7c 2184 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2185 break;
64d60670
PB		 2186 case MSR_IA32_SMBASE:
2187 if (!msr_info->host_initiated)
2188 return 1;
2189 vcpu->arch.smbase = data;
2190 break;
11c6bffa 2191 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2192 case MSR_KVM_WALL_CLOCK:
2193 vcpu->kvm->arch.wall_clock = data;
2194 kvm_write_wall_clock(vcpu->kvm, data);
2195 break;
11c6bffa 2196 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2197 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2198 struct kvm_arch *ka = &vcpu->kvm->arch;
2199
12f9a48f 2200 kvmclock_reset(vcpu);
18068523 2201
54750f2c
MT		 2202 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2203 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2204
2205 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2206 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2207 &vcpu->requests);
2208
2209 ka->boot_vcpu_runs_old_kvmclock = tmp;
2210 }
2211
18068523 2212 vcpu->arch.time = data;
0061d53d 2213 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2214
2215 /* we verify if the enable bit is set... */
2216 if (!(data & 1))
2217 break;
2218
bbd64115 2219 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu,
8f964525
AH		 2220 &vcpu->arch.pv_time, data & ~1ULL,
2221 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2222 vcpu->arch.pv_time_enabled = false;
2223 else
2224 vcpu->arch.pv_time_enabled = true;
32cad84f 2225
18068523
GOC		 2226 break;
2227 }
344d9588
GN		 2228 case MSR_KVM_ASYNC_PF_EN:
2229 if (kvm_pv_enable_async_pf(vcpu, data))
2230 return 1;
2231 break;
c9aaa895
GC		 2232 case MSR_KVM_STEAL_TIME:
2233
2234 if (unlikely(!sched_info_on()))
2235 return 1;
2236
2237 if (data & KVM_STEAL_RESERVED_MASK)
2238 return 1;
2239
bbd64115 2240 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.st.stime,
8f964525
AH		 2241 data & KVM_STEAL_VALID_BITS,
2242 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2243 return 1;
2244
2245 vcpu->arch.st.msr_val = data;
2246
2247 if (!(data & KVM_MSR_ENABLED))
2248 break;
2249
c9aaa895
GC		 2250 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2251
2252 break;
ae7a2a3f
MT		 2253 case MSR_KVM_PV_EOI_EN:
2254 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2255 return 1;
2256 break;
c9aaa895 2257
890ca9ae
HY		 2258 case MSR_IA32_MCG_CTL:
2259 case MSR_IA32_MCG_STATUS:
81760dcc 2260 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2261 return set_msr_mce(vcpu, msr, data);
71db6023 2262
6912ac32
WH		 2263 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2264 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2265 pr = true; /* fall through */
2266 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2267 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2268 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2269 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2270
2271 if (pr || data != 0)
a737f256
CD		 2272 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2273 "0x%x data 0x%llx\n", msr, data);
5753785f 2274 break;
84e0cefa
JS		 2275 case MSR_K7_CLK_CTL:
2276 /*
2277 * Ignore all writes to this no longer documented MSR.
2278 * Writes are only relevant for old K7 processors,
2279 * all pre-dating SVM, but a recommended workaround from
4a969980 2280 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2281 * affected processor models on the command line, hence
2282 * the need to ignore the workaround.
2283 */
2284 break;
55cd8e5a 2285 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2286 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2287 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2288 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2289 return kvm_hv_set_msr_common(vcpu, msr, data,
2290 msr_info->host_initiated);
91c9c3ed 2291 case MSR_IA32_BBL_CR_CTL3:
2292 /* Drop writes to this legacy MSR -- see rdmsr
2293 * counterpart for further detail.
2294 */
796f4687 2295 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2296 break;
2b036c6b
BO		 2297 case MSR_AMD64_OSVW_ID_LENGTH:
2298 if (!guest_cpuid_has_osvw(vcpu))
2299 return 1;
2300 vcpu->arch.osvw.length = data;
2301 break;
2302 case MSR_AMD64_OSVW_STATUS:
2303 if (!guest_cpuid_has_osvw(vcpu))
2304 return 1;
2305 vcpu->arch.osvw.status = data;
2306 break;
15c4a640 2307 default:
ffde22ac
ES		 2308 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2309 return xen_hvm_config(vcpu, data);
c6702c9d 2310 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2311 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2312 if (!ignore_msrs) {
ae0f5499 2313 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2314 msr, data);
ed85c068
AP		 2315 return 1;
2316 } else {
796f4687 2317 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2318 msr, data);
ed85c068
AP		 2319 break;
2320 }
15c4a640
CO		 2321 }
2322 return 0;
2323}
2324EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2325
2326
2327/*
2328 * Reads an msr value (of 'msr_index') into 'pdata'.
2329 * Returns 0 on success, non-0 otherwise.
2330 * Assumes vcpu_load() was already called.
2331 */
609e36d3 2332int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2333{
609e36d3 2334 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2335}
ff651cb6 2336EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2337
890ca9ae 2338static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2339{
2340 u64 data;
890ca9ae
HY		 2341 u64 mcg_cap = vcpu->arch.mcg_cap;
2342 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2343
2344 switch (msr) {
15c4a640
CO		 2345 case MSR_IA32_P5_MC_ADDR:
2346 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2347 data = 0;
2348 break;
15c4a640 2349 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2350 data = vcpu->arch.mcg_cap;
2351 break;
c7ac679c 2352 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2353 if (!(mcg_cap & MCG_CTL_P))
2354 return 1;
2355 data = vcpu->arch.mcg_ctl;
2356 break;
2357 case MSR_IA32_MCG_STATUS:
2358 data = vcpu->arch.mcg_status;
2359 break;
2360 default:
2361 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2362 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2363 u32 offset = msr - MSR_IA32_MC0_CTL;
2364 data = vcpu->arch.mce_banks[offset];
2365 break;
2366 }
2367 return 1;
2368 }
2369 *pdata = data;
2370 return 0;
2371}
2372
609e36d3 2373int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2374{
609e36d3 2375 switch (msr_info->index) {
890ca9ae 2376 case MSR_IA32_PLATFORM_ID:
15c4a640 2377 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2378 case MSR_IA32_DEBUGCTLMSR:
2379 case MSR_IA32_LASTBRANCHFROMIP:
2380 case MSR_IA32_LASTBRANCHTOIP:
2381 case MSR_IA32_LASTINTFROMIP:
2382 case MSR_IA32_LASTINTTOIP:
60af2ecd 2383 case MSR_K8_SYSCFG:
3afb1121
PB		 2384 case MSR_K8_TSEG_ADDR:
2385 case MSR_K8_TSEG_MASK:
60af2ecd 2386 case MSR_K7_HWCR:
61a6bd67 2387 case MSR_VM_HSAVE_PA:
1fdbd48c 2388 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2389 case MSR_AMD64_NB_CFG:
f7c6d140 2390 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2391 case MSR_AMD64_BU_CFG2:
0c2df2a1 2392 case MSR_IA32_PERF_CTL:
609e36d3 2393 msr_info->data = 0;
15c4a640 2394 break;
6912ac32
WH		 2395 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2396 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2397 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2398 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2399 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2400 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2401 msr_info->data = 0;
5753785f 2402 break;
742bc670 2403 case MSR_IA32_UCODE_REV:
609e36d3 2404 msr_info->data = 0x100000000ULL;
742bc670 2405 break;
9ba075a6 2406 case MSR_MTRRcap:
9ba075a6 2407 case 0x200 ... 0x2ff:
ff53604b 2408 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2409 case 0xcd: /* fsb frequency */
609e36d3 2410 msr_info->data = 3;
15c4a640 2411 break;
7b914098
JS		 2412 /*
2413 * MSR_EBC_FREQUENCY_ID
2414 * Conservative value valid for even the basic CPU models.
2415 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2416 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2417 * and 266MHz for model 3, or 4. Set Core Clock
2418 * Frequency to System Bus Frequency Ratio to 1 (bits
2419 * 31:24) even though these are only valid for CPU
2420 * models > 2, however guests may end up dividing or
2421 * multiplying by zero otherwise.
2422 */
2423 case MSR_EBC_FREQUENCY_ID:
609e36d3 2424 msr_info->data = 1 << 24;
7b914098 2425 break;
15c4a640 2426 case MSR_IA32_APICBASE:
609e36d3 2427 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2428 break;
0105d1a5 2429 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2430 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2431 break;
a3e06bbe 2432 case MSR_IA32_TSCDEADLINE:
609e36d3 2433 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2434 break;
ba904635 2435 case MSR_IA32_TSC_ADJUST:
609e36d3 2436 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2437 break;
15c4a640 2438 case MSR_IA32_MISC_ENABLE:
609e36d3 2439 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2440 break;
64d60670
PB		 2441 case MSR_IA32_SMBASE:
2442 if (!msr_info->host_initiated)
2443 return 1;
2444 msr_info->data = vcpu->arch.smbase;
15c4a640 2445 break;
847f0ad8
AG		 2446 case MSR_IA32_PERF_STATUS:
2447 /* TSC increment by tick */
609e36d3 2448 msr_info->data = 1000ULL;
847f0ad8 2449 /* CPU multiplier */
b0996ae4 2450 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2451 break;
15c4a640 2452 case MSR_EFER:
609e36d3 2453 msr_info->data = vcpu->arch.efer;
15c4a640 2454 break;
18068523 2455 case MSR_KVM_WALL_CLOCK:
11c6bffa 2456 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2457 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2458 break;
2459 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2460 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2461 msr_info->data = vcpu->arch.time;
18068523 2462 break;
344d9588 2463 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2464 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2465 break;
c9aaa895 2466 case MSR_KVM_STEAL_TIME:
609e36d3 2467 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2468 break;
1d92128f 2469 case MSR_KVM_PV_EOI_EN:
609e36d3 2470 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2471 break;
890ca9ae
HY		 2472 case MSR_IA32_P5_MC_ADDR:
2473 case MSR_IA32_P5_MC_TYPE:
2474 case MSR_IA32_MCG_CAP:
2475 case MSR_IA32_MCG_CTL:
2476 case MSR_IA32_MCG_STATUS:
81760dcc 2477 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2478 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2479 case MSR_K7_CLK_CTL:
2480 /*
2481 * Provide expected ramp-up count for K7. All other
2482 * are set to zero, indicating minimum divisors for
2483 * every field.
2484 *
2485 * This prevents guest kernels on AMD host with CPU
2486 * type 6, model 8 and higher from exploding due to
2487 * the rdmsr failing.
2488 */
609e36d3 2489 msr_info->data = 0x20000000;
84e0cefa 2490 break;
55cd8e5a 2491 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2492 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2493 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2494 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2495 return kvm_hv_get_msr_common(vcpu,
2496 msr_info->index, &msr_info->data);
55cd8e5a 2497 break;
91c9c3ed 2498 case MSR_IA32_BBL_CR_CTL3:
2499 /* This legacy MSR exists but isn't fully documented in current
2500 * silicon. It is however accessed by winxp in very narrow
2501 * scenarios where it sets bit #19, itself documented as
2502 * a "reserved" bit. Best effort attempt to source coherent
2503 * read data here should the balance of the register be
2504 * interpreted by the guest:
2505 *
2506 * L2 cache control register 3: 64GB range, 256KB size,
2507 * enabled, latency 0x1, configured
2508 */
609e36d3 2509 msr_info->data = 0xbe702111;
91c9c3ed 2510 break;
2b036c6b
BO		 2511 case MSR_AMD64_OSVW_ID_LENGTH:
2512 if (!guest_cpuid_has_osvw(vcpu))
2513 return 1;
609e36d3 2514 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2515 break;
2516 case MSR_AMD64_OSVW_STATUS:
2517 if (!guest_cpuid_has_osvw(vcpu))
2518 return 1;
609e36d3 2519 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2520 break;
15c4a640 2521 default:
c6702c9d 2522 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2523 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2524 if (!ignore_msrs) {
ae0f5499
BD		 2525 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2526 msr_info->index);
ed85c068
AP		 2527 return 1;
2528 } else {
609e36d3
PB		 2529 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2530 msr_info->data = 0;
ed85c068
AP		 2531 }
2532 break;
15c4a640 2533 }
15c4a640
CO		 2534 return 0;
2535}
2536EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2537
313a3dc7
CO		 2538/*
2539 * Read or write a bunch of msrs. All parameters are kernel addresses.
2540 *
2541 * @return number of msrs set successfully.
2542 */
2543static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2544 struct kvm_msr_entry *entries,
2545 int (*do_msr)(struct kvm_vcpu *vcpu,
2546 unsigned index, u64 *data))
2547{
f656ce01 2548 int i, idx;
313a3dc7 2549
f656ce01 2550 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2551 for (i = 0; i < msrs->nmsrs; ++i)
2552 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2553 break;
f656ce01 2554 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2555
313a3dc7
CO		 2556 return i;
2557}
2558
2559/*
2560 * Read or write a bunch of msrs. Parameters are user addresses.
2561 *
2562 * @return number of msrs set successfully.
2563 */
2564static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2565 int (*do_msr)(struct kvm_vcpu *vcpu,
2566 unsigned index, u64 *data),
2567 int writeback)
2568{
2569 struct kvm_msrs msrs;
2570 struct kvm_msr_entry *entries;
2571 int r, n;
2572 unsigned size;
2573
2574 r = -EFAULT;
2575 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2576 goto out;
2577
2578 r = -E2BIG;
2579 if (msrs.nmsrs >= MAX_IO_MSRS)
2580 goto out;
2581
313a3dc7 2582 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2583 entries = memdup_user(user_msrs->entries, size);
2584 if (IS_ERR(entries)) {
2585 r = PTR_ERR(entries);
313a3dc7 2586 goto out;
ff5c2c03 2587 }
313a3dc7
CO		 2588
2589 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2590 if (r < 0)
2591 goto out_free;
2592
2593 r = -EFAULT;
2594 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2595 goto out_free;
2596
2597 r = n;
2598
2599out_free:
7a73c028 2600 kfree(entries);
313a3dc7
CO		 2601out:
2602 return r;
2603}
2604
784aa3d7 2605int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2606{
2607 int r;
2608
2609 switch (ext) {
2610 case KVM_CAP_IRQCHIP:
2611 case KVM_CAP_HLT:
2612 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2613 case KVM_CAP_SET_TSS_ADDR:
07716717 2614 case KVM_CAP_EXT_CPUID:
9c15bb1d 2615 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2616 case KVM_CAP_CLOCKSOURCE:
7837699f 2617 case KVM_CAP_PIT:
a28e4f5a 2618 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2619 case KVM_CAP_MP_STATE:
ed848624 2620 case KVM_CAP_SYNC_MMU:
a355c85c 2621 case KVM_CAP_USER_NMI:
52d939a0 2622 case KVM_CAP_REINJECT_CONTROL:
4925663a 2623 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2624 case KVM_CAP_IOEVENTFD:
f848a5a8 2625 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2626 case KVM_CAP_PIT2:
e9f42757 2627 case KVM_CAP_PIT_STATE2:
b927a3ce 2628 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2629 case KVM_CAP_XEN_HVM:
3cfc3092 2630 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2631 case KVM_CAP_HYPERV:
10388a07 2632 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2633 case KVM_CAP_HYPERV_SPIN:
5c919412 2634 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2635 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2636 case KVM_CAP_DEBUGREGS:
d2be1651 2637 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2638 case KVM_CAP_XSAVE:
344d9588 2639 case KVM_CAP_ASYNC_PF:
92a1f12d 2640 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2641 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2642 case KVM_CAP_READONLY_MEM:
5f66b620 2643 case KVM_CAP_HYPERV_TIME:
100943c5 2644 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2645 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2646 case KVM_CAP_ENABLE_CAP_VM:
2647 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2648 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2649 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2650 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2651 r = 1;
2652 break;
e3fd9a93
PB		 2653 case KVM_CAP_ADJUST_CLOCK:
2654 r = KVM_CLOCK_TSC_STABLE;
2655 break;
6d396b55
PB		 2656 case KVM_CAP_X86_SMM:
2657 /* SMBASE is usually relocated above 1M on modern chipsets,
2658 * and SMM handlers might indeed rely on 4G segment limits,
2659 * so do not report SMM to be available if real mode is
2660 * emulated via vm86 mode. Still, do not go to great lengths
2661 * to avoid userspace's usage of the feature, because it is a
2662 * fringe case that is not enabled except via specific settings
2663 * of the module parameters.
2664 */
2665 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2666 break;
774ead3a
AK		 2667 case KVM_CAP_VAPIC:
2668 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2669 break;
f725230a 2670 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2671 r = KVM_SOFT_MAX_VCPUS;
2672 break;
2673 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2674 r = KVM_MAX_VCPUS;
2675 break;
a988b910 2676 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2677 r = KVM_USER_MEM_SLOTS;
a988b910 2678 break;
a68a6a72
MT		 2679 case KVM_CAP_PV_MMU: /* obsolete */
2680 r = 0;
2f333bcb 2681 break;
890ca9ae
HY		 2682 case KVM_CAP_MCE:
2683 r = KVM_MAX_MCE_BANKS;
2684 break;
2d5b5a66 2685 case KVM_CAP_XCRS:
d366bf7e 2686 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2687 break;
92a1f12d
JR		 2688 case KVM_CAP_TSC_CONTROL:
2689 r = kvm_has_tsc_control;
2690 break;
37131313
RK		 2691 case KVM_CAP_X2APIC_API:
2692 r = KVM_X2APIC_API_VALID_FLAGS;
2693 break;
018d00d2
ZX		 2694 default:
2695 r = 0;
2696 break;
2697 }
2698 return r;
2699
2700}
2701
043405e1
CO		 2702long kvm_arch_dev_ioctl(struct file *filp,
2703 unsigned int ioctl, unsigned long arg)
2704{
2705 void __user *argp = (void __user *)arg;
2706 long r;
2707
2708 switch (ioctl) {
2709 case KVM_GET_MSR_INDEX_LIST: {
2710 struct kvm_msr_list __user *user_msr_list = argp;
2711 struct kvm_msr_list msr_list;
2712 unsigned n;
2713
2714 r = -EFAULT;
2715 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2716 goto out;
2717 n = msr_list.nmsrs;
62ef68bb 2718 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2719 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2720 goto out;
2721 r = -E2BIG;
e125e7b6 2722 if (n < msr_list.nmsrs)
043405e1
CO		 2723 goto out;
2724 r = -EFAULT;
2725 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2726 num_msrs_to_save * sizeof(u32)))
2727 goto out;
e125e7b6 2728 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2729 &emulated_msrs,
62ef68bb 2730 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2731 goto out;
2732 r = 0;
2733 break;
2734 }
9c15bb1d
BP		 2735 case KVM_GET_SUPPORTED_CPUID:
2736 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2737 struct kvm_cpuid2 __user *cpuid_arg = argp;
2738 struct kvm_cpuid2 cpuid;
2739
2740 r = -EFAULT;
2741 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2742 goto out;
9c15bb1d
BP		 2743
2744 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2745 ioctl);
674eea0f
AK		 2746 if (r)
2747 goto out;
2748
2749 r = -EFAULT;
2750 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2751 goto out;
2752 r = 0;
2753 break;
2754 }
890ca9ae 2755 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2756 r = -EFAULT;
c45dcc71
AR		 2757 if (copy_to_user(argp, &kvm_mce_cap_supported,
2758 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2759 goto out;
2760 r = 0;
2761 break;
2762 }
043405e1
CO		 2763 default:
2764 r = -EINVAL;
2765 }
2766out:
2767 return r;
2768}
2769
f5f48ee1
SY		 2770static void wbinvd_ipi(void *garbage)
2771{
2772 wbinvd();
2773}
2774
2775static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2776{
e0f0bbc5 2777 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2778}
2779
2860c4b1
PB		 2780static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2781{
2782 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2783}
2784
313a3dc7
CO		 2785void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2786{
f5f48ee1
SY		 2787 /* Address WBINVD may be executed by guest */
2788 if (need_emulate_wbinvd(vcpu)) {
2789 if (kvm_x86_ops->has_wbinvd_exit())
2790 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2791 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2792 smp_call_function_single(vcpu->cpu,
2793 wbinvd_ipi, NULL, 1);
2794 }
2795
313a3dc7 2796 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2797
0dd6a6ed
ZA		 2798 /* Apply any externally detected TSC adjustments (due to suspend) */
2799 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2800 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2801 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2802 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2803 }
8f6055cb 2804
48434c20 2805 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2806 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2807 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2808 if (tsc_delta < 0)
2809 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2810
c285545f 2811 if (check_tsc_unstable()) {
07c1419a 2812 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2813 vcpu->arch.last_guest_tsc);
a545ab6a 2814 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2815 vcpu->arch.tsc_catchup = 1;
c285545f 2816 }
e12c8f36
WL		 2817 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2818 kvm_x86_ops->set_hv_timer(vcpu,
498f8162 2819 kvm_get_lapic_target_expiration_tsc(vcpu)))
e12c8f36 2820 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2821 /*
2822 * On a host with synchronized TSC, there is no need to update
2823 * kvmclock on vcpu->cpu migration
2824 */
2825 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2826 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2827 if (vcpu->cpu != cpu)
2828 kvm_migrate_timers(vcpu);
e48672fa 2829 vcpu->cpu = cpu;
6b7d7e76 2830 }
c9aaa895 2831
c9aaa895 2832 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2833}
2834
0b9f6c46
PX		 2835static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2836{
2837 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2838 return;
2839
2840 vcpu->arch.st.steal.preempted = 1;
2841
bbd64115 2842 kvm_vcpu_write_guest_offset_cached(vcpu, &vcpu->arch.st.stime,
0b9f6c46
PX		 2843 &vcpu->arch.st.steal.preempted,
2844 offsetof(struct kvm_steal_time, preempted),
2845 sizeof(vcpu->arch.st.steal.preempted));
2846}
2847
313a3dc7
CO		 2848void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2849{
cc0d907c 2850 int idx;
931f261b
AA		 2851 /*
2852 * Disable page faults because we're in atomic context here.
2853 * kvm_write_guest_offset_cached() would call might_fault()
2854 * that relies on pagefault_disable() to tell if there's a
2855 * bug. NOTE: the write to guest memory may not go through if
2856 * during postcopy live migration or if there's heavy guest
2857 * paging.
2858 */
2859 pagefault_disable();
cc0d907c
AA		 2860 /*
2861 * kvm_memslots() will be called by
2862 * kvm_write_guest_offset_cached() so take the srcu lock.
2863 */
2864 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2865 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2866 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2867 pagefault_enable();
02daab21 2868 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2869 kvm_put_guest_fpu(vcpu);
4ea1636b 2870 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2871}
2872
313a3dc7
CO		 2873static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2874 struct kvm_lapic_state *s)
2875{
76dfafd5 2876 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2877 kvm_x86_ops->sync_pir_to_irr(vcpu);
2878
a92e2543 2879 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2880}
2881
2882static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2883 struct kvm_lapic_state *s)
2884{
a92e2543
RK		 2885 int r;
2886
2887 r = kvm_apic_set_state(vcpu, s);
2888 if (r)
2889 return r;
cb142eb7 2890 update_cr8_intercept(vcpu);
313a3dc7
CO		 2891
2892 return 0;
2893}
2894
127a457a
MG		 2895static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2896{
2897 return (!lapic_in_kernel(vcpu) ||
2898 kvm_apic_accept_pic_intr(vcpu));
2899}
2900
782d422b
MG		 2901/*
2902 * if userspace requested an interrupt window, check that the
2903 * interrupt window is open.
2904 *
2905 * No need to exit to userspace if we already have an interrupt queued.
2906 */
2907static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2908{
2909 return kvm_arch_interrupt_allowed(vcpu) &&
2910 !kvm_cpu_has_interrupt(vcpu) &&
2911 !kvm_event_needs_reinjection(vcpu) &&
2912 kvm_cpu_accept_dm_intr(vcpu);
2913}
2914
f77bc6a4
ZX		 2915static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2916 struct kvm_interrupt *irq)
2917{
02cdb50f 2918 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2919 return -EINVAL;
1c1a9ce9
SR		 2920
2921 if (!irqchip_in_kernel(vcpu->kvm)) {
2922 kvm_queue_interrupt(vcpu, irq->irq, false);
2923 kvm_make_request(KVM_REQ_EVENT, vcpu);
2924 return 0;
2925 }
2926
2927 /*
2928 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2929 * fail for in-kernel 8259.
2930 */
2931 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2932 return -ENXIO;
f77bc6a4 2933
1c1a9ce9
SR		 2934 if (vcpu->arch.pending_external_vector != -1)
2935 return -EEXIST;
f77bc6a4 2936
1c1a9ce9 2937 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2938 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2939 return 0;
2940}
2941
c4abb7c9
JK		 2942static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2943{
c4abb7c9 2944 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2945
2946 return 0;
2947}
2948
f077825a
PB		 2949static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2950{
64d60670
PB		 2951 kvm_make_request(KVM_REQ_SMI, vcpu);
2952
f077825a
PB		 2953 return 0;
2954}
2955
b209749f
AK		 2956static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2957 struct kvm_tpr_access_ctl *tac)
2958{
2959 if (tac->flags)
2960 return -EINVAL;
2961 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2962 return 0;
2963}
2964
890ca9ae
HY		 2965static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2966 u64 mcg_cap)
2967{
2968 int r;
2969 unsigned bank_num = mcg_cap & 0xff, bank;
2970
2971 r = -EINVAL;
a9e38c3e 2972 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2973 goto out;
c45dcc71 2974 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2975 goto out;
2976 r = 0;
2977 vcpu->arch.mcg_cap = mcg_cap;
2978 /* Init IA32_MCG_CTL to all 1s */
2979 if (mcg_cap & MCG_CTL_P)
2980 vcpu->arch.mcg_ctl = ~(u64)0;
2981 /* Init IA32_MCi_CTL to all 1s */
2982 for (bank = 0; bank < bank_num; bank++)
2983 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 2984
2985 if (kvm_x86_ops->setup_mce)
2986 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 2987out:
2988 return r;
2989}
2990
2991static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2992 struct kvm_x86_mce *mce)
2993{
2994 u64 mcg_cap = vcpu->arch.mcg_cap;
2995 unsigned bank_num = mcg_cap & 0xff;
2996 u64 *banks = vcpu->arch.mce_banks;
2997
2998 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2999 return -EINVAL;
3000 /*
3001 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3002 * reporting is disabled
3003 */
3004 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3005 vcpu->arch.mcg_ctl != ~(u64)0)
3006 return 0;
3007 banks += 4 * mce->bank;
3008 /*
3009 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3010 * reporting is disabled for the bank
3011 */
3012 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3013 return 0;
3014 if (mce->status & MCI_STATUS_UC) {
3015 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3016 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3017 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3018 return 0;
3019 }
3020 if (banks[1] & MCI_STATUS_VAL)
3021 mce->status |= MCI_STATUS_OVER;
3022 banks[2] = mce->addr;
3023 banks[3] = mce->misc;
3024 vcpu->arch.mcg_status = mce->mcg_status;
3025 banks[1] = mce->status;
3026 kvm_queue_exception(vcpu, MC_VECTOR);
3027 } else if (!(banks[1] & MCI_STATUS_VAL)
3028 || !(banks[1] & MCI_STATUS_UC)) {
3029 if (banks[1] & MCI_STATUS_VAL)
3030 mce->status |= MCI_STATUS_OVER;
3031 banks[2] = mce->addr;
3032 banks[3] = mce->misc;
3033 banks[1] = mce->status;
3034 } else
3035 banks[1] |= MCI_STATUS_OVER;
3036 return 0;
3037}
3038
3cfc3092
JK		 3039static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3040 struct kvm_vcpu_events *events)
3041{
7460fb4a 3042 process_nmi(vcpu);
03b82a30
JK		 3043 events->exception.injected =
3044 vcpu->arch.exception.pending &&
3045 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3046 events->exception.nr = vcpu->arch.exception.nr;
3047 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3048 events->exception.pad = 0;
3cfc3092
JK		 3049 events->exception.error_code = vcpu->arch.exception.error_code;
3050
03b82a30
JK		 3051 events->interrupt.injected =
3052 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3053 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3054 events->interrupt.soft = 0;
37ccdcbe 3055 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3056
3057 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3058 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3059 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3060 events->nmi.pad = 0;
3cfc3092 3061
66450a21 3062 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3063
f077825a
PB		 3064 events->smi.smm = is_smm(vcpu);
3065 events->smi.pending = vcpu->arch.smi_pending;
3066 events->smi.smm_inside_nmi =
3067 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3068 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3069
dab4b911 3070 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3071 | KVM_VCPUEVENT_VALID_SHADOW
3072 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3073 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3074}
3075
6ef4e07e
XG		 3076static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3077
3cfc3092
JK		 3078static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3079 struct kvm_vcpu_events *events)
3080{
dab4b911 3081 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3082 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3083 | KVM_VCPUEVENT_VALID_SHADOW
3084 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3085 return -EINVAL;
3086
78e546c8 3087 if (events->exception.injected &&
28d06353
JM		 3088 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3089 is_guest_mode(vcpu)))
78e546c8
PB		 3090 return -EINVAL;
3091
28bf2888
DH		 3092 /* INITs are latched while in SMM */
3093 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3094 (events->smi.smm || events->smi.pending) &&
3095 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3096 return -EINVAL;
3097
7460fb4a 3098 process_nmi(vcpu);
3cfc3092
JK		 3099 vcpu->arch.exception.pending = events->exception.injected;
3100 vcpu->arch.exception.nr = events->exception.nr;
3101 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3102 vcpu->arch.exception.error_code = events->exception.error_code;
3103
3104 vcpu->arch.interrupt.pending = events->interrupt.injected;
3105 vcpu->arch.interrupt.nr = events->interrupt.nr;
3106 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3107 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3108 kvm_x86_ops->set_interrupt_shadow(vcpu,
3109 events->interrupt.shadow);
3cfc3092
JK		 3110
3111 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3112 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3113 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3114 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3115
66450a21 3116 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3117 lapic_in_kernel(vcpu))
66450a21 3118 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3119
f077825a 3120 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3121 u32 hflags = vcpu->arch.hflags;
f077825a 3122 if (events->smi.smm)
6ef4e07e 3123 hflags |= HF_SMM_MASK;
f077825a 3124 else
6ef4e07e
XG		 3125 hflags &= ~HF_SMM_MASK;
3126 kvm_set_hflags(vcpu, hflags);
3127
f077825a
PB		 3128 vcpu->arch.smi_pending = events->smi.pending;
3129 if (events->smi.smm_inside_nmi)
3130 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3131 else
3132 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3133 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3134 if (events->smi.latched_init)
3135 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3136 else
3137 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3138 }
3139 }
3140
3842d135
AK		 3141 kvm_make_request(KVM_REQ_EVENT, vcpu);
3142
3cfc3092
JK		 3143 return 0;
3144}
3145
a1efbe77
JK		 3146static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3147 struct kvm_debugregs *dbgregs)
3148{
73aaf249
JK		 3149 unsigned long val;
3150
a1efbe77 3151 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3152 kvm_get_dr(vcpu, 6, &val);
73aaf249 3153 dbgregs->dr6 = val;
a1efbe77
JK		 3154 dbgregs->dr7 = vcpu->arch.dr7;
3155 dbgregs->flags = 0;
97e69aa6 3156 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3157}
3158
3159static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3160 struct kvm_debugregs *dbgregs)
3161{
3162 if (dbgregs->flags)
3163 return -EINVAL;
3164
d14bdb55
PB		 3165 if (dbgregs->dr6 & ~0xffffffffull)
3166 return -EINVAL;
3167 if (dbgregs->dr7 & ~0xffffffffull)
3168 return -EINVAL;
3169
a1efbe77 3170 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3171 kvm_update_dr0123(vcpu);
a1efbe77 3172 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3173 kvm_update_dr6(vcpu);
a1efbe77 3174 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3175 kvm_update_dr7(vcpu);
a1efbe77 3176
a1efbe77
JK		 3177 return 0;
3178}
3179
df1daba7
PB		 3180#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3181
3182static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3183{
c47ada30 3184 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3185 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3186 u64 valid;
3187
3188 /*
3189 * Copy legacy XSAVE area, to avoid complications with CPUID
3190 * leaves 0 and 1 in the loop below.
3191 */
3192 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3193
3194 /* Set XSTATE_BV */
00c87e9a 3195 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3196 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3197
3198 /*
3199 * Copy each region from the possibly compacted offset to the
3200 * non-compacted offset.
3201 */
d91cab78 3202 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3203 while (valid) {
3204 u64 feature = valid & -valid;
3205 int index = fls64(feature) - 1;
3206 void *src = get_xsave_addr(xsave, feature);
3207
3208 if (src) {
3209 u32 size, offset, ecx, edx;
3210 cpuid_count(XSTATE_CPUID, index,
3211 &size, &offset, &ecx, &edx);
3212 memcpy(dest + offset, src, size);
3213 }
3214
3215 valid -= feature;
3216 }
3217}
3218
3219static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3220{
c47ada30 3221 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3222 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3223 u64 valid;
3224
3225 /*
3226 * Copy legacy XSAVE area, to avoid complications with CPUID
3227 * leaves 0 and 1 in the loop below.
3228 */
3229 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3230
3231 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3232 xsave->header.xfeatures = xstate_bv;
782511b0 3233 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3234 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3235
3236 /*
3237 * Copy each region from the non-compacted offset to the
3238 * possibly compacted offset.
3239 */
d91cab78 3240 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3241 while (valid) {
3242 u64 feature = valid & -valid;
3243 int index = fls64(feature) - 1;
3244 void *dest = get_xsave_addr(xsave, feature);
3245
3246 if (dest) {
3247 u32 size, offset, ecx, edx;
3248 cpuid_count(XSTATE_CPUID, index,
3249 &size, &offset, &ecx, &edx);
3250 memcpy(dest, src + offset, size);
ee4100da 3251 }
df1daba7
PB		 3252
3253 valid -= feature;
3254 }
3255}
3256
2d5b5a66
SY		 3257static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3258 struct kvm_xsave *guest_xsave)
3259{
d366bf7e 3260 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3261 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3262 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3263 } else {
2d5b5a66 3264 memcpy(guest_xsave->region,
7366ed77 3265 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3266 sizeof(struct fxregs_state));
2d5b5a66 3267 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3268 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3269 }
3270}
3271
3272static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3273 struct kvm_xsave *guest_xsave)
3274{
3275 u64 xstate_bv =
3276 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3277
d366bf7e 3278 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3279 /*
3280 * Here we allow setting states that are not present in
3281 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3282 * with old userspace.
3283 */
4ff41732 3284 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3285 return -EINVAL;
df1daba7 3286 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3287 } else {
d91cab78 3288 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3289 return -EINVAL;
7366ed77 3290 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3291 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3292 }
3293 return 0;
3294}
3295
3296static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3297 struct kvm_xcrs *guest_xcrs)
3298{
d366bf7e 3299 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3300 guest_xcrs->nr_xcrs = 0;
3301 return;
3302 }
3303
3304 guest_xcrs->nr_xcrs = 1;
3305 guest_xcrs->flags = 0;
3306 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3307 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3308}
3309
3310static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3311 struct kvm_xcrs *guest_xcrs)
3312{
3313 int i, r = 0;
3314
d366bf7e 3315 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3316 return -EINVAL;
3317
3318 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3319 return -EINVAL;
3320
3321 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3322 /* Only support XCR0 currently */
c67a04cb 3323 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3324 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3325 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3326 break;
3327 }
3328 if (r)
3329 r = -EINVAL;
3330 return r;
3331}
3332
1c0b28c2
EM		 3333/*
3334 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3335 * stopped by the hypervisor. This function will be called from the host only.
3336 * EINVAL is returned when the host attempts to set the flag for a guest that
3337 * does not support pv clocks.
3338 */
3339static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3340{
0b79459b 3341 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3342 return -EINVAL;
51d59c6b 3343 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3344 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3345 return 0;
3346}
3347
5c919412
AS		 3348static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3349 struct kvm_enable_cap *cap)
3350{
3351 if (cap->flags)
3352 return -EINVAL;
3353
3354 switch (cap->cap) {
3355 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3356 if (!irqchip_in_kernel(vcpu->kvm))
3357 return -EINVAL;
5c919412
AS		 3358 return kvm_hv_activate_synic(vcpu);
3359 default:
3360 return -EINVAL;
3361 }
3362}
3363
313a3dc7
CO		 3364long kvm_arch_vcpu_ioctl(struct file *filp,
3365 unsigned int ioctl, unsigned long arg)
3366{
3367 struct kvm_vcpu *vcpu = filp->private_data;
3368 void __user *argp = (void __user *)arg;
3369 int r;
d1ac91d8
AK		 3370 union {
3371 struct kvm_lapic_state *lapic;
3372 struct kvm_xsave *xsave;
3373 struct kvm_xcrs *xcrs;
3374 void *buffer;
3375 } u;
3376
3377 u.buffer = NULL;
313a3dc7
CO		 3378 switch (ioctl) {
3379 case KVM_GET_LAPIC: {
2204ae3c 3380 r = -EINVAL;
bce87cce 3381 if (!lapic_in_kernel(vcpu))
2204ae3c 3382 goto out;
d1ac91d8 3383 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3384
b772ff36 3385 r = -ENOMEM;
d1ac91d8 3386 if (!u.lapic)
b772ff36 3387 goto out;
d1ac91d8 3388 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3389 if (r)
3390 goto out;
3391 r = -EFAULT;
d1ac91d8 3392 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3393 goto out;
3394 r = 0;
3395 break;
3396 }
3397 case KVM_SET_LAPIC: {
2204ae3c 3398 r = -EINVAL;
bce87cce 3399 if (!lapic_in_kernel(vcpu))
2204ae3c 3400 goto out;
ff5c2c03 3401 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3402 if (IS_ERR(u.lapic))
3403 return PTR_ERR(u.lapic);
ff5c2c03 3404
d1ac91d8 3405 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3406 break;
3407 }
f77bc6a4
ZX		 3408 case KVM_INTERRUPT: {
3409 struct kvm_interrupt irq;
3410
3411 r = -EFAULT;
3412 if (copy_from_user(&irq, argp, sizeof irq))
3413 goto out;
3414 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3415 break;
3416 }
c4abb7c9
JK		 3417 case KVM_NMI: {
3418 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3419 break;
3420 }
f077825a
PB		 3421 case KVM_SMI: {
3422 r = kvm_vcpu_ioctl_smi(vcpu);
3423 break;
3424 }
313a3dc7
CO		 3425 case KVM_SET_CPUID: {
3426 struct kvm_cpuid __user *cpuid_arg = argp;
3427 struct kvm_cpuid cpuid;
3428
3429 r = -EFAULT;
3430 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3431 goto out;
3432 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3433 break;
3434 }
07716717
DK		 3435 case KVM_SET_CPUID2: {
3436 struct kvm_cpuid2 __user *cpuid_arg = argp;
3437 struct kvm_cpuid2 cpuid;
3438
3439 r = -EFAULT;
3440 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3441 goto out;
3442 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3443 cpuid_arg->entries);
07716717
DK		 3444 break;
3445 }
3446 case KVM_GET_CPUID2: {
3447 struct kvm_cpuid2 __user *cpuid_arg = argp;
3448 struct kvm_cpuid2 cpuid;
3449
3450 r = -EFAULT;
3451 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3452 goto out;
3453 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3454 cpuid_arg->entries);
07716717
DK		 3455 if (r)
3456 goto out;
3457 r = -EFAULT;
3458 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3459 goto out;
3460 r = 0;
3461 break;
3462 }
313a3dc7 3463 case KVM_GET_MSRS:
609e36d3 3464 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3465 break;
3466 case KVM_SET_MSRS:
3467 r = msr_io(vcpu, argp, do_set_msr, 0);
3468 break;
b209749f
AK		 3469 case KVM_TPR_ACCESS_REPORTING: {
3470 struct kvm_tpr_access_ctl tac;
3471
3472 r = -EFAULT;
3473 if (copy_from_user(&tac, argp, sizeof tac))
3474 goto out;
3475 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3476 if (r)
3477 goto out;
3478 r = -EFAULT;
3479 if (copy_to_user(argp, &tac, sizeof tac))
3480 goto out;
3481 r = 0;
3482 break;
3483 };
b93463aa
AK		 3484 case KVM_SET_VAPIC_ADDR: {
3485 struct kvm_vapic_addr va;
7301d6ab 3486 int idx;
b93463aa
AK		 3487
3488 r = -EINVAL;
35754c98 3489 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3490 goto out;
3491 r = -EFAULT;
3492 if (copy_from_user(&va, argp, sizeof va))
3493 goto out;
7301d6ab 3494 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3495 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3496 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3497 break;
3498 }
890ca9ae
HY		 3499 case KVM_X86_SETUP_MCE: {
3500 u64 mcg_cap;
3501
3502 r = -EFAULT;
3503 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3504 goto out;
3505 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3506 break;
3507 }
3508 case KVM_X86_SET_MCE: {
3509 struct kvm_x86_mce mce;
3510
3511 r = -EFAULT;
3512 if (copy_from_user(&mce, argp, sizeof mce))
3513 goto out;
3514 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3515 break;
3516 }
3cfc3092
JK		 3517 case KVM_GET_VCPU_EVENTS: {
3518 struct kvm_vcpu_events events;
3519
3520 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3521
3522 r = -EFAULT;
3523 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3524 break;
3525 r = 0;
3526 break;
3527 }
3528 case KVM_SET_VCPU_EVENTS: {
3529 struct kvm_vcpu_events events;
3530
3531 r = -EFAULT;
3532 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3533 break;
3534
3535 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3536 break;
3537 }
a1efbe77
JK		 3538 case KVM_GET_DEBUGREGS: {
3539 struct kvm_debugregs dbgregs;
3540
3541 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3542
3543 r = -EFAULT;
3544 if (copy_to_user(argp, &dbgregs,
3545 sizeof(struct kvm_debugregs)))
3546 break;
3547 r = 0;
3548 break;
3549 }
3550 case KVM_SET_DEBUGREGS: {
3551 struct kvm_debugregs dbgregs;
3552
3553 r = -EFAULT;
3554 if (copy_from_user(&dbgregs, argp,
3555 sizeof(struct kvm_debugregs)))
3556 break;
3557
3558 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3559 break;
3560 }
2d5b5a66 3561 case KVM_GET_XSAVE: {
d1ac91d8 3562 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3563 r = -ENOMEM;
d1ac91d8 3564 if (!u.xsave)
2d5b5a66
SY		 3565 break;
3566
d1ac91d8 3567 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3568
3569 r = -EFAULT;
d1ac91d8 3570 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3571 break;
3572 r = 0;
3573 break;
3574 }
3575 case KVM_SET_XSAVE: {
ff5c2c03 3576 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3577 if (IS_ERR(u.xsave))
3578 return PTR_ERR(u.xsave);
2d5b5a66 3579
d1ac91d8 3580 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3581 break;
3582 }
3583 case KVM_GET_XCRS: {
d1ac91d8 3584 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3585 r = -ENOMEM;
d1ac91d8 3586 if (!u.xcrs)
2d5b5a66
SY		 3587 break;
3588
d1ac91d8 3589 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3590
3591 r = -EFAULT;
d1ac91d8 3592 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3593 sizeof(struct kvm_xcrs)))
3594 break;
3595 r = 0;
3596 break;
3597 }
3598 case KVM_SET_XCRS: {
ff5c2c03 3599 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3600 if (IS_ERR(u.xcrs))
3601 return PTR_ERR(u.xcrs);
2d5b5a66 3602
d1ac91d8 3603 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3604 break;
3605 }
92a1f12d
JR		 3606 case KVM_SET_TSC_KHZ: {
3607 u32 user_tsc_khz;
3608
3609 r = -EINVAL;
92a1f12d
JR		 3610 user_tsc_khz = (u32)arg;
3611
3612 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3613 goto out;
3614
cc578287
ZA		 3615 if (user_tsc_khz == 0)
3616 user_tsc_khz = tsc_khz;
3617
381d585c
HZ		 3618 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3619 r = 0;
92a1f12d 3620
92a1f12d
JR		 3621 goto out;
3622 }
3623 case KVM_GET_TSC_KHZ: {
cc578287 3624 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3625 goto out;
3626 }
1c0b28c2
EM		 3627 case KVM_KVMCLOCK_CTRL: {
3628 r = kvm_set_guest_paused(vcpu);
3629 goto out;
3630 }
5c919412
AS		 3631 case KVM_ENABLE_CAP: {
3632 struct kvm_enable_cap cap;
3633
3634 r = -EFAULT;
3635 if (copy_from_user(&cap, argp, sizeof(cap)))
3636 goto out;
3637 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3638 break;
3639 }
313a3dc7
CO		 3640 default:
3641 r = -EINVAL;
3642 }
3643out:
d1ac91d8 3644 kfree(u.buffer);
313a3dc7
CO		 3645 return r;
3646}
3647
5b1c1493
CO		 3648int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3649{
3650 return VM_FAULT_SIGBUS;
3651}
3652
1fe779f8
CO		 3653static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3654{
3655 int ret;
3656
3657 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3658 return -EINVAL;
1fe779f8
CO		 3659 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3660 return ret;
3661}
3662
b927a3ce
SY		 3663static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3664 u64 ident_addr)
3665{
3666 kvm->arch.ept_identity_map_addr = ident_addr;
3667 return 0;
3668}
3669
1fe779f8
CO		 3670static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3671 u32 kvm_nr_mmu_pages)
3672{
3673 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3674 return -EINVAL;
3675
79fac95e 3676 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3677
3678 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3679 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3680
79fac95e 3681 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3682 return 0;
3683}
3684
3685static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3686{
39de71ec 3687 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3688}
3689
1fe779f8
CO		 3690static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3691{
90bca052 3692 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3693 int r;
3694
3695 r = 0;
3696 switch (chip->chip_id) {
3697 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3698 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3699 sizeof(struct kvm_pic_state));
3700 break;
3701 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3702 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3703 sizeof(struct kvm_pic_state));
3704 break;
3705 case KVM_IRQCHIP_IOAPIC:
33392b49 3706 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3707 break;
3708 default:
3709 r = -EINVAL;
3710 break;
3711 }
3712 return r;
3713}
3714
3715static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3716{
90bca052 3717 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3718 int r;
3719
3720 r = 0;
3721 switch (chip->chip_id) {
3722 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3723 spin_lock(&pic->lock);
3724 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3725 sizeof(struct kvm_pic_state));
90bca052 3726 spin_unlock(&pic->lock);
1fe779f8
CO		 3727 break;
3728 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3729 spin_lock(&pic->lock);
3730 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3731 sizeof(struct kvm_pic_state));
90bca052 3732 spin_unlock(&pic->lock);
1fe779f8
CO		 3733 break;
3734 case KVM_IRQCHIP_IOAPIC:
33392b49 3735 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3736 break;
3737 default:
3738 r = -EINVAL;
3739 break;
3740 }
90bca052 3741 kvm_pic_update_irq(pic);
1fe779f8
CO		 3742 return r;
3743}
3744
e0f63cb9
SY		 3745static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3746{
34f3941c
RK		 3747 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3748
3749 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3750
3751 mutex_lock(&kps->lock);
3752 memcpy(ps, &kps->channels, sizeof(*ps));
3753 mutex_unlock(&kps->lock);
2da29bcc 3754 return 0;
e0f63cb9
SY		 3755}
3756
3757static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3758{
0185604c 3759 int i;
09edea72
RK		 3760 struct kvm_pit *pit = kvm->arch.vpit;
3761
3762 mutex_lock(&pit->pit_state.lock);
34f3941c 3763 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3764 for (i = 0; i < 3; i++)
09edea72
RK		 3765 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3766 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3767 return 0;
e9f42757
BK		 3768}
3769
3770static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3771{
e9f42757
BK		 3772 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3773 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3774 sizeof(ps->channels));
3775 ps->flags = kvm->arch.vpit->pit_state.flags;
3776 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3777 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3778 return 0;
e9f42757
BK		 3779}
3780
3781static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3782{
2da29bcc 3783 int start = 0;
0185604c 3784 int i;
e9f42757 3785 u32 prev_legacy, cur_legacy;
09edea72
RK		 3786 struct kvm_pit *pit = kvm->arch.vpit;
3787
3788 mutex_lock(&pit->pit_state.lock);
3789 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3790 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3791 if (!prev_legacy && cur_legacy)
3792 start = 1;
09edea72
RK		 3793 memcpy(&pit->pit_state.channels, &ps->channels,
3794 sizeof(pit->pit_state.channels));
3795 pit->pit_state.flags = ps->flags;
0185604c 3796 for (i = 0; i < 3; i++)
09edea72 3797 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3798 start && i == 0);
09edea72 3799 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3800 return 0;
e0f63cb9
SY		 3801}
3802
52d939a0
MT		 3803static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3804 struct kvm_reinject_control *control)
3805{
71474e2f
RK		 3806 struct kvm_pit *pit = kvm->arch.vpit;
3807
3808 if (!pit)
52d939a0 3809 return -ENXIO;
b39c90b6 3810
71474e2f
RK		 3811 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3812 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3813 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3814 */
3815 mutex_lock(&pit->pit_state.lock);
3816 kvm_pit_set_reinject(pit, control->pit_reinject);
3817 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3818
52d939a0
MT		 3819 return 0;
3820}
3821
95d4c16c 3822/**
60c34612
TY		 3823 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3824 * @kvm: kvm instance
3825 * @log: slot id and address to which we copy the log
95d4c16c 3826 *
e108ff2f
PB		 3827 * Steps 1-4 below provide general overview of dirty page logging. See
3828 * kvm_get_dirty_log_protect() function description for additional details.
3829 *
3830 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3831 * always flush the TLB (step 4) even if previous step failed and the dirty
3832 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3833 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3834 * writes will be marked dirty for next log read.
95d4c16c 3835 *
60c34612
TY		 3836 * 1. Take a snapshot of the bit and clear it if needed.
3837 * 2. Write protect the corresponding page.
e108ff2f
PB		 3838 * 3. Copy the snapshot to the userspace.
3839 * 4. Flush TLB's if needed.
5bb064dc 3840 */
60c34612 3841int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3842{
60c34612 3843 bool is_dirty = false;
e108ff2f 3844 int r;
5bb064dc 3845
79fac95e 3846 mutex_lock(&kvm->slots_lock);
5bb064dc 3847
88178fd4
KH		 3848 /*
3849 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3850 */
3851 if (kvm_x86_ops->flush_log_dirty)
3852 kvm_x86_ops->flush_log_dirty(kvm);
3853
e108ff2f 3854 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3855
3856 /*
3857 * All the TLBs can be flushed out of mmu lock, see the comments in
3858 * kvm_mmu_slot_remove_write_access().
3859 */
e108ff2f 3860 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3861 if (is_dirty)
3862 kvm_flush_remote_tlbs(kvm);
3863
79fac95e 3864 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3865 return r;
3866}
3867
aa2fbe6d
YZ		 3868int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3869 bool line_status)
23d43cf9
CD		 3870{
3871 if (!irqchip_in_kernel(kvm))
3872 return -ENXIO;
3873
3874 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3875 irq_event->irq, irq_event->level,
3876 line_status);
23d43cf9
CD		 3877 return 0;
3878}
3879
90de4a18
NA		 3880static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3881 struct kvm_enable_cap *cap)
3882{
3883 int r;
3884
3885 if (cap->flags)
3886 return -EINVAL;
3887
3888 switch (cap->cap) {
3889 case KVM_CAP_DISABLE_QUIRKS:
3890 kvm->arch.disabled_quirks = cap->args[0];
3891 r = 0;
3892 break;
49df6397
SR		 3893 case KVM_CAP_SPLIT_IRQCHIP: {
3894 mutex_lock(&kvm->lock);
b053b2ae
SR		 3895 r = -EINVAL;
3896 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3897 goto split_irqchip_unlock;
49df6397
SR		 3898 r = -EEXIST;
3899 if (irqchip_in_kernel(kvm))
3900 goto split_irqchip_unlock;
557abc40 3901 if (kvm->created_vcpus)
49df6397 3902 goto split_irqchip_unlock;
637e3f86 3903 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
49df6397 3904 r = kvm_setup_empty_irq_routing(kvm);
637e3f86
DH		 3905 if (r) {
3906 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
3907 /* Pairs with smp_rmb() when reading irqchip_mode */
3908 smp_wmb();
49df6397 3909 goto split_irqchip_unlock;
637e3f86 3910 }
49df6397
SR		 3911 /* Pairs with irqchip_in_kernel. */
3912 smp_wmb();
49776faf 3913 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3914 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3915 r = 0;
3916split_irqchip_unlock:
3917 mutex_unlock(&kvm->lock);
3918 break;
3919 }
37131313
RK		 3920 case KVM_CAP_X2APIC_API:
3921 r = -EINVAL;
3922 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3923 break;
3924
3925 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3926 kvm->arch.x2apic_format = true;
c519265f
RK		 3927 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3928 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3929
3930 r = 0;
3931 break;
90de4a18
NA		 3932 default:
3933 r = -EINVAL;
3934 break;
3935 }
3936 return r;
3937}
3938
1fe779f8
CO		 3939long kvm_arch_vm_ioctl(struct file *filp,
3940 unsigned int ioctl, unsigned long arg)
3941{
3942 struct kvm *kvm = filp->private_data;
3943 void __user *argp = (void __user *)arg;
367e1319 3944 int r = -ENOTTY;
f0d66275
DH		 3945 /*
3946 * This union makes it completely explicit to gcc-3.x
3947 * that these two variables' stack usage should be
3948 * combined, not added together.
3949 */
3950 union {
3951 struct kvm_pit_state ps;
e9f42757 3952 struct kvm_pit_state2 ps2;
c5ff41ce 3953 struct kvm_pit_config pit_config;
f0d66275 3954 } u;
1fe779f8
CO		 3955
3956 switch (ioctl) {
3957 case KVM_SET_TSS_ADDR:
3958 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3959 break;
b927a3ce
SY		 3960 case KVM_SET_IDENTITY_MAP_ADDR: {
3961 u64 ident_addr;
3962
3963 r = -EFAULT;
3964 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3965 goto out;
3966 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3967 break;
3968 }
1fe779f8
CO		 3969 case KVM_SET_NR_MMU_PAGES:
3970 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3971 break;
3972 case KVM_GET_NR_MMU_PAGES:
3973 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3974 break;
3ddea128 3975 case KVM_CREATE_IRQCHIP: {
3ddea128 3976 mutex_lock(&kvm->lock);
09941366 3977
3ddea128 3978 r = -EEXIST;
35e6eaa3 3979 if (irqchip_in_kernel(kvm))
3ddea128 3980 goto create_irqchip_unlock;
09941366 3981
3e515705 3982 r = -EINVAL;
557abc40 3983 if (kvm->created_vcpus)
3e515705 3984 goto create_irqchip_unlock;
09941366
RK		 3985
3986 r = kvm_pic_init(kvm);
3987 if (r)
3ddea128 3988 goto create_irqchip_unlock;
09941366
RK		 3989
3990 r = kvm_ioapic_init(kvm);
3991 if (r) {
09941366 3992 kvm_pic_destroy(kvm);
3ddea128 3993 goto create_irqchip_unlock;
09941366
RK		 3994 }
3995
637e3f86 3996 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
399ec807
AK		 3997 r = kvm_setup_default_irq_routing(kvm);
3998 if (r) {
637e3f86
DH		 3999 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
4000 /* Pairs with smp_rmb() when reading irqchip_mode */
4001 smp_wmb();
72bb2fcd 4002 kvm_ioapic_destroy(kvm);
09941366 4003 kvm_pic_destroy(kvm);
71ba994c 4004 goto create_irqchip_unlock;
399ec807 4005 }
49776faf 4006 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4007 smp_wmb();
49776faf 4008 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4009 create_irqchip_unlock:
4010 mutex_unlock(&kvm->lock);
1fe779f8 4011 break;
3ddea128 4012 }
7837699f 4013 case KVM_CREATE_PIT:
c5ff41ce
JK		 4014 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4015 goto create_pit;
4016 case KVM_CREATE_PIT2:
4017 r = -EFAULT;
4018 if (copy_from_user(&u.pit_config, argp,
4019 sizeof(struct kvm_pit_config)))
4020 goto out;
4021 create_pit:
250715a6 4022 mutex_lock(&kvm->lock);
269e05e4
AK		 4023 r = -EEXIST;
4024 if (kvm->arch.vpit)
4025 goto create_pit_unlock;
7837699f 4026 r = -ENOMEM;
c5ff41ce 4027 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4028 if (kvm->arch.vpit)
4029 r = 0;
269e05e4 4030 create_pit_unlock:
250715a6 4031 mutex_unlock(&kvm->lock);
7837699f 4032 break;
1fe779f8
CO		 4033 case KVM_GET_IRQCHIP: {
4034 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4035 struct kvm_irqchip *chip;
1fe779f8 4036
ff5c2c03
SL		 4037 chip = memdup_user(argp, sizeof(*chip));
4038 if (IS_ERR(chip)) {
4039 r = PTR_ERR(chip);
1fe779f8 4040 goto out;
ff5c2c03
SL		 4041 }
4042
1fe779f8 4043 r = -ENXIO;
826da321 4044 if (!irqchip_kernel(kvm))
f0d66275
DH		 4045 goto get_irqchip_out;
4046 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4047 if (r)
f0d66275 4048 goto get_irqchip_out;
1fe779f8 4049 r = -EFAULT;
f0d66275
DH		 4050 if (copy_to_user(argp, chip, sizeof *chip))
4051 goto get_irqchip_out;
1fe779f8 4052 r = 0;
f0d66275
DH		 4053 get_irqchip_out:
4054 kfree(chip);
1fe779f8
CO		 4055 break;
4056 }
4057 case KVM_SET_IRQCHIP: {
4058 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4059 struct kvm_irqchip *chip;
1fe779f8 4060
ff5c2c03
SL		 4061 chip = memdup_user(argp, sizeof(*chip));
4062 if (IS_ERR(chip)) {
4063 r = PTR_ERR(chip);
1fe779f8 4064 goto out;
ff5c2c03
SL		 4065 }
4066
1fe779f8 4067 r = -ENXIO;
826da321 4068 if (!irqchip_kernel(kvm))
f0d66275
DH		 4069 goto set_irqchip_out;
4070 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4071 if (r)
f0d66275 4072 goto set_irqchip_out;
1fe779f8 4073 r = 0;
f0d66275
DH		 4074 set_irqchip_out:
4075 kfree(chip);
1fe779f8
CO		 4076 break;
4077 }
e0f63cb9 4078 case KVM_GET_PIT: {
e0f63cb9 4079 r = -EFAULT;
f0d66275 4080 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4081 goto out;
4082 r = -ENXIO;
4083 if (!kvm->arch.vpit)
4084 goto out;
f0d66275 4085 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4086 if (r)
4087 goto out;
4088 r = -EFAULT;
f0d66275 4089 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4090 goto out;
4091 r = 0;
4092 break;
4093 }
4094 case KVM_SET_PIT: {
e0f63cb9 4095 r = -EFAULT;
f0d66275 4096 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4097 goto out;
4098 r = -ENXIO;
4099 if (!kvm->arch.vpit)
4100 goto out;
f0d66275 4101 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4102 break;
4103 }
e9f42757
BK		 4104 case KVM_GET_PIT2: {
4105 r = -ENXIO;
4106 if (!kvm->arch.vpit)
4107 goto out;
4108 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4109 if (r)
4110 goto out;
4111 r = -EFAULT;
4112 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4113 goto out;
4114 r = 0;
4115 break;
4116 }
4117 case KVM_SET_PIT2: {
4118 r = -EFAULT;
4119 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4120 goto out;
4121 r = -ENXIO;
4122 if (!kvm->arch.vpit)
4123 goto out;
4124 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4125 break;
4126 }
52d939a0
MT		 4127 case KVM_REINJECT_CONTROL: {
4128 struct kvm_reinject_control control;
4129 r = -EFAULT;
4130 if (copy_from_user(&control, argp, sizeof(control)))
4131 goto out;
4132 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4133 break;
4134 }
d71ba788
PB		 4135 case KVM_SET_BOOT_CPU_ID:
4136 r = 0;
4137 mutex_lock(&kvm->lock);
557abc40 4138 if (kvm->created_vcpus)
d71ba788
PB		 4139 r = -EBUSY;
4140 else
4141 kvm->arch.bsp_vcpu_id = arg;
4142 mutex_unlock(&kvm->lock);
4143 break;
ffde22ac
ES		 4144 case KVM_XEN_HVM_CONFIG: {
4145 r = -EFAULT;
4146 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4147 sizeof(struct kvm_xen_hvm_config)))
4148 goto out;
4149 r = -EINVAL;
4150 if (kvm->arch.xen_hvm_config.flags)
4151 goto out;
4152 r = 0;
4153 break;
4154 }
afbcf7ab 4155 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4156 struct kvm_clock_data user_ns;
4157 u64 now_ns;
afbcf7ab
GC		 4158
4159 r = -EFAULT;
4160 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4161 goto out;
4162
4163 r = -EINVAL;
4164 if (user_ns.flags)
4165 goto out;
4166
4167 r = 0;
395c6b0a 4168 local_irq_disable();
108b249c
PB		 4169 now_ns = __get_kvmclock_ns(kvm);
4170 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
395c6b0a 4171 local_irq_enable();
2e762ff7 4172 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4173 break;
4174 }
4175 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4176 struct kvm_clock_data user_ns;
4177 u64 now_ns;
4178
e3fd9a93
PB		 4179 local_irq_disable();
4180 now_ns = __get_kvmclock_ns(kvm);
108b249c 4181 user_ns.clock = now_ns;
e3fd9a93
PB		 4182 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4183 local_irq_enable();
97e69aa6 4184 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4185
4186 r = -EFAULT;
4187 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4188 goto out;
4189 r = 0;
4190 break;
4191 }
90de4a18
NA		 4192 case KVM_ENABLE_CAP: {
4193 struct kvm_enable_cap cap;
afbcf7ab 4194
90de4a18
NA		 4195 r = -EFAULT;
4196 if (copy_from_user(&cap, argp, sizeof(cap)))
4197 goto out;
4198 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4199 break;
4200 }
1fe779f8 4201 default:
ad6260da 4202 r = -ENOTTY;
1fe779f8
CO		 4203 }
4204out:
4205 return r;
4206}
4207
a16b043c 4208static void kvm_init_msr_list(void)
043405e1
CO		 4209{
4210 u32 dummy[2];
4211 unsigned i, j;
4212
62ef68bb 4213 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4214 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4215 continue;
93c4adc7
PB		 4216
4217 /*
4218 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4219 * to the guests in some cases.
93c4adc7
PB		 4220 */
4221 switch (msrs_to_save[i]) {
4222 case MSR_IA32_BNDCFGS:
4223 if (!kvm_x86_ops->mpx_supported())
4224 continue;
4225 break;
9dbe6cf9
PB		 4226 case MSR_TSC_AUX:
4227 if (!kvm_x86_ops->rdtscp_supported())
4228 continue;
4229 break;
93c4adc7
PB		 4230 default:
4231 break;
4232 }
4233
043405e1
CO		 4234 if (j < i)
4235 msrs_to_save[j] = msrs_to_save[i];
4236 j++;
4237 }
4238 num_msrs_to_save = j;
62ef68bb
PB		 4239
4240 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4241 switch (emulated_msrs[i]) {
6d396b55
PB		 4242 case MSR_IA32_SMBASE:
4243 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4244 continue;
4245 break;
62ef68bb
PB		 4246 default:
4247 break;
4248 }
4249
4250 if (j < i)
4251 emulated_msrs[j] = emulated_msrs[i];
4252 j++;
4253 }
4254 num_emulated_msrs = j;
043405e1
CO		 4255}
4256
bda9020e
MT		 4257static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4258 const void *v)
bbd9b64e 4259{
70252a10
AK		 4260 int handled = 0;
4261 int n;
4262
4263 do {
4264 n = min(len, 8);
bce87cce 4265 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4266 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4267 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4268 break;
4269 handled += n;
4270 addr += n;
4271 len -= n;
4272 v += n;
4273 } while (len);
bbd9b64e 4274
70252a10 4275 return handled;
bbd9b64e
CO		 4276}
4277
bda9020e 4278static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4279{
70252a10
AK		 4280 int handled = 0;
4281 int n;
4282
4283 do {
4284 n = min(len, 8);
bce87cce 4285 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4286 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4287 addr, n, v))
4288 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4289 break;
4290 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4291 handled += n;
4292 addr += n;
4293 len -= n;
4294 v += n;
4295 } while (len);
bbd9b64e 4296
70252a10 4297 return handled;
bbd9b64e
CO		 4298}
4299
2dafc6c2
GN		 4300static void kvm_set_segment(struct kvm_vcpu *vcpu,
4301 struct kvm_segment *var, int seg)
4302{
4303 kvm_x86_ops->set_segment(vcpu, var, seg);
4304}
4305
4306void kvm_get_segment(struct kvm_vcpu *vcpu,
4307 struct kvm_segment *var, int seg)
4308{
4309 kvm_x86_ops->get_segment(vcpu, var, seg);
4310}
4311
54987b7a
PB		 4312gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4313 struct x86_exception *exception)
02f59dc9
JR		 4314{
4315 gpa_t t_gpa;
02f59dc9
JR		 4316
4317 BUG_ON(!mmu_is_nested(vcpu));
4318
4319 /* NPT walks are always user-walks */
4320 access |= PFERR_USER_MASK;
54987b7a 4321 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4322
4323 return t_gpa;
4324}
4325
ab9ae313
AK		 4326gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4327 struct x86_exception *exception)
1871c602
GN		 4328{
4329 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4330 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4331}
4332
ab9ae313
AK		 4333 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4334 struct x86_exception *exception)
1871c602
GN		 4335{
4336 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4337 access |= PFERR_FETCH_MASK;
ab9ae313 4338 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4339}
4340
ab9ae313
AK		 4341gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4342 struct x86_exception *exception)
1871c602
GN		 4343{
4344 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4345 access |= PFERR_WRITE_MASK;
ab9ae313 4346 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4347}
4348
4349/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4350gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4351 struct x86_exception *exception)
1871c602 4352{
ab9ae313 4353 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4354}
4355
4356static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4357 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4358 struct x86_exception *exception)
bbd9b64e
CO		 4359{
4360 void *data = val;
10589a46 4361 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4362
4363 while (bytes) {
14dfe855 4364 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4365 exception);
bbd9b64e 4366 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4367 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4368 int ret;
4369
bcc55cba 4370 if (gpa == UNMAPPED_GVA)
ab9ae313 4371 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4372 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4373 offset, toread);
10589a46 4374 if (ret < 0) {
c3cd7ffa 4375 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4376 goto out;
4377 }
bbd9b64e 4378
77c2002e
IE		 4379 bytes -= toread;
4380 data += toread;
4381 addr += toread;
bbd9b64e 4382 }
10589a46 4383out:
10589a46 4384 return r;
bbd9b64e 4385}
77c2002e 4386
1871c602 4387/* used for instruction fetching */
0f65dd70
AK		 4388static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4389 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4390 struct x86_exception *exception)
1871c602 4391{
0f65dd70 4392 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4393 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4394 unsigned offset;
4395 int ret;
0f65dd70 4396
44583cba
PB		 4397 /* Inline kvm_read_guest_virt_helper for speed. */
4398 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4399 exception);
4400 if (unlikely(gpa == UNMAPPED_GVA))
4401 return X86EMUL_PROPAGATE_FAULT;
4402
4403 offset = addr & (PAGE_SIZE-1);
4404 if (WARN_ON(offset + bytes > PAGE_SIZE))
4405 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4406 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4407 offset, bytes);
44583cba
PB		 4408 if (unlikely(ret < 0))
4409 return X86EMUL_IO_NEEDED;
4410
4411 return X86EMUL_CONTINUE;
1871c602
GN		 4412}
4413
064aea77 4414int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4415 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4416 struct x86_exception *exception)
1871c602 4417{
0f65dd70 4418 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4419 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4420
1871c602 4421 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4422 exception);
1871c602 4423}
064aea77 4424EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4425
0f65dd70
AK		 4426static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4427 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4428 struct x86_exception *exception)
1871c602 4429{
0f65dd70 4430 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4431 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4432}
4433
7a036a6f
RK		 4434static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4435 unsigned long addr, void *val, unsigned int bytes)
4436{
4437 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4438 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4439
4440 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4441}
4442
6a4d7550 4443int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4444 gva_t addr, void *val,
2dafc6c2 4445 unsigned int bytes,
bcc55cba 4446 struct x86_exception *exception)
77c2002e 4447{
0f65dd70 4448 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4449 void *data = val;
4450 int r = X86EMUL_CONTINUE;
4451
4452 while (bytes) {
14dfe855
JR		 4453 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4454 PFERR_WRITE_MASK,
ab9ae313 4455 exception);
77c2002e
IE		 4456 unsigned offset = addr & (PAGE_SIZE-1);
4457 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4458 int ret;
4459
bcc55cba 4460 if (gpa == UNMAPPED_GVA)
ab9ae313 4461 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4462 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4463 if (ret < 0) {
c3cd7ffa 4464 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4465 goto out;
4466 }
4467
4468 bytes -= towrite;
4469 data += towrite;
4470 addr += towrite;
4471 }
4472out:
4473 return r;
4474}
6a4d7550 4475EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4476
0f89b207
TL		 4477static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4478 gpa_t gpa, bool write)
4479{
4480 /* For APIC access vmexit */
4481 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4482 return 1;
4483
4484 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4485 trace_vcpu_match_mmio(gva, gpa, write, true);
4486 return 1;
4487 }
4488
4489 return 0;
4490}
4491
af7cc7d1
XG		 4492static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4493 gpa_t *gpa, struct x86_exception *exception,
4494 bool write)
4495{
97d64b78
AK		 4496 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4497 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4498
be94f6b7
HH		 4499 /*
4500 * currently PKRU is only applied to ept enabled guest so
4501 * there is no pkey in EPT page table for L1 guest or EPT
4502 * shadow page table for L2 guest.
4503 */
97d64b78 4504 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4505 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4506 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4507 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4508 (gva & (PAGE_SIZE - 1));
4f022648 4509 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4510 return 1;
4511 }
4512
af7cc7d1
XG		 4513 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4514
4515 if (*gpa == UNMAPPED_GVA)
4516 return -1;
4517
0f89b207 4518 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4519}
4520
3200f405 4521int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4522 const void *val, int bytes)
bbd9b64e
CO		 4523{
4524 int ret;
4525
54bf36aa 4526 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4527 if (ret < 0)
bbd9b64e 4528 return 0;
0eb05bf2 4529 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4530 return 1;
4531}
4532
77d197b2
XG		 4533struct read_write_emulator_ops {
4534 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4535 int bytes);
4536 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4537 void *val, int bytes);
4538 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4539 int bytes, void *val);
4540 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4541 void *val, int bytes);
4542 bool write;
4543};
4544
4545static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4546{
4547 if (vcpu->mmio_read_completed) {
77d197b2 4548 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4549 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4550 vcpu->mmio_read_completed = 0;
4551 return 1;
4552 }
4553
4554 return 0;
4555}
4556
4557static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4558 void *val, int bytes)
4559{
54bf36aa 4560 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4561}
4562
4563static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4564 void *val, int bytes)
4565{
4566 return emulator_write_phys(vcpu, gpa, val, bytes);
4567}
4568
4569static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4570{
4571 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4572 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4573}
4574
4575static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4576 void *val, int bytes)
4577{
4578 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4579 return X86EMUL_IO_NEEDED;
4580}
4581
4582static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4583 void *val, int bytes)
4584{
f78146b0
AK		 4585 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4586
87da7e66 4587 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4588 return X86EMUL_CONTINUE;
4589}
4590
0fbe9b0b 4591static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4592 .read_write_prepare = read_prepare,
4593 .read_write_emulate = read_emulate,
4594 .read_write_mmio = vcpu_mmio_read,
4595 .read_write_exit_mmio = read_exit_mmio,
4596};
4597
0fbe9b0b 4598static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4599 .read_write_emulate = write_emulate,
4600 .read_write_mmio = write_mmio,
4601 .read_write_exit_mmio = write_exit_mmio,
4602 .write = true,
4603};
4604
22388a3c
XG		 4605static int emulator_read_write_onepage(unsigned long addr, void *val,
4606 unsigned int bytes,
4607 struct x86_exception *exception,
4608 struct kvm_vcpu *vcpu,
0fbe9b0b 4609 const struct read_write_emulator_ops *ops)
bbd9b64e 4610{
af7cc7d1
XG		 4611 gpa_t gpa;
4612 int handled, ret;
22388a3c 4613 bool write = ops->write;
f78146b0 4614 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4615 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4616
4617 /*
4618 * If the exit was due to a NPF we may already have a GPA.
4619 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4620 * Note, this cannot be used on string operations since string
4621 * operation using rep will only have the initial GPA from the NPF
4622 * occurred.
4623 */
4624 if (vcpu->arch.gpa_available &&
4625 emulator_can_use_gpa(ctxt) &&
4626 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4627 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4628 gpa = exception->address;
4629 goto mmio;
4630 }
10589a46 4631
22388a3c 4632 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4633
af7cc7d1 4634 if (ret < 0)
bbd9b64e 4635 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4636
4637 /* For APIC access vmexit */
af7cc7d1 4638 if (ret)
bbd9b64e
CO		 4639 goto mmio;
4640
22388a3c 4641 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4642 return X86EMUL_CONTINUE;
4643
4644mmio:
4645 /*
4646 * Is this MMIO handled locally?
4647 */
22388a3c 4648 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4649 if (handled == bytes)
bbd9b64e 4650 return X86EMUL_CONTINUE;
bbd9b64e 4651
70252a10
AK		 4652 gpa += handled;
4653 bytes -= handled;
4654 val += handled;
4655
87da7e66
XG		 4656 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4657 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4658 frag->gpa = gpa;
4659 frag->data = val;
4660 frag->len = bytes;
f78146b0 4661 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4662}
4663
52eb5a6d
XL		 4664static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4665 unsigned long addr,
22388a3c
XG		 4666 void *val, unsigned int bytes,
4667 struct x86_exception *exception,
0fbe9b0b 4668 const struct read_write_emulator_ops *ops)
bbd9b64e 4669{
0f65dd70 4670 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4671 gpa_t gpa;
4672 int rc;
4673
4674 if (ops->read_write_prepare &&
4675 ops->read_write_prepare(vcpu, val, bytes))
4676 return X86EMUL_CONTINUE;
4677
4678 vcpu->mmio_nr_fragments = 0;
0f65dd70 4679
bbd9b64e
CO		 4680 /* Crossing a page boundary? */
4681 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4682 int now;
bbd9b64e
CO		 4683
4684 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4685 rc = emulator_read_write_onepage(addr, val, now, exception,
4686 vcpu, ops);
4687
bbd9b64e
CO		 4688 if (rc != X86EMUL_CONTINUE)
4689 return rc;
4690 addr += now;
bac15531
NA		 4691 if (ctxt->mode != X86EMUL_MODE_PROT64)
4692 addr = (u32)addr;
bbd9b64e
CO		 4693 val += now;
4694 bytes -= now;
4695 }
22388a3c 4696
f78146b0
AK		 4697 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4698 vcpu, ops);
4699 if (rc != X86EMUL_CONTINUE)
4700 return rc;
4701
4702 if (!vcpu->mmio_nr_fragments)
4703 return rc;
4704
4705 gpa = vcpu->mmio_fragments[0].gpa;
4706
4707 vcpu->mmio_needed = 1;
4708 vcpu->mmio_cur_fragment = 0;
4709
87da7e66 4710 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4711 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4712 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4713 vcpu->run->mmio.phys_addr = gpa;
4714
4715 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4716}
4717
4718static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4719 unsigned long addr,
4720 void *val,
4721 unsigned int bytes,
4722 struct x86_exception *exception)
4723{
4724 return emulator_read_write(ctxt, addr, val, bytes,
4725 exception, &read_emultor);
4726}
4727
52eb5a6d 4728static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4729 unsigned long addr,
4730 const void *val,
4731 unsigned int bytes,
4732 struct x86_exception *exception)
4733{
4734 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4735 exception, &write_emultor);
bbd9b64e 4736}
bbd9b64e 4737
daea3e73
AK		 4738#define CMPXCHG_TYPE(t, ptr, old, new) \
4739 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4740
4741#ifdef CONFIG_X86_64
4742# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4743#else
4744# define CMPXCHG64(ptr, old, new) \
9749a6c0 4745 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4746#endif
4747
0f65dd70
AK		 4748static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4749 unsigned long addr,
bbd9b64e
CO		 4750 const void *old,
4751 const void *new,
4752 unsigned int bytes,
0f65dd70 4753 struct x86_exception *exception)
bbd9b64e 4754{
0f65dd70 4755 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4756 gpa_t gpa;
4757 struct page *page;
4758 char *kaddr;
4759 bool exchanged;
2bacc55c 4760
daea3e73
AK		 4761 /* guests cmpxchg8b have to be emulated atomically */
4762 if (bytes > 8 || (bytes & (bytes - 1)))
4763 goto emul_write;
10589a46 4764
daea3e73 4765 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4766
daea3e73
AK		 4767 if (gpa == UNMAPPED_GVA ||
4768 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4769 goto emul_write;
2bacc55c 4770
daea3e73
AK		 4771 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4772 goto emul_write;
72dc67a6 4773
54bf36aa 4774 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4775 if (is_error_page(page))
c19b8bd6 4776 goto emul_write;
72dc67a6 4777
8fd75e12 4778 kaddr = kmap_atomic(page);
daea3e73
AK		 4779 kaddr += offset_in_page(gpa);
4780 switch (bytes) {
4781 case 1:
4782 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4783 break;
4784 case 2:
4785 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4786 break;
4787 case 4:
4788 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4789 break;
4790 case 8:
4791 exchanged = CMPXCHG64(kaddr, old, new);
4792 break;
4793 default:
4794 BUG();
2bacc55c 4795 }
8fd75e12 4796 kunmap_atomic(kaddr);
daea3e73
AK		 4797 kvm_release_page_dirty(page);
4798
4799 if (!exchanged)
4800 return X86EMUL_CMPXCHG_FAILED;
4801
54bf36aa 4802 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4803 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4804
4805 return X86EMUL_CONTINUE;
4a5f48f6 4806
3200f405 4807emul_write:
daea3e73 4808 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4809
0f65dd70 4810 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4811}
4812
cf8f70bf
GN		 4813static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4814{
4815 /* TODO: String I/O for in kernel device */
4816 int r;
4817
4818 if (vcpu->arch.pio.in)
e32edf4f 4819 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4820 vcpu->arch.pio.size, pd);
4821 else
e32edf4f 4822 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4823 vcpu->arch.pio.port, vcpu->arch.pio.size,
4824 pd);
4825 return r;
4826}
4827
6f6fbe98
XG		 4828static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4829 unsigned short port, void *val,
4830 unsigned int count, bool in)
cf8f70bf 4831{
cf8f70bf 4832 vcpu->arch.pio.port = port;
6f6fbe98 4833 vcpu->arch.pio.in = in;
7972995b 4834 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4835 vcpu->arch.pio.size = size;
4836
4837 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4838 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4839 return 1;
4840 }
4841
4842 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4843 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4844 vcpu->run->io.size = size;
4845 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4846 vcpu->run->io.count = count;
4847 vcpu->run->io.port = port;
4848
4849 return 0;
4850}
4851
6f6fbe98
XG		 4852static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4853 int size, unsigned short port, void *val,
4854 unsigned int count)
cf8f70bf 4855{
ca1d4a9e 4856 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4857 int ret;
ca1d4a9e 4858
6f6fbe98
XG		 4859 if (vcpu->arch.pio.count)
4860 goto data_avail;
cf8f70bf 4861
6f6fbe98
XG		 4862 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4863 if (ret) {
4864data_avail:
4865 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4866 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4867 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4868 return 1;
4869 }
4870
cf8f70bf
GN		 4871 return 0;
4872}
4873
6f6fbe98
XG		 4874static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4875 int size, unsigned short port,
4876 const void *val, unsigned int count)
4877{
4878 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4879
4880 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4881 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4882 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4883}
4884
bbd9b64e
CO		 4885static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4886{
4887 return kvm_x86_ops->get_segment_base(vcpu, seg);
4888}
4889
3cb16fe7 4890static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4891{
3cb16fe7 4892 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4893}
4894
ae6a2375 4895static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4896{
4897 if (!need_emulate_wbinvd(vcpu))
4898 return X86EMUL_CONTINUE;
4899
4900 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4901 int cpu = get_cpu();
4902
4903 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4904 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4905 wbinvd_ipi, NULL, 1);
2eec7343 4906 put_cpu();
f5f48ee1 4907 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4908 } else
4909 wbinvd();
f5f48ee1
SY		 4910 return X86EMUL_CONTINUE;
4911}
5cb56059
JS		 4912
4913int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4914{
6affcbed
KH		 4915 kvm_emulate_wbinvd_noskip(vcpu);
4916 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4917}
f5f48ee1
SY		 4918EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4919
5cb56059
JS		 4920
4921
bcaf5cc5
AK		 4922static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4923{
5cb56059 4924 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4925}
4926
52eb5a6d
XL		 4927static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4928 unsigned long *dest)
bbd9b64e 4929{
16f8a6f9 4930 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4931}
4932
52eb5a6d
XL		 4933static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4934 unsigned long value)
bbd9b64e 4935{
338dbc97 4936
717746e3 4937 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4938}
4939
52a46617 4940static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4941{
52a46617 4942 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4943}
4944
717746e3 4945static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4946{
717746e3 4947 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4948 unsigned long value;
4949
4950 switch (cr) {
4951 case 0:
4952 value = kvm_read_cr0(vcpu);
4953 break;
4954 case 2:
4955 value = vcpu->arch.cr2;
4956 break;
4957 case 3:
9f8fe504 4958 value = kvm_read_cr3(vcpu);
52a46617
GN		 4959 break;
4960 case 4:
4961 value = kvm_read_cr4(vcpu);
4962 break;
4963 case 8:
4964 value = kvm_get_cr8(vcpu);
4965 break;
4966 default:
a737f256 4967 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4968 return 0;
4969 }
4970
4971 return value;
4972}
4973
717746e3 4974static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4975{
717746e3 4976 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4977 int res = 0;
4978
52a46617
GN		 4979 switch (cr) {
4980 case 0:
49a9b07e 4981 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4982 break;
4983 case 2:
4984 vcpu->arch.cr2 = val;
4985 break;
4986 case 3:
2390218b 4987 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4988 break;
4989 case 4:
a83b29c6 4990 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4991 break;
4992 case 8:
eea1cff9 4993 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4994 break;
4995 default:
a737f256 4996 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4997 res = -1;
52a46617 4998 }
0f12244f
GN		 4999
5000 return res;
52a46617
GN		 5001}
5002
717746e3 5003static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5004{
717746e3 5005 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5006}
5007
4bff1e86 5008static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5009{
4bff1e86 5010 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5011}
5012
4bff1e86 5013static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5014{
4bff1e86 5015 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5016}
5017
1ac9d0cf
AK		 5018static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5019{
5020 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5021}
5022
5023static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5024{
5025 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5026}
5027
4bff1e86
AK		 5028static unsigned long emulator_get_cached_segment_base(
5029 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5030{
4bff1e86 5031 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5032}
5033
1aa36616
AK		 5034static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5035 struct desc_struct *desc, u32 *base3,
5036 int seg)
2dafc6c2
GN		 5037{
5038 struct kvm_segment var;
5039
4bff1e86 5040 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5041 *selector = var.selector;
2dafc6c2 5042
378a8b09
GN		 5043 if (var.unusable) {
5044 memset(desc, 0, sizeof(*desc));
2dafc6c2 5045 return false;
378a8b09 5046 }
2dafc6c2
GN		 5047
5048 if (var.g)
5049 var.limit >>= 12;
5050 set_desc_limit(desc, var.limit);
5051 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5052#ifdef CONFIG_X86_64
5053 if (base3)
5054 *base3 = var.base >> 32;
5055#endif
2dafc6c2
GN		 5056 desc->type = var.type;
5057 desc->s = var.s;
5058 desc->dpl = var.dpl;
5059 desc->p = var.present;
5060 desc->avl = var.avl;
5061 desc->l = var.l;
5062 desc->d = var.db;
5063 desc->g = var.g;
5064
5065 return true;
5066}
5067
1aa36616
AK		 5068static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5069 struct desc_struct *desc, u32 base3,
5070 int seg)
2dafc6c2 5071{
4bff1e86 5072 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5073 struct kvm_segment var;
5074
1aa36616 5075 var.selector = selector;
2dafc6c2 5076 var.base = get_desc_base(desc);
5601d05b
GN		 5077#ifdef CONFIG_X86_64
5078 var.base |= ((u64)base3) << 32;
5079#endif
2dafc6c2
GN		 5080 var.limit = get_desc_limit(desc);
5081 if (desc->g)
5082 var.limit = (var.limit << 12) | 0xfff;
5083 var.type = desc->type;
2dafc6c2
GN		 5084 var.dpl = desc->dpl;
5085 var.db = desc->d;
5086 var.s = desc->s;
5087 var.l = desc->l;
5088 var.g = desc->g;
5089 var.avl = desc->avl;
5090 var.present = desc->p;
5091 var.unusable = !var.present;
5092 var.padding = 0;
5093
5094 kvm_set_segment(vcpu, &var, seg);
5095 return;
5096}
5097
717746e3
AK		 5098static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5099 u32 msr_index, u64 *pdata)
5100{
609e36d3
PB		 5101 struct msr_data msr;
5102 int r;
5103
5104 msr.index = msr_index;
5105 msr.host_initiated = false;
5106 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5107 if (r)
5108 return r;
5109
5110 *pdata = msr.data;
5111 return 0;
717746e3
AK		 5112}
5113
5114static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5115 u32 msr_index, u64 data)
5116{
8fe8ab46
WA		 5117 struct msr_data msr;
5118
5119 msr.data = data;
5120 msr.index = msr_index;
5121 msr.host_initiated = false;
5122 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5123}
5124
64d60670
PB		 5125static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5126{
5127 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5128
5129 return vcpu->arch.smbase;
5130}
5131
5132static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5133{
5134 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5135
5136 vcpu->arch.smbase = smbase;
5137}
5138
67f4d428
NA		 5139static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5140 u32 pmc)
5141{
c6702c9d 5142 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5143}
5144
222d21aa
AK		 5145static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5146 u32 pmc, u64 *pdata)
5147{
c6702c9d 5148 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5149}
5150
6c3287f7
AK		 5151static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5152{
5153 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5154}
5155
5037f6f3
AK		 5156static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5157{
5158 preempt_disable();
5197b808 5159 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5160}
5161
5162static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5163{
5164 preempt_enable();
5165}
5166
2953538e 5167static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5168 struct x86_instruction_info *info,
c4f035c6
AK		 5169 enum x86_intercept_stage stage)
5170{
2953538e 5171 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5172}
5173
0017f93a 5174static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5175 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5176{
0017f93a 5177 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5178}
5179
dd856efa
AK		 5180static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5181{
5182 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5183}
5184
5185static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5186{
5187 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5188}
5189
801806d9
NA		 5190static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5191{
5192 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5193}
5194
0225fb50 5195static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5196 .read_gpr = emulator_read_gpr,
5197 .write_gpr = emulator_write_gpr,
1871c602 5198 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5199 .write_std = kvm_write_guest_virt_system,
7a036a6f 5200 .read_phys = kvm_read_guest_phys_system,
1871c602 5201 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5202 .read_emulated = emulator_read_emulated,
5203 .write_emulated = emulator_write_emulated,
5204 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5205 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5206 .pio_in_emulated = emulator_pio_in_emulated,
5207 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5208 .get_segment = emulator_get_segment,
5209 .set_segment = emulator_set_segment,
5951c442 5210 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5211 .get_gdt = emulator_get_gdt,
160ce1f1 5212 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5213 .set_gdt = emulator_set_gdt,
5214 .set_idt = emulator_set_idt,
52a46617
GN		 5215 .get_cr = emulator_get_cr,
5216 .set_cr = emulator_set_cr,
9c537244 5217 .cpl = emulator_get_cpl,
35aa5375
GN		 5218 .get_dr = emulator_get_dr,
5219 .set_dr = emulator_set_dr,
64d60670
PB		 5220 .get_smbase = emulator_get_smbase,
5221 .set_smbase = emulator_set_smbase,
717746e3
AK		 5222 .set_msr = emulator_set_msr,
5223 .get_msr = emulator_get_msr,
67f4d428 5224 .check_pmc = emulator_check_pmc,
222d21aa 5225 .read_pmc = emulator_read_pmc,
6c3287f7 5226 .halt = emulator_halt,
bcaf5cc5 5227 .wbinvd = emulator_wbinvd,
d6aa1000 5228 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5229 .get_fpu = emulator_get_fpu,
5230 .put_fpu = emulator_put_fpu,
c4f035c6 5231 .intercept = emulator_intercept,
bdb42f5a 5232 .get_cpuid = emulator_get_cpuid,
801806d9 5233 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5234};
5235
95cb2295
GN		 5236static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5237{
37ccdcbe 5238 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5239 /*
5240 * an sti; sti; sequence only disable interrupts for the first
5241 * instruction. So, if the last instruction, be it emulated or
5242 * not, left the system with the INT_STI flag enabled, it
5243 * means that the last instruction is an sti. We should not
5244 * leave the flag on in this case. The same goes for mov ss
5245 */
37ccdcbe
PB		 5246 if (int_shadow & mask)
5247 mask = 0;
6addfc42 5248 if (unlikely(int_shadow || mask)) {
95cb2295 5249 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5250 if (!mask)
5251 kvm_make_request(KVM_REQ_EVENT, vcpu);
5252 }
95cb2295
GN		 5253}
5254
ef54bcfe 5255static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5256{
5257 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5258 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5259 return kvm_propagate_fault(vcpu, &ctxt->exception);
5260
5261 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5262 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5263 ctxt->exception.error_code);
54b8486f 5264 else
da9cb575 5265 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5266 return false;
54b8486f
GN		 5267}
5268
8ec4722d
MG		 5269static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5270{
adf52235 5271 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5272 int cs_db, cs_l;
5273
8ec4722d
MG		 5274 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5275
adf52235
TY		 5276 ctxt->eflags = kvm_get_rflags(vcpu);
5277 ctxt->eip = kvm_rip_read(vcpu);
5278 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5279 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5280 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5281 cs_db ? X86EMUL_MODE_PROT32 :
5282 X86EMUL_MODE_PROT16;
a584539b 5283 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5284 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5285 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5286 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5287
dd856efa 5288 init_decode_cache(ctxt);
7ae441ea 5289 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5290}
5291
71f9833b 5292int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5293{
9d74191a 5294 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5295 int ret;
5296
5297 init_emulate_ctxt(vcpu);
5298
9dac77fa
AK		 5299 ctxt->op_bytes = 2;
5300 ctxt->ad_bytes = 2;
5301 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5302 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5303
5304 if (ret != X86EMUL_CONTINUE)
5305 return EMULATE_FAIL;
5306
9dac77fa 5307 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5308 kvm_rip_write(vcpu, ctxt->eip);
5309 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5310
5311 if (irq == NMI_VECTOR)
7460fb4a 5312 vcpu->arch.nmi_pending = 0;
63995653
MG		 5313 else
5314 vcpu->arch.interrupt.pending = false;
5315
5316 return EMULATE_DONE;
5317}
5318EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5319
6d77dbfc
GN		 5320static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5321{
fc3a9157
JR		 5322 int r = EMULATE_DONE;
5323
6d77dbfc
GN		 5324 ++vcpu->stat.insn_emulation_fail;
5325 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5326 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5327 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5328 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5329 vcpu->run->internal.ndata = 0;
5330 r = EMULATE_FAIL;
5331 }
6d77dbfc 5332 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5333
5334 return r;
6d77dbfc
GN		 5335}
5336
93c05d3e 5337static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5338 bool write_fault_to_shadow_pgtable,
5339 int emulation_type)
a6f177ef 5340{
95b3cf69 5341 gpa_t gpa = cr2;
ba049e93 5342 kvm_pfn_t pfn;
a6f177ef 5343
991eebf9
GN		 5344 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5345 return false;
5346
95b3cf69
XG		 5347 if (!vcpu->arch.mmu.direct_map) {
5348 /*
5349 * Write permission should be allowed since only
5350 * write access need to be emulated.
5351 */
5352 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5353
95b3cf69
XG		 5354 /*
5355 * If the mapping is invalid in guest, let cpu retry
5356 * it to generate fault.
5357 */
5358 if (gpa == UNMAPPED_GVA)
5359 return true;
5360 }
a6f177ef 5361
8e3d9d06
XG		 5362 /*
5363 * Do not retry the unhandleable instruction if it faults on the
5364 * readonly host memory, otherwise it will goto a infinite loop:
5365 * retry instruction -> write #PF -> emulation fail -> retry
5366 * instruction -> ...
5367 */
5368 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5369
5370 /*
5371 * If the instruction failed on the error pfn, it can not be fixed,
5372 * report the error to userspace.
5373 */
5374 if (is_error_noslot_pfn(pfn))
5375 return false;
5376
5377 kvm_release_pfn_clean(pfn);
5378
5379 /* The instructions are well-emulated on direct mmu. */
5380 if (vcpu->arch.mmu.direct_map) {
5381 unsigned int indirect_shadow_pages;
5382
5383 spin_lock(&vcpu->kvm->mmu_lock);
5384 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5385 spin_unlock(&vcpu->kvm->mmu_lock);
5386
5387 if (indirect_shadow_pages)
5388 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5389
a6f177ef 5390 return true;
8e3d9d06 5391 }
a6f177ef 5392
95b3cf69
XG		 5393 /*
5394 * if emulation was due to access to shadowed page table
5395 * and it failed try to unshadow page and re-enter the
5396 * guest to let CPU execute the instruction.
5397 */
5398 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5399
5400 /*
5401 * If the access faults on its page table, it can not
5402 * be fixed by unprotecting shadow page and it should
5403 * be reported to userspace.
5404 */
5405 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5406}
5407
1cb3f3ae
XG		 5408static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5409 unsigned long cr2, int emulation_type)
5410{
5411 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5412 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5413
5414 last_retry_eip = vcpu->arch.last_retry_eip;
5415 last_retry_addr = vcpu->arch.last_retry_addr;
5416
5417 /*
5418 * If the emulation is caused by #PF and it is non-page_table
5419 * writing instruction, it means the VM-EXIT is caused by shadow
5420 * page protected, we can zap the shadow page and retry this
5421 * instruction directly.
5422 *
5423 * Note: if the guest uses a non-page-table modifying instruction
5424 * on the PDE that points to the instruction, then we will unmap
5425 * the instruction and go to an infinite loop. So, we cache the
5426 * last retried eip and the last fault address, if we meet the eip
5427 * and the address again, we can break out of the potential infinite
5428 * loop.
5429 */
5430 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5431
5432 if (!(emulation_type & EMULTYPE_RETRY))
5433 return false;
5434
5435 if (x86_page_table_writing_insn(ctxt))
5436 return false;
5437
5438 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5439 return false;
5440
5441 vcpu->arch.last_retry_eip = ctxt->eip;
5442 vcpu->arch.last_retry_addr = cr2;
5443
5444 if (!vcpu->arch.mmu.direct_map)
5445 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5446
22368028 5447 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5448
5449 return true;
5450}
5451
716d51ab
GN		 5452static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5453static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5454
64d60670 5455static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5456{
64d60670 5457 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5458 /* This is a good place to trace that we are exiting SMM. */
5459 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5460
c43203ca
PB		 5461 /* Process a latched INIT or SMI, if any. */
5462 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5463 }
699023e2
PB		 5464
5465 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5466}
5467
5468static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5469{
5470 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5471
a584539b 5472 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5473
5474 if (changed & HF_SMM_MASK)
5475 kvm_smm_changed(vcpu);
a584539b
PB		 5476}
5477
4a1e10d5
PB		 5478static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5479 unsigned long *db)
5480{
5481 u32 dr6 = 0;
5482 int i;
5483 u32 enable, rwlen;
5484
5485 enable = dr7;
5486 rwlen = dr7 >> 16;
5487 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5488 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5489 dr6 |= (1 << i);
5490 return dr6;
5491}
5492
6addfc42 5493static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5494{
5495 struct kvm_run *kvm_run = vcpu->run;
5496
5497 /*
6addfc42
PB		 5498 * rflags is the old, "raw" value of the flags. The new value has
5499 * not been saved yet.
663f4c61
PB		 5500 *
5501 * This is correct even for TF set by the guest, because "the
5502 * processor will not generate this exception after the instruction
5503 * that sets the TF flag".
5504 */
663f4c61
PB		 5505 if (unlikely(rflags & X86_EFLAGS_TF)) {
5506 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5507 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5508 DR6_RTM;
663f4c61
PB		 5509 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5510 kvm_run->debug.arch.exception = DB_VECTOR;
5511 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5512 *r = EMULATE_USER_EXIT;
5513 } else {
663f4c61
PB		 5514 /*
5515 * "Certain debug exceptions may clear bit 0-3. The
5516 * remaining contents of the DR6 register are never
5517 * cleared by the processor".
5518 */
5519 vcpu->arch.dr6 &= ~15;
6f43ed01 5520 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5521 kvm_queue_exception(vcpu, DB_VECTOR);
5522 }
5523 }
5524}
5525
6affcbed
KH		 5526int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5527{
5528 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5529 int r = EMULATE_DONE;
5530
5531 kvm_x86_ops->skip_emulated_instruction(vcpu);
5532 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5533 return r == EMULATE_DONE;
5534}
5535EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5536
4a1e10d5
PB		 5537static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5538{
4a1e10d5
PB		 5539 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5540 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5541 struct kvm_run *kvm_run = vcpu->run;
5542 unsigned long eip = kvm_get_linear_rip(vcpu);
5543 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5544 vcpu->arch.guest_debug_dr7,
5545 vcpu->arch.eff_db);
5546
5547 if (dr6 != 0) {
6f43ed01 5548 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5549 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5550 kvm_run->debug.arch.exception = DB_VECTOR;
5551 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5552 *r = EMULATE_USER_EXIT;
5553 return true;
5554 }
5555 }
5556
4161a569
NA		 5557 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5558 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5559 unsigned long eip = kvm_get_linear_rip(vcpu);
5560 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5561 vcpu->arch.dr7,
5562 vcpu->arch.db);
5563
5564 if (dr6 != 0) {
5565 vcpu->arch.dr6 &= ~15;
6f43ed01 5566 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5567 kvm_queue_exception(vcpu, DB_VECTOR);
5568 *r = EMULATE_DONE;
5569 return true;
5570 }
5571 }
5572
5573 return false;
5574}
5575
51d8b661
AP		 5576int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5577 unsigned long cr2,
dc25e89e
AP		 5578 int emulation_type,
5579 void *insn,
5580 int insn_len)
bbd9b64e 5581{
95cb2295 5582 int r;
9d74191a 5583 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5584 bool writeback = true;
93c05d3e 5585 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5586
93c05d3e
XG		 5587 /*
5588 * Clear write_fault_to_shadow_pgtable here to ensure it is
5589 * never reused.
5590 */
5591 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5592 kvm_clear_exception_queue(vcpu);
8d7d8102 5593
571008da 5594 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5595 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5596
5597 /*
5598 * We will reenter on the same instruction since
5599 * we do not set complete_userspace_io. This does not
5600 * handle watchpoints yet, those would be handled in
5601 * the emulate_ops.
5602 */
5603 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5604 return r;
5605
9d74191a
TY		 5606 ctxt->interruptibility = 0;
5607 ctxt->have_exception = false;
e0ad0b47 5608 ctxt->exception.vector = -1;
9d74191a 5609 ctxt->perm_ok = false;
bbd9b64e 5610
b51e974f 5611 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5612
9d74191a 5613 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5614
e46479f8 5615 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5616 ++vcpu->stat.insn_emulation;
1d2887e2 5617 if (r != EMULATION_OK) {
4005996e
AK		 5618 if (emulation_type & EMULTYPE_TRAP_UD)
5619 return EMULATE_FAIL;
991eebf9
GN		 5620 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5621 emulation_type))
bbd9b64e 5622 return EMULATE_DONE;
6d77dbfc
GN		 5623 if (emulation_type & EMULTYPE_SKIP)
5624 return EMULATE_FAIL;
5625 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5626 }
5627 }
5628
ba8afb6b 5629 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5630 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5631 if (ctxt->eflags & X86_EFLAGS_RF)
5632 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5633 return EMULATE_DONE;
5634 }
5635
1cb3f3ae
XG		 5636 if (retry_instruction(ctxt, cr2, emulation_type))
5637 return EMULATE_DONE;
5638
7ae441ea 5639 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5640 changes registers values during IO operation */
7ae441ea
GN		 5641 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5642 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5643 emulator_invalidate_register_cache(ctxt);
7ae441ea 5644 }
4d2179e1 5645
5cd21917 5646restart:
0f89b207
TL		 5647 /* Save the faulting GPA (cr2) in the address field */
5648 ctxt->exception.address = cr2;
5649
9d74191a 5650 r = x86_emulate_insn(ctxt);
bbd9b64e 5651
775fde86
JR		 5652 if (r == EMULATION_INTERCEPTED)
5653 return EMULATE_DONE;
5654
d2ddd1c4 5655 if (r == EMULATION_FAILED) {
991eebf9
GN		 5656 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5657 emulation_type))
c3cd7ffa
GN		 5658 return EMULATE_DONE;
5659
6d77dbfc 5660 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5661 }
5662
9d74191a 5663 if (ctxt->have_exception) {
d2ddd1c4 5664 r = EMULATE_DONE;
ef54bcfe
PB		 5665 if (inject_emulated_exception(vcpu))
5666 return r;
d2ddd1c4 5667 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5668 if (!vcpu->arch.pio.in) {
5669 /* FIXME: return into emulator if single-stepping. */
3457e419 5670 vcpu->arch.pio.count = 0;
0912c977 5671 } else {
7ae441ea 5672 writeback = false;
716d51ab
GN		 5673 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5674 }
ac0a48c3 5675 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5676 } else if (vcpu->mmio_needed) {
5677 if (!vcpu->mmio_is_write)
5678 writeback = false;
ac0a48c3 5679 r = EMULATE_USER_EXIT;
716d51ab 5680 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5681 } else if (r == EMULATION_RESTART)
5cd21917 5682 goto restart;
d2ddd1c4
GN		 5683 else
5684 r = EMULATE_DONE;
f850e2e6 5685
7ae441ea 5686 if (writeback) {
6addfc42 5687 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5688 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5689 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5690 if (vcpu->arch.hflags != ctxt->emul_flags)
5691 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5692 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5693 if (r == EMULATE_DONE)
6addfc42 5694 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5695 if (!ctxt->have_exception ||
5696 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5697 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5698
5699 /*
5700 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5701 * do nothing, and it will be requested again as soon as
5702 * the shadow expires. But we still need to check here,
5703 * because POPF has no interrupt shadow.
5704 */
5705 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5706 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5707 } else
5708 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5709
5710 return r;
de7d789a 5711}
51d8b661 5712EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5713
cf8f70bf 5714int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5715{
cf8f70bf 5716 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5717 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5718 size, port, &val, 1);
cf8f70bf 5719 /* do not return to emulator after return from userspace */
7972995b 5720 vcpu->arch.pio.count = 0;
de7d789a
CO		 5721 return ret;
5722}
cf8f70bf 5723EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5724
8370c3d0
TL		 5725static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5726{
5727 unsigned long val;
5728
5729 /* We should only ever be called with arch.pio.count equal to 1 */
5730 BUG_ON(vcpu->arch.pio.count != 1);
5731
5732 /* For size less than 4 we merge, else we zero extend */
5733 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5734 : 0;
5735
5736 /*
5737 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5738 * the copy and tracing
5739 */
5740 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5741 vcpu->arch.pio.port, &val, 1);
5742 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5743
5744 return 1;
5745}
5746
5747int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5748{
5749 unsigned long val;
5750 int ret;
5751
5752 /* For size less than 4 we merge, else we zero extend */
5753 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5754
5755 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5756 &val, 1);
5757 if (ret) {
5758 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5759 return ret;
5760 }
5761
5762 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5763
5764 return 0;
5765}
5766EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5767
251a5fd6 5768static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5769{
0a3aee0d 5770 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5771 return 0;
8cfdc000
ZA		 5772}
5773
5774static void tsc_khz_changed(void *data)
c8076604 5775{
8cfdc000
ZA		 5776 struct cpufreq_freqs *freq = data;
5777 unsigned long khz = 0;
5778
5779 if (data)
5780 khz = freq->new;
5781 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5782 khz = cpufreq_quick_get(raw_smp_processor_id());
5783 if (!khz)
5784 khz = tsc_khz;
0a3aee0d 5785 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5786}
5787
c8076604
GH		 5788static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5789 void *data)
5790{
5791 struct cpufreq_freqs *freq = data;
5792 struct kvm *kvm;
5793 struct kvm_vcpu *vcpu;
5794 int i, send_ipi = 0;
5795
8cfdc000
ZA		 5796 /*
5797 * We allow guests to temporarily run on slowing clocks,
5798 * provided we notify them after, or to run on accelerating
5799 * clocks, provided we notify them before. Thus time never
5800 * goes backwards.
5801 *
5802 * However, we have a problem. We can't atomically update
5803 * the frequency of a given CPU from this function; it is
5804 * merely a notifier, which can be called from any CPU.
5805 * Changing the TSC frequency at arbitrary points in time
5806 * requires a recomputation of local variables related to
5807 * the TSC for each VCPU. We must flag these local variables
5808 * to be updated and be sure the update takes place with the
5809 * new frequency before any guests proceed.
5810 *
5811 * Unfortunately, the combination of hotplug CPU and frequency
5812 * change creates an intractable locking scenario; the order
5813 * of when these callouts happen is undefined with respect to
5814 * CPU hotplug, and they can race with each other. As such,
5815 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5816 * undefined; you can actually have a CPU frequency change take
5817 * place in between the computation of X and the setting of the
5818 * variable. To protect against this problem, all updates of
5819 * the per_cpu tsc_khz variable are done in an interrupt
5820 * protected IPI, and all callers wishing to update the value
5821 * must wait for a synchronous IPI to complete (which is trivial
5822 * if the caller is on the CPU already). This establishes the
5823 * necessary total order on variable updates.
5824 *
5825 * Note that because a guest time update may take place
5826 * anytime after the setting of the VCPU's request bit, the
5827 * correct TSC value must be set before the request. However,
5828 * to ensure the update actually makes it to any guest which
5829 * starts running in hardware virtualization between the set
5830 * and the acquisition of the spinlock, we must also ping the
5831 * CPU after setting the request bit.
5832 *
5833 */
5834
c8076604
GH		 5835 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5836 return 0;
5837 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5838 return 0;
8cfdc000
ZA		 5839
5840 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5841
2f303b74 5842 spin_lock(&kvm_lock);
c8076604 5843 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5844 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5845 if (vcpu->cpu != freq->cpu)
5846 continue;
c285545f 5847 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5848 if (vcpu->cpu != smp_processor_id())
8cfdc000 5849 send_ipi = 1;
c8076604
GH		 5850 }
5851 }
2f303b74 5852 spin_unlock(&kvm_lock);
c8076604
GH		 5853
5854 if (freq->old < freq->new && send_ipi) {
5855 /*
5856 * We upscale the frequency. Must make the guest
5857 * doesn't see old kvmclock values while running with
5858 * the new frequency, otherwise we risk the guest sees
5859 * time go backwards.
5860 *
5861 * In case we update the frequency for another cpu
5862 * (which might be in guest context) send an interrupt
5863 * to kick the cpu out of guest context. Next time
5864 * guest context is entered kvmclock will be updated,
5865 * so the guest will not see stale values.
5866 */
8cfdc000 5867 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5868 }
5869 return 0;
5870}
5871
5872static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5873 .notifier_call = kvmclock_cpufreq_notifier
5874};
5875
251a5fd6 5876static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5877{
251a5fd6
SAS		 5878 tsc_khz_changed(NULL);
5879 return 0;
8cfdc000
ZA		 5880}
5881
b820cc0c
ZA		 5882static void kvm_timer_init(void)
5883{
c285545f 5884 max_tsc_khz = tsc_khz;
460dd42e 5885
b820cc0c 5886 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5887#ifdef CONFIG_CPU_FREQ
5888 struct cpufreq_policy policy;
758f588d
BP		 5889 int cpu;
5890
c285545f 5891 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5892 cpu = get_cpu();
5893 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5894 if (policy.cpuinfo.max_freq)
5895 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5896 put_cpu();
c285545f 5897#endif
b820cc0c
ZA		 5898 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5899 CPUFREQ_TRANSITION_NOTIFIER);
5900 }
c285545f 5901 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5902
73c1b41e 5903 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5904 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5905}
5906
ff9d07a0
ZY		 5907static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5908
f5132b01 5909int kvm_is_in_guest(void)
ff9d07a0 5910{
086c9855 5911 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5912}
5913
5914static int kvm_is_user_mode(void)
5915{
5916 int user_mode = 3;
dcf46b94 5917
086c9855
AS		 5918 if (__this_cpu_read(current_vcpu))
5919 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5920
ff9d07a0
ZY		 5921 return user_mode != 0;
5922}
5923
5924static unsigned long kvm_get_guest_ip(void)
5925{
5926 unsigned long ip = 0;
dcf46b94 5927
086c9855
AS		 5928 if (__this_cpu_read(current_vcpu))
5929 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5930
ff9d07a0
ZY		 5931 return ip;
5932}
5933
5934static struct perf_guest_info_callbacks kvm_guest_cbs = {
5935 .is_in_guest = kvm_is_in_guest,
5936 .is_user_mode = kvm_is_user_mode,
5937 .get_guest_ip = kvm_get_guest_ip,
5938};
5939
5940void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5941{
086c9855 5942 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5943}
5944EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5945
5946void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5947{
086c9855 5948 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5949}
5950EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5951
ce88decf
XG		 5952static void kvm_set_mmio_spte_mask(void)
5953{
5954 u64 mask;
5955 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5956
5957 /*
5958 * Set the reserved bits and the present bit of an paging-structure
5959 * entry to generate page fault with PFER.RSV = 1.
5960 */
885032b9 5961 /* Mask the reserved physical address bits. */
d1431483 5962 mask = rsvd_bits(maxphyaddr, 51);
885032b9 5963
885032b9 5964 /* Set the present bit. */
ce88decf
XG		 5965 mask |= 1ull;
5966
5967#ifdef CONFIG_X86_64
5968 /*
5969 * If reserved bit is not supported, clear the present bit to disable
5970 * mmio page fault.
5971 */
5972 if (maxphyaddr == 52)
5973 mask &= ~1ull;
5974#endif
5975
5976 kvm_mmu_set_mmio_spte_mask(mask);
5977}
5978
16e8d74d
MT		 5979#ifdef CONFIG_X86_64
5980static void pvclock_gtod_update_fn(struct work_struct *work)
5981{
d828199e
MT		 5982 struct kvm *kvm;
5983
5984 struct kvm_vcpu *vcpu;
5985 int i;
5986
2f303b74 5987 spin_lock(&kvm_lock);
d828199e
MT		 5988 list_for_each_entry(kvm, &vm_list, vm_list)
5989 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5990 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5991 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5992 spin_unlock(&kvm_lock);
16e8d74d
MT		 5993}
5994
5995static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5996
5997/*
5998 * Notification about pvclock gtod data update.
5999 */
6000static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6001 void *priv)
6002{
6003 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6004 struct timekeeper *tk = priv;
6005
6006 update_pvclock_gtod(tk);
6007
6008 /* disable master clock if host does not trust, or does not
6009 * use, TSC clocksource
6010 */
6011 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6012 atomic_read(&kvm_guest_has_master_clock) != 0)
6013 queue_work(system_long_wq, &pvclock_gtod_work);
6014
6015 return 0;
6016}
6017
6018static struct notifier_block pvclock_gtod_notifier = {
6019 .notifier_call = pvclock_gtod_notify,
6020};
6021#endif
6022
f8c16bba 6023int kvm_arch_init(void *opaque)
043405e1 6024{
b820cc0c 6025 int r;
6b61edf7 6026 struct kvm_x86_ops *ops = opaque;
f8c16bba 6027
f8c16bba
ZX		 6028 if (kvm_x86_ops) {
6029 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6030 r = -EEXIST;
6031 goto out;
f8c16bba
ZX		 6032 }
6033
6034 if (!ops->cpu_has_kvm_support()) {
6035 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6036 r = -EOPNOTSUPP;
6037 goto out;
f8c16bba
ZX		 6038 }
6039 if (ops->disabled_by_bios()) {
6040 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6041 r = -EOPNOTSUPP;
6042 goto out;
f8c16bba
ZX		 6043 }
6044
013f6a5d
MT		 6045 r = -ENOMEM;
6046 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6047 if (!shared_msrs) {
6048 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6049 goto out;
6050 }
6051
97db56ce
AK		 6052 r = kvm_mmu_module_init();
6053 if (r)
013f6a5d 6054 goto out_free_percpu;
97db56ce 6055
ce88decf 6056 kvm_set_mmio_spte_mask();
97db56ce 6057
f8c16bba 6058 kvm_x86_ops = ops;
920c8377 6059
7b52345e 6060 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6061 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6062 PT_PRESENT_MASK, 0);
b820cc0c 6063 kvm_timer_init();
c8076604 6064
ff9d07a0
ZY		 6065 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6066
d366bf7e 6067 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6068 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6069
c5cc421b 6070 kvm_lapic_init();
16e8d74d
MT		 6071#ifdef CONFIG_X86_64
6072 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6073#endif
6074
f8c16bba 6075 return 0;
56c6d28a 6076
013f6a5d
MT		 6077out_free_percpu:
6078 free_percpu(shared_msrs);
56c6d28a 6079out:
56c6d28a 6080 return r;
043405e1 6081}
8776e519 6082
f8c16bba
ZX		 6083void kvm_arch_exit(void)
6084{
cef84c30 6085 kvm_lapic_exit();
ff9d07a0
ZY		 6086 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6087
888d256e
JK		 6088 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6089 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6090 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6091 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6092#ifdef CONFIG_X86_64
6093 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6094#endif
f8c16bba 6095 kvm_x86_ops = NULL;
56c6d28a 6096 kvm_mmu_module_exit();
013f6a5d 6097 free_percpu(shared_msrs);
56c6d28a 6098}
f8c16bba 6099
5cb56059 6100int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6101{
6102 ++vcpu->stat.halt_exits;
35754c98 6103 if (lapic_in_kernel(vcpu)) {
a4535290 6104 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6105 return 1;
6106 } else {
6107 vcpu->run->exit_reason = KVM_EXIT_HLT;
6108 return 0;
6109 }
6110}
5cb56059
JS		 6111EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6112
6113int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6114{
6affcbed
KH		 6115 int ret = kvm_skip_emulated_instruction(vcpu);
6116 /*
6117 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6118 * KVM_EXIT_DEBUG here.
6119 */
6120 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6121}
8776e519
HB		 6122EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6123
8ef81a9a 6124#ifdef CONFIG_X86_64
55dd00a7
MT		 6125static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6126 unsigned long clock_type)
6127{
6128 struct kvm_clock_pairing clock_pairing;
6129 struct timespec ts;
80fbd89c 6130 u64 cycle;
55dd00a7
MT		 6131 int ret;
6132
6133 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6134 return -KVM_EOPNOTSUPP;
6135
6136 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6137 return -KVM_EOPNOTSUPP;
6138
6139 clock_pairing.sec = ts.tv_sec;
6140 clock_pairing.nsec = ts.tv_nsec;
6141 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6142 clock_pairing.flags = 0;
6143
6144 ret = 0;
6145 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6146 sizeof(struct kvm_clock_pairing)))
6147 ret = -KVM_EFAULT;
6148
6149 return ret;
6150}
8ef81a9a 6151#endif
55dd00a7 6152
6aef266c
SV		 6153/*
6154 * kvm_pv_kick_cpu_op: Kick a vcpu.
6155 *
6156 * @apicid - apicid of vcpu to be kicked.
6157 */
6158static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6159{
24d2166b 6160 struct kvm_lapic_irq lapic_irq;
6aef266c 6161
24d2166b
R		 6162 lapic_irq.shorthand = 0;
6163 lapic_irq.dest_mode = 0;
6164 lapic_irq.dest_id = apicid;
93bbf0b8 6165 lapic_irq.msi_redir_hint = false;
6aef266c 6166
24d2166b 6167 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6168 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6169}
6170
d62caabb
AS		 6171void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6172{
6173 vcpu->arch.apicv_active = false;
6174 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6175}
6176
8776e519
HB		 6177int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6178{
6179 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6180 int op_64_bit, r;
8776e519 6181
6affcbed 6182 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6183
55cd8e5a
GN		 6184 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6185 return kvm_hv_hypercall(vcpu);
6186
5fdbf976
MT		 6187 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6188 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6189 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6190 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6191 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6192
229456fc 6193 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6194
a449c7aa
NA		 6195 op_64_bit = is_64_bit_mode(vcpu);
6196 if (!op_64_bit) {
8776e519
HB		 6197 nr &= 0xFFFFFFFF;
6198 a0 &= 0xFFFFFFFF;
6199 a1 &= 0xFFFFFFFF;
6200 a2 &= 0xFFFFFFFF;
6201 a3 &= 0xFFFFFFFF;
6202 }
6203
07708c4a
JK		 6204 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6205 ret = -KVM_EPERM;
6206 goto out;
6207 }
6208
8776e519 6209 switch (nr) {
b93463aa
AK		 6210 case KVM_HC_VAPIC_POLL_IRQ:
6211 ret = 0;
6212 break;
6aef266c
SV		 6213 case KVM_HC_KICK_CPU:
6214 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6215 ret = 0;
6216 break;
8ef81a9a 6217#ifdef CONFIG_X86_64
55dd00a7
MT		 6218 case KVM_HC_CLOCK_PAIRING:
6219 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6220 break;
8ef81a9a 6221#endif
8776e519
HB		 6222 default:
6223 ret = -KVM_ENOSYS;
6224 break;
6225 }
07708c4a 6226out:
a449c7aa
NA		 6227 if (!op_64_bit)
6228 ret = (u32)ret;
5fdbf976 6229 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6230 ++vcpu->stat.hypercalls;
2f333bcb 6231 return r;
8776e519
HB		 6232}
6233EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6234
b6785def 6235static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6236{
d6aa1000 6237 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6238 char instruction[3];
5fdbf976 6239 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6240
8776e519 6241 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6242
ce2e852e
DV		 6243 return emulator_write_emulated(ctxt, rip, instruction, 3,
6244 &ctxt->exception);
8776e519
HB		 6245}
6246
851ba692 6247static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6248{
782d422b
MG		 6249 return vcpu->run->request_interrupt_window &&
6250 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6251}
6252
851ba692 6253static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6254{
851ba692
AK		 6255 struct kvm_run *kvm_run = vcpu->run;
6256
91586a3b 6257 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6258 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6259 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6260 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6261 kvm_run->ready_for_interrupt_injection =
6262 pic_in_kernel(vcpu->kvm) ||
782d422b 6263 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6264}
6265
95ba8273
GN		 6266static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6267{
6268 int max_irr, tpr;
6269
6270 if (!kvm_x86_ops->update_cr8_intercept)
6271 return;
6272
bce87cce 6273 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6274 return;
6275
d62caabb
AS		 6276 if (vcpu->arch.apicv_active)
6277 return;
6278
8db3baa2
GN		 6279 if (!vcpu->arch.apic->vapic_addr)
6280 max_irr = kvm_lapic_find_highest_irr(vcpu);
6281 else
6282 max_irr = -1;
95ba8273
GN		 6283
6284 if (max_irr != -1)
6285 max_irr >>= 4;
6286
6287 tpr = kvm_lapic_get_cr8(vcpu);
6288
6289 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6290}
6291
b6b8a145 6292static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6293{
b6b8a145
JK		 6294 int r;
6295
95ba8273 6296 /* try to reinject previous events if any */
b59bb7bd 6297 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6298 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6299 vcpu->arch.exception.has_error_code,
6300 vcpu->arch.exception.error_code);
d6e8c854
NA		 6301
6302 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6303 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6304 X86_EFLAGS_RF);
6305
6bdf0662
NA		 6306 if (vcpu->arch.exception.nr == DB_VECTOR &&
6307 (vcpu->arch.dr7 & DR7_GD)) {
6308 vcpu->arch.dr7 &= ~DR7_GD;
6309 kvm_update_dr7(vcpu);
6310 }
6311
b59bb7bd
GN		 6312 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6313 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6314 vcpu->arch.exception.error_code,
6315 vcpu->arch.exception.reinject);
b6b8a145 6316 return 0;
b59bb7bd
GN		 6317 }
6318
95ba8273
GN		 6319 if (vcpu->arch.nmi_injected) {
6320 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6321 return 0;
95ba8273
GN		 6322 }
6323
6324 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6325 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6326 return 0;
6327 }
6328
6329 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6330 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6331 if (r != 0)
6332 return r;
95ba8273
GN		 6333 }
6334
6335 /* try to inject new event if pending */
c43203ca
PB		 6336 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6337 vcpu->arch.smi_pending = false;
ee2cd4b7 6338 enter_smm(vcpu);
c43203ca 6339 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6340 --vcpu->arch.nmi_pending;
6341 vcpu->arch.nmi_injected = true;
6342 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6343 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6344 /*
6345 * Because interrupts can be injected asynchronously, we are
6346 * calling check_nested_events again here to avoid a race condition.
6347 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6348 * proposal and current concerns. Perhaps we should be setting
6349 * KVM_REQ_EVENT only on certain events and not unconditionally?
6350 */
6351 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6352 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6353 if (r != 0)
6354 return r;
6355 }
95ba8273 6356 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6357 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6358 false);
6359 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6360 }
6361 }
ee2cd4b7 6362
b6b8a145 6363 return 0;
95ba8273
GN		 6364}
6365
7460fb4a
AK		 6366static void process_nmi(struct kvm_vcpu *vcpu)
6367{
6368 unsigned limit = 2;
6369
6370 /*
6371 * x86 is limited to one NMI running, and one NMI pending after it.
6372 * If an NMI is already in progress, limit further NMIs to just one.
6373 * Otherwise, allow two (and we'll inject the first one immediately).
6374 */
6375 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6376 limit = 1;
6377
6378 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6379 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6380 kvm_make_request(KVM_REQ_EVENT, vcpu);
6381}
6382
660a5d51
PB		 6383#define put_smstate(type, buf, offset, val) \
6384 *(type *)((buf) + (offset) - 0x7e00) = val
6385
ee2cd4b7 6386static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6387{
6388 u32 flags = 0;
6389 flags |= seg->g << 23;
6390 flags |= seg->db << 22;
6391 flags |= seg->l << 21;
6392 flags |= seg->avl << 20;
6393 flags |= seg->present << 15;
6394 flags |= seg->dpl << 13;
6395 flags |= seg->s << 12;
6396 flags |= seg->type << 8;
6397 return flags;
6398}
6399
ee2cd4b7 6400static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6401{
6402 struct kvm_segment seg;
6403 int offset;
6404
6405 kvm_get_segment(vcpu, &seg, n);
6406 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6407
6408 if (n < 3)
6409 offset = 0x7f84 + n * 12;
6410 else
6411 offset = 0x7f2c + (n - 3) * 12;
6412
6413 put_smstate(u32, buf, offset + 8, seg.base);
6414 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6415 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6416}
6417
efbb288a 6418#ifdef CONFIG_X86_64
ee2cd4b7 6419static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6420{
6421 struct kvm_segment seg;
6422 int offset;
6423 u16 flags;
6424
6425 kvm_get_segment(vcpu, &seg, n);
6426 offset = 0x7e00 + n * 16;
6427
ee2cd4b7 6428 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6429 put_smstate(u16, buf, offset, seg.selector);
6430 put_smstate(u16, buf, offset + 2, flags);
6431 put_smstate(u32, buf, offset + 4, seg.limit);
6432 put_smstate(u64, buf, offset + 8, seg.base);
6433}
efbb288a 6434#endif
660a5d51 6435
ee2cd4b7 6436static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6437{
6438 struct desc_ptr dt;
6439 struct kvm_segment seg;
6440 unsigned long val;
6441 int i;
6442
6443 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6444 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6445 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6446 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6447
6448 for (i = 0; i < 8; i++)
6449 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6450
6451 kvm_get_dr(vcpu, 6, &val);
6452 put_smstate(u32, buf, 0x7fcc, (u32)val);
6453 kvm_get_dr(vcpu, 7, &val);
6454 put_smstate(u32, buf, 0x7fc8, (u32)val);
6455
6456 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6457 put_smstate(u32, buf, 0x7fc4, seg.selector);
6458 put_smstate(u32, buf, 0x7f64, seg.base);
6459 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6460 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6461
6462 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6463 put_smstate(u32, buf, 0x7fc0, seg.selector);
6464 put_smstate(u32, buf, 0x7f80, seg.base);
6465 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6466 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6467
6468 kvm_x86_ops->get_gdt(vcpu, &dt);
6469 put_smstate(u32, buf, 0x7f74, dt.address);
6470 put_smstate(u32, buf, 0x7f70, dt.size);
6471
6472 kvm_x86_ops->get_idt(vcpu, &dt);
6473 put_smstate(u32, buf, 0x7f58, dt.address);
6474 put_smstate(u32, buf, 0x7f54, dt.size);
6475
6476 for (i = 0; i < 6; i++)
ee2cd4b7 6477 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6478
6479 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6480
6481 /* revision id */
6482 put_smstate(u32, buf, 0x7efc, 0x00020000);
6483 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6484}
6485
ee2cd4b7 6486static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6487{
6488#ifdef CONFIG_X86_64
6489 struct desc_ptr dt;
6490 struct kvm_segment seg;
6491 unsigned long val;
6492 int i;
6493
6494 for (i = 0; i < 16; i++)
6495 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6496
6497 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6498 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6499
6500 kvm_get_dr(vcpu, 6, &val);
6501 put_smstate(u64, buf, 0x7f68, val);
6502 kvm_get_dr(vcpu, 7, &val);
6503 put_smstate(u64, buf, 0x7f60, val);
6504
6505 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6506 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6507 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6508
6509 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6510
6511 /* revision id */
6512 put_smstate(u32, buf, 0x7efc, 0x00020064);
6513
6514 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6515
6516 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6517 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6518 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6519 put_smstate(u32, buf, 0x7e94, seg.limit);
6520 put_smstate(u64, buf, 0x7e98, seg.base);
6521
6522 kvm_x86_ops->get_idt(vcpu, &dt);
6523 put_smstate(u32, buf, 0x7e84, dt.size);
6524 put_smstate(u64, buf, 0x7e88, dt.address);
6525
6526 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6527 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6528 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6529 put_smstate(u32, buf, 0x7e74, seg.limit);
6530 put_smstate(u64, buf, 0x7e78, seg.base);
6531
6532 kvm_x86_ops->get_gdt(vcpu, &dt);
6533 put_smstate(u32, buf, 0x7e64, dt.size);
6534 put_smstate(u64, buf, 0x7e68, dt.address);
6535
6536 for (i = 0; i < 6; i++)
ee2cd4b7 6537 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6538#else
6539 WARN_ON_ONCE(1);
6540#endif
6541}
6542
ee2cd4b7 6543static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6544{
660a5d51 6545 struct kvm_segment cs, ds;
18c3626e 6546 struct desc_ptr dt;
660a5d51
PB		 6547 char buf[512];
6548 u32 cr0;
6549
660a5d51
PB		 6550 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6551 vcpu->arch.hflags |= HF_SMM_MASK;
6552 memset(buf, 0, 512);
6553 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6554 enter_smm_save_state_64(vcpu, buf);
660a5d51 6555 else
ee2cd4b7 6556 enter_smm_save_state_32(vcpu, buf);
660a5d51 6557
54bf36aa 6558 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6559
6560 if (kvm_x86_ops->get_nmi_mask(vcpu))
6561 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6562 else
6563 kvm_x86_ops->set_nmi_mask(vcpu, true);
6564
6565 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6566 kvm_rip_write(vcpu, 0x8000);
6567
6568 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6569 kvm_x86_ops->set_cr0(vcpu, cr0);
6570 vcpu->arch.cr0 = cr0;
6571
6572 kvm_x86_ops->set_cr4(vcpu, 0);
6573
18c3626e
PB		 6574 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6575 dt.address = dt.size = 0;
6576 kvm_x86_ops->set_idt(vcpu, &dt);
6577
660a5d51
PB		 6578 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6579
6580 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6581 cs.base = vcpu->arch.smbase;
6582
6583 ds.selector = 0;
6584 ds.base = 0;
6585
6586 cs.limit = ds.limit = 0xffffffff;
6587 cs.type = ds.type = 0x3;
6588 cs.dpl = ds.dpl = 0;
6589 cs.db = ds.db = 0;
6590 cs.s = ds.s = 1;
6591 cs.l = ds.l = 0;
6592 cs.g = ds.g = 1;
6593 cs.avl = ds.avl = 0;
6594 cs.present = ds.present = 1;
6595 cs.unusable = ds.unusable = 0;
6596 cs.padding = ds.padding = 0;
6597
6598 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6599 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6600 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6601 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6602 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6603 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6604
6605 if (guest_cpuid_has_longmode(vcpu))
6606 kvm_x86_ops->set_efer(vcpu, 0);
6607
6608 kvm_update_cpuid(vcpu);
6609 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6610}
6611
ee2cd4b7 6612static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6613{
6614 vcpu->arch.smi_pending = true;
6615 kvm_make_request(KVM_REQ_EVENT, vcpu);
6616}
6617
2860c4b1
PB		 6618void kvm_make_scan_ioapic_request(struct kvm *kvm)
6619{
6620 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6621}
6622
3d81bc7e 6623static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6624{
5c919412
AS		 6625 u64 eoi_exit_bitmap[4];
6626
3d81bc7e
YZ		 6627 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6628 return;
c7c9c56c 6629
6308630b 6630 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6631
b053b2ae 6632 if (irqchip_split(vcpu->kvm))
6308630b 6633 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6634 else {
76dfafd5 6635 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6636 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6637 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6638 }
5c919412
AS		 6639 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6640 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6641 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6642}
6643
a70656b6
RK		 6644static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6645{
6646 ++vcpu->stat.tlb_flush;
6647 kvm_x86_ops->tlb_flush(vcpu);
6648}
6649
4256f43f
TC		 6650void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6651{
c24ae0dc
TC		 6652 struct page *page = NULL;
6653
35754c98 6654 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6655 return;
6656
4256f43f
TC		 6657 if (!kvm_x86_ops->set_apic_access_page_addr)
6658 return;
6659
c24ae0dc 6660 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6661 if (is_error_page(page))
6662 return;
c24ae0dc
TC		 6663 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6664
6665 /*
6666 * Do not pin apic access page in memory, the MMU notifier
6667 * will call us again if it is migrated or swapped out.
6668 */
6669 put_page(page);
4256f43f
TC		 6670}
6671EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6672
fe71557a
TC		 6673void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6674 unsigned long address)
6675{
c24ae0dc
TC		 6676 /*
6677 * The physical address of apic access page is stored in the VMCS.
6678 * Update it when it becomes invalid.
6679 */
6680 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6681 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6682}
6683
9357d939 6684/*
362c698f 6685 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6686 * exiting to the userspace. Otherwise, the value will be returned to the
6687 * userspace.
6688 */
851ba692 6689static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6690{
6691 int r;
62a193ed
MG		 6692 bool req_int_win =
6693 dm_request_for_irq_injection(vcpu) &&
6694 kvm_cpu_accept_dm_intr(vcpu);
6695
730dca42 6696 bool req_immediate_exit = false;
b6c7a5dc 6697
3e007509 6698 if (vcpu->requests) {
a8eeb04a 6699 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6700 kvm_mmu_unload(vcpu);
a8eeb04a 6701 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6702 __kvm_migrate_timers(vcpu);
d828199e
MT		 6703 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6704 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6705 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6706 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6707 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6708 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6709 if (unlikely(r))
6710 goto out;
6711 }
a8eeb04a 6712 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6713 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6714 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6715 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6716 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6717 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6718 r = 0;
6719 goto out;
6720 }
a8eeb04a 6721 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6722 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6723 r = 0;
6724 goto out;
6725 }
af585b92
GN		 6726 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6727 /* Page is swapped out. Do synthetic halt */
6728 vcpu->arch.apf.halted = true;
6729 r = 1;
6730 goto out;
6731 }
c9aaa895
GC		 6732 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6733 record_steal_time(vcpu);
64d60670
PB		 6734 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6735 process_smi(vcpu);
7460fb4a
AK		 6736 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6737 process_nmi(vcpu);
f5132b01 6738 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6739 kvm_pmu_handle_event(vcpu);
f5132b01 6740 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6741 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6742 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6743 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6744 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6745 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6746 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6747 vcpu->run->eoi.vector =
6748 vcpu->arch.pending_ioapic_eoi;
6749 r = 0;
6750 goto out;
6751 }
6752 }
3d81bc7e
YZ		 6753 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6754 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6755 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6756 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6757 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6758 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6759 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6760 r = 0;
6761 goto out;
6762 }
e516cebb
AS		 6763 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6764 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6765 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6766 r = 0;
6767 goto out;
6768 }
db397571
AS		 6769 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6770 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6771 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6772 r = 0;
6773 goto out;
6774 }
f3b138c5
AS		 6775
6776 /*
6777 * KVM_REQ_HV_STIMER has to be processed after
6778 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6779 * depend on the guest clock being up-to-date
6780 */
1f4b34f8
AS		 6781 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6782 kvm_hv_process_stimers(vcpu);
2f52d58c 6783 }
b93463aa 6784
b463a6f7 6785 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6786 ++vcpu->stat.req_event;
66450a21
JK		 6787 kvm_apic_accept_events(vcpu);
6788 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6789 r = 1;
6790 goto out;
6791 }
6792
b6b8a145
JK		 6793 if (inject_pending_event(vcpu, req_int_win) != 0)
6794 req_immediate_exit = true;
321c5658 6795 else {
c43203ca
PB		 6796 /* Enable NMI/IRQ window open exits if needed.
6797 *
6798 * SMIs have two cases: 1) they can be nested, and
6799 * then there is nothing to do here because RSM will
6800 * cause a vmexit anyway; 2) or the SMI can be pending
6801 * because inject_pending_event has completed the
6802 * injection of an IRQ or NMI from the previous vmexit,
6803 * and then we request an immediate exit to inject the SMI.
6804 */
6805 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6806 req_immediate_exit = true;
321c5658
YS		 6807 if (vcpu->arch.nmi_pending)
6808 kvm_x86_ops->enable_nmi_window(vcpu);
6809 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6810 kvm_x86_ops->enable_irq_window(vcpu);
6811 }
b463a6f7
AK		 6812
6813 if (kvm_lapic_enabled(vcpu)) {
6814 update_cr8_intercept(vcpu);
6815 kvm_lapic_sync_to_vapic(vcpu);
6816 }
6817 }
6818
d8368af8
AK		 6819 r = kvm_mmu_reload(vcpu);
6820 if (unlikely(r)) {
d905c069 6821 goto cancel_injection;
d8368af8
AK		 6822 }
6823
b6c7a5dc
HB		 6824 preempt_disable();
6825
6826 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6827 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6828
6829 /*
6830 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6831 * IPI are then delayed after guest entry, which ensures that they
6832 * result in virtual interrupt delivery.
6833 */
6834 local_irq_disable();
6b7e2d09
XG		 6835 vcpu->mode = IN_GUEST_MODE;
6836
01b71917
MT		 6837 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6838
0f127d12 6839 /*
b95234c8
PB		 6840 * 1) We should set ->mode before checking ->requests. Please see
6841 * the comment in kvm_make_all_cpus_request.
6842 *
6843 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6844 * pairs with the memory barrier implicit in pi_test_and_set_on
6845 * (see vmx_deliver_posted_interrupt).
6846 *
6847 * 3) This also orders the write to mode from any reads to the page
6848 * tables done while the VCPU is running. Please see the comment
6849 * in kvm_flush_remote_tlbs.
6b7e2d09 6850 */
01b71917 6851 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6852
b95234c8
PB		 6853 /*
6854 * This handles the case where a posted interrupt was
6855 * notified with kvm_vcpu_kick.
6856 */
6857 if (kvm_lapic_enabled(vcpu)) {
6858 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6859 kvm_x86_ops->sync_pir_to_irr(vcpu);
6860 }
32f88400 6861
6b7e2d09 6862 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6863 || need_resched() || signal_pending(current)) {
6b7e2d09 6864 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6865 smp_wmb();
6c142801
AK		 6866 local_irq_enable();
6867 preempt_enable();
01b71917 6868 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6869 r = 1;
d905c069 6870 goto cancel_injection;
6c142801
AK		 6871 }
6872
fc5b7f3b
DM		 6873 kvm_load_guest_xcr0(vcpu);
6874
c43203ca
PB		 6875 if (req_immediate_exit) {
6876 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6877 smp_send_reschedule(vcpu->cpu);
c43203ca 6878 }
d6185f20 6879
8b89fe1f
PB		 6880 trace_kvm_entry(vcpu->vcpu_id);
6881 wait_lapic_expire(vcpu);
6edaa530 6882 guest_enter_irqoff();
b6c7a5dc 6883
42dbaa5a 6884 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6885 set_debugreg(0, 7);
6886 set_debugreg(vcpu->arch.eff_db[0], 0);
6887 set_debugreg(vcpu->arch.eff_db[1], 1);
6888 set_debugreg(vcpu->arch.eff_db[2], 2);
6889 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6890 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6891 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6892 }
b6c7a5dc 6893
851ba692 6894 kvm_x86_ops->run(vcpu);
b6c7a5dc 6895
c77fb5fe
PB		 6896 /*
6897 * Do this here before restoring debug registers on the host. And
6898 * since we do this before handling the vmexit, a DR access vmexit
6899 * can (a) read the correct value of the debug registers, (b) set
6900 * KVM_DEBUGREG_WONT_EXIT again.
6901 */
6902 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6903 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6904 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6905 kvm_update_dr0123(vcpu);
6906 kvm_update_dr6(vcpu);
6907 kvm_update_dr7(vcpu);
6908 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6909 }
6910
24f1e32c
FW		 6911 /*
6912 * If the guest has used debug registers, at least dr7
6913 * will be disabled while returning to the host.
6914 * If we don't have active breakpoints in the host, we don't
6915 * care about the messed up debug address registers. But if
6916 * we have some of them active, restore the old state.
6917 */
59d8eb53 6918 if (hw_breakpoint_active())
24f1e32c 6919 hw_breakpoint_restore();
42dbaa5a 6920
4ba76538 6921 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6922
6b7e2d09 6923 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6924 smp_wmb();
a547c6db 6925
fc5b7f3b
DM		 6926 kvm_put_guest_xcr0(vcpu);
6927
a547c6db 6928 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6929
6930 ++vcpu->stat.exits;
6931
f2485b3e 6932 guest_exit_irqoff();
b6c7a5dc 6933
f2485b3e 6934 local_irq_enable();
b6c7a5dc
HB		 6935 preempt_enable();
6936
f656ce01 6937 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6938
b6c7a5dc
HB		 6939 /*
6940 * Profile KVM exit RIPs:
6941 */
6942 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6943 unsigned long rip = kvm_rip_read(vcpu);
6944 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6945 }
6946
cc578287
ZA		 6947 if (unlikely(vcpu->arch.tsc_always_catchup))
6948 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6949
5cfb1d5a
MT		 6950 if (vcpu->arch.apic_attention)
6951 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6952
851ba692 6953 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6954 return r;
6955
6956cancel_injection:
6957 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6958 if (unlikely(vcpu->arch.apic_attention))
6959 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6960out:
6961 return r;
6962}
b6c7a5dc 6963
362c698f
PB		 6964static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6965{
bf9f6ac8
FW		 6966 if (!kvm_arch_vcpu_runnable(vcpu) &&
6967 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6968 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6969 kvm_vcpu_block(vcpu);
6970 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6971
6972 if (kvm_x86_ops->post_block)
6973 kvm_x86_ops->post_block(vcpu);
6974
9c8fd1ba
PB		 6975 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6976 return 1;
6977 }
362c698f
PB		 6978
6979 kvm_apic_accept_events(vcpu);
6980 switch(vcpu->arch.mp_state) {
6981 case KVM_MP_STATE_HALTED:
6982 vcpu->arch.pv.pv_unhalted = false;
6983 vcpu->arch.mp_state =
6984 KVM_MP_STATE_RUNNABLE;
6985 case KVM_MP_STATE_RUNNABLE:
6986 vcpu->arch.apf.halted = false;
6987 break;
6988 case KVM_MP_STATE_INIT_RECEIVED:
6989 break;
6990 default:
6991 return -EINTR;
6992 break;
6993 }
6994 return 1;
6995}
09cec754 6996
5d9bc648
PB		 6997static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6998{
0ad3bed6
PB		 6999 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7000 kvm_x86_ops->check_nested_events(vcpu, false);
7001
5d9bc648
PB		 7002 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7003 !vcpu->arch.apf.halted);
7004}
7005
362c698f 7006static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7007{
7008 int r;
f656ce01 7009 struct kvm *kvm = vcpu->kvm;
d7690175 7010
f656ce01 7011 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7012
362c698f 7013 for (;;) {
58f800d5 7014 if (kvm_vcpu_running(vcpu)) {
851ba692 7015 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7016 } else {
362c698f 7017 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7018 }
7019
09cec754
GN		 7020 if (r <= 0)
7021 break;
7022
7023 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
7024 if (kvm_cpu_has_pending_timer(vcpu))
7025 kvm_inject_pending_timer_irqs(vcpu);
7026
782d422b
MG		 7027 if (dm_request_for_irq_injection(vcpu) &&
7028 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7029 r = 0;
7030 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7031 ++vcpu->stat.request_irq_exits;
362c698f 7032 break;
09cec754 7033 }
af585b92
GN		 7034
7035 kvm_check_async_pf_completion(vcpu);
7036
09cec754
GN		 7037 if (signal_pending(current)) {
7038 r = -EINTR;
851ba692 7039 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7040 ++vcpu->stat.signal_exits;
362c698f 7041 break;
09cec754
GN		 7042 }
7043 if (need_resched()) {
f656ce01 7044 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7045 cond_resched();
f656ce01 7046 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7047 }
b6c7a5dc
HB		 7048 }
7049
f656ce01 7050 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7051
7052 return r;
7053}
7054
716d51ab
GN		 7055static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7056{
7057 int r;
7058 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7059 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7060 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7061 if (r != EMULATE_DONE)
7062 return 0;
7063 return 1;
7064}
7065
7066static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7067{
7068 BUG_ON(!vcpu->arch.pio.count);
7069
7070 return complete_emulated_io(vcpu);
7071}
7072
f78146b0
AK		 7073/*
7074 * Implements the following, as a state machine:
7075 *
7076 * read:
7077 * for each fragment
87da7e66
XG		 7078 * for each mmio piece in the fragment
7079 * write gpa, len
7080 * exit
7081 * copy data
f78146b0
AK		 7082 * execute insn
7083 *
7084 * write:
7085 * for each fragment
87da7e66
XG		 7086 * for each mmio piece in the fragment
7087 * write gpa, len
7088 * copy data
7089 * exit
f78146b0 7090 */
716d51ab 7091static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7092{
7093 struct kvm_run *run = vcpu->run;
f78146b0 7094 struct kvm_mmio_fragment *frag;
87da7e66 7095 unsigned len;
5287f194 7096
716d51ab 7097 BUG_ON(!vcpu->mmio_needed);
5287f194 7098
716d51ab 7099 /* Complete previous fragment */
87da7e66
XG		 7100 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7101 len = min(8u, frag->len);
716d51ab 7102 if (!vcpu->mmio_is_write)
87da7e66
XG		 7103 memcpy(frag->data, run->mmio.data, len);
7104
7105 if (frag->len <= 8) {
7106 /* Switch to the next fragment. */
7107 frag++;
7108 vcpu->mmio_cur_fragment++;
7109 } else {
7110 /* Go forward to the next mmio piece. */
7111 frag->data += len;
7112 frag->gpa += len;
7113 frag->len -= len;
7114 }
7115
a08d3b3b 7116 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7117 vcpu->mmio_needed = 0;
0912c977
PB		 7118
7119 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7120 if (vcpu->mmio_is_write)
716d51ab
GN		 7121 return 1;
7122 vcpu->mmio_read_completed = 1;
7123 return complete_emulated_io(vcpu);
7124 }
87da7e66 7125
716d51ab
GN		 7126 run->exit_reason = KVM_EXIT_MMIO;
7127 run->mmio.phys_addr = frag->gpa;
7128 if (vcpu->mmio_is_write)
87da7e66
XG		 7129 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7130 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7131 run->mmio.is_write = vcpu->mmio_is_write;
7132 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7133 return 0;
5287f194
AK		 7134}
7135
716d51ab 7136
b6c7a5dc
HB		 7137int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7138{
c5bedc68 7139 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7140 int r;
7141 sigset_t sigsaved;
7142
c4d72e2d 7143 fpu__activate_curr(fpu);
e5c30142 7144
ac9f6dc0
AK		 7145 if (vcpu->sigset_active)
7146 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7147
a4535290 7148 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7149 kvm_vcpu_block(vcpu);
66450a21 7150 kvm_apic_accept_events(vcpu);
d7690175 7151 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 7152 r = -EAGAIN;
7153 goto out;
b6c7a5dc
HB		 7154 }
7155
b6c7a5dc 7156 /* re-sync apic's tpr */
35754c98 7157 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7158 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7159 r = -EINVAL;
7160 goto out;
7161 }
7162 }
b6c7a5dc 7163
716d51ab
GN		 7164 if (unlikely(vcpu->arch.complete_userspace_io)) {
7165 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7166 vcpu->arch.complete_userspace_io = NULL;
7167 r = cui(vcpu);
7168 if (r <= 0)
7169 goto out;
7170 } else
7171 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7172
460df4c1
PB		 7173 if (kvm_run->immediate_exit)
7174 r = -EINTR;
7175 else
7176 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7177
7178out:
f1d86e46 7179 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7180 if (vcpu->sigset_active)
7181 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7182
b6c7a5dc
HB		 7183 return r;
7184}
7185
7186int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7187{
7ae441ea
GN		 7188 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7189 /*
7190 * We are here if userspace calls get_regs() in the middle of
7191 * instruction emulation. Registers state needs to be copied
4a969980 7192 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7193 * that usually, but some bad designed PV devices (vmware
7194 * backdoor interface) need this to work
7195 */
dd856efa 7196 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7197 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7198 }
5fdbf976
MT		 7199 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7200 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7201 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7202 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7203 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7204 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7205 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7206 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7207#ifdef CONFIG_X86_64
5fdbf976
MT		 7208 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7209 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7210 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7211 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7212 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7213 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7214 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7215 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7216#endif
7217
5fdbf976 7218 regs->rip = kvm_rip_read(vcpu);
91586a3b 7219 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7220
b6c7a5dc
HB		 7221 return 0;
7222}
7223
7224int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7225{
7ae441ea
GN		 7226 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7227 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7228
5fdbf976
MT		 7229 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7230 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7231 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7232 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7233 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7234 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7235 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7236 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7237#ifdef CONFIG_X86_64
5fdbf976
MT		 7238 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7239 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7240 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7241 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7242 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7243 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7244 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7245 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7246#endif
7247
5fdbf976 7248 kvm_rip_write(vcpu, regs->rip);
91586a3b 7249 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7250
b4f14abd
JK		 7251 vcpu->arch.exception.pending = false;
7252
3842d135
AK		 7253 kvm_make_request(KVM_REQ_EVENT, vcpu);
7254
b6c7a5dc
HB		 7255 return 0;
7256}
7257
b6c7a5dc
HB		 7258void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7259{
7260 struct kvm_segment cs;
7261
3e6e0aab 7262 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7263 *db = cs.db;
7264 *l = cs.l;
7265}
7266EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7267
7268int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7269 struct kvm_sregs *sregs)
7270{
89a27f4d 7271 struct desc_ptr dt;
b6c7a5dc 7272
3e6e0aab
GT		 7273 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7274 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7275 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7276 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7277 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7278 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7279
3e6e0aab
GT		 7280 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7281 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7282
7283 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7284 sregs->idt.limit = dt.size;
7285 sregs->idt.base = dt.address;
b6c7a5dc 7286 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7287 sregs->gdt.limit = dt.size;
7288 sregs->gdt.base = dt.address;
b6c7a5dc 7289
4d4ec087 7290 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7291 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7292 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7293 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7294 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7295 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7296 sregs->apic_base = kvm_get_apic_base(vcpu);
7297
923c61bb 7298 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7299
36752c9b 7300 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7301 set_bit(vcpu->arch.interrupt.nr,
7302 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7303
b6c7a5dc
HB		 7304 return 0;
7305}
7306
62d9f0db
MT		 7307int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7308 struct kvm_mp_state *mp_state)
7309{
66450a21 7310 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7311 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7312 vcpu->arch.pv.pv_unhalted)
7313 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7314 else
7315 mp_state->mp_state = vcpu->arch.mp_state;
7316
62d9f0db
MT		 7317 return 0;
7318}
7319
7320int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7321 struct kvm_mp_state *mp_state)
7322{
bce87cce 7323 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7324 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7325 return -EINVAL;
7326
28bf2888
DH		 7327 /* INITs are latched while in SMM */
7328 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7329 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7330 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7331 return -EINVAL;
7332
66450a21
JK		 7333 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7334 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7335 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7336 } else
7337 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7338 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7339 return 0;
7340}
7341
7f3d35fd
KW		 7342int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7343 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7344{
9d74191a 7345 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7346 int ret;
e01c2426 7347
8ec4722d 7348 init_emulate_ctxt(vcpu);
c697518a 7349
7f3d35fd 7350 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7351 has_error_code, error_code);
c697518a 7352
c697518a 7353 if (ret)
19d04437 7354 return EMULATE_FAIL;
37817f29 7355
9d74191a
TY		 7356 kvm_rip_write(vcpu, ctxt->eip);
7357 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7358 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7359 return EMULATE_DONE;
37817f29
IE		 7360}
7361EXPORT_SYMBOL_GPL(kvm_task_switch);
7362
b6c7a5dc
HB		 7363int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7364 struct kvm_sregs *sregs)
7365{
58cb628d 7366 struct msr_data apic_base_msr;
b6c7a5dc 7367 int mmu_reset_needed = 0;
63f42e02 7368 int pending_vec, max_bits, idx;
89a27f4d 7369 struct desc_ptr dt;
b6c7a5dc 7370
6d1068b3
PM		 7371 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7372 return -EINVAL;
7373
89a27f4d
GN		 7374 dt.size = sregs->idt.limit;
7375 dt.address = sregs->idt.base;
b6c7a5dc 7376 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7377 dt.size = sregs->gdt.limit;
7378 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7379 kvm_x86_ops->set_gdt(vcpu, &dt);
7380
ad312c7c 7381 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7382 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7383 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7384 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7385
2d3ad1f4 7386 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7387
f6801dff 7388 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7389 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7390 apic_base_msr.data = sregs->apic_base;
7391 apic_base_msr.host_initiated = true;
7392 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7393
4d4ec087 7394 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7395 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7396 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7397
fc78f519 7398 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7399 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7400 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7401 kvm_update_cpuid(vcpu);
63f42e02
XG		 7402
7403 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7404 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7405 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7406 mmu_reset_needed = 1;
7407 }
63f42e02 7408 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7409
7410 if (mmu_reset_needed)
7411 kvm_mmu_reset_context(vcpu);
7412
a50abc3b 7413 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7414 pending_vec = find_first_bit(
7415 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7416 if (pending_vec < max_bits) {
66fd3f7f 7417 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7418 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7419 }
7420
3e6e0aab
GT		 7421 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7422 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7423 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7424 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7425 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7426 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7427
3e6e0aab
GT		 7428 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7429 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7430
5f0269f5
ME		 7431 update_cr8_intercept(vcpu);
7432
9c3e4aab 7433 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7434 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7435 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7436 !is_protmode(vcpu))
9c3e4aab
MT		 7437 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7438
3842d135
AK		 7439 kvm_make_request(KVM_REQ_EVENT, vcpu);
7440
b6c7a5dc
HB		 7441 return 0;
7442}
7443
d0bfb940
JK		 7444int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7445 struct kvm_guest_debug *dbg)
b6c7a5dc 7446{
355be0b9 7447 unsigned long rflags;
ae675ef0 7448 int i, r;
b6c7a5dc 7449
4f926bf2
JK		 7450 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7451 r = -EBUSY;
7452 if (vcpu->arch.exception.pending)
2122ff5e 7453 goto out;
4f926bf2
JK		 7454 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7455 kvm_queue_exception(vcpu, DB_VECTOR);
7456 else
7457 kvm_queue_exception(vcpu, BP_VECTOR);
7458 }
7459
91586a3b
JK		 7460 /*
7461 * Read rflags as long as potentially injected trace flags are still
7462 * filtered out.
7463 */
7464 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7465
7466 vcpu->guest_debug = dbg->control;
7467 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7468 vcpu->guest_debug = 0;
7469
7470 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7471 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7472 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7473 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7474 } else {
7475 for (i = 0; i < KVM_NR_DB_REGS; i++)
7476 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7477 }
c8639010 7478 kvm_update_dr7(vcpu);
ae675ef0 7479
f92653ee
JK		 7480 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7481 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7482 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7483
91586a3b
JK		 7484 /*
7485 * Trigger an rflags update that will inject or remove the trace
7486 * flags.
7487 */
7488 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7489
a96036b8 7490 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7491
4f926bf2 7492 r = 0;
d0bfb940 7493
2122ff5e 7494out:
b6c7a5dc
HB		 7495
7496 return r;
7497}
7498
8b006791
ZX		 7499/*
7500 * Translate a guest virtual address to a guest physical address.
7501 */
7502int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7503 struct kvm_translation *tr)
7504{
7505 unsigned long vaddr = tr->linear_address;
7506 gpa_t gpa;
f656ce01 7507 int idx;
8b006791 7508
f656ce01 7509 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7510 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7511 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7512 tr->physical_address = gpa;
7513 tr->valid = gpa != UNMAPPED_GVA;
7514 tr->writeable = 1;
7515 tr->usermode = 0;
8b006791
ZX		 7516
7517 return 0;
7518}
7519
d0752060
HB		 7520int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7521{
c47ada30 7522 struct fxregs_state *fxsave =
7366ed77 7523 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7524
d0752060
HB		 7525 memcpy(fpu->fpr, fxsave->st_space, 128);
7526 fpu->fcw = fxsave->cwd;
7527 fpu->fsw = fxsave->swd;
7528 fpu->ftwx = fxsave->twd;
7529 fpu->last_opcode = fxsave->fop;
7530 fpu->last_ip = fxsave->rip;
7531 fpu->last_dp = fxsave->rdp;
7532 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7533
d0752060
HB		 7534 return 0;
7535}
7536
7537int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7538{
c47ada30 7539 struct fxregs_state *fxsave =
7366ed77 7540 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7541
d0752060
HB		 7542 memcpy(fxsave->st_space, fpu->fpr, 128);
7543 fxsave->cwd = fpu->fcw;
7544 fxsave->swd = fpu->fsw;
7545 fxsave->twd = fpu->ftwx;
7546 fxsave->fop = fpu->last_opcode;
7547 fxsave->rip = fpu->last_ip;
7548 fxsave->rdp = fpu->last_dp;
7549 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7550
d0752060
HB		 7551 return 0;
7552}
7553
0ee6a517 7554static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7555{
bf935b0b 7556 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7557 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7558 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7559 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7560
2acf923e
DC		 7561 /*
7562 * Ensure guest xcr0 is valid for loading
7563 */
d91cab78 7564 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7565
ad312c7c 7566 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7567}
d0752060
HB		 7568
7569void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7570{
2608d7a1 7571 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7572 return;
7573
2acf923e
DC		 7574 /*
7575 * Restore all possible states in the guest,
7576 * and assume host would use all available bits.
7577 * Guest xcr0 would be loaded later.
7578 */
d0752060 7579 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7580 __kernel_fpu_begin();
003e2e8b 7581 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7582 trace_kvm_fpu(1);
d0752060 7583}
d0752060
HB		 7584
7585void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7586{
3d42de25 7587 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7588 return;
7589
7590 vcpu->guest_fpu_loaded = 0;
4f836347 7591 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7592 __kernel_fpu_end();
f096ed85 7593 ++vcpu->stat.fpu_reload;
0c04851c 7594 trace_kvm_fpu(0);
d0752060 7595}
e9b11c17
ZX		 7596
7597void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7598{
bd768e14
IY		 7599 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7600
12f9a48f 7601 kvmclock_reset(vcpu);
7f1ea208 7602
e9b11c17 7603 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7604 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7605}
7606
7607struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7608 unsigned int id)
7609{
c447e76b
LL		 7610 struct kvm_vcpu *vcpu;
7611
6755bae8
ZA		 7612 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7613 printk_once(KERN_WARNING
7614 "kvm: SMP vm created on host with unstable TSC; "
7615 "guest TSC will not be reliable\n");
c447e76b
LL		 7616
7617 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7618
c447e76b 7619 return vcpu;
26e5215f 7620}
e9b11c17 7621
26e5215f
AK		 7622int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7623{
7624 int r;
e9b11c17 7625
19efffa2 7626 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7627 r = vcpu_load(vcpu);
7628 if (r)
7629 return r;
d28bc9dd 7630 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7631 kvm_mmu_setup(vcpu);
e9b11c17 7632 vcpu_put(vcpu);
26e5215f 7633 return r;
e9b11c17
ZX		 7634}
7635
31928aa5 7636void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7637{
8fe8ab46 7638 struct msr_data msr;
332967a3 7639 struct kvm *kvm = vcpu->kvm;
42897d86 7640
31928aa5
DD		 7641 if (vcpu_load(vcpu))
7642 return;
8fe8ab46
WA		 7643 msr.data = 0x0;
7644 msr.index = MSR_IA32_TSC;
7645 msr.host_initiated = true;
7646 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7647 vcpu_put(vcpu);
7648
630994b3
MT		 7649 if (!kvmclock_periodic_sync)
7650 return;
7651
332967a3
AJ		 7652 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7653 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7654}
7655
d40ccc62 7656void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7657{
9fc77441 7658 int r;
344d9588
GN		 7659 vcpu->arch.apf.msr_val = 0;
7660
9fc77441
MT		 7661 r = vcpu_load(vcpu);
7662 BUG_ON(r);
e9b11c17
ZX		 7663 kvm_mmu_unload(vcpu);
7664 vcpu_put(vcpu);
7665
7666 kvm_x86_ops->vcpu_free(vcpu);
7667}
7668
d28bc9dd 7669void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7670{
e69fab5d
PB		 7671 vcpu->arch.hflags = 0;
7672
c43203ca 7673 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7674 atomic_set(&vcpu->arch.nmi_queued, 0);
7675 vcpu->arch.nmi_pending = 0;
448fa4a9 7676 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7677 kvm_clear_interrupt_queue(vcpu);
7678 kvm_clear_exception_queue(vcpu);
448fa4a9 7679
42dbaa5a 7680 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7681 kvm_update_dr0123(vcpu);
6f43ed01 7682 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7683 kvm_update_dr6(vcpu);
42dbaa5a 7684 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7685 kvm_update_dr7(vcpu);
42dbaa5a 7686
1119022c
NA		 7687 vcpu->arch.cr2 = 0;
7688
3842d135 7689 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7690 vcpu->arch.apf.msr_val = 0;
c9aaa895 7691 vcpu->arch.st.msr_val = 0;
3842d135 7692
12f9a48f
GC		 7693 kvmclock_reset(vcpu);
7694
af585b92
GN		 7695 kvm_clear_async_pf_completion_queue(vcpu);
7696 kvm_async_pf_hash_reset(vcpu);
7697 vcpu->arch.apf.halted = false;
3842d135 7698
64d60670 7699 if (!init_event) {
d28bc9dd 7700 kvm_pmu_reset(vcpu);
64d60670
PB		 7701 vcpu->arch.smbase = 0x30000;
7702 }
f5132b01 7703
66f7b72e
JS		 7704 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7705 vcpu->arch.regs_avail = ~0;
7706 vcpu->arch.regs_dirty = ~0;
7707
d28bc9dd 7708 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7709}
7710
2b4a273b 7711void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7712{
7713 struct kvm_segment cs;
7714
7715 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7716 cs.selector = vector << 8;
7717 cs.base = vector << 12;
7718 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7719 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7720}
7721
13a34e06 7722int kvm_arch_hardware_enable(void)
e9b11c17 7723{
ca84d1a2
ZA		 7724 struct kvm *kvm;
7725 struct kvm_vcpu *vcpu;
7726 int i;
0dd6a6ed
ZA		 7727 int ret;
7728 u64 local_tsc;
7729 u64 max_tsc = 0;
7730 bool stable, backwards_tsc = false;
18863bdd
AK		 7731
7732 kvm_shared_msr_cpu_online();
13a34e06 7733 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7734 if (ret != 0)
7735 return ret;
7736
4ea1636b 7737 local_tsc = rdtsc();
0dd6a6ed
ZA		 7738 stable = !check_tsc_unstable();
7739 list_for_each_entry(kvm, &vm_list, vm_list) {
7740 kvm_for_each_vcpu(i, vcpu, kvm) {
7741 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7742 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7743 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7744 backwards_tsc = true;
7745 if (vcpu->arch.last_host_tsc > max_tsc)
7746 max_tsc = vcpu->arch.last_host_tsc;
7747 }
7748 }
7749 }
7750
7751 /*
7752 * Sometimes, even reliable TSCs go backwards. This happens on
7753 * platforms that reset TSC during suspend or hibernate actions, but
7754 * maintain synchronization. We must compensate. Fortunately, we can
7755 * detect that condition here, which happens early in CPU bringup,
7756 * before any KVM threads can be running. Unfortunately, we can't
7757 * bring the TSCs fully up to date with real time, as we aren't yet far
7758 * enough into CPU bringup that we know how much real time has actually
108b249c 7759 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7760 * variables that haven't been updated yet.
7761 *
7762 * So we simply find the maximum observed TSC above, then record the
7763 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7764 * the adjustment will be applied. Note that we accumulate
7765 * adjustments, in case multiple suspend cycles happen before some VCPU
7766 * gets a chance to run again. In the event that no KVM threads get a
7767 * chance to run, we will miss the entire elapsed period, as we'll have
7768 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7769 * loose cycle time. This isn't too big a deal, since the loss will be
7770 * uniform across all VCPUs (not to mention the scenario is extremely
7771 * unlikely). It is possible that a second hibernate recovery happens
7772 * much faster than a first, causing the observed TSC here to be
7773 * smaller; this would require additional padding adjustment, which is
7774 * why we set last_host_tsc to the local tsc observed here.
7775 *
7776 * N.B. - this code below runs only on platforms with reliable TSC,
7777 * as that is the only way backwards_tsc is set above. Also note
7778 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7779 * have the same delta_cyc adjustment applied if backwards_tsc
7780 * is detected. Note further, this adjustment is only done once,
7781 * as we reset last_host_tsc on all VCPUs to stop this from being
7782 * called multiple times (one for each physical CPU bringup).
7783 *
4a969980 7784 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7785 * will be compensated by the logic in vcpu_load, which sets the TSC to
7786 * catchup mode. This will catchup all VCPUs to real time, but cannot
7787 * guarantee that they stay in perfect synchronization.
7788 */
7789 if (backwards_tsc) {
7790 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7791 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7792 list_for_each_entry(kvm, &vm_list, vm_list) {
7793 kvm_for_each_vcpu(i, vcpu, kvm) {
7794 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7795 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7796 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7797 }
7798
7799 /*
7800 * We have to disable TSC offset matching.. if you were
7801 * booting a VM while issuing an S4 host suspend....
7802 * you may have some problem. Solving this issue is
7803 * left as an exercise to the reader.
7804 */
7805 kvm->arch.last_tsc_nsec = 0;
7806 kvm->arch.last_tsc_write = 0;
7807 }
7808
7809 }
7810 return 0;
e9b11c17
ZX		 7811}
7812
13a34e06 7813void kvm_arch_hardware_disable(void)
e9b11c17 7814{
13a34e06
RK		 7815 kvm_x86_ops->hardware_disable();
7816 drop_user_return_notifiers();
e9b11c17
ZX		 7817}
7818
7819int kvm_arch_hardware_setup(void)
7820{
9e9c3fe4
NA		 7821 int r;
7822
7823 r = kvm_x86_ops->hardware_setup();
7824 if (r != 0)
7825 return r;
7826
35181e86
HZ		 7827 if (kvm_has_tsc_control) {
7828 /*
7829 * Make sure the user can only configure tsc_khz values that
7830 * fit into a signed integer.
7831 * A min value is not calculated needed because it will always
7832 * be 1 on all machines.
7833 */
7834 u64 max = min(0x7fffffffULL,
7835 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7836 kvm_max_guest_tsc_khz = max;
7837
ad721883 7838 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7839 }
ad721883 7840
9e9c3fe4
NA		 7841 kvm_init_msr_list();
7842 return 0;
e9b11c17
ZX		 7843}
7844
7845void kvm_arch_hardware_unsetup(void)
7846{
7847 kvm_x86_ops->hardware_unsetup();
7848}
7849
7850void kvm_arch_check_processor_compat(void *rtn)
7851{
7852 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7853}
7854
7855bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7856{
7857 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7858}
7859EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7860
7861bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7862{
7863 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7864}
7865
54e9818f 7866struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7867EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7868
e9b11c17
ZX		 7869int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7870{
7871 struct page *page;
7872 struct kvm *kvm;
7873 int r;
7874
7875 BUG_ON(vcpu->kvm == NULL);
7876 kvm = vcpu->kvm;
7877
d62caabb 7878 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7879 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7880 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7881 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7882 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7883 else
a4535290 7884 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7885
7886 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7887 if (!page) {
7888 r = -ENOMEM;
7889 goto fail;
7890 }
ad312c7c 7891 vcpu->arch.pio_data = page_address(page);
e9b11c17 7892
cc578287 7893 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7894
e9b11c17
ZX		 7895 r = kvm_mmu_create(vcpu);
7896 if (r < 0)
7897 goto fail_free_pio_data;
7898
7899 if (irqchip_in_kernel(kvm)) {
7900 r = kvm_create_lapic(vcpu);
7901 if (r < 0)
7902 goto fail_mmu_destroy;
54e9818f
GN		 7903 } else
7904 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7905
890ca9ae
HY		 7906 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7907 GFP_KERNEL);
7908 if (!vcpu->arch.mce_banks) {
7909 r = -ENOMEM;
443c39bc 7910 goto fail_free_lapic;
890ca9ae
HY		 7911 }
7912 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7913
f1797359
WY		 7914 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7915 r = -ENOMEM;
f5f48ee1 7916 goto fail_free_mce_banks;
f1797359 7917 }
f5f48ee1 7918
0ee6a517 7919 fx_init(vcpu);
66f7b72e 7920
ba904635 7921 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7922 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7923
7924 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7925 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7926
5a4f55cd
EK		 7927 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7928
74545705
RK		 7929 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7930
af585b92 7931 kvm_async_pf_hash_reset(vcpu);
f5132b01 7932 kvm_pmu_init(vcpu);
af585b92 7933
1c1a9ce9
SR		 7934 vcpu->arch.pending_external_vector = -1;
7935
5c919412
AS		 7936 kvm_hv_vcpu_init(vcpu);
7937
e9b11c17 7938 return 0;
0ee6a517 7939
f5f48ee1
SY		 7940fail_free_mce_banks:
7941 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7942fail_free_lapic:
7943 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7944fail_mmu_destroy:
7945 kvm_mmu_destroy(vcpu);
7946fail_free_pio_data:
ad312c7c 7947 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7948fail:
7949 return r;
7950}
7951
7952void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7953{
f656ce01
MT		 7954 int idx;
7955
1f4b34f8 7956 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7957 kvm_pmu_destroy(vcpu);
36cb93fd 7958 kfree(vcpu->arch.mce_banks);
e9b11c17 7959 kvm_free_lapic(vcpu);
f656ce01 7960 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7961 kvm_mmu_destroy(vcpu);
f656ce01 7962 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7963 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7964 if (!lapic_in_kernel(vcpu))
54e9818f 7965 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7966}
d19a9cd2 7967
e790d9ef
RK		 7968void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7969{
ae97a3b8 7970 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7971}
7972
e08b9637 7973int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7974{
e08b9637
CO		 7975 if (type)
7976 return -EINVAL;
7977
6ef768fa 7978 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7979 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7980 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7981 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7982 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7983
5550af4d
SY		 7984 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7985 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7986 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7987 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7988 &kvm->arch.irq_sources_bitmap);
5550af4d 7989
038f8c11 7990 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7991 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 7992 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 7993 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7994
108b249c 7995 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 7996 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7997
7e44e449 7998 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7999 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8000
0eb05bf2 8001 kvm_page_track_init(kvm);
13d268ca 8002 kvm_mmu_init_vm(kvm);
0eb05bf2 8003
03543133
SS		 8004 if (kvm_x86_ops->vm_init)
8005 return kvm_x86_ops->vm_init(kvm);
8006
d89f5eff 8007 return 0;
d19a9cd2
ZX		 8008}
8009
8010static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8011{
9fc77441
MT		 8012 int r;
8013 r = vcpu_load(vcpu);
8014 BUG_ON(r);
d19a9cd2
ZX		 8015 kvm_mmu_unload(vcpu);
8016 vcpu_put(vcpu);
8017}
8018
8019static void kvm_free_vcpus(struct kvm *kvm)
8020{
8021 unsigned int i;
988a2cae 8022 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8023
8024 /*
8025 * Unpin any mmu pages first.
8026 */
af585b92
GN		 8027 kvm_for_each_vcpu(i, vcpu, kvm) {
8028 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8029 kvm_unload_vcpu_mmu(vcpu);
af585b92 8030 }
988a2cae
GN		 8031 kvm_for_each_vcpu(i, vcpu, kvm)
8032 kvm_arch_vcpu_free(vcpu);
8033
8034 mutex_lock(&kvm->lock);
8035 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8036 kvm->vcpus[i] = NULL;
d19a9cd2 8037
988a2cae
GN		 8038 atomic_set(&kvm->online_vcpus, 0);
8039 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8040}
8041
ad8ba2cd
SY		 8042void kvm_arch_sync_events(struct kvm *kvm)
8043{
332967a3 8044 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8045 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8046 kvm_free_pit(kvm);
ad8ba2cd
SY		 8047}
8048
1d8007bd 8049int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8050{
8051 int i, r;
25188b99 8052 unsigned long hva;
f0d648bd
PB		 8053 struct kvm_memslots *slots = kvm_memslots(kvm);
8054 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8055
8056 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8057 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8058 return -EINVAL;
9da0e4d5 8059
f0d648bd
PB		 8060 slot = id_to_memslot(slots, id);
8061 if (size) {
b21629da 8062 if (slot->npages)
f0d648bd
PB		 8063 return -EEXIST;
8064
8065 /*
8066 * MAP_SHARED to prevent internal slot pages from being moved
8067 * by fork()/COW.
8068 */
8069 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8070 MAP_SHARED | MAP_ANONYMOUS, 0);
8071 if (IS_ERR((void *)hva))
8072 return PTR_ERR((void *)hva);
8073 } else {
8074 if (!slot->npages)
8075 return 0;
8076
8077 hva = 0;
8078 }
8079
8080 old = *slot;
9da0e4d5 8081 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8082 struct kvm_userspace_memory_region m;
9da0e4d5 8083
1d8007bd
PB		 8084 m.slot = id | (i << 16);
8085 m.flags = 0;
8086 m.guest_phys_addr = gpa;
f0d648bd 8087 m.userspace_addr = hva;
1d8007bd 8088 m.memory_size = size;
9da0e4d5
PB		 8089 r = __kvm_set_memory_region(kvm, &m);
8090 if (r < 0)
8091 return r;
8092 }
8093
f0d648bd
PB		 8094 if (!size) {
8095 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8096 WARN_ON(r < 0);
8097 }
8098
9da0e4d5
PB		 8099 return 0;
8100}
8101EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8102
1d8007bd 8103int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8104{
8105 int r;
8106
8107 mutex_lock(&kvm->slots_lock);
1d8007bd 8108 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8109 mutex_unlock(&kvm->slots_lock);
8110
8111 return r;
8112}
8113EXPORT_SYMBOL_GPL(x86_set_memory_region);
8114
d19a9cd2
ZX		 8115void kvm_arch_destroy_vm(struct kvm *kvm)
8116{
27469d29
AH		 8117 if (current->mm == kvm->mm) {
8118 /*
8119 * Free memory regions allocated on behalf of userspace,
8120 * unless the the memory map has changed due to process exit
8121 * or fd copying.
8122 */
1d8007bd
PB		 8123 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8124 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8125 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8126 }
03543133
SS		 8127 if (kvm_x86_ops->vm_destroy)
8128 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8129 kvm_pic_destroy(kvm);
8130 kvm_ioapic_destroy(kvm);
d19a9cd2 8131 kvm_free_vcpus(kvm);
af1bae54 8132 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8133 kvm_mmu_uninit_vm(kvm);
2beb6dad 8134 kvm_page_track_cleanup(kvm);
d19a9cd2 8135}
0de10343 8136
5587027c 8137void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8138 struct kvm_memory_slot *dont)
8139{
8140 int i;
8141
d89cc617
TY		 8142 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8143 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8144 kvfree(free->arch.rmap[i]);
d89cc617 8145 free->arch.rmap[i] = NULL;
77d11309 8146 }
d89cc617
TY		 8147 if (i == 0)
8148 continue;
8149
8150 if (!dont || free->arch.lpage_info[i - 1] !=
8151 dont->arch.lpage_info[i - 1]) {
548ef284 8152 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8153 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8154 }
8155 }
21ebbeda
XG		 8156
8157 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8158}
8159
5587027c
AK		 8160int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8161 unsigned long npages)
db3fe4eb
TY		 8162{
8163 int i;
8164
d89cc617 8165 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8166 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8167 unsigned long ugfn;
8168 int lpages;
d89cc617 8169 int level = i + 1;
db3fe4eb
TY		 8170
8171 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8172 slot->base_gfn, level) + 1;
8173
d89cc617
TY		 8174 slot->arch.rmap[i] =
8175 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8176 if (!slot->arch.rmap[i])
77d11309 8177 goto out_free;
d89cc617
TY		 8178 if (i == 0)
8179 continue;
77d11309 8180
92f94f1e
XG		 8181 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8182 if (!linfo)
db3fe4eb
TY		 8183 goto out_free;
8184
92f94f1e
XG		 8185 slot->arch.lpage_info[i - 1] = linfo;
8186
db3fe4eb 8187 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8188 linfo[0].disallow_lpage = 1;
db3fe4eb 8189 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8190 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8191 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8192 /*
8193 * If the gfn and userspace address are not aligned wrt each
8194 * other, or if explicitly asked to, disable large page
8195 * support for this slot
8196 */
8197 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8198 !kvm_largepages_enabled()) {
8199 unsigned long j;
8200
8201 for (j = 0; j < lpages; ++j)
92f94f1e 8202 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8203 }
8204 }
8205
21ebbeda
XG		 8206 if (kvm_page_track_create_memslot(slot, npages))
8207 goto out_free;
8208
db3fe4eb
TY		 8209 return 0;
8210
8211out_free:
d89cc617 8212 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8213 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8214 slot->arch.rmap[i] = NULL;
8215 if (i == 0)
8216 continue;
8217
548ef284 8218 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8219 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8220 }
8221 return -ENOMEM;
8222}
8223
15f46015 8224void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8225{
e6dff7d1
TY		 8226 /*
8227 * memslots->generation has been incremented.
8228 * mmio generation may have reached its maximum value.
8229 */
54bf36aa 8230 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8231}
8232
f7784b8e
MT		 8233int kvm_arch_prepare_memory_region(struct kvm *kvm,
8234 struct kvm_memory_slot *memslot,
09170a49 8235 const struct kvm_userspace_memory_region *mem,
7b6195a9 8236 enum kvm_mr_change change)
0de10343 8237{
f7784b8e
MT		 8238 return 0;
8239}
8240
88178fd4
KH		 8241static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8242 struct kvm_memory_slot *new)
8243{
8244 /* Still write protect RO slot */
8245 if (new->flags & KVM_MEM_READONLY) {
8246 kvm_mmu_slot_remove_write_access(kvm, new);
8247 return;
8248 }
8249
8250 /*
8251 * Call kvm_x86_ops dirty logging hooks when they are valid.
8252 *
8253 * kvm_x86_ops->slot_disable_log_dirty is called when:
8254 *
8255 * - KVM_MR_CREATE with dirty logging is disabled
8256 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8257 *
8258 * The reason is, in case of PML, we need to set D-bit for any slots
8259 * with dirty logging disabled in order to eliminate unnecessary GPA
8260 * logging in PML buffer (and potential PML buffer full VMEXT). This
8261 * guarantees leaving PML enabled during guest's lifetime won't have
8262 * any additonal overhead from PML when guest is running with dirty
8263 * logging disabled for memory slots.
8264 *
8265 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8266 * to dirty logging mode.
8267 *
8268 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8269 *
8270 * In case of write protect:
8271 *
8272 * Write protect all pages for dirty logging.
8273 *
8274 * All the sptes including the large sptes which point to this
8275 * slot are set to readonly. We can not create any new large
8276 * spte on this slot until the end of the logging.
8277 *
8278 * See the comments in fast_page_fault().
8279 */
8280 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8281 if (kvm_x86_ops->slot_enable_log_dirty)
8282 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8283 else
8284 kvm_mmu_slot_remove_write_access(kvm, new);
8285 } else {
8286 if (kvm_x86_ops->slot_disable_log_dirty)
8287 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8288 }
8289}
8290
f7784b8e 8291void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8292 const struct kvm_userspace_memory_region *mem,
8482644a 8293 const struct kvm_memory_slot *old,
f36f3f28 8294 const struct kvm_memory_slot *new,
8482644a 8295 enum kvm_mr_change change)
f7784b8e 8296{
8482644a 8297 int nr_mmu_pages = 0;
f7784b8e 8298
48c0e4e9
XG		 8299 if (!kvm->arch.n_requested_mmu_pages)
8300 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8301
48c0e4e9 8302 if (nr_mmu_pages)
0de10343 8303 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8304
3ea3b7fa
WL		 8305 /*
8306 * Dirty logging tracks sptes in 4k granularity, meaning that large
8307 * sptes have to be split. If live migration is successful, the guest
8308 * in the source machine will be destroyed and large sptes will be
8309 * created in the destination. However, if the guest continues to run
8310 * in the source machine (for example if live migration fails), small
8311 * sptes will remain around and cause bad performance.
8312 *
8313 * Scan sptes if dirty logging has been stopped, dropping those
8314 * which can be collapsed into a single large-page spte. Later
8315 * page faults will create the large-page sptes.
8316 */
8317 if ((change != KVM_MR_DELETE) &&
8318 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8319 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8320 kvm_mmu_zap_collapsible_sptes(kvm, new);
8321
c972f3b1 8322 /*
88178fd4 8323 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8324 *
88178fd4
KH		 8325 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8326 * been zapped so no dirty logging staff is needed for old slot. For
8327 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8328 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8329 *
8330 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8331 */
88178fd4 8332 if (change != KVM_MR_DELETE)
f36f3f28 8333 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8334}
1d737c8a 8335
2df72e9b 8336void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8337{
6ca18b69 8338 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8339}
8340
2df72e9b
MT		 8341void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8342 struct kvm_memory_slot *slot)
8343{
ae7cd873 8344 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8345}
8346
5d9bc648
PB		 8347static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8348{
8349 if (!list_empty_careful(&vcpu->async_pf.done))
8350 return true;
8351
8352 if (kvm_apic_has_events(vcpu))
8353 return true;
8354
8355 if (vcpu->arch.pv.pv_unhalted)
8356 return true;
8357
8358 if (atomic_read(&vcpu->arch.nmi_queued))
8359 return true;
8360
73917739
PB		 8361 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8362 return true;
8363
5d9bc648
PB		 8364 if (kvm_arch_interrupt_allowed(vcpu) &&
8365 kvm_cpu_has_interrupt(vcpu))
8366 return true;
8367
1f4b34f8
AS		 8368 if (kvm_hv_has_stimer_pending(vcpu))
8369 return true;
8370
5d9bc648
PB		 8371 return false;
8372}
8373
1d737c8a
ZX		 8374int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8375{
5d9bc648 8376 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8377}
5736199a 8378
b6d33834 8379int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8380{
b6d33834 8381 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8382}
78646121
GN		 8383
8384int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8385{
8386 return kvm_x86_ops->interrupt_allowed(vcpu);
8387}
229456fc 8388
82b32774 8389unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8390{
82b32774
NA		 8391 if (is_64_bit_mode(vcpu))
8392 return kvm_rip_read(vcpu);
8393 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8394 kvm_rip_read(vcpu));
8395}
8396EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8397
82b32774
NA		 8398bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8399{
8400 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8401}
8402EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8403
94fe45da
JK		 8404unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8405{
8406 unsigned long rflags;
8407
8408 rflags = kvm_x86_ops->get_rflags(vcpu);
8409 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8410 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8411 return rflags;
8412}
8413EXPORT_SYMBOL_GPL(kvm_get_rflags);
8414
6addfc42 8415static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8416{
8417 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8418 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8419 rflags |= X86_EFLAGS_TF;
94fe45da 8420 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8421}
8422
8423void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8424{
8425 __kvm_set_rflags(vcpu, rflags);
3842d135 8426 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8427}
8428EXPORT_SYMBOL_GPL(kvm_set_rflags);
8429
56028d08
GN		 8430void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8431{
8432 int r;
8433
fb67e14f 8434 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8435 work->wakeup_all)
56028d08
GN		 8436 return;
8437
8438 r = kvm_mmu_reload(vcpu);
8439 if (unlikely(r))
8440 return;
8441
fb67e14f
XG		 8442 if (!vcpu->arch.mmu.direct_map &&
8443 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8444 return;
8445
56028d08
GN		 8446 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8447}
8448
af585b92
GN		 8449static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8450{
8451 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8452}
8453
8454static inline u32 kvm_async_pf_next_probe(u32 key)
8455{
8456 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8457}
8458
8459static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8460{
8461 u32 key = kvm_async_pf_hash_fn(gfn);
8462
8463 while (vcpu->arch.apf.gfns[key] != ~0)
8464 key = kvm_async_pf_next_probe(key);
8465
8466 vcpu->arch.apf.gfns[key] = gfn;
8467}
8468
8469static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8470{
8471 int i;
8472 u32 key = kvm_async_pf_hash_fn(gfn);
8473
8474 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8475 (vcpu->arch.apf.gfns[key] != gfn &&
8476 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8477 key = kvm_async_pf_next_probe(key);
8478
8479 return key;
8480}
8481
8482bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8483{
8484 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8485}
8486
8487static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8488{
8489 u32 i, j, k;
8490
8491 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8492 while (true) {
8493 vcpu->arch.apf.gfns[i] = ~0;
8494 do {
8495 j = kvm_async_pf_next_probe(j);
8496 if (vcpu->arch.apf.gfns[j] == ~0)
8497 return;
8498 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8499 /*
8500 * k lies cyclically in ]i,j]
8501 * | i.k.j |
8502 * |....j i.k.| or |.k..j i...|
8503 */
8504 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8505 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8506 i = j;
8507 }
8508}
8509
7c90705b
GN		 8510static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8511{
bbd64115
CL		 8512 return kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.apf.data, &val,
8513 sizeof(val));
7c90705b
GN		 8514}
8515
af585b92
GN		 8516void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8517 struct kvm_async_pf *work)
8518{
6389ee94
AK		 8519 struct x86_exception fault;
8520
7c90705b 8521 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8522 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8523
8524 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8525 (vcpu->arch.apf.send_user_only &&
8526 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8527 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8528 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8529 fault.vector = PF_VECTOR;
8530 fault.error_code_valid = true;
8531 fault.error_code = 0;
8532 fault.nested_page_fault = false;
8533 fault.address = work->arch.token;
8534 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8535 }
af585b92
GN		 8536}
8537
8538void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8539 struct kvm_async_pf *work)
8540{
6389ee94
AK		 8541 struct x86_exception fault;
8542
f2e10669 8543 if (work->wakeup_all)
7c90705b
GN		 8544 work->arch.token = ~0; /* broadcast wakeup */
8545 else
8546 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8547 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8548
8549 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8550 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8551 fault.vector = PF_VECTOR;
8552 fault.error_code_valid = true;
8553 fault.error_code = 0;
8554 fault.nested_page_fault = false;
8555 fault.address = work->arch.token;
8556 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8557 }
e6d53e3b 8558 vcpu->arch.apf.halted = false;
a4fa1635 8559 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8560}
8561
8562bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8563{
8564 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8565 return true;
8566 else
8567 return !kvm_event_needs_reinjection(vcpu) &&
8568 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8569}
8570
5544eb9b
PB		 8571void kvm_arch_start_assignment(struct kvm *kvm)
8572{
8573 atomic_inc(&kvm->arch.assigned_device_count);
8574}
8575EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8576
8577void kvm_arch_end_assignment(struct kvm *kvm)
8578{
8579 atomic_dec(&kvm->arch.assigned_device_count);
8580}
8581EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8582
8583bool kvm_arch_has_assigned_device(struct kvm *kvm)
8584{
8585 return atomic_read(&kvm->arch.assigned_device_count);
8586}
8587EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8588
e0f0bbc5
AW		 8589void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8590{
8591 atomic_inc(&kvm->arch.noncoherent_dma_count);
8592}
8593EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8594
8595void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8596{
8597 atomic_dec(&kvm->arch.noncoherent_dma_count);
8598}
8599EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8600
8601bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8602{
8603 return atomic_read(&kvm->arch.noncoherent_dma_count);
8604}
8605EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8606
14717e20
AW		 8607bool kvm_arch_has_irq_bypass(void)
8608{
8609 return kvm_x86_ops->update_pi_irte != NULL;
8610}
8611
87276880
FW		 8612int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8613 struct irq_bypass_producer *prod)
8614{
8615 struct kvm_kernel_irqfd *irqfd =
8616 container_of(cons, struct kvm_kernel_irqfd, consumer);
8617
14717e20 8618 irqfd->producer = prod;
87276880 8619
14717e20
AW		 8620 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8621 prod->irq, irqfd->gsi, 1);
87276880
FW		 8622}
8623
8624void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8625 struct irq_bypass_producer *prod)
8626{
8627 int ret;
8628 struct kvm_kernel_irqfd *irqfd =
8629 container_of(cons, struct kvm_kernel_irqfd, consumer);
8630
87276880
FW		 8631 WARN_ON(irqfd->producer != prod);
8632 irqfd->producer = NULL;
8633
8634 /*
8635 * When producer of consumer is unregistered, we change back to
8636 * remapped mode, so we can re-use the current implementation
bb3541f1 8637 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8638 * int this case doesn't want to receive the interrupts.
8639 */
8640 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8641 if (ret)
8642 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8643 " fails: %d\n", irqfd->consumer.token, ret);
8644}
8645
8646int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8647 uint32_t guest_irq, bool set)
8648{
8649 if (!kvm_x86_ops->update_pi_irte)
8650 return -EINVAL;
8651
8652 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8653}
8654
52004014
FW		 8655bool kvm_vector_hashing_enabled(void)
8656{
8657 return vector_hashing;
8658}
8659EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8660
229456fc 8661EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8662EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8663EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8664EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8665EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8666EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8667EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8668EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8669EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8670EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8671EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8672EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8673EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8674EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8675EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8676EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8677EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8678EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8679EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git