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Commit | Line | Data |
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1938f4a5 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2002-2006 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Marius Groeger <mgroeger@sysgo.de> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
11 | */ |
12 | ||
13 | #include <common.h> | |
24b852a7 | 14 | #include <console.h> |
1938f4a5 | 15 | #include <environment.h> |
ab7cd627 | 16 | #include <dm.h> |
1938f4a5 | 17 | #include <fdtdec.h> |
f828bf25 | 18 | #include <fs.h> |
e4fef6cf | 19 | #include <i2c.h> |
1938f4a5 | 20 | #include <initcall.h> |
96d4b75c | 21 | #include <init_helpers.h> |
1938f4a5 | 22 | #include <logbuff.h> |
fb5cf7f1 | 23 | #include <malloc.h> |
0eb25b61 | 24 | #include <mapmem.h> |
a733b06b | 25 | #include <os.h> |
1938f4a5 | 26 | #include <post.h> |
e47b2d67 | 27 | #include <relocate.h> |
e4fef6cf | 28 | #include <spi.h> |
c5d4001a | 29 | #include <status_led.h> |
1057e6cf | 30 | #include <timer.h> |
71c52dba | 31 | #include <trace.h> |
5a541945 | 32 | #include <video.h> |
e4fef6cf | 33 | #include <watchdog.h> |
1fbf97dc SG |
34 | #if defined(CONFIG_MP) && defined(CONFIG_PPC) |
35 | #include <asm/mp.h> | |
36 | #endif | |
1938f4a5 SG |
37 | #include <asm/io.h> |
38 | #include <asm/sections.h> | |
ab7cd627 | 39 | #include <dm/root.h> |
056285fd | 40 | #include <linux/errno.h> |
1938f4a5 SG |
41 | |
42 | /* | |
43 | * Pointer to initial global data area | |
44 | * | |
45 | * Here we initialize it if needed. | |
46 | */ | |
47 | #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR | |
48 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
49 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
50 | DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); | |
51 | #else | |
52 | DECLARE_GLOBAL_DATA_PTR; | |
53 | #endif | |
54 | ||
55 | /* | |
4c509343 | 56 | * TODO(sjg@chromium.org): IMO this code should be |
1938f4a5 SG |
57 | * refactored to a single function, something like: |
58 | * | |
59 | * void led_set_state(enum led_colour_t colour, int on); | |
60 | */ | |
61 | /************************************************************************ | |
62 | * Coloured LED functionality | |
63 | ************************************************************************ | |
64 | * May be supplied by boards if desired | |
65 | */ | |
c5d4001a JH |
66 | __weak void coloured_LED_init(void) {} |
67 | __weak void red_led_on(void) {} | |
68 | __weak void red_led_off(void) {} | |
69 | __weak void green_led_on(void) {} | |
70 | __weak void green_led_off(void) {} | |
71 | __weak void yellow_led_on(void) {} | |
72 | __weak void yellow_led_off(void) {} | |
73 | __weak void blue_led_on(void) {} | |
74 | __weak void blue_led_off(void) {} | |
1938f4a5 SG |
75 | |
76 | /* | |
77 | * Why is gd allocated a register? Prior to reloc it might be better to | |
78 | * just pass it around to each function in this file? | |
79 | * | |
80 | * After reloc one could argue that it is hardly used and doesn't need | |
81 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
82 | * global data for all modules, so that post-reloc we can avoid the massive | |
83 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
84 | * a structure... | |
85 | */ | |
86 | ||
d54d7eb9 | 87 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) |
e4fef6cf SG |
88 | static int init_func_watchdog_init(void) |
89 | { | |
ea3310e8 TR |
90 | # if defined(CONFIG_HW_WATCHDOG) && \ |
91 | (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ | |
14a380a8 | 92 | defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ |
46d7a3b3 | 93 | defined(CONFIG_DESIGNWARE_WATCHDOG) || \ |
14a380a8 | 94 | defined(CONFIG_IMX_WATCHDOG)) |
d54d7eb9 | 95 | hw_watchdog_init(); |
e4fef6cf | 96 | puts(" Watchdog enabled\n"); |
ba169d98 | 97 | # endif |
e4fef6cf SG |
98 | WATCHDOG_RESET(); |
99 | ||
100 | return 0; | |
101 | } | |
102 | ||
103 | int init_func_watchdog_reset(void) | |
104 | { | |
105 | WATCHDOG_RESET(); | |
106 | ||
107 | return 0; | |
108 | } | |
109 | #endif /* CONFIG_WATCHDOG */ | |
110 | ||
dd2a6cd0 | 111 | __weak void board_add_ram_info(int use_default) |
e4fef6cf SG |
112 | { |
113 | /* please define platform specific board_add_ram_info() */ | |
114 | } | |
115 | ||
1938f4a5 SG |
116 | static int init_baud_rate(void) |
117 | { | |
118 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); | |
119 | return 0; | |
120 | } | |
121 | ||
122 | static int display_text_info(void) | |
123 | { | |
9b217498 | 124 | #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) |
9fdee7d7 | 125 | ulong bss_start, bss_end, text_base; |
1938f4a5 | 126 | |
632efa74 SG |
127 | bss_start = (ulong)&__bss_start; |
128 | bss_end = (ulong)&__bss_end; | |
b60eff31 | 129 | |
d54d7eb9 | 130 | #ifdef CONFIG_SYS_TEXT_BASE |
9fdee7d7 | 131 | text_base = CONFIG_SYS_TEXT_BASE; |
d54d7eb9 | 132 | #else |
9fdee7d7 | 133 | text_base = CONFIG_SYS_MONITOR_BASE; |
d54d7eb9 | 134 | #endif |
9fdee7d7 DS |
135 | |
136 | debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", | |
137 | text_base, bss_start, bss_end); | |
a733b06b | 138 | #endif |
1938f4a5 | 139 | |
1938f4a5 SG |
140 | #ifdef CONFIG_USE_IRQ |
141 | debug("IRQ Stack: %08lx\n", IRQ_STACK_START); | |
142 | debug("FIQ Stack: %08lx\n", FIQ_STACK_START); | |
143 | #endif | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | static int announce_dram_init(void) | |
149 | { | |
150 | puts("DRAM: "); | |
151 | return 0; | |
152 | } | |
153 | ||
e310b93e | 154 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
155 | static int init_func_ram(void) |
156 | { | |
088454cd | 157 | return initdram(); |
e4fef6cf SG |
158 | } |
159 | #endif | |
160 | ||
1938f4a5 SG |
161 | static int show_dram_config(void) |
162 | { | |
fa39ffe5 | 163 | unsigned long long size; |
1938f4a5 SG |
164 | |
165 | #ifdef CONFIG_NR_DRAM_BANKS | |
166 | int i; | |
167 | ||
168 | debug("\nRAM Configuration:\n"); | |
169 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
170 | size += gd->bd->bi_dram[i].size; | |
715f599f BM |
171 | debug("Bank #%d: %llx ", i, |
172 | (unsigned long long)(gd->bd->bi_dram[i].start)); | |
1938f4a5 SG |
173 | #ifdef DEBUG |
174 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
175 | #endif | |
176 | } | |
177 | debug("\nDRAM: "); | |
178 | #else | |
179 | size = gd->ram_size; | |
180 | #endif | |
181 | ||
e4fef6cf SG |
182 | print_size(size, ""); |
183 | board_add_ram_info(0); | |
184 | putc('\n'); | |
1938f4a5 SG |
185 | |
186 | return 0; | |
187 | } | |
188 | ||
76b00aca | 189 | __weak int dram_init_banksize(void) |
1938f4a5 SG |
190 | { |
191 | #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) | |
192 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
193 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
194 | #endif | |
76b00aca SG |
195 | |
196 | return 0; | |
1938f4a5 SG |
197 | } |
198 | ||
ea818dbb | 199 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
200 | static int init_func_i2c(void) |
201 | { | |
202 | puts("I2C: "); | |
815a76f2 | 203 | #ifdef CONFIG_SYS_I2C |
204 | i2c_init_all(); | |
205 | #else | |
e4fef6cf | 206 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
815a76f2 | 207 | #endif |
e4fef6cf SG |
208 | puts("ready\n"); |
209 | return 0; | |
210 | } | |
211 | #endif | |
212 | ||
213 | #if defined(CONFIG_HARD_SPI) | |
214 | static int init_func_spi(void) | |
215 | { | |
216 | puts("SPI: "); | |
217 | spi_init(); | |
218 | puts("ready\n"); | |
219 | return 0; | |
220 | } | |
221 | #endif | |
222 | ||
223 | __maybe_unused | |
1938f4a5 SG |
224 | static int zero_global_data(void) |
225 | { | |
226 | memset((void *)gd, '\0', sizeof(gd_t)); | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | static int setup_mon_len(void) | |
232 | { | |
e945f6dc | 233 | #if defined(__ARM__) || defined(__MICROBLAZE__) |
b60eff31 | 234 | gd->mon_len = (ulong)&__bss_end - (ulong)_start; |
9b217498 | 235 | #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) |
a733b06b | 236 | gd->mon_len = (ulong)&_end - (ulong)_init; |
ea3310e8 | 237 | #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) |
d54d7eb9 | 238 | gd->mon_len = CONFIG_SYS_MONITOR_LEN; |
e2099d78 | 239 | #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) |
2e88bb28 | 240 | gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); |
b0b35953 | 241 | #elif defined(CONFIG_SYS_MONITOR_BASE) |
e4fef6cf SG |
242 | /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ |
243 | gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 244 | #endif |
1938f4a5 SG |
245 | return 0; |
246 | } | |
247 | ||
248 | __weak int arch_cpu_init(void) | |
249 | { | |
250 | return 0; | |
251 | } | |
252 | ||
8ebf5069 PB |
253 | __weak int mach_cpu_init(void) |
254 | { | |
255 | return 0; | |
256 | } | |
257 | ||
1938f4a5 SG |
258 | /* Get the top of usable RAM */ |
259 | __weak ulong board_get_usable_ram_top(ulong total_size) | |
260 | { | |
1e4d11a5 SW |
261 | #ifdef CONFIG_SYS_SDRAM_BASE |
262 | /* | |
4c509343 | 263 | * Detect whether we have so much RAM that it goes past the end of our |
1e4d11a5 SW |
264 | * 32-bit address space. If so, clip the usable RAM so it doesn't. |
265 | */ | |
266 | if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) | |
267 | /* | |
268 | * Will wrap back to top of 32-bit space when reservations | |
269 | * are made. | |
270 | */ | |
271 | return 0; | |
272 | #endif | |
1938f4a5 SG |
273 | return gd->ram_top; |
274 | } | |
275 | ||
276 | static int setup_dest_addr(void) | |
277 | { | |
278 | debug("Monitor len: %08lX\n", gd->mon_len); | |
279 | /* | |
280 | * Ram is setup, size stored in gd !! | |
281 | */ | |
282 | debug("Ram size: %08lX\n", (ulong)gd->ram_size); | |
36cc0de0 | 283 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) |
1938f4a5 SG |
284 | /* |
285 | * Subtract specified amount of memory to hide so that it won't | |
286 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
287 | * the Linux kernel should now get passed the now "corrected" | |
36cc0de0 YS |
288 | * memory size and won't touch it either. This should work |
289 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
290 | * arch/powerpc with bootwrapper support, that recalculate the | |
291 | * memory size from the SDRAM controller setup will have to | |
292 | * get fixed. | |
1938f4a5 | 293 | */ |
36cc0de0 YS |
294 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; |
295 | #endif | |
1938f4a5 SG |
296 | #ifdef CONFIG_SYS_SDRAM_BASE |
297 | gd->ram_top = CONFIG_SYS_SDRAM_BASE; | |
298 | #endif | |
e4fef6cf | 299 | gd->ram_top += get_effective_memsize(); |
1938f4a5 | 300 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 301 | gd->relocaddr = gd->ram_top; |
1938f4a5 | 302 | debug("Ram top: %08lX\n", (ulong)gd->ram_top); |
ec3b4820 | 303 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
e4fef6cf SG |
304 | /* |
305 | * We need to make sure the location we intend to put secondary core | |
306 | * boot code is reserved and not used by any part of u-boot | |
307 | */ | |
a0ba279a MY |
308 | if (gd->relocaddr > determine_mp_bootpg(NULL)) { |
309 | gd->relocaddr = determine_mp_bootpg(NULL); | |
310 | debug("Reserving MP boot page to %08lx\n", gd->relocaddr); | |
e4fef6cf SG |
311 | } |
312 | #endif | |
1938f4a5 SG |
313 | return 0; |
314 | } | |
315 | ||
b56db486 | 316 | #if defined(CONFIG_LOGBUFFER) |
1938f4a5 SG |
317 | static int reserve_logbuffer(void) |
318 | { | |
b56db486 | 319 | #ifndef CONFIG_ALT_LB_ADDR |
1938f4a5 | 320 | /* reserve kernel log buffer */ |
a0ba279a | 321 | gd->relocaddr -= LOGBUFF_RESERVE; |
1938f4a5 | 322 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
a0ba279a | 323 | gd->relocaddr); |
b56db486 SG |
324 | #endif |
325 | ||
1938f4a5 SG |
326 | return 0; |
327 | } | |
328 | #endif | |
329 | ||
330 | #ifdef CONFIG_PRAM | |
331 | /* reserve protected RAM */ | |
332 | static int reserve_pram(void) | |
333 | { | |
334 | ulong reg; | |
335 | ||
336 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); | |
a0ba279a | 337 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 338 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 339 | gd->relocaddr); |
1938f4a5 SG |
340 | return 0; |
341 | } | |
342 | #endif /* CONFIG_PRAM */ | |
343 | ||
344 | /* Round memory pointer down to next 4 kB limit */ | |
345 | static int reserve_round_4k(void) | |
346 | { | |
a0ba279a | 347 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
348 | return 0; |
349 | } | |
350 | ||
80d4bcd3 | 351 | #ifdef CONFIG_ARM |
1938f4a5 SG |
352 | static int reserve_mmu(void) |
353 | { | |
80d4bcd3 | 354 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) |
1938f4a5 | 355 | /* reserve TLB table */ |
cce6be7f | 356 | gd->arch.tlb_size = PGTABLE_SIZE; |
a0ba279a | 357 | gd->relocaddr -= gd->arch.tlb_size; |
1938f4a5 SG |
358 | |
359 | /* round down to next 64 kB limit */ | |
a0ba279a | 360 | gd->relocaddr &= ~(0x10000 - 1); |
1938f4a5 | 361 | |
a0ba279a | 362 | gd->arch.tlb_addr = gd->relocaddr; |
1938f4a5 SG |
363 | debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, |
364 | gd->arch.tlb_addr + gd->arch.tlb_size); | |
50e93b95 YS |
365 | |
366 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE | |
367 | /* | |
368 | * Record allocated tlb_addr in case gd->tlb_addr to be overwritten | |
369 | * with location within secure ram. | |
370 | */ | |
371 | gd->arch.tlb_allocated = gd->arch.tlb_addr; | |
80d4bcd3 | 372 | #endif |
50e93b95 YS |
373 | #endif |
374 | ||
1938f4a5 SG |
375 | return 0; |
376 | } | |
377 | #endif | |
378 | ||
5a541945 SG |
379 | static int reserve_video(void) |
380 | { | |
0f079eb5 | 381 | #ifdef CONFIG_DM_VIDEO |
5a541945 SG |
382 | ulong addr; |
383 | int ret; | |
384 | ||
385 | addr = gd->relocaddr; | |
386 | ret = video_reserve(&addr); | |
387 | if (ret) | |
388 | return ret; | |
389 | gd->relocaddr = addr; | |
0f079eb5 | 390 | #elif defined(CONFIG_LCD) |
5a541945 | 391 | # ifdef CONFIG_FB_ADDR |
1938f4a5 | 392 | gd->fb_base = CONFIG_FB_ADDR; |
5a541945 | 393 | # else |
1938f4a5 | 394 | /* reserve memory for LCD display (always full pages) */ |
a0ba279a MY |
395 | gd->relocaddr = lcd_setmem(gd->relocaddr); |
396 | gd->fb_base = gd->relocaddr; | |
5a541945 | 397 | # endif /* CONFIG_FB_ADDR */ |
0f079eb5 SG |
398 | #elif defined(CONFIG_VIDEO) && \ |
399 | (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ | |
d54d7eb9 | 400 | !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ |
ea3310e8 | 401 | !defined(CONFIG_M68K) |
e4fef6cf | 402 | /* reserve memory for video display (always full pages) */ |
a0ba279a MY |
403 | gd->relocaddr = video_setmem(gd->relocaddr); |
404 | gd->fb_base = gd->relocaddr; | |
0f079eb5 | 405 | #endif |
e4fef6cf SG |
406 | |
407 | return 0; | |
408 | } | |
e4fef6cf | 409 | |
8703ef3f SG |
410 | static int reserve_trace(void) |
411 | { | |
412 | #ifdef CONFIG_TRACE | |
413 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
414 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
415 | debug("Reserving %dk for trace data at: %08lx\n", | |
416 | CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
417 | #endif | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
1938f4a5 SG |
422 | static int reserve_uboot(void) |
423 | { | |
424 | /* | |
425 | * reserve memory for U-Boot code, data & bss | |
426 | * round down to next 4 kB limit | |
427 | */ | |
a0ba279a MY |
428 | gd->relocaddr -= gd->mon_len; |
429 | gd->relocaddr &= ~(4096 - 1); | |
e4fef6cf SG |
430 | #ifdef CONFIG_E500 |
431 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
a0ba279a | 432 | gd->relocaddr &= ~(65536 - 1); |
e4fef6cf | 433 | #endif |
1938f4a5 SG |
434 | |
435 | debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, | |
a0ba279a MY |
436 | gd->relocaddr); |
437 | ||
438 | gd->start_addr_sp = gd->relocaddr; | |
439 | ||
1938f4a5 SG |
440 | return 0; |
441 | } | |
442 | ||
443 | /* reserve memory for malloc() area */ | |
444 | static int reserve_malloc(void) | |
445 | { | |
a0ba279a | 446 | gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; |
1938f4a5 | 447 | debug("Reserving %dk for malloc() at: %08lx\n", |
a0ba279a | 448 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
1938f4a5 SG |
449 | return 0; |
450 | } | |
451 | ||
452 | /* (permanently) allocate a Board Info struct */ | |
453 | static int reserve_board(void) | |
454 | { | |
d54d7eb9 SZ |
455 | if (!gd->bd) { |
456 | gd->start_addr_sp -= sizeof(bd_t); | |
457 | gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); | |
458 | memset(gd->bd, '\0', sizeof(bd_t)); | |
459 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", | |
460 | sizeof(bd_t), gd->start_addr_sp); | |
461 | } | |
1938f4a5 SG |
462 | return 0; |
463 | } | |
464 | ||
465 | static int setup_machine(void) | |
466 | { | |
467 | #ifdef CONFIG_MACH_TYPE | |
468 | gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ | |
469 | #endif | |
470 | return 0; | |
471 | } | |
472 | ||
473 | static int reserve_global_data(void) | |
474 | { | |
a0ba279a MY |
475 | gd->start_addr_sp -= sizeof(gd_t); |
476 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); | |
1938f4a5 | 477 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
a0ba279a | 478 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
479 | return 0; |
480 | } | |
481 | ||
482 | static int reserve_fdt(void) | |
483 | { | |
e9acb9ea | 484 | #ifndef CONFIG_OF_EMBED |
1938f4a5 | 485 | /* |
4c509343 | 486 | * If the device tree is sitting immediately above our image then we |
1938f4a5 SG |
487 | * must relocate it. If it is embedded in the data section, then it |
488 | * will be relocated with other data. | |
489 | */ | |
490 | if (gd->fdt_blob) { | |
491 | gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); | |
492 | ||
a0ba279a MY |
493 | gd->start_addr_sp -= gd->fdt_size; |
494 | gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); | |
a733b06b | 495 | debug("Reserving %lu Bytes for FDT at: %08lx\n", |
a0ba279a | 496 | gd->fdt_size, gd->start_addr_sp); |
1938f4a5 | 497 | } |
e9acb9ea | 498 | #endif |
1938f4a5 SG |
499 | |
500 | return 0; | |
501 | } | |
502 | ||
68145d4c | 503 | int arch_reserve_stacks(void) |
1938f4a5 | 504 | { |
68145d4c AB |
505 | return 0; |
506 | } | |
8cae8a68 | 507 | |
68145d4c AB |
508 | static int reserve_stacks(void) |
509 | { | |
510 | /* make stack pointer 16-byte aligned */ | |
a0ba279a MY |
511 | gd->start_addr_sp -= 16; |
512 | gd->start_addr_sp &= ~0xf; | |
1938f4a5 SG |
513 | |
514 | /* | |
4c509343 | 515 | * let the architecture-specific code tailor gd->start_addr_sp and |
68145d4c | 516 | * gd->irq_sp |
1938f4a5 | 517 | */ |
68145d4c | 518 | return arch_reserve_stacks(); |
1938f4a5 SG |
519 | } |
520 | ||
521 | static int display_new_sp(void) | |
522 | { | |
a0ba279a | 523 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
524 | |
525 | return 0; | |
526 | } | |
527 | ||
e2099d78 VZ |
528 | #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ |
529 | defined(CONFIG_SH) | |
e4fef6cf SG |
530 | static int setup_board_part1(void) |
531 | { | |
532 | bd_t *bd = gd->bd; | |
533 | ||
534 | /* | |
535 | * Save local variables to board info struct | |
536 | */ | |
e4fef6cf SG |
537 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ |
538 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
539 | ||
540 | #ifdef CONFIG_SYS_SRAM_BASE | |
541 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
542 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
543 | #endif | |
544 | ||
58dac327 | 545 | #if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ |
e4fef6cf SG |
546 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
547 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ | |
548 | #endif | |
e310b93e | 549 | #if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) |
e4fef6cf SG |
550 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
551 | #endif | |
552 | #if defined(CONFIG_MPC83xx) | |
553 | bd->bi_immrbar = CONFIG_SYS_IMMR; | |
554 | #endif | |
e4fef6cf SG |
555 | |
556 | return 0; | |
557 | } | |
fb3db635 | 558 | #endif |
e4fef6cf | 559 | |
fb3db635 | 560 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
561 | static int setup_board_part2(void) |
562 | { | |
563 | bd_t *bd = gd->bd; | |
564 | ||
565 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ | |
566 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
567 | #if defined(CONFIG_CPM2) | |
568 | bd->bi_cpmfreq = gd->arch.cpm_clk; | |
569 | bd->bi_brgfreq = gd->arch.brg_clk; | |
570 | bd->bi_sccfreq = gd->arch.scc_clk; | |
571 | bd->bi_vco = gd->arch.vco_out; | |
572 | #endif /* CONFIG_CPM2 */ | |
573 | #if defined(CONFIG_MPC512X) | |
574 | bd->bi_ipsfreq = gd->arch.ips_clk; | |
575 | #endif /* CONFIG_MPC512X */ | |
576 | #if defined(CONFIG_MPC5xxx) | |
577 | bd->bi_ipbfreq = gd->arch.ipb_clk; | |
578 | bd->bi_pcifreq = gd->pci_clk; | |
579 | #endif /* CONFIG_MPC5xxx */ | |
1313db48 AW |
580 | #if defined(CONFIG_M68K) && defined(CONFIG_PCI) |
581 | bd->bi_pcifreq = gd->pci_clk; | |
582 | #endif | |
583 | #if defined(CONFIG_EXTRA_CLOCK) | |
584 | bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ | |
585 | bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ | |
586 | bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ | |
587 | #endif | |
e4fef6cf SG |
588 | |
589 | return 0; | |
590 | } | |
591 | #endif | |
592 | ||
1938f4a5 SG |
593 | #ifdef CONFIG_POST |
594 | static int init_post(void) | |
595 | { | |
596 | post_bootmode_init(); | |
597 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
598 | ||
599 | return 0; | |
600 | } | |
601 | #endif | |
602 | ||
1938f4a5 SG |
603 | static int reloc_fdt(void) |
604 | { | |
e9acb9ea | 605 | #ifndef CONFIG_OF_EMBED |
f05ad9ba SG |
606 | if (gd->flags & GD_FLG_SKIP_RELOC) |
607 | return 0; | |
1938f4a5 SG |
608 | if (gd->new_fdt) { |
609 | memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); | |
610 | gd->fdt_blob = gd->new_fdt; | |
611 | } | |
e9acb9ea | 612 | #endif |
1938f4a5 SG |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
617 | static int setup_reloc(void) | |
618 | { | |
f05ad9ba SG |
619 | if (gd->flags & GD_FLG_SKIP_RELOC) { |
620 | debug("Skipping relocation due to flag\n"); | |
621 | return 0; | |
622 | } | |
623 | ||
d54d7eb9 | 624 | #ifdef CONFIG_SYS_TEXT_BASE |
a0ba279a | 625 | gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; |
e310b93e | 626 | #ifdef CONFIG_M68K |
627 | /* | |
628 | * On all ColdFire arch cpu, monitor code starts always | |
629 | * just after the default vector table location, so at 0x400 | |
630 | */ | |
631 | gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); | |
632 | #endif | |
d54d7eb9 | 633 | #endif |
1938f4a5 SG |
634 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
635 | ||
636 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); | |
a733b06b | 637 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", |
a0ba279a MY |
638 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), |
639 | gd->start_addr_sp); | |
1938f4a5 SG |
640 | |
641 | return 0; | |
642 | } | |
643 | ||
2a792753 | 644 | #ifdef CONFIG_OF_BOARD_FIXUP |
645 | static int fix_fdt(void) | |
646 | { | |
647 | return board_fix_fdt((void *)gd->fdt_blob); | |
648 | } | |
649 | #endif | |
650 | ||
1938f4a5 | 651 | /* ARM calls relocate_code from its crt0.S */ |
530f27ea SG |
652 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
653 | !CONFIG_IS_ENABLED(X86_64) | |
1938f4a5 SG |
654 | |
655 | static int jump_to_copy(void) | |
656 | { | |
f05ad9ba SG |
657 | if (gd->flags & GD_FLG_SKIP_RELOC) |
658 | return 0; | |
48a33806 SG |
659 | /* |
660 | * x86 is special, but in a nice way. It uses a trampoline which | |
661 | * enables the dcache if possible. | |
662 | * | |
663 | * For now, other archs use relocate_code(), which is implemented | |
664 | * similarly for all archs. When we do generic relocation, hopefully | |
665 | * we can make all archs enable the dcache prior to relocation. | |
666 | */ | |
3fb80163 | 667 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
668 | /* |
669 | * SDRAM and console are now initialised. The final stack can now | |
670 | * be setup in SDRAM. Code execution will continue in Flash, but | |
671 | * with the stack in SDRAM and Global Data in temporary memory | |
672 | * (CPU cache) | |
673 | */ | |
f0c7d9c7 | 674 | arch_setup_gd(gd->new_gd); |
48a33806 SG |
675 | board_init_f_r_trampoline(gd->start_addr_sp); |
676 | #else | |
a0ba279a | 677 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 678 | #endif |
1938f4a5 SG |
679 | |
680 | return 0; | |
681 | } | |
682 | #endif | |
683 | ||
684 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
685 | static int mark_bootstage(void) | |
686 | { | |
687 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
9854a874 SG |
692 | static int initf_console_record(void) |
693 | { | |
694 | #if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F_LEN) | |
695 | return console_record_init(); | |
696 | #else | |
697 | return 0; | |
698 | #endif | |
699 | } | |
700 | ||
ab7cd627 SG |
701 | static int initf_dm(void) |
702 | { | |
703 | #if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) | |
704 | int ret; | |
705 | ||
706 | ret = dm_init_and_scan(true); | |
707 | if (ret) | |
708 | return ret; | |
709 | #endif | |
1057e6cf SG |
710 | #ifdef CONFIG_TIMER_EARLY |
711 | ret = dm_timer_init(); | |
712 | if (ret) | |
713 | return ret; | |
714 | #endif | |
ab7cd627 SG |
715 | |
716 | return 0; | |
717 | } | |
718 | ||
146251f8 SG |
719 | /* Architecture-specific memory reservation */ |
720 | __weak int reserve_arch(void) | |
721 | { | |
722 | return 0; | |
723 | } | |
724 | ||
d4c671cc SG |
725 | __weak int arch_cpu_init_dm(void) |
726 | { | |
727 | return 0; | |
728 | } | |
729 | ||
4acff452 | 730 | static const init_fnc_t init_sequence_f[] = { |
1938f4a5 | 731 | setup_mon_len, |
b45122fd | 732 | #ifdef CONFIG_OF_CONTROL |
0879361f | 733 | fdtdec_setup, |
b45122fd | 734 | #endif |
d210718d | 735 | #ifdef CONFIG_TRACE |
71c52dba | 736 | trace_early_init, |
d210718d | 737 | #endif |
768e0f52 | 738 | initf_malloc, |
9854a874 | 739 | initf_console_record, |
671549e5 SG |
740 | #if defined(CONFIG_HAVE_FSP) |
741 | arch_fsp_init, | |
e4fef6cf | 742 | #endif |
1938f4a5 | 743 | arch_cpu_init, /* basic arch cpu dependent setup */ |
8ebf5069 | 744 | mach_cpu_init, /* SoC/machine dependent CPU setup */ |
3ea0953d | 745 | initf_dm, |
d4c671cc | 746 | arch_cpu_init_dm, |
67521957 | 747 | mark_bootstage, /* need timer, go after init dm */ |
1938f4a5 SG |
748 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
749 | board_early_init_f, | |
750 | #endif | |
727e94a4 | 751 | #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) |
c252c068 | 752 | /* get CPU and bus clocks according to the environment variable */ |
e4fef6cf | 753 | get_clocks, /* get CPU and bus clocks (etc.) */ |
1793e782 | 754 | #endif |
1938f4a5 | 755 | timer_init, /* initialize timer */ |
e4fef6cf SG |
756 | #if defined(CONFIG_BOARD_POSTCLK_INIT) |
757 | board_postclk_init, | |
1938f4a5 SG |
758 | #endif |
759 | env_init, /* initialize environment */ | |
760 | init_baud_rate, /* initialze baudrate settings */ | |
761 | serial_init, /* serial communications setup */ | |
762 | console_init_f, /* stage 1 init of console */ | |
763 | display_options, /* say that we are here */ | |
764 | display_text_info, /* show debugging info if required */ | |
76d1d02f SG |
765 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ |
766 | defined(CONFIG_X86) | |
e4fef6cf SG |
767 | checkcpu, |
768 | #endif | |
cc664000 | 769 | #if defined(CONFIG_DISPLAY_CPUINFO) |
1938f4a5 | 770 | print_cpuinfo, /* display cpu info (and speed) */ |
cc664000 | 771 | #endif |
1938f4a5 | 772 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
0365ffcc | 773 | show_board_info, |
e4fef6cf SG |
774 | #endif |
775 | INIT_FUNC_WATCHDOG_INIT | |
776 | #if defined(CONFIG_MISC_INIT_F) | |
777 | misc_init_f, | |
778 | #endif | |
779 | INIT_FUNC_WATCHDOG_RESET | |
ea818dbb | 780 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
781 | init_func_i2c, |
782 | #endif | |
783 | #if defined(CONFIG_HARD_SPI) | |
784 | init_func_spi, | |
1938f4a5 SG |
785 | #endif |
786 | announce_dram_init, | |
787 | /* TODO: unify all these dram functions? */ | |
2e88bb28 | 788 | #if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_NDS32) || \ |
e2099d78 VZ |
789 | defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) || \ |
790 | defined(CONFIG_SH) | |
1938f4a5 SG |
791 | dram_init, /* configure available RAM banks */ |
792 | #endif | |
e310b93e | 793 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
794 | init_func_ram, |
795 | #endif | |
796 | #ifdef CONFIG_POST | |
797 | post_init_f, | |
798 | #endif | |
799 | INIT_FUNC_WATCHDOG_RESET | |
800 | #if defined(CONFIG_SYS_DRAM_TEST) | |
801 | testdram, | |
802 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
803 | INIT_FUNC_WATCHDOG_RESET | |
804 | ||
1938f4a5 SG |
805 | #ifdef CONFIG_POST |
806 | init_post, | |
807 | #endif | |
e4fef6cf | 808 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
809 | /* |
810 | * Now that we have DRAM mapped and working, we can | |
811 | * relocate the code and continue running from DRAM. | |
812 | * | |
813 | * Reserve memory at end of RAM for (top down in that order): | |
814 | * - area that won't get touched by U-Boot and Linux (optional) | |
815 | * - kernel log buffer | |
816 | * - protected RAM | |
817 | * - LCD framebuffer | |
818 | * - monitor code | |
819 | * - board info struct | |
820 | */ | |
821 | setup_dest_addr, | |
b56db486 | 822 | #if defined(CONFIG_LOGBUFFER) |
1938f4a5 SG |
823 | reserve_logbuffer, |
824 | #endif | |
825 | #ifdef CONFIG_PRAM | |
826 | reserve_pram, | |
827 | #endif | |
828 | reserve_round_4k, | |
80d4bcd3 | 829 | #ifdef CONFIG_ARM |
1938f4a5 SG |
830 | reserve_mmu, |
831 | #endif | |
5a541945 | 832 | reserve_video, |
8703ef3f | 833 | reserve_trace, |
1938f4a5 SG |
834 | reserve_uboot, |
835 | reserve_malloc, | |
836 | reserve_board, | |
837 | setup_machine, | |
838 | reserve_global_data, | |
839 | reserve_fdt, | |
146251f8 | 840 | reserve_arch, |
1938f4a5 | 841 | reserve_stacks, |
76b00aca | 842 | dram_init_banksize, |
1938f4a5 | 843 | show_dram_config, |
e2099d78 VZ |
844 | #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ |
845 | defined(CONFIG_SH) | |
e4fef6cf | 846 | setup_board_part1, |
fb3db635 DS |
847 | #endif |
848 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) | |
e4fef6cf SG |
849 | INIT_FUNC_WATCHDOG_RESET |
850 | setup_board_part2, | |
851 | #endif | |
1938f4a5 | 852 | display_new_sp, |
e4fef6cf SG |
853 | #ifdef CONFIG_SYS_EXTBDINFO |
854 | setup_board_extra, | |
2a792753 | 855 | #endif |
856 | #ifdef CONFIG_OF_BOARD_FIXUP | |
857 | fix_fdt, | |
e4fef6cf SG |
858 | #endif |
859 | INIT_FUNC_WATCHDOG_RESET | |
1938f4a5 SG |
860 | reloc_fdt, |
861 | setup_reloc, | |
3fb80163 | 862 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
313aef37 | 863 | copy_uboot_to_ram, |
313aef37 | 864 | do_elf_reloc_fixups, |
6bda55a3 | 865 | clear_bss, |
313aef37 | 866 | #endif |
de5e5cea CZ |
867 | #if defined(CONFIG_XTENSA) |
868 | clear_bss, | |
869 | #endif | |
530f27ea SG |
870 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
871 | !CONFIG_IS_ENABLED(X86_64) | |
1938f4a5 SG |
872 | jump_to_copy, |
873 | #endif | |
874 | NULL, | |
875 | }; | |
876 | ||
877 | void board_init_f(ulong boot_flags) | |
878 | { | |
2a1680e3 YS |
879 | #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA |
880 | /* | |
fc0b5948 | 881 | * For some architectures, global data is initialized and used before |
2a1680e3 YS |
882 | * calling this function. The data should be preserved. For others, |
883 | * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack | |
884 | * here to host global data until relocation. | |
885 | */ | |
1938f4a5 SG |
886 | gd_t data; |
887 | ||
888 | gd = &data; | |
889 | ||
cce6be7f DF |
890 | /* |
891 | * Clear global data before it is accessed at debug print | |
892 | * in initcall_run_list. Otherwise the debug print probably | |
fc0b5948 | 893 | * get the wrong value of gd->have_console. |
cce6be7f | 894 | */ |
cce6be7f DF |
895 | zero_global_data(); |
896 | #endif | |
897 | ||
1938f4a5 | 898 | gd->flags = boot_flags; |
9aed5a27 | 899 | gd->have_console = 0; |
1938f4a5 SG |
900 | |
901 | if (initcall_run_list(init_sequence_f)) | |
902 | hang(); | |
903 | ||
9b217498 | 904 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
530f27ea | 905 | !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) |
1938f4a5 SG |
906 | /* NOTREACHED - jump_to_copy() does not return */ |
907 | hang(); | |
908 | #endif | |
909 | } | |
910 | ||
3fb80163 | 911 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
912 | /* |
913 | * For now this code is only used on x86. | |
914 | * | |
915 | * init_sequence_f_r is the list of init functions which are run when | |
916 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
917 | * The following limitations must be considered when implementing an | |
918 | * '_f_r' function: | |
919 | * - 'static' variables are read-only | |
920 | * - Global Data (gd->xxx) is read/write | |
921 | * | |
922 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
923 | * supported). It _should_, if possible, copy global data to RAM and | |
924 | * initialise the CPU caches (to speed up the relocation process) | |
925 | * | |
926 | * NOTE: At present only x86 uses this route, but it is intended that | |
927 | * all archs will move to this when generic relocation is implemented. | |
928 | */ | |
4acff452 | 929 | static const init_fnc_t init_sequence_f_r[] = { |
530f27ea | 930 | #if !CONFIG_IS_ENABLED(X86_64) |
48a33806 | 931 | init_cache_f_r, |
530f27ea | 932 | #endif |
48a33806 SG |
933 | |
934 | NULL, | |
935 | }; | |
936 | ||
937 | void board_init_f_r(void) | |
938 | { | |
939 | if (initcall_run_list(init_sequence_f_r)) | |
940 | hang(); | |
941 | ||
e4d6ab0c SG |
942 | /* |
943 | * The pre-relocation drivers may be using memory that has now gone | |
944 | * away. Mark serial as unavailable - this will fall back to the debug | |
945 | * UART if available. | |
946 | */ | |
947 | gd->flags &= ~GD_FLG_SERIAL_READY; | |
948 | ||
48a33806 SG |
949 | /* |
950 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
951 | * Transfer execution from Flash to RAM by calculating the address | |
952 | * of the in-RAM copy of board_init_r() and calling it | |
953 | */ | |
7bf9f20d | 954 | (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); |
48a33806 SG |
955 | |
956 | /* NOTREACHED - board_init_r() does not return */ | |
957 | hang(); | |
958 | } | |
5bcd19aa | 959 | #endif /* CONFIG_X86 */ |