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Commit | Line | Data |
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1938f4a5 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2002-2006 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Marius Groeger <mgroeger@sysgo.de> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
11 | */ |
12 | ||
13 | #include <common.h> | |
14 | #include <linux/compiler.h> | |
15 | #include <version.h> | |
16 | #include <environment.h> | |
ab7cd627 | 17 | #include <dm.h> |
1938f4a5 | 18 | #include <fdtdec.h> |
f828bf25 | 19 | #include <fs.h> |
e4fef6cf SG |
20 | #if defined(CONFIG_CMD_IDE) |
21 | #include <ide.h> | |
22 | #endif | |
23 | #include <i2c.h> | |
1938f4a5 SG |
24 | #include <initcall.h> |
25 | #include <logbuff.h> | |
fb5cf7f1 | 26 | #include <malloc.h> |
0eb25b61 | 27 | #include <mapmem.h> |
e4fef6cf SG |
28 | |
29 | /* TODO: Can we move these into arch/ headers? */ | |
30 | #ifdef CONFIG_8xx | |
31 | #include <mpc8xx.h> | |
32 | #endif | |
33 | #ifdef CONFIG_5xx | |
34 | #include <mpc5xx.h> | |
35 | #endif | |
36 | #ifdef CONFIG_MPC5xxx | |
37 | #include <mpc5xxx.h> | |
38 | #endif | |
ec3b4820 | 39 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
a76df709 GH |
40 | #include <asm/mp.h> |
41 | #endif | |
e4fef6cf | 42 | |
a733b06b | 43 | #include <os.h> |
1938f4a5 | 44 | #include <post.h> |
e4fef6cf | 45 | #include <spi.h> |
c5d4001a | 46 | #include <status_led.h> |
71c52dba | 47 | #include <trace.h> |
e4fef6cf | 48 | #include <watchdog.h> |
a733b06b | 49 | #include <asm/errno.h> |
1938f4a5 SG |
50 | #include <asm/io.h> |
51 | #include <asm/sections.h> | |
3fb80163 | 52 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
53 | #include <asm/init_helpers.h> |
54 | #include <asm/relocate.h> | |
55 | #endif | |
a733b06b SG |
56 | #ifdef CONFIG_SANDBOX |
57 | #include <asm/state.h> | |
58 | #endif | |
ab7cd627 | 59 | #include <dm/root.h> |
1938f4a5 SG |
60 | #include <linux/compiler.h> |
61 | ||
62 | /* | |
63 | * Pointer to initial global data area | |
64 | * | |
65 | * Here we initialize it if needed. | |
66 | */ | |
67 | #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR | |
68 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
69 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
70 | DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); | |
71 | #else | |
72 | DECLARE_GLOBAL_DATA_PTR; | |
73 | #endif | |
74 | ||
75 | /* | |
4c509343 | 76 | * TODO(sjg@chromium.org): IMO this code should be |
1938f4a5 SG |
77 | * refactored to a single function, something like: |
78 | * | |
79 | * void led_set_state(enum led_colour_t colour, int on); | |
80 | */ | |
81 | /************************************************************************ | |
82 | * Coloured LED functionality | |
83 | ************************************************************************ | |
84 | * May be supplied by boards if desired | |
85 | */ | |
c5d4001a JH |
86 | __weak void coloured_LED_init(void) {} |
87 | __weak void red_led_on(void) {} | |
88 | __weak void red_led_off(void) {} | |
89 | __weak void green_led_on(void) {} | |
90 | __weak void green_led_off(void) {} | |
91 | __weak void yellow_led_on(void) {} | |
92 | __weak void yellow_led_off(void) {} | |
93 | __weak void blue_led_on(void) {} | |
94 | __weak void blue_led_off(void) {} | |
1938f4a5 SG |
95 | |
96 | /* | |
97 | * Why is gd allocated a register? Prior to reloc it might be better to | |
98 | * just pass it around to each function in this file? | |
99 | * | |
100 | * After reloc one could argue that it is hardly used and doesn't need | |
101 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
102 | * global data for all modules, so that post-reloc we can avoid the massive | |
103 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
104 | * a structure... | |
105 | */ | |
106 | ||
107 | /* | |
108 | * Could the CONFIG_SPL_BUILD infection become a flag in gd? | |
109 | */ | |
110 | ||
d54d7eb9 | 111 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) |
e4fef6cf SG |
112 | static int init_func_watchdog_init(void) |
113 | { | |
d54d7eb9 SZ |
114 | # if defined(CONFIG_HW_WATCHDOG) && (defined(CONFIG_BLACKFIN) || \ |
115 | defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ | |
14a380a8 SR |
116 | defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ |
117 | defined(CONFIG_IMX_WATCHDOG)) | |
d54d7eb9 SZ |
118 | hw_watchdog_init(); |
119 | # endif | |
e4fef6cf SG |
120 | puts(" Watchdog enabled\n"); |
121 | WATCHDOG_RESET(); | |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | int init_func_watchdog_reset(void) | |
127 | { | |
128 | WATCHDOG_RESET(); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | #endif /* CONFIG_WATCHDOG */ | |
133 | ||
dd2a6cd0 | 134 | __weak void board_add_ram_info(int use_default) |
e4fef6cf SG |
135 | { |
136 | /* please define platform specific board_add_ram_info() */ | |
137 | } | |
138 | ||
1938f4a5 SG |
139 | static int init_baud_rate(void) |
140 | { | |
141 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); | |
142 | return 0; | |
143 | } | |
144 | ||
145 | static int display_text_info(void) | |
146 | { | |
a733b06b | 147 | #ifndef CONFIG_SANDBOX |
9fdee7d7 | 148 | ulong bss_start, bss_end, text_base; |
1938f4a5 | 149 | |
632efa74 SG |
150 | bss_start = (ulong)&__bss_start; |
151 | bss_end = (ulong)&__bss_end; | |
b60eff31 | 152 | |
d54d7eb9 | 153 | #ifdef CONFIG_SYS_TEXT_BASE |
9fdee7d7 | 154 | text_base = CONFIG_SYS_TEXT_BASE; |
d54d7eb9 | 155 | #else |
9fdee7d7 | 156 | text_base = CONFIG_SYS_MONITOR_BASE; |
d54d7eb9 | 157 | #endif |
9fdee7d7 DS |
158 | |
159 | debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", | |
160 | text_base, bss_start, bss_end); | |
a733b06b | 161 | #endif |
1938f4a5 SG |
162 | |
163 | #ifdef CONFIG_MODEM_SUPPORT | |
164 | debug("Modem Support enabled\n"); | |
165 | #endif | |
166 | #ifdef CONFIG_USE_IRQ | |
167 | debug("IRQ Stack: %08lx\n", IRQ_STACK_START); | |
168 | debug("FIQ Stack: %08lx\n", FIQ_STACK_START); | |
169 | #endif | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | static int announce_dram_init(void) | |
175 | { | |
176 | puts("DRAM: "); | |
177 | return 0; | |
178 | } | |
179 | ||
e310b93e | 180 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
181 | static int init_func_ram(void) |
182 | { | |
183 | #ifdef CONFIG_BOARD_TYPES | |
184 | int board_type = gd->board_type; | |
185 | #else | |
186 | int board_type = 0; /* use dummy arg */ | |
187 | #endif | |
188 | ||
189 | gd->ram_size = initdram(board_type); | |
190 | ||
191 | if (gd->ram_size > 0) | |
192 | return 0; | |
193 | ||
194 | puts("*** failed ***\n"); | |
195 | return 1; | |
196 | } | |
197 | #endif | |
198 | ||
1938f4a5 SG |
199 | static int show_dram_config(void) |
200 | { | |
fa39ffe5 | 201 | unsigned long long size; |
1938f4a5 SG |
202 | |
203 | #ifdef CONFIG_NR_DRAM_BANKS | |
204 | int i; | |
205 | ||
206 | debug("\nRAM Configuration:\n"); | |
207 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
208 | size += gd->bd->bi_dram[i].size; | |
209 | debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); | |
210 | #ifdef DEBUG | |
211 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
212 | #endif | |
213 | } | |
214 | debug("\nDRAM: "); | |
215 | #else | |
216 | size = gd->ram_size; | |
217 | #endif | |
218 | ||
e4fef6cf SG |
219 | print_size(size, ""); |
220 | board_add_ram_info(0); | |
221 | putc('\n'); | |
1938f4a5 SG |
222 | |
223 | return 0; | |
224 | } | |
225 | ||
dd2a6cd0 | 226 | __weak void dram_init_banksize(void) |
1938f4a5 SG |
227 | { |
228 | #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) | |
229 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
230 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
231 | #endif | |
232 | } | |
233 | ||
ea818dbb | 234 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
235 | static int init_func_i2c(void) |
236 | { | |
237 | puts("I2C: "); | |
815a76f2 | 238 | #ifdef CONFIG_SYS_I2C |
239 | i2c_init_all(); | |
240 | #else | |
e4fef6cf | 241 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
815a76f2 | 242 | #endif |
e4fef6cf SG |
243 | puts("ready\n"); |
244 | return 0; | |
245 | } | |
246 | #endif | |
247 | ||
248 | #if defined(CONFIG_HARD_SPI) | |
249 | static int init_func_spi(void) | |
250 | { | |
251 | puts("SPI: "); | |
252 | spi_init(); | |
253 | puts("ready\n"); | |
254 | return 0; | |
255 | } | |
256 | #endif | |
257 | ||
258 | __maybe_unused | |
1938f4a5 SG |
259 | static int zero_global_data(void) |
260 | { | |
261 | memset((void *)gd, '\0', sizeof(gd_t)); | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
266 | static int setup_mon_len(void) | |
267 | { | |
e945f6dc | 268 | #if defined(__ARM__) || defined(__MICROBLAZE__) |
b60eff31 | 269 | gd->mon_len = (ulong)&__bss_end - (ulong)_start; |
a733b06b SG |
270 | #elif defined(CONFIG_SANDBOX) |
271 | gd->mon_len = (ulong)&_end - (ulong)_init; | |
5ff10aa7 | 272 | #elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) |
d54d7eb9 | 273 | gd->mon_len = CONFIG_SYS_MONITOR_LEN; |
632efa74 | 274 | #else |
e4fef6cf SG |
275 | /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ |
276 | gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 277 | #endif |
1938f4a5 SG |
278 | return 0; |
279 | } | |
280 | ||
281 | __weak int arch_cpu_init(void) | |
282 | { | |
283 | return 0; | |
284 | } | |
285 | ||
a733b06b SG |
286 | #ifdef CONFIG_SANDBOX |
287 | static int setup_ram_buf(void) | |
288 | { | |
5c2859cd SG |
289 | struct sandbox_state *state = state_get_current(); |
290 | ||
291 | gd->arch.ram_buf = state->ram_buf; | |
292 | gd->ram_size = state->ram_size; | |
a733b06b SG |
293 | |
294 | return 0; | |
295 | } | |
296 | #endif | |
297 | ||
1938f4a5 SG |
298 | /* Get the top of usable RAM */ |
299 | __weak ulong board_get_usable_ram_top(ulong total_size) | |
300 | { | |
1e4d11a5 SW |
301 | #ifdef CONFIG_SYS_SDRAM_BASE |
302 | /* | |
4c509343 | 303 | * Detect whether we have so much RAM that it goes past the end of our |
1e4d11a5 SW |
304 | * 32-bit address space. If so, clip the usable RAM so it doesn't. |
305 | */ | |
306 | if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) | |
307 | /* | |
308 | * Will wrap back to top of 32-bit space when reservations | |
309 | * are made. | |
310 | */ | |
311 | return 0; | |
312 | #endif | |
1938f4a5 SG |
313 | return gd->ram_top; |
314 | } | |
315 | ||
316 | static int setup_dest_addr(void) | |
317 | { | |
318 | debug("Monitor len: %08lX\n", gd->mon_len); | |
319 | /* | |
320 | * Ram is setup, size stored in gd !! | |
321 | */ | |
322 | debug("Ram size: %08lX\n", (ulong)gd->ram_size); | |
323 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) | |
324 | /* | |
325 | * Subtract specified amount of memory to hide so that it won't | |
326 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
327 | * the Linux kernel should now get passed the now "corrected" | |
328 | * memory size and won't touch it either. This should work | |
329 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
330 | * arch/powerpc with bootwrapper support, that recalculate the | |
331 | * memory size from the SDRAM controller setup will have to | |
332 | * get fixed. | |
333 | */ | |
334 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; | |
335 | #endif | |
336 | #ifdef CONFIG_SYS_SDRAM_BASE | |
337 | gd->ram_top = CONFIG_SYS_SDRAM_BASE; | |
338 | #endif | |
e4fef6cf | 339 | gd->ram_top += get_effective_memsize(); |
1938f4a5 | 340 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 341 | gd->relocaddr = gd->ram_top; |
1938f4a5 | 342 | debug("Ram top: %08lX\n", (ulong)gd->ram_top); |
ec3b4820 | 343 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
e4fef6cf SG |
344 | /* |
345 | * We need to make sure the location we intend to put secondary core | |
346 | * boot code is reserved and not used by any part of u-boot | |
347 | */ | |
a0ba279a MY |
348 | if (gd->relocaddr > determine_mp_bootpg(NULL)) { |
349 | gd->relocaddr = determine_mp_bootpg(NULL); | |
350 | debug("Reserving MP boot page to %08lx\n", gd->relocaddr); | |
e4fef6cf SG |
351 | } |
352 | #endif | |
1938f4a5 SG |
353 | return 0; |
354 | } | |
355 | ||
356 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) | |
357 | static int reserve_logbuffer(void) | |
358 | { | |
359 | /* reserve kernel log buffer */ | |
a0ba279a | 360 | gd->relocaddr -= LOGBUFF_RESERVE; |
1938f4a5 | 361 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
a0ba279a | 362 | gd->relocaddr); |
1938f4a5 SG |
363 | return 0; |
364 | } | |
365 | #endif | |
366 | ||
367 | #ifdef CONFIG_PRAM | |
368 | /* reserve protected RAM */ | |
369 | static int reserve_pram(void) | |
370 | { | |
371 | ulong reg; | |
372 | ||
373 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); | |
a0ba279a | 374 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 375 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 376 | gd->relocaddr); |
1938f4a5 SG |
377 | return 0; |
378 | } | |
379 | #endif /* CONFIG_PRAM */ | |
380 | ||
381 | /* Round memory pointer down to next 4 kB limit */ | |
382 | static int reserve_round_4k(void) | |
383 | { | |
a0ba279a | 384 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
385 | return 0; |
386 | } | |
387 | ||
388 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
389 | defined(CONFIG_ARM) | |
390 | static int reserve_mmu(void) | |
391 | { | |
392 | /* reserve TLB table */ | |
cce6be7f | 393 | gd->arch.tlb_size = PGTABLE_SIZE; |
a0ba279a | 394 | gd->relocaddr -= gd->arch.tlb_size; |
1938f4a5 SG |
395 | |
396 | /* round down to next 64 kB limit */ | |
a0ba279a | 397 | gd->relocaddr &= ~(0x10000 - 1); |
1938f4a5 | 398 | |
a0ba279a | 399 | gd->arch.tlb_addr = gd->relocaddr; |
1938f4a5 SG |
400 | debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, |
401 | gd->arch.tlb_addr + gd->arch.tlb_size); | |
402 | return 0; | |
403 | } | |
404 | #endif | |
405 | ||
406 | #ifdef CONFIG_LCD | |
407 | static int reserve_lcd(void) | |
408 | { | |
409 | #ifdef CONFIG_FB_ADDR | |
410 | gd->fb_base = CONFIG_FB_ADDR; | |
411 | #else | |
412 | /* reserve memory for LCD display (always full pages) */ | |
a0ba279a MY |
413 | gd->relocaddr = lcd_setmem(gd->relocaddr); |
414 | gd->fb_base = gd->relocaddr; | |
1938f4a5 SG |
415 | #endif /* CONFIG_FB_ADDR */ |
416 | return 0; | |
417 | } | |
418 | #endif /* CONFIG_LCD */ | |
419 | ||
71c52dba SG |
420 | static int reserve_trace(void) |
421 | { | |
422 | #ifdef CONFIG_TRACE | |
423 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
424 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
425 | debug("Reserving %dk for trace data at: %08lx\n", | |
426 | CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
427 | #endif | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
d54d7eb9 SZ |
432 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ |
433 | !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ | |
944ab340 | 434 | !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) |
e4fef6cf SG |
435 | static int reserve_video(void) |
436 | { | |
437 | /* reserve memory for video display (always full pages) */ | |
a0ba279a MY |
438 | gd->relocaddr = video_setmem(gd->relocaddr); |
439 | gd->fb_base = gd->relocaddr; | |
e4fef6cf SG |
440 | |
441 | return 0; | |
442 | } | |
443 | #endif | |
444 | ||
1938f4a5 SG |
445 | static int reserve_uboot(void) |
446 | { | |
447 | /* | |
448 | * reserve memory for U-Boot code, data & bss | |
449 | * round down to next 4 kB limit | |
450 | */ | |
a0ba279a MY |
451 | gd->relocaddr -= gd->mon_len; |
452 | gd->relocaddr &= ~(4096 - 1); | |
e4fef6cf SG |
453 | #ifdef CONFIG_E500 |
454 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
a0ba279a | 455 | gd->relocaddr &= ~(65536 - 1); |
e4fef6cf | 456 | #endif |
1938f4a5 SG |
457 | |
458 | debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, | |
a0ba279a MY |
459 | gd->relocaddr); |
460 | ||
461 | gd->start_addr_sp = gd->relocaddr; | |
462 | ||
1938f4a5 SG |
463 | return 0; |
464 | } | |
465 | ||
8cae8a68 | 466 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
467 | /* reserve memory for malloc() area */ |
468 | static int reserve_malloc(void) | |
469 | { | |
a0ba279a | 470 | gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; |
1938f4a5 | 471 | debug("Reserving %dk for malloc() at: %08lx\n", |
a0ba279a | 472 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
1938f4a5 SG |
473 | return 0; |
474 | } | |
475 | ||
476 | /* (permanently) allocate a Board Info struct */ | |
477 | static int reserve_board(void) | |
478 | { | |
d54d7eb9 SZ |
479 | if (!gd->bd) { |
480 | gd->start_addr_sp -= sizeof(bd_t); | |
481 | gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); | |
482 | memset(gd->bd, '\0', sizeof(bd_t)); | |
483 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", | |
484 | sizeof(bd_t), gd->start_addr_sp); | |
485 | } | |
1938f4a5 SG |
486 | return 0; |
487 | } | |
8cae8a68 | 488 | #endif |
1938f4a5 SG |
489 | |
490 | static int setup_machine(void) | |
491 | { | |
492 | #ifdef CONFIG_MACH_TYPE | |
493 | gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ | |
494 | #endif | |
495 | return 0; | |
496 | } | |
497 | ||
498 | static int reserve_global_data(void) | |
499 | { | |
a0ba279a MY |
500 | gd->start_addr_sp -= sizeof(gd_t); |
501 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); | |
1938f4a5 | 502 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
a0ba279a | 503 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
504 | return 0; |
505 | } | |
506 | ||
507 | static int reserve_fdt(void) | |
508 | { | |
509 | /* | |
4c509343 | 510 | * If the device tree is sitting immediately above our image then we |
1938f4a5 SG |
511 | * must relocate it. If it is embedded in the data section, then it |
512 | * will be relocated with other data. | |
513 | */ | |
514 | if (gd->fdt_blob) { | |
515 | gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); | |
516 | ||
a0ba279a MY |
517 | gd->start_addr_sp -= gd->fdt_size; |
518 | gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); | |
a733b06b | 519 | debug("Reserving %lu Bytes for FDT at: %08lx\n", |
a0ba279a | 520 | gd->fdt_size, gd->start_addr_sp); |
1938f4a5 SG |
521 | } |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
68145d4c | 526 | int arch_reserve_stacks(void) |
1938f4a5 | 527 | { |
68145d4c AB |
528 | return 0; |
529 | } | |
8cae8a68 | 530 | |
68145d4c AB |
531 | static int reserve_stacks(void) |
532 | { | |
533 | /* make stack pointer 16-byte aligned */ | |
a0ba279a MY |
534 | gd->start_addr_sp -= 16; |
535 | gd->start_addr_sp &= ~0xf; | |
1938f4a5 SG |
536 | |
537 | /* | |
4c509343 | 538 | * let the architecture-specific code tailor gd->start_addr_sp and |
68145d4c | 539 | * gd->irq_sp |
1938f4a5 | 540 | */ |
68145d4c | 541 | return arch_reserve_stacks(); |
1938f4a5 SG |
542 | } |
543 | ||
544 | static int display_new_sp(void) | |
545 | { | |
a0ba279a | 546 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
547 | |
548 | return 0; | |
549 | } | |
550 | ||
e310b93e | 551 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
552 | static int setup_board_part1(void) |
553 | { | |
554 | bd_t *bd = gd->bd; | |
555 | ||
556 | /* | |
557 | * Save local variables to board info struct | |
558 | */ | |
e4fef6cf SG |
559 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ |
560 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
561 | ||
562 | #ifdef CONFIG_SYS_SRAM_BASE | |
563 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
564 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
565 | #endif | |
566 | ||
58dac327 | 567 | #if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ |
e4fef6cf SG |
568 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
569 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ | |
570 | #endif | |
e310b93e | 571 | #if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) |
e4fef6cf SG |
572 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
573 | #endif | |
574 | #if defined(CONFIG_MPC83xx) | |
575 | bd->bi_immrbar = CONFIG_SYS_IMMR; | |
576 | #endif | |
e4fef6cf SG |
577 | |
578 | return 0; | |
579 | } | |
580 | ||
581 | static int setup_board_part2(void) | |
582 | { | |
583 | bd_t *bd = gd->bd; | |
584 | ||
585 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ | |
586 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
587 | #if defined(CONFIG_CPM2) | |
588 | bd->bi_cpmfreq = gd->arch.cpm_clk; | |
589 | bd->bi_brgfreq = gd->arch.brg_clk; | |
590 | bd->bi_sccfreq = gd->arch.scc_clk; | |
591 | bd->bi_vco = gd->arch.vco_out; | |
592 | #endif /* CONFIG_CPM2 */ | |
593 | #if defined(CONFIG_MPC512X) | |
594 | bd->bi_ipsfreq = gd->arch.ips_clk; | |
595 | #endif /* CONFIG_MPC512X */ | |
596 | #if defined(CONFIG_MPC5xxx) | |
597 | bd->bi_ipbfreq = gd->arch.ipb_clk; | |
598 | bd->bi_pcifreq = gd->pci_clk; | |
599 | #endif /* CONFIG_MPC5xxx */ | |
1313db48 AW |
600 | #if defined(CONFIG_M68K) && defined(CONFIG_PCI) |
601 | bd->bi_pcifreq = gd->pci_clk; | |
602 | #endif | |
603 | #if defined(CONFIG_EXTRA_CLOCK) | |
604 | bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ | |
605 | bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ | |
606 | bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ | |
607 | #endif | |
e4fef6cf SG |
608 | |
609 | return 0; | |
610 | } | |
611 | #endif | |
612 | ||
613 | #ifdef CONFIG_SYS_EXTBDINFO | |
614 | static int setup_board_extra(void) | |
615 | { | |
616 | bd_t *bd = gd->bd; | |
617 | ||
618 | strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); | |
619 | strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, | |
620 | sizeof(bd->bi_r_version)); | |
621 | ||
622 | bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ | |
623 | bd->bi_plb_busfreq = gd->bus_clk; | |
624 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ | |
625 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
626 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
627 | bd->bi_pci_busfreq = get_PCI_freq(); | |
628 | bd->bi_opbfreq = get_OPB_freq(); | |
629 | #elif defined(CONFIG_XILINX_405) | |
630 | bd->bi_pci_busfreq = get_PCI_freq(); | |
631 | #endif | |
632 | ||
633 | return 0; | |
634 | } | |
635 | #endif | |
636 | ||
1938f4a5 SG |
637 | #ifdef CONFIG_POST |
638 | static int init_post(void) | |
639 | { | |
640 | post_bootmode_init(); | |
641 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
642 | ||
643 | return 0; | |
644 | } | |
645 | #endif | |
646 | ||
1938f4a5 SG |
647 | static int setup_dram_config(void) |
648 | { | |
649 | /* Ram is board specific, so move it to board code ... */ | |
650 | dram_init_banksize(); | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
655 | static int reloc_fdt(void) | |
656 | { | |
657 | if (gd->new_fdt) { | |
658 | memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); | |
659 | gd->fdt_blob = gd->new_fdt; | |
660 | } | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
665 | static int setup_reloc(void) | |
666 | { | |
d54d7eb9 | 667 | #ifdef CONFIG_SYS_TEXT_BASE |
a0ba279a | 668 | gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; |
e310b93e | 669 | #ifdef CONFIG_M68K |
670 | /* | |
671 | * On all ColdFire arch cpu, monitor code starts always | |
672 | * just after the default vector table location, so at 0x400 | |
673 | */ | |
674 | gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); | |
675 | #endif | |
d54d7eb9 | 676 | #endif |
1938f4a5 SG |
677 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
678 | ||
679 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); | |
a733b06b | 680 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", |
a0ba279a MY |
681 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), |
682 | gd->start_addr_sp); | |
1938f4a5 SG |
683 | |
684 | return 0; | |
685 | } | |
686 | ||
687 | /* ARM calls relocate_code from its crt0.S */ | |
808434cd | 688 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
689 | |
690 | static int jump_to_copy(void) | |
691 | { | |
48a33806 SG |
692 | /* |
693 | * x86 is special, but in a nice way. It uses a trampoline which | |
694 | * enables the dcache if possible. | |
695 | * | |
696 | * For now, other archs use relocate_code(), which is implemented | |
697 | * similarly for all archs. When we do generic relocation, hopefully | |
698 | * we can make all archs enable the dcache prior to relocation. | |
699 | */ | |
3fb80163 | 700 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
701 | /* |
702 | * SDRAM and console are now initialised. The final stack can now | |
703 | * be setup in SDRAM. Code execution will continue in Flash, but | |
704 | * with the stack in SDRAM and Global Data in temporary memory | |
705 | * (CPU cache) | |
706 | */ | |
707 | board_init_f_r_trampoline(gd->start_addr_sp); | |
708 | #else | |
a0ba279a | 709 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 710 | #endif |
1938f4a5 SG |
711 | |
712 | return 0; | |
713 | } | |
714 | #endif | |
715 | ||
716 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
717 | static int mark_bootstage(void) | |
718 | { | |
719 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
ab7cd627 SG |
724 | static int initf_dm(void) |
725 | { | |
726 | #if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) | |
727 | int ret; | |
728 | ||
729 | ret = dm_init_and_scan(true); | |
730 | if (ret) | |
731 | return ret; | |
732 | #endif | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
146251f8 SG |
737 | /* Architecture-specific memory reservation */ |
738 | __weak int reserve_arch(void) | |
739 | { | |
740 | return 0; | |
741 | } | |
742 | ||
d4c671cc SG |
743 | __weak int arch_cpu_init_dm(void) |
744 | { | |
745 | return 0; | |
746 | } | |
747 | ||
1938f4a5 | 748 | static init_fnc_t init_sequence_f[] = { |
a733b06b SG |
749 | #ifdef CONFIG_SANDBOX |
750 | setup_ram_buf, | |
e4fef6cf | 751 | #endif |
1938f4a5 | 752 | setup_mon_len, |
b45122fd | 753 | #ifdef CONFIG_OF_CONTROL |
0879361f | 754 | fdtdec_setup, |
b45122fd | 755 | #endif |
d210718d | 756 | #ifdef CONFIG_TRACE |
71c52dba | 757 | trace_early_init, |
d210718d | 758 | #endif |
768e0f52 | 759 | initf_malloc, |
e4fef6cf SG |
760 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
761 | /* TODO: can this go into arch_cpu_init()? */ | |
762 | probecpu, | |
763 | #endif | |
1938f4a5 SG |
764 | arch_cpu_init, /* basic arch cpu dependent setup */ |
765 | mark_bootstage, | |
3ea0953d | 766 | initf_dm, |
d4c671cc | 767 | arch_cpu_init_dm, |
1938f4a5 SG |
768 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
769 | board_early_init_f, | |
770 | #endif | |
e4fef6cf SG |
771 | /* TODO: can any of this go into arch_cpu_init()? */ |
772 | #if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT) | |
773 | get_clocks, /* get CPU and bus clocks (etc.) */ | |
774 | #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ | |
775 | && !defined(CONFIG_TQM885D) | |
776 | adjust_sdram_tbs_8xx, | |
777 | #endif | |
778 | /* TODO: can we rename this to timer_init()? */ | |
779 | init_timebase, | |
780 | #endif | |
d54d7eb9 | 781 | #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || defined(CONFIG_BLACKFIN) |
1938f4a5 | 782 | timer_init, /* initialize timer */ |
e4fef6cf | 783 | #endif |
e4fef6cf SG |
784 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
785 | #if !defined(CONFIG_CPM2) | |
786 | dpram_init, | |
787 | #endif | |
788 | #endif | |
789 | #if defined(CONFIG_BOARD_POSTCLK_INIT) | |
790 | board_postclk_init, | |
b8521b74 MY |
791 | #endif |
792 | #ifdef CONFIG_FSL_ESDHC | |
793 | get_clocks, | |
e310b93e | 794 | #endif |
795 | #ifdef CONFIG_M68K | |
796 | get_clocks, | |
1938f4a5 SG |
797 | #endif |
798 | env_init, /* initialize environment */ | |
e4fef6cf SG |
799 | #if defined(CONFIG_8xx_CPUCLK_DEFAULT) |
800 | /* get CPU and bus clocks according to the environment variable */ | |
801 | get_clocks_866, | |
802 | /* adjust sdram refresh rate according to the new clock */ | |
803 | sdram_adjust_866, | |
804 | init_timebase, | |
805 | #endif | |
1938f4a5 SG |
806 | init_baud_rate, /* initialze baudrate settings */ |
807 | serial_init, /* serial communications setup */ | |
808 | console_init_f, /* stage 1 init of console */ | |
a733b06b SG |
809 | #ifdef CONFIG_SANDBOX |
810 | sandbox_early_getopt_check, | |
811 | #endif | |
812 | #ifdef CONFIG_OF_CONTROL | |
813 | fdtdec_prepare_fdt, | |
48a33806 | 814 | #endif |
1938f4a5 SG |
815 | display_options, /* say that we are here */ |
816 | display_text_info, /* show debugging info if required */ | |
58dac327 | 817 | #if defined(CONFIG_MPC8260) |
e4fef6cf SG |
818 | prt_8260_rsr, |
819 | prt_8260_clks, | |
58dac327 | 820 | #endif /* CONFIG_MPC8260 */ |
e4fef6cf SG |
821 | #if defined(CONFIG_MPC83xx) |
822 | prt_83xx_rsr, | |
823 | #endif | |
e310b93e | 824 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
825 | checkcpu, |
826 | #endif | |
1938f4a5 | 827 | print_cpuinfo, /* display cpu info (and speed) */ |
e4fef6cf SG |
828 | #if defined(CONFIG_MPC5xxx) |
829 | prt_mpc5xxx_clks, | |
830 | #endif /* CONFIG_MPC5xxx */ | |
1938f4a5 | 831 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
0365ffcc | 832 | show_board_info, |
e4fef6cf SG |
833 | #endif |
834 | INIT_FUNC_WATCHDOG_INIT | |
835 | #if defined(CONFIG_MISC_INIT_F) | |
836 | misc_init_f, | |
837 | #endif | |
838 | INIT_FUNC_WATCHDOG_RESET | |
ea818dbb | 839 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
840 | init_func_i2c, |
841 | #endif | |
842 | #if defined(CONFIG_HARD_SPI) | |
843 | init_func_spi, | |
1938f4a5 SG |
844 | #endif |
845 | announce_dram_init, | |
846 | /* TODO: unify all these dram functions? */ | |
a752a8b4 | 847 | #if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) |
1938f4a5 SG |
848 | dram_init, /* configure available RAM banks */ |
849 | #endif | |
e310b93e | 850 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
851 | init_func_ram, |
852 | #endif | |
853 | #ifdef CONFIG_POST | |
854 | post_init_f, | |
855 | #endif | |
856 | INIT_FUNC_WATCHDOG_RESET | |
857 | #if defined(CONFIG_SYS_DRAM_TEST) | |
858 | testdram, | |
859 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
860 | INIT_FUNC_WATCHDOG_RESET | |
861 | ||
1938f4a5 SG |
862 | #ifdef CONFIG_POST |
863 | init_post, | |
864 | #endif | |
e4fef6cf | 865 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
866 | /* |
867 | * Now that we have DRAM mapped and working, we can | |
868 | * relocate the code and continue running from DRAM. | |
869 | * | |
870 | * Reserve memory at end of RAM for (top down in that order): | |
871 | * - area that won't get touched by U-Boot and Linux (optional) | |
872 | * - kernel log buffer | |
873 | * - protected RAM | |
874 | * - LCD framebuffer | |
875 | * - monitor code | |
876 | * - board info struct | |
877 | */ | |
878 | setup_dest_addr, | |
5ff10aa7 | 879 | #if defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) |
d54d7eb9 SZ |
880 | /* Blackfin u-boot monitor should be on top of the ram */ |
881 | reserve_uboot, | |
882 | #endif | |
1938f4a5 SG |
883 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) |
884 | reserve_logbuffer, | |
885 | #endif | |
886 | #ifdef CONFIG_PRAM | |
887 | reserve_pram, | |
888 | #endif | |
889 | reserve_round_4k, | |
890 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
891 | defined(CONFIG_ARM) | |
892 | reserve_mmu, | |
893 | #endif | |
894 | #ifdef CONFIG_LCD | |
895 | reserve_lcd, | |
e4fef6cf | 896 | #endif |
71c52dba | 897 | reserve_trace, |
e4fef6cf | 898 | /* TODO: Why the dependency on CONFIG_8xx? */ |
d54d7eb9 SZ |
899 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ |
900 | !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ | |
944ab340 | 901 | !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) |
e4fef6cf | 902 | reserve_video, |
1938f4a5 | 903 | #endif |
5ff10aa7 | 904 | #if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_NIOS2) |
1938f4a5 | 905 | reserve_uboot, |
d54d7eb9 | 906 | #endif |
8cae8a68 | 907 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
908 | reserve_malloc, |
909 | reserve_board, | |
8cae8a68 | 910 | #endif |
1938f4a5 SG |
911 | setup_machine, |
912 | reserve_global_data, | |
913 | reserve_fdt, | |
146251f8 | 914 | reserve_arch, |
1938f4a5 SG |
915 | reserve_stacks, |
916 | setup_dram_config, | |
917 | show_dram_config, | |
e310b93e | 918 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
919 | setup_board_part1, |
920 | INIT_FUNC_WATCHDOG_RESET | |
921 | setup_board_part2, | |
922 | #endif | |
1938f4a5 | 923 | display_new_sp, |
e4fef6cf SG |
924 | #ifdef CONFIG_SYS_EXTBDINFO |
925 | setup_board_extra, | |
926 | #endif | |
927 | INIT_FUNC_WATCHDOG_RESET | |
1938f4a5 SG |
928 | reloc_fdt, |
929 | setup_reloc, | |
3fb80163 | 930 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
313aef37 SG |
931 | copy_uboot_to_ram, |
932 | clear_bss, | |
933 | do_elf_reloc_fixups, | |
934 | #endif | |
808434cd | 935 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
936 | jump_to_copy, |
937 | #endif | |
938 | NULL, | |
939 | }; | |
940 | ||
941 | void board_init_f(ulong boot_flags) | |
942 | { | |
2a1680e3 YS |
943 | #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA |
944 | /* | |
945 | * For some archtectures, global data is initialized and used before | |
946 | * calling this function. The data should be preserved. For others, | |
947 | * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack | |
948 | * here to host global data until relocation. | |
949 | */ | |
1938f4a5 SG |
950 | gd_t data; |
951 | ||
952 | gd = &data; | |
953 | ||
cce6be7f DF |
954 | /* |
955 | * Clear global data before it is accessed at debug print | |
956 | * in initcall_run_list. Otherwise the debug print probably | |
957 | * get the wrong vaule of gd->have_console. | |
958 | */ | |
cce6be7f DF |
959 | zero_global_data(); |
960 | #endif | |
961 | ||
1938f4a5 | 962 | gd->flags = boot_flags; |
9aed5a27 | 963 | gd->have_console = 0; |
1938f4a5 SG |
964 | |
965 | if (initcall_run_list(init_sequence_f)) | |
966 | hang(); | |
967 | ||
808434cd | 968 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
969 | /* NOTREACHED - jump_to_copy() does not return */ |
970 | hang(); | |
971 | #endif | |
972 | } | |
973 | ||
3fb80163 | 974 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
975 | /* |
976 | * For now this code is only used on x86. | |
977 | * | |
978 | * init_sequence_f_r is the list of init functions which are run when | |
979 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
980 | * The following limitations must be considered when implementing an | |
981 | * '_f_r' function: | |
982 | * - 'static' variables are read-only | |
983 | * - Global Data (gd->xxx) is read/write | |
984 | * | |
985 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
986 | * supported). It _should_, if possible, copy global data to RAM and | |
987 | * initialise the CPU caches (to speed up the relocation process) | |
988 | * | |
989 | * NOTE: At present only x86 uses this route, but it is intended that | |
990 | * all archs will move to this when generic relocation is implemented. | |
991 | */ | |
992 | static init_fnc_t init_sequence_f_r[] = { | |
993 | init_cache_f_r, | |
48a33806 SG |
994 | |
995 | NULL, | |
996 | }; | |
997 | ||
998 | void board_init_f_r(void) | |
999 | { | |
1000 | if (initcall_run_list(init_sequence_f_r)) | |
1001 | hang(); | |
1002 | ||
1003 | /* | |
1004 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
1005 | * Transfer execution from Flash to RAM by calculating the address | |
1006 | * of the in-RAM copy of board_init_r() and calling it | |
1007 | */ | |
7bf9f20d | 1008 | (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); |
48a33806 SG |
1009 | |
1010 | /* NOTREACHED - board_init_r() does not return */ | |
1011 | hang(); | |
1012 | } | |
5bcd19aa AB |
1013 | #endif /* CONFIG_X86 */ |
1014 | ||
1015 | #ifndef CONFIG_X86 | |
74d01867 SG |
1016 | ulong board_init_f_mem(ulong top) |
1017 | { | |
1018 | /* Leave space for the stack we are running with now */ | |
1019 | top -= 0x40; | |
1020 | ||
1021 | top -= sizeof(struct global_data); | |
1022 | top = ALIGN(top, 16); | |
1023 | gd = (struct global_data *)top; | |
1024 | memset((void *)gd, '\0', sizeof(*gd)); | |
1025 | ||
1026 | #ifdef CONFIG_SYS_MALLOC_F_LEN | |
1027 | top -= CONFIG_SYS_MALLOC_F_LEN; | |
1028 | gd->malloc_base = top; | |
1029 | #endif | |
1030 | ||
1031 | return top; | |
1032 | } | |
5bcd19aa | 1033 | #endif /* !CONFIG_X86 */ |