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1938f4a5 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2002-2006 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Marius Groeger <mgroeger@sysgo.de> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
11 | */ |
12 | ||
13 | #include <common.h> | |
14 | #include <linux/compiler.h> | |
15 | #include <version.h> | |
16 | #include <environment.h> | |
ab7cd627 | 17 | #include <dm.h> |
1938f4a5 | 18 | #include <fdtdec.h> |
f828bf25 | 19 | #include <fs.h> |
e4fef6cf SG |
20 | #if defined(CONFIG_CMD_IDE) |
21 | #include <ide.h> | |
22 | #endif | |
23 | #include <i2c.h> | |
1938f4a5 SG |
24 | #include <initcall.h> |
25 | #include <logbuff.h> | |
0eb25b61 | 26 | #include <mapmem.h> |
e4fef6cf SG |
27 | |
28 | /* TODO: Can we move these into arch/ headers? */ | |
29 | #ifdef CONFIG_8xx | |
30 | #include <mpc8xx.h> | |
31 | #endif | |
32 | #ifdef CONFIG_5xx | |
33 | #include <mpc5xx.h> | |
34 | #endif | |
35 | #ifdef CONFIG_MPC5xxx | |
36 | #include <mpc5xxx.h> | |
37 | #endif | |
ec3b4820 | 38 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
a76df709 GH |
39 | #include <asm/mp.h> |
40 | #endif | |
e4fef6cf | 41 | |
a733b06b | 42 | #include <os.h> |
1938f4a5 | 43 | #include <post.h> |
e4fef6cf | 44 | #include <spi.h> |
c5d4001a | 45 | #include <status_led.h> |
71c52dba | 46 | #include <trace.h> |
e4fef6cf | 47 | #include <watchdog.h> |
a733b06b | 48 | #include <asm/errno.h> |
1938f4a5 SG |
49 | #include <asm/io.h> |
50 | #include <asm/sections.h> | |
3fb80163 | 51 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
52 | #include <asm/init_helpers.h> |
53 | #include <asm/relocate.h> | |
54 | #endif | |
a733b06b SG |
55 | #ifdef CONFIG_SANDBOX |
56 | #include <asm/state.h> | |
57 | #endif | |
ab7cd627 | 58 | #include <dm/root.h> |
1938f4a5 SG |
59 | #include <linux/compiler.h> |
60 | ||
61 | /* | |
62 | * Pointer to initial global data area | |
63 | * | |
64 | * Here we initialize it if needed. | |
65 | */ | |
66 | #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR | |
67 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
68 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
69 | DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); | |
70 | #else | |
71 | DECLARE_GLOBAL_DATA_PTR; | |
72 | #endif | |
73 | ||
74 | /* | |
75 | * sjg: IMO this code should be | |
76 | * refactored to a single function, something like: | |
77 | * | |
78 | * void led_set_state(enum led_colour_t colour, int on); | |
79 | */ | |
80 | /************************************************************************ | |
81 | * Coloured LED functionality | |
82 | ************************************************************************ | |
83 | * May be supplied by boards if desired | |
84 | */ | |
c5d4001a JH |
85 | __weak void coloured_LED_init(void) {} |
86 | __weak void red_led_on(void) {} | |
87 | __weak void red_led_off(void) {} | |
88 | __weak void green_led_on(void) {} | |
89 | __weak void green_led_off(void) {} | |
90 | __weak void yellow_led_on(void) {} | |
91 | __weak void yellow_led_off(void) {} | |
92 | __weak void blue_led_on(void) {} | |
93 | __weak void blue_led_off(void) {} | |
1938f4a5 SG |
94 | |
95 | /* | |
96 | * Why is gd allocated a register? Prior to reloc it might be better to | |
97 | * just pass it around to each function in this file? | |
98 | * | |
99 | * After reloc one could argue that it is hardly used and doesn't need | |
100 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
101 | * global data for all modules, so that post-reloc we can avoid the massive | |
102 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
103 | * a structure... | |
104 | */ | |
105 | ||
106 | /* | |
107 | * Could the CONFIG_SPL_BUILD infection become a flag in gd? | |
108 | */ | |
109 | ||
d54d7eb9 | 110 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) |
e4fef6cf SG |
111 | static int init_func_watchdog_init(void) |
112 | { | |
d54d7eb9 SZ |
113 | # if defined(CONFIG_HW_WATCHDOG) && (defined(CONFIG_BLACKFIN) || \ |
114 | defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ | |
14a380a8 SR |
115 | defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ |
116 | defined(CONFIG_IMX_WATCHDOG)) | |
d54d7eb9 SZ |
117 | hw_watchdog_init(); |
118 | # endif | |
e4fef6cf SG |
119 | puts(" Watchdog enabled\n"); |
120 | WATCHDOG_RESET(); | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
125 | int init_func_watchdog_reset(void) | |
126 | { | |
127 | WATCHDOG_RESET(); | |
128 | ||
129 | return 0; | |
130 | } | |
131 | #endif /* CONFIG_WATCHDOG */ | |
132 | ||
dd2a6cd0 | 133 | __weak void board_add_ram_info(int use_default) |
e4fef6cf SG |
134 | { |
135 | /* please define platform specific board_add_ram_info() */ | |
136 | } | |
137 | ||
1938f4a5 SG |
138 | static int init_baud_rate(void) |
139 | { | |
140 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); | |
141 | return 0; | |
142 | } | |
143 | ||
144 | static int display_text_info(void) | |
145 | { | |
a733b06b | 146 | #ifndef CONFIG_SANDBOX |
9fdee7d7 | 147 | ulong bss_start, bss_end, text_base; |
1938f4a5 | 148 | |
632efa74 SG |
149 | bss_start = (ulong)&__bss_start; |
150 | bss_end = (ulong)&__bss_end; | |
b60eff31 | 151 | |
d54d7eb9 | 152 | #ifdef CONFIG_SYS_TEXT_BASE |
9fdee7d7 | 153 | text_base = CONFIG_SYS_TEXT_BASE; |
d54d7eb9 | 154 | #else |
9fdee7d7 | 155 | text_base = CONFIG_SYS_MONITOR_BASE; |
d54d7eb9 | 156 | #endif |
9fdee7d7 DS |
157 | |
158 | debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", | |
159 | text_base, bss_start, bss_end); | |
a733b06b | 160 | #endif |
1938f4a5 SG |
161 | |
162 | #ifdef CONFIG_MODEM_SUPPORT | |
163 | debug("Modem Support enabled\n"); | |
164 | #endif | |
165 | #ifdef CONFIG_USE_IRQ | |
166 | debug("IRQ Stack: %08lx\n", IRQ_STACK_START); | |
167 | debug("FIQ Stack: %08lx\n", FIQ_STACK_START); | |
168 | #endif | |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
173 | static int announce_dram_init(void) | |
174 | { | |
175 | puts("DRAM: "); | |
176 | return 0; | |
177 | } | |
178 | ||
e310b93e | 179 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
180 | static int init_func_ram(void) |
181 | { | |
182 | #ifdef CONFIG_BOARD_TYPES | |
183 | int board_type = gd->board_type; | |
184 | #else | |
185 | int board_type = 0; /* use dummy arg */ | |
186 | #endif | |
187 | ||
188 | gd->ram_size = initdram(board_type); | |
189 | ||
190 | if (gd->ram_size > 0) | |
191 | return 0; | |
192 | ||
193 | puts("*** failed ***\n"); | |
194 | return 1; | |
195 | } | |
196 | #endif | |
197 | ||
1938f4a5 SG |
198 | static int show_dram_config(void) |
199 | { | |
fa39ffe5 | 200 | unsigned long long size; |
1938f4a5 SG |
201 | |
202 | #ifdef CONFIG_NR_DRAM_BANKS | |
203 | int i; | |
204 | ||
205 | debug("\nRAM Configuration:\n"); | |
206 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
207 | size += gd->bd->bi_dram[i].size; | |
208 | debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); | |
209 | #ifdef DEBUG | |
210 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
211 | #endif | |
212 | } | |
213 | debug("\nDRAM: "); | |
214 | #else | |
215 | size = gd->ram_size; | |
216 | #endif | |
217 | ||
e4fef6cf SG |
218 | print_size(size, ""); |
219 | board_add_ram_info(0); | |
220 | putc('\n'); | |
1938f4a5 SG |
221 | |
222 | return 0; | |
223 | } | |
224 | ||
dd2a6cd0 | 225 | __weak void dram_init_banksize(void) |
1938f4a5 SG |
226 | { |
227 | #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) | |
228 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
229 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
230 | #endif | |
231 | } | |
232 | ||
ea818dbb | 233 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
234 | static int init_func_i2c(void) |
235 | { | |
236 | puts("I2C: "); | |
815a76f2 | 237 | #ifdef CONFIG_SYS_I2C |
238 | i2c_init_all(); | |
239 | #else | |
e4fef6cf | 240 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
815a76f2 | 241 | #endif |
e4fef6cf SG |
242 | puts("ready\n"); |
243 | return 0; | |
244 | } | |
245 | #endif | |
246 | ||
247 | #if defined(CONFIG_HARD_SPI) | |
248 | static int init_func_spi(void) | |
249 | { | |
250 | puts("SPI: "); | |
251 | spi_init(); | |
252 | puts("ready\n"); | |
253 | return 0; | |
254 | } | |
255 | #endif | |
256 | ||
257 | __maybe_unused | |
1938f4a5 SG |
258 | static int zero_global_data(void) |
259 | { | |
260 | memset((void *)gd, '\0', sizeof(gd_t)); | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static int setup_mon_len(void) | |
266 | { | |
e945f6dc | 267 | #if defined(__ARM__) || defined(__MICROBLAZE__) |
b60eff31 | 268 | gd->mon_len = (ulong)&__bss_end - (ulong)_start; |
a733b06b SG |
269 | #elif defined(CONFIG_SANDBOX) |
270 | gd->mon_len = (ulong)&_end - (ulong)_init; | |
5ff10aa7 | 271 | #elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) |
d54d7eb9 | 272 | gd->mon_len = CONFIG_SYS_MONITOR_LEN; |
632efa74 | 273 | #else |
e4fef6cf SG |
274 | /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ |
275 | gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 276 | #endif |
1938f4a5 SG |
277 | return 0; |
278 | } | |
279 | ||
280 | __weak int arch_cpu_init(void) | |
281 | { | |
282 | return 0; | |
283 | } | |
284 | ||
a733b06b SG |
285 | #ifdef CONFIG_SANDBOX |
286 | static int setup_ram_buf(void) | |
287 | { | |
5c2859cd SG |
288 | struct sandbox_state *state = state_get_current(); |
289 | ||
290 | gd->arch.ram_buf = state->ram_buf; | |
291 | gd->ram_size = state->ram_size; | |
a733b06b SG |
292 | |
293 | return 0; | |
294 | } | |
295 | #endif | |
296 | ||
1938f4a5 SG |
297 | /* Get the top of usable RAM */ |
298 | __weak ulong board_get_usable_ram_top(ulong total_size) | |
299 | { | |
1e4d11a5 SW |
300 | #ifdef CONFIG_SYS_SDRAM_BASE |
301 | /* | |
302 | * Detect whether we have so much RAM it goes past the end of our | |
303 | * 32-bit address space. If so, clip the usable RAM so it doesn't. | |
304 | */ | |
305 | if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) | |
306 | /* | |
307 | * Will wrap back to top of 32-bit space when reservations | |
308 | * are made. | |
309 | */ | |
310 | return 0; | |
311 | #endif | |
1938f4a5 SG |
312 | return gd->ram_top; |
313 | } | |
314 | ||
315 | static int setup_dest_addr(void) | |
316 | { | |
317 | debug("Monitor len: %08lX\n", gd->mon_len); | |
318 | /* | |
319 | * Ram is setup, size stored in gd !! | |
320 | */ | |
321 | debug("Ram size: %08lX\n", (ulong)gd->ram_size); | |
322 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) | |
323 | /* | |
324 | * Subtract specified amount of memory to hide so that it won't | |
325 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
326 | * the Linux kernel should now get passed the now "corrected" | |
327 | * memory size and won't touch it either. This should work | |
328 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
329 | * arch/powerpc with bootwrapper support, that recalculate the | |
330 | * memory size from the SDRAM controller setup will have to | |
331 | * get fixed. | |
332 | */ | |
333 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; | |
334 | #endif | |
335 | #ifdef CONFIG_SYS_SDRAM_BASE | |
336 | gd->ram_top = CONFIG_SYS_SDRAM_BASE; | |
337 | #endif | |
e4fef6cf | 338 | gd->ram_top += get_effective_memsize(); |
1938f4a5 | 339 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 340 | gd->relocaddr = gd->ram_top; |
1938f4a5 | 341 | debug("Ram top: %08lX\n", (ulong)gd->ram_top); |
ec3b4820 | 342 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
e4fef6cf SG |
343 | /* |
344 | * We need to make sure the location we intend to put secondary core | |
345 | * boot code is reserved and not used by any part of u-boot | |
346 | */ | |
a0ba279a MY |
347 | if (gd->relocaddr > determine_mp_bootpg(NULL)) { |
348 | gd->relocaddr = determine_mp_bootpg(NULL); | |
349 | debug("Reserving MP boot page to %08lx\n", gd->relocaddr); | |
e4fef6cf SG |
350 | } |
351 | #endif | |
1938f4a5 SG |
352 | return 0; |
353 | } | |
354 | ||
355 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) | |
356 | static int reserve_logbuffer(void) | |
357 | { | |
358 | /* reserve kernel log buffer */ | |
a0ba279a | 359 | gd->relocaddr -= LOGBUFF_RESERVE; |
1938f4a5 | 360 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
a0ba279a | 361 | gd->relocaddr); |
1938f4a5 SG |
362 | return 0; |
363 | } | |
364 | #endif | |
365 | ||
366 | #ifdef CONFIG_PRAM | |
367 | /* reserve protected RAM */ | |
368 | static int reserve_pram(void) | |
369 | { | |
370 | ulong reg; | |
371 | ||
372 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); | |
a0ba279a | 373 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 374 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 375 | gd->relocaddr); |
1938f4a5 SG |
376 | return 0; |
377 | } | |
378 | #endif /* CONFIG_PRAM */ | |
379 | ||
380 | /* Round memory pointer down to next 4 kB limit */ | |
381 | static int reserve_round_4k(void) | |
382 | { | |
a0ba279a | 383 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
384 | return 0; |
385 | } | |
386 | ||
387 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
388 | defined(CONFIG_ARM) | |
389 | static int reserve_mmu(void) | |
390 | { | |
391 | /* reserve TLB table */ | |
cce6be7f | 392 | gd->arch.tlb_size = PGTABLE_SIZE; |
a0ba279a | 393 | gd->relocaddr -= gd->arch.tlb_size; |
1938f4a5 SG |
394 | |
395 | /* round down to next 64 kB limit */ | |
a0ba279a | 396 | gd->relocaddr &= ~(0x10000 - 1); |
1938f4a5 | 397 | |
a0ba279a | 398 | gd->arch.tlb_addr = gd->relocaddr; |
1938f4a5 SG |
399 | debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, |
400 | gd->arch.tlb_addr + gd->arch.tlb_size); | |
401 | return 0; | |
402 | } | |
403 | #endif | |
404 | ||
405 | #ifdef CONFIG_LCD | |
406 | static int reserve_lcd(void) | |
407 | { | |
408 | #ifdef CONFIG_FB_ADDR | |
409 | gd->fb_base = CONFIG_FB_ADDR; | |
410 | #else | |
411 | /* reserve memory for LCD display (always full pages) */ | |
a0ba279a MY |
412 | gd->relocaddr = lcd_setmem(gd->relocaddr); |
413 | gd->fb_base = gd->relocaddr; | |
1938f4a5 SG |
414 | #endif /* CONFIG_FB_ADDR */ |
415 | return 0; | |
416 | } | |
417 | #endif /* CONFIG_LCD */ | |
418 | ||
71c52dba SG |
419 | static int reserve_trace(void) |
420 | { | |
421 | #ifdef CONFIG_TRACE | |
422 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
423 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
424 | debug("Reserving %dk for trace data at: %08lx\n", | |
425 | CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
426 | #endif | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
d54d7eb9 SZ |
431 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ |
432 | !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ | |
944ab340 | 433 | !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) |
e4fef6cf SG |
434 | static int reserve_video(void) |
435 | { | |
436 | /* reserve memory for video display (always full pages) */ | |
a0ba279a MY |
437 | gd->relocaddr = video_setmem(gd->relocaddr); |
438 | gd->fb_base = gd->relocaddr; | |
e4fef6cf SG |
439 | |
440 | return 0; | |
441 | } | |
442 | #endif | |
443 | ||
1938f4a5 SG |
444 | static int reserve_uboot(void) |
445 | { | |
446 | /* | |
447 | * reserve memory for U-Boot code, data & bss | |
448 | * round down to next 4 kB limit | |
449 | */ | |
a0ba279a MY |
450 | gd->relocaddr -= gd->mon_len; |
451 | gd->relocaddr &= ~(4096 - 1); | |
e4fef6cf SG |
452 | #ifdef CONFIG_E500 |
453 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
a0ba279a | 454 | gd->relocaddr &= ~(65536 - 1); |
e4fef6cf | 455 | #endif |
1938f4a5 SG |
456 | |
457 | debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, | |
a0ba279a MY |
458 | gd->relocaddr); |
459 | ||
460 | gd->start_addr_sp = gd->relocaddr; | |
461 | ||
1938f4a5 SG |
462 | return 0; |
463 | } | |
464 | ||
8cae8a68 | 465 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
466 | /* reserve memory for malloc() area */ |
467 | static int reserve_malloc(void) | |
468 | { | |
a0ba279a | 469 | gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; |
1938f4a5 | 470 | debug("Reserving %dk for malloc() at: %08lx\n", |
a0ba279a | 471 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
1938f4a5 SG |
472 | return 0; |
473 | } | |
474 | ||
475 | /* (permanently) allocate a Board Info struct */ | |
476 | static int reserve_board(void) | |
477 | { | |
d54d7eb9 SZ |
478 | if (!gd->bd) { |
479 | gd->start_addr_sp -= sizeof(bd_t); | |
480 | gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); | |
481 | memset(gd->bd, '\0', sizeof(bd_t)); | |
482 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", | |
483 | sizeof(bd_t), gd->start_addr_sp); | |
484 | } | |
1938f4a5 SG |
485 | return 0; |
486 | } | |
8cae8a68 | 487 | #endif |
1938f4a5 SG |
488 | |
489 | static int setup_machine(void) | |
490 | { | |
491 | #ifdef CONFIG_MACH_TYPE | |
492 | gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ | |
493 | #endif | |
494 | return 0; | |
495 | } | |
496 | ||
497 | static int reserve_global_data(void) | |
498 | { | |
a0ba279a MY |
499 | gd->start_addr_sp -= sizeof(gd_t); |
500 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); | |
1938f4a5 | 501 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
a0ba279a | 502 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
503 | return 0; |
504 | } | |
505 | ||
506 | static int reserve_fdt(void) | |
507 | { | |
508 | /* | |
509 | * If the device tree is sitting immediate above our image then we | |
510 | * must relocate it. If it is embedded in the data section, then it | |
511 | * will be relocated with other data. | |
512 | */ | |
513 | if (gd->fdt_blob) { | |
514 | gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); | |
515 | ||
a0ba279a MY |
516 | gd->start_addr_sp -= gd->fdt_size; |
517 | gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); | |
a733b06b | 518 | debug("Reserving %lu Bytes for FDT at: %08lx\n", |
a0ba279a | 519 | gd->fdt_size, gd->start_addr_sp); |
1938f4a5 SG |
520 | } |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
68145d4c | 525 | int arch_reserve_stacks(void) |
1938f4a5 | 526 | { |
68145d4c AB |
527 | return 0; |
528 | } | |
8cae8a68 | 529 | |
68145d4c AB |
530 | static int reserve_stacks(void) |
531 | { | |
532 | /* make stack pointer 16-byte aligned */ | |
a0ba279a MY |
533 | gd->start_addr_sp -= 16; |
534 | gd->start_addr_sp &= ~0xf; | |
1938f4a5 SG |
535 | |
536 | /* | |
68145d4c AB |
537 | * let the architecture specific code tailor gd->start_addr_sp and |
538 | * gd->irq_sp | |
1938f4a5 | 539 | */ |
68145d4c | 540 | return arch_reserve_stacks(); |
1938f4a5 SG |
541 | } |
542 | ||
543 | static int display_new_sp(void) | |
544 | { | |
a0ba279a | 545 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
546 | |
547 | return 0; | |
548 | } | |
549 | ||
e310b93e | 550 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
551 | static int setup_board_part1(void) |
552 | { | |
553 | bd_t *bd = gd->bd; | |
554 | ||
555 | /* | |
556 | * Save local variables to board info struct | |
557 | */ | |
558 | ||
559 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ | |
560 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
561 | ||
562 | #ifdef CONFIG_SYS_SRAM_BASE | |
563 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
564 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
565 | #endif | |
566 | ||
58dac327 | 567 | #if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ |
e4fef6cf SG |
568 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
569 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ | |
570 | #endif | |
e310b93e | 571 | #if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) |
e4fef6cf SG |
572 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
573 | #endif | |
574 | #if defined(CONFIG_MPC83xx) | |
575 | bd->bi_immrbar = CONFIG_SYS_IMMR; | |
576 | #endif | |
e4fef6cf SG |
577 | |
578 | return 0; | |
579 | } | |
580 | ||
581 | static int setup_board_part2(void) | |
582 | { | |
583 | bd_t *bd = gd->bd; | |
584 | ||
585 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ | |
586 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
587 | #if defined(CONFIG_CPM2) | |
588 | bd->bi_cpmfreq = gd->arch.cpm_clk; | |
589 | bd->bi_brgfreq = gd->arch.brg_clk; | |
590 | bd->bi_sccfreq = gd->arch.scc_clk; | |
591 | bd->bi_vco = gd->arch.vco_out; | |
592 | #endif /* CONFIG_CPM2 */ | |
593 | #if defined(CONFIG_MPC512X) | |
594 | bd->bi_ipsfreq = gd->arch.ips_clk; | |
595 | #endif /* CONFIG_MPC512X */ | |
596 | #if defined(CONFIG_MPC5xxx) | |
597 | bd->bi_ipbfreq = gd->arch.ipb_clk; | |
598 | bd->bi_pcifreq = gd->pci_clk; | |
599 | #endif /* CONFIG_MPC5xxx */ | |
1313db48 AW |
600 | #if defined(CONFIG_M68K) && defined(CONFIG_PCI) |
601 | bd->bi_pcifreq = gd->pci_clk; | |
602 | #endif | |
603 | #if defined(CONFIG_EXTRA_CLOCK) | |
604 | bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ | |
605 | bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ | |
606 | bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ | |
607 | #endif | |
e4fef6cf SG |
608 | |
609 | return 0; | |
610 | } | |
611 | #endif | |
612 | ||
613 | #ifdef CONFIG_SYS_EXTBDINFO | |
614 | static int setup_board_extra(void) | |
615 | { | |
616 | bd_t *bd = gd->bd; | |
617 | ||
618 | strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); | |
619 | strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, | |
620 | sizeof(bd->bi_r_version)); | |
621 | ||
622 | bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ | |
623 | bd->bi_plb_busfreq = gd->bus_clk; | |
624 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ | |
625 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
626 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
627 | bd->bi_pci_busfreq = get_PCI_freq(); | |
628 | bd->bi_opbfreq = get_OPB_freq(); | |
629 | #elif defined(CONFIG_XILINX_405) | |
630 | bd->bi_pci_busfreq = get_PCI_freq(); | |
631 | #endif | |
632 | ||
633 | return 0; | |
634 | } | |
635 | #endif | |
636 | ||
1938f4a5 SG |
637 | #ifdef CONFIG_POST |
638 | static int init_post(void) | |
639 | { | |
640 | post_bootmode_init(); | |
641 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
642 | ||
643 | return 0; | |
644 | } | |
645 | #endif | |
646 | ||
1938f4a5 SG |
647 | static int setup_dram_config(void) |
648 | { | |
649 | /* Ram is board specific, so move it to board code ... */ | |
650 | dram_init_banksize(); | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
655 | static int reloc_fdt(void) | |
656 | { | |
657 | if (gd->new_fdt) { | |
658 | memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); | |
659 | gd->fdt_blob = gd->new_fdt; | |
660 | } | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
665 | static int setup_reloc(void) | |
666 | { | |
d54d7eb9 | 667 | #ifdef CONFIG_SYS_TEXT_BASE |
a0ba279a | 668 | gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; |
e310b93e | 669 | #ifdef CONFIG_M68K |
670 | /* | |
671 | * On all ColdFire arch cpu, monitor code starts always | |
672 | * just after the default vector table location, so at 0x400 | |
673 | */ | |
674 | gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); | |
675 | #endif | |
d54d7eb9 | 676 | #endif |
1938f4a5 SG |
677 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
678 | ||
679 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); | |
a733b06b | 680 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", |
a0ba279a MY |
681 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), |
682 | gd->start_addr_sp); | |
1938f4a5 SG |
683 | |
684 | return 0; | |
685 | } | |
686 | ||
687 | /* ARM calls relocate_code from its crt0.S */ | |
808434cd | 688 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
689 | |
690 | static int jump_to_copy(void) | |
691 | { | |
48a33806 SG |
692 | /* |
693 | * x86 is special, but in a nice way. It uses a trampoline which | |
694 | * enables the dcache if possible. | |
695 | * | |
696 | * For now, other archs use relocate_code(), which is implemented | |
697 | * similarly for all archs. When we do generic relocation, hopefully | |
698 | * we can make all archs enable the dcache prior to relocation. | |
699 | */ | |
3fb80163 | 700 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
701 | /* |
702 | * SDRAM and console are now initialised. The final stack can now | |
703 | * be setup in SDRAM. Code execution will continue in Flash, but | |
704 | * with the stack in SDRAM and Global Data in temporary memory | |
705 | * (CPU cache) | |
706 | */ | |
707 | board_init_f_r_trampoline(gd->start_addr_sp); | |
708 | #else | |
a0ba279a | 709 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 710 | #endif |
1938f4a5 SG |
711 | |
712 | return 0; | |
713 | } | |
714 | #endif | |
715 | ||
716 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
717 | static int mark_bootstage(void) | |
718 | { | |
719 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
d59476b6 SG |
724 | static int initf_malloc(void) |
725 | { | |
726 | #ifdef CONFIG_SYS_MALLOC_F_LEN | |
727 | assert(gd->malloc_base); /* Set up by crt0.S */ | |
728 | gd->malloc_limit = gd->malloc_base + CONFIG_SYS_MALLOC_F_LEN; | |
729 | gd->malloc_ptr = 0; | |
730 | #endif | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
ab7cd627 SG |
735 | static int initf_dm(void) |
736 | { | |
737 | #if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) | |
738 | int ret; | |
739 | ||
740 | ret = dm_init_and_scan(true); | |
741 | if (ret) | |
742 | return ret; | |
743 | #endif | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
146251f8 SG |
748 | /* Architecture-specific memory reservation */ |
749 | __weak int reserve_arch(void) | |
750 | { | |
751 | return 0; | |
752 | } | |
753 | ||
d4c671cc SG |
754 | __weak int arch_cpu_init_dm(void) |
755 | { | |
756 | return 0; | |
757 | } | |
758 | ||
1938f4a5 | 759 | static init_fnc_t init_sequence_f[] = { |
a733b06b SG |
760 | #ifdef CONFIG_SANDBOX |
761 | setup_ram_buf, | |
e4fef6cf | 762 | #endif |
1938f4a5 | 763 | setup_mon_len, |
b45122fd | 764 | #ifdef CONFIG_OF_CONTROL |
71c52dba | 765 | setup_fdt, |
b45122fd | 766 | #endif |
d210718d | 767 | #ifdef CONFIG_TRACE |
71c52dba | 768 | trace_early_init, |
d210718d | 769 | #endif |
768e0f52 | 770 | initf_malloc, |
e4fef6cf SG |
771 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
772 | /* TODO: can this go into arch_cpu_init()? */ | |
773 | probecpu, | |
774 | #endif | |
1938f4a5 SG |
775 | arch_cpu_init, /* basic arch cpu dependent setup */ |
776 | mark_bootstage, | |
777 | #ifdef CONFIG_OF_CONTROL | |
778 | fdtdec_check_fdt, | |
779 | #endif | |
3ea0953d | 780 | initf_dm, |
d4c671cc | 781 | arch_cpu_init_dm, |
1938f4a5 SG |
782 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
783 | board_early_init_f, | |
784 | #endif | |
e4fef6cf SG |
785 | /* TODO: can any of this go into arch_cpu_init()? */ |
786 | #if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT) | |
787 | get_clocks, /* get CPU and bus clocks (etc.) */ | |
788 | #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ | |
789 | && !defined(CONFIG_TQM885D) | |
790 | adjust_sdram_tbs_8xx, | |
791 | #endif | |
792 | /* TODO: can we rename this to timer_init()? */ | |
793 | init_timebase, | |
794 | #endif | |
d54d7eb9 | 795 | #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || defined(CONFIG_BLACKFIN) |
1938f4a5 | 796 | timer_init, /* initialize timer */ |
e4fef6cf | 797 | #endif |
e4fef6cf SG |
798 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
799 | #if !defined(CONFIG_CPM2) | |
800 | dpram_init, | |
801 | #endif | |
802 | #endif | |
803 | #if defined(CONFIG_BOARD_POSTCLK_INIT) | |
804 | board_postclk_init, | |
b8521b74 MY |
805 | #endif |
806 | #ifdef CONFIG_FSL_ESDHC | |
807 | get_clocks, | |
e310b93e | 808 | #endif |
809 | #ifdef CONFIG_M68K | |
810 | get_clocks, | |
1938f4a5 SG |
811 | #endif |
812 | env_init, /* initialize environment */ | |
e4fef6cf SG |
813 | #if defined(CONFIG_8xx_CPUCLK_DEFAULT) |
814 | /* get CPU and bus clocks according to the environment variable */ | |
815 | get_clocks_866, | |
816 | /* adjust sdram refresh rate according to the new clock */ | |
817 | sdram_adjust_866, | |
818 | init_timebase, | |
819 | #endif | |
1938f4a5 SG |
820 | init_baud_rate, /* initialze baudrate settings */ |
821 | serial_init, /* serial communications setup */ | |
822 | console_init_f, /* stage 1 init of console */ | |
a733b06b SG |
823 | #ifdef CONFIG_SANDBOX |
824 | sandbox_early_getopt_check, | |
825 | #endif | |
826 | #ifdef CONFIG_OF_CONTROL | |
827 | fdtdec_prepare_fdt, | |
48a33806 | 828 | #endif |
1938f4a5 SG |
829 | display_options, /* say that we are here */ |
830 | display_text_info, /* show debugging info if required */ | |
58dac327 | 831 | #if defined(CONFIG_MPC8260) |
e4fef6cf SG |
832 | prt_8260_rsr, |
833 | prt_8260_clks, | |
58dac327 | 834 | #endif /* CONFIG_MPC8260 */ |
e4fef6cf SG |
835 | #if defined(CONFIG_MPC83xx) |
836 | prt_83xx_rsr, | |
837 | #endif | |
e310b93e | 838 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
839 | checkcpu, |
840 | #endif | |
1938f4a5 | 841 | print_cpuinfo, /* display cpu info (and speed) */ |
e4fef6cf SG |
842 | #if defined(CONFIG_MPC5xxx) |
843 | prt_mpc5xxx_clks, | |
844 | #endif /* CONFIG_MPC5xxx */ | |
1938f4a5 | 845 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
0365ffcc | 846 | show_board_info, |
e4fef6cf SG |
847 | #endif |
848 | INIT_FUNC_WATCHDOG_INIT | |
849 | #if defined(CONFIG_MISC_INIT_F) | |
850 | misc_init_f, | |
851 | #endif | |
852 | INIT_FUNC_WATCHDOG_RESET | |
ea818dbb | 853 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
854 | init_func_i2c, |
855 | #endif | |
856 | #if defined(CONFIG_HARD_SPI) | |
857 | init_func_spi, | |
1938f4a5 SG |
858 | #endif |
859 | announce_dram_init, | |
860 | /* TODO: unify all these dram functions? */ | |
a752a8b4 | 861 | #if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) |
1938f4a5 SG |
862 | dram_init, /* configure available RAM banks */ |
863 | #endif | |
e310b93e | 864 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
865 | init_func_ram, |
866 | #endif | |
867 | #ifdef CONFIG_POST | |
868 | post_init_f, | |
869 | #endif | |
870 | INIT_FUNC_WATCHDOG_RESET | |
871 | #if defined(CONFIG_SYS_DRAM_TEST) | |
872 | testdram, | |
873 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
874 | INIT_FUNC_WATCHDOG_RESET | |
875 | ||
1938f4a5 SG |
876 | #ifdef CONFIG_POST |
877 | init_post, | |
878 | #endif | |
e4fef6cf | 879 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
880 | /* |
881 | * Now that we have DRAM mapped and working, we can | |
882 | * relocate the code and continue running from DRAM. | |
883 | * | |
884 | * Reserve memory at end of RAM for (top down in that order): | |
885 | * - area that won't get touched by U-Boot and Linux (optional) | |
886 | * - kernel log buffer | |
887 | * - protected RAM | |
888 | * - LCD framebuffer | |
889 | * - monitor code | |
890 | * - board info struct | |
891 | */ | |
892 | setup_dest_addr, | |
5ff10aa7 | 893 | #if defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) |
d54d7eb9 SZ |
894 | /* Blackfin u-boot monitor should be on top of the ram */ |
895 | reserve_uboot, | |
896 | #endif | |
1938f4a5 SG |
897 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) |
898 | reserve_logbuffer, | |
899 | #endif | |
900 | #ifdef CONFIG_PRAM | |
901 | reserve_pram, | |
902 | #endif | |
903 | reserve_round_4k, | |
904 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
905 | defined(CONFIG_ARM) | |
906 | reserve_mmu, | |
907 | #endif | |
908 | #ifdef CONFIG_LCD | |
909 | reserve_lcd, | |
e4fef6cf | 910 | #endif |
71c52dba | 911 | reserve_trace, |
e4fef6cf | 912 | /* TODO: Why the dependency on CONFIG_8xx? */ |
d54d7eb9 SZ |
913 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ |
914 | !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ | |
944ab340 | 915 | !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) |
e4fef6cf | 916 | reserve_video, |
1938f4a5 | 917 | #endif |
5ff10aa7 | 918 | #if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_NIOS2) |
1938f4a5 | 919 | reserve_uboot, |
d54d7eb9 | 920 | #endif |
8cae8a68 | 921 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
922 | reserve_malloc, |
923 | reserve_board, | |
8cae8a68 | 924 | #endif |
1938f4a5 SG |
925 | setup_machine, |
926 | reserve_global_data, | |
927 | reserve_fdt, | |
146251f8 | 928 | reserve_arch, |
1938f4a5 SG |
929 | reserve_stacks, |
930 | setup_dram_config, | |
931 | show_dram_config, | |
e310b93e | 932 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
933 | setup_board_part1, |
934 | INIT_FUNC_WATCHDOG_RESET | |
935 | setup_board_part2, | |
936 | #endif | |
1938f4a5 | 937 | display_new_sp, |
e4fef6cf SG |
938 | #ifdef CONFIG_SYS_EXTBDINFO |
939 | setup_board_extra, | |
940 | #endif | |
941 | INIT_FUNC_WATCHDOG_RESET | |
1938f4a5 SG |
942 | reloc_fdt, |
943 | setup_reloc, | |
3fb80163 | 944 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
313aef37 SG |
945 | copy_uboot_to_ram, |
946 | clear_bss, | |
947 | do_elf_reloc_fixups, | |
948 | #endif | |
808434cd | 949 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
950 | jump_to_copy, |
951 | #endif | |
952 | NULL, | |
953 | }; | |
954 | ||
955 | void board_init_f(ulong boot_flags) | |
956 | { | |
2a1680e3 YS |
957 | #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA |
958 | /* | |
959 | * For some archtectures, global data is initialized and used before | |
960 | * calling this function. The data should be preserved. For others, | |
961 | * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack | |
962 | * here to host global data until relocation. | |
963 | */ | |
1938f4a5 SG |
964 | gd_t data; |
965 | ||
966 | gd = &data; | |
967 | ||
cce6be7f DF |
968 | /* |
969 | * Clear global data before it is accessed at debug print | |
970 | * in initcall_run_list. Otherwise the debug print probably | |
971 | * get the wrong vaule of gd->have_console. | |
972 | */ | |
cce6be7f DF |
973 | zero_global_data(); |
974 | #endif | |
975 | ||
1938f4a5 | 976 | gd->flags = boot_flags; |
9aed5a27 | 977 | gd->have_console = 0; |
1938f4a5 SG |
978 | |
979 | if (initcall_run_list(init_sequence_f)) | |
980 | hang(); | |
981 | ||
808434cd | 982 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
983 | /* NOTREACHED - jump_to_copy() does not return */ |
984 | hang(); | |
985 | #endif | |
986 | } | |
987 | ||
3fb80163 | 988 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
989 | /* |
990 | * For now this code is only used on x86. | |
991 | * | |
992 | * init_sequence_f_r is the list of init functions which are run when | |
993 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
994 | * The following limitations must be considered when implementing an | |
995 | * '_f_r' function: | |
996 | * - 'static' variables are read-only | |
997 | * - Global Data (gd->xxx) is read/write | |
998 | * | |
999 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
1000 | * supported). It _should_, if possible, copy global data to RAM and | |
1001 | * initialise the CPU caches (to speed up the relocation process) | |
1002 | * | |
1003 | * NOTE: At present only x86 uses this route, but it is intended that | |
1004 | * all archs will move to this when generic relocation is implemented. | |
1005 | */ | |
1006 | static init_fnc_t init_sequence_f_r[] = { | |
1007 | init_cache_f_r, | |
48a33806 SG |
1008 | |
1009 | NULL, | |
1010 | }; | |
1011 | ||
1012 | void board_init_f_r(void) | |
1013 | { | |
1014 | if (initcall_run_list(init_sequence_f_r)) | |
1015 | hang(); | |
1016 | ||
1017 | /* | |
1018 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
1019 | * Transfer execution from Flash to RAM by calculating the address | |
1020 | * of the in-RAM copy of board_init_r() and calling it | |
1021 | */ | |
7bf9f20d | 1022 | (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); |
48a33806 SG |
1023 | |
1024 | /* NOTREACHED - board_init_r() does not return */ | |
1025 | hang(); | |
1026 | } | |
5bcd19aa AB |
1027 | #endif /* CONFIG_X86 */ |
1028 | ||
1029 | #ifndef CONFIG_X86 | |
74d01867 SG |
1030 | ulong board_init_f_mem(ulong top) |
1031 | { | |
1032 | /* Leave space for the stack we are running with now */ | |
1033 | top -= 0x40; | |
1034 | ||
1035 | top -= sizeof(struct global_data); | |
1036 | top = ALIGN(top, 16); | |
1037 | gd = (struct global_data *)top; | |
1038 | memset((void *)gd, '\0', sizeof(*gd)); | |
1039 | ||
1040 | #ifdef CONFIG_SYS_MALLOC_F_LEN | |
1041 | top -= CONFIG_SYS_MALLOC_F_LEN; | |
1042 | gd->malloc_base = top; | |
1043 | #endif | |
1044 | ||
1045 | return top; | |
1046 | } | |
5bcd19aa | 1047 | #endif /* !CONFIG_X86 */ |