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Commit | Line | Data |
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1cb8e980 | 1 | /* |
531716e1 | 2 | * (C) Copyright 2002, 2003 |
1cb8e980 WD |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
792a09eb | 5 | * Gary Jennejohn <garyj@denx.de> |
1cb8e980 WD |
6 | * David Mueller <d.mueller@elsoft.ch> |
7 | * | |
8 | * Configuation settings for the MPL VCMA9 board. | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1cb8e980 WD |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
c686537f DMEA |
16 | |
17 | #define MACH_TYPE_MPL_VCMA9 227 | |
18 | ||
1cb8e980 WD |
19 | /* |
20 | * High Level Configuration Options | |
21 | * (easy to change) | |
22 | */ | |
f2168440 | 23 | #define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ |
f3108304 DMEA |
24 | #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ |
25 | #define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ | |
c686537f | 26 | #define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */ |
1cb8e980 | 27 | |
0bf42fec DMEA |
28 | #define CONFIG_SYS_TEXT_BASE 0x0 |
29 | ||
13bd4d87 DMEA |
30 | #define CONFIG_SYS_GENERIC_BOARD |
31 | ||
f3108304 | 32 | #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH |
1cb8e980 | 33 | |
f3108304 DMEA |
34 | /* input clock of PLL (VCMA9 has 12MHz input clock) */ |
35 | #define CONFIG_SYS_CLK_FREQ 12000000 | |
1cb8e980 | 36 | |
f3108304 DMEA |
37 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
38 | #define CONFIG_SETUP_MEMORY_TAGS | |
39 | #define CONFIG_INITRD_TAG | |
a5562901 | 40 | |
a1aa0bb5 JL |
41 | /* |
42 | * BOOTP options | |
43 | */ | |
44 | #define CONFIG_BOOTP_BOOTFILESIZE | |
45 | #define CONFIG_BOOTP_BOOTPATH | |
46 | #define CONFIG_BOOTP_GATEWAY | |
47 | #define CONFIG_BOOTP_HOSTNAME | |
48 | ||
a5562901 JL |
49 | /* |
50 | * Command line configuration. | |
51 | */ | |
52 | #include <config_cmd_default.h> | |
53 | ||
54 | #define CONFIG_CMD_CACHE | |
55 | #define CONFIG_CMD_EEPROM | |
56 | #define CONFIG_CMD_I2C | |
57 | #define CONFIG_CMD_USB | |
58 | #define CONFIG_CMD_REGINFO | |
a5562901 JL |
59 | #define CONFIG_CMD_DATE |
60 | #define CONFIG_CMD_ELF | |
61 | #define CONFIG_CMD_DHCP | |
62 | #define CONFIG_CMD_PING | |
63 | #define CONFIG_CMD_BSP | |
f3108304 | 64 | #define CONFIG_CMD_NAND |
b930a3e6 | 65 | #define CONFIG_CMD_NAND_YAFFS |
a5562901 | 66 | |
9660e442 | 67 | #define CONFIG_BOARD_LATE_INIT |
1cb8e980 | 68 | |
6d0f6bcf | 69 | #define CONFIG_SYS_HUSH_PARSER |
f3108304 DMEA |
70 | #define CONFIG_CMDLINE_EDITING |
71 | ||
72 | /* | |
1cb8e980 WD |
73 | * I2C stuff: |
74 | * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at | |
75 | * address 0x50 with 16bit addressing | |
f3108304 | 76 | */ |
2d8f1e27 | 77 | #define CONFIG_SYS_I2C |
1cb8e980 | 78 | |
f3108304 | 79 | /* we use the built-in I2C controller */ |
2d8f1e27 PW |
80 | #define CONFIG_SYS_I2C_S3C24X0 |
81 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* I2C speed */ | |
82 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x7F /* I2C slave addr */ | |
f3108304 | 83 | |
6d0f6bcf JCPV |
84 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
85 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
f3108304 DMEA |
86 | /* use EEPROM for environment vars */ |
87 | #define CONFIG_ENV_IS_IN_EEPROM 1 | |
88 | /* environment starts at offset 0 */ | |
89 | #define CONFIG_ENV_OFFSET 0x000 | |
90 | /* 2KB should be more than enough */ | |
91 | #define CONFIG_ENV_SIZE 0x800 | |
1cb8e980 | 92 | |
6d0f6bcf | 93 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
f3108304 DMEA |
94 | /* 64 bytes page write mode on 24C256 */ |
95 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
6d0f6bcf | 96 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
1cb8e980 | 97 | |
1cb8e980 WD |
98 | /* |
99 | * Hardware drivers | |
100 | */ | |
f3108304 DMEA |
101 | #define CONFIG_CS8900 /* we have a CS8900 on-board */ |
102 | #define CONFIG_CS8900_BASE 0x20000300 | |
103 | #define CONFIG_CS8900_BUS16 | |
1cb8e980 WD |
104 | |
105 | /* | |
106 | * select serial console configuration | |
107 | */ | |
300f99f4 | 108 | #define CONFIG_S3C24X0_SERIAL |
f3108304 | 109 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ |
1cb8e980 | 110 | |
f3108304 DMEA |
111 | /* USB support (currently only works with D-cache off) */ |
112 | #define CONFIG_USB_OHCI | |
fb24ffc0 | 113 | #define CONFIG_USB_OHCI_S3C24XX |
f3108304 DMEA |
114 | #define CONFIG_USB_KEYBOARD |
115 | #define CONFIG_USB_STORAGE | |
116 | #define CONFIG_DOS_PARTITION | |
48b42616 WD |
117 | |
118 | /* Enable needed helper functions */ | |
f3108304 | 119 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
48b42616 | 120 | |
f3108304 DMEA |
121 | /* RTC */ |
122 | #define CONFIG_RTC_S3C24X0 | |
48b42616 WD |
123 | |
124 | ||
1cb8e980 WD |
125 | /* allow to overwrite serial and ethaddr */ |
126 | #define CONFIG_ENV_OVERWRITE | |
127 | ||
f3108304 | 128 | #define CONFIG_BAUDRATE 9600 |
1cb8e980 | 129 | |
f3108304 DMEA |
130 | #define CONFIG_BOOTDELAY 5 |
131 | #define CONFIG_BOOT_RETRY_TIME -1 | |
132 | #define CONFIG_RESET_TO_RETRY | |
133 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
a2663ea4 | 134 | |
f3108304 DMEA |
135 | #define CONFIG_NETMASK 255.255.255.0 |
136 | #define CONFIG_IPADDR 10.0.0.110 | |
137 | #define CONFIG_SERVERIP 10.0.0.1 | |
1cb8e980 | 138 | |
a5562901 | 139 | #if defined(CONFIG_CMD_KGDB) |
f3108304 DMEA |
140 | /* speed to run kgdb serial port */ |
141 | #define CONFIG_KGDB_BAUDRATE 115200 | |
1cb8e980 WD |
142 | #endif |
143 | ||
f3108304 DMEA |
144 | /* Miscellaneous configurable options */ |
145 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
146 | #define CONFIG_SYS_PROMPT "VCMA9 # " | |
147 | #define CONFIG_SYS_CBSIZE 256 | |
148 | /* Print Buffer Size */ | |
149 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
150 | #define CONFIG_SYS_MAXARGS 16 | |
151 | /* Boot Argument Buffer Size */ | |
152 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
153 | ||
3d3206f1 | 154 | #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ |
f3108304 | 155 | #define CONFIG_DISPLAY_BOARDINFO /* Display board info */ |
1cb8e980 | 156 | |
f3108304 DMEA |
157 | #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ |
158 | #define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */ | |
531716e1 | 159 | |
6d0f6bcf | 160 | #define CONFIG_SYS_ALT_MEMTEST |
f3108304 | 161 | #define CONFIG_SYS_LOAD_ADDR 0x30800000 |
1cb8e980 | 162 | |
f3108304 | 163 | /* we configure PWM Timer 4 to 1ms 1000Hz */ |
1cb8e980 | 164 | |
f3108304 DMEA |
165 | /* support additional compression methods */ |
166 | #define CONFIG_BZIP2 | |
167 | #define CONFIG_LZO | |
168 | #define CONFIG_LZMA | |
a2663ea4 | 169 | |
f3108304 | 170 | /* Ident */ |
48b42616 WD |
171 | /*#define VERSION_TAG "released"*/ |
172 | #define VERSION_TAG "unstable" | |
f3108304 DMEA |
173 | #define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \ |
174 | "MEV-10080-001 " VERSION_TAG | |
48b42616 | 175 | |
f3108304 DMEA |
176 | /* Physical Memory Map */ |
177 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
178 | #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ | |
179 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
1cb8e980 | 180 | |
6d754843 | 181 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
1cb8e980 | 182 | |
f3108304 | 183 | /* FLASH and environment organization */ |
1cb8e980 | 184 | |
6d754843 DMEA |
185 | #define CONFIG_SYS_FLASH_CFI |
186 | #define CONFIG_FLASH_CFI_DRIVER | |
187 | #define CONFIG_FLASH_CFI_LEGACY | |
188 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
189 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
6d0f6bcf | 190 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
f3108304 | 191 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
6d754843 | 192 | #define CONFIG_SYS_MAX_FLASH_SECT (19) |
1cb8e980 | 193 | |
f3108304 DMEA |
194 | /* |
195 | * Size of malloc() pool | |
196 | * BZIP2 / LZO / LZMA need a lot of RAM | |
197 | */ | |
198 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
199 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
200 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
1cb8e980 | 201 | |
f3108304 DMEA |
202 | /* NAND configuration */ |
203 | #ifdef CONFIG_CMD_NAND | |
204 | #define CONFIG_NAND_S3C2410 | |
205 | #define CONFIG_SYS_S3C2410_NAND_HWECC | |
206 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
f3108304 DMEA |
207 | #define CONFIG_SYS_NAND_BASE 0x4E000000 |
208 | #define CONFIG_S3C24XX_CUSTOM_NAND_TIMING | |
209 | #define CONFIG_S3C24XX_TACLS 1 | |
210 | #define CONFIG_S3C24XX_TWRPH0 5 | |
211 | #define CONFIG_S3C24XX_TWRPH1 3 | |
212 | #endif | |
48b42616 | 213 | |
f3108304 | 214 | #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 |
48b42616 | 215 | |
f3108304 DMEA |
216 | /* File system */ |
217 | #define CONFIG_CMD_FAT | |
f3108304 DMEA |
218 | #define CONFIG_CMD_UBI |
219 | #define CONFIG_CMD_UBIFS | |
220 | #define CONFIG_CMD_JFFS2 | |
221 | #define CONFIG_YAFFS2 | |
222 | #define CONFIG_RBTREE | |
223 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
224 | #define CONFIG_MTD_PARTITIONS | |
225 | #define CONFIG_CMD_MTDPARTS | |
226 | #define CONFIG_LZO | |
48b42616 | 227 | |
d2d94571 DMEA |
228 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
229 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
230 | GENERATED_GBL_DATA_SIZE) | |
231 | ||
f3108304 | 232 | #define CONFIG_BOARD_EARLY_INIT_F |
d2d94571 | 233 | |
f3108304 | 234 | #endif /* __CONFIG_H */ |