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Commit | Line | Data |
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1cb8e980 | 1 | /* |
531716e1 | 2 | * (C) Copyright 2002, 2003 |
1cb8e980 WD |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
792a09eb | 5 | * Gary Jennejohn <garyj@denx.de> |
1cb8e980 WD |
6 | * David Mueller <d.mueller@elsoft.ch> |
7 | * | |
8 | * Configuation settings for the MPL VCMA9 board. | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1cb8e980 WD |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
c686537f DMEA |
16 | #define MACH_TYPE_MPL_VCMA9 227 |
17 | ||
1cb8e980 WD |
18 | /* |
19 | * High Level Configuration Options | |
20 | * (easy to change) | |
21 | */ | |
195629cd DMEA |
22 | #define CONFIG_SYS_THUMB_BUILD |
23 | ||
f2168440 | 24 | #define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ |
f3108304 DMEA |
25 | #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ |
26 | #define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ | |
c686537f | 27 | #define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */ |
1cb8e980 | 28 | |
0bf42fec DMEA |
29 | #define CONFIG_SYS_TEXT_BASE 0x0 |
30 | ||
f3108304 | 31 | #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH |
1cb8e980 | 32 | |
f3108304 DMEA |
33 | /* input clock of PLL (VCMA9 has 12MHz input clock) */ |
34 | #define CONFIG_SYS_CLK_FREQ 12000000 | |
1cb8e980 | 35 | |
f3108304 DMEA |
36 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
37 | #define CONFIG_SETUP_MEMORY_TAGS | |
38 | #define CONFIG_INITRD_TAG | |
a5562901 | 39 | |
a1aa0bb5 JL |
40 | /* |
41 | * BOOTP options | |
42 | */ | |
43 | #define CONFIG_BOOTP_BOOTFILESIZE | |
44 | #define CONFIG_BOOTP_BOOTPATH | |
45 | #define CONFIG_BOOTP_GATEWAY | |
46 | #define CONFIG_BOOTP_HOSTNAME | |
47 | ||
a5562901 JL |
48 | /* |
49 | * Command line configuration. | |
50 | */ | |
a5562901 | 51 | #define CONFIG_CMD_EEPROM |
a5562901 | 52 | #define CONFIG_CMD_REGINFO |
a5562901 | 53 | #define CONFIG_CMD_DATE |
a5562901 | 54 | #define CONFIG_CMD_BSP |
f3108304 | 55 | #define CONFIG_CMD_NAND |
a5562901 | 56 | |
9660e442 | 57 | #define CONFIG_BOARD_LATE_INIT |
1cb8e980 | 58 | |
f3108304 DMEA |
59 | #define CONFIG_CMDLINE_EDITING |
60 | ||
61 | /* | |
1cb8e980 WD |
62 | * I2C stuff: |
63 | * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at | |
64 | * address 0x50 with 16bit addressing | |
f3108304 | 65 | */ |
2d8f1e27 | 66 | #define CONFIG_SYS_I2C |
1cb8e980 | 67 | |
f3108304 | 68 | /* we use the built-in I2C controller */ |
2d8f1e27 PW |
69 | #define CONFIG_SYS_I2C_S3C24X0 |
70 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* I2C speed */ | |
71 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x7F /* I2C slave addr */ | |
f3108304 | 72 | |
6d0f6bcf JCPV |
73 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
74 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
f3108304 DMEA |
75 | /* use EEPROM for environment vars */ |
76 | #define CONFIG_ENV_IS_IN_EEPROM 1 | |
77 | /* environment starts at offset 0 */ | |
78 | #define CONFIG_ENV_OFFSET 0x000 | |
79 | /* 2KB should be more than enough */ | |
80 | #define CONFIG_ENV_SIZE 0x800 | |
1cb8e980 | 81 | |
6d0f6bcf | 82 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
f3108304 DMEA |
83 | /* 64 bytes page write mode on 24C256 */ |
84 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
6d0f6bcf | 85 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
1cb8e980 | 86 | |
1cb8e980 WD |
87 | /* |
88 | * Hardware drivers | |
89 | */ | |
f3108304 DMEA |
90 | #define CONFIG_CS8900 /* we have a CS8900 on-board */ |
91 | #define CONFIG_CS8900_BASE 0x20000300 | |
92 | #define CONFIG_CS8900_BUS16 | |
1cb8e980 WD |
93 | |
94 | /* | |
95 | * select serial console configuration | |
96 | */ | |
300f99f4 | 97 | #define CONFIG_S3C24X0_SERIAL |
f3108304 | 98 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ |
1cb8e980 | 99 | |
f3108304 DMEA |
100 | /* USB support (currently only works with D-cache off) */ |
101 | #define CONFIG_USB_OHCI | |
fb24ffc0 | 102 | #define CONFIG_USB_OHCI_S3C24XX |
f3108304 | 103 | #define CONFIG_DOS_PARTITION |
48b42616 WD |
104 | |
105 | /* Enable needed helper functions */ | |
48b42616 | 106 | |
f3108304 DMEA |
107 | /* RTC */ |
108 | #define CONFIG_RTC_S3C24X0 | |
48b42616 | 109 | |
1cb8e980 WD |
110 | /* allow to overwrite serial and ethaddr */ |
111 | #define CONFIG_ENV_OVERWRITE | |
112 | ||
f3108304 | 113 | #define CONFIG_BAUDRATE 9600 |
1cb8e980 | 114 | |
f3108304 DMEA |
115 | #define CONFIG_BOOT_RETRY_TIME -1 |
116 | #define CONFIG_RESET_TO_RETRY | |
a2663ea4 | 117 | |
f3108304 DMEA |
118 | #define CONFIG_NETMASK 255.255.255.0 |
119 | #define CONFIG_IPADDR 10.0.0.110 | |
120 | #define CONFIG_SERVERIP 10.0.0.1 | |
1cb8e980 | 121 | |
a5562901 | 122 | #if defined(CONFIG_CMD_KGDB) |
f3108304 DMEA |
123 | /* speed to run kgdb serial port */ |
124 | #define CONFIG_KGDB_BAUDRATE 115200 | |
1cb8e980 WD |
125 | #endif |
126 | ||
f3108304 DMEA |
127 | /* Miscellaneous configurable options */ |
128 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
f3108304 DMEA |
129 | #define CONFIG_SYS_CBSIZE 256 |
130 | /* Print Buffer Size */ | |
131 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
132 | #define CONFIG_SYS_MAXARGS 16 | |
133 | /* Boot Argument Buffer Size */ | |
134 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
135 | ||
f3108304 DMEA |
136 | #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ |
137 | #define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */ | |
531716e1 | 138 | |
6d0f6bcf | 139 | #define CONFIG_SYS_ALT_MEMTEST |
f3108304 | 140 | #define CONFIG_SYS_LOAD_ADDR 0x30800000 |
1cb8e980 | 141 | |
f3108304 | 142 | /* we configure PWM Timer 4 to 1ms 1000Hz */ |
1cb8e980 | 143 | |
f3108304 DMEA |
144 | /* support additional compression methods */ |
145 | #define CONFIG_BZIP2 | |
146 | #define CONFIG_LZO | |
147 | #define CONFIG_LZMA | |
a2663ea4 | 148 | |
f3108304 DMEA |
149 | /* Physical Memory Map */ |
150 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
151 | #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ | |
152 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
1cb8e980 | 153 | |
6d754843 | 154 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
1cb8e980 | 155 | |
f3108304 | 156 | /* FLASH and environment organization */ |
1cb8e980 | 157 | |
6d754843 DMEA |
158 | #define CONFIG_SYS_FLASH_CFI |
159 | #define CONFIG_FLASH_CFI_DRIVER | |
160 | #define CONFIG_FLASH_CFI_LEGACY | |
161 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
162 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
6d0f6bcf | 163 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
f3108304 | 164 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
6d754843 | 165 | #define CONFIG_SYS_MAX_FLASH_SECT (19) |
1cb8e980 | 166 | |
f3108304 DMEA |
167 | /* |
168 | * Size of malloc() pool | |
169 | * BZIP2 / LZO / LZMA need a lot of RAM | |
170 | */ | |
171 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
172 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
173 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
1cb8e980 | 174 | |
f3108304 DMEA |
175 | /* NAND configuration */ |
176 | #ifdef CONFIG_CMD_NAND | |
177 | #define CONFIG_NAND_S3C2410 | |
178 | #define CONFIG_SYS_S3C2410_NAND_HWECC | |
179 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
f3108304 DMEA |
180 | #define CONFIG_SYS_NAND_BASE 0x4E000000 |
181 | #define CONFIG_S3C24XX_CUSTOM_NAND_TIMING | |
182 | #define CONFIG_S3C24XX_TACLS 1 | |
183 | #define CONFIG_S3C24XX_TWRPH0 5 | |
184 | #define CONFIG_S3C24XX_TWRPH1 3 | |
185 | #endif | |
48b42616 | 186 | |
f3108304 | 187 | #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 |
48b42616 | 188 | |
f3108304 | 189 | /* File system */ |
f3108304 DMEA |
190 | #define CONFIG_CMD_UBIFS |
191 | #define CONFIG_CMD_JFFS2 | |
192 | #define CONFIG_YAFFS2 | |
193 | #define CONFIG_RBTREE | |
194 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
195 | #define CONFIG_MTD_PARTITIONS | |
196 | #define CONFIG_CMD_MTDPARTS | |
197 | #define CONFIG_LZO | |
48b42616 | 198 | |
d2d94571 DMEA |
199 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
200 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
201 | GENERATED_GBL_DATA_SIZE) | |
202 | ||
f3108304 | 203 | #define CONFIG_BOARD_EARLY_INIT_F |
d2d94571 | 204 | |
f3108304 | 205 | #endif /* __CONFIG_H */ |