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1cb8e980 | 1 | /* |
531716e1 | 2 | * (C) Copyright 2002, 2003 |
1cb8e980 WD |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
792a09eb | 5 | * Gary Jennejohn <garyj@denx.de> |
1cb8e980 WD |
6 | * David Mueller <d.mueller@elsoft.ch> |
7 | * | |
8 | * Configuation settings for the MPL VCMA9 board. | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
c686537f DMEA |
32 | |
33 | #define MACH_TYPE_MPL_VCMA9 227 | |
34 | ||
1cb8e980 WD |
35 | /* |
36 | * High Level Configuration Options | |
37 | * (easy to change) | |
38 | */ | |
f3108304 DMEA |
39 | #define CONFIG_ARM920T /* This is an ARM920T Core */ |
40 | #define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ | |
41 | #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ | |
42 | #define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ | |
c686537f | 43 | #define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */ |
1cb8e980 | 44 | |
0bf42fec DMEA |
45 | #define CONFIG_SYS_TEXT_BASE 0x0 |
46 | ||
f3108304 | 47 | #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH |
1cb8e980 | 48 | |
f3108304 DMEA |
49 | /* input clock of PLL (VCMA9 has 12MHz input clock) */ |
50 | #define CONFIG_SYS_CLK_FREQ 12000000 | |
1cb8e980 | 51 | |
f3108304 DMEA |
52 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
53 | #define CONFIG_SETUP_MEMORY_TAGS | |
54 | #define CONFIG_INITRD_TAG | |
a5562901 | 55 | |
a1aa0bb5 JL |
56 | /* |
57 | * BOOTP options | |
58 | */ | |
59 | #define CONFIG_BOOTP_BOOTFILESIZE | |
60 | #define CONFIG_BOOTP_BOOTPATH | |
61 | #define CONFIG_BOOTP_GATEWAY | |
62 | #define CONFIG_BOOTP_HOSTNAME | |
63 | ||
a5562901 JL |
64 | /* |
65 | * Command line configuration. | |
66 | */ | |
67 | #include <config_cmd_default.h> | |
68 | ||
69 | #define CONFIG_CMD_CACHE | |
70 | #define CONFIG_CMD_EEPROM | |
71 | #define CONFIG_CMD_I2C | |
72 | #define CONFIG_CMD_USB | |
73 | #define CONFIG_CMD_REGINFO | |
a5562901 JL |
74 | #define CONFIG_CMD_DATE |
75 | #define CONFIG_CMD_ELF | |
76 | #define CONFIG_CMD_DHCP | |
77 | #define CONFIG_CMD_PING | |
78 | #define CONFIG_CMD_BSP | |
f3108304 | 79 | #define CONFIG_CMD_NAND |
a5562901 | 80 | |
9660e442 | 81 | #define CONFIG_BOARD_LATE_INIT |
1cb8e980 | 82 | |
6d0f6bcf | 83 | #define CONFIG_SYS_HUSH_PARSER |
f3108304 DMEA |
84 | #define CONFIG_CMDLINE_EDITING |
85 | ||
86 | /* | |
1cb8e980 WD |
87 | * I2C stuff: |
88 | * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at | |
89 | * address 0x50 with 16bit addressing | |
f3108304 DMEA |
90 | */ |
91 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ |
93 | #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */ | |
1cb8e980 | 94 | |
f3108304 DMEA |
95 | /* we use the built-in I2C controller */ |
96 | #define CONFIG_DRIVER_S3C24X0_I2C | |
97 | ||
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
99 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
f3108304 DMEA |
100 | /* use EEPROM for environment vars */ |
101 | #define CONFIG_ENV_IS_IN_EEPROM 1 | |
102 | /* environment starts at offset 0 */ | |
103 | #define CONFIG_ENV_OFFSET 0x000 | |
104 | /* 2KB should be more than enough */ | |
105 | #define CONFIG_ENV_SIZE 0x800 | |
1cb8e980 | 106 | |
6d0f6bcf | 107 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
f3108304 DMEA |
108 | /* 64 bytes page write mode on 24C256 */ |
109 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
6d0f6bcf | 110 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
1cb8e980 | 111 | |
1cb8e980 WD |
112 | /* |
113 | * Hardware drivers | |
114 | */ | |
f3108304 DMEA |
115 | #define CONFIG_CS8900 /* we have a CS8900 on-board */ |
116 | #define CONFIG_CS8900_BASE 0x20000300 | |
117 | #define CONFIG_CS8900_BUS16 | |
1cb8e980 WD |
118 | |
119 | /* | |
120 | * select serial console configuration | |
121 | */ | |
300f99f4 | 122 | #define CONFIG_S3C24X0_SERIAL |
f3108304 | 123 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ |
1cb8e980 | 124 | |
f3108304 DMEA |
125 | /* USB support (currently only works with D-cache off) */ |
126 | #define CONFIG_USB_OHCI | |
fb24ffc0 | 127 | #define CONFIG_USB_OHCI_S3C24XX |
f3108304 DMEA |
128 | #define CONFIG_USB_KEYBOARD |
129 | #define CONFIG_USB_STORAGE | |
130 | #define CONFIG_DOS_PARTITION | |
48b42616 WD |
131 | |
132 | /* Enable needed helper functions */ | |
f3108304 | 133 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
48b42616 | 134 | |
f3108304 DMEA |
135 | /* RTC */ |
136 | #define CONFIG_RTC_S3C24X0 | |
48b42616 WD |
137 | |
138 | ||
1cb8e980 WD |
139 | /* allow to overwrite serial and ethaddr */ |
140 | #define CONFIG_ENV_OVERWRITE | |
141 | ||
f3108304 | 142 | #define CONFIG_BAUDRATE 9600 |
1cb8e980 | 143 | |
f3108304 DMEA |
144 | #define CONFIG_BOOTDELAY 5 |
145 | #define CONFIG_BOOT_RETRY_TIME -1 | |
146 | #define CONFIG_RESET_TO_RETRY | |
147 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
a2663ea4 | 148 | |
f3108304 DMEA |
149 | #define CONFIG_NETMASK 255.255.255.0 |
150 | #define CONFIG_IPADDR 10.0.0.110 | |
151 | #define CONFIG_SERVERIP 10.0.0.1 | |
1cb8e980 | 152 | |
a5562901 | 153 | #if defined(CONFIG_CMD_KGDB) |
f3108304 DMEA |
154 | /* speed to run kgdb serial port */ |
155 | #define CONFIG_KGDB_BAUDRATE 115200 | |
1cb8e980 | 156 | /* what's this ? it's not used anywhere */ |
f3108304 | 157 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
1cb8e980 WD |
158 | #endif |
159 | ||
f3108304 DMEA |
160 | /* Miscellaneous configurable options */ |
161 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
162 | #define CONFIG_SYS_PROMPT "VCMA9 # " | |
163 | #define CONFIG_SYS_CBSIZE 256 | |
164 | /* Print Buffer Size */ | |
165 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
166 | #define CONFIG_SYS_MAXARGS 16 | |
167 | /* Boot Argument Buffer Size */ | |
168 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
169 | ||
3d3206f1 | 170 | #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ |
f3108304 | 171 | #define CONFIG_DISPLAY_BOARDINFO /* Display board info */ |
1cb8e980 | 172 | |
f3108304 DMEA |
173 | #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ |
174 | #define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */ | |
531716e1 | 175 | |
6d0f6bcf | 176 | #define CONFIG_SYS_ALT_MEMTEST |
f3108304 | 177 | #define CONFIG_SYS_LOAD_ADDR 0x30800000 |
1cb8e980 | 178 | |
f3108304 DMEA |
179 | /* we configure PWM Timer 4 to 1ms 1000Hz */ |
180 | #define CONFIG_SYS_HZ 1000 | |
1cb8e980 | 181 | |
f3108304 DMEA |
182 | /* support additional compression methods */ |
183 | #define CONFIG_BZIP2 | |
184 | #define CONFIG_LZO | |
185 | #define CONFIG_LZMA | |
a2663ea4 | 186 | |
f3108304 | 187 | /* Ident */ |
48b42616 WD |
188 | /*#define VERSION_TAG "released"*/ |
189 | #define VERSION_TAG "unstable" | |
f3108304 DMEA |
190 | #define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \ |
191 | "MEV-10080-001 " VERSION_TAG | |
48b42616 | 192 | |
f3108304 DMEA |
193 | /* Physical Memory Map */ |
194 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
195 | #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ | |
196 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
1cb8e980 | 197 | |
6d754843 | 198 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
1cb8e980 | 199 | |
f3108304 | 200 | /* FLASH and environment organization */ |
1cb8e980 | 201 | |
6d754843 DMEA |
202 | #define CONFIG_SYS_FLASH_CFI |
203 | #define CONFIG_FLASH_CFI_DRIVER | |
204 | #define CONFIG_FLASH_CFI_LEGACY | |
205 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
206 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
6d0f6bcf | 207 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
f3108304 | 208 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
6d754843 | 209 | #define CONFIG_SYS_MAX_FLASH_SECT (19) |
1cb8e980 | 210 | |
f3108304 DMEA |
211 | /* |
212 | * Size of malloc() pool | |
213 | * BZIP2 / LZO / LZMA need a lot of RAM | |
214 | */ | |
215 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
216 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
217 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
1cb8e980 | 218 | |
f3108304 DMEA |
219 | /* NAND configuration */ |
220 | #ifdef CONFIG_CMD_NAND | |
221 | #define CONFIG_NAND_S3C2410 | |
222 | #define CONFIG_SYS_S3C2410_NAND_HWECC | |
223 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
f3108304 DMEA |
224 | #define CONFIG_SYS_NAND_BASE 0x4E000000 |
225 | #define CONFIG_S3C24XX_CUSTOM_NAND_TIMING | |
226 | #define CONFIG_S3C24XX_TACLS 1 | |
227 | #define CONFIG_S3C24XX_TWRPH0 5 | |
228 | #define CONFIG_S3C24XX_TWRPH1 3 | |
229 | #endif | |
48b42616 | 230 | |
f3108304 | 231 | #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 |
48b42616 | 232 | |
f3108304 DMEA |
233 | /* File system */ |
234 | #define CONFIG_CMD_FAT | |
235 | #define CONFIG_CMD_EXT2 | |
236 | #define CONFIG_CMD_UBI | |
237 | #define CONFIG_CMD_UBIFS | |
238 | #define CONFIG_CMD_JFFS2 | |
239 | #define CONFIG_YAFFS2 | |
240 | #define CONFIG_RBTREE | |
241 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
242 | #define CONFIG_MTD_PARTITIONS | |
243 | #define CONFIG_CMD_MTDPARTS | |
244 | #define CONFIG_LZO | |
48b42616 | 245 | |
d2d94571 DMEA |
246 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
247 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
248 | GENERATED_GBL_DATA_SIZE) | |
249 | ||
f3108304 | 250 | #define CONFIG_BOARD_EARLY_INIT_F |
d2d94571 | 251 | |
f3108304 | 252 | #endif /* __CONFIG_H */ |