]>
Commit | Line | Data |
---|---|---|
1cb8e980 | 1 | /* |
531716e1 | 2 | * (C) Copyright 2002, 2003 |
1cb8e980 WD |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
792a09eb | 5 | * Gary Jennejohn <garyj@denx.de> |
1cb8e980 WD |
6 | * David Mueller <d.mueller@elsoft.ch> |
7 | * | |
8 | * Configuation settings for the MPL VCMA9 board. | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1cb8e980 WD |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
c686537f DMEA |
16 | |
17 | #define MACH_TYPE_MPL_VCMA9 227 | |
18 | ||
1cb8e980 WD |
19 | /* |
20 | * High Level Configuration Options | |
21 | * (easy to change) | |
22 | */ | |
f3108304 DMEA |
23 | #define CONFIG_ARM920T /* This is an ARM920T Core */ |
24 | #define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ | |
25 | #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ | |
26 | #define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ | |
c686537f | 27 | #define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */ |
1cb8e980 | 28 | |
0bf42fec DMEA |
29 | #define CONFIG_SYS_TEXT_BASE 0x0 |
30 | ||
f3108304 | 31 | #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH |
1cb8e980 | 32 | |
f3108304 DMEA |
33 | /* input clock of PLL (VCMA9 has 12MHz input clock) */ |
34 | #define CONFIG_SYS_CLK_FREQ 12000000 | |
1cb8e980 | 35 | |
f3108304 DMEA |
36 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
37 | #define CONFIG_SETUP_MEMORY_TAGS | |
38 | #define CONFIG_INITRD_TAG | |
a5562901 | 39 | |
a1aa0bb5 JL |
40 | /* |
41 | * BOOTP options | |
42 | */ | |
43 | #define CONFIG_BOOTP_BOOTFILESIZE | |
44 | #define CONFIG_BOOTP_BOOTPATH | |
45 | #define CONFIG_BOOTP_GATEWAY | |
46 | #define CONFIG_BOOTP_HOSTNAME | |
47 | ||
a5562901 JL |
48 | /* |
49 | * Command line configuration. | |
50 | */ | |
51 | #include <config_cmd_default.h> | |
52 | ||
53 | #define CONFIG_CMD_CACHE | |
54 | #define CONFIG_CMD_EEPROM | |
55 | #define CONFIG_CMD_I2C | |
56 | #define CONFIG_CMD_USB | |
57 | #define CONFIG_CMD_REGINFO | |
a5562901 JL |
58 | #define CONFIG_CMD_DATE |
59 | #define CONFIG_CMD_ELF | |
60 | #define CONFIG_CMD_DHCP | |
61 | #define CONFIG_CMD_PING | |
62 | #define CONFIG_CMD_BSP | |
f3108304 | 63 | #define CONFIG_CMD_NAND |
b930a3e6 | 64 | #define CONFIG_CMD_NAND_YAFFS |
a5562901 | 65 | |
9660e442 | 66 | #define CONFIG_BOARD_LATE_INIT |
1cb8e980 | 67 | |
6d0f6bcf | 68 | #define CONFIG_SYS_HUSH_PARSER |
f3108304 DMEA |
69 | #define CONFIG_CMDLINE_EDITING |
70 | ||
71 | /* | |
1cb8e980 WD |
72 | * I2C stuff: |
73 | * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at | |
74 | * address 0x50 with 16bit addressing | |
f3108304 DMEA |
75 | */ |
76 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ |
78 | #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */ | |
1cb8e980 | 79 | |
f3108304 DMEA |
80 | /* we use the built-in I2C controller */ |
81 | #define CONFIG_DRIVER_S3C24X0_I2C | |
82 | ||
6d0f6bcf JCPV |
83 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
84 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
f3108304 DMEA |
85 | /* use EEPROM for environment vars */ |
86 | #define CONFIG_ENV_IS_IN_EEPROM 1 | |
87 | /* environment starts at offset 0 */ | |
88 | #define CONFIG_ENV_OFFSET 0x000 | |
89 | /* 2KB should be more than enough */ | |
90 | #define CONFIG_ENV_SIZE 0x800 | |
1cb8e980 | 91 | |
6d0f6bcf | 92 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
f3108304 DMEA |
93 | /* 64 bytes page write mode on 24C256 */ |
94 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
6d0f6bcf | 95 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
1cb8e980 | 96 | |
1cb8e980 WD |
97 | /* |
98 | * Hardware drivers | |
99 | */ | |
f3108304 DMEA |
100 | #define CONFIG_CS8900 /* we have a CS8900 on-board */ |
101 | #define CONFIG_CS8900_BASE 0x20000300 | |
102 | #define CONFIG_CS8900_BUS16 | |
1cb8e980 WD |
103 | |
104 | /* | |
105 | * select serial console configuration | |
106 | */ | |
300f99f4 | 107 | #define CONFIG_S3C24X0_SERIAL |
f3108304 | 108 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ |
1cb8e980 | 109 | |
f3108304 DMEA |
110 | /* USB support (currently only works with D-cache off) */ |
111 | #define CONFIG_USB_OHCI | |
fb24ffc0 | 112 | #define CONFIG_USB_OHCI_S3C24XX |
f3108304 DMEA |
113 | #define CONFIG_USB_KEYBOARD |
114 | #define CONFIG_USB_STORAGE | |
115 | #define CONFIG_DOS_PARTITION | |
48b42616 WD |
116 | |
117 | /* Enable needed helper functions */ | |
f3108304 | 118 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
48b42616 | 119 | |
f3108304 DMEA |
120 | /* RTC */ |
121 | #define CONFIG_RTC_S3C24X0 | |
48b42616 WD |
122 | |
123 | ||
1cb8e980 WD |
124 | /* allow to overwrite serial and ethaddr */ |
125 | #define CONFIG_ENV_OVERWRITE | |
126 | ||
f3108304 | 127 | #define CONFIG_BAUDRATE 9600 |
1cb8e980 | 128 | |
f3108304 DMEA |
129 | #define CONFIG_BOOTDELAY 5 |
130 | #define CONFIG_BOOT_RETRY_TIME -1 | |
131 | #define CONFIG_RESET_TO_RETRY | |
132 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
a2663ea4 | 133 | |
f3108304 DMEA |
134 | #define CONFIG_NETMASK 255.255.255.0 |
135 | #define CONFIG_IPADDR 10.0.0.110 | |
136 | #define CONFIG_SERVERIP 10.0.0.1 | |
1cb8e980 | 137 | |
a5562901 | 138 | #if defined(CONFIG_CMD_KGDB) |
f3108304 DMEA |
139 | /* speed to run kgdb serial port */ |
140 | #define CONFIG_KGDB_BAUDRATE 115200 | |
1cb8e980 | 141 | /* what's this ? it's not used anywhere */ |
f3108304 | 142 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
1cb8e980 WD |
143 | #endif |
144 | ||
f3108304 DMEA |
145 | /* Miscellaneous configurable options */ |
146 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
147 | #define CONFIG_SYS_PROMPT "VCMA9 # " | |
148 | #define CONFIG_SYS_CBSIZE 256 | |
149 | /* Print Buffer Size */ | |
150 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
151 | #define CONFIG_SYS_MAXARGS 16 | |
152 | /* Boot Argument Buffer Size */ | |
153 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
154 | ||
3d3206f1 | 155 | #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ |
f3108304 | 156 | #define CONFIG_DISPLAY_BOARDINFO /* Display board info */ |
1cb8e980 | 157 | |
f3108304 DMEA |
158 | #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ |
159 | #define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */ | |
531716e1 | 160 | |
6d0f6bcf | 161 | #define CONFIG_SYS_ALT_MEMTEST |
f3108304 | 162 | #define CONFIG_SYS_LOAD_ADDR 0x30800000 |
1cb8e980 | 163 | |
f3108304 | 164 | /* we configure PWM Timer 4 to 1ms 1000Hz */ |
1cb8e980 | 165 | |
f3108304 DMEA |
166 | /* support additional compression methods */ |
167 | #define CONFIG_BZIP2 | |
168 | #define CONFIG_LZO | |
169 | #define CONFIG_LZMA | |
a2663ea4 | 170 | |
f3108304 | 171 | /* Ident */ |
48b42616 WD |
172 | /*#define VERSION_TAG "released"*/ |
173 | #define VERSION_TAG "unstable" | |
f3108304 DMEA |
174 | #define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \ |
175 | "MEV-10080-001 " VERSION_TAG | |
48b42616 | 176 | |
f3108304 DMEA |
177 | /* Physical Memory Map */ |
178 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
179 | #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ | |
180 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
1cb8e980 | 181 | |
6d754843 | 182 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
1cb8e980 | 183 | |
f3108304 | 184 | /* FLASH and environment organization */ |
1cb8e980 | 185 | |
6d754843 DMEA |
186 | #define CONFIG_SYS_FLASH_CFI |
187 | #define CONFIG_FLASH_CFI_DRIVER | |
188 | #define CONFIG_FLASH_CFI_LEGACY | |
189 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
190 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
6d0f6bcf | 191 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
f3108304 | 192 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
6d754843 | 193 | #define CONFIG_SYS_MAX_FLASH_SECT (19) |
1cb8e980 | 194 | |
f3108304 DMEA |
195 | /* |
196 | * Size of malloc() pool | |
197 | * BZIP2 / LZO / LZMA need a lot of RAM | |
198 | */ | |
199 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
200 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
201 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
1cb8e980 | 202 | |
f3108304 DMEA |
203 | /* NAND configuration */ |
204 | #ifdef CONFIG_CMD_NAND | |
205 | #define CONFIG_NAND_S3C2410 | |
206 | #define CONFIG_SYS_S3C2410_NAND_HWECC | |
207 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
f3108304 DMEA |
208 | #define CONFIG_SYS_NAND_BASE 0x4E000000 |
209 | #define CONFIG_S3C24XX_CUSTOM_NAND_TIMING | |
210 | #define CONFIG_S3C24XX_TACLS 1 | |
211 | #define CONFIG_S3C24XX_TWRPH0 5 | |
212 | #define CONFIG_S3C24XX_TWRPH1 3 | |
213 | #endif | |
48b42616 | 214 | |
f3108304 | 215 | #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 |
48b42616 | 216 | |
f3108304 DMEA |
217 | /* File system */ |
218 | #define CONFIG_CMD_FAT | |
219 | #define CONFIG_CMD_EXT2 | |
220 | #define CONFIG_CMD_UBI | |
221 | #define CONFIG_CMD_UBIFS | |
222 | #define CONFIG_CMD_JFFS2 | |
223 | #define CONFIG_YAFFS2 | |
224 | #define CONFIG_RBTREE | |
225 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
226 | #define CONFIG_MTD_PARTITIONS | |
227 | #define CONFIG_CMD_MTDPARTS | |
228 | #define CONFIG_LZO | |
48b42616 | 229 | |
d2d94571 DMEA |
230 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
231 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
232 | GENERATED_GBL_DATA_SIZE) | |
233 | ||
f3108304 | 234 | #define CONFIG_BOARD_EARLY_INIT_F |
d2d94571 | 235 | |
f3108304 | 236 | #endif /* __CONFIG_H */ |