]> git.ipfire.org Git - people/ms/u-boot.git/blame - common/board_f.c
Remove unused CONFIG_MODEM_SUPPORT option and associated dead code.
[people/ms/u-boot.git] / common / board_f.c
CommitLineData
1938f4a5
SG
1/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2002-2006
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Marius Groeger <mgroeger@sysgo.de>
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
1938f4a5
SG
11 */
12
13#include <common.h>
14#include <linux/compiler.h>
15#include <version.h>
24b852a7 16#include <console.h>
1938f4a5 17#include <environment.h>
ab7cd627 18#include <dm.h>
1938f4a5 19#include <fdtdec.h>
f828bf25 20#include <fs.h>
e4fef6cf
SG
21#if defined(CONFIG_CMD_IDE)
22#include <ide.h>
23#endif
24#include <i2c.h>
1938f4a5
SG
25#include <initcall.h>
26#include <logbuff.h>
fb5cf7f1 27#include <malloc.h>
0eb25b61 28#include <mapmem.h>
e4fef6cf
SG
29
30/* TODO: Can we move these into arch/ headers? */
31#ifdef CONFIG_8xx
32#include <mpc8xx.h>
33#endif
34#ifdef CONFIG_5xx
35#include <mpc5xx.h>
36#endif
37#ifdef CONFIG_MPC5xxx
38#include <mpc5xxx.h>
39#endif
ec3b4820 40#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
a76df709
GH
41#include <asm/mp.h>
42#endif
e4fef6cf 43
a733b06b 44#include <os.h>
1938f4a5 45#include <post.h>
e4fef6cf 46#include <spi.h>
c5d4001a 47#include <status_led.h>
71c52dba 48#include <trace.h>
5a541945 49#include <video.h>
e4fef6cf 50#include <watchdog.h>
a733b06b 51#include <asm/errno.h>
1938f4a5
SG
52#include <asm/io.h>
53#include <asm/sections.h>
3fb80163 54#if defined(CONFIG_X86) || defined(CONFIG_ARC)
48a33806
SG
55#include <asm/init_helpers.h>
56#include <asm/relocate.h>
57#endif
a733b06b
SG
58#ifdef CONFIG_SANDBOX
59#include <asm/state.h>
60#endif
ab7cd627 61#include <dm/root.h>
1938f4a5
SG
62#include <linux/compiler.h>
63
64/*
65 * Pointer to initial global data area
66 *
67 * Here we initialize it if needed.
68 */
69#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
70#undef XTRN_DECLARE_GLOBAL_DATA_PTR
71#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
72DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
73#else
74DECLARE_GLOBAL_DATA_PTR;
75#endif
76
77/*
4c509343 78 * TODO(sjg@chromium.org): IMO this code should be
1938f4a5
SG
79 * refactored to a single function, something like:
80 *
81 * void led_set_state(enum led_colour_t colour, int on);
82 */
83/************************************************************************
84 * Coloured LED functionality
85 ************************************************************************
86 * May be supplied by boards if desired
87 */
c5d4001a
JH
88__weak void coloured_LED_init(void) {}
89__weak void red_led_on(void) {}
90__weak void red_led_off(void) {}
91__weak void green_led_on(void) {}
92__weak void green_led_off(void) {}
93__weak void yellow_led_on(void) {}
94__weak void yellow_led_off(void) {}
95__weak void blue_led_on(void) {}
96__weak void blue_led_off(void) {}
1938f4a5
SG
97
98/*
99 * Why is gd allocated a register? Prior to reloc it might be better to
100 * just pass it around to each function in this file?
101 *
102 * After reloc one could argue that it is hardly used and doesn't need
103 * to be in a register. Or if it is it should perhaps hold pointers to all
104 * global data for all modules, so that post-reloc we can avoid the massive
105 * literal pool we get on ARM. Or perhaps just encourage each module to use
106 * a structure...
107 */
108
109/*
110 * Could the CONFIG_SPL_BUILD infection become a flag in gd?
111 */
112
d54d7eb9 113#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
e4fef6cf
SG
114static int init_func_watchdog_init(void)
115{
d54d7eb9
SZ
116# if defined(CONFIG_HW_WATCHDOG) && (defined(CONFIG_BLACKFIN) || \
117 defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
14a380a8
SR
118 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \
119 defined(CONFIG_IMX_WATCHDOG))
d54d7eb9
SZ
120 hw_watchdog_init();
121# endif
e4fef6cf
SG
122 puts(" Watchdog enabled\n");
123 WATCHDOG_RESET();
124
125 return 0;
126}
127
128int init_func_watchdog_reset(void)
129{
130 WATCHDOG_RESET();
131
132 return 0;
133}
134#endif /* CONFIG_WATCHDOG */
135
dd2a6cd0 136__weak void board_add_ram_info(int use_default)
e4fef6cf
SG
137{
138 /* please define platform specific board_add_ram_info() */
139}
140
1938f4a5
SG
141static int init_baud_rate(void)
142{
143 gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
144 return 0;
145}
146
147static int display_text_info(void)
148{
9b217498 149#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
9fdee7d7 150 ulong bss_start, bss_end, text_base;
1938f4a5 151
632efa74
SG
152 bss_start = (ulong)&__bss_start;
153 bss_end = (ulong)&__bss_end;
b60eff31 154
d54d7eb9 155#ifdef CONFIG_SYS_TEXT_BASE
9fdee7d7 156 text_base = CONFIG_SYS_TEXT_BASE;
d54d7eb9 157#else
9fdee7d7 158 text_base = CONFIG_SYS_MONITOR_BASE;
d54d7eb9 159#endif
9fdee7d7
DS
160
161 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
162 text_base, bss_start, bss_end);
a733b06b 163#endif
1938f4a5 164
1938f4a5
SG
165#ifdef CONFIG_USE_IRQ
166 debug("IRQ Stack: %08lx\n", IRQ_STACK_START);
167 debug("FIQ Stack: %08lx\n", FIQ_STACK_START);
168#endif
169
170 return 0;
171}
172
173static int announce_dram_init(void)
174{
175 puts("DRAM: ");
176 return 0;
177}
178
e310b93e 179#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
e4fef6cf
SG
180static int init_func_ram(void)
181{
182#ifdef CONFIG_BOARD_TYPES
183 int board_type = gd->board_type;
184#else
185 int board_type = 0; /* use dummy arg */
186#endif
187
188 gd->ram_size = initdram(board_type);
189
190 if (gd->ram_size > 0)
191 return 0;
192
193 puts("*** failed ***\n");
194 return 1;
195}
196#endif
197
1938f4a5
SG
198static int show_dram_config(void)
199{
fa39ffe5 200 unsigned long long size;
1938f4a5
SG
201
202#ifdef CONFIG_NR_DRAM_BANKS
203 int i;
204
205 debug("\nRAM Configuration:\n");
206 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
207 size += gd->bd->bi_dram[i].size;
715f599f
BM
208 debug("Bank #%d: %llx ", i,
209 (unsigned long long)(gd->bd->bi_dram[i].start));
1938f4a5
SG
210#ifdef DEBUG
211 print_size(gd->bd->bi_dram[i].size, "\n");
212#endif
213 }
214 debug("\nDRAM: ");
215#else
216 size = gd->ram_size;
217#endif
218
e4fef6cf
SG
219 print_size(size, "");
220 board_add_ram_info(0);
221 putc('\n');
1938f4a5
SG
222
223 return 0;
224}
225
dd2a6cd0 226__weak void dram_init_banksize(void)
1938f4a5
SG
227{
228#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
229 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
230 gd->bd->bi_dram[0].size = get_effective_memsize();
231#endif
232}
233
ea818dbb 234#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
e4fef6cf
SG
235static int init_func_i2c(void)
236{
237 puts("I2C: ");
815a76f2 238#ifdef CONFIG_SYS_I2C
239 i2c_init_all();
240#else
e4fef6cf 241 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
815a76f2 242#endif
e4fef6cf
SG
243 puts("ready\n");
244 return 0;
245}
246#endif
247
248#if defined(CONFIG_HARD_SPI)
249static int init_func_spi(void)
250{
251 puts("SPI: ");
252 spi_init();
253 puts("ready\n");
254 return 0;
255}
256#endif
257
258__maybe_unused
1938f4a5
SG
259static int zero_global_data(void)
260{
261 memset((void *)gd, '\0', sizeof(gd_t));
262
263 return 0;
264}
265
266static int setup_mon_len(void)
267{
e945f6dc 268#if defined(__ARM__) || defined(__MICROBLAZE__)
b60eff31 269 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
9b217498 270#elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
a733b06b 271 gd->mon_len = (ulong)&_end - (ulong)_init;
5ff10aa7 272#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2)
d54d7eb9 273 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
2e88bb28
KHH
274#elif defined(CONFIG_NDS32)
275 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
632efa74 276#else
e4fef6cf
SG
277 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
278 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
632efa74 279#endif
1938f4a5
SG
280 return 0;
281}
282
283__weak int arch_cpu_init(void)
284{
285 return 0;
286}
287
a733b06b
SG
288#ifdef CONFIG_SANDBOX
289static int setup_ram_buf(void)
290{
5c2859cd
SG
291 struct sandbox_state *state = state_get_current();
292
293 gd->arch.ram_buf = state->ram_buf;
294 gd->ram_size = state->ram_size;
a733b06b
SG
295
296 return 0;
297}
298#endif
299
1938f4a5
SG
300/* Get the top of usable RAM */
301__weak ulong board_get_usable_ram_top(ulong total_size)
302{
1e4d11a5
SW
303#ifdef CONFIG_SYS_SDRAM_BASE
304 /*
4c509343 305 * Detect whether we have so much RAM that it goes past the end of our
1e4d11a5
SW
306 * 32-bit address space. If so, clip the usable RAM so it doesn't.
307 */
308 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
309 /*
310 * Will wrap back to top of 32-bit space when reservations
311 * are made.
312 */
313 return 0;
314#endif
1938f4a5
SG
315 return gd->ram_top;
316}
317
aabd7ddb
YS
318__weak phys_size_t board_reserve_ram_top(phys_size_t ram_size)
319{
320#ifdef CONFIG_SYS_MEM_TOP_HIDE
321 return ram_size - CONFIG_SYS_MEM_TOP_HIDE;
322#else
323 return ram_size;
324#endif
325}
326
1938f4a5
SG
327static int setup_dest_addr(void)
328{
329 debug("Monitor len: %08lX\n", gd->mon_len);
330 /*
331 * Ram is setup, size stored in gd !!
332 */
333 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
e8149522
YS
334#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
335 /* Reserve memory for secure MMU tables, and/or security monitor */
336 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
337 /*
338 * Record secure memory location. Need recalcuate if memory splits
339 * into banks, or the ram base is not zero.
340 */
341 gd->secure_ram = gd->ram_size;
342#endif
1938f4a5
SG
343 /*
344 * Subtract specified amount of memory to hide so that it won't
345 * get "touched" at all by U-Boot. By fixing up gd->ram_size
346 * the Linux kernel should now get passed the now "corrected"
aabd7ddb
YS
347 * memory size and won't touch it either. This has been used
348 * by arch/powerpc exclusively. Now ARMv8 takes advantage of
349 * thie mechanism. If memory is split into banks, addresses
350 * need to be calculated.
1938f4a5 351 */
aabd7ddb
YS
352 gd->ram_size = board_reserve_ram_top(gd->ram_size);
353
1938f4a5
SG
354#ifdef CONFIG_SYS_SDRAM_BASE
355 gd->ram_top = CONFIG_SYS_SDRAM_BASE;
356#endif
e4fef6cf 357 gd->ram_top += get_effective_memsize();
1938f4a5 358 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
a0ba279a 359 gd->relocaddr = gd->ram_top;
1938f4a5 360 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
ec3b4820 361#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
e4fef6cf
SG
362 /*
363 * We need to make sure the location we intend to put secondary core
364 * boot code is reserved and not used by any part of u-boot
365 */
a0ba279a
MY
366 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
367 gd->relocaddr = determine_mp_bootpg(NULL);
368 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
e4fef6cf
SG
369 }
370#endif
1938f4a5
SG
371 return 0;
372}
373
1e85ccec
FR
374#if defined(CONFIG_SPARC)
375static int reserve_prom(void)
376{
377 /* defined in arch/sparc/cpu/leon?/prom.c */
378 extern void *__prom_start_reloc;
379 int size = 8192; /* page table = 2k, prom = 6k */
380 gd->relocaddr -= size;
381 __prom_start_reloc = map_sysmem(gd->relocaddr + 2048, size - 2048);
382 debug("Reserving %dk for PROM and page table at %08lx\n", size,
383 gd->relocaddr);
384 return 0;
385}
386#endif
387
1938f4a5
SG
388#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
389static int reserve_logbuffer(void)
390{
391 /* reserve kernel log buffer */
a0ba279a 392 gd->relocaddr -= LOGBUFF_RESERVE;
1938f4a5 393 debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
a0ba279a 394 gd->relocaddr);
1938f4a5
SG
395 return 0;
396}
397#endif
398
399#ifdef CONFIG_PRAM
400/* reserve protected RAM */
401static int reserve_pram(void)
402{
403 ulong reg;
404
405 reg = getenv_ulong("pram", 10, CONFIG_PRAM);
a0ba279a 406 gd->relocaddr -= (reg << 10); /* size is in kB */
1938f4a5 407 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
a0ba279a 408 gd->relocaddr);
1938f4a5
SG
409 return 0;
410}
411#endif /* CONFIG_PRAM */
412
413/* Round memory pointer down to next 4 kB limit */
414static int reserve_round_4k(void)
415{
a0ba279a 416 gd->relocaddr &= ~(4096 - 1);
1938f4a5
SG
417 return 0;
418}
419
420#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
421 defined(CONFIG_ARM)
422static int reserve_mmu(void)
423{
424 /* reserve TLB table */
cce6be7f 425 gd->arch.tlb_size = PGTABLE_SIZE;
a0ba279a 426 gd->relocaddr -= gd->arch.tlb_size;
1938f4a5
SG
427
428 /* round down to next 64 kB limit */
a0ba279a 429 gd->relocaddr &= ~(0x10000 - 1);
1938f4a5 430
a0ba279a 431 gd->arch.tlb_addr = gd->relocaddr;
1938f4a5
SG
432 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
433 gd->arch.tlb_addr + gd->arch.tlb_size);
434 return 0;
435}
436#endif
437
5a541945
SG
438#ifdef CONFIG_DM_VIDEO
439static int reserve_video(void)
440{
441 ulong addr;
442 int ret;
443
444 addr = gd->relocaddr;
445 ret = video_reserve(&addr);
446 if (ret)
447 return ret;
448 gd->relocaddr = addr;
449
450 return 0;
451}
452#else
453
454# ifdef CONFIG_LCD
1938f4a5
SG
455static int reserve_lcd(void)
456{
5a541945 457# ifdef CONFIG_FB_ADDR
1938f4a5 458 gd->fb_base = CONFIG_FB_ADDR;
5a541945 459# else
1938f4a5 460 /* reserve memory for LCD display (always full pages) */
a0ba279a
MY
461 gd->relocaddr = lcd_setmem(gd->relocaddr);
462 gd->fb_base = gd->relocaddr;
5a541945
SG
463# endif /* CONFIG_FB_ADDR */
464
1938f4a5
SG
465 return 0;
466}
5a541945 467# endif /* CONFIG_LCD */
1938f4a5 468
5a541945 469# if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \
d54d7eb9 470 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
944ab340 471 !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K)
8703ef3f 472static int reserve_legacy_video(void)
e4fef6cf
SG
473{
474 /* reserve memory for video display (always full pages) */
a0ba279a
MY
475 gd->relocaddr = video_setmem(gd->relocaddr);
476 gd->fb_base = gd->relocaddr;
e4fef6cf
SG
477
478 return 0;
479}
5a541945
SG
480# endif
481#endif /* !CONFIG_DM_VIDEO */
e4fef6cf 482
8703ef3f
SG
483static int reserve_trace(void)
484{
485#ifdef CONFIG_TRACE
486 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
487 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
488 debug("Reserving %dk for trace data at: %08lx\n",
489 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
490#endif
491
492 return 0;
493}
494
1938f4a5
SG
495static int reserve_uboot(void)
496{
497 /*
498 * reserve memory for U-Boot code, data & bss
499 * round down to next 4 kB limit
500 */
a0ba279a
MY
501 gd->relocaddr -= gd->mon_len;
502 gd->relocaddr &= ~(4096 - 1);
e4fef6cf
SG
503#ifdef CONFIG_E500
504 /* round down to next 64 kB limit so that IVPR stays aligned */
a0ba279a 505 gd->relocaddr &= ~(65536 - 1);
e4fef6cf 506#endif
1938f4a5
SG
507
508 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10,
a0ba279a
MY
509 gd->relocaddr);
510
511 gd->start_addr_sp = gd->relocaddr;
512
1938f4a5
SG
513 return 0;
514}
515
8cae8a68 516#ifndef CONFIG_SPL_BUILD
1938f4a5
SG
517/* reserve memory for malloc() area */
518static int reserve_malloc(void)
519{
a0ba279a 520 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
1938f4a5 521 debug("Reserving %dk for malloc() at: %08lx\n",
a0ba279a 522 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
1938f4a5
SG
523 return 0;
524}
525
526/* (permanently) allocate a Board Info struct */
527static int reserve_board(void)
528{
d54d7eb9
SZ
529 if (!gd->bd) {
530 gd->start_addr_sp -= sizeof(bd_t);
531 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
532 memset(gd->bd, '\0', sizeof(bd_t));
533 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
534 sizeof(bd_t), gd->start_addr_sp);
535 }
1938f4a5
SG
536 return 0;
537}
8cae8a68 538#endif
1938f4a5
SG
539
540static int setup_machine(void)
541{
542#ifdef CONFIG_MACH_TYPE
543 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
544#endif
545 return 0;
546}
547
548static int reserve_global_data(void)
549{
a0ba279a
MY
550 gd->start_addr_sp -= sizeof(gd_t);
551 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
1938f4a5 552 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
a0ba279a 553 sizeof(gd_t), gd->start_addr_sp);
1938f4a5
SG
554 return 0;
555}
556
557static int reserve_fdt(void)
558{
e9acb9ea 559#ifndef CONFIG_OF_EMBED
1938f4a5 560 /*
4c509343 561 * If the device tree is sitting immediately above our image then we
1938f4a5
SG
562 * must relocate it. If it is embedded in the data section, then it
563 * will be relocated with other data.
564 */
565 if (gd->fdt_blob) {
566 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
567
a0ba279a
MY
568 gd->start_addr_sp -= gd->fdt_size;
569 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
a733b06b 570 debug("Reserving %lu Bytes for FDT at: %08lx\n",
a0ba279a 571 gd->fdt_size, gd->start_addr_sp);
1938f4a5 572 }
e9acb9ea 573#endif
1938f4a5
SG
574
575 return 0;
576}
577
68145d4c 578int arch_reserve_stacks(void)
1938f4a5 579{
68145d4c
AB
580 return 0;
581}
8cae8a68 582
68145d4c
AB
583static int reserve_stacks(void)
584{
585 /* make stack pointer 16-byte aligned */
a0ba279a
MY
586 gd->start_addr_sp -= 16;
587 gd->start_addr_sp &= ~0xf;
1938f4a5
SG
588
589 /*
4c509343 590 * let the architecture-specific code tailor gd->start_addr_sp and
68145d4c 591 * gd->irq_sp
1938f4a5 592 */
68145d4c 593 return arch_reserve_stacks();
1938f4a5
SG
594}
595
596static int display_new_sp(void)
597{
a0ba279a 598 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
1938f4a5
SG
599
600 return 0;
601}
602
fb3db635 603#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
e4fef6cf
SG
604static int setup_board_part1(void)
605{
606 bd_t *bd = gd->bd;
607
608 /*
609 * Save local variables to board info struct
610 */
e4fef6cf
SG
611 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
612 bd->bi_memsize = gd->ram_size; /* size in bytes */
613
614#ifdef CONFIG_SYS_SRAM_BASE
615 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
616 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
617#endif
618
58dac327 619#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \
e4fef6cf
SG
620 defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
621 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
622#endif
e310b93e 623#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
e4fef6cf
SG
624 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
625#endif
626#if defined(CONFIG_MPC83xx)
627 bd->bi_immrbar = CONFIG_SYS_IMMR;
628#endif
e4fef6cf
SG
629
630 return 0;
631}
fb3db635 632#endif
e4fef6cf 633
fb3db635 634#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
e4fef6cf
SG
635static int setup_board_part2(void)
636{
637 bd_t *bd = gd->bd;
638
639 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
640 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
641#if defined(CONFIG_CPM2)
642 bd->bi_cpmfreq = gd->arch.cpm_clk;
643 bd->bi_brgfreq = gd->arch.brg_clk;
644 bd->bi_sccfreq = gd->arch.scc_clk;
645 bd->bi_vco = gd->arch.vco_out;
646#endif /* CONFIG_CPM2 */
647#if defined(CONFIG_MPC512X)
648 bd->bi_ipsfreq = gd->arch.ips_clk;
649#endif /* CONFIG_MPC512X */
650#if defined(CONFIG_MPC5xxx)
651 bd->bi_ipbfreq = gd->arch.ipb_clk;
652 bd->bi_pcifreq = gd->pci_clk;
653#endif /* CONFIG_MPC5xxx */
1313db48
AW
654#if defined(CONFIG_M68K) && defined(CONFIG_PCI)
655 bd->bi_pcifreq = gd->pci_clk;
656#endif
657#if defined(CONFIG_EXTRA_CLOCK)
658 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
659 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
660 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
661#endif
e4fef6cf
SG
662
663 return 0;
664}
665#endif
666
667#ifdef CONFIG_SYS_EXTBDINFO
668static int setup_board_extra(void)
669{
670 bd_t *bd = gd->bd;
671
672 strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
673 strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,
674 sizeof(bd->bi_r_version));
675
676 bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
677 bd->bi_plb_busfreq = gd->bus_clk;
678#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
679 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
680 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
681 bd->bi_pci_busfreq = get_PCI_freq();
682 bd->bi_opbfreq = get_OPB_freq();
683#elif defined(CONFIG_XILINX_405)
684 bd->bi_pci_busfreq = get_PCI_freq();
685#endif
686
687 return 0;
688}
689#endif
690
1938f4a5
SG
691#ifdef CONFIG_POST
692static int init_post(void)
693{
694 post_bootmode_init();
695 post_run(NULL, POST_ROM | post_bootmode_get(0));
696
697 return 0;
698}
699#endif
700
1938f4a5
SG
701static int setup_dram_config(void)
702{
703 /* Ram is board specific, so move it to board code ... */
704 dram_init_banksize();
705
706 return 0;
707}
708
709static int reloc_fdt(void)
710{
e9acb9ea 711#ifndef CONFIG_OF_EMBED
f05ad9ba
SG
712 if (gd->flags & GD_FLG_SKIP_RELOC)
713 return 0;
1938f4a5
SG
714 if (gd->new_fdt) {
715 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
716 gd->fdt_blob = gd->new_fdt;
717 }
e9acb9ea 718#endif
1938f4a5
SG
719
720 return 0;
721}
722
723static int setup_reloc(void)
724{
f05ad9ba
SG
725 if (gd->flags & GD_FLG_SKIP_RELOC) {
726 debug("Skipping relocation due to flag\n");
727 return 0;
728 }
729
d54d7eb9 730#ifdef CONFIG_SYS_TEXT_BASE
a0ba279a 731 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
e310b93e 732#ifdef CONFIG_M68K
733 /*
734 * On all ColdFire arch cpu, monitor code starts always
735 * just after the default vector table location, so at 0x400
736 */
737 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
738#endif
d54d7eb9 739#endif
1938f4a5
SG
740 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
741
742 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
a733b06b 743 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
a0ba279a
MY
744 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
745 gd->start_addr_sp);
1938f4a5
SG
746
747 return 0;
748}
749
750/* ARM calls relocate_code from its crt0.S */
808434cd 751#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
1938f4a5
SG
752
753static int jump_to_copy(void)
754{
f05ad9ba
SG
755 if (gd->flags & GD_FLG_SKIP_RELOC)
756 return 0;
48a33806
SG
757 /*
758 * x86 is special, but in a nice way. It uses a trampoline which
759 * enables the dcache if possible.
760 *
761 * For now, other archs use relocate_code(), which is implemented
762 * similarly for all archs. When we do generic relocation, hopefully
763 * we can make all archs enable the dcache prior to relocation.
764 */
3fb80163 765#if defined(CONFIG_X86) || defined(CONFIG_ARC)
48a33806
SG
766 /*
767 * SDRAM and console are now initialised. The final stack can now
768 * be setup in SDRAM. Code execution will continue in Flash, but
769 * with the stack in SDRAM and Global Data in temporary memory
770 * (CPU cache)
771 */
f0c7d9c7 772 arch_setup_gd(gd->new_gd);
48a33806
SG
773 board_init_f_r_trampoline(gd->start_addr_sp);
774#else
a0ba279a 775 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
48a33806 776#endif
1938f4a5
SG
777
778 return 0;
779}
780#endif
781
782/* Record the board_init_f() bootstage (after arch_cpu_init()) */
783static int mark_bootstage(void)
784{
785 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
786
787 return 0;
788}
789
9854a874
SG
790static int initf_console_record(void)
791{
792#if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F_LEN)
793 return console_record_init();
794#else
795 return 0;
796#endif
797}
798
ab7cd627
SG
799static int initf_dm(void)
800{
801#if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN)
802 int ret;
803
804 ret = dm_init_and_scan(true);
805 if (ret)
806 return ret;
807#endif
808
809 return 0;
810}
811
146251f8
SG
812/* Architecture-specific memory reservation */
813__weak int reserve_arch(void)
814{
815 return 0;
816}
817
d4c671cc
SG
818__weak int arch_cpu_init_dm(void)
819{
820 return 0;
821}
822
1938f4a5 823static init_fnc_t init_sequence_f[] = {
a733b06b
SG
824#ifdef CONFIG_SANDBOX
825 setup_ram_buf,
e4fef6cf 826#endif
1938f4a5 827 setup_mon_len,
b45122fd 828#ifdef CONFIG_OF_CONTROL
0879361f 829 fdtdec_setup,
b45122fd 830#endif
d210718d 831#ifdef CONFIG_TRACE
71c52dba 832 trace_early_init,
d210718d 833#endif
768e0f52 834 initf_malloc,
9854a874 835 initf_console_record,
e4fef6cf
SG
836#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
837 /* TODO: can this go into arch_cpu_init()? */
838 probecpu,
a52a068e
BM
839#endif
840#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
841 x86_fsp_init,
e4fef6cf 842#endif
1938f4a5 843 arch_cpu_init, /* basic arch cpu dependent setup */
3ea0953d 844 initf_dm,
d4c671cc 845 arch_cpu_init_dm,
67521957 846 mark_bootstage, /* need timer, go after init dm */
1938f4a5
SG
847#if defined(CONFIG_BOARD_EARLY_INIT_F)
848 board_early_init_f,
849#endif
e4fef6cf
SG
850 /* TODO: can any of this go into arch_cpu_init()? */
851#if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT)
852 get_clocks, /* get CPU and bus clocks (etc.) */
853#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
854 && !defined(CONFIG_TQM885D)
855 adjust_sdram_tbs_8xx,
856#endif
857 /* TODO: can we rename this to timer_init()? */
858 init_timebase,
859#endif
2317cf09 860#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
c97088c3
FR
861 defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
862 defined(CONFIG_SPARC)
1938f4a5 863 timer_init, /* initialize timer */
e4fef6cf 864#endif
e4fef6cf
SG
865#ifdef CONFIG_SYS_ALLOC_DPRAM
866#if !defined(CONFIG_CPM2)
867 dpram_init,
868#endif
869#endif
870#if defined(CONFIG_BOARD_POSTCLK_INIT)
871 board_postclk_init,
b8521b74 872#endif
7664846b 873#if defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
e310b93e 874 get_clocks,
1938f4a5
SG
875#endif
876 env_init, /* initialize environment */
e4fef6cf
SG
877#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
878 /* get CPU and bus clocks according to the environment variable */
879 get_clocks_866,
880 /* adjust sdram refresh rate according to the new clock */
881 sdram_adjust_866,
882 init_timebase,
883#endif
1938f4a5
SG
884 init_baud_rate, /* initialze baudrate settings */
885 serial_init, /* serial communications setup */
886 console_init_f, /* stage 1 init of console */
a733b06b
SG
887#ifdef CONFIG_SANDBOX
888 sandbox_early_getopt_check,
889#endif
890#ifdef CONFIG_OF_CONTROL
891 fdtdec_prepare_fdt,
48a33806 892#endif
1938f4a5
SG
893 display_options, /* say that we are here */
894 display_text_info, /* show debugging info if required */
58dac327 895#if defined(CONFIG_MPC8260)
e4fef6cf
SG
896 prt_8260_rsr,
897 prt_8260_clks,
58dac327 898#endif /* CONFIG_MPC8260 */
e4fef6cf
SG
899#if defined(CONFIG_MPC83xx)
900 prt_83xx_rsr,
901#endif
e310b93e 902#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
e4fef6cf
SG
903 checkcpu,
904#endif
1938f4a5 905 print_cpuinfo, /* display cpu info (and speed) */
e4fef6cf
SG
906#if defined(CONFIG_MPC5xxx)
907 prt_mpc5xxx_clks,
908#endif /* CONFIG_MPC5xxx */
1938f4a5 909#if defined(CONFIG_DISPLAY_BOARDINFO)
0365ffcc 910 show_board_info,
e4fef6cf
SG
911#endif
912 INIT_FUNC_WATCHDOG_INIT
913#if defined(CONFIG_MISC_INIT_F)
914 misc_init_f,
915#endif
916 INIT_FUNC_WATCHDOG_RESET
ea818dbb 917#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
e4fef6cf
SG
918 init_func_i2c,
919#endif
920#if defined(CONFIG_HARD_SPI)
921 init_func_spi,
1938f4a5
SG
922#endif
923 announce_dram_init,
924 /* TODO: unify all these dram functions? */
2e88bb28
KHH
925#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_NDS32) || \
926 defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
1938f4a5
SG
927 dram_init, /* configure available RAM banks */
928#endif
e310b93e 929#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
e4fef6cf
SG
930 init_func_ram,
931#endif
932#ifdef CONFIG_POST
933 post_init_f,
934#endif
935 INIT_FUNC_WATCHDOG_RESET
936#if defined(CONFIG_SYS_DRAM_TEST)
937 testdram,
938#endif /* CONFIG_SYS_DRAM_TEST */
939 INIT_FUNC_WATCHDOG_RESET
940
1938f4a5
SG
941#ifdef CONFIG_POST
942 init_post,
943#endif
e4fef6cf 944 INIT_FUNC_WATCHDOG_RESET
1938f4a5
SG
945 /*
946 * Now that we have DRAM mapped and working, we can
947 * relocate the code and continue running from DRAM.
948 *
949 * Reserve memory at end of RAM for (top down in that order):
950 * - area that won't get touched by U-Boot and Linux (optional)
951 * - kernel log buffer
952 * - protected RAM
953 * - LCD framebuffer
954 * - monitor code
955 * - board info struct
956 */
957 setup_dest_addr,
bbfdff31 958#if defined(CONFIG_BLACKFIN)
d54d7eb9
SZ
959 /* Blackfin u-boot monitor should be on top of the ram */
960 reserve_uboot,
961#endif
1e85ccec
FR
962#if defined(CONFIG_SPARC)
963 reserve_prom,
964#endif
1938f4a5
SG
965#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR)
966 reserve_logbuffer,
967#endif
968#ifdef CONFIG_PRAM
969 reserve_pram,
970#endif
971 reserve_round_4k,
972#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
973 defined(CONFIG_ARM)
974 reserve_mmu,
975#endif
5a541945
SG
976#ifdef CONFIG_DM_VIDEO
977 reserve_video,
978#else
979# ifdef CONFIG_LCD
1938f4a5 980 reserve_lcd,
5a541945 981# endif
e4fef6cf 982 /* TODO: Why the dependency on CONFIG_8xx? */
5a541945 983# if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \
d54d7eb9 984 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
944ab340 985 !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K)
5a541945
SG
986 reserve_legacy_video,
987# endif
988#endif /* CONFIG_DM_VIDEO */
8703ef3f 989 reserve_trace,
bbfdff31 990#if !defined(CONFIG_BLACKFIN)
1938f4a5 991 reserve_uboot,
d54d7eb9 992#endif
8cae8a68 993#ifndef CONFIG_SPL_BUILD
1938f4a5
SG
994 reserve_malloc,
995 reserve_board,
8cae8a68 996#endif
1938f4a5
SG
997 setup_machine,
998 reserve_global_data,
999 reserve_fdt,
146251f8 1000 reserve_arch,
1938f4a5
SG
1001 reserve_stacks,
1002 setup_dram_config,
1003 show_dram_config,
fb3db635 1004#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS)
e4fef6cf 1005 setup_board_part1,
fb3db635
DS
1006#endif
1007#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
e4fef6cf
SG
1008 INIT_FUNC_WATCHDOG_RESET
1009 setup_board_part2,
1010#endif
1938f4a5 1011 display_new_sp,
e4fef6cf
SG
1012#ifdef CONFIG_SYS_EXTBDINFO
1013 setup_board_extra,
1014#endif
1015 INIT_FUNC_WATCHDOG_RESET
1938f4a5
SG
1016 reloc_fdt,
1017 setup_reloc,
3fb80163 1018#if defined(CONFIG_X86) || defined(CONFIG_ARC)
313aef37
SG
1019 copy_uboot_to_ram,
1020 clear_bss,
1021 do_elf_reloc_fixups,
1022#endif
808434cd 1023#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
1938f4a5
SG
1024 jump_to_copy,
1025#endif
1026 NULL,
1027};
1028
1029void board_init_f(ulong boot_flags)
1030{
2a1680e3
YS
1031#ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA
1032 /*
1033 * For some archtectures, global data is initialized and used before
1034 * calling this function. The data should be preserved. For others,
1035 * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack
1036 * here to host global data until relocation.
1037 */
1938f4a5
SG
1038 gd_t data;
1039
1040 gd = &data;
1041
cce6be7f
DF
1042 /*
1043 * Clear global data before it is accessed at debug print
1044 * in initcall_run_list. Otherwise the debug print probably
1045 * get the wrong vaule of gd->have_console.
1046 */
cce6be7f
DF
1047 zero_global_data();
1048#endif
1049
1938f4a5 1050 gd->flags = boot_flags;
9aed5a27 1051 gd->have_console = 0;
1938f4a5
SG
1052
1053 if (initcall_run_list(init_sequence_f))
1054 hang();
1055
9b217498
BS
1056#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
1057 !defined(CONFIG_EFI_APP)
1938f4a5
SG
1058 /* NOTREACHED - jump_to_copy() does not return */
1059 hang();
1060#endif
1061}
1062
3fb80163 1063#if defined(CONFIG_X86) || defined(CONFIG_ARC)
48a33806
SG
1064/*
1065 * For now this code is only used on x86.
1066 *
1067 * init_sequence_f_r is the list of init functions which are run when
1068 * U-Boot is executing from Flash with a semi-limited 'C' environment.
1069 * The following limitations must be considered when implementing an
1070 * '_f_r' function:
1071 * - 'static' variables are read-only
1072 * - Global Data (gd->xxx) is read/write
1073 *
1074 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1075 * supported). It _should_, if possible, copy global data to RAM and
1076 * initialise the CPU caches (to speed up the relocation process)
1077 *
1078 * NOTE: At present only x86 uses this route, but it is intended that
1079 * all archs will move to this when generic relocation is implemented.
1080 */
1081static init_fnc_t init_sequence_f_r[] = {
1082 init_cache_f_r,
48a33806
SG
1083
1084 NULL,
1085};
1086
1087void board_init_f_r(void)
1088{
1089 if (initcall_run_list(init_sequence_f_r))
1090 hang();
1091
1092 /*
1093 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1094 * Transfer execution from Flash to RAM by calculating the address
1095 * of the in-RAM copy of board_init_r() and calling it
1096 */
7bf9f20d 1097 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
48a33806
SG
1098
1099 /* NOTREACHED - board_init_r() does not return */
1100 hang();
1101}
5bcd19aa 1102#endif /* CONFIG_X86 */