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Commit | Line | Data |
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1938f4a5 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2002-2006 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Marius Groeger <mgroeger@sysgo.de> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
11 | */ |
12 | ||
13 | #include <common.h> | |
14 | #include <linux/compiler.h> | |
15 | #include <version.h> | |
16 | #include <environment.h> | |
ab7cd627 | 17 | #include <dm.h> |
1938f4a5 | 18 | #include <fdtdec.h> |
f828bf25 | 19 | #include <fs.h> |
e4fef6cf SG |
20 | #if defined(CONFIG_CMD_IDE) |
21 | #include <ide.h> | |
22 | #endif | |
23 | #include <i2c.h> | |
1938f4a5 SG |
24 | #include <initcall.h> |
25 | #include <logbuff.h> | |
e4fef6cf SG |
26 | |
27 | /* TODO: Can we move these into arch/ headers? */ | |
28 | #ifdef CONFIG_8xx | |
29 | #include <mpc8xx.h> | |
30 | #endif | |
31 | #ifdef CONFIG_5xx | |
32 | #include <mpc5xx.h> | |
33 | #endif | |
34 | #ifdef CONFIG_MPC5xxx | |
35 | #include <mpc5xxx.h> | |
36 | #endif | |
ec3b4820 | 37 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
a76df709 GH |
38 | #include <asm/mp.h> |
39 | #endif | |
e4fef6cf | 40 | |
a733b06b | 41 | #include <os.h> |
1938f4a5 | 42 | #include <post.h> |
e4fef6cf | 43 | #include <spi.h> |
c5d4001a | 44 | #include <status_led.h> |
71c52dba | 45 | #include <trace.h> |
e4fef6cf | 46 | #include <watchdog.h> |
a733b06b | 47 | #include <asm/errno.h> |
1938f4a5 SG |
48 | #include <asm/io.h> |
49 | #include <asm/sections.h> | |
3fb80163 | 50 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
51 | #include <asm/init_helpers.h> |
52 | #include <asm/relocate.h> | |
53 | #endif | |
a733b06b SG |
54 | #ifdef CONFIG_SANDBOX |
55 | #include <asm/state.h> | |
56 | #endif | |
ab7cd627 | 57 | #include <dm/root.h> |
1938f4a5 SG |
58 | #include <linux/compiler.h> |
59 | ||
60 | /* | |
61 | * Pointer to initial global data area | |
62 | * | |
63 | * Here we initialize it if needed. | |
64 | */ | |
65 | #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR | |
66 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
67 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
68 | DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); | |
69 | #else | |
70 | DECLARE_GLOBAL_DATA_PTR; | |
71 | #endif | |
72 | ||
73 | /* | |
74 | * sjg: IMO this code should be | |
75 | * refactored to a single function, something like: | |
76 | * | |
77 | * void led_set_state(enum led_colour_t colour, int on); | |
78 | */ | |
79 | /************************************************************************ | |
80 | * Coloured LED functionality | |
81 | ************************************************************************ | |
82 | * May be supplied by boards if desired | |
83 | */ | |
c5d4001a JH |
84 | __weak void coloured_LED_init(void) {} |
85 | __weak void red_led_on(void) {} | |
86 | __weak void red_led_off(void) {} | |
87 | __weak void green_led_on(void) {} | |
88 | __weak void green_led_off(void) {} | |
89 | __weak void yellow_led_on(void) {} | |
90 | __weak void yellow_led_off(void) {} | |
91 | __weak void blue_led_on(void) {} | |
92 | __weak void blue_led_off(void) {} | |
1938f4a5 SG |
93 | |
94 | /* | |
95 | * Why is gd allocated a register? Prior to reloc it might be better to | |
96 | * just pass it around to each function in this file? | |
97 | * | |
98 | * After reloc one could argue that it is hardly used and doesn't need | |
99 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
100 | * global data for all modules, so that post-reloc we can avoid the massive | |
101 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
102 | * a structure... | |
103 | */ | |
104 | ||
105 | /* | |
106 | * Could the CONFIG_SPL_BUILD infection become a flag in gd? | |
107 | */ | |
108 | ||
d54d7eb9 | 109 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) |
e4fef6cf SG |
110 | static int init_func_watchdog_init(void) |
111 | { | |
d54d7eb9 SZ |
112 | # if defined(CONFIG_HW_WATCHDOG) && (defined(CONFIG_BLACKFIN) || \ |
113 | defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ | |
14a380a8 SR |
114 | defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ |
115 | defined(CONFIG_IMX_WATCHDOG)) | |
d54d7eb9 SZ |
116 | hw_watchdog_init(); |
117 | # endif | |
e4fef6cf SG |
118 | puts(" Watchdog enabled\n"); |
119 | WATCHDOG_RESET(); | |
120 | ||
121 | return 0; | |
122 | } | |
123 | ||
124 | int init_func_watchdog_reset(void) | |
125 | { | |
126 | WATCHDOG_RESET(); | |
127 | ||
128 | return 0; | |
129 | } | |
130 | #endif /* CONFIG_WATCHDOG */ | |
131 | ||
dd2a6cd0 | 132 | __weak void board_add_ram_info(int use_default) |
e4fef6cf SG |
133 | { |
134 | /* please define platform specific board_add_ram_info() */ | |
135 | } | |
136 | ||
1938f4a5 SG |
137 | static int init_baud_rate(void) |
138 | { | |
139 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); | |
140 | return 0; | |
141 | } | |
142 | ||
143 | static int display_text_info(void) | |
144 | { | |
a733b06b | 145 | #ifndef CONFIG_SANDBOX |
9fdee7d7 | 146 | ulong bss_start, bss_end, text_base; |
1938f4a5 | 147 | |
632efa74 SG |
148 | bss_start = (ulong)&__bss_start; |
149 | bss_end = (ulong)&__bss_end; | |
b60eff31 | 150 | |
d54d7eb9 | 151 | #ifdef CONFIG_SYS_TEXT_BASE |
9fdee7d7 | 152 | text_base = CONFIG_SYS_TEXT_BASE; |
d54d7eb9 | 153 | #else |
9fdee7d7 | 154 | text_base = CONFIG_SYS_MONITOR_BASE; |
d54d7eb9 | 155 | #endif |
9fdee7d7 DS |
156 | |
157 | debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", | |
158 | text_base, bss_start, bss_end); | |
a733b06b | 159 | #endif |
1938f4a5 SG |
160 | |
161 | #ifdef CONFIG_MODEM_SUPPORT | |
162 | debug("Modem Support enabled\n"); | |
163 | #endif | |
164 | #ifdef CONFIG_USE_IRQ | |
165 | debug("IRQ Stack: %08lx\n", IRQ_STACK_START); | |
166 | debug("FIQ Stack: %08lx\n", FIQ_STACK_START); | |
167 | #endif | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | static int announce_dram_init(void) | |
173 | { | |
174 | puts("DRAM: "); | |
175 | return 0; | |
176 | } | |
177 | ||
e310b93e | 178 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
179 | static int init_func_ram(void) |
180 | { | |
181 | #ifdef CONFIG_BOARD_TYPES | |
182 | int board_type = gd->board_type; | |
183 | #else | |
184 | int board_type = 0; /* use dummy arg */ | |
185 | #endif | |
186 | ||
187 | gd->ram_size = initdram(board_type); | |
188 | ||
189 | if (gd->ram_size > 0) | |
190 | return 0; | |
191 | ||
192 | puts("*** failed ***\n"); | |
193 | return 1; | |
194 | } | |
195 | #endif | |
196 | ||
1938f4a5 SG |
197 | static int show_dram_config(void) |
198 | { | |
fa39ffe5 | 199 | unsigned long long size; |
1938f4a5 SG |
200 | |
201 | #ifdef CONFIG_NR_DRAM_BANKS | |
202 | int i; | |
203 | ||
204 | debug("\nRAM Configuration:\n"); | |
205 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
206 | size += gd->bd->bi_dram[i].size; | |
207 | debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); | |
208 | #ifdef DEBUG | |
209 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
210 | #endif | |
211 | } | |
212 | debug("\nDRAM: "); | |
213 | #else | |
214 | size = gd->ram_size; | |
215 | #endif | |
216 | ||
e4fef6cf SG |
217 | print_size(size, ""); |
218 | board_add_ram_info(0); | |
219 | putc('\n'); | |
1938f4a5 SG |
220 | |
221 | return 0; | |
222 | } | |
223 | ||
dd2a6cd0 | 224 | __weak void dram_init_banksize(void) |
1938f4a5 SG |
225 | { |
226 | #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) | |
227 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
228 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
229 | #endif | |
230 | } | |
231 | ||
ea818dbb | 232 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
233 | static int init_func_i2c(void) |
234 | { | |
235 | puts("I2C: "); | |
815a76f2 | 236 | #ifdef CONFIG_SYS_I2C |
237 | i2c_init_all(); | |
238 | #else | |
e4fef6cf | 239 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
815a76f2 | 240 | #endif |
e4fef6cf SG |
241 | puts("ready\n"); |
242 | return 0; | |
243 | } | |
244 | #endif | |
245 | ||
246 | #if defined(CONFIG_HARD_SPI) | |
247 | static int init_func_spi(void) | |
248 | { | |
249 | puts("SPI: "); | |
250 | spi_init(); | |
251 | puts("ready\n"); | |
252 | return 0; | |
253 | } | |
254 | #endif | |
255 | ||
256 | __maybe_unused | |
1938f4a5 SG |
257 | static int zero_global_data(void) |
258 | { | |
259 | memset((void *)gd, '\0', sizeof(gd_t)); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | static int setup_mon_len(void) | |
265 | { | |
e945f6dc | 266 | #if defined(__ARM__) || defined(__MICROBLAZE__) |
b60eff31 | 267 | gd->mon_len = (ulong)&__bss_end - (ulong)_start; |
a733b06b SG |
268 | #elif defined(CONFIG_SANDBOX) |
269 | gd->mon_len = (ulong)&_end - (ulong)_init; | |
5ff10aa7 | 270 | #elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) |
d54d7eb9 | 271 | gd->mon_len = CONFIG_SYS_MONITOR_LEN; |
632efa74 | 272 | #else |
e4fef6cf SG |
273 | /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ |
274 | gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 275 | #endif |
1938f4a5 SG |
276 | return 0; |
277 | } | |
278 | ||
279 | __weak int arch_cpu_init(void) | |
280 | { | |
281 | return 0; | |
282 | } | |
283 | ||
f828bf25 SG |
284 | #ifdef CONFIG_OF_HOSTFILE |
285 | ||
f828bf25 SG |
286 | static int read_fdt_from_file(void) |
287 | { | |
288 | struct sandbox_state *state = state_get_current(); | |
95fac6ab | 289 | const char *fname = state->fdt_fname; |
f828bf25 | 290 | void *blob; |
96b1046d | 291 | loff_t size; |
f828bf25 | 292 | int err; |
95fac6ab | 293 | int fd; |
f828bf25 SG |
294 | |
295 | blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0); | |
296 | if (!state->fdt_fname) { | |
95fac6ab | 297 | err = fdt_create_empty_tree(blob, 256); |
f828bf25 SG |
298 | if (!err) |
299 | goto done; | |
95fac6ab SG |
300 | printf("Unable to create empty FDT: %s\n", fdt_strerror(err)); |
301 | return -EINVAL; | |
302 | } | |
303 | ||
96b1046d SR |
304 | err = os_get_filesize(fname, &size); |
305 | if (err < 0) { | |
95fac6ab | 306 | printf("Failed to file FDT file '%s'\n", fname); |
96b1046d | 307 | return err; |
95fac6ab SG |
308 | } |
309 | fd = os_open(fname, OS_O_RDONLY); | |
310 | if (fd < 0) { | |
311 | printf("Failed to open FDT file '%s'\n", fname); | |
312 | return -EACCES; | |
f828bf25 | 313 | } |
95fac6ab SG |
314 | if (os_read(fd, blob, size) != size) { |
315 | os_close(fd); | |
f828bf25 | 316 | return -EIO; |
95fac6ab SG |
317 | } |
318 | os_close(fd); | |
f828bf25 SG |
319 | |
320 | done: | |
321 | gd->fdt_blob = blob; | |
322 | ||
323 | return 0; | |
324 | } | |
325 | #endif | |
326 | ||
a733b06b SG |
327 | #ifdef CONFIG_SANDBOX |
328 | static int setup_ram_buf(void) | |
329 | { | |
5c2859cd SG |
330 | struct sandbox_state *state = state_get_current(); |
331 | ||
332 | gd->arch.ram_buf = state->ram_buf; | |
333 | gd->ram_size = state->ram_size; | |
a733b06b SG |
334 | |
335 | return 0; | |
336 | } | |
337 | #endif | |
338 | ||
1938f4a5 SG |
339 | static int setup_fdt(void) |
340 | { | |
c970dffe MY |
341 | #ifdef CONFIG_OF_CONTROL |
342 | # ifdef CONFIG_OF_EMBED | |
1938f4a5 | 343 | /* Get a pointer to the FDT */ |
6ab6b2af | 344 | gd->fdt_blob = __dtb_dt_begin; |
c970dffe | 345 | # elif defined CONFIG_OF_SEPARATE |
1938f4a5 | 346 | /* FDT is at end of image */ |
632efa74 | 347 | gd->fdt_blob = (ulong *)&_end; |
c970dffe | 348 | # elif defined(CONFIG_OF_HOSTFILE) |
f828bf25 SG |
349 | if (read_fdt_from_file()) { |
350 | puts("Failed to read control FDT\n"); | |
351 | return -1; | |
352 | } | |
c970dffe | 353 | # endif |
1938f4a5 SG |
354 | /* Allow the early environment to override the fdt address */ |
355 | gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, | |
356 | (uintptr_t)gd->fdt_blob); | |
c970dffe | 357 | #endif |
1938f4a5 SG |
358 | return 0; |
359 | } | |
360 | ||
361 | /* Get the top of usable RAM */ | |
362 | __weak ulong board_get_usable_ram_top(ulong total_size) | |
363 | { | |
1e4d11a5 SW |
364 | #ifdef CONFIG_SYS_SDRAM_BASE |
365 | /* | |
366 | * Detect whether we have so much RAM it goes past the end of our | |
367 | * 32-bit address space. If so, clip the usable RAM so it doesn't. | |
368 | */ | |
369 | if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) | |
370 | /* | |
371 | * Will wrap back to top of 32-bit space when reservations | |
372 | * are made. | |
373 | */ | |
374 | return 0; | |
375 | #endif | |
1938f4a5 SG |
376 | return gd->ram_top; |
377 | } | |
378 | ||
379 | static int setup_dest_addr(void) | |
380 | { | |
381 | debug("Monitor len: %08lX\n", gd->mon_len); | |
382 | /* | |
383 | * Ram is setup, size stored in gd !! | |
384 | */ | |
385 | debug("Ram size: %08lX\n", (ulong)gd->ram_size); | |
386 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) | |
387 | /* | |
388 | * Subtract specified amount of memory to hide so that it won't | |
389 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
390 | * the Linux kernel should now get passed the now "corrected" | |
391 | * memory size and won't touch it either. This should work | |
392 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
393 | * arch/powerpc with bootwrapper support, that recalculate the | |
394 | * memory size from the SDRAM controller setup will have to | |
395 | * get fixed. | |
396 | */ | |
397 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; | |
398 | #endif | |
399 | #ifdef CONFIG_SYS_SDRAM_BASE | |
400 | gd->ram_top = CONFIG_SYS_SDRAM_BASE; | |
401 | #endif | |
e4fef6cf | 402 | gd->ram_top += get_effective_memsize(); |
1938f4a5 | 403 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 404 | gd->relocaddr = gd->ram_top; |
1938f4a5 | 405 | debug("Ram top: %08lX\n", (ulong)gd->ram_top); |
ec3b4820 | 406 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
e4fef6cf SG |
407 | /* |
408 | * We need to make sure the location we intend to put secondary core | |
409 | * boot code is reserved and not used by any part of u-boot | |
410 | */ | |
a0ba279a MY |
411 | if (gd->relocaddr > determine_mp_bootpg(NULL)) { |
412 | gd->relocaddr = determine_mp_bootpg(NULL); | |
413 | debug("Reserving MP boot page to %08lx\n", gd->relocaddr); | |
e4fef6cf SG |
414 | } |
415 | #endif | |
1938f4a5 SG |
416 | return 0; |
417 | } | |
418 | ||
419 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) | |
420 | static int reserve_logbuffer(void) | |
421 | { | |
422 | /* reserve kernel log buffer */ | |
a0ba279a | 423 | gd->relocaddr -= LOGBUFF_RESERVE; |
1938f4a5 | 424 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
a0ba279a | 425 | gd->relocaddr); |
1938f4a5 SG |
426 | return 0; |
427 | } | |
428 | #endif | |
429 | ||
430 | #ifdef CONFIG_PRAM | |
431 | /* reserve protected RAM */ | |
432 | static int reserve_pram(void) | |
433 | { | |
434 | ulong reg; | |
435 | ||
436 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); | |
a0ba279a | 437 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 438 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 439 | gd->relocaddr); |
1938f4a5 SG |
440 | return 0; |
441 | } | |
442 | #endif /* CONFIG_PRAM */ | |
443 | ||
444 | /* Round memory pointer down to next 4 kB limit */ | |
445 | static int reserve_round_4k(void) | |
446 | { | |
a0ba279a | 447 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
448 | return 0; |
449 | } | |
450 | ||
451 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
452 | defined(CONFIG_ARM) | |
453 | static int reserve_mmu(void) | |
454 | { | |
455 | /* reserve TLB table */ | |
cce6be7f | 456 | gd->arch.tlb_size = PGTABLE_SIZE; |
a0ba279a | 457 | gd->relocaddr -= gd->arch.tlb_size; |
1938f4a5 SG |
458 | |
459 | /* round down to next 64 kB limit */ | |
a0ba279a | 460 | gd->relocaddr &= ~(0x10000 - 1); |
1938f4a5 | 461 | |
a0ba279a | 462 | gd->arch.tlb_addr = gd->relocaddr; |
1938f4a5 SG |
463 | debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, |
464 | gd->arch.tlb_addr + gd->arch.tlb_size); | |
465 | return 0; | |
466 | } | |
467 | #endif | |
468 | ||
469 | #ifdef CONFIG_LCD | |
470 | static int reserve_lcd(void) | |
471 | { | |
472 | #ifdef CONFIG_FB_ADDR | |
473 | gd->fb_base = CONFIG_FB_ADDR; | |
474 | #else | |
475 | /* reserve memory for LCD display (always full pages) */ | |
a0ba279a MY |
476 | gd->relocaddr = lcd_setmem(gd->relocaddr); |
477 | gd->fb_base = gd->relocaddr; | |
1938f4a5 SG |
478 | #endif /* CONFIG_FB_ADDR */ |
479 | return 0; | |
480 | } | |
481 | #endif /* CONFIG_LCD */ | |
482 | ||
71c52dba SG |
483 | static int reserve_trace(void) |
484 | { | |
485 | #ifdef CONFIG_TRACE | |
486 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
487 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
488 | debug("Reserving %dk for trace data at: %08lx\n", | |
489 | CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
490 | #endif | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
d54d7eb9 SZ |
495 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ |
496 | !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ | |
944ab340 | 497 | !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) |
e4fef6cf SG |
498 | static int reserve_video(void) |
499 | { | |
500 | /* reserve memory for video display (always full pages) */ | |
a0ba279a MY |
501 | gd->relocaddr = video_setmem(gd->relocaddr); |
502 | gd->fb_base = gd->relocaddr; | |
e4fef6cf SG |
503 | |
504 | return 0; | |
505 | } | |
506 | #endif | |
507 | ||
1938f4a5 SG |
508 | static int reserve_uboot(void) |
509 | { | |
510 | /* | |
511 | * reserve memory for U-Boot code, data & bss | |
512 | * round down to next 4 kB limit | |
513 | */ | |
a0ba279a MY |
514 | gd->relocaddr -= gd->mon_len; |
515 | gd->relocaddr &= ~(4096 - 1); | |
e4fef6cf SG |
516 | #ifdef CONFIG_E500 |
517 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
a0ba279a | 518 | gd->relocaddr &= ~(65536 - 1); |
e4fef6cf | 519 | #endif |
1938f4a5 SG |
520 | |
521 | debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, | |
a0ba279a MY |
522 | gd->relocaddr); |
523 | ||
524 | gd->start_addr_sp = gd->relocaddr; | |
525 | ||
1938f4a5 SG |
526 | return 0; |
527 | } | |
528 | ||
8cae8a68 | 529 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
530 | /* reserve memory for malloc() area */ |
531 | static int reserve_malloc(void) | |
532 | { | |
a0ba279a | 533 | gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; |
1938f4a5 | 534 | debug("Reserving %dk for malloc() at: %08lx\n", |
a0ba279a | 535 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
1938f4a5 SG |
536 | return 0; |
537 | } | |
538 | ||
539 | /* (permanently) allocate a Board Info struct */ | |
540 | static int reserve_board(void) | |
541 | { | |
d54d7eb9 SZ |
542 | if (!gd->bd) { |
543 | gd->start_addr_sp -= sizeof(bd_t); | |
544 | gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); | |
545 | memset(gd->bd, '\0', sizeof(bd_t)); | |
546 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", | |
547 | sizeof(bd_t), gd->start_addr_sp); | |
548 | } | |
1938f4a5 SG |
549 | return 0; |
550 | } | |
8cae8a68 | 551 | #endif |
1938f4a5 SG |
552 | |
553 | static int setup_machine(void) | |
554 | { | |
555 | #ifdef CONFIG_MACH_TYPE | |
556 | gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ | |
557 | #endif | |
558 | return 0; | |
559 | } | |
560 | ||
561 | static int reserve_global_data(void) | |
562 | { | |
a0ba279a MY |
563 | gd->start_addr_sp -= sizeof(gd_t); |
564 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); | |
1938f4a5 | 565 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
a0ba279a | 566 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
567 | return 0; |
568 | } | |
569 | ||
570 | static int reserve_fdt(void) | |
571 | { | |
572 | /* | |
573 | * If the device tree is sitting immediate above our image then we | |
574 | * must relocate it. If it is embedded in the data section, then it | |
575 | * will be relocated with other data. | |
576 | */ | |
577 | if (gd->fdt_blob) { | |
578 | gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); | |
579 | ||
a0ba279a MY |
580 | gd->start_addr_sp -= gd->fdt_size; |
581 | gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); | |
a733b06b | 582 | debug("Reserving %lu Bytes for FDT at: %08lx\n", |
a0ba279a | 583 | gd->fdt_size, gd->start_addr_sp); |
1938f4a5 SG |
584 | } |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
68145d4c | 589 | int arch_reserve_stacks(void) |
1938f4a5 | 590 | { |
68145d4c AB |
591 | return 0; |
592 | } | |
8cae8a68 | 593 | |
68145d4c AB |
594 | static int reserve_stacks(void) |
595 | { | |
596 | /* make stack pointer 16-byte aligned */ | |
a0ba279a MY |
597 | gd->start_addr_sp -= 16; |
598 | gd->start_addr_sp &= ~0xf; | |
1938f4a5 SG |
599 | |
600 | /* | |
68145d4c AB |
601 | * let the architecture specific code tailor gd->start_addr_sp and |
602 | * gd->irq_sp | |
1938f4a5 | 603 | */ |
68145d4c | 604 | return arch_reserve_stacks(); |
1938f4a5 SG |
605 | } |
606 | ||
607 | static int display_new_sp(void) | |
608 | { | |
a0ba279a | 609 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
610 | |
611 | return 0; | |
612 | } | |
613 | ||
e310b93e | 614 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
615 | static int setup_board_part1(void) |
616 | { | |
617 | bd_t *bd = gd->bd; | |
618 | ||
619 | /* | |
620 | * Save local variables to board info struct | |
621 | */ | |
622 | ||
623 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ | |
624 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
625 | ||
626 | #ifdef CONFIG_SYS_SRAM_BASE | |
627 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
628 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
629 | #endif | |
630 | ||
58dac327 | 631 | #if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ |
e4fef6cf SG |
632 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
633 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ | |
634 | #endif | |
e310b93e | 635 | #if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) |
e4fef6cf SG |
636 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
637 | #endif | |
638 | #if defined(CONFIG_MPC83xx) | |
639 | bd->bi_immrbar = CONFIG_SYS_IMMR; | |
640 | #endif | |
e4fef6cf SG |
641 | |
642 | return 0; | |
643 | } | |
644 | ||
645 | static int setup_board_part2(void) | |
646 | { | |
647 | bd_t *bd = gd->bd; | |
648 | ||
649 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ | |
650 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
651 | #if defined(CONFIG_CPM2) | |
652 | bd->bi_cpmfreq = gd->arch.cpm_clk; | |
653 | bd->bi_brgfreq = gd->arch.brg_clk; | |
654 | bd->bi_sccfreq = gd->arch.scc_clk; | |
655 | bd->bi_vco = gd->arch.vco_out; | |
656 | #endif /* CONFIG_CPM2 */ | |
657 | #if defined(CONFIG_MPC512X) | |
658 | bd->bi_ipsfreq = gd->arch.ips_clk; | |
659 | #endif /* CONFIG_MPC512X */ | |
660 | #if defined(CONFIG_MPC5xxx) | |
661 | bd->bi_ipbfreq = gd->arch.ipb_clk; | |
662 | bd->bi_pcifreq = gd->pci_clk; | |
663 | #endif /* CONFIG_MPC5xxx */ | |
1313db48 AW |
664 | #if defined(CONFIG_M68K) && defined(CONFIG_PCI) |
665 | bd->bi_pcifreq = gd->pci_clk; | |
666 | #endif | |
667 | #if defined(CONFIG_EXTRA_CLOCK) | |
668 | bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ | |
669 | bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ | |
670 | bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ | |
671 | #endif | |
e4fef6cf SG |
672 | |
673 | return 0; | |
674 | } | |
675 | #endif | |
676 | ||
677 | #ifdef CONFIG_SYS_EXTBDINFO | |
678 | static int setup_board_extra(void) | |
679 | { | |
680 | bd_t *bd = gd->bd; | |
681 | ||
682 | strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); | |
683 | strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, | |
684 | sizeof(bd->bi_r_version)); | |
685 | ||
686 | bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ | |
687 | bd->bi_plb_busfreq = gd->bus_clk; | |
688 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ | |
689 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
690 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
691 | bd->bi_pci_busfreq = get_PCI_freq(); | |
692 | bd->bi_opbfreq = get_OPB_freq(); | |
693 | #elif defined(CONFIG_XILINX_405) | |
694 | bd->bi_pci_busfreq = get_PCI_freq(); | |
695 | #endif | |
696 | ||
697 | return 0; | |
698 | } | |
699 | #endif | |
700 | ||
1938f4a5 SG |
701 | #ifdef CONFIG_POST |
702 | static int init_post(void) | |
703 | { | |
704 | post_bootmode_init(); | |
705 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
706 | ||
707 | return 0; | |
708 | } | |
709 | #endif | |
710 | ||
1938f4a5 SG |
711 | static int setup_dram_config(void) |
712 | { | |
713 | /* Ram is board specific, so move it to board code ... */ | |
714 | dram_init_banksize(); | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
719 | static int reloc_fdt(void) | |
720 | { | |
721 | if (gd->new_fdt) { | |
722 | memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); | |
723 | gd->fdt_blob = gd->new_fdt; | |
724 | } | |
725 | ||
726 | return 0; | |
727 | } | |
728 | ||
729 | static int setup_reloc(void) | |
730 | { | |
d54d7eb9 | 731 | #ifdef CONFIG_SYS_TEXT_BASE |
a0ba279a | 732 | gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; |
e310b93e | 733 | #ifdef CONFIG_M68K |
734 | /* | |
735 | * On all ColdFire arch cpu, monitor code starts always | |
736 | * just after the default vector table location, so at 0x400 | |
737 | */ | |
738 | gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); | |
739 | #endif | |
d54d7eb9 | 740 | #endif |
1938f4a5 SG |
741 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
742 | ||
743 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); | |
a733b06b | 744 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", |
a0ba279a MY |
745 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), |
746 | gd->start_addr_sp); | |
1938f4a5 SG |
747 | |
748 | return 0; | |
749 | } | |
750 | ||
751 | /* ARM calls relocate_code from its crt0.S */ | |
808434cd | 752 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
753 | |
754 | static int jump_to_copy(void) | |
755 | { | |
48a33806 SG |
756 | /* |
757 | * x86 is special, but in a nice way. It uses a trampoline which | |
758 | * enables the dcache if possible. | |
759 | * | |
760 | * For now, other archs use relocate_code(), which is implemented | |
761 | * similarly for all archs. When we do generic relocation, hopefully | |
762 | * we can make all archs enable the dcache prior to relocation. | |
763 | */ | |
3fb80163 | 764 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
765 | /* |
766 | * SDRAM and console are now initialised. The final stack can now | |
767 | * be setup in SDRAM. Code execution will continue in Flash, but | |
768 | * with the stack in SDRAM and Global Data in temporary memory | |
769 | * (CPU cache) | |
770 | */ | |
771 | board_init_f_r_trampoline(gd->start_addr_sp); | |
772 | #else | |
a0ba279a | 773 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 774 | #endif |
1938f4a5 SG |
775 | |
776 | return 0; | |
777 | } | |
778 | #endif | |
779 | ||
780 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
781 | static int mark_bootstage(void) | |
782 | { | |
783 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
d59476b6 SG |
788 | static int initf_malloc(void) |
789 | { | |
790 | #ifdef CONFIG_SYS_MALLOC_F_LEN | |
791 | assert(gd->malloc_base); /* Set up by crt0.S */ | |
792 | gd->malloc_limit = gd->malloc_base + CONFIG_SYS_MALLOC_F_LEN; | |
793 | gd->malloc_ptr = 0; | |
794 | #endif | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
ab7cd627 SG |
799 | static int initf_dm(void) |
800 | { | |
801 | #if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) | |
802 | int ret; | |
803 | ||
804 | ret = dm_init_and_scan(true); | |
805 | if (ret) | |
806 | return ret; | |
807 | #endif | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
146251f8 SG |
812 | /* Architecture-specific memory reservation */ |
813 | __weak int reserve_arch(void) | |
814 | { | |
815 | return 0; | |
816 | } | |
817 | ||
1938f4a5 | 818 | static init_fnc_t init_sequence_f[] = { |
a733b06b SG |
819 | #ifdef CONFIG_SANDBOX |
820 | setup_ram_buf, | |
e4fef6cf | 821 | #endif |
1938f4a5 | 822 | setup_mon_len, |
71c52dba | 823 | setup_fdt, |
d210718d | 824 | #ifdef CONFIG_TRACE |
71c52dba | 825 | trace_early_init, |
d210718d | 826 | #endif |
768e0f52 | 827 | initf_malloc, |
e4fef6cf SG |
828 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
829 | /* TODO: can this go into arch_cpu_init()? */ | |
830 | probecpu, | |
831 | #endif | |
1938f4a5 SG |
832 | arch_cpu_init, /* basic arch cpu dependent setup */ |
833 | mark_bootstage, | |
834 | #ifdef CONFIG_OF_CONTROL | |
835 | fdtdec_check_fdt, | |
836 | #endif | |
3ea0953d | 837 | initf_dm, |
1938f4a5 SG |
838 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
839 | board_early_init_f, | |
840 | #endif | |
e4fef6cf SG |
841 | /* TODO: can any of this go into arch_cpu_init()? */ |
842 | #if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT) | |
843 | get_clocks, /* get CPU and bus clocks (etc.) */ | |
844 | #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ | |
845 | && !defined(CONFIG_TQM885D) | |
846 | adjust_sdram_tbs_8xx, | |
847 | #endif | |
848 | /* TODO: can we rename this to timer_init()? */ | |
849 | init_timebase, | |
850 | #endif | |
d54d7eb9 | 851 | #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || defined(CONFIG_BLACKFIN) |
1938f4a5 | 852 | timer_init, /* initialize timer */ |
e4fef6cf | 853 | #endif |
e4fef6cf SG |
854 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
855 | #if !defined(CONFIG_CPM2) | |
856 | dpram_init, | |
857 | #endif | |
858 | #endif | |
859 | #if defined(CONFIG_BOARD_POSTCLK_INIT) | |
860 | board_postclk_init, | |
b8521b74 MY |
861 | #endif |
862 | #ifdef CONFIG_FSL_ESDHC | |
863 | get_clocks, | |
e310b93e | 864 | #endif |
865 | #ifdef CONFIG_M68K | |
866 | get_clocks, | |
1938f4a5 SG |
867 | #endif |
868 | env_init, /* initialize environment */ | |
e4fef6cf SG |
869 | #if defined(CONFIG_8xx_CPUCLK_DEFAULT) |
870 | /* get CPU and bus clocks according to the environment variable */ | |
871 | get_clocks_866, | |
872 | /* adjust sdram refresh rate according to the new clock */ | |
873 | sdram_adjust_866, | |
874 | init_timebase, | |
875 | #endif | |
1938f4a5 SG |
876 | init_baud_rate, /* initialze baudrate settings */ |
877 | serial_init, /* serial communications setup */ | |
878 | console_init_f, /* stage 1 init of console */ | |
a733b06b SG |
879 | #ifdef CONFIG_SANDBOX |
880 | sandbox_early_getopt_check, | |
881 | #endif | |
882 | #ifdef CONFIG_OF_CONTROL | |
883 | fdtdec_prepare_fdt, | |
48a33806 | 884 | #endif |
1938f4a5 SG |
885 | display_options, /* say that we are here */ |
886 | display_text_info, /* show debugging info if required */ | |
58dac327 | 887 | #if defined(CONFIG_MPC8260) |
e4fef6cf SG |
888 | prt_8260_rsr, |
889 | prt_8260_clks, | |
58dac327 | 890 | #endif /* CONFIG_MPC8260 */ |
e4fef6cf SG |
891 | #if defined(CONFIG_MPC83xx) |
892 | prt_83xx_rsr, | |
893 | #endif | |
e310b93e | 894 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
895 | checkcpu, |
896 | #endif | |
1938f4a5 | 897 | print_cpuinfo, /* display cpu info (and speed) */ |
e4fef6cf SG |
898 | #if defined(CONFIG_MPC5xxx) |
899 | prt_mpc5xxx_clks, | |
900 | #endif /* CONFIG_MPC5xxx */ | |
1938f4a5 | 901 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
0365ffcc | 902 | show_board_info, |
e4fef6cf SG |
903 | #endif |
904 | INIT_FUNC_WATCHDOG_INIT | |
905 | #if defined(CONFIG_MISC_INIT_F) | |
906 | misc_init_f, | |
907 | #endif | |
908 | INIT_FUNC_WATCHDOG_RESET | |
ea818dbb | 909 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
910 | init_func_i2c, |
911 | #endif | |
912 | #if defined(CONFIG_HARD_SPI) | |
913 | init_func_spi, | |
1938f4a5 SG |
914 | #endif |
915 | announce_dram_init, | |
916 | /* TODO: unify all these dram functions? */ | |
a752a8b4 | 917 | #if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) |
1938f4a5 SG |
918 | dram_init, /* configure available RAM banks */ |
919 | #endif | |
e310b93e | 920 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
921 | init_func_ram, |
922 | #endif | |
923 | #ifdef CONFIG_POST | |
924 | post_init_f, | |
925 | #endif | |
926 | INIT_FUNC_WATCHDOG_RESET | |
927 | #if defined(CONFIG_SYS_DRAM_TEST) | |
928 | testdram, | |
929 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
930 | INIT_FUNC_WATCHDOG_RESET | |
931 | ||
1938f4a5 SG |
932 | #ifdef CONFIG_POST |
933 | init_post, | |
934 | #endif | |
e4fef6cf | 935 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
936 | /* |
937 | * Now that we have DRAM mapped and working, we can | |
938 | * relocate the code and continue running from DRAM. | |
939 | * | |
940 | * Reserve memory at end of RAM for (top down in that order): | |
941 | * - area that won't get touched by U-Boot and Linux (optional) | |
942 | * - kernel log buffer | |
943 | * - protected RAM | |
944 | * - LCD framebuffer | |
945 | * - monitor code | |
946 | * - board info struct | |
947 | */ | |
948 | setup_dest_addr, | |
5ff10aa7 | 949 | #if defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) |
d54d7eb9 SZ |
950 | /* Blackfin u-boot monitor should be on top of the ram */ |
951 | reserve_uboot, | |
952 | #endif | |
1938f4a5 SG |
953 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) |
954 | reserve_logbuffer, | |
955 | #endif | |
956 | #ifdef CONFIG_PRAM | |
957 | reserve_pram, | |
958 | #endif | |
959 | reserve_round_4k, | |
960 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
961 | defined(CONFIG_ARM) | |
962 | reserve_mmu, | |
963 | #endif | |
964 | #ifdef CONFIG_LCD | |
965 | reserve_lcd, | |
e4fef6cf | 966 | #endif |
71c52dba | 967 | reserve_trace, |
e4fef6cf | 968 | /* TODO: Why the dependency on CONFIG_8xx? */ |
d54d7eb9 SZ |
969 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ |
970 | !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ | |
944ab340 | 971 | !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) |
e4fef6cf | 972 | reserve_video, |
1938f4a5 | 973 | #endif |
5ff10aa7 | 974 | #if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_NIOS2) |
1938f4a5 | 975 | reserve_uboot, |
d54d7eb9 | 976 | #endif |
8cae8a68 | 977 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
978 | reserve_malloc, |
979 | reserve_board, | |
8cae8a68 | 980 | #endif |
1938f4a5 SG |
981 | setup_machine, |
982 | reserve_global_data, | |
983 | reserve_fdt, | |
146251f8 | 984 | reserve_arch, |
1938f4a5 SG |
985 | reserve_stacks, |
986 | setup_dram_config, | |
987 | show_dram_config, | |
e310b93e | 988 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
989 | setup_board_part1, |
990 | INIT_FUNC_WATCHDOG_RESET | |
991 | setup_board_part2, | |
992 | #endif | |
1938f4a5 | 993 | display_new_sp, |
e4fef6cf SG |
994 | #ifdef CONFIG_SYS_EXTBDINFO |
995 | setup_board_extra, | |
996 | #endif | |
997 | INIT_FUNC_WATCHDOG_RESET | |
1938f4a5 SG |
998 | reloc_fdt, |
999 | setup_reloc, | |
3fb80163 | 1000 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
313aef37 SG |
1001 | copy_uboot_to_ram, |
1002 | clear_bss, | |
1003 | do_elf_reloc_fixups, | |
1004 | #endif | |
808434cd | 1005 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
1006 | jump_to_copy, |
1007 | #endif | |
1008 | NULL, | |
1009 | }; | |
1010 | ||
1011 | void board_init_f(ulong boot_flags) | |
1012 | { | |
2a1680e3 YS |
1013 | #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA |
1014 | /* | |
1015 | * For some archtectures, global data is initialized and used before | |
1016 | * calling this function. The data should be preserved. For others, | |
1017 | * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack | |
1018 | * here to host global data until relocation. | |
1019 | */ | |
1938f4a5 SG |
1020 | gd_t data; |
1021 | ||
1022 | gd = &data; | |
1023 | ||
cce6be7f DF |
1024 | /* |
1025 | * Clear global data before it is accessed at debug print | |
1026 | * in initcall_run_list. Otherwise the debug print probably | |
1027 | * get the wrong vaule of gd->have_console. | |
1028 | */ | |
cce6be7f DF |
1029 | zero_global_data(); |
1030 | #endif | |
1031 | ||
1938f4a5 | 1032 | gd->flags = boot_flags; |
9aed5a27 | 1033 | gd->have_console = 0; |
1938f4a5 SG |
1034 | |
1035 | if (initcall_run_list(init_sequence_f)) | |
1036 | hang(); | |
1037 | ||
808434cd | 1038 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
1039 | /* NOTREACHED - jump_to_copy() does not return */ |
1040 | hang(); | |
1041 | #endif | |
1042 | } | |
1043 | ||
3fb80163 | 1044 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
1045 | /* |
1046 | * For now this code is only used on x86. | |
1047 | * | |
1048 | * init_sequence_f_r is the list of init functions which are run when | |
1049 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
1050 | * The following limitations must be considered when implementing an | |
1051 | * '_f_r' function: | |
1052 | * - 'static' variables are read-only | |
1053 | * - Global Data (gd->xxx) is read/write | |
1054 | * | |
1055 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
1056 | * supported). It _should_, if possible, copy global data to RAM and | |
1057 | * initialise the CPU caches (to speed up the relocation process) | |
1058 | * | |
1059 | * NOTE: At present only x86 uses this route, but it is intended that | |
1060 | * all archs will move to this when generic relocation is implemented. | |
1061 | */ | |
1062 | static init_fnc_t init_sequence_f_r[] = { | |
1063 | init_cache_f_r, | |
48a33806 SG |
1064 | |
1065 | NULL, | |
1066 | }; | |
1067 | ||
1068 | void board_init_f_r(void) | |
1069 | { | |
1070 | if (initcall_run_list(init_sequence_f_r)) | |
1071 | hang(); | |
1072 | ||
1073 | /* | |
1074 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
1075 | * Transfer execution from Flash to RAM by calculating the address | |
1076 | * of the in-RAM copy of board_init_r() and calling it | |
1077 | */ | |
7bf9f20d | 1078 | (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); |
48a33806 SG |
1079 | |
1080 | /* NOTREACHED - board_init_r() does not return */ | |
1081 | hang(); | |
1082 | } | |
5bcd19aa AB |
1083 | #endif /* CONFIG_X86 */ |
1084 | ||
1085 | #ifndef CONFIG_X86 | |
74d01867 SG |
1086 | ulong board_init_f_mem(ulong top) |
1087 | { | |
1088 | /* Leave space for the stack we are running with now */ | |
1089 | top -= 0x40; | |
1090 | ||
1091 | top -= sizeof(struct global_data); | |
1092 | top = ALIGN(top, 16); | |
1093 | gd = (struct global_data *)top; | |
1094 | memset((void *)gd, '\0', sizeof(*gd)); | |
1095 | ||
1096 | #ifdef CONFIG_SYS_MALLOC_F_LEN | |
1097 | top -= CONFIG_SYS_MALLOC_F_LEN; | |
1098 | gd->malloc_base = top; | |
1099 | #endif | |
1100 | ||
1101 | return top; | |
1102 | } | |
5bcd19aa | 1103 | #endif /* !CONFIG_X86 */ |