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de941241 SG |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * Sukumar Ghorai <s-ghorai@ti.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation's version 2 of | |
12 | * the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <config.h> | |
26 | #include <common.h> | |
93bfd616 | 27 | #include <malloc.h> |
de941241 SG |
28 | #include <mmc.h> |
29 | #include <part.h> | |
30 | #include <i2c.h> | |
31 | #include <twl4030.h> | |
14fa2dd0 | 32 | #include <twl6030.h> |
cb199102 | 33 | #include <palmas.h> |
de941241 SG |
34 | #include <asm/io.h> |
35 | #include <asm/arch/mmc_host_def.h> | |
3b68939f RQ |
36 | #if !defined(CONFIG_SOC_KEYSTONE) |
37 | #include <asm/gpio.h> | |
96e0e7b3 | 38 | #include <asm/arch/sys_proto.h> |
3b68939f | 39 | #endif |
2a48b3a2 TR |
40 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
41 | #include <asm/arch/mux.h> | |
42 | #endif | |
a9d6a7e2 M |
43 | #include <dm.h> |
44 | ||
45 | DECLARE_GLOBAL_DATA_PTR; | |
de941241 | 46 | |
ab769f22 PA |
47 | /* simplify defines to OMAP_HSMMC_USE_GPIO */ |
48 | #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ | |
49 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) | |
50 | #define OMAP_HSMMC_USE_GPIO | |
51 | #else | |
52 | #undef OMAP_HSMMC_USE_GPIO | |
53 | #endif | |
54 | ||
25c719e2 GI |
55 | /* common definitions for all OMAPs */ |
56 | #define SYSCTL_SRC (1 << 25) | |
57 | #define SYSCTL_SRD (1 << 26) | |
58 | ||
3d673ffc JJH |
59 | struct omap_hsmmc_plat { |
60 | struct mmc_config cfg; | |
17c9a1c1 | 61 | struct mmc mmc; |
3d673ffc JJH |
62 | }; |
63 | ||
46831c1a AF |
64 | struct omap2_mmc_platform_config { |
65 | u32 reg_offset; | |
66 | }; | |
67 | ||
cc22b0c0 NK |
68 | struct omap_hsmmc_data { |
69 | struct hsmmc *base_addr; | |
3d673ffc | 70 | #ifndef CONFIG_DM_MMC |
93bfd616 | 71 | struct mmc_config cfg; |
3d673ffc | 72 | #endif |
ab769f22 | 73 | #ifdef OMAP_HSMMC_USE_GPIO |
a9d6a7e2 M |
74 | #ifdef CONFIG_DM_MMC |
75 | struct gpio_desc cd_gpio; /* Change Detect GPIO */ | |
76 | struct gpio_desc wp_gpio; /* Write Protect GPIO */ | |
77 | bool cd_inverted; | |
78 | #else | |
e874d5b0 | 79 | int cd_gpio; |
e3913f56 | 80 | int wp_gpio; |
ab769f22 | 81 | #endif |
a9d6a7e2 | 82 | #endif |
cc22b0c0 NK |
83 | }; |
84 | ||
eb9a28f6 NM |
85 | /* If we fail after 1 second wait, something is really bad */ |
86 | #define MAX_RETRY_MS 1000 | |
87 | ||
933efe64 S |
88 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); |
89 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, | |
90 | unsigned int siz); | |
14fa2dd0 | 91 | |
ae000e23 JJH |
92 | static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) |
93 | { | |
94 | #ifdef CONFIG_DM_MMC | |
95 | return dev_get_priv(mmc->dev); | |
96 | #else | |
97 | return (struct omap_hsmmc_data *)mmc->priv; | |
98 | #endif | |
3d673ffc JJH |
99 | } |
100 | static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc) | |
101 | { | |
102 | #ifdef CONFIG_DM_MMC | |
103 | struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev); | |
104 | return &plat->cfg; | |
105 | #else | |
106 | return &((struct omap_hsmmc_data *)mmc->priv)->cfg; | |
107 | #endif | |
ae000e23 JJH |
108 | } |
109 | ||
110 | #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC) | |
e874d5b0 NK |
111 | static int omap_mmc_setup_gpio_in(int gpio, const char *label) |
112 | { | |
5915a2ad | 113 | int ret; |
e874d5b0 | 114 | |
5915a2ad SG |
115 | #ifndef CONFIG_DM_GPIO |
116 | if (!gpio_is_valid(gpio)) | |
e874d5b0 | 117 | return -1; |
5915a2ad SG |
118 | #endif |
119 | ret = gpio_request(gpio, label); | |
120 | if (ret) | |
121 | return ret; | |
e874d5b0 | 122 | |
5915a2ad SG |
123 | ret = gpio_direction_input(gpio); |
124 | if (ret) | |
125 | return ret; | |
e874d5b0 NK |
126 | |
127 | return gpio; | |
128 | } | |
e874d5b0 NK |
129 | #endif |
130 | ||
750121c3 | 131 | static unsigned char mmc_board_init(struct mmc *mmc) |
de941241 | 132 | { |
de941241 | 133 | #if defined(CONFIG_OMAP34XX) |
3d673ffc | 134 | struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); |
de941241 SG |
135 | t2_t *t2_base = (t2_t *)T2_BASE; |
136 | struct prcm *prcm_base = (struct prcm *)PRCM_BASE; | |
b1e725f2 | 137 | u32 pbias_lite; |
6aca17c9 AF |
138 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
139 | u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL); | |
140 | #endif | |
de941241 | 141 | |
b1e725f2 GI |
142 | pbias_lite = readl(&t2_base->pbias_lite); |
143 | pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); | |
5bfdd1fc AA |
144 | #ifdef CONFIG_TARGET_OMAP3_CAIRO |
145 | /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ | |
146 | pbias_lite &= ~PBIASLITEVMODE0; | |
6aca17c9 AF |
147 | #endif |
148 | #ifdef CONFIG_MMC_OMAP36XX_PINS | |
149 | if (get_cpu_family() == CPU_OMAP36XX) { | |
150 | /* Disable extended drain IO before changing PBIAS */ | |
151 | wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ; | |
152 | writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL); | |
153 | } | |
5bfdd1fc | 154 | #endif |
b1e725f2 | 155 | writel(pbias_lite, &t2_base->pbias_lite); |
aac5450e | 156 | |
b1e725f2 | 157 | writel(pbias_lite | PBIASLITEPWRDNZ1 | |
de941241 SG |
158 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, |
159 | &t2_base->pbias_lite); | |
160 | ||
6aca17c9 AF |
161 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
162 | if (get_cpu_family() == CPU_OMAP36XX) | |
163 | /* Enable extended drain IO after changing PBIAS */ | |
164 | writel(wkup_ctrl | | |
165 | OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, | |
166 | OMAP34XX_CTRL_WKUP_CTRL); | |
167 | #endif | |
de941241 SG |
168 | writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, |
169 | &t2_base->devconf0); | |
170 | ||
171 | writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, | |
172 | &t2_base->devconf1); | |
173 | ||
bbbc1ae9 | 174 | /* Change from default of 52MHz to 26MHz if necessary */ |
3d673ffc | 175 | if (!(cfg->host_caps & MMC_MODE_HS_52MHz)) |
bbbc1ae9 JS |
176 | writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, |
177 | &t2_base->ctl_prog_io1); | |
178 | ||
de941241 SG |
179 | writel(readl(&prcm_base->fclken1_core) | |
180 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
181 | &prcm_base->fclken1_core); | |
182 | ||
183 | writel(readl(&prcm_base->iclken1_core) | | |
184 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
185 | &prcm_base->iclken1_core); | |
186 | #endif | |
187 | ||
b4b06006 | 188 | #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX) |
14fa2dd0 | 189 | /* PBIAS config needed for MMC1 only */ |
dc09127a | 190 | if (mmc_get_blk_desc(mmc)->devnum == 0) |
b4b06006 | 191 | vmmc_pbias_config(LDO_VOLT_3V0); |
dd23e59d | 192 | #endif |
de941241 SG |
193 | |
194 | return 0; | |
195 | } | |
196 | ||
933efe64 | 197 | void mmc_init_stream(struct hsmmc *mmc_base) |
de941241 | 198 | { |
eb9a28f6 | 199 | ulong start; |
de941241 SG |
200 | |
201 | writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); | |
202 | ||
203 | writel(MMC_CMD0, &mmc_base->cmd); | |
eb9a28f6 NM |
204 | start = get_timer(0); |
205 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
206 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
207 | printf("%s: timedout waiting for cc!\n", __func__); | |
208 | return; | |
209 | } | |
210 | } | |
de941241 SG |
211 | writel(CC_MASK, &mmc_base->stat) |
212 | ; | |
213 | writel(MMC_CMD0, &mmc_base->cmd) | |
214 | ; | |
eb9a28f6 NM |
215 | start = get_timer(0); |
216 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
217 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
218 | printf("%s: timedout waiting for cc2!\n", __func__); | |
219 | return; | |
220 | } | |
221 | } | |
de941241 SG |
222 | writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); |
223 | } | |
224 | ||
ab769f22 | 225 | static int omap_hsmmc_init_setup(struct mmc *mmc) |
de941241 | 226 | { |
ae000e23 | 227 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
cc22b0c0 | 228 | struct hsmmc *mmc_base; |
de941241 SG |
229 | unsigned int reg_val; |
230 | unsigned int dsor; | |
eb9a28f6 | 231 | ulong start; |
de941241 | 232 | |
ae000e23 | 233 | mmc_base = priv->base_addr; |
14fa2dd0 | 234 | mmc_board_init(mmc); |
de941241 SG |
235 | |
236 | writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, | |
237 | &mmc_base->sysconfig); | |
eb9a28f6 NM |
238 | start = get_timer(0); |
239 | while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { | |
240 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
241 | printf("%s: timedout waiting for cc2!\n", __func__); | |
915ffa52 | 242 | return -ETIMEDOUT; |
eb9a28f6 NM |
243 | } |
244 | } | |
de941241 | 245 | writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); |
eb9a28f6 NM |
246 | start = get_timer(0); |
247 | while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { | |
248 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
249 | printf("%s: timedout waiting for softresetall!\n", | |
250 | __func__); | |
915ffa52 | 251 | return -ETIMEDOUT; |
eb9a28f6 NM |
252 | } |
253 | } | |
de941241 SG |
254 | writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); |
255 | writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, | |
256 | &mmc_base->capa); | |
257 | ||
258 | reg_val = readl(&mmc_base->con) & RESERVED_MASK; | |
259 | ||
260 | writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | | |
261 | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | | |
262 | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); | |
263 | ||
264 | dsor = 240; | |
265 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
266 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
267 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
268 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
eb9a28f6 NM |
269 | start = get_timer(0); |
270 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
271 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
272 | printf("%s: timedout waiting for ics!\n", __func__); | |
915ffa52 | 273 | return -ETIMEDOUT; |
eb9a28f6 NM |
274 | } |
275 | } | |
de941241 SG |
276 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
277 | ||
278 | writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); | |
279 | ||
280 | writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | | |
281 | IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, | |
282 | &mmc_base->ie); | |
283 | ||
284 | mmc_init_stream(mmc_base); | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
25c719e2 GI |
289 | /* |
290 | * MMC controller internal finite state machine reset | |
291 | * | |
292 | * Used to reset command or data internal state machines, using respectively | |
293 | * SRC or SRD bit of SYSCTL register | |
294 | */ | |
295 | static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) | |
296 | { | |
297 | ulong start; | |
298 | ||
299 | mmc_reg_out(&mmc_base->sysctl, bit, bit); | |
300 | ||
61a6cc27 OT |
301 | /* |
302 | * CMD(DAT) lines reset procedures are slightly different | |
303 | * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). | |
304 | * According to OMAP3 TRM: | |
305 | * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it | |
306 | * returns to 0x0. | |
307 | * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset | |
308 | * procedure steps must be as follows: | |
309 | * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in | |
310 | * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). | |
311 | * 2. Poll the SRC(SRD) bit until it is set to 0x1. | |
312 | * 3. Wait until the SRC (SRD) bit returns to 0x0 | |
313 | * (reset procedure is completed). | |
314 | */ | |
315 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ | |
dce55b93 | 316 | defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) |
61a6cc27 OT |
317 | if (!(readl(&mmc_base->sysctl) & bit)) { |
318 | start = get_timer(0); | |
319 | while (!(readl(&mmc_base->sysctl) & bit)) { | |
320 | if (get_timer(0) - start > MAX_RETRY_MS) | |
321 | return; | |
322 | } | |
323 | } | |
324 | #endif | |
25c719e2 GI |
325 | start = get_timer(0); |
326 | while ((readl(&mmc_base->sysctl) & bit) != 0) { | |
327 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
328 | printf("%s: timedout waiting for sysctl %x to clear\n", | |
329 | __func__, bit); | |
330 | return; | |
331 | } | |
332 | } | |
333 | } | |
de941241 | 334 | |
ab769f22 | 335 | static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
de941241 SG |
336 | struct mmc_data *data) |
337 | { | |
ae000e23 | 338 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
cc22b0c0 | 339 | struct hsmmc *mmc_base; |
de941241 | 340 | unsigned int flags, mmc_stat; |
eb9a28f6 | 341 | ulong start; |
de941241 | 342 | |
ae000e23 | 343 | mmc_base = priv->base_addr; |
eb9a28f6 | 344 | start = get_timer(0); |
a7778f8f | 345 | while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { |
eb9a28f6 | 346 | if (get_timer(0) - start > MAX_RETRY_MS) { |
a7778f8f TR |
347 | printf("%s: timedout waiting on cmd inhibit to clear\n", |
348 | __func__); | |
915ffa52 | 349 | return -ETIMEDOUT; |
eb9a28f6 NM |
350 | } |
351 | } | |
de941241 | 352 | writel(0xFFFFFFFF, &mmc_base->stat); |
eb9a28f6 NM |
353 | start = get_timer(0); |
354 | while (readl(&mmc_base->stat)) { | |
355 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
15ceb1de GI |
356 | printf("%s: timedout waiting for STAT (%x) to clear\n", |
357 | __func__, readl(&mmc_base->stat)); | |
915ffa52 | 358 | return -ETIMEDOUT; |
eb9a28f6 NM |
359 | } |
360 | } | |
de941241 SG |
361 | /* |
362 | * CMDREG | |
363 | * CMDIDX[13:8] : Command index | |
364 | * DATAPRNT[5] : Data Present Select | |
365 | * ENCMDIDX[4] : Command Index Check Enable | |
366 | * ENCMDCRC[3] : Command CRC Check Enable | |
367 | * RSPTYP[1:0] | |
368 | * 00 = No Response | |
369 | * 01 = Length 136 | |
370 | * 10 = Length 48 | |
371 | * 11 = Length 48 Check busy after response | |
372 | */ | |
373 | /* Delay added before checking the status of frq change | |
374 | * retry not supported by mmc.c(core file) | |
375 | */ | |
376 | if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) | |
377 | udelay(50000); /* wait 50 ms */ | |
378 | ||
379 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) | |
380 | flags = 0; | |
381 | else if (cmd->resp_type & MMC_RSP_136) | |
382 | flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; | |
383 | else if (cmd->resp_type & MMC_RSP_BUSY) | |
384 | flags = RSP_TYPE_LGHT48B; | |
385 | else | |
386 | flags = RSP_TYPE_LGHT48; | |
387 | ||
388 | /* enable default flags */ | |
389 | flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | | |
390 | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); | |
391 | ||
392 | if (cmd->resp_type & MMC_RSP_CRC) | |
393 | flags |= CCCE_CHECK; | |
394 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
395 | flags |= CICE_CHECK; | |
396 | ||
397 | if (data) { | |
398 | if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || | |
399 | (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { | |
400 | flags |= (MSBS_MULTIBLK | BCE_ENABLE); | |
401 | data->blocksize = 512; | |
402 | writel(data->blocksize | (data->blocks << 16), | |
403 | &mmc_base->blk); | |
404 | } else | |
405 | writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); | |
406 | ||
407 | if (data->flags & MMC_DATA_READ) | |
408 | flags |= (DP_DATA | DDIR_READ); | |
409 | else | |
410 | flags |= (DP_DATA | DDIR_WRITE); | |
411 | } | |
412 | ||
413 | writel(cmd->cmdarg, &mmc_base->arg); | |
152ba363 | 414 | udelay(20); /* To fix "No status update" error on eMMC */ |
de941241 SG |
415 | writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); |
416 | ||
eb9a28f6 | 417 | start = get_timer(0); |
de941241 SG |
418 | do { |
419 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
420 | if (get_timer(0) - start > MAX_RETRY_MS) { |
421 | printf("%s : timeout: No status update\n", __func__); | |
915ffa52 | 422 | return -ETIMEDOUT; |
eb9a28f6 NM |
423 | } |
424 | } while (!mmc_stat); | |
de941241 | 425 | |
25c719e2 GI |
426 | if ((mmc_stat & IE_CTO) != 0) { |
427 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); | |
915ffa52 | 428 | return -ETIMEDOUT; |
25c719e2 | 429 | } else if ((mmc_stat & ERRI_MASK) != 0) |
de941241 SG |
430 | return -1; |
431 | ||
432 | if (mmc_stat & CC_MASK) { | |
433 | writel(CC_MASK, &mmc_base->stat); | |
434 | if (cmd->resp_type & MMC_RSP_PRESENT) { | |
435 | if (cmd->resp_type & MMC_RSP_136) { | |
436 | /* response type 2 */ | |
437 | cmd->response[3] = readl(&mmc_base->rsp10); | |
438 | cmd->response[2] = readl(&mmc_base->rsp32); | |
439 | cmd->response[1] = readl(&mmc_base->rsp54); | |
440 | cmd->response[0] = readl(&mmc_base->rsp76); | |
441 | } else | |
442 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
443 | cmd->response[0] = readl(&mmc_base->rsp10); | |
444 | } | |
445 | } | |
446 | ||
447 | if (data && (data->flags & MMC_DATA_READ)) { | |
448 | mmc_read_data(mmc_base, data->dest, | |
449 | data->blocksize * data->blocks); | |
450 | } else if (data && (data->flags & MMC_DATA_WRITE)) { | |
451 | mmc_write_data(mmc_base, data->src, | |
452 | data->blocksize * data->blocks); | |
453 | } | |
454 | return 0; | |
455 | } | |
456 | ||
933efe64 | 457 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) |
de941241 SG |
458 | { |
459 | unsigned int *output_buf = (unsigned int *)buf; | |
460 | unsigned int mmc_stat; | |
461 | unsigned int count; | |
462 | ||
463 | /* | |
464 | * Start Polled Read | |
465 | */ | |
466 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
467 | count /= 4; | |
468 | ||
469 | while (size) { | |
eb9a28f6 | 470 | ulong start = get_timer(0); |
de941241 SG |
471 | do { |
472 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
473 | if (get_timer(0) - start > MAX_RETRY_MS) { |
474 | printf("%s: timedout waiting for status!\n", | |
475 | __func__); | |
915ffa52 | 476 | return -ETIMEDOUT; |
eb9a28f6 | 477 | } |
de941241 SG |
478 | } while (mmc_stat == 0); |
479 | ||
25c719e2 GI |
480 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
481 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
482 | ||
de941241 SG |
483 | if ((mmc_stat & ERRI_MASK) != 0) |
484 | return 1; | |
485 | ||
486 | if (mmc_stat & BRR_MASK) { | |
487 | unsigned int k; | |
488 | ||
489 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
490 | &mmc_base->stat); | |
491 | for (k = 0; k < count; k++) { | |
492 | *output_buf = readl(&mmc_base->data); | |
493 | output_buf++; | |
494 | } | |
495 | size -= (count*4); | |
496 | } | |
497 | ||
498 | if (mmc_stat & BWR_MASK) | |
499 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
500 | &mmc_base->stat); | |
501 | ||
502 | if (mmc_stat & TC_MASK) { | |
503 | writel(readl(&mmc_base->stat) | TC_MASK, | |
504 | &mmc_base->stat); | |
505 | break; | |
506 | } | |
507 | } | |
508 | return 0; | |
509 | } | |
510 | ||
933efe64 S |
511 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, |
512 | unsigned int size) | |
de941241 SG |
513 | { |
514 | unsigned int *input_buf = (unsigned int *)buf; | |
515 | unsigned int mmc_stat; | |
516 | unsigned int count; | |
517 | ||
518 | /* | |
152ba363 | 519 | * Start Polled Write |
de941241 SG |
520 | */ |
521 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
522 | count /= 4; | |
523 | ||
524 | while (size) { | |
eb9a28f6 | 525 | ulong start = get_timer(0); |
de941241 SG |
526 | do { |
527 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
528 | if (get_timer(0) - start > MAX_RETRY_MS) { |
529 | printf("%s: timedout waiting for status!\n", | |
530 | __func__); | |
915ffa52 | 531 | return -ETIMEDOUT; |
eb9a28f6 | 532 | } |
de941241 SG |
533 | } while (mmc_stat == 0); |
534 | ||
25c719e2 GI |
535 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
536 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
537 | ||
de941241 SG |
538 | if ((mmc_stat & ERRI_MASK) != 0) |
539 | return 1; | |
540 | ||
541 | if (mmc_stat & BWR_MASK) { | |
542 | unsigned int k; | |
543 | ||
544 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
545 | &mmc_base->stat); | |
546 | for (k = 0; k < count; k++) { | |
547 | writel(*input_buf, &mmc_base->data); | |
548 | input_buf++; | |
549 | } | |
550 | size -= (count*4); | |
551 | } | |
552 | ||
553 | if (mmc_stat & BRR_MASK) | |
554 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
555 | &mmc_base->stat); | |
556 | ||
557 | if (mmc_stat & TC_MASK) { | |
558 | writel(readl(&mmc_base->stat) | TC_MASK, | |
559 | &mmc_base->stat); | |
560 | break; | |
561 | } | |
562 | } | |
563 | return 0; | |
564 | } | |
565 | ||
07b0b9c0 | 566 | static int omap_hsmmc_set_ios(struct mmc *mmc) |
de941241 | 567 | { |
ae000e23 | 568 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
cc22b0c0 | 569 | struct hsmmc *mmc_base; |
de941241 | 570 | unsigned int dsor = 0; |
eb9a28f6 | 571 | ulong start; |
de941241 | 572 | |
ae000e23 | 573 | mmc_base = priv->base_addr; |
de941241 SG |
574 | /* configue bus width */ |
575 | switch (mmc->bus_width) { | |
576 | case 8: | |
577 | writel(readl(&mmc_base->con) | DTW_8_BITMODE, | |
578 | &mmc_base->con); | |
579 | break; | |
580 | ||
581 | case 4: | |
582 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
583 | &mmc_base->con); | |
584 | writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, | |
585 | &mmc_base->hctl); | |
586 | break; | |
587 | ||
588 | case 1: | |
589 | default: | |
590 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
591 | &mmc_base->con); | |
592 | writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, | |
593 | &mmc_base->hctl); | |
594 | break; | |
595 | } | |
596 | ||
597 | /* configure clock with 96Mhz system clock. | |
598 | */ | |
599 | if (mmc->clock != 0) { | |
600 | dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); | |
601 | if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) | |
602 | dsor++; | |
603 | } | |
604 | ||
605 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
606 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
607 | ||
608 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
609 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
610 | ||
eb9a28f6 NM |
611 | start = get_timer(0); |
612 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
613 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
614 | printf("%s: timedout waiting for ics!\n", __func__); | |
07b0b9c0 | 615 | return -ETIMEDOUT; |
eb9a28f6 NM |
616 | } |
617 | } | |
de941241 | 618 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
07b0b9c0 JC |
619 | |
620 | return 0; | |
de941241 SG |
621 | } |
622 | ||
ab769f22 | 623 | #ifdef OMAP_HSMMC_USE_GPIO |
a9d6a7e2 M |
624 | #ifdef CONFIG_DM_MMC |
625 | static int omap_hsmmc_getcd(struct mmc *mmc) | |
626 | { | |
ae000e23 | 627 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
a9d6a7e2 M |
628 | int value; |
629 | ||
630 | value = dm_gpio_get_value(&priv->cd_gpio); | |
631 | /* if no CD return as 1 */ | |
632 | if (value < 0) | |
633 | return 1; | |
634 | ||
635 | if (priv->cd_inverted) | |
636 | return !value; | |
637 | return value; | |
638 | } | |
639 | ||
640 | static int omap_hsmmc_getwp(struct mmc *mmc) | |
641 | { | |
ae000e23 | 642 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
a9d6a7e2 M |
643 | int value; |
644 | ||
645 | value = dm_gpio_get_value(&priv->wp_gpio); | |
646 | /* if no WP return as 0 */ | |
647 | if (value < 0) | |
648 | return 0; | |
649 | return value; | |
650 | } | |
651 | #else | |
ab769f22 PA |
652 | static int omap_hsmmc_getcd(struct mmc *mmc) |
653 | { | |
ae000e23 | 654 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
ab769f22 PA |
655 | int cd_gpio; |
656 | ||
657 | /* if no CD return as 1 */ | |
ae000e23 | 658 | cd_gpio = priv->cd_gpio; |
ab769f22 PA |
659 | if (cd_gpio < 0) |
660 | return 1; | |
661 | ||
0b03a931 IG |
662 | /* NOTE: assumes card detect signal is active-low */ |
663 | return !gpio_get_value(cd_gpio); | |
ab769f22 PA |
664 | } |
665 | ||
666 | static int omap_hsmmc_getwp(struct mmc *mmc) | |
667 | { | |
ae000e23 | 668 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
ab769f22 PA |
669 | int wp_gpio; |
670 | ||
671 | /* if no WP return as 0 */ | |
ae000e23 | 672 | wp_gpio = priv->wp_gpio; |
ab769f22 PA |
673 | if (wp_gpio < 0) |
674 | return 0; | |
675 | ||
0b03a931 | 676 | /* NOTE: assumes write protect signal is active-high */ |
ab769f22 PA |
677 | return gpio_get_value(wp_gpio); |
678 | } | |
679 | #endif | |
a9d6a7e2 | 680 | #endif |
ab769f22 PA |
681 | |
682 | static const struct mmc_ops omap_hsmmc_ops = { | |
683 | .send_cmd = omap_hsmmc_send_cmd, | |
684 | .set_ios = omap_hsmmc_set_ios, | |
685 | .init = omap_hsmmc_init_setup, | |
686 | #ifdef OMAP_HSMMC_USE_GPIO | |
687 | .getcd = omap_hsmmc_getcd, | |
688 | .getwp = omap_hsmmc_getwp, | |
689 | #endif | |
690 | }; | |
691 | ||
a9d6a7e2 | 692 | #ifndef CONFIG_DM_MMC |
e3913f56 NK |
693 | int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, |
694 | int wp_gpio) | |
de941241 | 695 | { |
93bfd616 | 696 | struct mmc *mmc; |
ae000e23 | 697 | struct omap_hsmmc_data *priv; |
93bfd616 PA |
698 | struct mmc_config *cfg; |
699 | uint host_caps_val; | |
700 | ||
ae000e23 JJH |
701 | priv = malloc(sizeof(*priv)); |
702 | if (priv == NULL) | |
93bfd616 | 703 | return -1; |
de941241 | 704 | |
5a20397b | 705 | host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; |
de941241 SG |
706 | |
707 | switch (dev_index) { | |
708 | case 0: | |
ae000e23 | 709 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 | 710 | break; |
1037d585 | 711 | #ifdef OMAP_HSMMC2_BASE |
de941241 | 712 | case 1: |
ae000e23 | 713 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; |
152ba363 | 714 | #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ |
3891a54f | 715 | defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ |
3b68939f RQ |
716 | defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ |
717 | defined(CONFIG_HSMMC2_8BIT) | |
152ba363 LP |
718 | /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ |
719 | host_caps_val |= MMC_MODE_8BIT; | |
720 | #endif | |
de941241 | 721 | break; |
1037d585 TR |
722 | #endif |
723 | #ifdef OMAP_HSMMC3_BASE | |
de941241 | 724 | case 2: |
ae000e23 | 725 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; |
3891a54f | 726 | #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) |
152ba363 LP |
727 | /* Enable 8-bit interface for eMMC on DRA7XX */ |
728 | host_caps_val |= MMC_MODE_8BIT; | |
729 | #endif | |
de941241 | 730 | break; |
1037d585 | 731 | #endif |
de941241 | 732 | default: |
ae000e23 | 733 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 SG |
734 | return 1; |
735 | } | |
ab769f22 PA |
736 | #ifdef OMAP_HSMMC_USE_GPIO |
737 | /* on error gpio values are set to -1, which is what we want */ | |
ae000e23 JJH |
738 | priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); |
739 | priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); | |
ab769f22 | 740 | #endif |
173ddc5b | 741 | |
ae000e23 | 742 | cfg = &priv->cfg; |
de941241 | 743 | |
93bfd616 PA |
744 | cfg->name = "OMAP SD/MMC"; |
745 | cfg->ops = &omap_hsmmc_ops; | |
746 | ||
747 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
748 | cfg->host_caps = host_caps_val & ~host_caps_mask; | |
749 | ||
750 | cfg->f_min = 400000; | |
bbbc1ae9 JS |
751 | |
752 | if (f_max != 0) | |
93bfd616 | 753 | cfg->f_max = f_max; |
bbbc1ae9 | 754 | else { |
93bfd616 PA |
755 | if (cfg->host_caps & MMC_MODE_HS) { |
756 | if (cfg->host_caps & MMC_MODE_HS_52MHz) | |
757 | cfg->f_max = 52000000; | |
bbbc1ae9 | 758 | else |
93bfd616 | 759 | cfg->f_max = 26000000; |
bbbc1ae9 | 760 | } else |
93bfd616 | 761 | cfg->f_max = 20000000; |
bbbc1ae9 | 762 | } |
de941241 | 763 | |
93bfd616 | 764 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
8feafcc4 | 765 | |
4ca9244d JR |
766 | #if defined(CONFIG_OMAP34XX) |
767 | /* | |
768 | * Silicon revs 2.1 and older do not support multiblock transfers. | |
769 | */ | |
770 | if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) | |
93bfd616 | 771 | cfg->b_max = 1; |
4ca9244d | 772 | #endif |
ae000e23 | 773 | mmc = mmc_create(cfg, priv); |
93bfd616 PA |
774 | if (mmc == NULL) |
775 | return -1; | |
de941241 SG |
776 | |
777 | return 0; | |
778 | } | |
a9d6a7e2 M |
779 | #else |
780 | static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) | |
781 | { | |
782 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
3d673ffc JJH |
783 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); |
784 | struct mmc_config *cfg = &plat->cfg; | |
46831c1a AF |
785 | struct omap2_mmc_platform_config *data = |
786 | (struct omap2_mmc_platform_config *)dev_get_driver_data(dev); | |
a9d6a7e2 | 787 | const void *fdt = gd->fdt_blob; |
e160f7d4 | 788 | int node = dev_of_offset(dev); |
a9d6a7e2 M |
789 | int val; |
790 | ||
4bc5e19e | 791 | priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *), |
46831c1a | 792 | MAP_NOCACHE) + data->reg_offset; |
a9d6a7e2 M |
793 | |
794 | cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; | |
795 | val = fdtdec_get_int(fdt, node, "bus-width", -1); | |
796 | if (val < 0) { | |
797 | printf("error: bus-width property missing\n"); | |
798 | return -ENOENT; | |
799 | } | |
800 | ||
801 | switch (val) { | |
802 | case 0x8: | |
803 | cfg->host_caps |= MMC_MODE_8BIT; | |
804 | case 0x4: | |
805 | cfg->host_caps |= MMC_MODE_4BIT; | |
806 | break; | |
807 | default: | |
808 | printf("error: invalid bus-width property\n"); | |
809 | return -ENOENT; | |
810 | } | |
811 | ||
812 | cfg->f_min = 400000; | |
813 | cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000); | |
814 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
815 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; | |
816 | ||
4de2de51 | 817 | #ifdef OMAP_HSMMC_USE_GPIO |
a9d6a7e2 | 818 | priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); |
4de2de51 | 819 | #endif |
a9d6a7e2 M |
820 | |
821 | return 0; | |
822 | } | |
823 | ||
17c9a1c1 JJH |
824 | #ifdef CONFIG_BLK |
825 | ||
826 | static int omap_hsmmc_bind(struct udevice *dev) | |
827 | { | |
828 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); | |
829 | ||
830 | return mmc_bind(dev, &plat->mmc, &plat->cfg); | |
831 | } | |
832 | #endif | |
a9d6a7e2 M |
833 | static int omap_hsmmc_probe(struct udevice *dev) |
834 | { | |
3d673ffc | 835 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); |
a9d6a7e2 M |
836 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
837 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
3d673ffc | 838 | struct mmc_config *cfg = &plat->cfg; |
a9d6a7e2 M |
839 | struct mmc *mmc; |
840 | ||
a9d6a7e2 M |
841 | cfg->name = "OMAP SD/MMC"; |
842 | cfg->ops = &omap_hsmmc_ops; | |
843 | ||
17c9a1c1 JJH |
844 | #ifdef CONFIG_BLK |
845 | mmc = &plat->mmc; | |
846 | #else | |
a9d6a7e2 M |
847 | mmc = mmc_create(cfg, priv); |
848 | if (mmc == NULL) | |
849 | return -1; | |
17c9a1c1 | 850 | #endif |
a9d6a7e2 | 851 | |
5cc6a245 M |
852 | #ifdef OMAP_HSMMC_USE_GPIO |
853 | gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); | |
854 | gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); | |
855 | #endif | |
856 | ||
cffe5d86 | 857 | mmc->dev = dev; |
a9d6a7e2 M |
858 | upriv->mmc = mmc; |
859 | ||
860 | return 0; | |
861 | } | |
862 | ||
46831c1a AF |
863 | static const struct omap2_mmc_platform_config omap3_mmc_pdata = { |
864 | .reg_offset = 0, | |
865 | }; | |
866 | ||
867 | static const struct omap2_mmc_platform_config am33xx_mmc_pdata = { | |
868 | .reg_offset = 0x100, | |
869 | }; | |
870 | ||
871 | static const struct omap2_mmc_platform_config omap4_mmc_pdata = { | |
872 | .reg_offset = 0x100, | |
873 | }; | |
874 | ||
a9d6a7e2 | 875 | static const struct udevice_id omap_hsmmc_ids[] = { |
46831c1a AF |
876 | { |
877 | .compatible = "ti,omap3-hsmmc", | |
878 | .data = (ulong)&omap3_mmc_pdata | |
879 | }, | |
880 | { | |
881 | .compatible = "ti,omap4-hsmmc", | |
882 | .data = (ulong)&omap4_mmc_pdata | |
883 | }, | |
884 | { | |
885 | .compatible = "ti,am33xx-hsmmc", | |
886 | .data = (ulong)&am33xx_mmc_pdata | |
887 | }, | |
a9d6a7e2 M |
888 | { } |
889 | }; | |
890 | ||
891 | U_BOOT_DRIVER(omap_hsmmc) = { | |
892 | .name = "omap_hsmmc", | |
893 | .id = UCLASS_MMC, | |
894 | .of_match = omap_hsmmc_ids, | |
895 | .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata, | |
17c9a1c1 JJH |
896 | #ifdef CONFIG_BLK |
897 | .bind = omap_hsmmc_bind, | |
898 | #endif | |
a9d6a7e2 M |
899 | .probe = omap_hsmmc_probe, |
900 | .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), | |
3d673ffc | 901 | .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat), |
a9d6a7e2 M |
902 | }; |
903 | #endif |