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mmc: omap_hsmmc: Add support for DMA (ADMA2)
[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c
CommitLineData
de941241
SG		 1/*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <common.h>
93bfd616 27#include <malloc.h>
f0d53e88 28#include <memalign.h>
de941241
SG		 29#include <mmc.h>
30#include <part.h>
31#include <i2c.h>
339d5789 32#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
cb199102 33#include <palmas.h>
339d5789 34#endif
de941241
SG		 35#include <asm/io.h>
36#include <asm/arch/mmc_host_def.h>
3b68939f
RQ		 37#if !defined(CONFIG_SOC_KEYSTONE)
38#include <asm/gpio.h>
96e0e7b3 39#include <asm/arch/sys_proto.h>
3b68939f 40#endif
2a48b3a2
TR		 41#ifdef CONFIG_MMC_OMAP36XX_PINS
42#include <asm/arch/mux.h>
43#endif
a9d6a7e2
M		 44#include <dm.h>
45
46DECLARE_GLOBAL_DATA_PTR;
de941241 47
ab769f22
PA		 48/* simplify defines to OMAP_HSMMC_USE_GPIO */
49#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
50 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
51#define OMAP_HSMMC_USE_GPIO
52#else
53#undef OMAP_HSMMC_USE_GPIO
54#endif
55
25c719e2
GI		 56/* common definitions for all OMAPs */
57#define SYSCTL_SRC (1 << 25)
58#define SYSCTL_SRD (1 << 26)
59
cc22b0c0
NK		 60struct omap_hsmmc_data {
61 struct hsmmc *base_addr;
c4d660d4 62#if !CONFIG_IS_ENABLED(DM_MMC)
93bfd616 63 struct mmc_config cfg;
3d673ffc 64#endif
ab769f22 65#ifdef OMAP_HSMMC_USE_GPIO
c4d660d4 66#if CONFIG_IS_ENABLED(DM_MMC)
a9d6a7e2
M		 67 struct gpio_desc cd_gpio; /* Change Detect GPIO */
68 struct gpio_desc wp_gpio; /* Write Protect GPIO */
69 bool cd_inverted;
70#else
e874d5b0 71 int cd_gpio;
e3913f56 72 int wp_gpio;
ab769f22 73#endif
a9d6a7e2 74#endif
f0d53e88
KVA		 75 u8 controller_flags;
76#ifndef CONFIG_OMAP34XX
77 struct omap_hsmmc_adma_desc *adma_desc_table;
78 uint desc_slot;
79#endif
80};
81
82#ifndef CONFIG_OMAP34XX
83struct omap_hsmmc_adma_desc {
84 u8 attr;
85 u8 reserved;
86 u16 len;
87 u32 addr;
cc22b0c0
NK		 88};
89
f0d53e88
KVA		 90#define ADMA_MAX_LEN 63488
91
92/* Decriptor table defines */
93#define ADMA_DESC_ATTR_VALID BIT(0)
94#define ADMA_DESC_ATTR_END BIT(1)
95#define ADMA_DESC_ATTR_INT BIT(2)
96#define ADMA_DESC_ATTR_ACT1 BIT(4)
97#define ADMA_DESC_ATTR_ACT2 BIT(5)
98
99#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
100#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
101#endif
102
eb9a28f6
NM		 103/* If we fail after 1 second wait, something is really bad */
104#define MAX_RETRY_MS 1000
105
f0d53e88
KVA		 106/* DMA transfers can take a long time if a lot a data is transferred.
107 * The timeout must take in account the amount of data. Let's assume
108 * that the time will never exceed 333 ms per MB (in other word we assume
109 * that the bandwidth is always above 3MB/s).
110 */
111#define DMA_TIMEOUT_PER_MB 333
112#define OMAP_HSMMC_USE_ADMA BIT(2)
113
933efe64
S		 114static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
115static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
116 unsigned int siz);
14fa2dd0 117
ae000e23
JJH		 118static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
119{
c4d660d4 120#if CONFIG_IS_ENABLED(DM_MMC)
ae000e23
JJH		 121 return dev_get_priv(mmc->dev);
122#else
123 return (struct omap_hsmmc_data *)mmc->priv;
124#endif
3d673ffc
JJH		 125}
126static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
127{
c4d660d4 128#if CONFIG_IS_ENABLED(DM_MMC)
3d673ffc
JJH		 129 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
130 return &plat->cfg;
131#else
132 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
133#endif
ae000e23
JJH		 134}
135
c4d660d4 136#if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
e874d5b0
NK		 137static int omap_mmc_setup_gpio_in(int gpio, const char *label)
138{
5915a2ad 139 int ret;
e874d5b0 140
5915a2ad
SG		 141#ifndef CONFIG_DM_GPIO
142 if (!gpio_is_valid(gpio))
e874d5b0 143 return -1;
5915a2ad
SG		 144#endif
145 ret = gpio_request(gpio, label);
146 if (ret)
147 return ret;
e874d5b0 148
5915a2ad
SG		 149 ret = gpio_direction_input(gpio);
150 if (ret)
151 return ret;
e874d5b0
NK		 152
153 return gpio;
154}
e874d5b0
NK		 155#endif
156
750121c3 157static unsigned char mmc_board_init(struct mmc *mmc)
de941241 158{
de941241 159#if defined(CONFIG_OMAP34XX)
3d673ffc 160 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
de941241
SG		 161 t2_t *t2_base = (t2_t *)T2_BASE;
162 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
b1e725f2 163 u32 pbias_lite;
6aca17c9
AF		 164#ifdef CONFIG_MMC_OMAP36XX_PINS
165 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
166#endif
de941241 167
b1e725f2
GI		 168 pbias_lite = readl(&t2_base->pbias_lite);
169 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
5bfdd1fc
AA		 170#ifdef CONFIG_TARGET_OMAP3_CAIRO
171 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
172 pbias_lite &= ~PBIASLITEVMODE0;
6aca17c9
AF		 173#endif
174#ifdef CONFIG_MMC_OMAP36XX_PINS
175 if (get_cpu_family() == CPU_OMAP36XX) {
176 /* Disable extended drain IO before changing PBIAS */
177 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
178 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
179 }
5bfdd1fc 180#endif
b1e725f2 181 writel(pbias_lite, &t2_base->pbias_lite);
aac5450e 182
b1e725f2 183 writel(pbias_lite | PBIASLITEPWRDNZ1 |
de941241
SG		 184 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
185 &t2_base->pbias_lite);
186
6aca17c9
AF		 187#ifdef CONFIG_MMC_OMAP36XX_PINS
188 if (get_cpu_family() == CPU_OMAP36XX)
189 /* Enable extended drain IO after changing PBIAS */
190 writel(wkup_ctrl |
191 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
192 OMAP34XX_CTRL_WKUP_CTRL);
193#endif
de941241
SG		 194 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
195 &t2_base->devconf0);
196
197 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
198 &t2_base->devconf1);
199
bbbc1ae9 200 /* Change from default of 52MHz to 26MHz if necessary */
3d673ffc 201 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
bbbc1ae9
JS		 202 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
203 &t2_base->ctl_prog_io1);
204
de941241
SG		 205 writel(readl(&prcm_base->fclken1_core) |
206 EN_MMC1 | EN_MMC2 | EN_MMC3,
207 &prcm_base->fclken1_core);
208
209 writel(readl(&prcm_base->iclken1_core) |
210 EN_MMC1 | EN_MMC2 | EN_MMC3,
211 &prcm_base->iclken1_core);
212#endif
213
b4b06006 214#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
14fa2dd0 215 /* PBIAS config needed for MMC1 only */
dc09127a 216 if (mmc_get_blk_desc(mmc)->devnum == 0)
b4b06006 217 vmmc_pbias_config(LDO_VOLT_3V0);
dd23e59d 218#endif
de941241
SG		 219
220 return 0;
221}
222
933efe64 223void mmc_init_stream(struct hsmmc *mmc_base)
de941241 224{
eb9a28f6 225 ulong start;
de941241
SG		 226
227 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
228
229 writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6
NM		 230 start = get_timer(0);
231 while (!(readl(&mmc_base->stat) & CC_MASK)) {
232 if (get_timer(0) - start > MAX_RETRY_MS) {
233 printf("%s: timedout waiting for cc!\n", __func__);
234 return;
235 }
236 }
de941241
SG		 237 writel(CC_MASK, &mmc_base->stat)
238 ;
239 writel(MMC_CMD0, &mmc_base->cmd)
240 ;
eb9a28f6
NM		 241 start = get_timer(0);
242 while (!(readl(&mmc_base->stat) & CC_MASK)) {
243 if (get_timer(0) - start > MAX_RETRY_MS) {
244 printf("%s: timedout waiting for cc2!\n", __func__);
245 return;
246 }
247 }
de941241
SG		 248 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
249}
250
ab769f22 251static int omap_hsmmc_init_setup(struct mmc *mmc)
de941241 252{
ae000e23 253 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
cc22b0c0 254 struct hsmmc *mmc_base;
de941241
SG		 255 unsigned int reg_val;
256 unsigned int dsor;
eb9a28f6 257 ulong start;
de941241 258
ae000e23 259 mmc_base = priv->base_addr;
14fa2dd0 260 mmc_board_init(mmc);
de941241
SG		 261
262 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
263 &mmc_base->sysconfig);
eb9a28f6
NM		 264 start = get_timer(0);
265 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
266 if (get_timer(0) - start > MAX_RETRY_MS) {
267 printf("%s: timedout waiting for cc2!\n", __func__);
915ffa52 268 return -ETIMEDOUT;
eb9a28f6
NM		 269 }
270 }
de941241 271 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6
NM		 272 start = get_timer(0);
273 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
274 if (get_timer(0) - start > MAX_RETRY_MS) {
275 printf("%s: timedout waiting for softresetall!\n",
276 __func__);
915ffa52 277 return -ETIMEDOUT;
eb9a28f6
NM		 278 }
279 }
f0d53e88
KVA		 280#ifndef CONFIG_OMAP34XX
281 reg_val = readl(&mmc_base->hl_hwinfo);
282 if (reg_val & MADMA_EN)
283 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
284#endif
de941241
SG		 285 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
286 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
287 &mmc_base->capa);
288
289 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
290
291 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
292 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
293 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
294
295 dsor = 240;
296 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
297 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
298 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
299 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
eb9a28f6
NM		 300 start = get_timer(0);
301 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
302 if (get_timer(0) - start > MAX_RETRY_MS) {
303 printf("%s: timedout waiting for ics!\n", __func__);
915ffa52 304 return -ETIMEDOUT;
eb9a28f6
NM		 305 }
306 }
de941241
SG		 307 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
308
309 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
310
311 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
f0d53e88
KVA		 312 IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
313 IE_CC, &mmc_base->ie);
de941241
SG		 314
315 mmc_init_stream(mmc_base);
316
317 return 0;
318}
319
25c719e2
GI		 320/*
321 * MMC controller internal finite state machine reset
322 *
323 * Used to reset command or data internal state machines, using respectively
324 * SRC or SRD bit of SYSCTL register
325 */
326static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
327{
328 ulong start;
329
330 mmc_reg_out(&mmc_base->sysctl, bit, bit);
331
61a6cc27
OT		 332 /*
333 * CMD(DAT) lines reset procedures are slightly different
334 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
335 * According to OMAP3 TRM:
336 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
337 * returns to 0x0.
338 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
339 * procedure steps must be as follows:
340 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
341 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
342 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
343 * 3. Wait until the SRC (SRD) bit returns to 0x0
344 * (reset procedure is completed).
345 */
346#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
dce55b93 347 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
61a6cc27
OT		 348 if (!(readl(&mmc_base->sysctl) & bit)) {
349 start = get_timer(0);
350 while (!(readl(&mmc_base->sysctl) & bit)) {
351 if (get_timer(0) - start > MAX_RETRY_MS)
352 return;
353 }
354 }
355#endif
25c719e2
GI		 356 start = get_timer(0);
357 while ((readl(&mmc_base->sysctl) & bit) != 0) {
358 if (get_timer(0) - start > MAX_RETRY_MS) {
359 printf("%s: timedout waiting for sysctl %x to clear\n",
360 __func__, bit);
361 return;
362 }
363 }
364}
f0d53e88
KVA		 365
366#ifndef CONFIG_OMAP34XX
367static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
368{
369 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
370 struct omap_hsmmc_adma_desc *desc;
371 u8 attr;
372
373 desc = &priv->adma_desc_table[priv->desc_slot];
374
375 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
376 if (!end)
377 priv->desc_slot++;
378 else
379 attr |= ADMA_DESC_ATTR_END;
380
381 desc->len = len;
382 desc->addr = (u32)buf;
383 desc->reserved = 0;
384 desc->attr = attr;
385}
386
387static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
388 struct mmc_data *data)
389{
390 uint total_len = data->blocksize * data->blocks;
391 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
392 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
393 int i = desc_count;
394 char *buf;
395
396 priv->desc_slot = 0;
397 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
398 memalign(ARCH_DMA_MINALIGN, desc_count *
399 sizeof(struct omap_hsmmc_adma_desc));
400
401 if (data->flags & MMC_DATA_READ)
402 buf = data->dest;
403 else
404 buf = (char *)data->src;
405
406 while (--i) {
407 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
408 buf += ADMA_MAX_LEN;
409 total_len -= ADMA_MAX_LEN;
410 }
411
412 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
413
414 flush_dcache_range((long)priv->adma_desc_table,
415 (long)priv->adma_desc_table +
416 ROUND(desc_count *
417 sizeof(struct omap_hsmmc_adma_desc),
418 ARCH_DMA_MINALIGN));
419}
420
421static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
422{
423 struct hsmmc *mmc_base;
424 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
425 u32 val;
426 char *buf;
427
428 mmc_base = priv->base_addr;
429 omap_hsmmc_prepare_adma_table(mmc, data);
430
431 if (data->flags & MMC_DATA_READ)
432 buf = data->dest;
433 else
434 buf = (char *)data->src;
435
436 val = readl(&mmc_base->hctl);
437 val |= DMA_SELECT;
438 writel(val, &mmc_base->hctl);
439
440 val = readl(&mmc_base->con);
441 val |= DMA_MASTER;
442 writel(val, &mmc_base->con);
443
444 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
445
446 flush_dcache_range((u32)buf,
447 (u32)buf +
448 ROUND(data->blocksize * data->blocks,
449 ARCH_DMA_MINALIGN));
450}
451
452static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
453{
454 struct hsmmc *mmc_base;
455 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
456 u32 val;
457
458 mmc_base = priv->base_addr;
459
460 val = readl(&mmc_base->con);
461 val &= ~DMA_MASTER;
462 writel(val, &mmc_base->con);
463
464 val = readl(&mmc_base->hctl);
465 val &= ~DMA_SELECT;
466 writel(val, &mmc_base->hctl);
467
468 kfree(priv->adma_desc_table);
469}
470#else
471#define omap_hsmmc_adma_desc
472#define omap_hsmmc_prepare_adma_table
473#define omap_hsmmc_prepare_data
474#define omap_hsmmc_dma_cleanup
475#endif
476
c4d660d4 477#if !CONFIG_IS_ENABLED(DM_MMC)
ab769f22 478static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
de941241
SG		 479 struct mmc_data *data)
480{
ae000e23 481 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
b5511d6c
JJH		 482#else
483static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
484 struct mmc_data *data)
485{
486 struct omap_hsmmc_data *priv = dev_get_priv(dev);
f0d53e88
KVA		 487#ifndef CONFIG_OMAP34XX
488 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
489 struct mmc *mmc = upriv->mmc;
490#endif
b5511d6c 491#endif
cc22b0c0 492 struct hsmmc *mmc_base;
de941241 493 unsigned int flags, mmc_stat;
eb9a28f6 494 ulong start;
de941241 495
ae000e23 496 mmc_base = priv->base_addr;
eb9a28f6 497 start = get_timer(0);
a7778f8f 498 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
eb9a28f6 499 if (get_timer(0) - start > MAX_RETRY_MS) {
a7778f8f
TR		 500 printf("%s: timedout waiting on cmd inhibit to clear\n",
501 __func__);
915ffa52 502 return -ETIMEDOUT;
eb9a28f6
NM		 503 }
504 }
de941241 505 writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6
NM		 506 start = get_timer(0);
507 while (readl(&mmc_base->stat)) {
508 if (get_timer(0) - start > MAX_RETRY_MS) {
15ceb1de
GI		 509 printf("%s: timedout waiting for STAT (%x) to clear\n",
510 __func__, readl(&mmc_base->stat));
915ffa52 511 return -ETIMEDOUT;
eb9a28f6
NM		 512 }
513 }
de941241
SG		 514 /*
515 * CMDREG
516 * CMDIDX[13:8] : Command index
517 * DATAPRNT[5] : Data Present Select
518 * ENCMDIDX[4] : Command Index Check Enable
519 * ENCMDCRC[3] : Command CRC Check Enable
520 * RSPTYP[1:0]
521 * 00 = No Response
522 * 01 = Length 136
523 * 10 = Length 48
524 * 11 = Length 48 Check busy after response
525 */
526 /* Delay added before checking the status of frq change
527 * retry not supported by mmc.c(core file)
528 */
529 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
530 udelay(50000); /* wait 50 ms */
531
532 if (!(cmd->resp_type & MMC_RSP_PRESENT))
533 flags = 0;
534 else if (cmd->resp_type & MMC_RSP_136)
535 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
536 else if (cmd->resp_type & MMC_RSP_BUSY)
537 flags = RSP_TYPE_LGHT48B;
538 else
539 flags = RSP_TYPE_LGHT48;
540
541 /* enable default flags */
542 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
543 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
544
545 if (cmd->resp_type & MMC_RSP_CRC)
546 flags |= CCCE_CHECK;
547 if (cmd->resp_type & MMC_RSP_OPCODE)
548 flags |= CICE_CHECK;
549
550 if (data) {
551 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
552 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
553 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
554 data->blocksize = 512;
555 writel(data->blocksize | (data->blocks << 16),
556 &mmc_base->blk);
557 } else
558 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
559
560 if (data->flags & MMC_DATA_READ)
561 flags |= (DP_DATA | DDIR_READ);
562 else
563 flags |= (DP_DATA | DDIR_WRITE);
f0d53e88
KVA		 564
565#ifndef CONFIG_OMAP34XX
566 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
567 !mmc_is_tuning_cmd(cmd->cmdidx)) {
568 omap_hsmmc_prepare_data(mmc, data);
569 flags |= DE_ENABLE;
570 }
571#endif
de941241
SG		 572 }
573
574 writel(cmd->cmdarg, &mmc_base->arg);
152ba363 575 udelay(20); /* To fix "No status update" error on eMMC */
de941241
SG		 576 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
577
eb9a28f6 578 start = get_timer(0);
de941241
SG		 579 do {
580 mmc_stat = readl(&mmc_base->stat);
f0d53e88 581 if (get_timer(start) > MAX_RETRY_MS) {
eb9a28f6 582 printf("%s : timeout: No status update\n", __func__);
915ffa52 583 return -ETIMEDOUT;
eb9a28f6
NM		 584 }
585 } while (!mmc_stat);
de941241 586
25c719e2
GI		 587 if ((mmc_stat & IE_CTO) != 0) {
588 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
915ffa52 589 return -ETIMEDOUT;
25c719e2 590 } else if ((mmc_stat & ERRI_MASK) != 0)
de941241
SG		 591 return -1;
592
593 if (mmc_stat & CC_MASK) {
594 writel(CC_MASK, &mmc_base->stat);
595 if (cmd->resp_type & MMC_RSP_PRESENT) {
596 if (cmd->resp_type & MMC_RSP_136) {
597 /* response type 2 */
598 cmd->response[3] = readl(&mmc_base->rsp10);
599 cmd->response[2] = readl(&mmc_base->rsp32);
600 cmd->response[1] = readl(&mmc_base->rsp54);
601 cmd->response[0] = readl(&mmc_base->rsp76);
602 } else
603 /* response types 1, 1b, 3, 4, 5, 6 */
604 cmd->response[0] = readl(&mmc_base->rsp10);
605 }
606 }
607
f0d53e88
KVA		 608#ifndef CONFIG_OMAP34XX
609 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
610 !mmc_is_tuning_cmd(cmd->cmdidx)) {
611 u32 sz_mb, timeout;
612
613 if (mmc_stat & IE_ADMAE) {
614 omap_hsmmc_dma_cleanup(mmc);
615 return -EIO;
616 }
617
618 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
619 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
620 if (timeout < MAX_RETRY_MS)
621 timeout = MAX_RETRY_MS;
622
623 start = get_timer(0);
624 do {
625 mmc_stat = readl(&mmc_base->stat);
626 if (mmc_stat & TC_MASK) {
627 writel(readl(&mmc_base->stat) | TC_MASK,
628 &mmc_base->stat);
629 break;
630 }
631 if (get_timer(start) > timeout) {
632 printf("%s : DMA timeout: No status update\n",
633 __func__);
634 return -ETIMEDOUT;
635 }
636 } while (1);
637
638 omap_hsmmc_dma_cleanup(mmc);
639 return 0;
640 }
641#endif
642
de941241
SG		 643 if (data && (data->flags & MMC_DATA_READ)) {
644 mmc_read_data(mmc_base, data->dest,
645 data->blocksize * data->blocks);
646 } else if (data && (data->flags & MMC_DATA_WRITE)) {
647 mmc_write_data(mmc_base, data->src,
648 data->blocksize * data->blocks);
649 }
650 return 0;
651}
652
933efe64 653static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
de941241
SG		 654{
655 unsigned int *output_buf = (unsigned int *)buf;
656 unsigned int mmc_stat;
657 unsigned int count;
658
659 /*
660 * Start Polled Read
661 */
662 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
663 count /= 4;
664
665 while (size) {
eb9a28f6 666 ulong start = get_timer(0);
de941241
SG		 667 do {
668 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 669 if (get_timer(0) - start > MAX_RETRY_MS) {
670 printf("%s: timedout waiting for status!\n",
671 __func__);
915ffa52 672 return -ETIMEDOUT;
eb9a28f6 673 }
de941241
SG		 674 } while (mmc_stat == 0);
675
25c719e2
GI		 676 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
677 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
678
de941241
SG		 679 if ((mmc_stat & ERRI_MASK) != 0)
680 return 1;
681
682 if (mmc_stat & BRR_MASK) {
683 unsigned int k;
684
685 writel(readl(&mmc_base->stat) | BRR_MASK,
686 &mmc_base->stat);
687 for (k = 0; k < count; k++) {
688 *output_buf = readl(&mmc_base->data);
689 output_buf++;
690 }
691 size -= (count*4);
692 }
693
694 if (mmc_stat & BWR_MASK)
695 writel(readl(&mmc_base->stat) | BWR_MASK,
696 &mmc_base->stat);
697
698 if (mmc_stat & TC_MASK) {
699 writel(readl(&mmc_base->stat) | TC_MASK,
700 &mmc_base->stat);
701 break;
702 }
703 }
704 return 0;
705}
706
933efe64
S		 707static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
708 unsigned int size)
de941241
SG		 709{
710 unsigned int *input_buf = (unsigned int *)buf;
711 unsigned int mmc_stat;
712 unsigned int count;
713
714 /*
152ba363 715 * Start Polled Write
de941241
SG		 716 */
717 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
718 count /= 4;
719
720 while (size) {
eb9a28f6 721 ulong start = get_timer(0);
de941241
SG		 722 do {
723 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 724 if (get_timer(0) - start > MAX_RETRY_MS) {
725 printf("%s: timedout waiting for status!\n",
726 __func__);
915ffa52 727 return -ETIMEDOUT;
eb9a28f6 728 }
de941241
SG		 729 } while (mmc_stat == 0);
730
25c719e2
GI		 731 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
732 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
733
de941241
SG		 734 if ((mmc_stat & ERRI_MASK) != 0)
735 return 1;
736
737 if (mmc_stat & BWR_MASK) {
738 unsigned int k;
739
740 writel(readl(&mmc_base->stat) | BWR_MASK,
741 &mmc_base->stat);
742 for (k = 0; k < count; k++) {
743 writel(*input_buf, &mmc_base->data);
744 input_buf++;
745 }
746 size -= (count*4);
747 }
748
749 if (mmc_stat & BRR_MASK)
750 writel(readl(&mmc_base->stat) | BRR_MASK,
751 &mmc_base->stat);
752
753 if (mmc_stat & TC_MASK) {
754 writel(readl(&mmc_base->stat) | TC_MASK,
755 &mmc_base->stat);
756 break;
757 }
758 }
759 return 0;
760}
761
c4d660d4 762#if !CONFIG_IS_ENABLED(DM_MMC)
07b0b9c0 763static int omap_hsmmc_set_ios(struct mmc *mmc)
de941241 764{
ae000e23 765 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
b5511d6c
JJH		 766#else
767static int omap_hsmmc_set_ios(struct udevice *dev)
768{
769 struct omap_hsmmc_data *priv = dev_get_priv(dev);
770 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
771 struct mmc *mmc = upriv->mmc;
772#endif
cc22b0c0 773 struct hsmmc *mmc_base;
de941241 774 unsigned int dsor = 0;
eb9a28f6 775 ulong start;
de941241 776
ae000e23 777 mmc_base = priv->base_addr;
de941241
SG		 778 /* configue bus width */
779 switch (mmc->bus_width) {
780 case 8:
781 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
782 &mmc_base->con);
783 break;
784
785 case 4:
786 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
787 &mmc_base->con);
788 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
789 &mmc_base->hctl);
790 break;
791
792 case 1:
793 default:
794 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
795 &mmc_base->con);
796 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
797 &mmc_base->hctl);
798 break;
799 }
800
801 /* configure clock with 96Mhz system clock.
802 */
803 if (mmc->clock != 0) {
804 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
805 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
806 dsor++;
807 }
808
809 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
810 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
811
812 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
813 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
814
eb9a28f6
NM		 815 start = get_timer(0);
816 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
817 if (get_timer(0) - start > MAX_RETRY_MS) {
818 printf("%s: timedout waiting for ics!\n", __func__);
07b0b9c0 819 return -ETIMEDOUT;
eb9a28f6
NM		 820 }
821 }
de941241 822 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
07b0b9c0
JC		 823
824 return 0;
de941241
SG		 825}
826
ab769f22 827#ifdef OMAP_HSMMC_USE_GPIO
c4d660d4 828#if CONFIG_IS_ENABLED(DM_MMC)
b5511d6c 829static int omap_hsmmc_getcd(struct udevice *dev)
a9d6a7e2 830{
b5511d6c 831 struct omap_hsmmc_data *priv = dev_get_priv(dev);
a9d6a7e2
M		 832 int value;
833
834 value = dm_gpio_get_value(&priv->cd_gpio);
835 /* if no CD return as 1 */
836 if (value < 0)
837 return 1;
838
839 if (priv->cd_inverted)
840 return !value;
841 return value;
842}
843
b5511d6c 844static int omap_hsmmc_getwp(struct udevice *dev)
a9d6a7e2 845{
b5511d6c 846 struct omap_hsmmc_data *priv = dev_get_priv(dev);
a9d6a7e2
M		 847 int value;
848
849 value = dm_gpio_get_value(&priv->wp_gpio);
850 /* if no WP return as 0 */
851 if (value < 0)
852 return 0;
853 return value;
854}
855#else
ab769f22
PA		 856static int omap_hsmmc_getcd(struct mmc *mmc)
857{
ae000e23 858 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
ab769f22
PA		 859 int cd_gpio;
860
861 /* if no CD return as 1 */
ae000e23 862 cd_gpio = priv->cd_gpio;
ab769f22
PA		 863 if (cd_gpio < 0)
864 return 1;
865
0b03a931
IG		 866 /* NOTE: assumes card detect signal is active-low */
867 return !gpio_get_value(cd_gpio);
ab769f22
PA		 868}
869
870static int omap_hsmmc_getwp(struct mmc *mmc)
871{
ae000e23 872 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
ab769f22
PA		 873 int wp_gpio;
874
875 /* if no WP return as 0 */
ae000e23 876 wp_gpio = priv->wp_gpio;
ab769f22
PA		 877 if (wp_gpio < 0)
878 return 0;
879
0b03a931 880 /* NOTE: assumes write protect signal is active-high */
ab769f22
PA		 881 return gpio_get_value(wp_gpio);
882}
883#endif
a9d6a7e2 884#endif
ab769f22 885
c4d660d4 886#if CONFIG_IS_ENABLED(DM_MMC)
b5511d6c
JJH		 887static const struct dm_mmc_ops omap_hsmmc_ops = {
888 .send_cmd = omap_hsmmc_send_cmd,
889 .set_ios = omap_hsmmc_set_ios,
890#ifdef OMAP_HSMMC_USE_GPIO
891 .get_cd = omap_hsmmc_getcd,
892 .get_wp = omap_hsmmc_getwp,
893#endif
894};
895#else
ab769f22
PA		 896static const struct mmc_ops omap_hsmmc_ops = {
897 .send_cmd = omap_hsmmc_send_cmd,
898 .set_ios = omap_hsmmc_set_ios,
899 .init = omap_hsmmc_init_setup,
900#ifdef OMAP_HSMMC_USE_GPIO
901 .getcd = omap_hsmmc_getcd,
902 .getwp = omap_hsmmc_getwp,
903#endif
904};
b5511d6c 905#endif
ab769f22 906
c4d660d4 907#if !CONFIG_IS_ENABLED(DM_MMC)
e3913f56
NK		 908int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
909 int wp_gpio)
de941241 910{
93bfd616 911 struct mmc *mmc;
ae000e23 912 struct omap_hsmmc_data *priv;
93bfd616
PA		 913 struct mmc_config *cfg;
914 uint host_caps_val;
915
ae000e23
JJH		 916 priv = malloc(sizeof(*priv));
917 if (priv == NULL)
93bfd616 918 return -1;
de941241 919
5a20397b 920 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
de941241
SG		 921
922 switch (dev_index) {
923 case 0:
ae000e23 924 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 925 break;
1037d585 926#ifdef OMAP_HSMMC2_BASE
de941241 927 case 1:
ae000e23 928 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
152ba363 929#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
3891a54f 930 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
3b68939f
RQ		 931 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
932 defined(CONFIG_HSMMC2_8BIT)
152ba363
LP		 933 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
934 host_caps_val |= MMC_MODE_8BIT;
935#endif
de941241 936 break;
1037d585
TR		 937#endif
938#ifdef OMAP_HSMMC3_BASE
de941241 939 case 2:
ae000e23 940 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
3891a54f 941#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
152ba363
LP		 942 /* Enable 8-bit interface for eMMC on DRA7XX */
943 host_caps_val |= MMC_MODE_8BIT;
944#endif
de941241 945 break;
1037d585 946#endif
de941241 947 default:
ae000e23 948 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241
SG		 949 return 1;
950 }
ab769f22
PA		 951#ifdef OMAP_HSMMC_USE_GPIO
952 /* on error gpio values are set to -1, which is what we want */
ae000e23
JJH		 953 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
954 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
ab769f22 955#endif
173ddc5b 956
ae000e23 957 cfg = &priv->cfg;
de941241 958
93bfd616
PA		 959 cfg->name = "OMAP SD/MMC";
960 cfg->ops = &omap_hsmmc_ops;
961
962 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
963 cfg->host_caps = host_caps_val & ~host_caps_mask;
964
965 cfg->f_min = 400000;
bbbc1ae9
JS		 966
967 if (f_max != 0)
93bfd616 968 cfg->f_max = f_max;
bbbc1ae9 969 else {
93bfd616
PA		 970 if (cfg->host_caps & MMC_MODE_HS) {
971 if (cfg->host_caps & MMC_MODE_HS_52MHz)
972 cfg->f_max = 52000000;
bbbc1ae9 973 else
93bfd616 974 cfg->f_max = 26000000;
bbbc1ae9 975 } else
93bfd616 976 cfg->f_max = 20000000;
bbbc1ae9 977 }
de941241 978
93bfd616 979 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
8feafcc4 980
4ca9244d
JR		 981#if defined(CONFIG_OMAP34XX)
982 /*
983 * Silicon revs 2.1 and older do not support multiblock transfers.
984 */
985 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
93bfd616 986 cfg->b_max = 1;
4ca9244d 987#endif
ae000e23 988 mmc = mmc_create(cfg, priv);
93bfd616
PA		 989 if (mmc == NULL)
990 return -1;
de941241
SG		 991
992 return 0;
993}
a9d6a7e2 994#else
2558c049 995#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2
M		 996static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
997{
3d673ffc
JJH		 998 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
999 struct mmc_config *cfg = &plat->cfg;
a9d6a7e2 1000 const void *fdt = gd->fdt_blob;
e160f7d4 1001 int node = dev_of_offset(dev);
a9d6a7e2
M		 1002 int val;
1003
a821c4af
SG		 1004 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1005 sizeof(struct hsmmc *),
741726ae 1006 MAP_NOCACHE);
a9d6a7e2
M		 1007
1008 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
1009 val = fdtdec_get_int(fdt, node, "bus-width", -1);
1010 if (val < 0) {
1011 printf("error: bus-width property missing\n");
1012 return -ENOENT;
1013 }
1014
1015 switch (val) {
1016 case 0x8:
1017 cfg->host_caps |= MMC_MODE_8BIT;
1018 case 0x4:
1019 cfg->host_caps |= MMC_MODE_4BIT;
1020 break;
1021 default:
1022 printf("error: invalid bus-width property\n");
1023 return -ENOENT;
1024 }
1025
1026 cfg->f_min = 400000;
1027 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
1028 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1029 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1030
4de2de51 1031#ifdef OMAP_HSMMC_USE_GPIO
2558c049 1032 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
4de2de51 1033#endif
a9d6a7e2
M		 1034
1035 return 0;
1036}
2558c049 1037#endif
a9d6a7e2 1038
17c9a1c1
JJH		 1039#ifdef CONFIG_BLK
1040
1041static int omap_hsmmc_bind(struct udevice *dev)
1042{
1043 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1044
1045 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1046}
1047#endif
a9d6a7e2
M		 1048static int omap_hsmmc_probe(struct udevice *dev)
1049{
3d673ffc 1050 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
a9d6a7e2
M		 1051 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1052 struct omap_hsmmc_data *priv = dev_get_priv(dev);
3d673ffc 1053 struct mmc_config *cfg = &plat->cfg;
a9d6a7e2
M		 1054 struct mmc *mmc;
1055
a9d6a7e2 1056 cfg->name = "OMAP SD/MMC";
2558c049
LV		 1057 priv->base_addr = plat->base_addr;
1058#ifdef OMAP_HSMMC_USE_GPIO
1059 priv->cd_inverted = plat->cd_inverted;
1060#endif
a9d6a7e2 1061
17c9a1c1
JJH		 1062#ifdef CONFIG_BLK
1063 mmc = &plat->mmc;
1064#else
a9d6a7e2
M		 1065 mmc = mmc_create(cfg, priv);
1066 if (mmc == NULL)
1067 return -1;
17c9a1c1 1068#endif
a9d6a7e2 1069
2558c049 1070#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
5cc6a245
M		 1071 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1072 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1073#endif
1074
cffe5d86 1075 mmc->dev = dev;
a9d6a7e2
M		 1076 upriv->mmc = mmc;
1077
b5511d6c 1078 return omap_hsmmc_init_setup(mmc);
a9d6a7e2
M		 1079}
1080
2558c049 1081#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2 1082static const struct udevice_id omap_hsmmc_ids[] = {
741726ae
JJH		 1083 { .compatible = "ti,omap3-hsmmc" },
1084 { .compatible = "ti,omap4-hsmmc" },
1085 { .compatible = "ti,am33xx-hsmmc" },
a9d6a7e2
M		 1086 { }
1087};
2558c049 1088#endif
a9d6a7e2
M		 1089
1090U_BOOT_DRIVER(omap_hsmmc) = {
1091 .name = "omap_hsmmc",
1092 .id = UCLASS_MMC,
2558c049 1093#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2
M		 1094 .of_match = omap_hsmmc_ids,
1095 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2558c049
LV		 1096 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1097#endif
17c9a1c1
JJH		 1098#ifdef CONFIG_BLK
1099 .bind = omap_hsmmc_bind,
1100#endif
b5511d6c 1101 .ops = &omap_hsmmc_ops,
a9d6a7e2
M		 1102 .probe = omap_hsmmc_probe,
1103 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
cbcb1701 1104 .flags = DM_FLAG_PRE_RELOC,
a9d6a7e2
M		 1105};
1106#endif
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