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0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
4 | * (C) Copyright 2008 Armadeus Systems nc | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <malloc.h> | |
26 | #include <net.h> | |
27 | #include <miiphy.h> | |
28 | #include "fec_mxc.h" | |
29 | ||
30 | #include <asm/arch/clock.h> | |
31 | #include <asm/arch/imx-regs.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/errno.h> | |
e2a66e60 | 34 | #include <linux/compiler.h> |
0b23fb36 IY |
35 | |
36 | DECLARE_GLOBAL_DATA_PTR; | |
37 | ||
38 | #ifndef CONFIG_MII | |
39 | #error "CONFIG_MII has to be defined!" | |
40 | #endif | |
41 | ||
5c1ad3e6 EN |
42 | #ifndef CONFIG_FEC_XCV_TYPE |
43 | #define CONFIG_FEC_XCV_TYPE MII100 | |
392b8502 MV |
44 | #endif |
45 | ||
be7e87e2 MV |
46 | /* |
47 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
48 | * sending and after receiving. | |
49 | */ | |
5c1ad3e6 EN |
50 | #ifdef CONFIG_MX28 |
51 | #define CONFIG_FEC_MXC_SWAP_PACKET | |
52 | #endif | |
53 | ||
54 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) | |
55 | ||
56 | /* Check various alignment issues at compile time */ | |
57 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) | |
58 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" | |
59 | #endif | |
60 | ||
61 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ | |
62 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) | |
63 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" | |
be7e87e2 MV |
64 | #endif |
65 | ||
0b23fb36 IY |
66 | #undef DEBUG |
67 | ||
68 | struct nbuf { | |
69 | uint8_t data[1500]; /**< actual data */ | |
70 | int length; /**< actual length */ | |
71 | int used; /**< buffer in use or not */ | |
72 | uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ | |
73 | }; | |
74 | ||
5c1ad3e6 | 75 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
76 | static void swap_packet(uint32_t *packet, int length) |
77 | { | |
78 | int i; | |
79 | ||
80 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
81 | packet[i] = __swab32(packet[i]); | |
82 | } | |
83 | #endif | |
84 | ||
0b23fb36 IY |
85 | /* |
86 | * MII-interface related functions | |
87 | */ | |
13947f43 TK |
88 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, |
89 | uint8_t regAddr) | |
0b23fb36 | 90 | { |
0b23fb36 IY |
91 | uint32_t reg; /* convenient holder for the PHY register */ |
92 | uint32_t phy; /* convenient holder for the PHY */ | |
93 | uint32_t start; | |
13947f43 | 94 | int val; |
0b23fb36 IY |
95 | |
96 | /* | |
97 | * reading from any PHY's register is done by properly | |
98 | * programming the FEC's MII data register. | |
99 | */ | |
d133b881 | 100 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
101 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; |
102 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
103 | ||
104 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 105 | phy | reg, ð->mii_data); |
0b23fb36 IY |
106 | |
107 | /* | |
108 | * wait for the related interrupt | |
109 | */ | |
a60d1e5b | 110 | start = get_timer(0); |
d133b881 | 111 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
112 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
113 | printf("Read MDIO failed...\n"); | |
114 | return -1; | |
115 | } | |
116 | } | |
117 | ||
118 | /* | |
119 | * clear mii interrupt bit | |
120 | */ | |
d133b881 | 121 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
122 | |
123 | /* | |
124 | * it's now safe to read the PHY's register | |
125 | */ | |
13947f43 TK |
126 | val = (unsigned short)readl(ð->mii_data); |
127 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, | |
128 | regAddr, val); | |
129 | return val; | |
0b23fb36 IY |
130 | } |
131 | ||
4294b248 SB |
132 | static void fec_mii_setspeed(struct fec_priv *fec) |
133 | { | |
134 | /* | |
135 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
136 | * and do not drop the Preamble. | |
137 | */ | |
138 | writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, | |
139 | &fec->eth->mii_speed); | |
13947f43 | 140 | debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed)); |
4294b248 | 141 | } |
0b23fb36 | 142 | |
13947f43 TK |
143 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, |
144 | uint8_t regAddr, uint16_t data) | |
145 | { | |
0b23fb36 IY |
146 | uint32_t reg; /* convenient holder for the PHY register */ |
147 | uint32_t phy; /* convenient holder for the PHY */ | |
148 | uint32_t start; | |
149 | ||
150 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; | |
151 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
152 | ||
153 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 154 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 IY |
155 | |
156 | /* | |
157 | * wait for the MII interrupt | |
158 | */ | |
a60d1e5b | 159 | start = get_timer(0); |
d133b881 | 160 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
161 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
162 | printf("Write MDIO failed...\n"); | |
163 | return -1; | |
164 | } | |
165 | } | |
166 | ||
167 | /* | |
168 | * clear MII interrupt bit | |
169 | */ | |
d133b881 | 170 | writel(FEC_IEVENT_MII, ð->ievent); |
13947f43 | 171 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, |
0b23fb36 IY |
172 | regAddr, data); |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
13947f43 TK |
177 | int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr) |
178 | { | |
179 | return fec_mdio_read(bus->priv, phyAddr, regAddr); | |
180 | } | |
181 | ||
182 | int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr, | |
183 | u16 data) | |
184 | { | |
185 | return fec_mdio_write(bus->priv, phyAddr, regAddr, data); | |
186 | } | |
187 | ||
188 | #ifndef CONFIG_PHYLIB | |
0b23fb36 IY |
189 | static int miiphy_restart_aneg(struct eth_device *dev) |
190 | { | |
b774fe9d SB |
191 | int ret = 0; |
192 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) | |
9e27e9dc | 193 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 194 | struct ethernet_regs *eth = fec->bus->priv; |
9e27e9dc | 195 | |
0b23fb36 IY |
196 | /* |
197 | * Wake up from sleep if necessary | |
198 | * Reset PHY, then delay 300ns | |
199 | */ | |
cb17b92d | 200 | #ifdef CONFIG_MX27 |
13947f43 | 201 | fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); |
cb17b92d | 202 | #endif |
13947f43 | 203 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
0b23fb36 IY |
204 | udelay(1000); |
205 | ||
206 | /* | |
207 | * Set the auto-negotiation advertisement register bits | |
208 | */ | |
13947f43 | 209 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
8ef583a0 MF |
210 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
211 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
13947f43 | 212 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
8ef583a0 | 213 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
214 | |
215 | if (fec->mii_postcall) | |
216 | ret = fec->mii_postcall(fec->phy_id); | |
217 | ||
b774fe9d | 218 | #endif |
2e5f4421 | 219 | return ret; |
0b23fb36 IY |
220 | } |
221 | ||
222 | static int miiphy_wait_aneg(struct eth_device *dev) | |
223 | { | |
224 | uint32_t start; | |
13947f43 | 225 | int status; |
9e27e9dc | 226 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 227 | struct ethernet_regs *eth = fec->bus->priv; |
0b23fb36 IY |
228 | |
229 | /* | |
230 | * Wait for AN completion | |
231 | */ | |
a60d1e5b | 232 | start = get_timer(0); |
0b23fb36 IY |
233 | do { |
234 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
235 | printf("%s: Autonegotiation timeout\n", dev->name); | |
236 | return -1; | |
237 | } | |
238 | ||
13947f43 TK |
239 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
240 | if (status < 0) { | |
241 | printf("%s: Autonegotiation failed. status: %d\n", | |
0b23fb36 IY |
242 | dev->name, status); |
243 | return -1; | |
244 | } | |
8ef583a0 | 245 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
246 | |
247 | return 0; | |
248 | } | |
13947f43 TK |
249 | #endif |
250 | ||
0b23fb36 IY |
251 | static int fec_rx_task_enable(struct fec_priv *fec) |
252 | { | |
253 | writel(1 << 24, &fec->eth->r_des_active); | |
254 | return 0; | |
255 | } | |
256 | ||
257 | static int fec_rx_task_disable(struct fec_priv *fec) | |
258 | { | |
259 | return 0; | |
260 | } | |
261 | ||
262 | static int fec_tx_task_enable(struct fec_priv *fec) | |
263 | { | |
264 | writel(1 << 24, &fec->eth->x_des_active); | |
265 | return 0; | |
266 | } | |
267 | ||
268 | static int fec_tx_task_disable(struct fec_priv *fec) | |
269 | { | |
270 | return 0; | |
271 | } | |
272 | ||
273 | /** | |
274 | * Initialize receive task's buffer descriptors | |
275 | * @param[in] fec all we know about the device yet | |
276 | * @param[in] count receive buffer count to be allocated | |
5c1ad3e6 | 277 | * @param[in] dsize desired size of each receive buffer |
0b23fb36 IY |
278 | * @return 0 on success |
279 | * | |
280 | * For this task we need additional memory for the data buffers. And each | |
281 | * data buffer requires some alignment. Thy must be aligned to a specific | |
5c1ad3e6 | 282 | * boundary each. |
0b23fb36 | 283 | */ |
5c1ad3e6 | 284 | static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
0b23fb36 | 285 | { |
5c1ad3e6 EN |
286 | uint32_t size; |
287 | int i; | |
288 | ||
0b23fb36 | 289 | /* |
5c1ad3e6 EN |
290 | * Allocate memory for the buffers. This allocation respects the |
291 | * alignment | |
0b23fb36 | 292 | */ |
5c1ad3e6 EN |
293 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
294 | for (i = 0; i < count; i++) { | |
295 | uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); | |
296 | if (data_ptr == 0) { | |
297 | uint8_t *data = memalign(ARCH_DMA_MINALIGN, | |
298 | size); | |
299 | if (!data) { | |
300 | printf("%s: error allocating rxbuf %d\n", | |
301 | __func__, i); | |
302 | goto err; | |
303 | } | |
304 | writel((uint32_t)data, &fec->rbd_base[i].data_pointer); | |
305 | } /* needs allocation */ | |
306 | writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status); | |
307 | writew(0, &fec->rbd_base[i].data_length); | |
308 | } | |
309 | ||
310 | /* Mark the last RBD to close the ring. */ | |
311 | writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status); | |
0b23fb36 IY |
312 | fec->rbd_index = 0; |
313 | ||
314 | return 0; | |
5c1ad3e6 EN |
315 | |
316 | err: | |
317 | for (; i >= 0; i--) { | |
318 | uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); | |
319 | free((void *)data_ptr); | |
320 | } | |
321 | ||
322 | return -ENOMEM; | |
0b23fb36 IY |
323 | } |
324 | ||
325 | /** | |
326 | * Initialize transmit task's buffer descriptors | |
327 | * @param[in] fec all we know about the device yet | |
328 | * | |
329 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
330 | * Note: There is a race condition in the hardware. When only one BD is in | |
331 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
332 | * This bit in combination with the READY bit results into double transmit | |
333 | * of each data buffer. It seems the state machine checks READY earlier then | |
334 | * resetting it after the first transfer. | |
335 | * Using two BDs solves this issue. | |
336 | */ | |
337 | static void fec_tbd_init(struct fec_priv *fec) | |
338 | { | |
5c1ad3e6 EN |
339 | unsigned addr = (unsigned)fec->tbd_base; |
340 | unsigned size = roundup(2 * sizeof(struct fec_bd), | |
341 | ARCH_DMA_MINALIGN); | |
0b23fb36 IY |
342 | writew(0x0000, &fec->tbd_base[0].status); |
343 | writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); | |
344 | fec->tbd_index = 0; | |
5c1ad3e6 | 345 | flush_dcache_range(addr, addr+size); |
0b23fb36 IY |
346 | } |
347 | ||
348 | /** | |
349 | * Mark the given read buffer descriptor as free | |
350 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
351 | * @param[in] pRbd buffer descriptor to mark free again | |
352 | */ | |
353 | static void fec_rbd_clean(int last, struct fec_bd *pRbd) | |
354 | { | |
5c1ad3e6 | 355 | unsigned short flags = FEC_RBD_EMPTY; |
0b23fb36 | 356 | if (last) |
5c1ad3e6 EN |
357 | flags |= FEC_RBD_WRAP; |
358 | writew(flags, &pRbd->status); | |
0b23fb36 IY |
359 | writew(0, &pRbd->data_length); |
360 | } | |
361 | ||
be252b65 FE |
362 | static int fec_get_hwaddr(struct eth_device *dev, int dev_id, |
363 | unsigned char *mac) | |
0b23fb36 | 364 | { |
be252b65 | 365 | imx_get_mac_from_fuse(dev_id, mac); |
2e236bf2 | 366 | return !is_valid_ether_addr(mac); |
0b23fb36 IY |
367 | } |
368 | ||
4294b248 | 369 | static int fec_set_hwaddr(struct eth_device *dev) |
0b23fb36 | 370 | { |
4294b248 | 371 | uchar *mac = dev->enetaddr; |
0b23fb36 IY |
372 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
373 | ||
374 | writel(0, &fec->eth->iaddr1); | |
375 | writel(0, &fec->eth->iaddr2); | |
376 | writel(0, &fec->eth->gaddr1); | |
377 | writel(0, &fec->eth->gaddr2); | |
378 | ||
379 | /* | |
380 | * Set physical address | |
381 | */ | |
382 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], | |
383 | &fec->eth->paddr1); | |
384 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
13947f43 TK |
389 | static void fec_eth_phy_config(struct eth_device *dev) |
390 | { | |
391 | #ifdef CONFIG_PHYLIB | |
392 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
393 | struct phy_device *phydev; | |
394 | ||
395 | phydev = phy_connect(fec->bus, fec->phy_id, dev, | |
396 | PHY_INTERFACE_MODE_RGMII); | |
397 | if (phydev) { | |
398 | fec->phydev = phydev; | |
399 | phy_config(phydev); | |
400 | } | |
401 | #endif | |
402 | } | |
403 | ||
a5990b26 MV |
404 | /* |
405 | * Do initial configuration of the FEC registers | |
406 | */ | |
407 | static void fec_reg_setup(struct fec_priv *fec) | |
408 | { | |
409 | uint32_t rcntrl; | |
410 | ||
411 | /* | |
412 | * Set interrupt mask register | |
413 | */ | |
414 | writel(0x00000000, &fec->eth->imask); | |
415 | ||
416 | /* | |
417 | * Clear FEC-Lite interrupt event register(IEVENT) | |
418 | */ | |
419 | writel(0xffffffff, &fec->eth->ievent); | |
420 | ||
421 | ||
422 | /* | |
423 | * Set FEC-Lite receive control register(R_CNTRL): | |
424 | */ | |
425 | ||
426 | /* Start with frame length = 1518, common for all modes. */ | |
427 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
9d2d924a | 428 | if (fec->xcv_type != SEVENWIRE) /* xMII modes */ |
429 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
430 | if (fec->xcv_type == RGMII) | |
a5990b26 MV |
431 | rcntrl |= FEC_RCNTRL_RGMII; |
432 | else if (fec->xcv_type == RMII) | |
433 | rcntrl |= FEC_RCNTRL_RMII; | |
a5990b26 MV |
434 | |
435 | writel(rcntrl, &fec->eth->r_cntrl); | |
436 | } | |
437 | ||
0b23fb36 IY |
438 | /** |
439 | * Start the FEC engine | |
440 | * @param[in] dev Our device to handle | |
441 | */ | |
442 | static int fec_open(struct eth_device *edev) | |
443 | { | |
444 | struct fec_priv *fec = (struct fec_priv *)edev->priv; | |
28774cba | 445 | int speed; |
5c1ad3e6 EN |
446 | uint32_t addr, size; |
447 | int i; | |
0b23fb36 IY |
448 | |
449 | debug("fec_open: fec_open(dev)\n"); | |
450 | /* full-duplex, heartbeat disabled */ | |
451 | writel(1 << 2, &fec->eth->x_cntrl); | |
452 | fec->rbd_index = 0; | |
453 | ||
5c1ad3e6 EN |
454 | /* Invalidate all descriptors */ |
455 | for (i = 0; i < FEC_RBD_NUM - 1; i++) | |
456 | fec_rbd_clean(0, &fec->rbd_base[i]); | |
457 | fec_rbd_clean(1, &fec->rbd_base[i]); | |
458 | ||
459 | /* Flush the descriptors into RAM */ | |
460 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
461 | ARCH_DMA_MINALIGN); | |
462 | addr = (uint32_t)fec->rbd_base; | |
463 | flush_dcache_range(addr, addr + size); | |
464 | ||
28774cba | 465 | #ifdef FEC_QUIRK_ENET_MAC |
2ef2b950 JL |
466 | /* Enable ENET HW endian SWAP */ |
467 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
468 | &fec->eth->ecntrl); | |
469 | /* Enable ENET store and forward mode */ | |
470 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
471 | &fec->eth->x_wmrk); | |
472 | #endif | |
0b23fb36 IY |
473 | /* |
474 | * Enable FEC-Lite controller | |
475 | */ | |
cb17b92d JR |
476 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
477 | &fec->eth->ecntrl); | |
96912453 | 478 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) |
740d6ae5 JR |
479 | udelay(100); |
480 | /* | |
481 | * setup the MII gasket for RMII mode | |
482 | */ | |
483 | ||
484 | /* disable the gasket */ | |
485 | writew(0, &fec->eth->miigsk_enr); | |
486 | ||
487 | /* wait for the gasket to be disabled */ | |
488 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
489 | udelay(2); | |
490 | ||
491 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
492 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
493 | ||
494 | /* re-enable the gasket */ | |
495 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
496 | ||
497 | /* wait until MII gasket is ready */ | |
498 | int max_loops = 10; | |
499 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
500 | if (--max_loops <= 0) { | |
501 | printf("WAIT for MII Gasket ready timed out\n"); | |
502 | break; | |
503 | } | |
504 | } | |
505 | #endif | |
0b23fb36 | 506 | |
13947f43 TK |
507 | #ifdef CONFIG_PHYLIB |
508 | if (!fec->phydev) | |
509 | fec_eth_phy_config(edev); | |
510 | if (fec->phydev) { | |
511 | /* Start up the PHY */ | |
11af8d65 TT |
512 | int ret = phy_startup(fec->phydev); |
513 | ||
514 | if (ret) { | |
515 | printf("Could not initialize PHY %s\n", | |
516 | fec->phydev->dev->name); | |
517 | return ret; | |
518 | } | |
13947f43 TK |
519 | speed = fec->phydev->speed; |
520 | } else { | |
521 | speed = _100BASET; | |
522 | } | |
523 | #else | |
0b23fb36 | 524 | miiphy_wait_aneg(edev); |
28774cba | 525 | speed = miiphy_speed(edev->name, fec->phy_id); |
9e27e9dc | 526 | miiphy_duplex(edev->name, fec->phy_id); |
13947f43 | 527 | #endif |
0b23fb36 | 528 | |
28774cba TK |
529 | #ifdef FEC_QUIRK_ENET_MAC |
530 | { | |
531 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; | |
532 | u32 rcr = (readl(&fec->eth->r_cntrl) & | |
533 | ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | | |
534 | FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; | |
535 | if (speed == _1000BASET) | |
536 | ecr |= FEC_ECNTRL_SPEED; | |
537 | else if (speed != _100BASET) | |
538 | rcr |= FEC_RCNTRL_RMII_10T; | |
539 | writel(ecr, &fec->eth->ecntrl); | |
540 | writel(rcr, &fec->eth->r_cntrl); | |
541 | } | |
542 | #endif | |
543 | debug("%s:Speed=%i\n", __func__, speed); | |
544 | ||
0b23fb36 IY |
545 | /* |
546 | * Enable SmartDMA receive task | |
547 | */ | |
548 | fec_rx_task_enable(fec); | |
549 | ||
550 | udelay(100000); | |
551 | return 0; | |
552 | } | |
553 | ||
554 | static int fec_init(struct eth_device *dev, bd_t* bd) | |
555 | { | |
0b23fb36 | 556 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
9e27e9dc | 557 | uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; |
5c1ad3e6 EN |
558 | uint32_t size; |
559 | int i, ret; | |
0b23fb36 | 560 | |
e9319f11 JR |
561 | /* Initialize MAC address */ |
562 | fec_set_hwaddr(dev); | |
563 | ||
0b23fb36 | 564 | /* |
5c1ad3e6 EN |
565 | * Allocate transmit descriptors, there are two in total. This |
566 | * allocation respects cache alignment. | |
0b23fb36 | 567 | */ |
5c1ad3e6 EN |
568 | if (!fec->tbd_base) { |
569 | size = roundup(2 * sizeof(struct fec_bd), | |
570 | ARCH_DMA_MINALIGN); | |
571 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
572 | if (!fec->tbd_base) { | |
573 | ret = -ENOMEM; | |
574 | goto err1; | |
575 | } | |
576 | memset(fec->tbd_base, 0, size); | |
577 | fec_tbd_init(fec); | |
578 | flush_dcache_range((unsigned)fec->tbd_base, size); | |
0b23fb36 | 579 | } |
0b23fb36 | 580 | |
5c1ad3e6 EN |
581 | /* |
582 | * Allocate receive descriptors. This allocation respects cache | |
583 | * alignment. | |
584 | */ | |
585 | if (!fec->rbd_base) { | |
586 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
587 | ARCH_DMA_MINALIGN); | |
588 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
589 | if (!fec->rbd_base) { | |
590 | ret = -ENOMEM; | |
591 | goto err2; | |
592 | } | |
593 | memset(fec->rbd_base, 0, size); | |
594 | /* | |
595 | * Initialize RxBD ring | |
596 | */ | |
597 | if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { | |
598 | ret = -ENOMEM; | |
599 | goto err3; | |
600 | } | |
601 | flush_dcache_range((unsigned)fec->rbd_base, | |
602 | (unsigned)fec->rbd_base + size); | |
603 | } | |
0b23fb36 | 604 | |
a5990b26 | 605 | fec_reg_setup(fec); |
9eb3770b | 606 | |
f41471e6 | 607 | if (fec->xcv_type != SEVENWIRE) |
4294b248 | 608 | fec_mii_setspeed(fec); |
9eb3770b | 609 | |
0b23fb36 IY |
610 | /* |
611 | * Set Opcode/Pause Duration Register | |
612 | */ | |
613 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ | |
614 | writel(0x2, &fec->eth->x_wmrk); | |
615 | /* | |
616 | * Set multicast address filter | |
617 | */ | |
618 | writel(0x00000000, &fec->eth->gaddr1); | |
619 | writel(0x00000000, &fec->eth->gaddr2); | |
620 | ||
621 | ||
622 | /* clear MIB RAM */ | |
9e27e9dc MV |
623 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) |
624 | writel(0, i); | |
0b23fb36 IY |
625 | |
626 | /* FIFO receive start register */ | |
627 | writel(0x520, &fec->eth->r_fstart); | |
628 | ||
629 | /* size and address of each buffer */ | |
630 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
631 | writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); | |
632 | writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); | |
633 | ||
13947f43 | 634 | #ifndef CONFIG_PHYLIB |
0b23fb36 IY |
635 | if (fec->xcv_type != SEVENWIRE) |
636 | miiphy_restart_aneg(dev); | |
13947f43 | 637 | #endif |
0b23fb36 IY |
638 | fec_open(dev); |
639 | return 0; | |
5c1ad3e6 EN |
640 | |
641 | err3: | |
642 | free(fec->rbd_base); | |
643 | err2: | |
644 | free(fec->tbd_base); | |
645 | err1: | |
646 | return ret; | |
0b23fb36 IY |
647 | } |
648 | ||
649 | /** | |
650 | * Halt the FEC engine | |
651 | * @param[in] dev Our device to handle | |
652 | */ | |
653 | static void fec_halt(struct eth_device *dev) | |
654 | { | |
9e27e9dc | 655 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
0b23fb36 IY |
656 | int counter = 0xffff; |
657 | ||
658 | /* | |
659 | * issue graceful stop command to the FEC transmitter if necessary | |
660 | */ | |
cb17b92d | 661 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
0b23fb36 IY |
662 | &fec->eth->x_cntrl); |
663 | ||
664 | debug("eth_halt: wait for stop regs\n"); | |
665 | /* | |
666 | * wait for graceful stop to register | |
667 | */ | |
668 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) | |
cb17b92d | 669 | udelay(1); |
0b23fb36 IY |
670 | |
671 | /* | |
672 | * Disable SmartDMA tasks | |
673 | */ | |
674 | fec_tx_task_disable(fec); | |
675 | fec_rx_task_disable(fec); | |
676 | ||
677 | /* | |
678 | * Disable the Ethernet Controller | |
679 | * Note: this will also reset the BD index counter! | |
680 | */ | |
740d6ae5 JR |
681 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
682 | &fec->eth->ecntrl); | |
0b23fb36 IY |
683 | fec->rbd_index = 0; |
684 | fec->tbd_index = 0; | |
0b23fb36 IY |
685 | debug("eth_halt: done\n"); |
686 | } | |
687 | ||
688 | /** | |
689 | * Transmit one frame | |
690 | * @param[in] dev Our ethernet device to handle | |
691 | * @param[in] packet Pointer to the data to be transmitted | |
692 | * @param[in] length Data count in bytes | |
693 | * @return 0 on success | |
694 | */ | |
442dac4c | 695 | static int fec_send(struct eth_device *dev, void *packet, int length) |
0b23fb36 IY |
696 | { |
697 | unsigned int status; | |
5c1ad3e6 EN |
698 | uint32_t size; |
699 | uint32_t addr; | |
0b23fb36 IY |
700 | |
701 | /* | |
702 | * This routine transmits one frame. This routine only accepts | |
703 | * 6-byte Ethernet addresses. | |
704 | */ | |
705 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
706 | ||
707 | /* | |
708 | * Check for valid length of data. | |
709 | */ | |
710 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 711 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
712 | return -1; |
713 | } | |
714 | ||
715 | /* | |
5c1ad3e6 EN |
716 | * Setup the transmit buffer. We are always using the first buffer for |
717 | * transmission, the second will be empty and only used to stop the DMA | |
718 | * engine. We also flush the packet to RAM here to avoid cache trouble. | |
0b23fb36 | 719 | */ |
5c1ad3e6 | 720 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
721 | swap_packet((uint32_t *)packet, length); |
722 | #endif | |
5c1ad3e6 EN |
723 | |
724 | addr = (uint32_t)packet; | |
725 | size = roundup(length, ARCH_DMA_MINALIGN); | |
726 | flush_dcache_range(addr, addr + size); | |
727 | ||
0b23fb36 | 728 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
5c1ad3e6 EN |
729 | writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
730 | ||
0b23fb36 IY |
731 | /* |
732 | * update BD's status now | |
733 | * This block: | |
734 | * - is always the last in a chain (means no chain) | |
735 | * - should transmitt the CRC | |
736 | * - might be the last BD in the list, so the address counter should | |
737 | * wrap (-> keep the WRAP flag) | |
738 | */ | |
739 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
740 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
741 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
742 | ||
5c1ad3e6 EN |
743 | /* |
744 | * Flush data cache. This code flushes both TX descriptors to RAM. | |
745 | * After this code, the descriptors will be safely in RAM and we | |
746 | * can start DMA. | |
747 | */ | |
748 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
749 | addr = (uint32_t)fec->tbd_base; | |
750 | flush_dcache_range(addr, addr + size); | |
751 | ||
0b23fb36 IY |
752 | /* |
753 | * Enable SmartDMA transmit task | |
754 | */ | |
755 | fec_tx_task_enable(fec); | |
756 | ||
757 | /* | |
5c1ad3e6 EN |
758 | * Wait until frame is sent. On each turn of the wait cycle, we must |
759 | * invalidate data cache to see what's really in RAM. Also, we need | |
760 | * barrier here. | |
0b23fb36 | 761 | */ |
5c1ad3e6 | 762 | invalidate_dcache_range(addr, addr + size); |
0b23fb36 | 763 | while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { |
cb17b92d | 764 | udelay(1); |
5c1ad3e6 | 765 | invalidate_dcache_range(addr, addr + size); |
0b23fb36 | 766 | } |
5c1ad3e6 | 767 | |
0b23fb36 IY |
768 | debug("fec_send: status 0x%x index %d\n", |
769 | readw(&fec->tbd_base[fec->tbd_index].status), | |
770 | fec->tbd_index); | |
771 | /* for next transmission use the other buffer */ | |
772 | if (fec->tbd_index) | |
773 | fec->tbd_index = 0; | |
774 | else | |
775 | fec->tbd_index = 1; | |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
780 | /** | |
781 | * Pull one frame from the card | |
782 | * @param[in] dev Our ethernet device to handle | |
783 | * @return Length of packet read | |
784 | */ | |
785 | static int fec_recv(struct eth_device *dev) | |
786 | { | |
787 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
788 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; | |
789 | unsigned long ievent; | |
790 | int frame_length, len = 0; | |
791 | struct nbuf *frame; | |
792 | uint16_t bd_status; | |
5c1ad3e6 EN |
793 | uint32_t addr, size; |
794 | int i; | |
e2a66e60 | 795 | uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN); |
0b23fb36 IY |
796 | |
797 | /* | |
798 | * Check if any critical events have happened | |
799 | */ | |
800 | ievent = readl(&fec->eth->ievent); | |
801 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 802 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 IY |
803 | if (ievent & FEC_IEVENT_BABR) { |
804 | fec_halt(dev); | |
805 | fec_init(dev, fec->bd); | |
806 | printf("some error: 0x%08lx\n", ievent); | |
807 | return 0; | |
808 | } | |
809 | if (ievent & FEC_IEVENT_HBERR) { | |
810 | /* Heartbeat error */ | |
811 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
812 | &fec->eth->x_cntrl); | |
813 | } | |
814 | if (ievent & FEC_IEVENT_GRA) { | |
815 | /* Graceful stop complete */ | |
816 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
817 | fec_halt(dev); | |
818 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), | |
819 | &fec->eth->x_cntrl); | |
820 | fec_init(dev, fec->bd); | |
821 | } | |
822 | } | |
823 | ||
824 | /* | |
5c1ad3e6 EN |
825 | * Read the buffer status. Before the status can be read, the data cache |
826 | * must be invalidated, because the data in RAM might have been changed | |
827 | * by DMA. The descriptors are properly aligned to cachelines so there's | |
828 | * no need to worry they'd overlap. | |
829 | * | |
830 | * WARNING: By invalidating the descriptor here, we also invalidate | |
831 | * the descriptors surrounding this one. Therefore we can NOT change the | |
832 | * contents of this descriptor nor the surrounding ones. The problem is | |
833 | * that in order to mark the descriptor as processed, we need to change | |
834 | * the descriptor. The solution is to mark the whole cache line when all | |
835 | * descriptors in the cache line are processed. | |
0b23fb36 | 836 | */ |
5c1ad3e6 EN |
837 | addr = (uint32_t)rbd; |
838 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
839 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
840 | invalidate_dcache_range(addr, addr + size); | |
841 | ||
0b23fb36 IY |
842 | bd_status = readw(&rbd->status); |
843 | debug("fec_recv: status 0x%x\n", bd_status); | |
844 | ||
845 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
846 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
847 | ((readw(&rbd->data_length) - 4) > 14)) { | |
848 | /* | |
849 | * Get buffer address and size | |
850 | */ | |
851 | frame = (struct nbuf *)readl(&rbd->data_pointer); | |
852 | frame_length = readw(&rbd->data_length) - 4; | |
5c1ad3e6 EN |
853 | /* |
854 | * Invalidate data cache over the buffer | |
855 | */ | |
856 | addr = (uint32_t)frame; | |
857 | size = roundup(frame_length, ARCH_DMA_MINALIGN); | |
858 | invalidate_dcache_range(addr, addr + size); | |
859 | ||
0b23fb36 IY |
860 | /* |
861 | * Fill the buffer and pass it to upper layers | |
862 | */ | |
5c1ad3e6 | 863 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
864 | swap_packet((uint32_t *)frame->data, frame_length); |
865 | #endif | |
0b23fb36 IY |
866 | memcpy(buff, frame->data, frame_length); |
867 | NetReceive(buff, frame_length); | |
868 | len = frame_length; | |
869 | } else { | |
870 | if (bd_status & FEC_RBD_ERR) | |
871 | printf("error frame: 0x%08lx 0x%08x\n", | |
872 | (ulong)rbd->data_pointer, | |
873 | bd_status); | |
874 | } | |
5c1ad3e6 | 875 | |
0b23fb36 | 876 | /* |
5c1ad3e6 EN |
877 | * Free the current buffer, restart the engine and move forward |
878 | * to the next buffer. Here we check if the whole cacheline of | |
879 | * descriptors was already processed and if so, we mark it free | |
880 | * as whole. | |
0b23fb36 | 881 | */ |
5c1ad3e6 EN |
882 | size = RXDESC_PER_CACHELINE - 1; |
883 | if ((fec->rbd_index & size) == size) { | |
884 | i = fec->rbd_index - size; | |
885 | addr = (uint32_t)&fec->rbd_base[i]; | |
886 | for (; i <= fec->rbd_index ; i++) { | |
887 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), | |
888 | &fec->rbd_base[i]); | |
889 | } | |
890 | flush_dcache_range(addr, | |
891 | addr + ARCH_DMA_MINALIGN); | |
892 | } | |
893 | ||
0b23fb36 IY |
894 | fec_rx_task_enable(fec); |
895 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
896 | } | |
897 | debug("fec_recv: stop\n"); | |
898 | ||
899 | return len; | |
900 | } | |
901 | ||
9e27e9dc | 902 | static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) |
0b23fb36 | 903 | { |
0b23fb36 | 904 | struct eth_device *edev; |
9e27e9dc | 905 | struct fec_priv *fec; |
13947f43 | 906 | struct mii_dev *bus; |
0b23fb36 | 907 | unsigned char ethaddr[6]; |
e382fb48 MV |
908 | uint32_t start; |
909 | int ret = 0; | |
0b23fb36 IY |
910 | |
911 | /* create and fill edev struct */ | |
912 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
913 | if (!edev) { | |
9e27e9dc | 914 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
e382fb48 MV |
915 | ret = -ENOMEM; |
916 | goto err1; | |
9e27e9dc MV |
917 | } |
918 | ||
919 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); | |
920 | if (!fec) { | |
921 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); | |
e382fb48 MV |
922 | ret = -ENOMEM; |
923 | goto err2; | |
0b23fb36 | 924 | } |
9e27e9dc | 925 | |
de0b9576 | 926 | memset(edev, 0, sizeof(*edev)); |
9e27e9dc MV |
927 | memset(fec, 0, sizeof(*fec)); |
928 | ||
0b23fb36 IY |
929 | edev->priv = fec; |
930 | edev->init = fec_init; | |
931 | edev->send = fec_send; | |
932 | edev->recv = fec_recv; | |
933 | edev->halt = fec_halt; | |
fb57ec97 | 934 | edev->write_hwaddr = fec_set_hwaddr; |
0b23fb36 | 935 | |
9e27e9dc | 936 | fec->eth = (struct ethernet_regs *)base_addr; |
0b23fb36 IY |
937 | fec->bd = bd; |
938 | ||
392b8502 | 939 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
0b23fb36 IY |
940 | |
941 | /* Reset chip. */ | |
cb17b92d | 942 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
e382fb48 MV |
943 | start = get_timer(0); |
944 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
945 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
946 | printf("FEC MXC: Timeout reseting chip\n"); | |
947 | goto err3; | |
948 | } | |
0b23fb36 | 949 | udelay(10); |
e382fb48 | 950 | } |
0b23fb36 | 951 | |
a5990b26 | 952 | fec_reg_setup(fec); |
4294b248 | 953 | fec_mii_setspeed(fec); |
0b23fb36 | 954 | |
9e27e9dc MV |
955 | if (dev_id == -1) { |
956 | sprintf(edev->name, "FEC"); | |
957 | fec->dev_id = 0; | |
958 | } else { | |
959 | sprintf(edev->name, "FEC%i", dev_id); | |
960 | fec->dev_id = dev_id; | |
961 | } | |
962 | fec->phy_id = phy_id; | |
0b23fb36 | 963 | |
13947f43 TK |
964 | bus = mdio_alloc(); |
965 | if (!bus) { | |
966 | printf("mdio_alloc failed\n"); | |
967 | ret = -ENOMEM; | |
968 | goto err3; | |
969 | } | |
970 | bus->read = fec_phy_read; | |
971 | bus->write = fec_phy_write; | |
972 | sprintf(bus->name, edev->name); | |
5c1ad3e6 | 973 | #ifdef CONFIG_MX28 |
13947f43 TK |
974 | /* |
975 | * The i.MX28 has two ethernet interfaces, but they are not equal. | |
976 | * Only the first one can access the MDIO bus. | |
977 | */ | |
978 | bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE; | |
979 | #else | |
980 | bus->priv = fec->eth; | |
981 | #endif | |
982 | ret = mdio_register(bus); | |
983 | if (ret) { | |
984 | printf("mdio_register failed\n"); | |
985 | free(bus); | |
986 | ret = -ENOMEM; | |
987 | goto err3; | |
988 | } | |
989 | fec->bus = bus; | |
0b23fb36 IY |
990 | eth_register(edev); |
991 | ||
be252b65 FE |
992 | if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { |
993 | debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); | |
4294b248 | 994 | memcpy(edev->enetaddr, ethaddr, 6); |
0b23fb36 | 995 | } |
13947f43 TK |
996 | /* Configure phy */ |
997 | fec_eth_phy_config(edev); | |
e382fb48 MV |
998 | return ret; |
999 | ||
1000 | err3: | |
1001 | free(fec); | |
1002 | err2: | |
1003 | free(edev); | |
1004 | err1: | |
1005 | return ret; | |
0b23fb36 IY |
1006 | } |
1007 | ||
5c1ad3e6 | 1008 | #ifndef CONFIG_FEC_MXC_MULTI |
0b23fb36 IY |
1009 | int fecmxc_initialize(bd_t *bd) |
1010 | { | |
1011 | int lout = 1; | |
1012 | ||
1013 | debug("eth_init: fec_probe(bd)\n"); | |
9e27e9dc MV |
1014 | lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); |
1015 | ||
1016 | return lout; | |
1017 | } | |
1018 | #endif | |
1019 | ||
1020 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) | |
1021 | { | |
1022 | int lout = 1; | |
1023 | ||
1024 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); | |
1025 | lout = fec_probe(bd, dev_id, phy_id, addr); | |
0b23fb36 IY |
1026 | |
1027 | return lout; | |
1028 | } | |
2e5f4421 | 1029 | |
13947f43 | 1030 | #ifndef CONFIG_PHYLIB |
2e5f4421 MV |
1031 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) |
1032 | { | |
1033 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
1034 | fec->mii_postcall = cb; | |
1035 | return 0; | |
1036 | } | |
13947f43 | 1037 | #endif |