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1cb8e980 | 1 | /* |
531716e1 | 2 | * (C) Copyright 2002, 2003 |
1cb8e980 WD |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
792a09eb | 5 | * Gary Jennejohn <garyj@denx.de> |
1cb8e980 WD |
6 | * David Mueller <d.mueller@elsoft.ch> |
7 | * | |
8 | * Configuation settings for the MPL VCMA9 board. | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
c686537f DMEA |
32 | |
33 | #define MACH_TYPE_MPL_VCMA9 227 | |
34 | ||
1cb8e980 WD |
35 | /* |
36 | * High Level Configuration Options | |
37 | * (easy to change) | |
38 | */ | |
f3108304 DMEA |
39 | #define CONFIG_ARM920T /* This is an ARM920T Core */ |
40 | #define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ | |
41 | #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ | |
42 | #define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ | |
c686537f | 43 | #define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */ |
1cb8e980 | 44 | |
0bf42fec DMEA |
45 | #define CONFIG_SYS_TEXT_BASE 0x0 |
46 | ||
f3108304 | 47 | #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH |
1cb8e980 | 48 | |
f3108304 DMEA |
49 | /* input clock of PLL (VCMA9 has 12MHz input clock) */ |
50 | #define CONFIG_SYS_CLK_FREQ 12000000 | |
1cb8e980 | 51 | |
f3108304 | 52 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
1cb8e980 | 53 | |
f3108304 DMEA |
54 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
55 | #define CONFIG_SETUP_MEMORY_TAGS | |
56 | #define CONFIG_INITRD_TAG | |
a5562901 | 57 | |
a1aa0bb5 JL |
58 | /* |
59 | * BOOTP options | |
60 | */ | |
61 | #define CONFIG_BOOTP_BOOTFILESIZE | |
62 | #define CONFIG_BOOTP_BOOTPATH | |
63 | #define CONFIG_BOOTP_GATEWAY | |
64 | #define CONFIG_BOOTP_HOSTNAME | |
65 | ||
a5562901 JL |
66 | /* |
67 | * Command line configuration. | |
68 | */ | |
69 | #include <config_cmd_default.h> | |
70 | ||
71 | #define CONFIG_CMD_CACHE | |
72 | #define CONFIG_CMD_EEPROM | |
73 | #define CONFIG_CMD_I2C | |
74 | #define CONFIG_CMD_USB | |
75 | #define CONFIG_CMD_REGINFO | |
a5562901 JL |
76 | #define CONFIG_CMD_DATE |
77 | #define CONFIG_CMD_ELF | |
78 | #define CONFIG_CMD_DHCP | |
79 | #define CONFIG_CMD_PING | |
80 | #define CONFIG_CMD_BSP | |
f3108304 | 81 | #define CONFIG_CMD_NAND |
a5562901 | 82 | |
9660e442 | 83 | #define CONFIG_BOARD_LATE_INIT |
1cb8e980 | 84 | |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_HUSH_PARSER |
86 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
f3108304 DMEA |
87 | #define CONFIG_CMDLINE_EDITING |
88 | ||
89 | /* | |
1cb8e980 WD |
90 | * I2C stuff: |
91 | * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at | |
92 | * address 0x50 with 16bit addressing | |
f3108304 DMEA |
93 | */ |
94 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ |
96 | #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */ | |
1cb8e980 | 97 | |
f3108304 DMEA |
98 | /* we use the built-in I2C controller */ |
99 | #define CONFIG_DRIVER_S3C24X0_I2C | |
100 | ||
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
102 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
f3108304 DMEA |
103 | /* use EEPROM for environment vars */ |
104 | #define CONFIG_ENV_IS_IN_EEPROM 1 | |
105 | /* environment starts at offset 0 */ | |
106 | #define CONFIG_ENV_OFFSET 0x000 | |
107 | /* 2KB should be more than enough */ | |
108 | #define CONFIG_ENV_SIZE 0x800 | |
1cb8e980 | 109 | |
6d0f6bcf | 110 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
f3108304 DMEA |
111 | /* 64 bytes page write mode on 24C256 */ |
112 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
6d0f6bcf | 113 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
1cb8e980 | 114 | |
1cb8e980 WD |
115 | /* |
116 | * Hardware drivers | |
117 | */ | |
f3108304 DMEA |
118 | #define CONFIG_CS8900 /* we have a CS8900 on-board */ |
119 | #define CONFIG_CS8900_BASE 0x20000300 | |
120 | #define CONFIG_CS8900_BUS16 | |
1cb8e980 WD |
121 | |
122 | /* | |
123 | * select serial console configuration | |
124 | */ | |
300f99f4 | 125 | #define CONFIG_S3C24X0_SERIAL |
f3108304 | 126 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ |
1cb8e980 | 127 | |
f3108304 DMEA |
128 | /* USB support (currently only works with D-cache off) */ |
129 | #define CONFIG_USB_OHCI | |
130 | #define CONFIG_USB_KEYBOARD | |
131 | #define CONFIG_USB_STORAGE | |
132 | #define CONFIG_DOS_PARTITION | |
48b42616 WD |
133 | |
134 | /* Enable needed helper functions */ | |
f3108304 | 135 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
48b42616 | 136 | |
f3108304 DMEA |
137 | /* RTC */ |
138 | #define CONFIG_RTC_S3C24X0 | |
48b42616 WD |
139 | |
140 | ||
1cb8e980 WD |
141 | /* allow to overwrite serial and ethaddr */ |
142 | #define CONFIG_ENV_OVERWRITE | |
143 | ||
f3108304 | 144 | #define CONFIG_BAUDRATE 9600 |
1cb8e980 | 145 | |
f3108304 DMEA |
146 | #define CONFIG_BOOTDELAY 5 |
147 | #define CONFIG_BOOT_RETRY_TIME -1 | |
148 | #define CONFIG_RESET_TO_RETRY | |
149 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
a2663ea4 | 150 | |
f3108304 DMEA |
151 | #define CONFIG_NETMASK 255.255.255.0 |
152 | #define CONFIG_IPADDR 10.0.0.110 | |
153 | #define CONFIG_SERVERIP 10.0.0.1 | |
1cb8e980 | 154 | |
a5562901 | 155 | #if defined(CONFIG_CMD_KGDB) |
f3108304 DMEA |
156 | /* speed to run kgdb serial port */ |
157 | #define CONFIG_KGDB_BAUDRATE 115200 | |
1cb8e980 | 158 | /* what's this ? it's not used anywhere */ |
f3108304 | 159 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
1cb8e980 WD |
160 | #endif |
161 | ||
f3108304 DMEA |
162 | /* Miscellaneous configurable options */ |
163 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
164 | #define CONFIG_SYS_PROMPT "VCMA9 # " | |
165 | #define CONFIG_SYS_CBSIZE 256 | |
166 | /* Print Buffer Size */ | |
167 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
168 | #define CONFIG_SYS_MAXARGS 16 | |
169 | /* Boot Argument Buffer Size */ | |
170 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
171 | ||
172 | /* to be activated as soon as s3c24x0 has print_cpuinfo support */ | |
173 | /*#define CONFIG_DISPLAY_CPUINFO*/ /* Display cpu info */ | |
174 | #define CONFIG_DISPLAY_BOARDINFO /* Display board info */ | |
1cb8e980 | 175 | |
f3108304 DMEA |
176 | #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ |
177 | #define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */ | |
531716e1 | 178 | |
6d0f6bcf | 179 | #define CONFIG_SYS_ALT_MEMTEST |
f3108304 | 180 | #define CONFIG_SYS_LOAD_ADDR 0x30800000 |
1cb8e980 | 181 | |
f3108304 DMEA |
182 | /* we configure PWM Timer 4 to 1ms 1000Hz */ |
183 | #define CONFIG_SYS_HZ 1000 | |
1cb8e980 WD |
184 | |
185 | /* valid baudrates */ | |
6d0f6bcf | 186 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
1cb8e980 | 187 | |
f3108304 DMEA |
188 | /* support additional compression methods */ |
189 | #define CONFIG_BZIP2 | |
190 | #define CONFIG_LZO | |
191 | #define CONFIG_LZMA | |
a2663ea4 | 192 | |
f3108304 | 193 | /* Ident */ |
48b42616 WD |
194 | /*#define VERSION_TAG "released"*/ |
195 | #define VERSION_TAG "unstable" | |
f3108304 DMEA |
196 | #define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \ |
197 | "MEV-10080-001 " VERSION_TAG | |
48b42616 | 198 | |
f3108304 | 199 | /* |
1cb8e980 | 200 | * Stack sizes |
1cb8e980 WD |
201 | * The stack sizes are set up in start.S using the settings below |
202 | */ | |
f3108304 | 203 | #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ |
1cb8e980 | 204 | #ifdef CONFIG_USE_IRQ |
f3108304 DMEA |
205 | #define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ |
206 | #define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ | |
1cb8e980 WD |
207 | #endif |
208 | ||
f3108304 DMEA |
209 | /* Physical Memory Map */ |
210 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
211 | #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ | |
212 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
1cb8e980 | 213 | |
6d754843 | 214 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
1cb8e980 | 215 | |
f3108304 | 216 | /* FLASH and environment organization */ |
1cb8e980 | 217 | |
6d754843 DMEA |
218 | #define CONFIG_SYS_FLASH_CFI |
219 | #define CONFIG_FLASH_CFI_DRIVER | |
220 | #define CONFIG_FLASH_CFI_LEGACY | |
221 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
222 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
6d0f6bcf | 223 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
f3108304 | 224 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
6d754843 | 225 | #define CONFIG_SYS_MAX_FLASH_SECT (19) |
1cb8e980 | 226 | |
f3108304 DMEA |
227 | /* |
228 | * Size of malloc() pool | |
229 | * BZIP2 / LZO / LZMA need a lot of RAM | |
230 | */ | |
231 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
232 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
233 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
1cb8e980 | 234 | |
f3108304 DMEA |
235 | /* NAND configuration */ |
236 | #ifdef CONFIG_CMD_NAND | |
237 | #define CONFIG_NAND_S3C2410 | |
238 | #define CONFIG_SYS_S3C2410_NAND_HWECC | |
239 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
f3108304 DMEA |
240 | #define CONFIG_SYS_NAND_BASE 0x4E000000 |
241 | #define CONFIG_S3C24XX_CUSTOM_NAND_TIMING | |
242 | #define CONFIG_S3C24XX_TACLS 1 | |
243 | #define CONFIG_S3C24XX_TWRPH0 5 | |
244 | #define CONFIG_S3C24XX_TWRPH1 3 | |
245 | #endif | |
48b42616 | 246 | |
f3108304 | 247 | #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 |
48b42616 | 248 | |
f3108304 DMEA |
249 | /* File system */ |
250 | #define CONFIG_CMD_FAT | |
251 | #define CONFIG_CMD_EXT2 | |
252 | #define CONFIG_CMD_UBI | |
253 | #define CONFIG_CMD_UBIFS | |
254 | #define CONFIG_CMD_JFFS2 | |
255 | #define CONFIG_YAFFS2 | |
256 | #define CONFIG_RBTREE | |
257 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
258 | #define CONFIG_MTD_PARTITIONS | |
259 | #define CONFIG_CMD_MTDPARTS | |
260 | #define CONFIG_LZO | |
48b42616 | 261 | |
d2d94571 DMEA |
262 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
263 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
264 | GENERATED_GBL_DATA_SIZE) | |
265 | ||
f3108304 | 266 | #define CONFIG_BOARD_EARLY_INIT_F |
d2d94571 | 267 | |
f3108304 | 268 | #endif /* __CONFIG_H */ |