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KVM: Documentation: remove VM mmap documentation
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
893590c7 137static bool __read_mostly backwards_tsc_observed = false;
16a96021 138
18863bdd
AK		 139#define KVM_NR_SHARED_MSRS 16
140
141struct kvm_shared_msrs_global {
142 int nr;
2bf78fa7 143 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 144};
145
146struct kvm_shared_msrs {
147 struct user_return_notifier urn;
148 bool registered;
2bf78fa7
SY		 149 struct kvm_shared_msr_values {
150 u64 host;
151 u64 curr;
152 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 153};
154
155static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 156static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 157
417bc304 158struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 159 { "pf_fixed", VCPU_STAT(pf_fixed) },
160 { "pf_guest", VCPU_STAT(pf_guest) },
161 { "tlb_flush", VCPU_STAT(tlb_flush) },
162 { "invlpg", VCPU_STAT(invlpg) },
163 { "exits", VCPU_STAT(exits) },
164 { "io_exits", VCPU_STAT(io_exits) },
165 { "mmio_exits", VCPU_STAT(mmio_exits) },
166 { "signal_exits", VCPU_STAT(signal_exits) },
167 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 168 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 169 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 170 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 171 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 172 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 173 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 174 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 175 { "request_irq", VCPU_STAT(request_irq_exits) },
176 { "irq_exits", VCPU_STAT(irq_exits) },
177 { "host_state_reload", VCPU_STAT(host_state_reload) },
178 { "efer_reload", VCPU_STAT(efer_reload) },
179 { "fpu_reload", VCPU_STAT(fpu_reload) },
180 { "insn_emulation", VCPU_STAT(insn_emulation) },
181 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 182 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 183 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 184 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 185 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
186 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
187 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
188 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
189 { "mmu_flooded", VM_STAT(mmu_flooded) },
190 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 191 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 192 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 193 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 194 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 195 { "max_mmu_page_hash_collisions",
196 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 197 { NULL }
198};
199
2acf923e
DC		 200u64 __read_mostly host_xcr0;
201
b6785def 202static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 203
af585b92
GN		 204static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
205{
206 int i;
207 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
208 vcpu->arch.apf.gfns[i] = ~0;
209}
210
18863bdd
AK		 211static void kvm_on_user_return(struct user_return_notifier *urn)
212{
213 unsigned slot;
18863bdd
AK		 214 struct kvm_shared_msrs *locals
215 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 216 struct kvm_shared_msr_values *values;
1650b4eb
IA		 217 unsigned long flags;
218
219 /*
220 * Disabling irqs at this point since the following code could be
221 * interrupted and executed through kvm_arch_hardware_disable()
222 */
223 local_irq_save(flags);
224 if (locals->registered) {
225 locals->registered = false;
226 user_return_notifier_unregister(urn);
227 }
228 local_irq_restore(flags);
18863bdd 229 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 230 values = &locals->values[slot];
231 if (values->host != values->curr) {
232 wrmsrl(shared_msrs_global.msrs[slot], values->host);
233 values->curr = values->host;
18863bdd
AK		 234 }
235 }
18863bdd
AK		 236}
237
2bf78fa7 238static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 239{
18863bdd 240 u64 value;
013f6a5d
MT		 241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 243
2bf78fa7
SY		 244 /* only read, and nobody should modify it at this time,
245 * so don't need lock */
246 if (slot >= shared_msrs_global.nr) {
247 printk(KERN_ERR "kvm: invalid MSR slot!");
248 return;
249 }
250 rdmsrl_safe(msr, &value);
251 smsr->values[slot].host = value;
252 smsr->values[slot].curr = value;
253}
254
255void kvm_define_shared_msr(unsigned slot, u32 msr)
256{
0123be42 257 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 258 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 259 if (slot >= shared_msrs_global.nr)
260 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 261}
262EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
263
264static void kvm_shared_msr_cpu_online(void)
265{
266 unsigned i;
18863bdd
AK		 267
268 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 269 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 270}
271
8b3c3104 272int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 273{
013f6a5d
MT		 274 unsigned int cpu = smp_processor_id();
275 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 276 int err;
18863bdd 277
2bf78fa7 278 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 279 return 0;
2bf78fa7 280 smsr->values[slot].curr = value;
8b3c3104
AH		 281 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
282 if (err)
283 return 1;
284
18863bdd
AK		 285 if (!smsr->registered) {
286 smsr->urn.on_user_return = kvm_on_user_return;
287 user_return_notifier_register(&smsr->urn);
288 smsr->registered = true;
289 }
8b3c3104 290 return 0;
18863bdd
AK		 291}
292EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
293
13a34e06 294static void drop_user_return_notifiers(void)
3548bab5 295{
013f6a5d
MT		 296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 298
299 if (smsr->registered)
300 kvm_on_user_return(&smsr->urn);
301}
302
6866b83e
CO		 303u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
304{
8a5a87d9 305 return vcpu->arch.apic_base;
6866b83e
CO		 306}
307EXPORT_SYMBOL_GPL(kvm_get_apic_base);
308
58cb628d
JK		 309int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
310{
311 u64 old_state = vcpu->arch.apic_base &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 new_state = msr_info->data &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
316 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
317
318 if (!msr_info->host_initiated &&
319 ((msr_info->data & reserved_bits) != 0 ||
320 new_state == X2APIC_ENABLE ||
321 (new_state == MSR_IA32_APICBASE_ENABLE &&
322 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
323 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
324 old_state == 0)))
325 return 1;
326
327 kvm_lapic_set_base(vcpu, msr_info->data);
328 return 0;
6866b83e
CO		 329}
330EXPORT_SYMBOL_GPL(kvm_set_apic_base);
331
2605fc21 332asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 333{
334 /* Fault while not rebooting. We want the trace. */
335 BUG();
336}
337EXPORT_SYMBOL_GPL(kvm_spurious_fault);
338
3fd28fce
ED		 339#define EXCPT_BENIGN 0
340#define EXCPT_CONTRIBUTORY 1
341#define EXCPT_PF 2
342
343static int exception_class(int vector)
344{
345 switch (vector) {
346 case PF_VECTOR:
347 return EXCPT_PF;
348 case DE_VECTOR:
349 case TS_VECTOR:
350 case NP_VECTOR:
351 case SS_VECTOR:
352 case GP_VECTOR:
353 return EXCPT_CONTRIBUTORY;
354 default:
355 break;
356 }
357 return EXCPT_BENIGN;
358}
359
d6e8c854
NA		 360#define EXCPT_FAULT 0
361#define EXCPT_TRAP 1
362#define EXCPT_ABORT 2
363#define EXCPT_INTERRUPT 3
364
365static int exception_type(int vector)
366{
367 unsigned int mask;
368
369 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
370 return EXCPT_INTERRUPT;
371
372 mask = 1 << vector;
373
374 /* #DB is trap, as instruction watchpoints are handled elsewhere */
375 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
376 return EXCPT_TRAP;
377
378 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
379 return EXCPT_ABORT;
380
381 /* Reserved exceptions will result in fault */
382 return EXCPT_FAULT;
383}
384
3fd28fce 385static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 386 unsigned nr, bool has_error, u32 error_code,
387 bool reinject)
3fd28fce
ED		 388{
389 u32 prev_nr;
390 int class1, class2;
391
3842d135
AK		 392 kvm_make_request(KVM_REQ_EVENT, vcpu);
393
3fd28fce
ED		 394 if (!vcpu->arch.exception.pending) {
395 queue:
3ffb2468
NA		 396 if (has_error && !is_protmode(vcpu))
397 has_error = false;
3fd28fce
ED		 398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = has_error;
400 vcpu->arch.exception.nr = nr;
401 vcpu->arch.exception.error_code = error_code;
3f0fd292 402 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 403 return;
404 }
405
406 /* to check exception */
407 prev_nr = vcpu->arch.exception.nr;
408 if (prev_nr == DF_VECTOR) {
409 /* triple fault -> shutdown */
a8eeb04a 410 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 411 return;
412 }
413 class1 = exception_class(prev_nr);
414 class2 = exception_class(nr);
415 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
416 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
417 /* generate double fault per SDM Table 5-5 */
418 vcpu->arch.exception.pending = true;
419 vcpu->arch.exception.has_error_code = true;
420 vcpu->arch.exception.nr = DF_VECTOR;
421 vcpu->arch.exception.error_code = 0;
422 } else
423 /* replace previous exception with a new one in a hope
424 that instruction re-execution will regenerate lost
425 exception */
426 goto queue;
427}
428
298101da
AK		 429void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
430{
ce7ddec4 431 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 432}
433EXPORT_SYMBOL_GPL(kvm_queue_exception);
434
ce7ddec4
JR		 435void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
436{
437 kvm_multiple_exception(vcpu, nr, false, 0, true);
438}
439EXPORT_SYMBOL_GPL(kvm_requeue_exception);
440
6affcbed 441int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 442{
db8fcefa
AP		 443 if (err)
444 kvm_inject_gp(vcpu, 0);
445 else
6affcbed
KH		 446 return kvm_skip_emulated_instruction(vcpu);
447
448 return 1;
db8fcefa
AP		 449}
450EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 451
6389ee94 452void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 453{
454 ++vcpu->stat.pf_guest;
6389ee94
AK		 455 vcpu->arch.cr2 = fault->address;
456 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 457}
27d6c865 458EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 459
ef54bcfe 460static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 461{
6389ee94
AK		 462 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
463 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 464 else
6389ee94 465 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 466
467 return fault->nested_page_fault;
d4f8cf66
JR		 468}
469
3419ffc8
SY		 470void kvm_inject_nmi(struct kvm_vcpu *vcpu)
471{
7460fb4a
AK		 472 atomic_inc(&vcpu->arch.nmi_queued);
473 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 474}
475EXPORT_SYMBOL_GPL(kvm_inject_nmi);
476
298101da
AK		 477void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
478{
ce7ddec4 479 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 480}
481EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
482
ce7ddec4
JR		 483void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
484{
485 kvm_multiple_exception(vcpu, nr, true, error_code, true);
486}
487EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
488
0a79b009
AK		 489/*
490 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
491 * a #GP and return false.
492 */
493bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 494{
0a79b009
AK		 495 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
496 return true;
497 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
498 return false;
298101da 499}
0a79b009 500EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 501
16f8a6f9
NA		 502bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
503{
504 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
505 return true;
506
507 kvm_queue_exception(vcpu, UD_VECTOR);
508 return false;
509}
510EXPORT_SYMBOL_GPL(kvm_require_dr);
511
ec92fe44
JR		 512/*
513 * This function will be used to read from the physical memory of the currently
54bf36aa 514 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 515 * can read from guest physical or from the guest's guest physical memory.
516 */
517int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
518 gfn_t ngfn, void *data, int offset, int len,
519 u32 access)
520{
54987b7a 521 struct x86_exception exception;
ec92fe44
JR		 522 gfn_t real_gfn;
523 gpa_t ngpa;
524
525 ngpa = gfn_to_gpa(ngfn);
54987b7a 526 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 527 if (real_gfn == UNMAPPED_GVA)
528 return -EFAULT;
529
530 real_gfn = gpa_to_gfn(real_gfn);
531
54bf36aa 532 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 533}
534EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
535
69b0049a 536static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 537 void *data, int offset, int len, u32 access)
538{
539 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
540 data, offset, len, access);
541}
542
a03490ed
CO		 543/*
544 * Load the pae pdptrs. Return true is they are all valid.
545 */
ff03a073 546int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 547{
548 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
549 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
550 int i;
551 int ret;
ff03a073 552 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 553
ff03a073
JR		 554 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
555 offset * sizeof(u64), sizeof(pdpte),
556 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 557 if (ret < 0) {
558 ret = 0;
559 goto out;
560 }
561 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 562 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 563 (pdpte[i] &
564 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 565 ret = 0;
566 goto out;
567 }
568 }
569 ret = 1;
570
ff03a073 571 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 572 __set_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_avail);
574 __set_bit(VCPU_EXREG_PDPTR,
575 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 576out:
a03490ed
CO		 577
578 return ret;
579}
cc4b6871 580EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 581
9ed38ffa 582bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 583{
ff03a073 584 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 585 bool changed = true;
3d06b8bf
JR		 586 int offset;
587 gfn_t gfn;
d835dfec
AK		 588 int r;
589
590 if (is_long_mode(vcpu) || !is_pae(vcpu))
591 return false;
592
6de4f3ad
AK		 593 if (!test_bit(VCPU_EXREG_PDPTR,
594 (unsigned long *)&vcpu->arch.regs_avail))
595 return true;
596
9f8fe504
AK		 597 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
598 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 599 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
600 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 601 if (r < 0)
602 goto out;
ff03a073 603 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 604out:
d835dfec
AK		 605
606 return changed;
607}
9ed38ffa 608EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 609
49a9b07e 610int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 611{
aad82703 612 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 613 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 614
f9a48e6a
AK		 615 cr0 |= X86_CR0_ET;
616
ab344828 617#ifdef CONFIG_X86_64
0f12244f
GN		 618 if (cr0 & 0xffffffff00000000UL)
619 return 1;
ab344828
GN		 620#endif
621
622 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 623
0f12244f
GN		 624 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
625 return 1;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
628 return 1;
a03490ed
CO		 629
630 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
631#ifdef CONFIG_X86_64
f6801dff 632 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 633 int cs_db, cs_l;
634
0f12244f
GN		 635 if (!is_pae(vcpu))
636 return 1;
a03490ed 637 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 638 if (cs_l)
639 return 1;
a03490ed
CO		 640 } else
641#endif
ff03a073 642 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 643 kvm_read_cr3(vcpu)))
0f12244f 644 return 1;
a03490ed
CO		 645 }
646
ad756a16
MJ		 647 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
648 return 1;
649
a03490ed 650 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 651
d170c419 652 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 653 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 654 kvm_async_pf_hash_reset(vcpu);
655 }
e5f3f027 656
aad82703
SY		 657 if ((cr0 ^ old_cr0) & update_bits)
658 kvm_mmu_reset_context(vcpu);
b18d5431 659
879ae188
LE		 660 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
661 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
662 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 663 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
664
0f12244f
GN		 665 return 0;
666}
2d3ad1f4 667EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 668
2d3ad1f4 669void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 670{
49a9b07e 671 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 672}
2d3ad1f4 673EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 674
42bdf991
MT		 675static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
676{
677 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
678 !vcpu->guest_xcr0_loaded) {
679 /* kvm_set_xcr() also depends on this */
680 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
681 vcpu->guest_xcr0_loaded = 1;
682 }
683}
684
685static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
686{
687 if (vcpu->guest_xcr0_loaded) {
688 if (vcpu->arch.xcr0 != host_xcr0)
689 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
690 vcpu->guest_xcr0_loaded = 0;
691 }
692}
693
69b0049a 694static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 695{
56c103ec
LJ		 696 u64 xcr0 = xcr;
697 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 698 u64 valid_bits;
2acf923e
DC		 699
700 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
701 if (index != XCR_XFEATURE_ENABLED_MASK)
702 return 1;
d91cab78 703 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 704 return 1;
d91cab78 705 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 706 return 1;
46c34cb0
PB		 707
708 /*
709 * Do not allow the guest to set bits that we do not support
710 * saving. However, xcr0 bit 0 is always set, even if the
711 * emulated CPU does not support XSAVE (see fx_init).
712 */
d91cab78 713 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 714 if (xcr0 & ~valid_bits)
2acf923e 715 return 1;
46c34cb0 716
d91cab78
DH		 717 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
718 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 719 return 1;
720
d91cab78
DH		 721 if (xcr0 & XFEATURE_MASK_AVX512) {
722 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 723 return 1;
d91cab78 724 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 725 return 1;
726 }
2acf923e 727 vcpu->arch.xcr0 = xcr0;
56c103ec 728
d91cab78 729 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 730 kvm_update_cpuid(vcpu);
2acf923e
DC		 731 return 0;
732}
733
734int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
735{
764bcbc5
Z		 736 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
737 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 738 kvm_inject_gp(vcpu, 0);
739 return 1;
740 }
741 return 0;
742}
743EXPORT_SYMBOL_GPL(kvm_set_xcr);
744
a83b29c6 745int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 746{
fc78f519 747 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 748 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 749 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 750
0f12244f
GN		 751 if (cr4 & CR4_RESERVED_BITS)
752 return 1;
a03490ed 753
2acf923e
DC		 754 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
755 return 1;
756
c68b734f
YW		 757 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
758 return 1;
759
97ec8c06
FW		 760 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
761 return 1;
762
afcbf13f 763 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 764 return 1;
765
b9baba86
HH		 766 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
767 return 1;
768
a03490ed 769 if (is_long_mode(vcpu)) {
0f12244f
GN		 770 if (!(cr4 & X86_CR4_PAE))
771 return 1;
a2edf57f
AK		 772 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
773 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 774 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
775 kvm_read_cr3(vcpu)))
0f12244f
GN		 776 return 1;
777
ad756a16
MJ		 778 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
779 if (!guest_cpuid_has_pcid(vcpu))
780 return 1;
781
782 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
783 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
784 return 1;
785 }
786
5e1746d6 787 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 788 return 1;
a03490ed 789
ad756a16
MJ		 790 if (((cr4 ^ old_cr4) & pdptr_bits) ||
791 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 792 kvm_mmu_reset_context(vcpu);
0f12244f 793
b9baba86 794 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 795 kvm_update_cpuid(vcpu);
2acf923e 796
0f12244f
GN		 797 return 0;
798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 800
2390218b 801int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 802{
ac146235 803#ifdef CONFIG_X86_64
9d88fca7 804 cr3 &= ~CR3_PCID_INVD;
ac146235 805#endif
9d88fca7 806
9f8fe504 807 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 808 kvm_mmu_sync_roots(vcpu);
77c3913b 809 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 810 return 0;
d835dfec
AK		 811 }
812
a03490ed 813 if (is_long_mode(vcpu)) {
d9f89b88
JK		 814 if (cr3 & CR3_L_MODE_RESERVED_BITS)
815 return 1;
816 } else if (is_pae(vcpu) && is_paging(vcpu) &&
817 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 818 return 1;
a03490ed 819
0f12244f 820 vcpu->arch.cr3 = cr3;
aff48baa 821 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 822 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 823 return 0;
824}
2d3ad1f4 825EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 826
eea1cff9 827int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 828{
0f12244f
GN		 829 if (cr8 & CR8_RESERVED_BITS)
830 return 1;
35754c98 831 if (lapic_in_kernel(vcpu))
a03490ed
CO		 832 kvm_lapic_set_tpr(vcpu, cr8);
833 else
ad312c7c 834 vcpu->arch.cr8 = cr8;
0f12244f
GN		 835 return 0;
836}
2d3ad1f4 837EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 838
2d3ad1f4 839unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 840{
35754c98 841 if (lapic_in_kernel(vcpu))
a03490ed
CO		 842 return kvm_lapic_get_cr8(vcpu);
843 else
ad312c7c 844 return vcpu->arch.cr8;
a03490ed 845}
2d3ad1f4 846EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 847
ae561ede
NA		 848static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
849{
850 int i;
851
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
853 for (i = 0; i < KVM_NR_DB_REGS; i++)
854 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
855 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
856 }
857}
858
73aaf249
JK		 859static void kvm_update_dr6(struct kvm_vcpu *vcpu)
860{
861 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
862 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
863}
864
c8639010
JK		 865static void kvm_update_dr7(struct kvm_vcpu *vcpu)
866{
867 unsigned long dr7;
868
869 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
870 dr7 = vcpu->arch.guest_debug_dr7;
871 else
872 dr7 = vcpu->arch.dr7;
873 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 874 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
875 if (dr7 & DR7_BP_EN_MASK)
876 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 877}
878
6f43ed01
NA		 879static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
880{
881 u64 fixed = DR6_FIXED_1;
882
883 if (!guest_cpuid_has_rtm(vcpu))
884 fixed |= DR6_RTM;
885 return fixed;
886}
887
338dbc97 888static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 889{
890 switch (dr) {
891 case 0 ... 3:
892 vcpu->arch.db[dr] = val;
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 vcpu->arch.eff_db[dr] = val;
895 break;
896 case 4:
020df079
GN		 897 /* fall through */
898 case 6:
338dbc97
GN		 899 if (val & 0xffffffff00000000ULL)
900 return -1; /* #GP */
6f43ed01 901 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 902 kvm_update_dr6(vcpu);
020df079
GN		 903 break;
904 case 5:
020df079
GN		 905 /* fall through */
906 default: /* 7 */
338dbc97
GN		 907 if (val & 0xffffffff00000000ULL)
908 return -1; /* #GP */
020df079 909 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 910 kvm_update_dr7(vcpu);
020df079
GN		 911 break;
912 }
913
914 return 0;
915}
338dbc97
GN		 916
917int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
918{
16f8a6f9 919 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 920 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 921 return 1;
922 }
923 return 0;
338dbc97 924}
020df079
GN		 925EXPORT_SYMBOL_GPL(kvm_set_dr);
926
16f8a6f9 927int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 928{
929 switch (dr) {
930 case 0 ... 3:
931 *val = vcpu->arch.db[dr];
932 break;
933 case 4:
020df079
GN		 934 /* fall through */
935 case 6:
73aaf249
JK		 936 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
937 *val = vcpu->arch.dr6;
938 else
939 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 940 break;
941 case 5:
020df079
GN		 942 /* fall through */
943 default: /* 7 */
944 *val = vcpu->arch.dr7;
945 break;
946 }
338dbc97
GN		 947 return 0;
948}
020df079
GN		 949EXPORT_SYMBOL_GPL(kvm_get_dr);
950
022cd0e8
AK		 951bool kvm_rdpmc(struct kvm_vcpu *vcpu)
952{
953 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
954 u64 data;
955 int err;
956
c6702c9d 957 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 958 if (err)
959 return err;
960 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
961 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
962 return err;
963}
964EXPORT_SYMBOL_GPL(kvm_rdpmc);
965
043405e1
CO		 966/*
967 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
968 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
969 *
970 * This list is modified at module load time to reflect the
e3267cbb 971 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 972 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
973 * may depend on host virtualization features rather than host cpu features.
043405e1 974 */
e3267cbb 975
043405e1
CO		 976static u32 msrs_to_save[] = {
977 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 978 MSR_STAR,
043405e1
CO		 979#ifdef CONFIG_X86_64
980 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
981#endif
b3897a49 982 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 983 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 984};
985
986static unsigned num_msrs_to_save;
987
62ef68bb
PB		 988static u32 emulated_msrs[] = {
989 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
990 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
991 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
992 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 993 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
994 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 995 HV_X64_MSR_RESET,
11c4b1ca 996 HV_X64_MSR_VP_INDEX,
9eec50b8 997 HV_X64_MSR_VP_RUNTIME,
5c919412 998 HV_X64_MSR_SCONTROL,
1f4b34f8 999 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1000 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1001 MSR_KVM_PV_EOI_EN,
1002
ba904635 1003 MSR_IA32_TSC_ADJUST,
a3e06bbe 1004 MSR_IA32_TSCDEADLINE,
043405e1 1005 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1006 MSR_IA32_MCG_STATUS,
1007 MSR_IA32_MCG_CTL,
c45dcc71 1008 MSR_IA32_MCG_EXT_CTL,
64d60670 1009 MSR_IA32_SMBASE,
db2336a8
KH		 1010 MSR_PLATFORM_INFO,
1011 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1012};
1013
62ef68bb
PB		 1014static unsigned num_emulated_msrs;
1015
384bb783 1016bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1017{
b69e8cae 1018 if (efer & efer_reserved_bits)
384bb783 1019 return false;
15c4a640 1020
1b2fd70c
AG		 1021 if (efer & EFER_FFXSR) {
1022 struct kvm_cpuid_entry2 *feat;
1023
1024 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1025 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1026 return false;
1b2fd70c
AG		 1027 }
1028
d8017474
AG		 1029 if (efer & EFER_SVME) {
1030 struct kvm_cpuid_entry2 *feat;
1031
1032 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1033 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1034 return false;
d8017474
AG		 1035 }
1036
384bb783
JK		 1037 return true;
1038}
1039EXPORT_SYMBOL_GPL(kvm_valid_efer);
1040
1041static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1042{
1043 u64 old_efer = vcpu->arch.efer;
1044
1045 if (!kvm_valid_efer(vcpu, efer))
1046 return 1;
1047
1048 if (is_paging(vcpu)
1049 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1050 return 1;
1051
15c4a640 1052 efer &= ~EFER_LMA;
f6801dff 1053 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1054
a3d204e2
SY		 1055 kvm_x86_ops->set_efer(vcpu, efer);
1056
aad82703
SY		 1057 /* Update reserved bits */
1058 if ((efer ^ old_efer) & EFER_NX)
1059 kvm_mmu_reset_context(vcpu);
1060
b69e8cae 1061 return 0;
15c4a640
CO		 1062}
1063
f2b4b7dd
JR		 1064void kvm_enable_efer_bits(u64 mask)
1065{
1066 efer_reserved_bits &= ~mask;
1067}
1068EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1069
15c4a640
CO		 1070/*
1071 * Writes msr value into into the appropriate "register".
1072 * Returns 0 on success, non-0 otherwise.
1073 * Assumes vcpu_load() was already called.
1074 */
8fe8ab46 1075int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1076{
854e8bb1
NA		 1077 switch (msr->index) {
1078 case MSR_FS_BASE:
1079 case MSR_GS_BASE:
1080 case MSR_KERNEL_GS_BASE:
1081 case MSR_CSTAR:
1082 case MSR_LSTAR:
1083 if (is_noncanonical_address(msr->data))
1084 return 1;
1085 break;
1086 case MSR_IA32_SYSENTER_EIP:
1087 case MSR_IA32_SYSENTER_ESP:
1088 /*
1089 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1090 * non-canonical address is written on Intel but not on
1091 * AMD (which ignores the top 32-bits, because it does
1092 * not implement 64-bit SYSENTER).
1093 *
1094 * 64-bit code should hence be able to write a non-canonical
1095 * value on AMD. Making the address canonical ensures that
1096 * vmentry does not fail on Intel after writing a non-canonical
1097 * value, and that something deterministic happens if the guest
1098 * invokes 64-bit SYSENTER.
1099 */
1100 msr->data = get_canonical(msr->data);
1101 }
8fe8ab46 1102 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1103}
854e8bb1 1104EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1105
313a3dc7
CO		 1106/*
1107 * Adapt set_msr() to msr_io()'s calling convention
1108 */
609e36d3
PB		 1109static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1110{
1111 struct msr_data msr;
1112 int r;
1113
1114 msr.index = index;
1115 msr.host_initiated = true;
1116 r = kvm_get_msr(vcpu, &msr);
1117 if (r)
1118 return r;
1119
1120 *data = msr.data;
1121 return 0;
1122}
1123
313a3dc7
CO		 1124static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1125{
8fe8ab46
WA		 1126 struct msr_data msr;
1127
1128 msr.data = *data;
1129 msr.index = index;
1130 msr.host_initiated = true;
1131 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1132}
1133
16e8d74d
MT		 1134#ifdef CONFIG_X86_64
1135struct pvclock_gtod_data {
1136 seqcount_t seq;
1137
1138 struct { /* extract of a clocksource struct */
1139 int vclock_mode;
a5a1d1c2
TG		 1140 u64 cycle_last;
1141 u64 mask;
16e8d74d
MT		 1142 u32 mult;
1143 u32 shift;
1144 } clock;
1145
cbcf2dd3
TG		 1146 u64 boot_ns;
1147 u64 nsec_base;
55dd00a7 1148 u64 wall_time_sec;
16e8d74d
MT		 1149};
1150
1151static struct pvclock_gtod_data pvclock_gtod_data;
1152
1153static void update_pvclock_gtod(struct timekeeper *tk)
1154{
1155 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1156 u64 boot_ns;
1157
876e7881 1158 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1159
1160 write_seqcount_begin(&vdata->seq);
1161
1162 /* copy pvclock gtod data */
876e7881
PZ		 1163 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1164 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1165 vdata->clock.mask = tk->tkr_mono.mask;
1166 vdata->clock.mult = tk->tkr_mono.mult;
1167 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1168
cbcf2dd3 1169 vdata->boot_ns = boot_ns;
876e7881 1170 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1171
55dd00a7
MT		 1172 vdata->wall_time_sec = tk->xtime_sec;
1173
16e8d74d
MT		 1174 write_seqcount_end(&vdata->seq);
1175}
1176#endif
1177
bab5bb39
NK		 1178void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1179{
1180 /*
1181 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1182 * vcpu_enter_guest. This function is only called from
1183 * the physical CPU that is running vcpu.
1184 */
1185 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1186}
16e8d74d 1187
18068523
GOC		 1188static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1189{
9ed3c444
AK		 1190 int version;
1191 int r;
50d0a0f9 1192 struct pvclock_wall_clock wc;
87aeb54f 1193 struct timespec64 boot;
18068523
GOC		 1194
1195 if (!wall_clock)
1196 return;
1197
9ed3c444
AK		 1198 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1199 if (r)
1200 return;
1201
1202 if (version & 1)
1203 ++version; /* first time write, random junk */
1204
1205 ++version;
18068523 1206
1dab1345
NK		 1207 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1208 return;
18068523 1209
50d0a0f9
GH		 1210 /*
1211 * The guest calculates current wall clock time by adding
34c238a1 1212 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1213 * wall clock specified here. guest system time equals host
1214 * system time for us, thus we must fill in host boot time here.
1215 */
87aeb54f 1216 getboottime64(&boot);
50d0a0f9 1217
4b648665 1218 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1219 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1220 boot = timespec64_sub(boot, ts);
4b648665 1221 }
87aeb54f 1222 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1223 wc.nsec = boot.tv_nsec;
1224 wc.version = version;
18068523
GOC		 1225
1226 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1227
1228 version++;
1229 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1230}
1231
50d0a0f9
GH		 1232static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1233{
b51012de
PB		 1234 do_shl32_div32(dividend, divisor);
1235 return dividend;
50d0a0f9
GH		 1236}
1237
3ae13faa 1238static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1239 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1240{
5f4e3f88 1241 uint64_t scaled64;
50d0a0f9
GH		 1242 int32_t shift = 0;
1243 uint64_t tps64;
1244 uint32_t tps32;
1245
3ae13faa
PB		 1246 tps64 = base_hz;
1247 scaled64 = scaled_hz;
50933623 1248 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1249 tps64 >>= 1;
1250 shift--;
1251 }
1252
1253 tps32 = (uint32_t)tps64;
50933623
JK		 1254 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1255 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1256 scaled64 >>= 1;
1257 else
1258 tps32 <<= 1;
50d0a0f9
GH		 1259 shift++;
1260 }
1261
5f4e3f88
ZA		 1262 *pshift = shift;
1263 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1264
3ae13faa
PB		 1265 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1266 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1267}
1268
d828199e 1269#ifdef CONFIG_X86_64
16e8d74d 1270static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1271#endif
16e8d74d 1272
c8076604 1273static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1274static unsigned long max_tsc_khz;
c8076604 1275
cc578287 1276static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1277{
cc578287
ZA		 1278 u64 v = (u64)khz * (1000000 + ppm);
1279 do_div(v, 1000000);
1280 return v;
1e993611
JR		 1281}
1282
381d585c
HZ		 1283static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1284{
1285 u64 ratio;
1286
1287 /* Guest TSC same frequency as host TSC? */
1288 if (!scale) {
1289 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1290 return 0;
1291 }
1292
1293 /* TSC scaling supported? */
1294 if (!kvm_has_tsc_control) {
1295 if (user_tsc_khz > tsc_khz) {
1296 vcpu->arch.tsc_catchup = 1;
1297 vcpu->arch.tsc_always_catchup = 1;
1298 return 0;
1299 } else {
1300 WARN(1, "user requested TSC rate below hardware speed\n");
1301 return -1;
1302 }
1303 }
1304
1305 /* TSC scaling required - calculate ratio */
1306 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1307 user_tsc_khz, tsc_khz);
1308
1309 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1310 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1311 user_tsc_khz);
1312 return -1;
1313 }
1314
1315 vcpu->arch.tsc_scaling_ratio = ratio;
1316 return 0;
1317}
1318
4941b8cb 1319static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1320{
cc578287
ZA		 1321 u32 thresh_lo, thresh_hi;
1322 int use_scaling = 0;
217fc9cf 1323
03ba32ca 1324 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1325 if (user_tsc_khz == 0) {
ad721883
HZ		 1326 /* set tsc_scaling_ratio to a safe value */
1327 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1328 return -1;
ad721883 1329 }
03ba32ca 1330
c285545f 1331 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1332 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1333 &vcpu->arch.virtual_tsc_shift,
1334 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1335 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1336
1337 /*
1338 * Compute the variation in TSC rate which is acceptable
1339 * within the range of tolerance and decide if the
1340 * rate being applied is within that bounds of the hardware
1341 * rate. If so, no scaling or compensation need be done.
1342 */
1343 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1344 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1345 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1346 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1347 use_scaling = 1;
1348 }
4941b8cb 1349 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1350}
1351
1352static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1353{
e26101b1 1354 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1355 vcpu->arch.virtual_tsc_mult,
1356 vcpu->arch.virtual_tsc_shift);
e26101b1 1357 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1358 return tsc;
1359}
1360
69b0049a 1361static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1362{
1363#ifdef CONFIG_X86_64
1364 bool vcpus_matched;
b48aa97e
MT		 1365 struct kvm_arch *ka = &vcpu->kvm->arch;
1366 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1367
1368 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1369 atomic_read(&vcpu->kvm->online_vcpus));
1370
7f187922
MT		 1371 /*
1372 * Once the masterclock is enabled, always perform request in
1373 * order to update it.
1374 *
1375 * In order to enable masterclock, the host clocksource must be TSC
1376 * and the vcpus need to have matched TSCs. When that happens,
1377 * perform request to enable masterclock.
1378 */
1379 if (ka->use_master_clock ||
1380 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1381 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1382
1383 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1384 atomic_read(&vcpu->kvm->online_vcpus),
1385 ka->use_master_clock, gtod->clock.vclock_mode);
1386#endif
1387}
1388
ba904635
WA		 1389static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1390{
3e3f5026 1391 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1392 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1393}
1394
35181e86
HZ		 1395/*
1396 * Multiply tsc by a fixed point number represented by ratio.
1397 *
1398 * The most significant 64-N bits (mult) of ratio represent the
1399 * integral part of the fixed point number; the remaining N bits
1400 * (frac) represent the fractional part, ie. ratio represents a fixed
1401 * point number (mult + frac * 2^(-N)).
1402 *
1403 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1404 */
1405static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1406{
1407 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1408}
1409
1410u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1411{
1412 u64 _tsc = tsc;
1413 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1414
1415 if (ratio != kvm_default_tsc_scaling_ratio)
1416 _tsc = __scale_tsc(ratio, tsc);
1417
1418 return _tsc;
1419}
1420EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1421
07c1419a
HZ		 1422static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1423{
1424 u64 tsc;
1425
1426 tsc = kvm_scale_tsc(vcpu, rdtsc());
1427
1428 return target_tsc - tsc;
1429}
1430
4ba76538
HZ		 1431u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1432{
ea26e4ec 1433 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1434}
1435EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1436
a545ab6a
LC		 1437static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1438{
1439 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1440 vcpu->arch.tsc_offset = offset;
1441}
1442
8fe8ab46 1443void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1444{
1445 struct kvm *kvm = vcpu->kvm;
f38e098f 1446 u64 offset, ns, elapsed;
99e3e30a 1447 unsigned long flags;
b48aa97e 1448 bool matched;
0d3da0d2 1449 bool already_matched;
8fe8ab46 1450 u64 data = msr->data;
c5e8ec8e 1451 bool synchronizing = false;
99e3e30a 1452
038f8c11 1453 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1454 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1455 ns = ktime_get_boot_ns();
f38e098f 1456 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1457
03ba32ca 1458 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1459 if (data == 0 && msr->host_initiated) {
1460 /*
1461 * detection of vcpu initialization -- need to sync
1462 * with other vCPUs. This particularly helps to keep
1463 * kvm_clock stable after CPU hotplug
1464 */
1465 synchronizing = true;
1466 } else {
1467 u64 tsc_exp = kvm->arch.last_tsc_write +
1468 nsec_to_cycles(vcpu, elapsed);
1469 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1470 /*
1471 * Special case: TSC write with a small delta (1 second)
1472 * of virtual cycle time against real time is
1473 * interpreted as an attempt to synchronize the CPU.
1474 */
1475 synchronizing = data < tsc_exp + tsc_hz &&
1476 data + tsc_hz > tsc_exp;
1477 }
c5e8ec8e 1478 }
f38e098f
ZA		 1479
1480 /*
5d3cb0f6
ZA		 1481 * For a reliable TSC, we can match TSC offsets, and for an unstable
1482 * TSC, we add elapsed time in this computation. We could let the
1483 * compensation code attempt to catch up if we fall behind, but
1484 * it's better to try to match offsets from the beginning.
1485 */
c5e8ec8e 1486 if (synchronizing &&
5d3cb0f6 1487 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1488 if (!check_tsc_unstable()) {
e26101b1 1489 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1490 pr_debug("kvm: matched tsc offset for %llu\n", data);
1491 } else {
857e4099 1492 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1493 data += delta;
07c1419a 1494 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1495 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1496 }
b48aa97e 1497 matched = true;
0d3da0d2 1498 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1499 } else {
1500 /*
1501 * We split periods of matched TSC writes into generations.
1502 * For each generation, we track the original measured
1503 * nanosecond time, offset, and write, so if TSCs are in
1504 * sync, we can match exact offset, and if not, we can match
4a969980 1505 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1506 *
1507 * These values are tracked in kvm->arch.cur_xxx variables.
1508 */
1509 kvm->arch.cur_tsc_generation++;
1510 kvm->arch.cur_tsc_nsec = ns;
1511 kvm->arch.cur_tsc_write = data;
1512 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1513 matched = false;
0d3da0d2 1514 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1515 kvm->arch.cur_tsc_generation, data);
f38e098f 1516 }
e26101b1
ZA		 1517
1518 /*
1519 * We also track th most recent recorded KHZ, write and time to
1520 * allow the matching interval to be extended at each write.
1521 */
f38e098f
ZA		 1522 kvm->arch.last_tsc_nsec = ns;
1523 kvm->arch.last_tsc_write = data;
5d3cb0f6 1524 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1525
b183aa58 1526 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1527
1528 /* Keep track of which generation this VCPU has synchronized to */
1529 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1530 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1531 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1532
ba904635
WA		 1533 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1534 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1535 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1536 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1537
1538 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1539 if (!matched) {
b48aa97e 1540 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1541 } else if (!already_matched) {
1542 kvm->arch.nr_vcpus_matched_tsc++;
1543 }
b48aa97e
MT		 1544
1545 kvm_track_tsc_matching(vcpu);
1546 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1547}
e26101b1 1548
99e3e30a
ZA		 1549EXPORT_SYMBOL_GPL(kvm_write_tsc);
1550
58ea6767
HZ		 1551static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1552 s64 adjustment)
1553{
ea26e4ec 1554 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1555}
1556
1557static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1558{
1559 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1560 WARN_ON(adjustment < 0);
1561 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1562 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1563}
1564
d828199e
MT		 1565#ifdef CONFIG_X86_64
1566
a5a1d1c2 1567static u64 read_tsc(void)
d828199e 1568{
a5a1d1c2 1569 u64 ret = (u64)rdtsc_ordered();
03b9730b 1570 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1571
1572 if (likely(ret >= last))
1573 return ret;
1574
1575 /*
1576 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1577 * predictable (it's just a function of time and the likely is
d828199e
MT		 1578 * very likely) and there's a data dependence, so force GCC
1579 * to generate a branch instead. I don't barrier() because
1580 * we don't actually need a barrier, and if this function
1581 * ever gets inlined it will generate worse code.
1582 */
1583 asm volatile ("");
1584 return last;
1585}
1586
a5a1d1c2 1587static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1588{
1589 long v;
1590 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1591
1592 *cycle_now = read_tsc();
1593
1594 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1595 return v * gtod->clock.mult;
1596}
1597
a5a1d1c2 1598static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1599{
cbcf2dd3 1600 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1601 unsigned long seq;
d828199e 1602 int mode;
cbcf2dd3 1603 u64 ns;
d828199e 1604
d828199e
MT		 1605 do {
1606 seq = read_seqcount_begin(&gtod->seq);
1607 mode = gtod->clock.vclock_mode;
cbcf2dd3 1608 ns = gtod->nsec_base;
d828199e
MT		 1609 ns += vgettsc(cycle_now);
1610 ns >>= gtod->clock.shift;
cbcf2dd3 1611 ns += gtod->boot_ns;
d828199e 1612 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1613 *t = ns;
d828199e
MT		 1614
1615 return mode;
1616}
1617
55dd00a7
MT		 1618static int do_realtime(struct timespec *ts, u64 *cycle_now)
1619{
1620 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1621 unsigned long seq;
1622 int mode;
1623 u64 ns;
1624
1625 do {
1626 seq = read_seqcount_begin(&gtod->seq);
1627 mode = gtod->clock.vclock_mode;
1628 ts->tv_sec = gtod->wall_time_sec;
1629 ns = gtod->nsec_base;
1630 ns += vgettsc(cycle_now);
1631 ns >>= gtod->clock.shift;
1632 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1633
1634 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1635 ts->tv_nsec = ns;
1636
1637 return mode;
1638}
1639
d828199e 1640/* returns true if host is using tsc clocksource */
a5a1d1c2 1641static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1642{
d828199e
MT		 1643 /* checked again under seqlock below */
1644 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1645 return false;
1646
cbcf2dd3 1647 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1648}
55dd00a7
MT		 1649
1650/* returns true if host is using tsc clocksource */
1651static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1652 u64 *cycle_now)
1653{
1654 /* checked again under seqlock below */
1655 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1656 return false;
1657
1658 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1659}
d828199e
MT		 1660#endif
1661
1662/*
1663 *
b48aa97e
MT		 1664 * Assuming a stable TSC across physical CPUS, and a stable TSC
1665 * across virtual CPUs, the following condition is possible.
1666 * Each numbered line represents an event visible to both
d828199e
MT		 1667 * CPUs at the next numbered event.
1668 *
1669 * "timespecX" represents host monotonic time. "tscX" represents
1670 * RDTSC value.
1671 *
1672 * VCPU0 on CPU0 | VCPU1 on CPU1
1673 *
1674 * 1. read timespec0,tsc0
1675 * 2. | timespec1 = timespec0 + N
1676 * | tsc1 = tsc0 + M
1677 * 3. transition to guest | transition to guest
1678 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1679 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1680 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1681 *
1682 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1683 *
1684 * - ret0 < ret1
1685 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1686 * ...
1687 * - 0 < N - M => M < N
1688 *
1689 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1690 * always the case (the difference between two distinct xtime instances
1691 * might be smaller then the difference between corresponding TSC reads,
1692 * when updating guest vcpus pvclock areas).
1693 *
1694 * To avoid that problem, do not allow visibility of distinct
1695 * system_timestamp/tsc_timestamp values simultaneously: use a master
1696 * copy of host monotonic time values. Update that master copy
1697 * in lockstep.
1698 *
b48aa97e 1699 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1700 *
1701 */
1702
1703static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1704{
1705#ifdef CONFIG_X86_64
1706 struct kvm_arch *ka = &kvm->arch;
1707 int vclock_mode;
b48aa97e
MT		 1708 bool host_tsc_clocksource, vcpus_matched;
1709
1710 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1711 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1712
1713 /*
1714 * If the host uses TSC clock, then passthrough TSC as stable
1715 * to the guest.
1716 */
b48aa97e 1717 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1718 &ka->master_kernel_ns,
1719 &ka->master_cycle_now);
1720
16a96021 1721 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1722 && !backwards_tsc_observed
1723 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1724
d828199e
MT		 1725 if (ka->use_master_clock)
1726 atomic_set(&kvm_guest_has_master_clock, 1);
1727
1728 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1729 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1730 vcpus_matched);
d828199e
MT		 1731#endif
1732}
1733
2860c4b1
PB		 1734void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1735{
1736 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1737}
1738
2e762ff7
MT		 1739static void kvm_gen_update_masterclock(struct kvm *kvm)
1740{
1741#ifdef CONFIG_X86_64
1742 int i;
1743 struct kvm_vcpu *vcpu;
1744 struct kvm_arch *ka = &kvm->arch;
1745
1746 spin_lock(&ka->pvclock_gtod_sync_lock);
1747 kvm_make_mclock_inprogress_request(kvm);
1748 /* no guest entries from this point */
1749 pvclock_update_vm_gtod_copy(kvm);
1750
1751 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1752 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1753
1754 /* guest entries allowed */
1755 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1756 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1757
1758 spin_unlock(&ka->pvclock_gtod_sync_lock);
1759#endif
1760}
1761
e891a32e 1762u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1763{
108b249c 1764 struct kvm_arch *ka = &kvm->arch;
8b953440 1765 struct pvclock_vcpu_time_info hv_clock;
108b249c 1766
8b953440
PB		 1767 spin_lock(&ka->pvclock_gtod_sync_lock);
1768 if (!ka->use_master_clock) {
1769 spin_unlock(&ka->pvclock_gtod_sync_lock);
1770 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1771 }
1772
8b953440
PB		 1773 hv_clock.tsc_timestamp = ka->master_cycle_now;
1774 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1775 spin_unlock(&ka->pvclock_gtod_sync_lock);
1776
1777 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1778 &hv_clock.tsc_shift,
1779 &hv_clock.tsc_to_system_mul);
1780 return __pvclock_read_cycles(&hv_clock, rdtsc());
108b249c
PB		 1781}
1782
0d6dd2ff
PB		 1783static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1784{
1785 struct kvm_vcpu_arch *vcpu = &v->arch;
1786 struct pvclock_vcpu_time_info guest_hv_clock;
1787
bbd64115 1788 if (unlikely(kvm_vcpu_read_guest_cached(v, &vcpu->pv_time,
0d6dd2ff
PB		 1789 &guest_hv_clock, sizeof(guest_hv_clock))))
1790 return;
1791
1792 /* This VCPU is paused, but it's legal for a guest to read another
1793 * VCPU's kvmclock, so we really have to follow the specification where
1794 * it says that version is odd if data is being modified, and even after
1795 * it is consistent.
1796 *
1797 * Version field updates must be kept separate. This is because
1798 * kvm_write_guest_cached might use a "rep movs" instruction, and
1799 * writes within a string instruction are weakly ordered. So there
1800 * are three writes overall.
1801 *
1802 * As a small optimization, only write the version field in the first
1803 * and third write. The vcpu->pv_time cache is still valid, because the
1804 * version field is the first in the struct.
1805 */
1806 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1807
1808 vcpu->hv_clock.version = guest_hv_clock.version + 1;
bbd64115
CL		 1809 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1810 &vcpu->hv_clock,
1811 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1812
1813 smp_wmb();
1814
1815 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1816 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1817
1818 if (vcpu->pvclock_set_guest_stopped_request) {
1819 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1820 vcpu->pvclock_set_guest_stopped_request = false;
1821 }
1822
1823 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1824
bbd64115
CL		 1825 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1826 &vcpu->hv_clock,
1827 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1828
1829 smp_wmb();
1830
1831 vcpu->hv_clock.version++;
bbd64115
CL		 1832 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1833 &vcpu->hv_clock,
1834 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1835}
1836
34c238a1 1837static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1838{
78db6a50 1839 unsigned long flags, tgt_tsc_khz;
18068523 1840 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1841 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1842 s64 kernel_ns;
d828199e 1843 u64 tsc_timestamp, host_tsc;
51d59c6b 1844 u8 pvclock_flags;
d828199e
MT		 1845 bool use_master_clock;
1846
1847 kernel_ns = 0;
1848 host_tsc = 0;
18068523 1849
d828199e
MT		 1850 /*
1851 * If the host uses TSC clock, then passthrough TSC as stable
1852 * to the guest.
1853 */
1854 spin_lock(&ka->pvclock_gtod_sync_lock);
1855 use_master_clock = ka->use_master_clock;
1856 if (use_master_clock) {
1857 host_tsc = ka->master_cycle_now;
1858 kernel_ns = ka->master_kernel_ns;
1859 }
1860 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1861
1862 /* Keep irq disabled to prevent changes to the clock */
1863 local_irq_save(flags);
78db6a50
PB		 1864 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1865 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1866 local_irq_restore(flags);
1867 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1868 return 1;
1869 }
d828199e 1870 if (!use_master_clock) {
4ea1636b 1871 host_tsc = rdtsc();
108b249c 1872 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1873 }
1874
4ba76538 1875 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1876
c285545f
ZA		 1877 /*
1878 * We may have to catch up the TSC to match elapsed wall clock
1879 * time for two reasons, even if kvmclock is used.
1880 * 1) CPU could have been running below the maximum TSC rate
1881 * 2) Broken TSC compensation resets the base at each VCPU
1882 * entry to avoid unknown leaps of TSC even when running
1883 * again on the same CPU. This may cause apparent elapsed
1884 * time to disappear, and the guest to stand still or run
1885 * very slowly.
1886 */
1887 if (vcpu->tsc_catchup) {
1888 u64 tsc = compute_guest_tsc(v, kernel_ns);
1889 if (tsc > tsc_timestamp) {
f1e2b260 1890 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1891 tsc_timestamp = tsc;
1892 }
50d0a0f9
GH		 1893 }
1894
18068523
GOC		 1895 local_irq_restore(flags);
1896
0d6dd2ff 1897 /* With all the info we got, fill in the values */
18068523 1898
78db6a50
PB		 1899 if (kvm_has_tsc_control)
1900 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1901
1902 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1903 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1904 &vcpu->hv_clock.tsc_shift,
1905 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1906 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1907 }
1908
1d5f066e 1909 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1910 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1911 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1912
d828199e 1913 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1914 pvclock_flags = 0;
d828199e
MT		 1915 if (use_master_clock)
1916 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1917
78c0337a
MT		 1918 vcpu->hv_clock.flags = pvclock_flags;
1919
095cf55d
PB		 1920 if (vcpu->pv_time_enabled)
1921 kvm_setup_pvclock_page(v);
1922 if (v == kvm_get_vcpu(v->kvm, 0))
1923 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1924 return 0;
c8076604
GH		 1925}
1926
0061d53d
MT		 1927/*
1928 * kvmclock updates which are isolated to a given vcpu, such as
1929 * vcpu->cpu migration, should not allow system_timestamp from
1930 * the rest of the vcpus to remain static. Otherwise ntp frequency
1931 * correction applies to one vcpu's system_timestamp but not
1932 * the others.
1933 *
1934 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1935 * We need to rate-limit these requests though, as they can
1936 * considerably slow guests that have a large number of vcpus.
1937 * The time for a remote vcpu to update its kvmclock is bound
1938 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1939 */
1940
7e44e449
AJ		 1941#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1942
1943static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1944{
1945 int i;
7e44e449
AJ		 1946 struct delayed_work *dwork = to_delayed_work(work);
1947 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1948 kvmclock_update_work);
1949 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1950 struct kvm_vcpu *vcpu;
1951
1952 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1953 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1954 kvm_vcpu_kick(vcpu);
1955 }
1956}
1957
7e44e449
AJ		 1958static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1959{
1960 struct kvm *kvm = v->kvm;
1961
105b21bb 1962 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1963 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1964 KVMCLOCK_UPDATE_DELAY);
1965}
1966
332967a3
AJ		 1967#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1968
1969static void kvmclock_sync_fn(struct work_struct *work)
1970{
1971 struct delayed_work *dwork = to_delayed_work(work);
1972 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1973 kvmclock_sync_work);
1974 struct kvm *kvm = container_of(ka, struct kvm, arch);
1975
630994b3
MT		 1976 if (!kvmclock_periodic_sync)
1977 return;
1978
332967a3
AJ		 1979 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1980 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1981 KVMCLOCK_SYNC_PERIOD);
1982}
1983
890ca9ae 1984static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1985{
890ca9ae
HY		 1986 u64 mcg_cap = vcpu->arch.mcg_cap;
1987 unsigned bank_num = mcg_cap & 0xff;
1988
15c4a640 1989 switch (msr) {
15c4a640 1990 case MSR_IA32_MCG_STATUS:
890ca9ae 1991 vcpu->arch.mcg_status = data;
15c4a640 1992 break;
c7ac679c 1993 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1994 if (!(mcg_cap & MCG_CTL_P))
1995 return 1;
1996 if (data != 0 && data != ~(u64)0)
1997 return -1;
1998 vcpu->arch.mcg_ctl = data;
1999 break;
2000 default:
2001 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2002 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2003 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2004 /* only 0 or all 1s can be written to IA32_MCi_CTL
2005 * some Linux kernels though clear bit 10 in bank 4 to
2006 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2007 * this to avoid an uncatched #GP in the guest
2008 */
890ca9ae 2009 if ((offset & 0x3) == 0 &&
114be429 2010 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2011 return -1;
2012 vcpu->arch.mce_banks[offset] = data;
2013 break;
2014 }
2015 return 1;
2016 }
2017 return 0;
2018}
2019
ffde22ac
ES		 2020static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2021{
2022 struct kvm *kvm = vcpu->kvm;
2023 int lm = is_long_mode(vcpu);
2024 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2025 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2026 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2027 : kvm->arch.xen_hvm_config.blob_size_32;
2028 u32 page_num = data & ~PAGE_MASK;
2029 u64 page_addr = data & PAGE_MASK;
2030 u8 *page;
2031 int r;
2032
2033 r = -E2BIG;
2034 if (page_num >= blob_size)
2035 goto out;
2036 r = -ENOMEM;
ff5c2c03
SL		 2037 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2038 if (IS_ERR(page)) {
2039 r = PTR_ERR(page);
ffde22ac 2040 goto out;
ff5c2c03 2041 }
54bf36aa 2042 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2043 goto out_free;
2044 r = 0;
2045out_free:
2046 kfree(page);
2047out:
2048 return r;
2049}
2050
344d9588
GN		 2051static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2052{
2053 gpa_t gpa = data & ~0x3f;
2054
4a969980 2055 /* Bits 2:5 are reserved, Should be zero */
6adba527 2056 if (data & 0x3c)
344d9588
GN		 2057 return 1;
2058
2059 vcpu->arch.apf.msr_val = data;
2060
2061 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2062 kvm_clear_async_pf_completion_queue(vcpu);
2063 kvm_async_pf_hash_reset(vcpu);
2064 return 0;
2065 }
2066
bbd64115 2067 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.apf.data, gpa,
8f964525 2068 sizeof(u32)))
344d9588
GN		 2069 return 1;
2070
6adba527 2071 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2072 kvm_async_pf_wakeup_all(vcpu);
2073 return 0;
2074}
2075
12f9a48f
GC		 2076static void kvmclock_reset(struct kvm_vcpu *vcpu)
2077{
0b79459b 2078 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2079}
2080
c9aaa895
GC		 2081static void record_steal_time(struct kvm_vcpu *vcpu)
2082{
2083 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2084 return;
2085
bbd64115 2086 if (unlikely(kvm_vcpu_read_guest_cached(vcpu, &vcpu->arch.st.stime,
c9aaa895
GC		 2087 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2088 return;
2089
0b9f6c46
PX		 2090 vcpu->arch.st.steal.preempted = 0;
2091
35f3fae1
WL		 2092 if (vcpu->arch.st.steal.version & 1)
2093 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2094
2095 vcpu->arch.st.steal.version += 1;
2096
bbd64115 2097 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
35f3fae1
WL		 2098 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2099
2100 smp_wmb();
2101
c54cdf14
LC		 2102 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2103 vcpu->arch.st.last_steal;
2104 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2105
bbd64115 2106 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
35f3fae1
WL		 2107 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2108
2109 smp_wmb();
2110
2111 vcpu->arch.st.steal.version += 1;
c9aaa895 2112
bbd64115 2113 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
c9aaa895
GC		 2114 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2115}
2116
8fe8ab46 2117int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2118{
5753785f 2119 bool pr = false;
8fe8ab46
WA		 2120 u32 msr = msr_info->index;
2121 u64 data = msr_info->data;
5753785f 2122
15c4a640 2123 switch (msr) {
2e32b719
BP		 2124 case MSR_AMD64_NB_CFG:
2125 case MSR_IA32_UCODE_REV:
2126 case MSR_IA32_UCODE_WRITE:
2127 case MSR_VM_HSAVE_PA:
2128 case MSR_AMD64_PATCH_LOADER:
2129 case MSR_AMD64_BU_CFG2:
405a353a 2130 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2131 break;
2132
15c4a640 2133 case MSR_EFER:
b69e8cae 2134 return set_efer(vcpu, data);
8f1589d9
AP		 2135 case MSR_K7_HWCR:
2136 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2137 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2138 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2139 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2140 if (data != 0) {
a737f256
CD		 2141 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2142 data);
8f1589d9
AP		 2143 return 1;
2144 }
15c4a640 2145 break;
f7c6d140
AP		 2146 case MSR_FAM10H_MMIO_CONF_BASE:
2147 if (data != 0) {
a737f256
CD		 2148 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2149 "0x%llx\n", data);
f7c6d140
AP		 2150 return 1;
2151 }
15c4a640 2152 break;
b5e2fec0
AG		 2153 case MSR_IA32_DEBUGCTLMSR:
2154 if (!data) {
2155 /* We support the non-activated case already */
2156 break;
2157 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2158 /* Values other than LBR and BTF are vendor-specific,
2159 thus reserved and should throw a #GP */
2160 return 1;
2161 }
a737f256
CD		 2162 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2163 __func__, data);
b5e2fec0 2164 break;
9ba075a6 2165 case 0x200 ... 0x2ff:
ff53604b 2166 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2167 case MSR_IA32_APICBASE:
58cb628d 2168 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2169 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2170 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2171 case MSR_IA32_TSCDEADLINE:
2172 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2173 break;
ba904635
WA		 2174 case MSR_IA32_TSC_ADJUST:
2175 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2176 if (!msr_info->host_initiated) {
d913b904 2177 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2178 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2179 }
2180 vcpu->arch.ia32_tsc_adjust_msr = data;
2181 }
2182 break;
15c4a640 2183 case MSR_IA32_MISC_ENABLE:
ad312c7c 2184 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2185 break;
64d60670
PB		 2186 case MSR_IA32_SMBASE:
2187 if (!msr_info->host_initiated)
2188 return 1;
2189 vcpu->arch.smbase = data;
2190 break;
11c6bffa 2191 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2192 case MSR_KVM_WALL_CLOCK:
2193 vcpu->kvm->arch.wall_clock = data;
2194 kvm_write_wall_clock(vcpu->kvm, data);
2195 break;
11c6bffa 2196 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2197 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2198 struct kvm_arch *ka = &vcpu->kvm->arch;
2199
12f9a48f 2200 kvmclock_reset(vcpu);
18068523 2201
54750f2c
MT		 2202 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2203 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2204
2205 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2206 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2207
2208 ka->boot_vcpu_runs_old_kvmclock = tmp;
2209 }
2210
18068523 2211 vcpu->arch.time = data;
0061d53d 2212 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2213
2214 /* we verify if the enable bit is set... */
2215 if (!(data & 1))
2216 break;
2217
bbd64115 2218 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu,
8f964525
AH		 2219 &vcpu->arch.pv_time, data & ~1ULL,
2220 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2221 vcpu->arch.pv_time_enabled = false;
2222 else
2223 vcpu->arch.pv_time_enabled = true;
32cad84f 2224
18068523
GOC		 2225 break;
2226 }
344d9588
GN		 2227 case MSR_KVM_ASYNC_PF_EN:
2228 if (kvm_pv_enable_async_pf(vcpu, data))
2229 return 1;
2230 break;
c9aaa895
GC		 2231 case MSR_KVM_STEAL_TIME:
2232
2233 if (unlikely(!sched_info_on()))
2234 return 1;
2235
2236 if (data & KVM_STEAL_RESERVED_MASK)
2237 return 1;
2238
bbd64115 2239 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.st.stime,
8f964525
AH		 2240 data & KVM_STEAL_VALID_BITS,
2241 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2242 return 1;
2243
2244 vcpu->arch.st.msr_val = data;
2245
2246 if (!(data & KVM_MSR_ENABLED))
2247 break;
2248
c9aaa895
GC		 2249 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2250
2251 break;
ae7a2a3f
MT		 2252 case MSR_KVM_PV_EOI_EN:
2253 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2254 return 1;
2255 break;
c9aaa895 2256
890ca9ae
HY		 2257 case MSR_IA32_MCG_CTL:
2258 case MSR_IA32_MCG_STATUS:
81760dcc 2259 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2260 return set_msr_mce(vcpu, msr, data);
71db6023 2261
6912ac32
WH		 2262 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2263 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2264 pr = true; /* fall through */
2265 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2266 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2267 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2268 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2269
2270 if (pr || data != 0)
a737f256
CD		 2271 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2272 "0x%x data 0x%llx\n", msr, data);
5753785f 2273 break;
84e0cefa
JS		 2274 case MSR_K7_CLK_CTL:
2275 /*
2276 * Ignore all writes to this no longer documented MSR.
2277 * Writes are only relevant for old K7 processors,
2278 * all pre-dating SVM, but a recommended workaround from
4a969980 2279 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2280 * affected processor models on the command line, hence
2281 * the need to ignore the workaround.
2282 */
2283 break;
55cd8e5a 2284 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2285 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2286 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2287 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2288 return kvm_hv_set_msr_common(vcpu, msr, data,
2289 msr_info->host_initiated);
91c9c3ed 2290 case MSR_IA32_BBL_CR_CTL3:
2291 /* Drop writes to this legacy MSR -- see rdmsr
2292 * counterpart for further detail.
2293 */
796f4687 2294 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2295 break;
2b036c6b
BO		 2296 case MSR_AMD64_OSVW_ID_LENGTH:
2297 if (!guest_cpuid_has_osvw(vcpu))
2298 return 1;
2299 vcpu->arch.osvw.length = data;
2300 break;
2301 case MSR_AMD64_OSVW_STATUS:
2302 if (!guest_cpuid_has_osvw(vcpu))
2303 return 1;
2304 vcpu->arch.osvw.status = data;
2305 break;
db2336a8
KH		 2306 case MSR_PLATFORM_INFO:
2307 if (!msr_info->host_initiated ||
2308 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2309 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2310 cpuid_fault_enabled(vcpu)))
2311 return 1;
2312 vcpu->arch.msr_platform_info = data;
2313 break;
2314 case MSR_MISC_FEATURES_ENABLES:
2315 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2316 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2317 !supports_cpuid_fault(vcpu)))
2318 return 1;
2319 vcpu->arch.msr_misc_features_enables = data;
2320 break;
15c4a640 2321 default:
ffde22ac
ES		 2322 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2323 return xen_hvm_config(vcpu, data);
c6702c9d 2324 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2325 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2326 if (!ignore_msrs) {
ae0f5499 2327 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2328 msr, data);
ed85c068
AP		 2329 return 1;
2330 } else {
796f4687 2331 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2332 msr, data);
ed85c068
AP		 2333 break;
2334 }
15c4a640
CO		 2335 }
2336 return 0;
2337}
2338EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2339
2340
2341/*
2342 * Reads an msr value (of 'msr_index') into 'pdata'.
2343 * Returns 0 on success, non-0 otherwise.
2344 * Assumes vcpu_load() was already called.
2345 */
609e36d3 2346int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2347{
609e36d3 2348 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2349}
ff651cb6 2350EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2351
890ca9ae 2352static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2353{
2354 u64 data;
890ca9ae
HY		 2355 u64 mcg_cap = vcpu->arch.mcg_cap;
2356 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2357
2358 switch (msr) {
15c4a640
CO		 2359 case MSR_IA32_P5_MC_ADDR:
2360 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2361 data = 0;
2362 break;
15c4a640 2363 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2364 data = vcpu->arch.mcg_cap;
2365 break;
c7ac679c 2366 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2367 if (!(mcg_cap & MCG_CTL_P))
2368 return 1;
2369 data = vcpu->arch.mcg_ctl;
2370 break;
2371 case MSR_IA32_MCG_STATUS:
2372 data = vcpu->arch.mcg_status;
2373 break;
2374 default:
2375 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2376 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2377 u32 offset = msr - MSR_IA32_MC0_CTL;
2378 data = vcpu->arch.mce_banks[offset];
2379 break;
2380 }
2381 return 1;
2382 }
2383 *pdata = data;
2384 return 0;
2385}
2386
609e36d3 2387int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2388{
609e36d3 2389 switch (msr_info->index) {
890ca9ae 2390 case MSR_IA32_PLATFORM_ID:
15c4a640 2391 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2392 case MSR_IA32_DEBUGCTLMSR:
2393 case MSR_IA32_LASTBRANCHFROMIP:
2394 case MSR_IA32_LASTBRANCHTOIP:
2395 case MSR_IA32_LASTINTFROMIP:
2396 case MSR_IA32_LASTINTTOIP:
60af2ecd 2397 case MSR_K8_SYSCFG:
3afb1121
PB		 2398 case MSR_K8_TSEG_ADDR:
2399 case MSR_K8_TSEG_MASK:
60af2ecd 2400 case MSR_K7_HWCR:
61a6bd67 2401 case MSR_VM_HSAVE_PA:
1fdbd48c 2402 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2403 case MSR_AMD64_NB_CFG:
f7c6d140 2404 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2405 case MSR_AMD64_BU_CFG2:
0c2df2a1 2406 case MSR_IA32_PERF_CTL:
405a353a 2407 case MSR_AMD64_DC_CFG:
609e36d3 2408 msr_info->data = 0;
15c4a640 2409 break;
6912ac32
WH		 2410 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2411 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2412 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2413 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2414 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2415 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2416 msr_info->data = 0;
5753785f 2417 break;
742bc670 2418 case MSR_IA32_UCODE_REV:
609e36d3 2419 msr_info->data = 0x100000000ULL;
742bc670 2420 break;
9ba075a6 2421 case MSR_MTRRcap:
9ba075a6 2422 case 0x200 ... 0x2ff:
ff53604b 2423 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2424 case 0xcd: /* fsb frequency */
609e36d3 2425 msr_info->data = 3;
15c4a640 2426 break;
7b914098
JS		 2427 /*
2428 * MSR_EBC_FREQUENCY_ID
2429 * Conservative value valid for even the basic CPU models.
2430 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2431 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2432 * and 266MHz for model 3, or 4. Set Core Clock
2433 * Frequency to System Bus Frequency Ratio to 1 (bits
2434 * 31:24) even though these are only valid for CPU
2435 * models > 2, however guests may end up dividing or
2436 * multiplying by zero otherwise.
2437 */
2438 case MSR_EBC_FREQUENCY_ID:
609e36d3 2439 msr_info->data = 1 << 24;
7b914098 2440 break;
15c4a640 2441 case MSR_IA32_APICBASE:
609e36d3 2442 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2443 break;
0105d1a5 2444 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2445 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2446 break;
a3e06bbe 2447 case MSR_IA32_TSCDEADLINE:
609e36d3 2448 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2449 break;
ba904635 2450 case MSR_IA32_TSC_ADJUST:
609e36d3 2451 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2452 break;
15c4a640 2453 case MSR_IA32_MISC_ENABLE:
609e36d3 2454 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2455 break;
64d60670
PB		 2456 case MSR_IA32_SMBASE:
2457 if (!msr_info->host_initiated)
2458 return 1;
2459 msr_info->data = vcpu->arch.smbase;
15c4a640 2460 break;
847f0ad8
AG		 2461 case MSR_IA32_PERF_STATUS:
2462 /* TSC increment by tick */
609e36d3 2463 msr_info->data = 1000ULL;
847f0ad8 2464 /* CPU multiplier */
b0996ae4 2465 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2466 break;
15c4a640 2467 case MSR_EFER:
609e36d3 2468 msr_info->data = vcpu->arch.efer;
15c4a640 2469 break;
18068523 2470 case MSR_KVM_WALL_CLOCK:
11c6bffa 2471 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2472 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2473 break;
2474 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2475 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2476 msr_info->data = vcpu->arch.time;
18068523 2477 break;
344d9588 2478 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2479 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2480 break;
c9aaa895 2481 case MSR_KVM_STEAL_TIME:
609e36d3 2482 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2483 break;
1d92128f 2484 case MSR_KVM_PV_EOI_EN:
609e36d3 2485 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2486 break;
890ca9ae
HY		 2487 case MSR_IA32_P5_MC_ADDR:
2488 case MSR_IA32_P5_MC_TYPE:
2489 case MSR_IA32_MCG_CAP:
2490 case MSR_IA32_MCG_CTL:
2491 case MSR_IA32_MCG_STATUS:
81760dcc 2492 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2493 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2494 case MSR_K7_CLK_CTL:
2495 /*
2496 * Provide expected ramp-up count for K7. All other
2497 * are set to zero, indicating minimum divisors for
2498 * every field.
2499 *
2500 * This prevents guest kernels on AMD host with CPU
2501 * type 6, model 8 and higher from exploding due to
2502 * the rdmsr failing.
2503 */
609e36d3 2504 msr_info->data = 0x20000000;
84e0cefa 2505 break;
55cd8e5a 2506 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2507 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2508 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2509 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2510 return kvm_hv_get_msr_common(vcpu,
2511 msr_info->index, &msr_info->data);
55cd8e5a 2512 break;
91c9c3ed 2513 case MSR_IA32_BBL_CR_CTL3:
2514 /* This legacy MSR exists but isn't fully documented in current
2515 * silicon. It is however accessed by winxp in very narrow
2516 * scenarios where it sets bit #19, itself documented as
2517 * a "reserved" bit. Best effort attempt to source coherent
2518 * read data here should the balance of the register be
2519 * interpreted by the guest:
2520 *
2521 * L2 cache control register 3: 64GB range, 256KB size,
2522 * enabled, latency 0x1, configured
2523 */
609e36d3 2524 msr_info->data = 0xbe702111;
91c9c3ed 2525 break;
2b036c6b
BO		 2526 case MSR_AMD64_OSVW_ID_LENGTH:
2527 if (!guest_cpuid_has_osvw(vcpu))
2528 return 1;
609e36d3 2529 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2530 break;
2531 case MSR_AMD64_OSVW_STATUS:
2532 if (!guest_cpuid_has_osvw(vcpu))
2533 return 1;
609e36d3 2534 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2535 break;
db2336a8
KH		 2536 case MSR_PLATFORM_INFO:
2537 msr_info->data = vcpu->arch.msr_platform_info;
2538 break;
2539 case MSR_MISC_FEATURES_ENABLES:
2540 msr_info->data = vcpu->arch.msr_misc_features_enables;
2541 break;
15c4a640 2542 default:
c6702c9d 2543 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2544 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2545 if (!ignore_msrs) {
ae0f5499
BD		 2546 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2547 msr_info->index);
ed85c068
AP		 2548 return 1;
2549 } else {
609e36d3
PB		 2550 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2551 msr_info->data = 0;
ed85c068
AP		 2552 }
2553 break;
15c4a640 2554 }
15c4a640
CO		 2555 return 0;
2556}
2557EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2558
313a3dc7
CO		 2559/*
2560 * Read or write a bunch of msrs. All parameters are kernel addresses.
2561 *
2562 * @return number of msrs set successfully.
2563 */
2564static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2565 struct kvm_msr_entry *entries,
2566 int (*do_msr)(struct kvm_vcpu *vcpu,
2567 unsigned index, u64 *data))
2568{
f656ce01 2569 int i, idx;
313a3dc7 2570
f656ce01 2571 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2572 for (i = 0; i < msrs->nmsrs; ++i)
2573 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2574 break;
f656ce01 2575 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2576
313a3dc7
CO		 2577 return i;
2578}
2579
2580/*
2581 * Read or write a bunch of msrs. Parameters are user addresses.
2582 *
2583 * @return number of msrs set successfully.
2584 */
2585static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2586 int (*do_msr)(struct kvm_vcpu *vcpu,
2587 unsigned index, u64 *data),
2588 int writeback)
2589{
2590 struct kvm_msrs msrs;
2591 struct kvm_msr_entry *entries;
2592 int r, n;
2593 unsigned size;
2594
2595 r = -EFAULT;
2596 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2597 goto out;
2598
2599 r = -E2BIG;
2600 if (msrs.nmsrs >= MAX_IO_MSRS)
2601 goto out;
2602
313a3dc7 2603 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2604 entries = memdup_user(user_msrs->entries, size);
2605 if (IS_ERR(entries)) {
2606 r = PTR_ERR(entries);
313a3dc7 2607 goto out;
ff5c2c03 2608 }
313a3dc7
CO		 2609
2610 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2611 if (r < 0)
2612 goto out_free;
2613
2614 r = -EFAULT;
2615 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2616 goto out_free;
2617
2618 r = n;
2619
2620out_free:
7a73c028 2621 kfree(entries);
313a3dc7
CO		 2622out:
2623 return r;
2624}
2625
784aa3d7 2626int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2627{
2628 int r;
2629
2630 switch (ext) {
2631 case KVM_CAP_IRQCHIP:
2632 case KVM_CAP_HLT:
2633 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2634 case KVM_CAP_SET_TSS_ADDR:
07716717 2635 case KVM_CAP_EXT_CPUID:
9c15bb1d 2636 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2637 case KVM_CAP_CLOCKSOURCE:
7837699f 2638 case KVM_CAP_PIT:
a28e4f5a 2639 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2640 case KVM_CAP_MP_STATE:
ed848624 2641 case KVM_CAP_SYNC_MMU:
a355c85c 2642 case KVM_CAP_USER_NMI:
52d939a0 2643 case KVM_CAP_REINJECT_CONTROL:
4925663a 2644 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2645 case KVM_CAP_IOEVENTFD:
f848a5a8 2646 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2647 case KVM_CAP_PIT2:
e9f42757 2648 case KVM_CAP_PIT_STATE2:
b927a3ce 2649 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2650 case KVM_CAP_XEN_HVM:
3cfc3092 2651 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2652 case KVM_CAP_HYPERV:
10388a07 2653 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2654 case KVM_CAP_HYPERV_SPIN:
5c919412 2655 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2656 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2657 case KVM_CAP_DEBUGREGS:
d2be1651 2658 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2659 case KVM_CAP_XSAVE:
344d9588 2660 case KVM_CAP_ASYNC_PF:
92a1f12d 2661 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2662 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2663 case KVM_CAP_READONLY_MEM:
5f66b620 2664 case KVM_CAP_HYPERV_TIME:
100943c5 2665 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2666 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2667 case KVM_CAP_ENABLE_CAP_VM:
2668 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2669 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2670 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2671 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2672 r = 1;
2673 break;
e3fd9a93
PB		 2674 case KVM_CAP_ADJUST_CLOCK:
2675 r = KVM_CLOCK_TSC_STABLE;
2676 break;
668fffa3
MT		 2677 case KVM_CAP_X86_GUEST_MWAIT:
2678 r = kvm_mwait_in_guest();
2679 break;
6d396b55
PB		 2680 case KVM_CAP_X86_SMM:
2681 /* SMBASE is usually relocated above 1M on modern chipsets,
2682 * and SMM handlers might indeed rely on 4G segment limits,
2683 * so do not report SMM to be available if real mode is
2684 * emulated via vm86 mode. Still, do not go to great lengths
2685 * to avoid userspace's usage of the feature, because it is a
2686 * fringe case that is not enabled except via specific settings
2687 * of the module parameters.
2688 */
2689 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2690 break;
774ead3a
AK		 2691 case KVM_CAP_VAPIC:
2692 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2693 break;
f725230a 2694 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2695 r = KVM_SOFT_MAX_VCPUS;
2696 break;
2697 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2698 r = KVM_MAX_VCPUS;
2699 break;
a988b910 2700 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2701 r = KVM_USER_MEM_SLOTS;
a988b910 2702 break;
a68a6a72
MT		 2703 case KVM_CAP_PV_MMU: /* obsolete */
2704 r = 0;
2f333bcb 2705 break;
890ca9ae
HY		 2706 case KVM_CAP_MCE:
2707 r = KVM_MAX_MCE_BANKS;
2708 break;
2d5b5a66 2709 case KVM_CAP_XCRS:
d366bf7e 2710 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2711 break;
92a1f12d
JR		 2712 case KVM_CAP_TSC_CONTROL:
2713 r = kvm_has_tsc_control;
2714 break;
37131313
RK		 2715 case KVM_CAP_X2APIC_API:
2716 r = KVM_X2APIC_API_VALID_FLAGS;
2717 break;
018d00d2
ZX		 2718 default:
2719 r = 0;
2720 break;
2721 }
2722 return r;
2723
2724}
2725
043405e1
CO		 2726long kvm_arch_dev_ioctl(struct file *filp,
2727 unsigned int ioctl, unsigned long arg)
2728{
2729 void __user *argp = (void __user *)arg;
2730 long r;
2731
2732 switch (ioctl) {
2733 case KVM_GET_MSR_INDEX_LIST: {
2734 struct kvm_msr_list __user *user_msr_list = argp;
2735 struct kvm_msr_list msr_list;
2736 unsigned n;
2737
2738 r = -EFAULT;
2739 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2740 goto out;
2741 n = msr_list.nmsrs;
62ef68bb 2742 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2743 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2744 goto out;
2745 r = -E2BIG;
e125e7b6 2746 if (n < msr_list.nmsrs)
043405e1
CO		 2747 goto out;
2748 r = -EFAULT;
2749 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2750 num_msrs_to_save * sizeof(u32)))
2751 goto out;
e125e7b6 2752 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2753 &emulated_msrs,
62ef68bb 2754 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2755 goto out;
2756 r = 0;
2757 break;
2758 }
9c15bb1d
BP		 2759 case KVM_GET_SUPPORTED_CPUID:
2760 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2761 struct kvm_cpuid2 __user *cpuid_arg = argp;
2762 struct kvm_cpuid2 cpuid;
2763
2764 r = -EFAULT;
2765 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2766 goto out;
9c15bb1d
BP		 2767
2768 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2769 ioctl);
674eea0f
AK		 2770 if (r)
2771 goto out;
2772
2773 r = -EFAULT;
2774 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2775 goto out;
2776 r = 0;
2777 break;
2778 }
890ca9ae 2779 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2780 r = -EFAULT;
c45dcc71
AR		 2781 if (copy_to_user(argp, &kvm_mce_cap_supported,
2782 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2783 goto out;
2784 r = 0;
2785 break;
2786 }
043405e1
CO		 2787 default:
2788 r = -EINVAL;
2789 }
2790out:
2791 return r;
2792}
2793
f5f48ee1
SY		 2794static void wbinvd_ipi(void *garbage)
2795{
2796 wbinvd();
2797}
2798
2799static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2800{
e0f0bbc5 2801 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2802}
2803
313a3dc7
CO		 2804void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2805{
f5f48ee1
SY		 2806 /* Address WBINVD may be executed by guest */
2807 if (need_emulate_wbinvd(vcpu)) {
2808 if (kvm_x86_ops->has_wbinvd_exit())
2809 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2810 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2811 smp_call_function_single(vcpu->cpu,
2812 wbinvd_ipi, NULL, 1);
2813 }
2814
313a3dc7 2815 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2816
0dd6a6ed
ZA		 2817 /* Apply any externally detected TSC adjustments (due to suspend) */
2818 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2819 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2820 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2821 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2822 }
8f6055cb 2823
48434c20 2824 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2825 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2826 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2827 if (tsc_delta < 0)
2828 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2829
c285545f 2830 if (check_tsc_unstable()) {
07c1419a 2831 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2832 vcpu->arch.last_guest_tsc);
a545ab6a 2833 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2834 vcpu->arch.tsc_catchup = 1;
c285545f 2835 }
e12c8f36
WL		 2836 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2837 kvm_x86_ops->set_hv_timer(vcpu,
498f8162 2838 kvm_get_lapic_target_expiration_tsc(vcpu)))
e12c8f36 2839 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2840 /*
2841 * On a host with synchronized TSC, there is no need to update
2842 * kvmclock on vcpu->cpu migration
2843 */
2844 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2845 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2846 if (vcpu->cpu != cpu)
1bd2009e 2847 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2848 vcpu->cpu = cpu;
6b7d7e76 2849 }
c9aaa895 2850
c9aaa895 2851 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2852}
2853
0b9f6c46
PX		 2854static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2855{
2856 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2857 return;
2858
2859 vcpu->arch.st.steal.preempted = 1;
2860
bbd64115 2861 kvm_vcpu_write_guest_offset_cached(vcpu, &vcpu->arch.st.stime,
0b9f6c46
PX		 2862 &vcpu->arch.st.steal.preempted,
2863 offsetof(struct kvm_steal_time, preempted),
2864 sizeof(vcpu->arch.st.steal.preempted));
2865}
2866
313a3dc7
CO		 2867void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2868{
cc0d907c 2869 int idx;
931f261b
AA		 2870 /*
2871 * Disable page faults because we're in atomic context here.
2872 * kvm_write_guest_offset_cached() would call might_fault()
2873 * that relies on pagefault_disable() to tell if there's a
2874 * bug. NOTE: the write to guest memory may not go through if
2875 * during postcopy live migration or if there's heavy guest
2876 * paging.
2877 */
2878 pagefault_disable();
cc0d907c
AA		 2879 /*
2880 * kvm_memslots() will be called by
2881 * kvm_write_guest_offset_cached() so take the srcu lock.
2882 */
2883 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2884 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2885 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2886 pagefault_enable();
02daab21 2887 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2888 kvm_put_guest_fpu(vcpu);
4ea1636b 2889 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2890}
2891
313a3dc7
CO		 2892static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2893 struct kvm_lapic_state *s)
2894{
76dfafd5 2895 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2896 kvm_x86_ops->sync_pir_to_irr(vcpu);
2897
a92e2543 2898 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2899}
2900
2901static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2902 struct kvm_lapic_state *s)
2903{
a92e2543
RK		 2904 int r;
2905
2906 r = kvm_apic_set_state(vcpu, s);
2907 if (r)
2908 return r;
cb142eb7 2909 update_cr8_intercept(vcpu);
313a3dc7
CO		 2910
2911 return 0;
2912}
2913
127a457a
MG		 2914static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2915{
2916 return (!lapic_in_kernel(vcpu) ||
2917 kvm_apic_accept_pic_intr(vcpu));
2918}
2919
782d422b
MG		 2920/*
2921 * if userspace requested an interrupt window, check that the
2922 * interrupt window is open.
2923 *
2924 * No need to exit to userspace if we already have an interrupt queued.
2925 */
2926static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2927{
2928 return kvm_arch_interrupt_allowed(vcpu) &&
2929 !kvm_cpu_has_interrupt(vcpu) &&
2930 !kvm_event_needs_reinjection(vcpu) &&
2931 kvm_cpu_accept_dm_intr(vcpu);
2932}
2933
f77bc6a4
ZX		 2934static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2935 struct kvm_interrupt *irq)
2936{
02cdb50f 2937 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2938 return -EINVAL;
1c1a9ce9
SR		 2939
2940 if (!irqchip_in_kernel(vcpu->kvm)) {
2941 kvm_queue_interrupt(vcpu, irq->irq, false);
2942 kvm_make_request(KVM_REQ_EVENT, vcpu);
2943 return 0;
2944 }
2945
2946 /*
2947 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2948 * fail for in-kernel 8259.
2949 */
2950 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2951 return -ENXIO;
f77bc6a4 2952
1c1a9ce9
SR		 2953 if (vcpu->arch.pending_external_vector != -1)
2954 return -EEXIST;
f77bc6a4 2955
1c1a9ce9 2956 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2957 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2958 return 0;
2959}
2960
c4abb7c9
JK		 2961static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2962{
c4abb7c9 2963 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2964
2965 return 0;
2966}
2967
f077825a
PB		 2968static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2969{
64d60670
PB		 2970 kvm_make_request(KVM_REQ_SMI, vcpu);
2971
f077825a
PB		 2972 return 0;
2973}
2974
b209749f
AK		 2975static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2976 struct kvm_tpr_access_ctl *tac)
2977{
2978 if (tac->flags)
2979 return -EINVAL;
2980 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2981 return 0;
2982}
2983
890ca9ae
HY		 2984static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2985 u64 mcg_cap)
2986{
2987 int r;
2988 unsigned bank_num = mcg_cap & 0xff, bank;
2989
2990 r = -EINVAL;
a9e38c3e 2991 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2992 goto out;
c45dcc71 2993 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2994 goto out;
2995 r = 0;
2996 vcpu->arch.mcg_cap = mcg_cap;
2997 /* Init IA32_MCG_CTL to all 1s */
2998 if (mcg_cap & MCG_CTL_P)
2999 vcpu->arch.mcg_ctl = ~(u64)0;
3000 /* Init IA32_MCi_CTL to all 1s */
3001 for (bank = 0; bank < bank_num; bank++)
3002 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3003
3004 if (kvm_x86_ops->setup_mce)
3005 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3006out:
3007 return r;
3008}
3009
3010static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3011 struct kvm_x86_mce *mce)
3012{
3013 u64 mcg_cap = vcpu->arch.mcg_cap;
3014 unsigned bank_num = mcg_cap & 0xff;
3015 u64 *banks = vcpu->arch.mce_banks;
3016
3017 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3018 return -EINVAL;
3019 /*
3020 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3021 * reporting is disabled
3022 */
3023 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3024 vcpu->arch.mcg_ctl != ~(u64)0)
3025 return 0;
3026 banks += 4 * mce->bank;
3027 /*
3028 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3029 * reporting is disabled for the bank
3030 */
3031 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3032 return 0;
3033 if (mce->status & MCI_STATUS_UC) {
3034 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3035 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3036 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3037 return 0;
3038 }
3039 if (banks[1] & MCI_STATUS_VAL)
3040 mce->status |= MCI_STATUS_OVER;
3041 banks[2] = mce->addr;
3042 banks[3] = mce->misc;
3043 vcpu->arch.mcg_status = mce->mcg_status;
3044 banks[1] = mce->status;
3045 kvm_queue_exception(vcpu, MC_VECTOR);
3046 } else if (!(banks[1] & MCI_STATUS_VAL)
3047 || !(banks[1] & MCI_STATUS_UC)) {
3048 if (banks[1] & MCI_STATUS_VAL)
3049 mce->status |= MCI_STATUS_OVER;
3050 banks[2] = mce->addr;
3051 banks[3] = mce->misc;
3052 banks[1] = mce->status;
3053 } else
3054 banks[1] |= MCI_STATUS_OVER;
3055 return 0;
3056}
3057
3cfc3092
JK		 3058static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3059 struct kvm_vcpu_events *events)
3060{
7460fb4a 3061 process_nmi(vcpu);
03b82a30
JK		 3062 events->exception.injected =
3063 vcpu->arch.exception.pending &&
3064 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3065 events->exception.nr = vcpu->arch.exception.nr;
3066 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3067 events->exception.pad = 0;
3cfc3092
JK		 3068 events->exception.error_code = vcpu->arch.exception.error_code;
3069
03b82a30
JK		 3070 events->interrupt.injected =
3071 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3072 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3073 events->interrupt.soft = 0;
37ccdcbe 3074 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3075
3076 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3077 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3078 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3079 events->nmi.pad = 0;
3cfc3092 3080
66450a21 3081 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3082
f077825a
PB		 3083 events->smi.smm = is_smm(vcpu);
3084 events->smi.pending = vcpu->arch.smi_pending;
3085 events->smi.smm_inside_nmi =
3086 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3087 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3088
dab4b911 3089 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3090 | KVM_VCPUEVENT_VALID_SHADOW
3091 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3092 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3093}
3094
6ef4e07e
XG		 3095static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3096
3cfc3092
JK		 3097static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3098 struct kvm_vcpu_events *events)
3099{
dab4b911 3100 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3101 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3102 | KVM_VCPUEVENT_VALID_SHADOW
3103 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3104 return -EINVAL;
3105
78e546c8 3106 if (events->exception.injected &&
28d06353
JM		 3107 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3108 is_guest_mode(vcpu)))
78e546c8
PB		 3109 return -EINVAL;
3110
28bf2888
DH		 3111 /* INITs are latched while in SMM */
3112 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3113 (events->smi.smm || events->smi.pending) &&
3114 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3115 return -EINVAL;
3116
7460fb4a 3117 process_nmi(vcpu);
3cfc3092
JK		 3118 vcpu->arch.exception.pending = events->exception.injected;
3119 vcpu->arch.exception.nr = events->exception.nr;
3120 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3121 vcpu->arch.exception.error_code = events->exception.error_code;
3122
3123 vcpu->arch.interrupt.pending = events->interrupt.injected;
3124 vcpu->arch.interrupt.nr = events->interrupt.nr;
3125 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3126 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3127 kvm_x86_ops->set_interrupt_shadow(vcpu,
3128 events->interrupt.shadow);
3cfc3092
JK		 3129
3130 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3131 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3132 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3133 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3134
66450a21 3135 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3136 lapic_in_kernel(vcpu))
66450a21 3137 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3138
f077825a 3139 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3140 u32 hflags = vcpu->arch.hflags;
f077825a 3141 if (events->smi.smm)
6ef4e07e 3142 hflags |= HF_SMM_MASK;
f077825a 3143 else
6ef4e07e
XG		 3144 hflags &= ~HF_SMM_MASK;
3145 kvm_set_hflags(vcpu, hflags);
3146
f077825a
PB		 3147 vcpu->arch.smi_pending = events->smi.pending;
3148 if (events->smi.smm_inside_nmi)
3149 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3150 else
3151 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3152 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3153 if (events->smi.latched_init)
3154 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3155 else
3156 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3157 }
3158 }
3159
3842d135
AK		 3160 kvm_make_request(KVM_REQ_EVENT, vcpu);
3161
3cfc3092
JK		 3162 return 0;
3163}
3164
a1efbe77
JK		 3165static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3166 struct kvm_debugregs *dbgregs)
3167{
73aaf249
JK		 3168 unsigned long val;
3169
a1efbe77 3170 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3171 kvm_get_dr(vcpu, 6, &val);
73aaf249 3172 dbgregs->dr6 = val;
a1efbe77
JK		 3173 dbgregs->dr7 = vcpu->arch.dr7;
3174 dbgregs->flags = 0;
97e69aa6 3175 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3176}
3177
3178static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3179 struct kvm_debugregs *dbgregs)
3180{
3181 if (dbgregs->flags)
3182 return -EINVAL;
3183
d14bdb55
PB		 3184 if (dbgregs->dr6 & ~0xffffffffull)
3185 return -EINVAL;
3186 if (dbgregs->dr7 & ~0xffffffffull)
3187 return -EINVAL;
3188
a1efbe77 3189 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3190 kvm_update_dr0123(vcpu);
a1efbe77 3191 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3192 kvm_update_dr6(vcpu);
a1efbe77 3193 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3194 kvm_update_dr7(vcpu);
a1efbe77 3195
a1efbe77
JK		 3196 return 0;
3197}
3198
df1daba7
PB		 3199#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3200
3201static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3202{
c47ada30 3203 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3204 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3205 u64 valid;
3206
3207 /*
3208 * Copy legacy XSAVE area, to avoid complications with CPUID
3209 * leaves 0 and 1 in the loop below.
3210 */
3211 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3212
3213 /* Set XSTATE_BV */
00c87e9a 3214 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3215 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3216
3217 /*
3218 * Copy each region from the possibly compacted offset to the
3219 * non-compacted offset.
3220 */
d91cab78 3221 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3222 while (valid) {
3223 u64 feature = valid & -valid;
3224 int index = fls64(feature) - 1;
3225 void *src = get_xsave_addr(xsave, feature);
3226
3227 if (src) {
3228 u32 size, offset, ecx, edx;
3229 cpuid_count(XSTATE_CPUID, index,
3230 &size, &offset, &ecx, &edx);
3231 memcpy(dest + offset, src, size);
3232 }
3233
3234 valid -= feature;
3235 }
3236}
3237
3238static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3239{
c47ada30 3240 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3241 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3242 u64 valid;
3243
3244 /*
3245 * Copy legacy XSAVE area, to avoid complications with CPUID
3246 * leaves 0 and 1 in the loop below.
3247 */
3248 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3249
3250 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3251 xsave->header.xfeatures = xstate_bv;
782511b0 3252 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3253 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3254
3255 /*
3256 * Copy each region from the non-compacted offset to the
3257 * possibly compacted offset.
3258 */
d91cab78 3259 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3260 while (valid) {
3261 u64 feature = valid & -valid;
3262 int index = fls64(feature) - 1;
3263 void *dest = get_xsave_addr(xsave, feature);
3264
3265 if (dest) {
3266 u32 size, offset, ecx, edx;
3267 cpuid_count(XSTATE_CPUID, index,
3268 &size, &offset, &ecx, &edx);
3269 memcpy(dest, src + offset, size);
ee4100da 3270 }
df1daba7
PB		 3271
3272 valid -= feature;
3273 }
3274}
3275
2d5b5a66
SY		 3276static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3277 struct kvm_xsave *guest_xsave)
3278{
d366bf7e 3279 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3280 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3281 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3282 } else {
2d5b5a66 3283 memcpy(guest_xsave->region,
7366ed77 3284 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3285 sizeof(struct fxregs_state));
2d5b5a66 3286 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3287 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3288 }
3289}
3290
3291static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3292 struct kvm_xsave *guest_xsave)
3293{
3294 u64 xstate_bv =
3295 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3296
d366bf7e 3297 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3298 /*
3299 * Here we allow setting states that are not present in
3300 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3301 * with old userspace.
3302 */
4ff41732 3303 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3304 return -EINVAL;
df1daba7 3305 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3306 } else {
d91cab78 3307 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3308 return -EINVAL;
7366ed77 3309 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3310 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3311 }
3312 return 0;
3313}
3314
3315static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3316 struct kvm_xcrs *guest_xcrs)
3317{
d366bf7e 3318 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3319 guest_xcrs->nr_xcrs = 0;
3320 return;
3321 }
3322
3323 guest_xcrs->nr_xcrs = 1;
3324 guest_xcrs->flags = 0;
3325 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3326 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3327}
3328
3329static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3330 struct kvm_xcrs *guest_xcrs)
3331{
3332 int i, r = 0;
3333
d366bf7e 3334 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3335 return -EINVAL;
3336
3337 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3338 return -EINVAL;
3339
3340 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3341 /* Only support XCR0 currently */
c67a04cb 3342 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3343 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3344 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3345 break;
3346 }
3347 if (r)
3348 r = -EINVAL;
3349 return r;
3350}
3351
1c0b28c2
EM		 3352/*
3353 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3354 * stopped by the hypervisor. This function will be called from the host only.
3355 * EINVAL is returned when the host attempts to set the flag for a guest that
3356 * does not support pv clocks.
3357 */
3358static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3359{
0b79459b 3360 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3361 return -EINVAL;
51d59c6b 3362 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3363 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3364 return 0;
3365}
3366
5c919412
AS		 3367static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3368 struct kvm_enable_cap *cap)
3369{
3370 if (cap->flags)
3371 return -EINVAL;
3372
3373 switch (cap->cap) {
3374 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3375 if (!irqchip_in_kernel(vcpu->kvm))
3376 return -EINVAL;
5c919412
AS		 3377 return kvm_hv_activate_synic(vcpu);
3378 default:
3379 return -EINVAL;
3380 }
3381}
3382
313a3dc7
CO		 3383long kvm_arch_vcpu_ioctl(struct file *filp,
3384 unsigned int ioctl, unsigned long arg)
3385{
3386 struct kvm_vcpu *vcpu = filp->private_data;
3387 void __user *argp = (void __user *)arg;
3388 int r;
d1ac91d8
AK		 3389 union {
3390 struct kvm_lapic_state *lapic;
3391 struct kvm_xsave *xsave;
3392 struct kvm_xcrs *xcrs;
3393 void *buffer;
3394 } u;
3395
3396 u.buffer = NULL;
313a3dc7
CO		 3397 switch (ioctl) {
3398 case KVM_GET_LAPIC: {
2204ae3c 3399 r = -EINVAL;
bce87cce 3400 if (!lapic_in_kernel(vcpu))
2204ae3c 3401 goto out;
d1ac91d8 3402 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3403
b772ff36 3404 r = -ENOMEM;
d1ac91d8 3405 if (!u.lapic)
b772ff36 3406 goto out;
d1ac91d8 3407 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3408 if (r)
3409 goto out;
3410 r = -EFAULT;
d1ac91d8 3411 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3412 goto out;
3413 r = 0;
3414 break;
3415 }
3416 case KVM_SET_LAPIC: {
2204ae3c 3417 r = -EINVAL;
bce87cce 3418 if (!lapic_in_kernel(vcpu))
2204ae3c 3419 goto out;
ff5c2c03 3420 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3421 if (IS_ERR(u.lapic))
3422 return PTR_ERR(u.lapic);
ff5c2c03 3423
d1ac91d8 3424 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3425 break;
3426 }
f77bc6a4
ZX		 3427 case KVM_INTERRUPT: {
3428 struct kvm_interrupt irq;
3429
3430 r = -EFAULT;
3431 if (copy_from_user(&irq, argp, sizeof irq))
3432 goto out;
3433 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3434 break;
3435 }
c4abb7c9
JK		 3436 case KVM_NMI: {
3437 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3438 break;
3439 }
f077825a
PB		 3440 case KVM_SMI: {
3441 r = kvm_vcpu_ioctl_smi(vcpu);
3442 break;
3443 }
313a3dc7
CO		 3444 case KVM_SET_CPUID: {
3445 struct kvm_cpuid __user *cpuid_arg = argp;
3446 struct kvm_cpuid cpuid;
3447
3448 r = -EFAULT;
3449 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3450 goto out;
3451 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3452 break;
3453 }
07716717
DK		 3454 case KVM_SET_CPUID2: {
3455 struct kvm_cpuid2 __user *cpuid_arg = argp;
3456 struct kvm_cpuid2 cpuid;
3457
3458 r = -EFAULT;
3459 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3460 goto out;
3461 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3462 cpuid_arg->entries);
07716717
DK		 3463 break;
3464 }
3465 case KVM_GET_CPUID2: {
3466 struct kvm_cpuid2 __user *cpuid_arg = argp;
3467 struct kvm_cpuid2 cpuid;
3468
3469 r = -EFAULT;
3470 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3471 goto out;
3472 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3473 cpuid_arg->entries);
07716717
DK		 3474 if (r)
3475 goto out;
3476 r = -EFAULT;
3477 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3478 goto out;
3479 r = 0;
3480 break;
3481 }
313a3dc7 3482 case KVM_GET_MSRS:
609e36d3 3483 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3484 break;
3485 case KVM_SET_MSRS:
3486 r = msr_io(vcpu, argp, do_set_msr, 0);
3487 break;
b209749f
AK		 3488 case KVM_TPR_ACCESS_REPORTING: {
3489 struct kvm_tpr_access_ctl tac;
3490
3491 r = -EFAULT;
3492 if (copy_from_user(&tac, argp, sizeof tac))
3493 goto out;
3494 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3495 if (r)
3496 goto out;
3497 r = -EFAULT;
3498 if (copy_to_user(argp, &tac, sizeof tac))
3499 goto out;
3500 r = 0;
3501 break;
3502 };
b93463aa
AK		 3503 case KVM_SET_VAPIC_ADDR: {
3504 struct kvm_vapic_addr va;
7301d6ab 3505 int idx;
b93463aa
AK		 3506
3507 r = -EINVAL;
35754c98 3508 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3509 goto out;
3510 r = -EFAULT;
3511 if (copy_from_user(&va, argp, sizeof va))
3512 goto out;
7301d6ab 3513 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3514 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3515 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3516 break;
3517 }
890ca9ae
HY		 3518 case KVM_X86_SETUP_MCE: {
3519 u64 mcg_cap;
3520
3521 r = -EFAULT;
3522 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3523 goto out;
3524 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3525 break;
3526 }
3527 case KVM_X86_SET_MCE: {
3528 struct kvm_x86_mce mce;
3529
3530 r = -EFAULT;
3531 if (copy_from_user(&mce, argp, sizeof mce))
3532 goto out;
3533 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3534 break;
3535 }
3cfc3092
JK		 3536 case KVM_GET_VCPU_EVENTS: {
3537 struct kvm_vcpu_events events;
3538
3539 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3540
3541 r = -EFAULT;
3542 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3543 break;
3544 r = 0;
3545 break;
3546 }
3547 case KVM_SET_VCPU_EVENTS: {
3548 struct kvm_vcpu_events events;
3549
3550 r = -EFAULT;
3551 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3552 break;
3553
3554 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3555 break;
3556 }
a1efbe77
JK		 3557 case KVM_GET_DEBUGREGS: {
3558 struct kvm_debugregs dbgregs;
3559
3560 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3561
3562 r = -EFAULT;
3563 if (copy_to_user(argp, &dbgregs,
3564 sizeof(struct kvm_debugregs)))
3565 break;
3566 r = 0;
3567 break;
3568 }
3569 case KVM_SET_DEBUGREGS: {
3570 struct kvm_debugregs dbgregs;
3571
3572 r = -EFAULT;
3573 if (copy_from_user(&dbgregs, argp,
3574 sizeof(struct kvm_debugregs)))
3575 break;
3576
3577 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3578 break;
3579 }
2d5b5a66 3580 case KVM_GET_XSAVE: {
d1ac91d8 3581 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3582 r = -ENOMEM;
d1ac91d8 3583 if (!u.xsave)
2d5b5a66
SY		 3584 break;
3585
d1ac91d8 3586 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3587
3588 r = -EFAULT;
d1ac91d8 3589 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3590 break;
3591 r = 0;
3592 break;
3593 }
3594 case KVM_SET_XSAVE: {
ff5c2c03 3595 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3596 if (IS_ERR(u.xsave))
3597 return PTR_ERR(u.xsave);
2d5b5a66 3598
d1ac91d8 3599 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3600 break;
3601 }
3602 case KVM_GET_XCRS: {
d1ac91d8 3603 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3604 r = -ENOMEM;
d1ac91d8 3605 if (!u.xcrs)
2d5b5a66
SY		 3606 break;
3607
d1ac91d8 3608 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3609
3610 r = -EFAULT;
d1ac91d8 3611 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3612 sizeof(struct kvm_xcrs)))
3613 break;
3614 r = 0;
3615 break;
3616 }
3617 case KVM_SET_XCRS: {
ff5c2c03 3618 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3619 if (IS_ERR(u.xcrs))
3620 return PTR_ERR(u.xcrs);
2d5b5a66 3621
d1ac91d8 3622 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3623 break;
3624 }
92a1f12d
JR		 3625 case KVM_SET_TSC_KHZ: {
3626 u32 user_tsc_khz;
3627
3628 r = -EINVAL;
92a1f12d
JR		 3629 user_tsc_khz = (u32)arg;
3630
3631 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3632 goto out;
3633
cc578287
ZA		 3634 if (user_tsc_khz == 0)
3635 user_tsc_khz = tsc_khz;
3636
381d585c
HZ		 3637 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3638 r = 0;
92a1f12d 3639
92a1f12d
JR		 3640 goto out;
3641 }
3642 case KVM_GET_TSC_KHZ: {
cc578287 3643 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3644 goto out;
3645 }
1c0b28c2
EM		 3646 case KVM_KVMCLOCK_CTRL: {
3647 r = kvm_set_guest_paused(vcpu);
3648 goto out;
3649 }
5c919412
AS		 3650 case KVM_ENABLE_CAP: {
3651 struct kvm_enable_cap cap;
3652
3653 r = -EFAULT;
3654 if (copy_from_user(&cap, argp, sizeof(cap)))
3655 goto out;
3656 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3657 break;
3658 }
313a3dc7
CO		 3659 default:
3660 r = -EINVAL;
3661 }
3662out:
d1ac91d8 3663 kfree(u.buffer);
313a3dc7
CO		 3664 return r;
3665}
3666
5b1c1493
CO		 3667int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3668{
3669 return VM_FAULT_SIGBUS;
3670}
3671
1fe779f8
CO		 3672static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3673{
3674 int ret;
3675
3676 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3677 return -EINVAL;
1fe779f8
CO		 3678 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3679 return ret;
3680}
3681
b927a3ce
SY		 3682static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3683 u64 ident_addr)
3684{
3685 kvm->arch.ept_identity_map_addr = ident_addr;
3686 return 0;
3687}
3688
1fe779f8
CO		 3689static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3690 u32 kvm_nr_mmu_pages)
3691{
3692 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3693 return -EINVAL;
3694
79fac95e 3695 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3696
3697 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3698 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3699
79fac95e 3700 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3701 return 0;
3702}
3703
3704static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3705{
39de71ec 3706 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3707}
3708
1fe779f8
CO		 3709static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3710{
90bca052 3711 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3712 int r;
3713
3714 r = 0;
3715 switch (chip->chip_id) {
3716 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3717 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3718 sizeof(struct kvm_pic_state));
3719 break;
3720 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3721 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3722 sizeof(struct kvm_pic_state));
3723 break;
3724 case KVM_IRQCHIP_IOAPIC:
33392b49 3725 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3726 break;
3727 default:
3728 r = -EINVAL;
3729 break;
3730 }
3731 return r;
3732}
3733
3734static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3735{
90bca052 3736 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3737 int r;
3738
3739 r = 0;
3740 switch (chip->chip_id) {
3741 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3742 spin_lock(&pic->lock);
3743 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3744 sizeof(struct kvm_pic_state));
90bca052 3745 spin_unlock(&pic->lock);
1fe779f8
CO		 3746 break;
3747 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3748 spin_lock(&pic->lock);
3749 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3750 sizeof(struct kvm_pic_state));
90bca052 3751 spin_unlock(&pic->lock);
1fe779f8
CO		 3752 break;
3753 case KVM_IRQCHIP_IOAPIC:
33392b49 3754 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3755 break;
3756 default:
3757 r = -EINVAL;
3758 break;
3759 }
90bca052 3760 kvm_pic_update_irq(pic);
1fe779f8
CO		 3761 return r;
3762}
3763
e0f63cb9
SY		 3764static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3765{
34f3941c
RK		 3766 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3767
3768 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3769
3770 mutex_lock(&kps->lock);
3771 memcpy(ps, &kps->channels, sizeof(*ps));
3772 mutex_unlock(&kps->lock);
2da29bcc 3773 return 0;
e0f63cb9
SY		 3774}
3775
3776static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3777{
0185604c 3778 int i;
09edea72
RK		 3779 struct kvm_pit *pit = kvm->arch.vpit;
3780
3781 mutex_lock(&pit->pit_state.lock);
34f3941c 3782 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3783 for (i = 0; i < 3; i++)
09edea72
RK		 3784 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3785 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3786 return 0;
e9f42757
BK		 3787}
3788
3789static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3790{
e9f42757
BK		 3791 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3792 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3793 sizeof(ps->channels));
3794 ps->flags = kvm->arch.vpit->pit_state.flags;
3795 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3796 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3797 return 0;
e9f42757
BK		 3798}
3799
3800static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3801{
2da29bcc 3802 int start = 0;
0185604c 3803 int i;
e9f42757 3804 u32 prev_legacy, cur_legacy;
09edea72
RK		 3805 struct kvm_pit *pit = kvm->arch.vpit;
3806
3807 mutex_lock(&pit->pit_state.lock);
3808 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3809 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3810 if (!prev_legacy && cur_legacy)
3811 start = 1;
09edea72
RK		 3812 memcpy(&pit->pit_state.channels, &ps->channels,
3813 sizeof(pit->pit_state.channels));
3814 pit->pit_state.flags = ps->flags;
0185604c 3815 for (i = 0; i < 3; i++)
09edea72 3816 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3817 start && i == 0);
09edea72 3818 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3819 return 0;
e0f63cb9
SY		 3820}
3821
52d939a0
MT		 3822static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3823 struct kvm_reinject_control *control)
3824{
71474e2f
RK		 3825 struct kvm_pit *pit = kvm->arch.vpit;
3826
3827 if (!pit)
52d939a0 3828 return -ENXIO;
b39c90b6 3829
71474e2f
RK		 3830 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3831 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3832 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3833 */
3834 mutex_lock(&pit->pit_state.lock);
3835 kvm_pit_set_reinject(pit, control->pit_reinject);
3836 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3837
52d939a0
MT		 3838 return 0;
3839}
3840
95d4c16c 3841/**
60c34612
TY		 3842 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3843 * @kvm: kvm instance
3844 * @log: slot id and address to which we copy the log
95d4c16c 3845 *
e108ff2f
PB		 3846 * Steps 1-4 below provide general overview of dirty page logging. See
3847 * kvm_get_dirty_log_protect() function description for additional details.
3848 *
3849 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3850 * always flush the TLB (step 4) even if previous step failed and the dirty
3851 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3852 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3853 * writes will be marked dirty for next log read.
95d4c16c 3854 *
60c34612
TY		 3855 * 1. Take a snapshot of the bit and clear it if needed.
3856 * 2. Write protect the corresponding page.
e108ff2f
PB		 3857 * 3. Copy the snapshot to the userspace.
3858 * 4. Flush TLB's if needed.
5bb064dc 3859 */
60c34612 3860int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3861{
60c34612 3862 bool is_dirty = false;
e108ff2f 3863 int r;
5bb064dc 3864
79fac95e 3865 mutex_lock(&kvm->slots_lock);
5bb064dc 3866
88178fd4
KH		 3867 /*
3868 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3869 */
3870 if (kvm_x86_ops->flush_log_dirty)
3871 kvm_x86_ops->flush_log_dirty(kvm);
3872
e108ff2f 3873 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3874
3875 /*
3876 * All the TLBs can be flushed out of mmu lock, see the comments in
3877 * kvm_mmu_slot_remove_write_access().
3878 */
e108ff2f 3879 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3880 if (is_dirty)
3881 kvm_flush_remote_tlbs(kvm);
3882
79fac95e 3883 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3884 return r;
3885}
3886
aa2fbe6d
YZ		 3887int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3888 bool line_status)
23d43cf9
CD		 3889{
3890 if (!irqchip_in_kernel(kvm))
3891 return -ENXIO;
3892
3893 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3894 irq_event->irq, irq_event->level,
3895 line_status);
23d43cf9
CD		 3896 return 0;
3897}
3898
90de4a18
NA		 3899static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3900 struct kvm_enable_cap *cap)
3901{
3902 int r;
3903
3904 if (cap->flags)
3905 return -EINVAL;
3906
3907 switch (cap->cap) {
3908 case KVM_CAP_DISABLE_QUIRKS:
3909 kvm->arch.disabled_quirks = cap->args[0];
3910 r = 0;
3911 break;
49df6397
SR		 3912 case KVM_CAP_SPLIT_IRQCHIP: {
3913 mutex_lock(&kvm->lock);
b053b2ae
SR		 3914 r = -EINVAL;
3915 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3916 goto split_irqchip_unlock;
49df6397
SR		 3917 r = -EEXIST;
3918 if (irqchip_in_kernel(kvm))
3919 goto split_irqchip_unlock;
557abc40 3920 if (kvm->created_vcpus)
49df6397 3921 goto split_irqchip_unlock;
637e3f86 3922 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
49df6397 3923 r = kvm_setup_empty_irq_routing(kvm);
637e3f86
DH		 3924 if (r) {
3925 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
3926 /* Pairs with smp_rmb() when reading irqchip_mode */
3927 smp_wmb();
49df6397 3928 goto split_irqchip_unlock;
637e3f86 3929 }
49df6397
SR		 3930 /* Pairs with irqchip_in_kernel. */
3931 smp_wmb();
49776faf 3932 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3933 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3934 r = 0;
3935split_irqchip_unlock:
3936 mutex_unlock(&kvm->lock);
3937 break;
3938 }
37131313
RK		 3939 case KVM_CAP_X2APIC_API:
3940 r = -EINVAL;
3941 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3942 break;
3943
3944 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3945 kvm->arch.x2apic_format = true;
c519265f
RK		 3946 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3947 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3948
3949 r = 0;
3950 break;
90de4a18
NA		 3951 default:
3952 r = -EINVAL;
3953 break;
3954 }
3955 return r;
3956}
3957
1fe779f8
CO		 3958long kvm_arch_vm_ioctl(struct file *filp,
3959 unsigned int ioctl, unsigned long arg)
3960{
3961 struct kvm *kvm = filp->private_data;
3962 void __user *argp = (void __user *)arg;
367e1319 3963 int r = -ENOTTY;
f0d66275
DH		 3964 /*
3965 * This union makes it completely explicit to gcc-3.x
3966 * that these two variables' stack usage should be
3967 * combined, not added together.
3968 */
3969 union {
3970 struct kvm_pit_state ps;
e9f42757 3971 struct kvm_pit_state2 ps2;
c5ff41ce 3972 struct kvm_pit_config pit_config;
f0d66275 3973 } u;
1fe779f8
CO		 3974
3975 switch (ioctl) {
3976 case KVM_SET_TSS_ADDR:
3977 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3978 break;
b927a3ce
SY		 3979 case KVM_SET_IDENTITY_MAP_ADDR: {
3980 u64 ident_addr;
3981
3982 r = -EFAULT;
3983 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3984 goto out;
3985 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3986 break;
3987 }
1fe779f8
CO		 3988 case KVM_SET_NR_MMU_PAGES:
3989 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3990 break;
3991 case KVM_GET_NR_MMU_PAGES:
3992 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3993 break;
3ddea128 3994 case KVM_CREATE_IRQCHIP: {
3ddea128 3995 mutex_lock(&kvm->lock);
09941366 3996
3ddea128 3997 r = -EEXIST;
35e6eaa3 3998 if (irqchip_in_kernel(kvm))
3ddea128 3999 goto create_irqchip_unlock;
09941366 4000
3e515705 4001 r = -EINVAL;
557abc40 4002 if (kvm->created_vcpus)
3e515705 4003 goto create_irqchip_unlock;
09941366
RK		 4004
4005 r = kvm_pic_init(kvm);
4006 if (r)
3ddea128 4007 goto create_irqchip_unlock;
09941366
RK		 4008
4009 r = kvm_ioapic_init(kvm);
4010 if (r) {
09941366 4011 kvm_pic_destroy(kvm);
3ddea128 4012 goto create_irqchip_unlock;
09941366
RK		 4013 }
4014
637e3f86 4015 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
399ec807
AK		 4016 r = kvm_setup_default_irq_routing(kvm);
4017 if (r) {
637e3f86
DH		 4018 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
4019 /* Pairs with smp_rmb() when reading irqchip_mode */
4020 smp_wmb();
72bb2fcd 4021 kvm_ioapic_destroy(kvm);
09941366 4022 kvm_pic_destroy(kvm);
71ba994c 4023 goto create_irqchip_unlock;
399ec807 4024 }
49776faf 4025 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4026 smp_wmb();
49776faf 4027 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4028 create_irqchip_unlock:
4029 mutex_unlock(&kvm->lock);
1fe779f8 4030 break;
3ddea128 4031 }
7837699f 4032 case KVM_CREATE_PIT:
c5ff41ce
JK		 4033 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4034 goto create_pit;
4035 case KVM_CREATE_PIT2:
4036 r = -EFAULT;
4037 if (copy_from_user(&u.pit_config, argp,
4038 sizeof(struct kvm_pit_config)))
4039 goto out;
4040 create_pit:
250715a6 4041 mutex_lock(&kvm->lock);
269e05e4
AK		 4042 r = -EEXIST;
4043 if (kvm->arch.vpit)
4044 goto create_pit_unlock;
7837699f 4045 r = -ENOMEM;
c5ff41ce 4046 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4047 if (kvm->arch.vpit)
4048 r = 0;
269e05e4 4049 create_pit_unlock:
250715a6 4050 mutex_unlock(&kvm->lock);
7837699f 4051 break;
1fe779f8
CO		 4052 case KVM_GET_IRQCHIP: {
4053 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4054 struct kvm_irqchip *chip;
1fe779f8 4055
ff5c2c03
SL		 4056 chip = memdup_user(argp, sizeof(*chip));
4057 if (IS_ERR(chip)) {
4058 r = PTR_ERR(chip);
1fe779f8 4059 goto out;
ff5c2c03
SL		 4060 }
4061
1fe779f8 4062 r = -ENXIO;
826da321 4063 if (!irqchip_kernel(kvm))
f0d66275
DH		 4064 goto get_irqchip_out;
4065 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4066 if (r)
f0d66275 4067 goto get_irqchip_out;
1fe779f8 4068 r = -EFAULT;
f0d66275
DH		 4069 if (copy_to_user(argp, chip, sizeof *chip))
4070 goto get_irqchip_out;
1fe779f8 4071 r = 0;
f0d66275
DH		 4072 get_irqchip_out:
4073 kfree(chip);
1fe779f8
CO		 4074 break;
4075 }
4076 case KVM_SET_IRQCHIP: {
4077 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4078 struct kvm_irqchip *chip;
1fe779f8 4079
ff5c2c03
SL		 4080 chip = memdup_user(argp, sizeof(*chip));
4081 if (IS_ERR(chip)) {
4082 r = PTR_ERR(chip);
1fe779f8 4083 goto out;
ff5c2c03
SL		 4084 }
4085
1fe779f8 4086 r = -ENXIO;
826da321 4087 if (!irqchip_kernel(kvm))
f0d66275
DH		 4088 goto set_irqchip_out;
4089 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4090 if (r)
f0d66275 4091 goto set_irqchip_out;
1fe779f8 4092 r = 0;
f0d66275
DH		 4093 set_irqchip_out:
4094 kfree(chip);
1fe779f8
CO		 4095 break;
4096 }
e0f63cb9 4097 case KVM_GET_PIT: {
e0f63cb9 4098 r = -EFAULT;
f0d66275 4099 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4100 goto out;
4101 r = -ENXIO;
4102 if (!kvm->arch.vpit)
4103 goto out;
f0d66275 4104 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4105 if (r)
4106 goto out;
4107 r = -EFAULT;
f0d66275 4108 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4109 goto out;
4110 r = 0;
4111 break;
4112 }
4113 case KVM_SET_PIT: {
e0f63cb9 4114 r = -EFAULT;
f0d66275 4115 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4116 goto out;
4117 r = -ENXIO;
4118 if (!kvm->arch.vpit)
4119 goto out;
f0d66275 4120 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4121 break;
4122 }
e9f42757
BK		 4123 case KVM_GET_PIT2: {
4124 r = -ENXIO;
4125 if (!kvm->arch.vpit)
4126 goto out;
4127 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4128 if (r)
4129 goto out;
4130 r = -EFAULT;
4131 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4132 goto out;
4133 r = 0;
4134 break;
4135 }
4136 case KVM_SET_PIT2: {
4137 r = -EFAULT;
4138 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4139 goto out;
4140 r = -ENXIO;
4141 if (!kvm->arch.vpit)
4142 goto out;
4143 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4144 break;
4145 }
52d939a0
MT		 4146 case KVM_REINJECT_CONTROL: {
4147 struct kvm_reinject_control control;
4148 r = -EFAULT;
4149 if (copy_from_user(&control, argp, sizeof(control)))
4150 goto out;
4151 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4152 break;
4153 }
d71ba788
PB		 4154 case KVM_SET_BOOT_CPU_ID:
4155 r = 0;
4156 mutex_lock(&kvm->lock);
557abc40 4157 if (kvm->created_vcpus)
d71ba788
PB		 4158 r = -EBUSY;
4159 else
4160 kvm->arch.bsp_vcpu_id = arg;
4161 mutex_unlock(&kvm->lock);
4162 break;
ffde22ac
ES		 4163 case KVM_XEN_HVM_CONFIG: {
4164 r = -EFAULT;
4165 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4166 sizeof(struct kvm_xen_hvm_config)))
4167 goto out;
4168 r = -EINVAL;
4169 if (kvm->arch.xen_hvm_config.flags)
4170 goto out;
4171 r = 0;
4172 break;
4173 }
afbcf7ab 4174 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4175 struct kvm_clock_data user_ns;
4176 u64 now_ns;
afbcf7ab
GC		 4177
4178 r = -EFAULT;
4179 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4180 goto out;
4181
4182 r = -EINVAL;
4183 if (user_ns.flags)
4184 goto out;
4185
4186 r = 0;
e891a32e 4187 now_ns = get_kvmclock_ns(kvm);
108b249c 4188 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
2e762ff7 4189 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4190 break;
4191 }
4192 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4193 struct kvm_clock_data user_ns;
4194 u64 now_ns;
4195
e891a32e 4196 now_ns = get_kvmclock_ns(kvm);
108b249c 4197 user_ns.clock = now_ns;
e3fd9a93 4198 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4199 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4200
4201 r = -EFAULT;
4202 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4203 goto out;
4204 r = 0;
4205 break;
4206 }
90de4a18
NA		 4207 case KVM_ENABLE_CAP: {
4208 struct kvm_enable_cap cap;
afbcf7ab 4209
90de4a18
NA		 4210 r = -EFAULT;
4211 if (copy_from_user(&cap, argp, sizeof(cap)))
4212 goto out;
4213 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4214 break;
4215 }
1fe779f8 4216 default:
ad6260da 4217 r = -ENOTTY;
1fe779f8
CO		 4218 }
4219out:
4220 return r;
4221}
4222
a16b043c 4223static void kvm_init_msr_list(void)
043405e1
CO		 4224{
4225 u32 dummy[2];
4226 unsigned i, j;
4227
62ef68bb 4228 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4229 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4230 continue;
93c4adc7
PB		 4231
4232 /*
4233 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4234 * to the guests in some cases.
93c4adc7
PB		 4235 */
4236 switch (msrs_to_save[i]) {
4237 case MSR_IA32_BNDCFGS:
4238 if (!kvm_x86_ops->mpx_supported())
4239 continue;
4240 break;
9dbe6cf9
PB		 4241 case MSR_TSC_AUX:
4242 if (!kvm_x86_ops->rdtscp_supported())
4243 continue;
4244 break;
93c4adc7
PB		 4245 default:
4246 break;
4247 }
4248
043405e1
CO		 4249 if (j < i)
4250 msrs_to_save[j] = msrs_to_save[i];
4251 j++;
4252 }
4253 num_msrs_to_save = j;
62ef68bb
PB		 4254
4255 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4256 switch (emulated_msrs[i]) {
6d396b55
PB		 4257 case MSR_IA32_SMBASE:
4258 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4259 continue;
4260 break;
62ef68bb
PB		 4261 default:
4262 break;
4263 }
4264
4265 if (j < i)
4266 emulated_msrs[j] = emulated_msrs[i];
4267 j++;
4268 }
4269 num_emulated_msrs = j;
043405e1
CO		 4270}
4271
bda9020e
MT		 4272static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4273 const void *v)
bbd9b64e 4274{
70252a10
AK		 4275 int handled = 0;
4276 int n;
4277
4278 do {
4279 n = min(len, 8);
bce87cce 4280 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4281 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4282 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4283 break;
4284 handled += n;
4285 addr += n;
4286 len -= n;
4287 v += n;
4288 } while (len);
bbd9b64e 4289
70252a10 4290 return handled;
bbd9b64e
CO		 4291}
4292
bda9020e 4293static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4294{
70252a10
AK		 4295 int handled = 0;
4296 int n;
4297
4298 do {
4299 n = min(len, 8);
bce87cce 4300 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4301 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4302 addr, n, v))
4303 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4304 break;
4305 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4306 handled += n;
4307 addr += n;
4308 len -= n;
4309 v += n;
4310 } while (len);
bbd9b64e 4311
70252a10 4312 return handled;
bbd9b64e
CO		 4313}
4314
2dafc6c2
GN		 4315static void kvm_set_segment(struct kvm_vcpu *vcpu,
4316 struct kvm_segment *var, int seg)
4317{
4318 kvm_x86_ops->set_segment(vcpu, var, seg);
4319}
4320
4321void kvm_get_segment(struct kvm_vcpu *vcpu,
4322 struct kvm_segment *var, int seg)
4323{
4324 kvm_x86_ops->get_segment(vcpu, var, seg);
4325}
4326
54987b7a
PB		 4327gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4328 struct x86_exception *exception)
02f59dc9
JR		 4329{
4330 gpa_t t_gpa;
02f59dc9
JR		 4331
4332 BUG_ON(!mmu_is_nested(vcpu));
4333
4334 /* NPT walks are always user-walks */
4335 access |= PFERR_USER_MASK;
54987b7a 4336 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4337
4338 return t_gpa;
4339}
4340
ab9ae313
AK		 4341gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4342 struct x86_exception *exception)
1871c602
GN		 4343{
4344 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4345 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4346}
4347
ab9ae313
AK		 4348 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4349 struct x86_exception *exception)
1871c602
GN		 4350{
4351 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4352 access |= PFERR_FETCH_MASK;
ab9ae313 4353 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4354}
4355
ab9ae313
AK		 4356gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4357 struct x86_exception *exception)
1871c602
GN		 4358{
4359 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4360 access |= PFERR_WRITE_MASK;
ab9ae313 4361 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4362}
4363
4364/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4365gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4366 struct x86_exception *exception)
1871c602 4367{
ab9ae313 4368 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4369}
4370
4371static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4372 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4373 struct x86_exception *exception)
bbd9b64e
CO		 4374{
4375 void *data = val;
10589a46 4376 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4377
4378 while (bytes) {
14dfe855 4379 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4380 exception);
bbd9b64e 4381 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4382 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4383 int ret;
4384
bcc55cba 4385 if (gpa == UNMAPPED_GVA)
ab9ae313 4386 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4387 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4388 offset, toread);
10589a46 4389 if (ret < 0) {
c3cd7ffa 4390 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4391 goto out;
4392 }
bbd9b64e 4393
77c2002e
IE		 4394 bytes -= toread;
4395 data += toread;
4396 addr += toread;
bbd9b64e 4397 }
10589a46 4398out:
10589a46 4399 return r;
bbd9b64e 4400}
77c2002e 4401
1871c602 4402/* used for instruction fetching */
0f65dd70
AK		 4403static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4404 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4405 struct x86_exception *exception)
1871c602 4406{
0f65dd70 4407 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4408 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4409 unsigned offset;
4410 int ret;
0f65dd70 4411
44583cba
PB		 4412 /* Inline kvm_read_guest_virt_helper for speed. */
4413 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4414 exception);
4415 if (unlikely(gpa == UNMAPPED_GVA))
4416 return X86EMUL_PROPAGATE_FAULT;
4417
4418 offset = addr & (PAGE_SIZE-1);
4419 if (WARN_ON(offset + bytes > PAGE_SIZE))
4420 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4421 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4422 offset, bytes);
44583cba
PB		 4423 if (unlikely(ret < 0))
4424 return X86EMUL_IO_NEEDED;
4425
4426 return X86EMUL_CONTINUE;
1871c602
GN		 4427}
4428
064aea77 4429int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4430 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4431 struct x86_exception *exception)
1871c602 4432{
0f65dd70 4433 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4434 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4435
1871c602 4436 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4437 exception);
1871c602 4438}
064aea77 4439EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4440
0f65dd70
AK		 4441static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4442 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4443 struct x86_exception *exception)
1871c602 4444{
0f65dd70 4445 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4446 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4447}
4448
7a036a6f
RK		 4449static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4450 unsigned long addr, void *val, unsigned int bytes)
4451{
4452 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4453 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4454
4455 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4456}
4457
6a4d7550 4458int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4459 gva_t addr, void *val,
2dafc6c2 4460 unsigned int bytes,
bcc55cba 4461 struct x86_exception *exception)
77c2002e 4462{
0f65dd70 4463 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4464 void *data = val;
4465 int r = X86EMUL_CONTINUE;
4466
4467 while (bytes) {
14dfe855
JR		 4468 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4469 PFERR_WRITE_MASK,
ab9ae313 4470 exception);
77c2002e
IE		 4471 unsigned offset = addr & (PAGE_SIZE-1);
4472 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4473 int ret;
4474
bcc55cba 4475 if (gpa == UNMAPPED_GVA)
ab9ae313 4476 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4477 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4478 if (ret < 0) {
c3cd7ffa 4479 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4480 goto out;
4481 }
4482
4483 bytes -= towrite;
4484 data += towrite;
4485 addr += towrite;
4486 }
4487out:
4488 return r;
4489}
6a4d7550 4490EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4491
0f89b207
TL		 4492static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4493 gpa_t gpa, bool write)
4494{
4495 /* For APIC access vmexit */
4496 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4497 return 1;
4498
4499 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4500 trace_vcpu_match_mmio(gva, gpa, write, true);
4501 return 1;
4502 }
4503
4504 return 0;
4505}
4506
af7cc7d1
XG		 4507static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4508 gpa_t *gpa, struct x86_exception *exception,
4509 bool write)
4510{
97d64b78
AK		 4511 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4512 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4513
be94f6b7
HH		 4514 /*
4515 * currently PKRU is only applied to ept enabled guest so
4516 * there is no pkey in EPT page table for L1 guest or EPT
4517 * shadow page table for L2 guest.
4518 */
97d64b78 4519 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4520 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4521 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4522 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4523 (gva & (PAGE_SIZE - 1));
4f022648 4524 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4525 return 1;
4526 }
4527
af7cc7d1
XG		 4528 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4529
4530 if (*gpa == UNMAPPED_GVA)
4531 return -1;
4532
0f89b207 4533 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4534}
4535
3200f405 4536int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4537 const void *val, int bytes)
bbd9b64e
CO		 4538{
4539 int ret;
4540
54bf36aa 4541 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4542 if (ret < 0)
bbd9b64e 4543 return 0;
0eb05bf2 4544 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4545 return 1;
4546}
4547
77d197b2
XG		 4548struct read_write_emulator_ops {
4549 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4550 int bytes);
4551 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4552 void *val, int bytes);
4553 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4554 int bytes, void *val);
4555 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4556 void *val, int bytes);
4557 bool write;
4558};
4559
4560static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4561{
4562 if (vcpu->mmio_read_completed) {
77d197b2 4563 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4564 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4565 vcpu->mmio_read_completed = 0;
4566 return 1;
4567 }
4568
4569 return 0;
4570}
4571
4572static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4573 void *val, int bytes)
4574{
54bf36aa 4575 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4576}
4577
4578static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4579 void *val, int bytes)
4580{
4581 return emulator_write_phys(vcpu, gpa, val, bytes);
4582}
4583
4584static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4585{
4586 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4587 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4588}
4589
4590static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4591 void *val, int bytes)
4592{
4593 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4594 return X86EMUL_IO_NEEDED;
4595}
4596
4597static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4598 void *val, int bytes)
4599{
f78146b0
AK		 4600 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4601
87da7e66 4602 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4603 return X86EMUL_CONTINUE;
4604}
4605
0fbe9b0b 4606static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4607 .read_write_prepare = read_prepare,
4608 .read_write_emulate = read_emulate,
4609 .read_write_mmio = vcpu_mmio_read,
4610 .read_write_exit_mmio = read_exit_mmio,
4611};
4612
0fbe9b0b 4613static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4614 .read_write_emulate = write_emulate,
4615 .read_write_mmio = write_mmio,
4616 .read_write_exit_mmio = write_exit_mmio,
4617 .write = true,
4618};
4619
22388a3c
XG		 4620static int emulator_read_write_onepage(unsigned long addr, void *val,
4621 unsigned int bytes,
4622 struct x86_exception *exception,
4623 struct kvm_vcpu *vcpu,
0fbe9b0b 4624 const struct read_write_emulator_ops *ops)
bbd9b64e 4625{
af7cc7d1
XG		 4626 gpa_t gpa;
4627 int handled, ret;
22388a3c 4628 bool write = ops->write;
f78146b0 4629 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4630 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4631
4632 /*
4633 * If the exit was due to a NPF we may already have a GPA.
4634 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4635 * Note, this cannot be used on string operations since string
4636 * operation using rep will only have the initial GPA from the NPF
4637 * occurred.
4638 */
4639 if (vcpu->arch.gpa_available &&
4640 emulator_can_use_gpa(ctxt) &&
4641 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4642 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4643 gpa = exception->address;
4644 goto mmio;
4645 }
10589a46 4646
22388a3c 4647 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4648
af7cc7d1 4649 if (ret < 0)
bbd9b64e 4650 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4651
4652 /* For APIC access vmexit */
af7cc7d1 4653 if (ret)
bbd9b64e
CO		 4654 goto mmio;
4655
22388a3c 4656 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4657 return X86EMUL_CONTINUE;
4658
4659mmio:
4660 /*
4661 * Is this MMIO handled locally?
4662 */
22388a3c 4663 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4664 if (handled == bytes)
bbd9b64e 4665 return X86EMUL_CONTINUE;
bbd9b64e 4666
70252a10
AK		 4667 gpa += handled;
4668 bytes -= handled;
4669 val += handled;
4670
87da7e66
XG		 4671 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4672 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4673 frag->gpa = gpa;
4674 frag->data = val;
4675 frag->len = bytes;
f78146b0 4676 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4677}
4678
52eb5a6d
XL		 4679static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4680 unsigned long addr,
22388a3c
XG		 4681 void *val, unsigned int bytes,
4682 struct x86_exception *exception,
0fbe9b0b 4683 const struct read_write_emulator_ops *ops)
bbd9b64e 4684{
0f65dd70 4685 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4686 gpa_t gpa;
4687 int rc;
4688
4689 if (ops->read_write_prepare &&
4690 ops->read_write_prepare(vcpu, val, bytes))
4691 return X86EMUL_CONTINUE;
4692
4693 vcpu->mmio_nr_fragments = 0;
0f65dd70 4694
bbd9b64e
CO		 4695 /* Crossing a page boundary? */
4696 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4697 int now;
bbd9b64e
CO		 4698
4699 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4700 rc = emulator_read_write_onepage(addr, val, now, exception,
4701 vcpu, ops);
4702
bbd9b64e
CO		 4703 if (rc != X86EMUL_CONTINUE)
4704 return rc;
4705 addr += now;
bac15531
NA		 4706 if (ctxt->mode != X86EMUL_MODE_PROT64)
4707 addr = (u32)addr;
bbd9b64e
CO		 4708 val += now;
4709 bytes -= now;
4710 }
22388a3c 4711
f78146b0
AK		 4712 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4713 vcpu, ops);
4714 if (rc != X86EMUL_CONTINUE)
4715 return rc;
4716
4717 if (!vcpu->mmio_nr_fragments)
4718 return rc;
4719
4720 gpa = vcpu->mmio_fragments[0].gpa;
4721
4722 vcpu->mmio_needed = 1;
4723 vcpu->mmio_cur_fragment = 0;
4724
87da7e66 4725 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4726 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4727 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4728 vcpu->run->mmio.phys_addr = gpa;
4729
4730 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4731}
4732
4733static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4734 unsigned long addr,
4735 void *val,
4736 unsigned int bytes,
4737 struct x86_exception *exception)
4738{
4739 return emulator_read_write(ctxt, addr, val, bytes,
4740 exception, &read_emultor);
4741}
4742
52eb5a6d 4743static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4744 unsigned long addr,
4745 const void *val,
4746 unsigned int bytes,
4747 struct x86_exception *exception)
4748{
4749 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4750 exception, &write_emultor);
bbd9b64e 4751}
bbd9b64e 4752
daea3e73
AK		 4753#define CMPXCHG_TYPE(t, ptr, old, new) \
4754 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4755
4756#ifdef CONFIG_X86_64
4757# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4758#else
4759# define CMPXCHG64(ptr, old, new) \
9749a6c0 4760 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4761#endif
4762
0f65dd70
AK		 4763static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4764 unsigned long addr,
bbd9b64e
CO		 4765 const void *old,
4766 const void *new,
4767 unsigned int bytes,
0f65dd70 4768 struct x86_exception *exception)
bbd9b64e 4769{
0f65dd70 4770 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4771 gpa_t gpa;
4772 struct page *page;
4773 char *kaddr;
4774 bool exchanged;
2bacc55c 4775
daea3e73
AK		 4776 /* guests cmpxchg8b have to be emulated atomically */
4777 if (bytes > 8 || (bytes & (bytes - 1)))
4778 goto emul_write;
10589a46 4779
daea3e73 4780 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4781
daea3e73
AK		 4782 if (gpa == UNMAPPED_GVA ||
4783 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4784 goto emul_write;
2bacc55c 4785
daea3e73
AK		 4786 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4787 goto emul_write;
72dc67a6 4788
54bf36aa 4789 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4790 if (is_error_page(page))
c19b8bd6 4791 goto emul_write;
72dc67a6 4792
8fd75e12 4793 kaddr = kmap_atomic(page);
daea3e73
AK		 4794 kaddr += offset_in_page(gpa);
4795 switch (bytes) {
4796 case 1:
4797 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4798 break;
4799 case 2:
4800 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4801 break;
4802 case 4:
4803 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4804 break;
4805 case 8:
4806 exchanged = CMPXCHG64(kaddr, old, new);
4807 break;
4808 default:
4809 BUG();
2bacc55c 4810 }
8fd75e12 4811 kunmap_atomic(kaddr);
daea3e73
AK		 4812 kvm_release_page_dirty(page);
4813
4814 if (!exchanged)
4815 return X86EMUL_CMPXCHG_FAILED;
4816
54bf36aa 4817 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4818 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4819
4820 return X86EMUL_CONTINUE;
4a5f48f6 4821
3200f405 4822emul_write:
daea3e73 4823 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4824
0f65dd70 4825 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4826}
4827
cf8f70bf
GN		 4828static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4829{
4830 /* TODO: String I/O for in kernel device */
4831 int r;
4832
4833 if (vcpu->arch.pio.in)
e32edf4f 4834 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4835 vcpu->arch.pio.size, pd);
4836 else
e32edf4f 4837 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4838 vcpu->arch.pio.port, vcpu->arch.pio.size,
4839 pd);
4840 return r;
4841}
4842
6f6fbe98
XG		 4843static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4844 unsigned short port, void *val,
4845 unsigned int count, bool in)
cf8f70bf 4846{
cf8f70bf 4847 vcpu->arch.pio.port = port;
6f6fbe98 4848 vcpu->arch.pio.in = in;
7972995b 4849 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4850 vcpu->arch.pio.size = size;
4851
4852 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4853 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4854 return 1;
4855 }
4856
4857 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4858 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4859 vcpu->run->io.size = size;
4860 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4861 vcpu->run->io.count = count;
4862 vcpu->run->io.port = port;
4863
4864 return 0;
4865}
4866
6f6fbe98
XG		 4867static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4868 int size, unsigned short port, void *val,
4869 unsigned int count)
cf8f70bf 4870{
ca1d4a9e 4871 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4872 int ret;
ca1d4a9e 4873
6f6fbe98
XG		 4874 if (vcpu->arch.pio.count)
4875 goto data_avail;
cf8f70bf 4876
6f6fbe98
XG		 4877 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4878 if (ret) {
4879data_avail:
4880 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4881 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4882 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4883 return 1;
4884 }
4885
cf8f70bf
GN		 4886 return 0;
4887}
4888
6f6fbe98
XG		 4889static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4890 int size, unsigned short port,
4891 const void *val, unsigned int count)
4892{
4893 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4894
4895 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4896 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4897 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4898}
4899
bbd9b64e
CO		 4900static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4901{
4902 return kvm_x86_ops->get_segment_base(vcpu, seg);
4903}
4904
3cb16fe7 4905static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4906{
3cb16fe7 4907 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4908}
4909
ae6a2375 4910static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4911{
4912 if (!need_emulate_wbinvd(vcpu))
4913 return X86EMUL_CONTINUE;
4914
4915 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4916 int cpu = get_cpu();
4917
4918 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4919 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4920 wbinvd_ipi, NULL, 1);
2eec7343 4921 put_cpu();
f5f48ee1 4922 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4923 } else
4924 wbinvd();
f5f48ee1
SY		 4925 return X86EMUL_CONTINUE;
4926}
5cb56059
JS		 4927
4928int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4929{
6affcbed
KH		 4930 kvm_emulate_wbinvd_noskip(vcpu);
4931 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4932}
f5f48ee1
SY		 4933EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4934
5cb56059
JS		 4935
4936
bcaf5cc5
AK		 4937static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4938{
5cb56059 4939 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4940}
4941
52eb5a6d
XL		 4942static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4943 unsigned long *dest)
bbd9b64e 4944{
16f8a6f9 4945 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4946}
4947
52eb5a6d
XL		 4948static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4949 unsigned long value)
bbd9b64e 4950{
338dbc97 4951
717746e3 4952 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4953}
4954
52a46617 4955static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4956{
52a46617 4957 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4958}
4959
717746e3 4960static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4961{
717746e3 4962 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4963 unsigned long value;
4964
4965 switch (cr) {
4966 case 0:
4967 value = kvm_read_cr0(vcpu);
4968 break;
4969 case 2:
4970 value = vcpu->arch.cr2;
4971 break;
4972 case 3:
9f8fe504 4973 value = kvm_read_cr3(vcpu);
52a46617
GN		 4974 break;
4975 case 4:
4976 value = kvm_read_cr4(vcpu);
4977 break;
4978 case 8:
4979 value = kvm_get_cr8(vcpu);
4980 break;
4981 default:
a737f256 4982 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4983 return 0;
4984 }
4985
4986 return value;
4987}
4988
717746e3 4989static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4990{
717746e3 4991 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4992 int res = 0;
4993
52a46617
GN		 4994 switch (cr) {
4995 case 0:
49a9b07e 4996 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4997 break;
4998 case 2:
4999 vcpu->arch.cr2 = val;
5000 break;
5001 case 3:
2390218b 5002 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5003 break;
5004 case 4:
a83b29c6 5005 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5006 break;
5007 case 8:
eea1cff9 5008 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5009 break;
5010 default:
a737f256 5011 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5012 res = -1;
52a46617 5013 }
0f12244f
GN		 5014
5015 return res;
52a46617
GN		 5016}
5017
717746e3 5018static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5019{
717746e3 5020 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5021}
5022
4bff1e86 5023static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5024{
4bff1e86 5025 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5026}
5027
4bff1e86 5028static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5029{
4bff1e86 5030 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5031}
5032
1ac9d0cf
AK		 5033static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5034{
5035 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5036}
5037
5038static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5039{
5040 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5041}
5042
4bff1e86
AK		 5043static unsigned long emulator_get_cached_segment_base(
5044 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5045{
4bff1e86 5046 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5047}
5048
1aa36616
AK		 5049static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5050 struct desc_struct *desc, u32 *base3,
5051 int seg)
2dafc6c2
GN		 5052{
5053 struct kvm_segment var;
5054
4bff1e86 5055 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5056 *selector = var.selector;
2dafc6c2 5057
378a8b09
GN		 5058 if (var.unusable) {
5059 memset(desc, 0, sizeof(*desc));
2dafc6c2 5060 return false;
378a8b09 5061 }
2dafc6c2
GN		 5062
5063 if (var.g)
5064 var.limit >>= 12;
5065 set_desc_limit(desc, var.limit);
5066 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5067#ifdef CONFIG_X86_64
5068 if (base3)
5069 *base3 = var.base >> 32;
5070#endif
2dafc6c2
GN		 5071 desc->type = var.type;
5072 desc->s = var.s;
5073 desc->dpl = var.dpl;
5074 desc->p = var.present;
5075 desc->avl = var.avl;
5076 desc->l = var.l;
5077 desc->d = var.db;
5078 desc->g = var.g;
5079
5080 return true;
5081}
5082
1aa36616
AK		 5083static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5084 struct desc_struct *desc, u32 base3,
5085 int seg)
2dafc6c2 5086{
4bff1e86 5087 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5088 struct kvm_segment var;
5089
1aa36616 5090 var.selector = selector;
2dafc6c2 5091 var.base = get_desc_base(desc);
5601d05b
GN		 5092#ifdef CONFIG_X86_64
5093 var.base |= ((u64)base3) << 32;
5094#endif
2dafc6c2
GN		 5095 var.limit = get_desc_limit(desc);
5096 if (desc->g)
5097 var.limit = (var.limit << 12) | 0xfff;
5098 var.type = desc->type;
2dafc6c2
GN		 5099 var.dpl = desc->dpl;
5100 var.db = desc->d;
5101 var.s = desc->s;
5102 var.l = desc->l;
5103 var.g = desc->g;
5104 var.avl = desc->avl;
5105 var.present = desc->p;
5106 var.unusable = !var.present;
5107 var.padding = 0;
5108
5109 kvm_set_segment(vcpu, &var, seg);
5110 return;
5111}
5112
717746e3
AK		 5113static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5114 u32 msr_index, u64 *pdata)
5115{
609e36d3
PB		 5116 struct msr_data msr;
5117 int r;
5118
5119 msr.index = msr_index;
5120 msr.host_initiated = false;
5121 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5122 if (r)
5123 return r;
5124
5125 *pdata = msr.data;
5126 return 0;
717746e3
AK		 5127}
5128
5129static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5130 u32 msr_index, u64 data)
5131{
8fe8ab46
WA		 5132 struct msr_data msr;
5133
5134 msr.data = data;
5135 msr.index = msr_index;
5136 msr.host_initiated = false;
5137 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5138}
5139
64d60670
PB		 5140static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5141{
5142 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5143
5144 return vcpu->arch.smbase;
5145}
5146
5147static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5148{
5149 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5150
5151 vcpu->arch.smbase = smbase;
5152}
5153
67f4d428
NA		 5154static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5155 u32 pmc)
5156{
c6702c9d 5157 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5158}
5159
222d21aa
AK		 5160static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5161 u32 pmc, u64 *pdata)
5162{
c6702c9d 5163 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5164}
5165
6c3287f7
AK		 5166static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5167{
5168 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5169}
5170
5037f6f3
AK		 5171static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5172{
5173 preempt_disable();
5197b808 5174 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5175}
5176
5177static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5178{
5179 preempt_enable();
5180}
5181
2953538e 5182static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5183 struct x86_instruction_info *info,
c4f035c6
AK		 5184 enum x86_intercept_stage stage)
5185{
2953538e 5186 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5187}
5188
0017f93a 5189static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5190 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5191{
0017f93a 5192 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5193}
5194
dd856efa
AK		 5195static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5196{
5197 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5198}
5199
5200static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5201{
5202 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5203}
5204
801806d9
NA		 5205static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5206{
5207 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5208}
5209
6ed071f0
LP		 5210static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5211{
5212 return emul_to_vcpu(ctxt)->arch.hflags;
5213}
5214
5215static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5216{
5217 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5218}
5219
0225fb50 5220static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5221 .read_gpr = emulator_read_gpr,
5222 .write_gpr = emulator_write_gpr,
1871c602 5223 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5224 .write_std = kvm_write_guest_virt_system,
7a036a6f 5225 .read_phys = kvm_read_guest_phys_system,
1871c602 5226 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5227 .read_emulated = emulator_read_emulated,
5228 .write_emulated = emulator_write_emulated,
5229 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5230 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5231 .pio_in_emulated = emulator_pio_in_emulated,
5232 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5233 .get_segment = emulator_get_segment,
5234 .set_segment = emulator_set_segment,
5951c442 5235 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5236 .get_gdt = emulator_get_gdt,
160ce1f1 5237 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5238 .set_gdt = emulator_set_gdt,
5239 .set_idt = emulator_set_idt,
52a46617
GN		 5240 .get_cr = emulator_get_cr,
5241 .set_cr = emulator_set_cr,
9c537244 5242 .cpl = emulator_get_cpl,
35aa5375
GN		 5243 .get_dr = emulator_get_dr,
5244 .set_dr = emulator_set_dr,
64d60670
PB		 5245 .get_smbase = emulator_get_smbase,
5246 .set_smbase = emulator_set_smbase,
717746e3
AK		 5247 .set_msr = emulator_set_msr,
5248 .get_msr = emulator_get_msr,
67f4d428 5249 .check_pmc = emulator_check_pmc,
222d21aa 5250 .read_pmc = emulator_read_pmc,
6c3287f7 5251 .halt = emulator_halt,
bcaf5cc5 5252 .wbinvd = emulator_wbinvd,
d6aa1000 5253 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5254 .get_fpu = emulator_get_fpu,
5255 .put_fpu = emulator_put_fpu,
c4f035c6 5256 .intercept = emulator_intercept,
bdb42f5a 5257 .get_cpuid = emulator_get_cpuid,
801806d9 5258 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5259 .get_hflags = emulator_get_hflags,
5260 .set_hflags = emulator_set_hflags,
bbd9b64e
CO		 5261};
5262
95cb2295
GN		 5263static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5264{
37ccdcbe 5265 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5266 /*
5267 * an sti; sti; sequence only disable interrupts for the first
5268 * instruction. So, if the last instruction, be it emulated or
5269 * not, left the system with the INT_STI flag enabled, it
5270 * means that the last instruction is an sti. We should not
5271 * leave the flag on in this case. The same goes for mov ss
5272 */
37ccdcbe
PB		 5273 if (int_shadow & mask)
5274 mask = 0;
6addfc42 5275 if (unlikely(int_shadow || mask)) {
95cb2295 5276 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5277 if (!mask)
5278 kvm_make_request(KVM_REQ_EVENT, vcpu);
5279 }
95cb2295
GN		 5280}
5281
ef54bcfe 5282static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5283{
5284 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5285 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5286 return kvm_propagate_fault(vcpu, &ctxt->exception);
5287
5288 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5289 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5290 ctxt->exception.error_code);
54b8486f 5291 else
da9cb575 5292 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5293 return false;
54b8486f
GN		 5294}
5295
8ec4722d
MG		 5296static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5297{
adf52235 5298 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5299 int cs_db, cs_l;
5300
8ec4722d
MG		 5301 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5302
adf52235
TY		 5303 ctxt->eflags = kvm_get_rflags(vcpu);
5304 ctxt->eip = kvm_rip_read(vcpu);
5305 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5306 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5307 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5308 cs_db ? X86EMUL_MODE_PROT32 :
5309 X86EMUL_MODE_PROT16;
a584539b 5310 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5311 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5312 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5313
dd856efa 5314 init_decode_cache(ctxt);
7ae441ea 5315 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5316}
5317
71f9833b 5318int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5319{
9d74191a 5320 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5321 int ret;
5322
5323 init_emulate_ctxt(vcpu);
5324
9dac77fa
AK		 5325 ctxt->op_bytes = 2;
5326 ctxt->ad_bytes = 2;
5327 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5328 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5329
5330 if (ret != X86EMUL_CONTINUE)
5331 return EMULATE_FAIL;
5332
9dac77fa 5333 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5334 kvm_rip_write(vcpu, ctxt->eip);
5335 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5336
5337 if (irq == NMI_VECTOR)
7460fb4a 5338 vcpu->arch.nmi_pending = 0;
63995653
MG		 5339 else
5340 vcpu->arch.interrupt.pending = false;
5341
5342 return EMULATE_DONE;
5343}
5344EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5345
6d77dbfc
GN		 5346static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5347{
fc3a9157
JR		 5348 int r = EMULATE_DONE;
5349
6d77dbfc
GN		 5350 ++vcpu->stat.insn_emulation_fail;
5351 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5352 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5353 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5354 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5355 vcpu->run->internal.ndata = 0;
5356 r = EMULATE_FAIL;
5357 }
6d77dbfc 5358 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5359
5360 return r;
6d77dbfc
GN		 5361}
5362
93c05d3e 5363static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5364 bool write_fault_to_shadow_pgtable,
5365 int emulation_type)
a6f177ef 5366{
95b3cf69 5367 gpa_t gpa = cr2;
ba049e93 5368 kvm_pfn_t pfn;
a6f177ef 5369
991eebf9
GN		 5370 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5371 return false;
5372
95b3cf69
XG		 5373 if (!vcpu->arch.mmu.direct_map) {
5374 /*
5375 * Write permission should be allowed since only
5376 * write access need to be emulated.
5377 */
5378 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5379
95b3cf69
XG		 5380 /*
5381 * If the mapping is invalid in guest, let cpu retry
5382 * it to generate fault.
5383 */
5384 if (gpa == UNMAPPED_GVA)
5385 return true;
5386 }
a6f177ef 5387
8e3d9d06
XG		 5388 /*
5389 * Do not retry the unhandleable instruction if it faults on the
5390 * readonly host memory, otherwise it will goto a infinite loop:
5391 * retry instruction -> write #PF -> emulation fail -> retry
5392 * instruction -> ...
5393 */
5394 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5395
5396 /*
5397 * If the instruction failed on the error pfn, it can not be fixed,
5398 * report the error to userspace.
5399 */
5400 if (is_error_noslot_pfn(pfn))
5401 return false;
5402
5403 kvm_release_pfn_clean(pfn);
5404
5405 /* The instructions are well-emulated on direct mmu. */
5406 if (vcpu->arch.mmu.direct_map) {
5407 unsigned int indirect_shadow_pages;
5408
5409 spin_lock(&vcpu->kvm->mmu_lock);
5410 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5411 spin_unlock(&vcpu->kvm->mmu_lock);
5412
5413 if (indirect_shadow_pages)
5414 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5415
a6f177ef 5416 return true;
8e3d9d06 5417 }
a6f177ef 5418
95b3cf69
XG		 5419 /*
5420 * if emulation was due to access to shadowed page table
5421 * and it failed try to unshadow page and re-enter the
5422 * guest to let CPU execute the instruction.
5423 */
5424 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5425
5426 /*
5427 * If the access faults on its page table, it can not
5428 * be fixed by unprotecting shadow page and it should
5429 * be reported to userspace.
5430 */
5431 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5432}
5433
1cb3f3ae
XG		 5434static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5435 unsigned long cr2, int emulation_type)
5436{
5437 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5438 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5439
5440 last_retry_eip = vcpu->arch.last_retry_eip;
5441 last_retry_addr = vcpu->arch.last_retry_addr;
5442
5443 /*
5444 * If the emulation is caused by #PF and it is non-page_table
5445 * writing instruction, it means the VM-EXIT is caused by shadow
5446 * page protected, we can zap the shadow page and retry this
5447 * instruction directly.
5448 *
5449 * Note: if the guest uses a non-page-table modifying instruction
5450 * on the PDE that points to the instruction, then we will unmap
5451 * the instruction and go to an infinite loop. So, we cache the
5452 * last retried eip and the last fault address, if we meet the eip
5453 * and the address again, we can break out of the potential infinite
5454 * loop.
5455 */
5456 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5457
5458 if (!(emulation_type & EMULTYPE_RETRY))
5459 return false;
5460
5461 if (x86_page_table_writing_insn(ctxt))
5462 return false;
5463
5464 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5465 return false;
5466
5467 vcpu->arch.last_retry_eip = ctxt->eip;
5468 vcpu->arch.last_retry_addr = cr2;
5469
5470 if (!vcpu->arch.mmu.direct_map)
5471 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5472
22368028 5473 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5474
5475 return true;
5476}
5477
716d51ab
GN		 5478static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5479static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5480
64d60670 5481static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5482{
64d60670 5483 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5484 /* This is a good place to trace that we are exiting SMM. */
5485 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5486
c43203ca
PB		 5487 /* Process a latched INIT or SMI, if any. */
5488 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5489 }
699023e2
PB		 5490
5491 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5492}
5493
5494static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5495{
5496 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5497
a584539b 5498 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5499
5500 if (changed & HF_SMM_MASK)
5501 kvm_smm_changed(vcpu);
a584539b
PB		 5502}
5503
4a1e10d5
PB		 5504static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5505 unsigned long *db)
5506{
5507 u32 dr6 = 0;
5508 int i;
5509 u32 enable, rwlen;
5510
5511 enable = dr7;
5512 rwlen = dr7 >> 16;
5513 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5514 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5515 dr6 |= (1 << i);
5516 return dr6;
5517}
5518
6addfc42 5519static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5520{
5521 struct kvm_run *kvm_run = vcpu->run;
5522
5523 /*
6addfc42
PB		 5524 * rflags is the old, "raw" value of the flags. The new value has
5525 * not been saved yet.
663f4c61
PB		 5526 *
5527 * This is correct even for TF set by the guest, because "the
5528 * processor will not generate this exception after the instruction
5529 * that sets the TF flag".
5530 */
663f4c61
PB		 5531 if (unlikely(rflags & X86_EFLAGS_TF)) {
5532 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5533 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5534 DR6_RTM;
663f4c61
PB		 5535 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5536 kvm_run->debug.arch.exception = DB_VECTOR;
5537 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5538 *r = EMULATE_USER_EXIT;
5539 } else {
663f4c61
PB		 5540 /*
5541 * "Certain debug exceptions may clear bit 0-3. The
5542 * remaining contents of the DR6 register are never
5543 * cleared by the processor".
5544 */
5545 vcpu->arch.dr6 &= ~15;
6f43ed01 5546 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5547 kvm_queue_exception(vcpu, DB_VECTOR);
5548 }
5549 }
5550}
5551
6affcbed
KH		 5552int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5553{
5554 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5555 int r = EMULATE_DONE;
5556
5557 kvm_x86_ops->skip_emulated_instruction(vcpu);
5558 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5559 return r == EMULATE_DONE;
5560}
5561EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5562
4a1e10d5
PB		 5563static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5564{
4a1e10d5
PB		 5565 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5566 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5567 struct kvm_run *kvm_run = vcpu->run;
5568 unsigned long eip = kvm_get_linear_rip(vcpu);
5569 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5570 vcpu->arch.guest_debug_dr7,
5571 vcpu->arch.eff_db);
5572
5573 if (dr6 != 0) {
6f43ed01 5574 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5575 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5576 kvm_run->debug.arch.exception = DB_VECTOR;
5577 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5578 *r = EMULATE_USER_EXIT;
5579 return true;
5580 }
5581 }
5582
4161a569
NA		 5583 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5584 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5585 unsigned long eip = kvm_get_linear_rip(vcpu);
5586 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5587 vcpu->arch.dr7,
5588 vcpu->arch.db);
5589
5590 if (dr6 != 0) {
5591 vcpu->arch.dr6 &= ~15;
6f43ed01 5592 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5593 kvm_queue_exception(vcpu, DB_VECTOR);
5594 *r = EMULATE_DONE;
5595 return true;
5596 }
5597 }
5598
5599 return false;
5600}
5601
51d8b661
AP		 5602int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5603 unsigned long cr2,
dc25e89e
AP		 5604 int emulation_type,
5605 void *insn,
5606 int insn_len)
bbd9b64e 5607{
95cb2295 5608 int r;
9d74191a 5609 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5610 bool writeback = true;
93c05d3e 5611 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5612
93c05d3e
XG		 5613 /*
5614 * Clear write_fault_to_shadow_pgtable here to ensure it is
5615 * never reused.
5616 */
5617 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5618 kvm_clear_exception_queue(vcpu);
8d7d8102 5619
571008da 5620 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5621 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5622
5623 /*
5624 * We will reenter on the same instruction since
5625 * we do not set complete_userspace_io. This does not
5626 * handle watchpoints yet, those would be handled in
5627 * the emulate_ops.
5628 */
5629 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5630 return r;
5631
9d74191a
TY		 5632 ctxt->interruptibility = 0;
5633 ctxt->have_exception = false;
e0ad0b47 5634 ctxt->exception.vector = -1;
9d74191a 5635 ctxt->perm_ok = false;
bbd9b64e 5636
b51e974f 5637 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5638
9d74191a 5639 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5640
e46479f8 5641 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5642 ++vcpu->stat.insn_emulation;
1d2887e2 5643 if (r != EMULATION_OK) {
4005996e
AK		 5644 if (emulation_type & EMULTYPE_TRAP_UD)
5645 return EMULATE_FAIL;
991eebf9
GN		 5646 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5647 emulation_type))
bbd9b64e 5648 return EMULATE_DONE;
6d77dbfc
GN		 5649 if (emulation_type & EMULTYPE_SKIP)
5650 return EMULATE_FAIL;
5651 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5652 }
5653 }
5654
ba8afb6b 5655 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5656 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5657 if (ctxt->eflags & X86_EFLAGS_RF)
5658 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5659 return EMULATE_DONE;
5660 }
5661
1cb3f3ae
XG		 5662 if (retry_instruction(ctxt, cr2, emulation_type))
5663 return EMULATE_DONE;
5664
7ae441ea 5665 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5666 changes registers values during IO operation */
7ae441ea
GN		 5667 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5668 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5669 emulator_invalidate_register_cache(ctxt);
7ae441ea 5670 }
4d2179e1 5671
5cd21917 5672restart:
0f89b207
TL		 5673 /* Save the faulting GPA (cr2) in the address field */
5674 ctxt->exception.address = cr2;
5675
9d74191a 5676 r = x86_emulate_insn(ctxt);
bbd9b64e 5677
775fde86
JR		 5678 if (r == EMULATION_INTERCEPTED)
5679 return EMULATE_DONE;
5680
d2ddd1c4 5681 if (r == EMULATION_FAILED) {
991eebf9
GN		 5682 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5683 emulation_type))
c3cd7ffa
GN		 5684 return EMULATE_DONE;
5685
6d77dbfc 5686 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5687 }
5688
9d74191a 5689 if (ctxt->have_exception) {
d2ddd1c4 5690 r = EMULATE_DONE;
ef54bcfe
PB		 5691 if (inject_emulated_exception(vcpu))
5692 return r;
d2ddd1c4 5693 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5694 if (!vcpu->arch.pio.in) {
5695 /* FIXME: return into emulator if single-stepping. */
3457e419 5696 vcpu->arch.pio.count = 0;
0912c977 5697 } else {
7ae441ea 5698 writeback = false;
716d51ab
GN		 5699 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5700 }
ac0a48c3 5701 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5702 } else if (vcpu->mmio_needed) {
5703 if (!vcpu->mmio_is_write)
5704 writeback = false;
ac0a48c3 5705 r = EMULATE_USER_EXIT;
716d51ab 5706 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5707 } else if (r == EMULATION_RESTART)
5cd21917 5708 goto restart;
d2ddd1c4
GN		 5709 else
5710 r = EMULATE_DONE;
f850e2e6 5711
7ae441ea 5712 if (writeback) {
6addfc42 5713 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5714 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5715 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5716 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5717 if (r == EMULATE_DONE)
6addfc42 5718 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5719 if (!ctxt->have_exception ||
5720 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5721 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5722
5723 /*
5724 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5725 * do nothing, and it will be requested again as soon as
5726 * the shadow expires. But we still need to check here,
5727 * because POPF has no interrupt shadow.
5728 */
5729 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5730 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5731 } else
5732 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5733
5734 return r;
de7d789a 5735}
51d8b661 5736EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5737
cf8f70bf 5738int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5739{
cf8f70bf 5740 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5741 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5742 size, port, &val, 1);
cf8f70bf 5743 /* do not return to emulator after return from userspace */
7972995b 5744 vcpu->arch.pio.count = 0;
de7d789a
CO		 5745 return ret;
5746}
cf8f70bf 5747EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5748
8370c3d0
TL		 5749static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5750{
5751 unsigned long val;
5752
5753 /* We should only ever be called with arch.pio.count equal to 1 */
5754 BUG_ON(vcpu->arch.pio.count != 1);
5755
5756 /* For size less than 4 we merge, else we zero extend */
5757 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5758 : 0;
5759
5760 /*
5761 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5762 * the copy and tracing
5763 */
5764 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5765 vcpu->arch.pio.port, &val, 1);
5766 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5767
5768 return 1;
5769}
5770
5771int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5772{
5773 unsigned long val;
5774 int ret;
5775
5776 /* For size less than 4 we merge, else we zero extend */
5777 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5778
5779 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5780 &val, 1);
5781 if (ret) {
5782 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5783 return ret;
5784 }
5785
5786 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5787
5788 return 0;
5789}
5790EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5791
251a5fd6 5792static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5793{
0a3aee0d 5794 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5795 return 0;
8cfdc000
ZA		 5796}
5797
5798static void tsc_khz_changed(void *data)
c8076604 5799{
8cfdc000
ZA		 5800 struct cpufreq_freqs *freq = data;
5801 unsigned long khz = 0;
5802
5803 if (data)
5804 khz = freq->new;
5805 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5806 khz = cpufreq_quick_get(raw_smp_processor_id());
5807 if (!khz)
5808 khz = tsc_khz;
0a3aee0d 5809 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5810}
5811
c8076604
GH		 5812static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5813 void *data)
5814{
5815 struct cpufreq_freqs *freq = data;
5816 struct kvm *kvm;
5817 struct kvm_vcpu *vcpu;
5818 int i, send_ipi = 0;
5819
8cfdc000
ZA		 5820 /*
5821 * We allow guests to temporarily run on slowing clocks,
5822 * provided we notify them after, or to run on accelerating
5823 * clocks, provided we notify them before. Thus time never
5824 * goes backwards.
5825 *
5826 * However, we have a problem. We can't atomically update
5827 * the frequency of a given CPU from this function; it is
5828 * merely a notifier, which can be called from any CPU.
5829 * Changing the TSC frequency at arbitrary points in time
5830 * requires a recomputation of local variables related to
5831 * the TSC for each VCPU. We must flag these local variables
5832 * to be updated and be sure the update takes place with the
5833 * new frequency before any guests proceed.
5834 *
5835 * Unfortunately, the combination of hotplug CPU and frequency
5836 * change creates an intractable locking scenario; the order
5837 * of when these callouts happen is undefined with respect to
5838 * CPU hotplug, and they can race with each other. As such,
5839 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5840 * undefined; you can actually have a CPU frequency change take
5841 * place in between the computation of X and the setting of the
5842 * variable. To protect against this problem, all updates of
5843 * the per_cpu tsc_khz variable are done in an interrupt
5844 * protected IPI, and all callers wishing to update the value
5845 * must wait for a synchronous IPI to complete (which is trivial
5846 * if the caller is on the CPU already). This establishes the
5847 * necessary total order on variable updates.
5848 *
5849 * Note that because a guest time update may take place
5850 * anytime after the setting of the VCPU's request bit, the
5851 * correct TSC value must be set before the request. However,
5852 * to ensure the update actually makes it to any guest which
5853 * starts running in hardware virtualization between the set
5854 * and the acquisition of the spinlock, we must also ping the
5855 * CPU after setting the request bit.
5856 *
5857 */
5858
c8076604
GH		 5859 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5860 return 0;
5861 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5862 return 0;
8cfdc000
ZA		 5863
5864 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5865
2f303b74 5866 spin_lock(&kvm_lock);
c8076604 5867 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5868 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5869 if (vcpu->cpu != freq->cpu)
5870 continue;
c285545f 5871 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5872 if (vcpu->cpu != smp_processor_id())
8cfdc000 5873 send_ipi = 1;
c8076604
GH		 5874 }
5875 }
2f303b74 5876 spin_unlock(&kvm_lock);
c8076604
GH		 5877
5878 if (freq->old < freq->new && send_ipi) {
5879 /*
5880 * We upscale the frequency. Must make the guest
5881 * doesn't see old kvmclock values while running with
5882 * the new frequency, otherwise we risk the guest sees
5883 * time go backwards.
5884 *
5885 * In case we update the frequency for another cpu
5886 * (which might be in guest context) send an interrupt
5887 * to kick the cpu out of guest context. Next time
5888 * guest context is entered kvmclock will be updated,
5889 * so the guest will not see stale values.
5890 */
8cfdc000 5891 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5892 }
5893 return 0;
5894}
5895
5896static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5897 .notifier_call = kvmclock_cpufreq_notifier
5898};
5899
251a5fd6 5900static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5901{
251a5fd6
SAS		 5902 tsc_khz_changed(NULL);
5903 return 0;
8cfdc000
ZA		 5904}
5905
b820cc0c
ZA		 5906static void kvm_timer_init(void)
5907{
c285545f 5908 max_tsc_khz = tsc_khz;
460dd42e 5909
b820cc0c 5910 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5911#ifdef CONFIG_CPU_FREQ
5912 struct cpufreq_policy policy;
758f588d
BP		 5913 int cpu;
5914
c285545f 5915 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5916 cpu = get_cpu();
5917 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5918 if (policy.cpuinfo.max_freq)
5919 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5920 put_cpu();
c285545f 5921#endif
b820cc0c
ZA		 5922 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5923 CPUFREQ_TRANSITION_NOTIFIER);
5924 }
c285545f 5925 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5926
73c1b41e 5927 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5928 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5929}
5930
ff9d07a0
ZY		 5931static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5932
f5132b01 5933int kvm_is_in_guest(void)
ff9d07a0 5934{
086c9855 5935 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5936}
5937
5938static int kvm_is_user_mode(void)
5939{
5940 int user_mode = 3;
dcf46b94 5941
086c9855
AS		 5942 if (__this_cpu_read(current_vcpu))
5943 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5944
ff9d07a0
ZY		 5945 return user_mode != 0;
5946}
5947
5948static unsigned long kvm_get_guest_ip(void)
5949{
5950 unsigned long ip = 0;
dcf46b94 5951
086c9855
AS		 5952 if (__this_cpu_read(current_vcpu))
5953 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5954
ff9d07a0
ZY		 5955 return ip;
5956}
5957
5958static struct perf_guest_info_callbacks kvm_guest_cbs = {
5959 .is_in_guest = kvm_is_in_guest,
5960 .is_user_mode = kvm_is_user_mode,
5961 .get_guest_ip = kvm_get_guest_ip,
5962};
5963
5964void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5965{
086c9855 5966 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5967}
5968EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5969
5970void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5971{
086c9855 5972 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5973}
5974EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5975
ce88decf
XG		 5976static void kvm_set_mmio_spte_mask(void)
5977{
5978 u64 mask;
5979 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5980
5981 /*
5982 * Set the reserved bits and the present bit of an paging-structure
5983 * entry to generate page fault with PFER.RSV = 1.
5984 */
885032b9 5985 /* Mask the reserved physical address bits. */
d1431483 5986 mask = rsvd_bits(maxphyaddr, 51);
885032b9 5987
885032b9 5988 /* Set the present bit. */
ce88decf
XG		 5989 mask |= 1ull;
5990
5991#ifdef CONFIG_X86_64
5992 /*
5993 * If reserved bit is not supported, clear the present bit to disable
5994 * mmio page fault.
5995 */
5996 if (maxphyaddr == 52)
5997 mask &= ~1ull;
5998#endif
5999
6000 kvm_mmu_set_mmio_spte_mask(mask);
6001}
6002
16e8d74d
MT		 6003#ifdef CONFIG_X86_64
6004static void pvclock_gtod_update_fn(struct work_struct *work)
6005{
d828199e
MT		 6006 struct kvm *kvm;
6007
6008 struct kvm_vcpu *vcpu;
6009 int i;
6010
2f303b74 6011 spin_lock(&kvm_lock);
d828199e
MT		 6012 list_for_each_entry(kvm, &vm_list, vm_list)
6013 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6014 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6015 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6016 spin_unlock(&kvm_lock);
16e8d74d
MT		 6017}
6018
6019static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6020
6021/*
6022 * Notification about pvclock gtod data update.
6023 */
6024static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6025 void *priv)
6026{
6027 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6028 struct timekeeper *tk = priv;
6029
6030 update_pvclock_gtod(tk);
6031
6032 /* disable master clock if host does not trust, or does not
6033 * use, TSC clocksource
6034 */
6035 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6036 atomic_read(&kvm_guest_has_master_clock) != 0)
6037 queue_work(system_long_wq, &pvclock_gtod_work);
6038
6039 return 0;
6040}
6041
6042static struct notifier_block pvclock_gtod_notifier = {
6043 .notifier_call = pvclock_gtod_notify,
6044};
6045#endif
6046
f8c16bba 6047int kvm_arch_init(void *opaque)
043405e1 6048{
b820cc0c 6049 int r;
6b61edf7 6050 struct kvm_x86_ops *ops = opaque;
f8c16bba 6051
f8c16bba
ZX		 6052 if (kvm_x86_ops) {
6053 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6054 r = -EEXIST;
6055 goto out;
f8c16bba
ZX		 6056 }
6057
6058 if (!ops->cpu_has_kvm_support()) {
6059 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6060 r = -EOPNOTSUPP;
6061 goto out;
f8c16bba
ZX		 6062 }
6063 if (ops->disabled_by_bios()) {
6064 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6065 r = -EOPNOTSUPP;
6066 goto out;
f8c16bba
ZX		 6067 }
6068
013f6a5d
MT		 6069 r = -ENOMEM;
6070 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6071 if (!shared_msrs) {
6072 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6073 goto out;
6074 }
6075
97db56ce
AK		 6076 r = kvm_mmu_module_init();
6077 if (r)
013f6a5d 6078 goto out_free_percpu;
97db56ce 6079
ce88decf 6080 kvm_set_mmio_spte_mask();
97db56ce 6081
f8c16bba 6082 kvm_x86_ops = ops;
920c8377 6083
7b52345e 6084 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6085 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6086 PT_PRESENT_MASK, 0);
b820cc0c 6087 kvm_timer_init();
c8076604 6088
ff9d07a0
ZY		 6089 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6090
d366bf7e 6091 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6092 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6093
c5cc421b 6094 kvm_lapic_init();
16e8d74d
MT		 6095#ifdef CONFIG_X86_64
6096 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6097#endif
6098
f8c16bba 6099 return 0;
56c6d28a 6100
013f6a5d
MT		 6101out_free_percpu:
6102 free_percpu(shared_msrs);
56c6d28a 6103out:
56c6d28a 6104 return r;
043405e1 6105}
8776e519 6106
f8c16bba
ZX		 6107void kvm_arch_exit(void)
6108{
cef84c30 6109 kvm_lapic_exit();
ff9d07a0
ZY		 6110 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6111
888d256e
JK		 6112 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6113 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6114 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6115 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6116#ifdef CONFIG_X86_64
6117 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6118#endif
f8c16bba 6119 kvm_x86_ops = NULL;
56c6d28a 6120 kvm_mmu_module_exit();
013f6a5d 6121 free_percpu(shared_msrs);
56c6d28a 6122}
f8c16bba 6123
5cb56059 6124int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6125{
6126 ++vcpu->stat.halt_exits;
35754c98 6127 if (lapic_in_kernel(vcpu)) {
a4535290 6128 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6129 return 1;
6130 } else {
6131 vcpu->run->exit_reason = KVM_EXIT_HLT;
6132 return 0;
6133 }
6134}
5cb56059
JS		 6135EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6136
6137int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6138{
6affcbed
KH		 6139 int ret = kvm_skip_emulated_instruction(vcpu);
6140 /*
6141 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6142 * KVM_EXIT_DEBUG here.
6143 */
6144 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6145}
8776e519
HB		 6146EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6147
8ef81a9a 6148#ifdef CONFIG_X86_64
55dd00a7
MT		 6149static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6150 unsigned long clock_type)
6151{
6152 struct kvm_clock_pairing clock_pairing;
6153 struct timespec ts;
80fbd89c 6154 u64 cycle;
55dd00a7
MT		 6155 int ret;
6156
6157 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6158 return -KVM_EOPNOTSUPP;
6159
6160 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6161 return -KVM_EOPNOTSUPP;
6162
6163 clock_pairing.sec = ts.tv_sec;
6164 clock_pairing.nsec = ts.tv_nsec;
6165 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6166 clock_pairing.flags = 0;
6167
6168 ret = 0;
6169 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6170 sizeof(struct kvm_clock_pairing)))
6171 ret = -KVM_EFAULT;
6172
6173 return ret;
6174}
8ef81a9a 6175#endif
55dd00a7 6176
6aef266c
SV		 6177/*
6178 * kvm_pv_kick_cpu_op: Kick a vcpu.
6179 *
6180 * @apicid - apicid of vcpu to be kicked.
6181 */
6182static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6183{
24d2166b 6184 struct kvm_lapic_irq lapic_irq;
6aef266c 6185
24d2166b
R		 6186 lapic_irq.shorthand = 0;
6187 lapic_irq.dest_mode = 0;
6188 lapic_irq.dest_id = apicid;
93bbf0b8 6189 lapic_irq.msi_redir_hint = false;
6aef266c 6190
24d2166b 6191 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6192 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6193}
6194
d62caabb
AS		 6195void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6196{
6197 vcpu->arch.apicv_active = false;
6198 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6199}
6200
8776e519
HB		 6201int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6202{
6203 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6204 int op_64_bit, r;
8776e519 6205
6affcbed 6206 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6207
55cd8e5a
GN		 6208 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6209 return kvm_hv_hypercall(vcpu);
6210
5fdbf976
MT		 6211 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6212 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6213 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6214 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6215 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6216
229456fc 6217 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6218
a449c7aa
NA		 6219 op_64_bit = is_64_bit_mode(vcpu);
6220 if (!op_64_bit) {
8776e519
HB		 6221 nr &= 0xFFFFFFFF;
6222 a0 &= 0xFFFFFFFF;
6223 a1 &= 0xFFFFFFFF;
6224 a2 &= 0xFFFFFFFF;
6225 a3 &= 0xFFFFFFFF;
6226 }
6227
07708c4a
JK		 6228 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6229 ret = -KVM_EPERM;
6230 goto out;
6231 }
6232
8776e519 6233 switch (nr) {
b93463aa
AK		 6234 case KVM_HC_VAPIC_POLL_IRQ:
6235 ret = 0;
6236 break;
6aef266c
SV		 6237 case KVM_HC_KICK_CPU:
6238 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6239 ret = 0;
6240 break;
8ef81a9a 6241#ifdef CONFIG_X86_64
55dd00a7
MT		 6242 case KVM_HC_CLOCK_PAIRING:
6243 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6244 break;
8ef81a9a 6245#endif
8776e519
HB		 6246 default:
6247 ret = -KVM_ENOSYS;
6248 break;
6249 }
07708c4a 6250out:
a449c7aa
NA		 6251 if (!op_64_bit)
6252 ret = (u32)ret;
5fdbf976 6253 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6254 ++vcpu->stat.hypercalls;
2f333bcb 6255 return r;
8776e519
HB		 6256}
6257EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6258
b6785def 6259static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6260{
d6aa1000 6261 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6262 char instruction[3];
5fdbf976 6263 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6264
8776e519 6265 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6266
ce2e852e
DV		 6267 return emulator_write_emulated(ctxt, rip, instruction, 3,
6268 &ctxt->exception);
8776e519
HB		 6269}
6270
851ba692 6271static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6272{
782d422b
MG		 6273 return vcpu->run->request_interrupt_window &&
6274 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6275}
6276
851ba692 6277static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6278{
851ba692
AK		 6279 struct kvm_run *kvm_run = vcpu->run;
6280
91586a3b 6281 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6282 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6283 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6284 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6285 kvm_run->ready_for_interrupt_injection =
6286 pic_in_kernel(vcpu->kvm) ||
782d422b 6287 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6288}
6289
95ba8273
GN		 6290static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6291{
6292 int max_irr, tpr;
6293
6294 if (!kvm_x86_ops->update_cr8_intercept)
6295 return;
6296
bce87cce 6297 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6298 return;
6299
d62caabb
AS		 6300 if (vcpu->arch.apicv_active)
6301 return;
6302
8db3baa2
GN		 6303 if (!vcpu->arch.apic->vapic_addr)
6304 max_irr = kvm_lapic_find_highest_irr(vcpu);
6305 else
6306 max_irr = -1;
95ba8273
GN		 6307
6308 if (max_irr != -1)
6309 max_irr >>= 4;
6310
6311 tpr = kvm_lapic_get_cr8(vcpu);
6312
6313 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6314}
6315
b6b8a145 6316static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6317{
b6b8a145
JK		 6318 int r;
6319
95ba8273 6320 /* try to reinject previous events if any */
b59bb7bd 6321 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6322 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6323 vcpu->arch.exception.has_error_code,
6324 vcpu->arch.exception.error_code);
d6e8c854
NA		 6325
6326 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6327 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6328 X86_EFLAGS_RF);
6329
6bdf0662
NA		 6330 if (vcpu->arch.exception.nr == DB_VECTOR &&
6331 (vcpu->arch.dr7 & DR7_GD)) {
6332 vcpu->arch.dr7 &= ~DR7_GD;
6333 kvm_update_dr7(vcpu);
6334 }
6335
b59bb7bd
GN		 6336 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6337 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6338 vcpu->arch.exception.error_code,
6339 vcpu->arch.exception.reinject);
b6b8a145 6340 return 0;
b59bb7bd
GN		 6341 }
6342
95ba8273
GN		 6343 if (vcpu->arch.nmi_injected) {
6344 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6345 return 0;
95ba8273
GN		 6346 }
6347
6348 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6349 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6350 return 0;
6351 }
6352
6353 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6354 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6355 if (r != 0)
6356 return r;
95ba8273
GN		 6357 }
6358
6359 /* try to inject new event if pending */
c43203ca
PB		 6360 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6361 vcpu->arch.smi_pending = false;
ee2cd4b7 6362 enter_smm(vcpu);
c43203ca 6363 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6364 --vcpu->arch.nmi_pending;
6365 vcpu->arch.nmi_injected = true;
6366 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6367 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6368 /*
6369 * Because interrupts can be injected asynchronously, we are
6370 * calling check_nested_events again here to avoid a race condition.
6371 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6372 * proposal and current concerns. Perhaps we should be setting
6373 * KVM_REQ_EVENT only on certain events and not unconditionally?
6374 */
6375 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6376 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6377 if (r != 0)
6378 return r;
6379 }
95ba8273 6380 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6381 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6382 false);
6383 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6384 }
6385 }
ee2cd4b7 6386
b6b8a145 6387 return 0;
95ba8273
GN		 6388}
6389
7460fb4a
AK		 6390static void process_nmi(struct kvm_vcpu *vcpu)
6391{
6392 unsigned limit = 2;
6393
6394 /*
6395 * x86 is limited to one NMI running, and one NMI pending after it.
6396 * If an NMI is already in progress, limit further NMIs to just one.
6397 * Otherwise, allow two (and we'll inject the first one immediately).
6398 */
6399 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6400 limit = 1;
6401
6402 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6403 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6404 kvm_make_request(KVM_REQ_EVENT, vcpu);
6405}
6406
660a5d51
PB		 6407#define put_smstate(type, buf, offset, val) \
6408 *(type *)((buf) + (offset) - 0x7e00) = val
6409
ee2cd4b7 6410static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6411{
6412 u32 flags = 0;
6413 flags |= seg->g << 23;
6414 flags |= seg->db << 22;
6415 flags |= seg->l << 21;
6416 flags |= seg->avl << 20;
6417 flags |= seg->present << 15;
6418 flags |= seg->dpl << 13;
6419 flags |= seg->s << 12;
6420 flags |= seg->type << 8;
6421 return flags;
6422}
6423
ee2cd4b7 6424static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6425{
6426 struct kvm_segment seg;
6427 int offset;
6428
6429 kvm_get_segment(vcpu, &seg, n);
6430 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6431
6432 if (n < 3)
6433 offset = 0x7f84 + n * 12;
6434 else
6435 offset = 0x7f2c + (n - 3) * 12;
6436
6437 put_smstate(u32, buf, offset + 8, seg.base);
6438 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6439 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6440}
6441
efbb288a 6442#ifdef CONFIG_X86_64
ee2cd4b7 6443static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6444{
6445 struct kvm_segment seg;
6446 int offset;
6447 u16 flags;
6448
6449 kvm_get_segment(vcpu, &seg, n);
6450 offset = 0x7e00 + n * 16;
6451
ee2cd4b7 6452 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6453 put_smstate(u16, buf, offset, seg.selector);
6454 put_smstate(u16, buf, offset + 2, flags);
6455 put_smstate(u32, buf, offset + 4, seg.limit);
6456 put_smstate(u64, buf, offset + 8, seg.base);
6457}
efbb288a 6458#endif
660a5d51 6459
ee2cd4b7 6460static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6461{
6462 struct desc_ptr dt;
6463 struct kvm_segment seg;
6464 unsigned long val;
6465 int i;
6466
6467 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6468 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6469 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6470 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6471
6472 for (i = 0; i < 8; i++)
6473 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6474
6475 kvm_get_dr(vcpu, 6, &val);
6476 put_smstate(u32, buf, 0x7fcc, (u32)val);
6477 kvm_get_dr(vcpu, 7, &val);
6478 put_smstate(u32, buf, 0x7fc8, (u32)val);
6479
6480 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6481 put_smstate(u32, buf, 0x7fc4, seg.selector);
6482 put_smstate(u32, buf, 0x7f64, seg.base);
6483 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6484 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6485
6486 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6487 put_smstate(u32, buf, 0x7fc0, seg.selector);
6488 put_smstate(u32, buf, 0x7f80, seg.base);
6489 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6490 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6491
6492 kvm_x86_ops->get_gdt(vcpu, &dt);
6493 put_smstate(u32, buf, 0x7f74, dt.address);
6494 put_smstate(u32, buf, 0x7f70, dt.size);
6495
6496 kvm_x86_ops->get_idt(vcpu, &dt);
6497 put_smstate(u32, buf, 0x7f58, dt.address);
6498 put_smstate(u32, buf, 0x7f54, dt.size);
6499
6500 for (i = 0; i < 6; i++)
ee2cd4b7 6501 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6502
6503 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6504
6505 /* revision id */
6506 put_smstate(u32, buf, 0x7efc, 0x00020000);
6507 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6508}
6509
ee2cd4b7 6510static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6511{
6512#ifdef CONFIG_X86_64
6513 struct desc_ptr dt;
6514 struct kvm_segment seg;
6515 unsigned long val;
6516 int i;
6517
6518 for (i = 0; i < 16; i++)
6519 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6520
6521 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6522 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6523
6524 kvm_get_dr(vcpu, 6, &val);
6525 put_smstate(u64, buf, 0x7f68, val);
6526 kvm_get_dr(vcpu, 7, &val);
6527 put_smstate(u64, buf, 0x7f60, val);
6528
6529 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6530 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6531 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6532
6533 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6534
6535 /* revision id */
6536 put_smstate(u32, buf, 0x7efc, 0x00020064);
6537
6538 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6539
6540 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6541 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6542 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6543 put_smstate(u32, buf, 0x7e94, seg.limit);
6544 put_smstate(u64, buf, 0x7e98, seg.base);
6545
6546 kvm_x86_ops->get_idt(vcpu, &dt);
6547 put_smstate(u32, buf, 0x7e84, dt.size);
6548 put_smstate(u64, buf, 0x7e88, dt.address);
6549
6550 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6551 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6552 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6553 put_smstate(u32, buf, 0x7e74, seg.limit);
6554 put_smstate(u64, buf, 0x7e78, seg.base);
6555
6556 kvm_x86_ops->get_gdt(vcpu, &dt);
6557 put_smstate(u32, buf, 0x7e64, dt.size);
6558 put_smstate(u64, buf, 0x7e68, dt.address);
6559
6560 for (i = 0; i < 6; i++)
ee2cd4b7 6561 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6562#else
6563 WARN_ON_ONCE(1);
6564#endif
6565}
6566
ee2cd4b7 6567static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6568{
660a5d51 6569 struct kvm_segment cs, ds;
18c3626e 6570 struct desc_ptr dt;
660a5d51
PB		 6571 char buf[512];
6572 u32 cr0;
6573
660a5d51
PB		 6574 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6575 vcpu->arch.hflags |= HF_SMM_MASK;
6576 memset(buf, 0, 512);
6577 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6578 enter_smm_save_state_64(vcpu, buf);
660a5d51 6579 else
ee2cd4b7 6580 enter_smm_save_state_32(vcpu, buf);
660a5d51 6581
54bf36aa 6582 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6583
6584 if (kvm_x86_ops->get_nmi_mask(vcpu))
6585 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6586 else
6587 kvm_x86_ops->set_nmi_mask(vcpu, true);
6588
6589 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6590 kvm_rip_write(vcpu, 0x8000);
6591
6592 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6593 kvm_x86_ops->set_cr0(vcpu, cr0);
6594 vcpu->arch.cr0 = cr0;
6595
6596 kvm_x86_ops->set_cr4(vcpu, 0);
6597
18c3626e
PB		 6598 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6599 dt.address = dt.size = 0;
6600 kvm_x86_ops->set_idt(vcpu, &dt);
6601
660a5d51
PB		 6602 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6603
6604 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6605 cs.base = vcpu->arch.smbase;
6606
6607 ds.selector = 0;
6608 ds.base = 0;
6609
6610 cs.limit = ds.limit = 0xffffffff;
6611 cs.type = ds.type = 0x3;
6612 cs.dpl = ds.dpl = 0;
6613 cs.db = ds.db = 0;
6614 cs.s = ds.s = 1;
6615 cs.l = ds.l = 0;
6616 cs.g = ds.g = 1;
6617 cs.avl = ds.avl = 0;
6618 cs.present = ds.present = 1;
6619 cs.unusable = ds.unusable = 0;
6620 cs.padding = ds.padding = 0;
6621
6622 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6623 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6624 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6625 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6626 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6627 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6628
6629 if (guest_cpuid_has_longmode(vcpu))
6630 kvm_x86_ops->set_efer(vcpu, 0);
6631
6632 kvm_update_cpuid(vcpu);
6633 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6634}
6635
ee2cd4b7 6636static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6637{
6638 vcpu->arch.smi_pending = true;
6639 kvm_make_request(KVM_REQ_EVENT, vcpu);
6640}
6641
2860c4b1
PB		 6642void kvm_make_scan_ioapic_request(struct kvm *kvm)
6643{
6644 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6645}
6646
3d81bc7e 6647static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6648{
5c919412
AS		 6649 u64 eoi_exit_bitmap[4];
6650
3d81bc7e
YZ		 6651 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6652 return;
c7c9c56c 6653
6308630b 6654 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6655
b053b2ae 6656 if (irqchip_split(vcpu->kvm))
6308630b 6657 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6658 else {
76dfafd5 6659 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6660 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6661 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6662 }
5c919412
AS		 6663 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6664 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6665 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6666}
6667
a70656b6
RK		 6668static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6669{
6670 ++vcpu->stat.tlb_flush;
6671 kvm_x86_ops->tlb_flush(vcpu);
6672}
6673
4256f43f
TC		 6674void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6675{
c24ae0dc
TC		 6676 struct page *page = NULL;
6677
35754c98 6678 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6679 return;
6680
4256f43f
TC		 6681 if (!kvm_x86_ops->set_apic_access_page_addr)
6682 return;
6683
c24ae0dc 6684 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6685 if (is_error_page(page))
6686 return;
c24ae0dc
TC		 6687 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6688
6689 /*
6690 * Do not pin apic access page in memory, the MMU notifier
6691 * will call us again if it is migrated or swapped out.
6692 */
6693 put_page(page);
4256f43f
TC		 6694}
6695EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6696
fe71557a
TC		 6697void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6698 unsigned long address)
6699{
c24ae0dc
TC		 6700 /*
6701 * The physical address of apic access page is stored in the VMCS.
6702 * Update it when it becomes invalid.
6703 */
6704 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6705 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6706}
6707
9357d939 6708/*
362c698f 6709 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6710 * exiting to the userspace. Otherwise, the value will be returned to the
6711 * userspace.
6712 */
851ba692 6713static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6714{
6715 int r;
62a193ed
MG		 6716 bool req_int_win =
6717 dm_request_for_irq_injection(vcpu) &&
6718 kvm_cpu_accept_dm_intr(vcpu);
6719
730dca42 6720 bool req_immediate_exit = false;
b6c7a5dc 6721
3e007509 6722 if (vcpu->requests) {
a8eeb04a 6723 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6724 kvm_mmu_unload(vcpu);
a8eeb04a 6725 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6726 __kvm_migrate_timers(vcpu);
d828199e
MT		 6727 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6728 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6729 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6730 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6731 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6732 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6733 if (unlikely(r))
6734 goto out;
6735 }
a8eeb04a 6736 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6737 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6738 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6739 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6740 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6741 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6742 r = 0;
6743 goto out;
6744 }
a8eeb04a 6745 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6746 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6747 r = 0;
6748 goto out;
6749 }
af585b92
GN		 6750 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6751 /* Page is swapped out. Do synthetic halt */
6752 vcpu->arch.apf.halted = true;
6753 r = 1;
6754 goto out;
6755 }
c9aaa895
GC		 6756 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6757 record_steal_time(vcpu);
64d60670
PB		 6758 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6759 process_smi(vcpu);
7460fb4a
AK		 6760 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6761 process_nmi(vcpu);
f5132b01 6762 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6763 kvm_pmu_handle_event(vcpu);
f5132b01 6764 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6765 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6766 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6767 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6768 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6769 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6770 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6771 vcpu->run->eoi.vector =
6772 vcpu->arch.pending_ioapic_eoi;
6773 r = 0;
6774 goto out;
6775 }
6776 }
3d81bc7e
YZ		 6777 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6778 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6779 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6780 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6781 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6782 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6783 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6784 r = 0;
6785 goto out;
6786 }
e516cebb
AS		 6787 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6788 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6789 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6790 r = 0;
6791 goto out;
6792 }
db397571
AS		 6793 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6794 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6795 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6796 r = 0;
6797 goto out;
6798 }
f3b138c5
AS		 6799
6800 /*
6801 * KVM_REQ_HV_STIMER has to be processed after
6802 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6803 * depend on the guest clock being up-to-date
6804 */
1f4b34f8
AS		 6805 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6806 kvm_hv_process_stimers(vcpu);
2f52d58c 6807 }
b93463aa 6808
b463a6f7 6809 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6810 ++vcpu->stat.req_event;
66450a21
JK		 6811 kvm_apic_accept_events(vcpu);
6812 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6813 r = 1;
6814 goto out;
6815 }
6816
b6b8a145
JK		 6817 if (inject_pending_event(vcpu, req_int_win) != 0)
6818 req_immediate_exit = true;
321c5658 6819 else {
c43203ca
PB		 6820 /* Enable NMI/IRQ window open exits if needed.
6821 *
6822 * SMIs have two cases: 1) they can be nested, and
6823 * then there is nothing to do here because RSM will
6824 * cause a vmexit anyway; 2) or the SMI can be pending
6825 * because inject_pending_event has completed the
6826 * injection of an IRQ or NMI from the previous vmexit,
6827 * and then we request an immediate exit to inject the SMI.
6828 */
6829 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6830 req_immediate_exit = true;
321c5658
YS		 6831 if (vcpu->arch.nmi_pending)
6832 kvm_x86_ops->enable_nmi_window(vcpu);
6833 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6834 kvm_x86_ops->enable_irq_window(vcpu);
6835 }
b463a6f7
AK		 6836
6837 if (kvm_lapic_enabled(vcpu)) {
6838 update_cr8_intercept(vcpu);
6839 kvm_lapic_sync_to_vapic(vcpu);
6840 }
6841 }
6842
d8368af8
AK		 6843 r = kvm_mmu_reload(vcpu);
6844 if (unlikely(r)) {
d905c069 6845 goto cancel_injection;
d8368af8
AK		 6846 }
6847
b6c7a5dc
HB		 6848 preempt_disable();
6849
6850 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6851 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6852
6853 /*
6854 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6855 * IPI are then delayed after guest entry, which ensures that they
6856 * result in virtual interrupt delivery.
6857 */
6858 local_irq_disable();
6b7e2d09
XG		 6859 vcpu->mode = IN_GUEST_MODE;
6860
01b71917
MT		 6861 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6862
0f127d12 6863 /*
b95234c8 6864 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6865 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6866 *
6867 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6868 * pairs with the memory barrier implicit in pi_test_and_set_on
6869 * (see vmx_deliver_posted_interrupt).
6870 *
6871 * 3) This also orders the write to mode from any reads to the page
6872 * tables done while the VCPU is running. Please see the comment
6873 * in kvm_flush_remote_tlbs.
6b7e2d09 6874 */
01b71917 6875 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6876
b95234c8
PB		 6877 /*
6878 * This handles the case where a posted interrupt was
6879 * notified with kvm_vcpu_kick.
6880 */
6881 if (kvm_lapic_enabled(vcpu)) {
6882 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6883 kvm_x86_ops->sync_pir_to_irr(vcpu);
6884 }
32f88400 6885
6b7e2d09 6886 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6887 || need_resched() || signal_pending(current)) {
6b7e2d09 6888 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6889 smp_wmb();
6c142801
AK		 6890 local_irq_enable();
6891 preempt_enable();
01b71917 6892 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6893 r = 1;
d905c069 6894 goto cancel_injection;
6c142801
AK		 6895 }
6896
fc5b7f3b
DM		 6897 kvm_load_guest_xcr0(vcpu);
6898
c43203ca
PB		 6899 if (req_immediate_exit) {
6900 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6901 smp_send_reschedule(vcpu->cpu);
c43203ca 6902 }
d6185f20 6903
8b89fe1f
PB		 6904 trace_kvm_entry(vcpu->vcpu_id);
6905 wait_lapic_expire(vcpu);
6edaa530 6906 guest_enter_irqoff();
b6c7a5dc 6907
42dbaa5a 6908 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6909 set_debugreg(0, 7);
6910 set_debugreg(vcpu->arch.eff_db[0], 0);
6911 set_debugreg(vcpu->arch.eff_db[1], 1);
6912 set_debugreg(vcpu->arch.eff_db[2], 2);
6913 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6914 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6915 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6916 }
b6c7a5dc 6917
851ba692 6918 kvm_x86_ops->run(vcpu);
b6c7a5dc 6919
c77fb5fe
PB		 6920 /*
6921 * Do this here before restoring debug registers on the host. And
6922 * since we do this before handling the vmexit, a DR access vmexit
6923 * can (a) read the correct value of the debug registers, (b) set
6924 * KVM_DEBUGREG_WONT_EXIT again.
6925 */
6926 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6927 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6928 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6929 kvm_update_dr0123(vcpu);
6930 kvm_update_dr6(vcpu);
6931 kvm_update_dr7(vcpu);
6932 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6933 }
6934
24f1e32c
FW		 6935 /*
6936 * If the guest has used debug registers, at least dr7
6937 * will be disabled while returning to the host.
6938 * If we don't have active breakpoints in the host, we don't
6939 * care about the messed up debug address registers. But if
6940 * we have some of them active, restore the old state.
6941 */
59d8eb53 6942 if (hw_breakpoint_active())
24f1e32c 6943 hw_breakpoint_restore();
42dbaa5a 6944
4ba76538 6945 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6946
6b7e2d09 6947 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6948 smp_wmb();
a547c6db 6949
fc5b7f3b
DM		 6950 kvm_put_guest_xcr0(vcpu);
6951
a547c6db 6952 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6953
6954 ++vcpu->stat.exits;
6955
f2485b3e 6956 guest_exit_irqoff();
b6c7a5dc 6957
f2485b3e 6958 local_irq_enable();
b6c7a5dc
HB		 6959 preempt_enable();
6960
f656ce01 6961 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6962
b6c7a5dc
HB		 6963 /*
6964 * Profile KVM exit RIPs:
6965 */
6966 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6967 unsigned long rip = kvm_rip_read(vcpu);
6968 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6969 }
6970
cc578287
ZA		 6971 if (unlikely(vcpu->arch.tsc_always_catchup))
6972 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6973
5cfb1d5a
MT		 6974 if (vcpu->arch.apic_attention)
6975 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6976
851ba692 6977 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6978 return r;
6979
6980cancel_injection:
6981 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6982 if (unlikely(vcpu->arch.apic_attention))
6983 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6984out:
6985 return r;
6986}
b6c7a5dc 6987
362c698f
PB		 6988static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6989{
bf9f6ac8
FW		 6990 if (!kvm_arch_vcpu_runnable(vcpu) &&
6991 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6992 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6993 kvm_vcpu_block(vcpu);
6994 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6995
6996 if (kvm_x86_ops->post_block)
6997 kvm_x86_ops->post_block(vcpu);
6998
9c8fd1ba
PB		 6999 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7000 return 1;
7001 }
362c698f
PB		 7002
7003 kvm_apic_accept_events(vcpu);
7004 switch(vcpu->arch.mp_state) {
7005 case KVM_MP_STATE_HALTED:
7006 vcpu->arch.pv.pv_unhalted = false;
7007 vcpu->arch.mp_state =
7008 KVM_MP_STATE_RUNNABLE;
7009 case KVM_MP_STATE_RUNNABLE:
7010 vcpu->arch.apf.halted = false;
7011 break;
7012 case KVM_MP_STATE_INIT_RECEIVED:
7013 break;
7014 default:
7015 return -EINTR;
7016 break;
7017 }
7018 return 1;
7019}
09cec754 7020
5d9bc648
PB		 7021static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7022{
0ad3bed6
PB		 7023 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7024 kvm_x86_ops->check_nested_events(vcpu, false);
7025
5d9bc648
PB		 7026 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7027 !vcpu->arch.apf.halted);
7028}
7029
362c698f 7030static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7031{
7032 int r;
f656ce01 7033 struct kvm *kvm = vcpu->kvm;
d7690175 7034
f656ce01 7035 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7036
362c698f 7037 for (;;) {
58f800d5 7038 if (kvm_vcpu_running(vcpu)) {
851ba692 7039 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7040 } else {
362c698f 7041 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7042 }
7043
09cec754
GN		 7044 if (r <= 0)
7045 break;
7046
72875d8a 7047 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7048 if (kvm_cpu_has_pending_timer(vcpu))
7049 kvm_inject_pending_timer_irqs(vcpu);
7050
782d422b
MG		 7051 if (dm_request_for_irq_injection(vcpu) &&
7052 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7053 r = 0;
7054 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7055 ++vcpu->stat.request_irq_exits;
362c698f 7056 break;
09cec754 7057 }
af585b92
GN		 7058
7059 kvm_check_async_pf_completion(vcpu);
7060
09cec754
GN		 7061 if (signal_pending(current)) {
7062 r = -EINTR;
851ba692 7063 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7064 ++vcpu->stat.signal_exits;
362c698f 7065 break;
09cec754
GN		 7066 }
7067 if (need_resched()) {
f656ce01 7068 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7069 cond_resched();
f656ce01 7070 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7071 }
b6c7a5dc
HB		 7072 }
7073
f656ce01 7074 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7075
7076 return r;
7077}
7078
716d51ab
GN		 7079static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7080{
7081 int r;
7082 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7083 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7084 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7085 if (r != EMULATE_DONE)
7086 return 0;
7087 return 1;
7088}
7089
7090static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7091{
7092 BUG_ON(!vcpu->arch.pio.count);
7093
7094 return complete_emulated_io(vcpu);
7095}
7096
f78146b0
AK		 7097/*
7098 * Implements the following, as a state machine:
7099 *
7100 * read:
7101 * for each fragment
87da7e66
XG		 7102 * for each mmio piece in the fragment
7103 * write gpa, len
7104 * exit
7105 * copy data
f78146b0
AK		 7106 * execute insn
7107 *
7108 * write:
7109 * for each fragment
87da7e66
XG		 7110 * for each mmio piece in the fragment
7111 * write gpa, len
7112 * copy data
7113 * exit
f78146b0 7114 */
716d51ab 7115static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7116{
7117 struct kvm_run *run = vcpu->run;
f78146b0 7118 struct kvm_mmio_fragment *frag;
87da7e66 7119 unsigned len;
5287f194 7120
716d51ab 7121 BUG_ON(!vcpu->mmio_needed);
5287f194 7122
716d51ab 7123 /* Complete previous fragment */
87da7e66
XG		 7124 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7125 len = min(8u, frag->len);
716d51ab 7126 if (!vcpu->mmio_is_write)
87da7e66
XG		 7127 memcpy(frag->data, run->mmio.data, len);
7128
7129 if (frag->len <= 8) {
7130 /* Switch to the next fragment. */
7131 frag++;
7132 vcpu->mmio_cur_fragment++;
7133 } else {
7134 /* Go forward to the next mmio piece. */
7135 frag->data += len;
7136 frag->gpa += len;
7137 frag->len -= len;
7138 }
7139
a08d3b3b 7140 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7141 vcpu->mmio_needed = 0;
0912c977
PB		 7142
7143 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7144 if (vcpu->mmio_is_write)
716d51ab
GN		 7145 return 1;
7146 vcpu->mmio_read_completed = 1;
7147 return complete_emulated_io(vcpu);
7148 }
87da7e66 7149
716d51ab
GN		 7150 run->exit_reason = KVM_EXIT_MMIO;
7151 run->mmio.phys_addr = frag->gpa;
7152 if (vcpu->mmio_is_write)
87da7e66
XG		 7153 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7154 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7155 run->mmio.is_write = vcpu->mmio_is_write;
7156 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7157 return 0;
5287f194
AK		 7158}
7159
716d51ab 7160
b6c7a5dc
HB		 7161int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7162{
c5bedc68 7163 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7164 int r;
7165 sigset_t sigsaved;
7166
c4d72e2d 7167 fpu__activate_curr(fpu);
e5c30142 7168
ac9f6dc0
AK		 7169 if (vcpu->sigset_active)
7170 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7171
a4535290 7172 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7173 kvm_vcpu_block(vcpu);
66450a21 7174 kvm_apic_accept_events(vcpu);
72875d8a 7175 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0
AK		 7176 r = -EAGAIN;
7177 goto out;
b6c7a5dc
HB		 7178 }
7179
b6c7a5dc 7180 /* re-sync apic's tpr */
35754c98 7181 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7182 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7183 r = -EINVAL;
7184 goto out;
7185 }
7186 }
b6c7a5dc 7187
716d51ab
GN		 7188 if (unlikely(vcpu->arch.complete_userspace_io)) {
7189 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7190 vcpu->arch.complete_userspace_io = NULL;
7191 r = cui(vcpu);
7192 if (r <= 0)
7193 goto out;
7194 } else
7195 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7196
460df4c1
PB		 7197 if (kvm_run->immediate_exit)
7198 r = -EINTR;
7199 else
7200 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7201
7202out:
f1d86e46 7203 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7204 if (vcpu->sigset_active)
7205 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7206
b6c7a5dc
HB		 7207 return r;
7208}
7209
7210int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7211{
7ae441ea
GN		 7212 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7213 /*
7214 * We are here if userspace calls get_regs() in the middle of
7215 * instruction emulation. Registers state needs to be copied
4a969980 7216 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7217 * that usually, but some bad designed PV devices (vmware
7218 * backdoor interface) need this to work
7219 */
dd856efa 7220 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7221 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7222 }
5fdbf976
MT		 7223 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7224 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7225 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7226 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7227 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7228 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7229 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7230 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7231#ifdef CONFIG_X86_64
5fdbf976
MT		 7232 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7233 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7234 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7235 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7236 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7237 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7238 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7239 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7240#endif
7241
5fdbf976 7242 regs->rip = kvm_rip_read(vcpu);
91586a3b 7243 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7244
b6c7a5dc
HB		 7245 return 0;
7246}
7247
7248int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7249{
7ae441ea
GN		 7250 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7251 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7252
5fdbf976
MT		 7253 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7254 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7255 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7256 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7257 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7258 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7259 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7260 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7261#ifdef CONFIG_X86_64
5fdbf976
MT		 7262 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7263 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7264 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7265 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7266 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7267 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7268 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7269 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7270#endif
7271
5fdbf976 7272 kvm_rip_write(vcpu, regs->rip);
91586a3b 7273 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7274
b4f14abd
JK		 7275 vcpu->arch.exception.pending = false;
7276
3842d135
AK		 7277 kvm_make_request(KVM_REQ_EVENT, vcpu);
7278
b6c7a5dc
HB		 7279 return 0;
7280}
7281
b6c7a5dc
HB		 7282void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7283{
7284 struct kvm_segment cs;
7285
3e6e0aab 7286 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7287 *db = cs.db;
7288 *l = cs.l;
7289}
7290EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7291
7292int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7293 struct kvm_sregs *sregs)
7294{
89a27f4d 7295 struct desc_ptr dt;
b6c7a5dc 7296
3e6e0aab
GT		 7297 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7298 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7299 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7300 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7301 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7302 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7303
3e6e0aab
GT		 7304 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7305 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7306
7307 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7308 sregs->idt.limit = dt.size;
7309 sregs->idt.base = dt.address;
b6c7a5dc 7310 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7311 sregs->gdt.limit = dt.size;
7312 sregs->gdt.base = dt.address;
b6c7a5dc 7313
4d4ec087 7314 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7315 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7316 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7317 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7318 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7319 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7320 sregs->apic_base = kvm_get_apic_base(vcpu);
7321
923c61bb 7322 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7323
36752c9b 7324 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7325 set_bit(vcpu->arch.interrupt.nr,
7326 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7327
b6c7a5dc
HB		 7328 return 0;
7329}
7330
62d9f0db
MT		 7331int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7332 struct kvm_mp_state *mp_state)
7333{
66450a21 7334 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7335 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7336 vcpu->arch.pv.pv_unhalted)
7337 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7338 else
7339 mp_state->mp_state = vcpu->arch.mp_state;
7340
62d9f0db
MT		 7341 return 0;
7342}
7343
7344int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7345 struct kvm_mp_state *mp_state)
7346{
bce87cce 7347 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7348 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7349 return -EINVAL;
7350
28bf2888
DH		 7351 /* INITs are latched while in SMM */
7352 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7353 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7354 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7355 return -EINVAL;
7356
66450a21
JK		 7357 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7358 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7359 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7360 } else
7361 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7362 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7363 return 0;
7364}
7365
7f3d35fd
KW		 7366int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7367 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7368{
9d74191a 7369 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7370 int ret;
e01c2426 7371
8ec4722d 7372 init_emulate_ctxt(vcpu);
c697518a 7373
7f3d35fd 7374 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7375 has_error_code, error_code);
c697518a 7376
c697518a 7377 if (ret)
19d04437 7378 return EMULATE_FAIL;
37817f29 7379
9d74191a
TY		 7380 kvm_rip_write(vcpu, ctxt->eip);
7381 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7382 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7383 return EMULATE_DONE;
37817f29
IE		 7384}
7385EXPORT_SYMBOL_GPL(kvm_task_switch);
7386
b6c7a5dc
HB		 7387int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7388 struct kvm_sregs *sregs)
7389{
58cb628d 7390 struct msr_data apic_base_msr;
b6c7a5dc 7391 int mmu_reset_needed = 0;
63f42e02 7392 int pending_vec, max_bits, idx;
89a27f4d 7393 struct desc_ptr dt;
b6c7a5dc 7394
6d1068b3
PM		 7395 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7396 return -EINVAL;
7397
89a27f4d
GN		 7398 dt.size = sregs->idt.limit;
7399 dt.address = sregs->idt.base;
b6c7a5dc 7400 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7401 dt.size = sregs->gdt.limit;
7402 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7403 kvm_x86_ops->set_gdt(vcpu, &dt);
7404
ad312c7c 7405 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7406 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7407 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7408 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7409
2d3ad1f4 7410 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7411
f6801dff 7412 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7413 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7414 apic_base_msr.data = sregs->apic_base;
7415 apic_base_msr.host_initiated = true;
7416 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7417
4d4ec087 7418 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7419 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7420 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7421
fc78f519 7422 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7423 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7424 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7425 kvm_update_cpuid(vcpu);
63f42e02
XG		 7426
7427 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7428 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7429 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7430 mmu_reset_needed = 1;
7431 }
63f42e02 7432 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7433
7434 if (mmu_reset_needed)
7435 kvm_mmu_reset_context(vcpu);
7436
a50abc3b 7437 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7438 pending_vec = find_first_bit(
7439 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7440 if (pending_vec < max_bits) {
66fd3f7f 7441 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7442 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7443 }
7444
3e6e0aab
GT		 7445 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7446 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7447 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7448 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7449 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7450 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7451
3e6e0aab
GT		 7452 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7453 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7454
5f0269f5
ME		 7455 update_cr8_intercept(vcpu);
7456
9c3e4aab 7457 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7458 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7459 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7460 !is_protmode(vcpu))
9c3e4aab
MT		 7461 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7462
3842d135
AK		 7463 kvm_make_request(KVM_REQ_EVENT, vcpu);
7464
b6c7a5dc
HB		 7465 return 0;
7466}
7467
d0bfb940
JK		 7468int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7469 struct kvm_guest_debug *dbg)
b6c7a5dc 7470{
355be0b9 7471 unsigned long rflags;
ae675ef0 7472 int i, r;
b6c7a5dc 7473
4f926bf2
JK		 7474 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7475 r = -EBUSY;
7476 if (vcpu->arch.exception.pending)
2122ff5e 7477 goto out;
4f926bf2
JK		 7478 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7479 kvm_queue_exception(vcpu, DB_VECTOR);
7480 else
7481 kvm_queue_exception(vcpu, BP_VECTOR);
7482 }
7483
91586a3b
JK		 7484 /*
7485 * Read rflags as long as potentially injected trace flags are still
7486 * filtered out.
7487 */
7488 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7489
7490 vcpu->guest_debug = dbg->control;
7491 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7492 vcpu->guest_debug = 0;
7493
7494 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7495 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7496 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7497 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7498 } else {
7499 for (i = 0; i < KVM_NR_DB_REGS; i++)
7500 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7501 }
c8639010 7502 kvm_update_dr7(vcpu);
ae675ef0 7503
f92653ee
JK		 7504 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7505 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7506 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7507
91586a3b
JK		 7508 /*
7509 * Trigger an rflags update that will inject or remove the trace
7510 * flags.
7511 */
7512 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7513
a96036b8 7514 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7515
4f926bf2 7516 r = 0;
d0bfb940 7517
2122ff5e 7518out:
b6c7a5dc
HB		 7519
7520 return r;
7521}
7522
8b006791
ZX		 7523/*
7524 * Translate a guest virtual address to a guest physical address.
7525 */
7526int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7527 struct kvm_translation *tr)
7528{
7529 unsigned long vaddr = tr->linear_address;
7530 gpa_t gpa;
f656ce01 7531 int idx;
8b006791 7532
f656ce01 7533 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7534 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7535 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7536 tr->physical_address = gpa;
7537 tr->valid = gpa != UNMAPPED_GVA;
7538 tr->writeable = 1;
7539 tr->usermode = 0;
8b006791
ZX		 7540
7541 return 0;
7542}
7543
d0752060
HB		 7544int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7545{
c47ada30 7546 struct fxregs_state *fxsave =
7366ed77 7547 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7548
d0752060
HB		 7549 memcpy(fpu->fpr, fxsave->st_space, 128);
7550 fpu->fcw = fxsave->cwd;
7551 fpu->fsw = fxsave->swd;
7552 fpu->ftwx = fxsave->twd;
7553 fpu->last_opcode = fxsave->fop;
7554 fpu->last_ip = fxsave->rip;
7555 fpu->last_dp = fxsave->rdp;
7556 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7557
d0752060
HB		 7558 return 0;
7559}
7560
7561int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7562{
c47ada30 7563 struct fxregs_state *fxsave =
7366ed77 7564 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7565
d0752060
HB		 7566 memcpy(fxsave->st_space, fpu->fpr, 128);
7567 fxsave->cwd = fpu->fcw;
7568 fxsave->swd = fpu->fsw;
7569 fxsave->twd = fpu->ftwx;
7570 fxsave->fop = fpu->last_opcode;
7571 fxsave->rip = fpu->last_ip;
7572 fxsave->rdp = fpu->last_dp;
7573 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7574
d0752060
HB		 7575 return 0;
7576}
7577
0ee6a517 7578static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7579{
bf935b0b 7580 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7581 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7582 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7583 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7584
2acf923e
DC		 7585 /*
7586 * Ensure guest xcr0 is valid for loading
7587 */
d91cab78 7588 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7589
ad312c7c 7590 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7591}
d0752060
HB		 7592
7593void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7594{
2608d7a1 7595 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7596 return;
7597
2acf923e
DC		 7598 /*
7599 * Restore all possible states in the guest,
7600 * and assume host would use all available bits.
7601 * Guest xcr0 would be loaded later.
7602 */
d0752060 7603 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7604 __kernel_fpu_begin();
003e2e8b 7605 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7606 trace_kvm_fpu(1);
d0752060 7607}
d0752060
HB		 7608
7609void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7610{
3d42de25 7611 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7612 return;
7613
7614 vcpu->guest_fpu_loaded = 0;
4f836347 7615 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7616 __kernel_fpu_end();
f096ed85 7617 ++vcpu->stat.fpu_reload;
0c04851c 7618 trace_kvm_fpu(0);
d0752060 7619}
e9b11c17
ZX		 7620
7621void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7622{
bd768e14
IY		 7623 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7624
12f9a48f 7625 kvmclock_reset(vcpu);
7f1ea208 7626
e9b11c17 7627 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7628 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7629}
7630
7631struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7632 unsigned int id)
7633{
c447e76b
LL		 7634 struct kvm_vcpu *vcpu;
7635
6755bae8
ZA		 7636 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7637 printk_once(KERN_WARNING
7638 "kvm: SMP vm created on host with unstable TSC; "
7639 "guest TSC will not be reliable\n");
c447e76b
LL		 7640
7641 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7642
c447e76b 7643 return vcpu;
26e5215f 7644}
e9b11c17 7645
26e5215f
AK		 7646int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7647{
7648 int r;
e9b11c17 7649
19efffa2 7650 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7651 r = vcpu_load(vcpu);
7652 if (r)
7653 return r;
d28bc9dd 7654 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7655 kvm_mmu_setup(vcpu);
e9b11c17 7656 vcpu_put(vcpu);
26e5215f 7657 return r;
e9b11c17
ZX		 7658}
7659
31928aa5 7660void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7661{
8fe8ab46 7662 struct msr_data msr;
332967a3 7663 struct kvm *kvm = vcpu->kvm;
42897d86 7664
31928aa5
DD		 7665 if (vcpu_load(vcpu))
7666 return;
8fe8ab46
WA		 7667 msr.data = 0x0;
7668 msr.index = MSR_IA32_TSC;
7669 msr.host_initiated = true;
7670 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7671 vcpu_put(vcpu);
7672
630994b3
MT		 7673 if (!kvmclock_periodic_sync)
7674 return;
7675
332967a3
AJ		 7676 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7677 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7678}
7679
d40ccc62 7680void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7681{
9fc77441 7682 int r;
344d9588
GN		 7683 vcpu->arch.apf.msr_val = 0;
7684
9fc77441
MT		 7685 r = vcpu_load(vcpu);
7686 BUG_ON(r);
e9b11c17
ZX		 7687 kvm_mmu_unload(vcpu);
7688 vcpu_put(vcpu);
7689
7690 kvm_x86_ops->vcpu_free(vcpu);
7691}
7692
d28bc9dd 7693void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7694{
e69fab5d
PB		 7695 vcpu->arch.hflags = 0;
7696
c43203ca 7697 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7698 atomic_set(&vcpu->arch.nmi_queued, 0);
7699 vcpu->arch.nmi_pending = 0;
448fa4a9 7700 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7701 kvm_clear_interrupt_queue(vcpu);
7702 kvm_clear_exception_queue(vcpu);
448fa4a9 7703
42dbaa5a 7704 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7705 kvm_update_dr0123(vcpu);
6f43ed01 7706 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7707 kvm_update_dr6(vcpu);
42dbaa5a 7708 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7709 kvm_update_dr7(vcpu);
42dbaa5a 7710
1119022c
NA		 7711 vcpu->arch.cr2 = 0;
7712
3842d135 7713 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7714 vcpu->arch.apf.msr_val = 0;
c9aaa895 7715 vcpu->arch.st.msr_val = 0;
3842d135 7716
12f9a48f
GC		 7717 kvmclock_reset(vcpu);
7718
af585b92
GN		 7719 kvm_clear_async_pf_completion_queue(vcpu);
7720 kvm_async_pf_hash_reset(vcpu);
7721 vcpu->arch.apf.halted = false;
3842d135 7722
64d60670 7723 if (!init_event) {
d28bc9dd 7724 kvm_pmu_reset(vcpu);
64d60670 7725 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7726
7727 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7728 vcpu->arch.msr_misc_features_enables = 0;
64d60670 7729 }
f5132b01 7730
66f7b72e
JS		 7731 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7732 vcpu->arch.regs_avail = ~0;
7733 vcpu->arch.regs_dirty = ~0;
7734
d28bc9dd 7735 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7736}
7737
2b4a273b 7738void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7739{
7740 struct kvm_segment cs;
7741
7742 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7743 cs.selector = vector << 8;
7744 cs.base = vector << 12;
7745 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7746 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7747}
7748
13a34e06 7749int kvm_arch_hardware_enable(void)
e9b11c17 7750{
ca84d1a2
ZA		 7751 struct kvm *kvm;
7752 struct kvm_vcpu *vcpu;
7753 int i;
0dd6a6ed
ZA		 7754 int ret;
7755 u64 local_tsc;
7756 u64 max_tsc = 0;
7757 bool stable, backwards_tsc = false;
18863bdd
AK		 7758
7759 kvm_shared_msr_cpu_online();
13a34e06 7760 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7761 if (ret != 0)
7762 return ret;
7763
4ea1636b 7764 local_tsc = rdtsc();
0dd6a6ed
ZA		 7765 stable = !check_tsc_unstable();
7766 list_for_each_entry(kvm, &vm_list, vm_list) {
7767 kvm_for_each_vcpu(i, vcpu, kvm) {
7768 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7769 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7770 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7771 backwards_tsc = true;
7772 if (vcpu->arch.last_host_tsc > max_tsc)
7773 max_tsc = vcpu->arch.last_host_tsc;
7774 }
7775 }
7776 }
7777
7778 /*
7779 * Sometimes, even reliable TSCs go backwards. This happens on
7780 * platforms that reset TSC during suspend or hibernate actions, but
7781 * maintain synchronization. We must compensate. Fortunately, we can
7782 * detect that condition here, which happens early in CPU bringup,
7783 * before any KVM threads can be running. Unfortunately, we can't
7784 * bring the TSCs fully up to date with real time, as we aren't yet far
7785 * enough into CPU bringup that we know how much real time has actually
108b249c 7786 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7787 * variables that haven't been updated yet.
7788 *
7789 * So we simply find the maximum observed TSC above, then record the
7790 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7791 * the adjustment will be applied. Note that we accumulate
7792 * adjustments, in case multiple suspend cycles happen before some VCPU
7793 * gets a chance to run again. In the event that no KVM threads get a
7794 * chance to run, we will miss the entire elapsed period, as we'll have
7795 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7796 * loose cycle time. This isn't too big a deal, since the loss will be
7797 * uniform across all VCPUs (not to mention the scenario is extremely
7798 * unlikely). It is possible that a second hibernate recovery happens
7799 * much faster than a first, causing the observed TSC here to be
7800 * smaller; this would require additional padding adjustment, which is
7801 * why we set last_host_tsc to the local tsc observed here.
7802 *
7803 * N.B. - this code below runs only on platforms with reliable TSC,
7804 * as that is the only way backwards_tsc is set above. Also note
7805 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7806 * have the same delta_cyc adjustment applied if backwards_tsc
7807 * is detected. Note further, this adjustment is only done once,
7808 * as we reset last_host_tsc on all VCPUs to stop this from being
7809 * called multiple times (one for each physical CPU bringup).
7810 *
4a969980 7811 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7812 * will be compensated by the logic in vcpu_load, which sets the TSC to
7813 * catchup mode. This will catchup all VCPUs to real time, but cannot
7814 * guarantee that they stay in perfect synchronization.
7815 */
7816 if (backwards_tsc) {
7817 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7818 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7819 list_for_each_entry(kvm, &vm_list, vm_list) {
7820 kvm_for_each_vcpu(i, vcpu, kvm) {
7821 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7822 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7823 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7824 }
7825
7826 /*
7827 * We have to disable TSC offset matching.. if you were
7828 * booting a VM while issuing an S4 host suspend....
7829 * you may have some problem. Solving this issue is
7830 * left as an exercise to the reader.
7831 */
7832 kvm->arch.last_tsc_nsec = 0;
7833 kvm->arch.last_tsc_write = 0;
7834 }
7835
7836 }
7837 return 0;
e9b11c17
ZX		 7838}
7839
13a34e06 7840void kvm_arch_hardware_disable(void)
e9b11c17 7841{
13a34e06
RK		 7842 kvm_x86_ops->hardware_disable();
7843 drop_user_return_notifiers();
e9b11c17
ZX		 7844}
7845
7846int kvm_arch_hardware_setup(void)
7847{
9e9c3fe4
NA		 7848 int r;
7849
7850 r = kvm_x86_ops->hardware_setup();
7851 if (r != 0)
7852 return r;
7853
35181e86
HZ		 7854 if (kvm_has_tsc_control) {
7855 /*
7856 * Make sure the user can only configure tsc_khz values that
7857 * fit into a signed integer.
7858 * A min value is not calculated needed because it will always
7859 * be 1 on all machines.
7860 */
7861 u64 max = min(0x7fffffffULL,
7862 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7863 kvm_max_guest_tsc_khz = max;
7864
ad721883 7865 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7866 }
ad721883 7867
9e9c3fe4
NA		 7868 kvm_init_msr_list();
7869 return 0;
e9b11c17
ZX		 7870}
7871
7872void kvm_arch_hardware_unsetup(void)
7873{
7874 kvm_x86_ops->hardware_unsetup();
7875}
7876
7877void kvm_arch_check_processor_compat(void *rtn)
7878{
7879 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7880}
7881
7882bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7883{
7884 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7885}
7886EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7887
7888bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7889{
7890 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7891}
7892
54e9818f 7893struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7894EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7895
e9b11c17
ZX		 7896int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7897{
7898 struct page *page;
7899 struct kvm *kvm;
7900 int r;
7901
7902 BUG_ON(vcpu->kvm == NULL);
7903 kvm = vcpu->kvm;
7904
d62caabb 7905 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7906 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7907 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7908 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7909 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7910 else
a4535290 7911 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7912
7913 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7914 if (!page) {
7915 r = -ENOMEM;
7916 goto fail;
7917 }
ad312c7c 7918 vcpu->arch.pio_data = page_address(page);
e9b11c17 7919
cc578287 7920 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7921
e9b11c17
ZX		 7922 r = kvm_mmu_create(vcpu);
7923 if (r < 0)
7924 goto fail_free_pio_data;
7925
7926 if (irqchip_in_kernel(kvm)) {
7927 r = kvm_create_lapic(vcpu);
7928 if (r < 0)
7929 goto fail_mmu_destroy;
54e9818f
GN		 7930 } else
7931 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7932
890ca9ae
HY		 7933 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7934 GFP_KERNEL);
7935 if (!vcpu->arch.mce_banks) {
7936 r = -ENOMEM;
443c39bc 7937 goto fail_free_lapic;
890ca9ae
HY		 7938 }
7939 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7940
f1797359
WY		 7941 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7942 r = -ENOMEM;
f5f48ee1 7943 goto fail_free_mce_banks;
f1797359 7944 }
f5f48ee1 7945
0ee6a517 7946 fx_init(vcpu);
66f7b72e 7947
ba904635 7948 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7949 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7950
7951 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7952 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7953
5a4f55cd
EK		 7954 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7955
74545705
RK		 7956 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7957
af585b92 7958 kvm_async_pf_hash_reset(vcpu);
f5132b01 7959 kvm_pmu_init(vcpu);
af585b92 7960
1c1a9ce9
SR		 7961 vcpu->arch.pending_external_vector = -1;
7962
5c919412
AS		 7963 kvm_hv_vcpu_init(vcpu);
7964
e9b11c17 7965 return 0;
0ee6a517 7966
f5f48ee1
SY		 7967fail_free_mce_banks:
7968 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7969fail_free_lapic:
7970 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7971fail_mmu_destroy:
7972 kvm_mmu_destroy(vcpu);
7973fail_free_pio_data:
ad312c7c 7974 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7975fail:
7976 return r;
7977}
7978
7979void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7980{
f656ce01
MT		 7981 int idx;
7982
1f4b34f8 7983 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7984 kvm_pmu_destroy(vcpu);
36cb93fd 7985 kfree(vcpu->arch.mce_banks);
e9b11c17 7986 kvm_free_lapic(vcpu);
f656ce01 7987 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7988 kvm_mmu_destroy(vcpu);
f656ce01 7989 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7990 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7991 if (!lapic_in_kernel(vcpu))
54e9818f 7992 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7993}
d19a9cd2 7994
e790d9ef
RK		 7995void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7996{
ae97a3b8 7997 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7998}
7999
e08b9637 8000int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8001{
e08b9637
CO		 8002 if (type)
8003 return -EINVAL;
8004
6ef768fa 8005 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8006 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8007 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8008 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8009 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8010
5550af4d
SY		 8011 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8012 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8013 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8014 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8015 &kvm->arch.irq_sources_bitmap);
5550af4d 8016
038f8c11 8017 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8018 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8019 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8020 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8021
108b249c 8022 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8023 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8024
7e44e449 8025 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8026 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8027
0eb05bf2 8028 kvm_page_track_init(kvm);
13d268ca 8029 kvm_mmu_init_vm(kvm);
0eb05bf2 8030
03543133
SS		 8031 if (kvm_x86_ops->vm_init)
8032 return kvm_x86_ops->vm_init(kvm);
8033
d89f5eff 8034 return 0;
d19a9cd2
ZX		 8035}
8036
8037static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8038{
9fc77441
MT		 8039 int r;
8040 r = vcpu_load(vcpu);
8041 BUG_ON(r);
d19a9cd2
ZX		 8042 kvm_mmu_unload(vcpu);
8043 vcpu_put(vcpu);
8044}
8045
8046static void kvm_free_vcpus(struct kvm *kvm)
8047{
8048 unsigned int i;
988a2cae 8049 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8050
8051 /*
8052 * Unpin any mmu pages first.
8053 */
af585b92
GN		 8054 kvm_for_each_vcpu(i, vcpu, kvm) {
8055 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8056 kvm_unload_vcpu_mmu(vcpu);
af585b92 8057 }
988a2cae
GN		 8058 kvm_for_each_vcpu(i, vcpu, kvm)
8059 kvm_arch_vcpu_free(vcpu);
8060
8061 mutex_lock(&kvm->lock);
8062 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8063 kvm->vcpus[i] = NULL;
d19a9cd2 8064
988a2cae
GN		 8065 atomic_set(&kvm->online_vcpus, 0);
8066 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8067}
8068
ad8ba2cd
SY		 8069void kvm_arch_sync_events(struct kvm *kvm)
8070{
332967a3 8071 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8072 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8073 kvm_free_pit(kvm);
ad8ba2cd
SY		 8074}
8075
1d8007bd 8076int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8077{
8078 int i, r;
25188b99 8079 unsigned long hva;
f0d648bd
PB		 8080 struct kvm_memslots *slots = kvm_memslots(kvm);
8081 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8082
8083 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8084 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8085 return -EINVAL;
9da0e4d5 8086
f0d648bd
PB		 8087 slot = id_to_memslot(slots, id);
8088 if (size) {
b21629da 8089 if (slot->npages)
f0d648bd
PB		 8090 return -EEXIST;
8091
8092 /*
8093 * MAP_SHARED to prevent internal slot pages from being moved
8094 * by fork()/COW.
8095 */
8096 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8097 MAP_SHARED | MAP_ANONYMOUS, 0);
8098 if (IS_ERR((void *)hva))
8099 return PTR_ERR((void *)hva);
8100 } else {
8101 if (!slot->npages)
8102 return 0;
8103
8104 hva = 0;
8105 }
8106
8107 old = *slot;
9da0e4d5 8108 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8109 struct kvm_userspace_memory_region m;
9da0e4d5 8110
1d8007bd
PB		 8111 m.slot = id | (i << 16);
8112 m.flags = 0;
8113 m.guest_phys_addr = gpa;
f0d648bd 8114 m.userspace_addr = hva;
1d8007bd 8115 m.memory_size = size;
9da0e4d5
PB		 8116 r = __kvm_set_memory_region(kvm, &m);
8117 if (r < 0)
8118 return r;
8119 }
8120
f0d648bd
PB		 8121 if (!size) {
8122 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8123 WARN_ON(r < 0);
8124 }
8125
9da0e4d5
PB		 8126 return 0;
8127}
8128EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8129
1d8007bd 8130int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8131{
8132 int r;
8133
8134 mutex_lock(&kvm->slots_lock);
1d8007bd 8135 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8136 mutex_unlock(&kvm->slots_lock);
8137
8138 return r;
8139}
8140EXPORT_SYMBOL_GPL(x86_set_memory_region);
8141
d19a9cd2
ZX		 8142void kvm_arch_destroy_vm(struct kvm *kvm)
8143{
27469d29
AH		 8144 if (current->mm == kvm->mm) {
8145 /*
8146 * Free memory regions allocated on behalf of userspace,
8147 * unless the the memory map has changed due to process exit
8148 * or fd copying.
8149 */
1d8007bd
PB		 8150 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8151 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8152 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8153 }
03543133
SS		 8154 if (kvm_x86_ops->vm_destroy)
8155 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8156 kvm_pic_destroy(kvm);
8157 kvm_ioapic_destroy(kvm);
d19a9cd2 8158 kvm_free_vcpus(kvm);
af1bae54 8159 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8160 kvm_mmu_uninit_vm(kvm);
2beb6dad 8161 kvm_page_track_cleanup(kvm);
d19a9cd2 8162}
0de10343 8163
5587027c 8164void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8165 struct kvm_memory_slot *dont)
8166{
8167 int i;
8168
d89cc617
TY		 8169 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8170 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8171 kvfree(free->arch.rmap[i]);
d89cc617 8172 free->arch.rmap[i] = NULL;
77d11309 8173 }
d89cc617
TY		 8174 if (i == 0)
8175 continue;
8176
8177 if (!dont || free->arch.lpage_info[i - 1] !=
8178 dont->arch.lpage_info[i - 1]) {
548ef284 8179 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8180 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8181 }
8182 }
21ebbeda
XG		 8183
8184 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8185}
8186
5587027c
AK		 8187int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8188 unsigned long npages)
db3fe4eb
TY		 8189{
8190 int i;
8191
d89cc617 8192 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8193 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8194 unsigned long ugfn;
8195 int lpages;
d89cc617 8196 int level = i + 1;
db3fe4eb
TY		 8197
8198 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8199 slot->base_gfn, level) + 1;
8200
d89cc617
TY		 8201 slot->arch.rmap[i] =
8202 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8203 if (!slot->arch.rmap[i])
77d11309 8204 goto out_free;
d89cc617
TY		 8205 if (i == 0)
8206 continue;
77d11309 8207
92f94f1e
XG		 8208 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8209 if (!linfo)
db3fe4eb
TY		 8210 goto out_free;
8211
92f94f1e
XG		 8212 slot->arch.lpage_info[i - 1] = linfo;
8213
db3fe4eb 8214 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8215 linfo[0].disallow_lpage = 1;
db3fe4eb 8216 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8217 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8218 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8219 /*
8220 * If the gfn and userspace address are not aligned wrt each
8221 * other, or if explicitly asked to, disable large page
8222 * support for this slot
8223 */
8224 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8225 !kvm_largepages_enabled()) {
8226 unsigned long j;
8227
8228 for (j = 0; j < lpages; ++j)
92f94f1e 8229 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8230 }
8231 }
8232
21ebbeda
XG		 8233 if (kvm_page_track_create_memslot(slot, npages))
8234 goto out_free;
8235
db3fe4eb
TY		 8236 return 0;
8237
8238out_free:
d89cc617 8239 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8240 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8241 slot->arch.rmap[i] = NULL;
8242 if (i == 0)
8243 continue;
8244
548ef284 8245 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8246 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8247 }
8248 return -ENOMEM;
8249}
8250
15f46015 8251void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8252{
e6dff7d1
TY		 8253 /*
8254 * memslots->generation has been incremented.
8255 * mmio generation may have reached its maximum value.
8256 */
54bf36aa 8257 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8258}
8259
f7784b8e
MT		 8260int kvm_arch_prepare_memory_region(struct kvm *kvm,
8261 struct kvm_memory_slot *memslot,
09170a49 8262 const struct kvm_userspace_memory_region *mem,
7b6195a9 8263 enum kvm_mr_change change)
0de10343 8264{
f7784b8e
MT		 8265 return 0;
8266}
8267
88178fd4
KH		 8268static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8269 struct kvm_memory_slot *new)
8270{
8271 /* Still write protect RO slot */
8272 if (new->flags & KVM_MEM_READONLY) {
8273 kvm_mmu_slot_remove_write_access(kvm, new);
8274 return;
8275 }
8276
8277 /*
8278 * Call kvm_x86_ops dirty logging hooks when they are valid.
8279 *
8280 * kvm_x86_ops->slot_disable_log_dirty is called when:
8281 *
8282 * - KVM_MR_CREATE with dirty logging is disabled
8283 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8284 *
8285 * The reason is, in case of PML, we need to set D-bit for any slots
8286 * with dirty logging disabled in order to eliminate unnecessary GPA
8287 * logging in PML buffer (and potential PML buffer full VMEXT). This
8288 * guarantees leaving PML enabled during guest's lifetime won't have
8289 * any additonal overhead from PML when guest is running with dirty
8290 * logging disabled for memory slots.
8291 *
8292 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8293 * to dirty logging mode.
8294 *
8295 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8296 *
8297 * In case of write protect:
8298 *
8299 * Write protect all pages for dirty logging.
8300 *
8301 * All the sptes including the large sptes which point to this
8302 * slot are set to readonly. We can not create any new large
8303 * spte on this slot until the end of the logging.
8304 *
8305 * See the comments in fast_page_fault().
8306 */
8307 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8308 if (kvm_x86_ops->slot_enable_log_dirty)
8309 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8310 else
8311 kvm_mmu_slot_remove_write_access(kvm, new);
8312 } else {
8313 if (kvm_x86_ops->slot_disable_log_dirty)
8314 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8315 }
8316}
8317
f7784b8e 8318void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8319 const struct kvm_userspace_memory_region *mem,
8482644a 8320 const struct kvm_memory_slot *old,
f36f3f28 8321 const struct kvm_memory_slot *new,
8482644a 8322 enum kvm_mr_change change)
f7784b8e 8323{
8482644a 8324 int nr_mmu_pages = 0;
f7784b8e 8325
48c0e4e9
XG		 8326 if (!kvm->arch.n_requested_mmu_pages)
8327 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8328
48c0e4e9 8329 if (nr_mmu_pages)
0de10343 8330 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8331
3ea3b7fa
WL		 8332 /*
8333 * Dirty logging tracks sptes in 4k granularity, meaning that large
8334 * sptes have to be split. If live migration is successful, the guest
8335 * in the source machine will be destroyed and large sptes will be
8336 * created in the destination. However, if the guest continues to run
8337 * in the source machine (for example if live migration fails), small
8338 * sptes will remain around and cause bad performance.
8339 *
8340 * Scan sptes if dirty logging has been stopped, dropping those
8341 * which can be collapsed into a single large-page spte. Later
8342 * page faults will create the large-page sptes.
8343 */
8344 if ((change != KVM_MR_DELETE) &&
8345 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8346 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8347 kvm_mmu_zap_collapsible_sptes(kvm, new);
8348
c972f3b1 8349 /*
88178fd4 8350 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8351 *
88178fd4
KH		 8352 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8353 * been zapped so no dirty logging staff is needed for old slot. For
8354 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8355 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8356 *
8357 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8358 */
88178fd4 8359 if (change != KVM_MR_DELETE)
f36f3f28 8360 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8361}
1d737c8a 8362
2df72e9b 8363void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8364{
6ca18b69 8365 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8366}
8367
2df72e9b
MT		 8368void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8369 struct kvm_memory_slot *slot)
8370{
ae7cd873 8371 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8372}
8373
5d9bc648
PB		 8374static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8375{
8376 if (!list_empty_careful(&vcpu->async_pf.done))
8377 return true;
8378
8379 if (kvm_apic_has_events(vcpu))
8380 return true;
8381
8382 if (vcpu->arch.pv.pv_unhalted)
8383 return true;
8384
8385 if (atomic_read(&vcpu->arch.nmi_queued))
8386 return true;
8387
72875d8a 8388 if (kvm_test_request(KVM_REQ_SMI, vcpu))
73917739
PB		 8389 return true;
8390
5d9bc648
PB		 8391 if (kvm_arch_interrupt_allowed(vcpu) &&
8392 kvm_cpu_has_interrupt(vcpu))
8393 return true;
8394
1f4b34f8
AS		 8395 if (kvm_hv_has_stimer_pending(vcpu))
8396 return true;
8397
5d9bc648
PB		 8398 return false;
8399}
8400
1d737c8a
ZX		 8401int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8402{
5d9bc648 8403 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8404}
5736199a 8405
b6d33834 8406int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8407{
b6d33834 8408 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8409}
78646121
GN		 8410
8411int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8412{
8413 return kvm_x86_ops->interrupt_allowed(vcpu);
8414}
229456fc 8415
82b32774 8416unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8417{
82b32774
NA		 8418 if (is_64_bit_mode(vcpu))
8419 return kvm_rip_read(vcpu);
8420 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8421 kvm_rip_read(vcpu));
8422}
8423EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8424
82b32774
NA		 8425bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8426{
8427 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8428}
8429EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8430
94fe45da
JK		 8431unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8432{
8433 unsigned long rflags;
8434
8435 rflags = kvm_x86_ops->get_rflags(vcpu);
8436 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8437 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8438 return rflags;
8439}
8440EXPORT_SYMBOL_GPL(kvm_get_rflags);
8441
6addfc42 8442static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8443{
8444 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8445 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8446 rflags |= X86_EFLAGS_TF;
94fe45da 8447 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8448}
8449
8450void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8451{
8452 __kvm_set_rflags(vcpu, rflags);
3842d135 8453 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8454}
8455EXPORT_SYMBOL_GPL(kvm_set_rflags);
8456
56028d08
GN		 8457void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8458{
8459 int r;
8460
fb67e14f 8461 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8462 work->wakeup_all)
56028d08
GN		 8463 return;
8464
8465 r = kvm_mmu_reload(vcpu);
8466 if (unlikely(r))
8467 return;
8468
fb67e14f
XG		 8469 if (!vcpu->arch.mmu.direct_map &&
8470 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8471 return;
8472
56028d08
GN		 8473 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8474}
8475
af585b92
GN		 8476static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8477{
8478 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8479}
8480
8481static inline u32 kvm_async_pf_next_probe(u32 key)
8482{
8483 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8484}
8485
8486static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8487{
8488 u32 key = kvm_async_pf_hash_fn(gfn);
8489
8490 while (vcpu->arch.apf.gfns[key] != ~0)
8491 key = kvm_async_pf_next_probe(key);
8492
8493 vcpu->arch.apf.gfns[key] = gfn;
8494}
8495
8496static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8497{
8498 int i;
8499 u32 key = kvm_async_pf_hash_fn(gfn);
8500
8501 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8502 (vcpu->arch.apf.gfns[key] != gfn &&
8503 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8504 key = kvm_async_pf_next_probe(key);
8505
8506 return key;
8507}
8508
8509bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8510{
8511 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8512}
8513
8514static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8515{
8516 u32 i, j, k;
8517
8518 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8519 while (true) {
8520 vcpu->arch.apf.gfns[i] = ~0;
8521 do {
8522 j = kvm_async_pf_next_probe(j);
8523 if (vcpu->arch.apf.gfns[j] == ~0)
8524 return;
8525 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8526 /*
8527 * k lies cyclically in ]i,j]
8528 * | i.k.j |
8529 * |....j i.k.| or |.k..j i...|
8530 */
8531 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8532 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8533 i = j;
8534 }
8535}
8536
7c90705b
GN		 8537static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8538{
bbd64115
CL		 8539 return kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.apf.data, &val,
8540 sizeof(val));
7c90705b
GN		 8541}
8542
af585b92
GN		 8543void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8544 struct kvm_async_pf *work)
8545{
6389ee94
AK		 8546 struct x86_exception fault;
8547
7c90705b 8548 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8549 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8550
8551 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8552 (vcpu->arch.apf.send_user_only &&
8553 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8554 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8555 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8556 fault.vector = PF_VECTOR;
8557 fault.error_code_valid = true;
8558 fault.error_code = 0;
8559 fault.nested_page_fault = false;
8560 fault.address = work->arch.token;
8561 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8562 }
af585b92
GN		 8563}
8564
8565void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8566 struct kvm_async_pf *work)
8567{
6389ee94
AK		 8568 struct x86_exception fault;
8569
f2e10669 8570 if (work->wakeup_all)
7c90705b
GN		 8571 work->arch.token = ~0; /* broadcast wakeup */
8572 else
8573 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8574 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8575
8576 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8577 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8578 fault.vector = PF_VECTOR;
8579 fault.error_code_valid = true;
8580 fault.error_code = 0;
8581 fault.nested_page_fault = false;
8582 fault.address = work->arch.token;
8583 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8584 }
e6d53e3b 8585 vcpu->arch.apf.halted = false;
a4fa1635 8586 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8587}
8588
8589bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8590{
8591 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8592 return true;
8593 else
8594 return !kvm_event_needs_reinjection(vcpu) &&
8595 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8596}
8597
5544eb9b
PB		 8598void kvm_arch_start_assignment(struct kvm *kvm)
8599{
8600 atomic_inc(&kvm->arch.assigned_device_count);
8601}
8602EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8603
8604void kvm_arch_end_assignment(struct kvm *kvm)
8605{
8606 atomic_dec(&kvm->arch.assigned_device_count);
8607}
8608EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8609
8610bool kvm_arch_has_assigned_device(struct kvm *kvm)
8611{
8612 return atomic_read(&kvm->arch.assigned_device_count);
8613}
8614EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8615
e0f0bbc5
AW		 8616void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8617{
8618 atomic_inc(&kvm->arch.noncoherent_dma_count);
8619}
8620EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8621
8622void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8623{
8624 atomic_dec(&kvm->arch.noncoherent_dma_count);
8625}
8626EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8627
8628bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8629{
8630 return atomic_read(&kvm->arch.noncoherent_dma_count);
8631}
8632EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8633
14717e20
AW		 8634bool kvm_arch_has_irq_bypass(void)
8635{
8636 return kvm_x86_ops->update_pi_irte != NULL;
8637}
8638
87276880
FW		 8639int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8640 struct irq_bypass_producer *prod)
8641{
8642 struct kvm_kernel_irqfd *irqfd =
8643 container_of(cons, struct kvm_kernel_irqfd, consumer);
8644
14717e20 8645 irqfd->producer = prod;
87276880 8646
14717e20
AW		 8647 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8648 prod->irq, irqfd->gsi, 1);
87276880
FW		 8649}
8650
8651void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8652 struct irq_bypass_producer *prod)
8653{
8654 int ret;
8655 struct kvm_kernel_irqfd *irqfd =
8656 container_of(cons, struct kvm_kernel_irqfd, consumer);
8657
87276880
FW		 8658 WARN_ON(irqfd->producer != prod);
8659 irqfd->producer = NULL;
8660
8661 /*
8662 * When producer of consumer is unregistered, we change back to
8663 * remapped mode, so we can re-use the current implementation
bb3541f1 8664 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8665 * int this case doesn't want to receive the interrupts.
8666 */
8667 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8668 if (ret)
8669 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8670 " fails: %d\n", irqfd->consumer.token, ret);
8671}
8672
8673int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8674 uint32_t guest_irq, bool set)
8675{
8676 if (!kvm_x86_ops->update_pi_irte)
8677 return -EINVAL;
8678
8679 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8680}
8681
52004014
FW		 8682bool kvm_vector_hashing_enabled(void)
8683{
8684 return vector_hashing;
8685}
8686EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8687
229456fc 8688EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8689EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8690EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8691EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8692EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8693EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8694EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8695EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8696EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8697EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8698EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8699EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8700EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8701EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8702EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8703EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8704EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8705EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8706EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git