[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

2020-02-11  Jan Beulich  <jbeulich@suse.com>

	* i386-gen.c (opcode_modifiers): Remove ShortForm entry.
	* i386-opc.h (ShortForm): Delete.
	(struct i386_opcode_modifier): Remove shortform field.
	* i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
	fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
	fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
	ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
	Drop ShortForm.
	* i386-tbl.h: Re-generate.

2020-02-11  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
	fucompi): Drop ShortForm from operand-less templates.
	* i386-tbl.h: Re-generate.

2020-02-11  Alan Modra  <amodra@gmail.com>

	* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
	* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
	* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
	* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
	* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.

2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (print_insn_cde): Define 'V' parse character.
	(cde_opcodes): Add VCX* instructions.

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (struct cdeopcode32): New.
	(CDE_OPCODE): New macro.
	(cde_opcodes): New disassembly table.
	(regnames): New option to table.
	(cde_coprocs): New global variable.
	(print_insn_cde): New
	(print_insn_thumb32): Use print_insn_cde.
	(parse_arm_disassembler_options): Parse coprocN args.

2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/25516
	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	with ISA64.
	* i386-opc.h (AMD64): Removed.
	(Intel64): Likewose.
	(AMD64): New.
	(INTEL64): Likewise.
	(INTEL64ONLY): Likewise.
	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	* i386-opc.tbl (Amd64): New.
	(Intel64): Likewise.
	(Intel64Only): Likewise.
	Replace AMD64 with Amd64.  Update sysenter/sysenter with
	Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
	* i386-tbl.h: Regenerated.

2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25469
	* z80-dis.c: Add support for GBZ80 opcodes.

2020-02-04  Alan Modra  <amodra@gmail.com>

	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.

2020-02-03  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-02-01  Alan Modra  <amodra@gmail.com>

	* frv-ibld.c: Regenerate.

2020-01-31  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
	(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
	(OP_E_memory): Replace xmm_mdq_mode case label by
	vex_scalar_w_dq_mode one.
	* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.

2020-01-31  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
	(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
	vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
	(intel_operand_size): Drop vex_w_dq_mode case label.

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.

2020-01-30  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c: Regenerate.

2020-01-30  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
	(dis386): Use them to replace C2/C3 table entries.
	(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
	* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
	ones. Use Size64 instead of DefaultSize on Intel64 ones.
	* i386-tbl.h: Re-generate.

2020-01-30  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
	forms.
	(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
	DefaultSize.
	* i386-tbl.h: Re-generate.

2020-01-30  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_dp): Make unsigned.

2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
	    Jan Beulich  <jbeulich@suse.com>

	PR binutils/25445
	* i386-dis.c (MOVSXD_Fixup): New function.
	(movsxd_mode): New enum.
	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	(intel_operand_size): Handle movsxd_mode.
	(OP_E_register): Likewise.
	(OP_G): Likewise.
	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	register on movsxd.  Add movsxd with 16-bit destination register
	for AMD64 and Intel64 ISAs.
	* i386-tbl.h: Regenerated.

2020-01-27  Tamar Christina  <tamar.christina@arm.com>

	PR 25403
	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	* aarch64-asm-2.c: Regenerate
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2020-01-21  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (sysret): Drop DefaultSize.
	* i386-tbl.h: Re-generate.

2020-01-21  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
	Dword.
	(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
	* i386-tbl.h: Re-generate.

2020-01-20  Nick Clifton  <nickc@redhat.com>

	* po/de.po: Updated German translation.
	* po/pt_BR.po: Updated Brazilian Portuguese translation.
	* po/uk.po: Updated Ukranian translation.

2020-01-20  Alan Modra  <amodra@gmail.com>

	* hppa-dis.c (fput_const): Remove useless cast.

2020-01-20  Alan Modra  <amodra@gmail.com>

	* arm-dis.c (print_insn_arm): Wrap 'T' value.

2020-01-18  Nick Clifton  <nickc@redhat.com>

	* configure: Regenerate.
	* po/opcodes.pot: Regenerate.

2020-01-18  Nick Clifton  <nickc@redhat.com>

	Binutils 2.34 branch created.

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* opintl.h: Fix spelling error (seperate).

2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add {vex} pseudo prefix.
	* i386-tbl.h: Regenerated.

2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: Drop stale comment from XOP section.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
	(extractps): Add VexWIG to SSE2AVX forms.
	* i386-tbl.h: Re-generate.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
	Size64 from and use VexW1 on SSE2AVX forms.
	(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
	VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
	* i386-tbl.h: Re-generate.

2020-01-15  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_version): Make unsigned long.
	(optab, optab_special, registernames): New file scope vars.
	(tic4x_print_register): Set up registernames rather than
	malloc'd registertable.
	(tic4x_disassemble): Delete optable and optable_special.  Use
	optab and optab_special instead.  Throw away old optab,
	optab_special and registernames when info->mach changes.

2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25377
	* z80-dis.c (suffix): Use .db instruction to generate double
	prefix.

2020-01-14  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
	values to unsigned before shifting.

2020-01-13  Thomas Troeger  <tstroege@gmx.de>

	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	flow instructions.
	(print_insn_thumb16, print_insn_thumb32): Likewise.
	(print_insn): Initialize the insn info.
	* i386-dis.c (print_insn): Initialize the insn info fields, and
	detect jumps.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

	* arc-opc.c (C_NE): Make it required.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

        * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	reserved register name.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
	result of wasm_read_leb128 in a uint64_t and check that bits
	are not lost when copying to other locals.  Use uint32_t for
	most locals.  Use PRId64 when printing int64_t.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c: Formatting.
	* score7-dis.c: Formatting.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c (print_insn_score48): Use unsigned variables for
	unsigned values.  Don't left shift negative values.
	(print_insn_score32): Likewise.
	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_print_register): Remove dead code.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* fr30-ibld.c: Regenerate.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* xgate-dis.c (print_insn): Don't left shift signed value.
	(ripBits): Formatting, use 1u.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	and XRREG value earlier to avoid a shift with negative exponent.
	* m10200-dis.c (disassemble): Similarly.

2020-01-09  Nick Clifton  <nickc@redhat.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use correct cast.

2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use character constant when checking
	opcode byte value.

2020-01-09  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (SEP_Fixup): New.
	(SEP): Define.
	(dis386_twobyte): Use it for sysenter/sysexit.
	(enum x86_64_isa): Change amd64 enumerator to value 1.
	(OP_J): Compare isa64 against intel64 instead of amd64.
	* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
	forms.
	* i386-tbl.h: Re-generate.

2020-01-08  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c: Include libiberty.h
	(instr_data_s): Make max_fetched unsigned.
	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	Don't exceed byte_info bounds.
	(output_instr): Make num_bytes unsigned.
	(unpack_instr): Likewise for nibl_count and loop.
	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	idx unsigned.
	* z8k-opc.h: Regenerate.

2020-01-07  Shahab Vahedi  <shahab@synopsys.com>

	* arc-tbl.h (llock): Use 'LLOCK' as class.
	(llockd): Likewise.
	(scond): Use 'SCOND' as class.
	(scondd): Likewise.
	(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
	(scondd): Likewise.

2020-01-06  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-01-06  Alan Modra  <amodra@gmail.com>

	PR 25344
	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	Peek at next byte to prevent recursion on repeated prefix bytes.
	Ensure uninitialised "mybuf" is not accessed.
	(print_insn_z80): Don't zero n_fetch and n_used here,..
	(print_insn_z80_buf): ..do it here instead.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* m32r-ibld.c: Regenerate.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* crx-dis.c (match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* d30v-dis.c (print_insn): Avoid signed overflow in left shift.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Use
	SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
	forms of SUDOT and USDOT.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
	uzip{1,2}.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
	FMMLA encoding.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>

	* z80-dis.c: Add support for eZ80 and Z80 instructions.

2020-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2019
\f
Copyright (C) 2020 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
50128d0c JB	1	2020-02-11 Jan Beulich <jbeulich@suse.com>
	2
	3	* i386-gen.c (opcode_modifiers): Remove ShortForm entry.
	4	* i386-opc.h (ShortForm): Delete.
	5	(struct i386_opcode_modifier): Remove shortform field.
	6	* i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
	7	fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
	8	fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
	9	ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
	10	Drop ShortForm.
	11	* i386-tbl.h: Re-generate.
	12
1e05b5c4 JB	13	2020-02-11 Jan Beulich <jbeulich@suse.com>
	14
	15	* i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
	16	fucompi): Drop ShortForm from operand-less templates.
	17	* i386-tbl.h: Re-generate.
	18
2f5dd314 AM	19	2020-02-11 Alan Modra <amodra@gmail.com>
	20
	21	* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
	22	* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
	23	* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
	24	* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
	25	* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
	26
5aae9ae9 MM	27	2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
	28
	29	* arm-dis.c (print_insn_cde): Define 'V' parse character.
	30	(cde_opcodes): Add VCX* instructions.
	31
4934a27c MM	32	2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
	33	Matthew Malcomson <matthew.malcomson@arm.com>
	34
	35	* arm-dis.c (struct cdeopcode32): New.
	36	(CDE_OPCODE): New macro.
	37	(cde_opcodes): New disassembly table.
	38	(regnames): New option to table.
	39	(cde_coprocs): New global variable.
	40	(print_insn_cde): New
	41	(print_insn_thumb32): Use print_insn_cde.
	42	(parse_arm_disassembler_options): Parse coprocN args.
	43
4b5aaf5f L	44	2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
	45
	46	PR gas/25516
	47	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	48	with ISA64.
	49	* i386-opc.h (AMD64): Removed.
	50	(Intel64): Likewose.
	51	(AMD64): New.
	52	(INTEL64): Likewise.
	53	(INTEL64ONLY): Likewise.
	54	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	55	* i386-opc.tbl (Amd64): New.
	56	(Intel64): Likewise.
	57	(Intel64Only): Likewise.
	58	Replace AMD64 with Amd64. Update sysenter/sysenter with
	59	Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
	60	* i386-tbl.h: Regenerated.
	61
9fc0b501 SB	62	2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
	63
	64	PR 25469
	65	* z80-dis.c: Add support for GBZ80 opcodes.
	66
c5d7be0c AM	67	2020-02-04 Alan Modra <amodra@gmail.com>
	68
	69	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
	70
44e4546f AM	71	2020-02-03 Alan Modra <amodra@gmail.com>
	72
	73	* m32c-ibld.c: Regenerate.
	74
b2b1453a AM	75	2020-02-01 Alan Modra <amodra@gmail.com>
	76
	77	* frv-ibld.c: Regenerate.
	78
4102be5c JB	79	2020-01-31 Jan Beulich <jbeulich@suse.com>
	80
	81	* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
	82	(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
	83	(OP_E_memory): Replace xmm_mdq_mode case label by
	84	vex_scalar_w_dq_mode one.
	85	* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
	86
825bd36c JB	87	2020-01-31 Jan Beulich <jbeulich@suse.com>
	88
	89	* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
	90	(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
	91	vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
	92	(intel_operand_size): Drop vex_w_dq_mode case label.
	93
c3036ed0 RS	94	2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
	95
	96	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	97	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
	98
0c115f84 AM	99	2020-01-30 Alan Modra <amodra@gmail.com>
	100
	101	* m32c-ibld.c: Regenerate.
	102
bd434cc4 JM	103	2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
	104
	105	* bpf-opc.c: Regenerate.
	106
aeab2b26 JB	107	2020-01-30 Jan Beulich <jbeulich@suse.com>
	108
	109	* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
	110	(dis386): Use them to replace C2/C3 table entries.
	111	(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
	112	* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
	113	ones. Use Size64 instead of DefaultSize on Intel64 ones.
	114	* i386-tbl.h: Re-generate.
	115
62b3f548 JB	116	2020-01-30 Jan Beulich <jbeulich@suse.com>
	117
	118	* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
	119	forms.
	120	(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
	121	DefaultSize.
	122	* i386-tbl.h: Re-generate.
	123
1bd8ae10 AM	124	2020-01-30 Alan Modra <amodra@gmail.com>
	125
	126	* tic4x-dis.c (tic4x_dp): Make unsigned.
	127
bc31405e L	128	2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
	129	Jan Beulich <jbeulich@suse.com>
	130
	131	PR binutils/25445
	132	* i386-dis.c (MOVSXD_Fixup): New function.
	133	(movsxd_mode): New enum.
	134	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	135	(intel_operand_size): Handle movsxd_mode.
	136	(OP_E_register): Likewise.
	137	(OP_G): Likewise.
	138	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	139	register on movsxd. Add movsxd with 16-bit destination register
	140	for AMD64 and Intel64 ISAs.
	141	* i386-tbl.h: Regenerated.
	142
7568c93b TC	143	2020-01-27 Tamar Christina <tamar.christina@arm.com>
	144
	145	PR 25403
	146	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	147	* aarch64-asm-2.c: Regenerate
	148	* aarch64-dis-2.c: Likewise.
	149	* aarch64-opc-2.c: Likewise.
	150
c006a730 JB	151	2020-01-21 Jan Beulich <jbeulich@suse.com>
	152
	153	* i386-opc.tbl (sysret): Drop DefaultSize.
	154	* i386-tbl.h: Re-generate.
	155
c906a69a JB	156	2020-01-21 Jan Beulich <jbeulich@suse.com>
	157
	158	* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
	159	Dword.
	160	(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
	161	* i386-tbl.h: Re-generate.
	162
26916852 NC	163	2020-01-20 Nick Clifton <nickc@redhat.com>
	164
	165	* po/de.po: Updated German translation.
	166	* po/pt_BR.po: Updated Brazilian Portuguese translation.
	167	* po/uk.po: Updated Ukranian translation.
	168
4d6cbb64 AM	169	2020-01-20 Alan Modra <amodra@gmail.com>
	170
	171	* hppa-dis.c (fput_const): Remove useless cast.
	172
2bddb71a AM	173	2020-01-20 Alan Modra <amodra@gmail.com>
	174
	175	* arm-dis.c (print_insn_arm): Wrap 'T' value.
	176
1b1bb2c6 NC	177	2020-01-18 Nick Clifton <nickc@redhat.com>
	178
	179	* configure: Regenerate.
	180	* po/opcodes.pot: Regenerate.
	181
ae774686 NC	182	2020-01-18 Nick Clifton <nickc@redhat.com>
	183
	184	Binutils 2.34 branch created.
	185
07f1f3aa CB	186	2020-01-17 Christian Biesinger <cbiesinger@google.com>
	187
	188	* opintl.h: Fix spelling error (seperate).
	189
42e04b36 L	190	2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
	191
	192	* i386-opc.tbl: Add {vex} pseudo prefix.
	193	* i386-tbl.h: Regenerated.
	194
2da2eaf4 AV	195	2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
	196
	197	PR 25376
	198	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	199	(neon_opcodes): Likewise.
	200	(select_arm_features): Make sure we enable MVE bits when selecting
	201	armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
	202	any architecture.
	203
d0849eed JB	204	2020-01-16 Jan Beulich <jbeulich@suse.com>
	205
	206	* i386-opc.tbl: Drop stale comment from XOP section.
	207
9cf70a44 JB	208	2020-01-16 Jan Beulich <jbeulich@suse.com>
	209
	210	* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
	211	(extractps): Add VexWIG to SSE2AVX forms.
	212	* i386-tbl.h: Re-generate.
	213
4814632e JB	214	2020-01-16 Jan Beulich <jbeulich@suse.com>
	215
	216	* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
	217	Size64 from and use VexW1 on SSE2AVX forms.
	218	(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
	219	VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
	220	* i386-tbl.h: Re-generate.
	221
aad09917 AM	222	2020-01-15 Alan Modra <amodra@gmail.com>
	223
	224	* tic4x-dis.c (tic4x_version): Make unsigned long.
	225	(optab, optab_special, registernames): New file scope vars.
	226	(tic4x_print_register): Set up registernames rather than
	227	malloc'd registertable.
	228	(tic4x_disassemble): Delete optable and optable_special. Use
	229	optab and optab_special instead. Throw away old optab,
	230	optab_special and registernames when info->mach changes.
	231
7a6bf3be SB	232	2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
	233
	234	PR 25377
	235	* z80-dis.c (suffix): Use .db instruction to generate double
	236	prefix.
	237
ca1eaac0 AM	238	2020-01-14 Alan Modra <amodra@gmail.com>
	239
	240	* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
	241	values to unsigned before shifting.
	242
1d67fe3b TT	243	2020-01-13 Thomas Troeger <tstroege@gmx.de>
	244
	245	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	246	flow instructions.
	247	(print_insn_thumb16, print_insn_thumb32): Likewise.
	248	(print_insn): Initialize the insn info.
	249	* i386-dis.c (print_insn): Initialize the insn info fields, and
	250	detect jumps.
	251
5e4f7e05 CZ	252	2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
	253
	254	* arc-opc.c (C_NE): Make it required.
	255
b9fe6b8a CZ	256	2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
	257
	258	* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	259	reserved register name.
	260
90dee485 AM	261	2020-01-13 Alan Modra <amodra@gmail.com>
	262
	263	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	264	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
	265
febda64f AM	266	2020-01-13 Alan Modra <amodra@gmail.com>
	267
	268	* wasm32-dis.c (print_insn_wasm32): Localise variables. Store
	269	result of wasm_read_leb128 in a uint64_t and check that bits
	270	are not lost when copying to other locals. Use uint32_t for
	271	most locals. Use PRId64 when printing int64_t.
	272
df08b588 AM	273	2020-01-13 Alan Modra <amodra@gmail.com>
	274
	275	* score-dis.c: Formatting.
	276	* score7-dis.c: Formatting.
	277
b2c759ce AM	278	2020-01-13 Alan Modra <amodra@gmail.com>
	279
	280	* score-dis.c (print_insn_score48): Use unsigned variables for
	281	unsigned values. Don't left shift negative values.
	282	(print_insn_score32): Likewise.
	283	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
	284
5496abe1 AM	285	2020-01-13 Alan Modra <amodra@gmail.com>
	286
	287	* tic4x-dis.c (tic4x_print_register): Remove dead code.
	288
202e762b AM	289	2020-01-13 Alan Modra <amodra@gmail.com>
	290
	291	* fr30-ibld.c: Regenerate.
	292
7ef412cf AM	293	2020-01-13 Alan Modra <amodra@gmail.com>
	294
	295	* xgate-dis.c (print_insn): Don't left shift signed value.
	296	(ripBits): Formatting, use 1u.
	297
7f578b95 AM	298	2020-01-10 Alan Modra <amodra@gmail.com>
	299
	300	* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	301	* tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
	302
441af85b AM	303	2020-01-10 Alan Modra <amodra@gmail.com>
	304
	305	* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	306	and XRREG value earlier to avoid a shift with negative exponent.
	307	* m10200-dis.c (disassemble): Similarly.
	308
bce58db4 NC	309	2020-01-09 Nick Clifton <nickc@redhat.com>
	310
	311	PR 25224
	312	* z80-dis.c (ld_ii_ii): Use correct cast.
	313
40c75bc8 SB	314	2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
	315
	316	PR 25224
	317	* z80-dis.c (ld_ii_ii): Use character constant when checking
	318	opcode byte value.
	319
d835a58b JB	320	2020-01-09 Jan Beulich <jbeulich@suse.com>
	321
	322	* i386-dis.c (SEP_Fixup): New.
	323	(SEP): Define.
	324	(dis386_twobyte): Use it for sysenter/sysexit.
	325	(enum x86_64_isa): Change amd64 enumerator to value 1.
	326	(OP_J): Compare isa64 against intel64 instead of amd64.
	327	* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
	328	forms.
	329	* i386-tbl.h: Re-generate.
	330
030a2e78 AM	331	2020-01-08 Alan Modra <amodra@gmail.com>
	332
	333	* z8k-dis.c: Include libiberty.h
	334	(instr_data_s): Make max_fetched unsigned.
	335	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	336	Don't exceed byte_info bounds.
	337	(output_instr): Make num_bytes unsigned.
	338	(unpack_instr): Likewise for nibl_count and loop.
	339	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	340	idx unsigned.
	341	* z8k-opc.h: Regenerate.
	342
bb82aefe SV	343	2020-01-07 Shahab Vahedi <shahab@synopsys.com>
	344
	345	* arc-tbl.h (llock): Use 'LLOCK' as class.
	346	(llockd): Likewise.
	347	(scond): Use 'SCOND' as class.
	348	(scondd): Likewise.
	349	(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
	350	(scondd): Likewise.
	351
cc6aa1a6 AM	352	2020-01-06 Alan Modra <amodra@gmail.com>
	353
	354	* m32c-ibld.c: Regenerate.
	355
660e62b1 AM	356	2020-01-06 Alan Modra <amodra@gmail.com>
	357
	358	PR 25344
	359	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	360	Peek at next byte to prevent recursion on repeated prefix bytes.
	361	Ensure uninitialised "mybuf" is not accessed.
	362	(print_insn_z80): Don't zero n_fetch and n_used here,..
	363	(print_insn_z80_buf): ..do it here instead.
	364
c9ae58fe AM	365	2020-01-04 Alan Modra <amodra@gmail.com>
	366
	367	* m32r-ibld.c: Regenerate.
	368
5f57d4ec AM	369	2020-01-04 Alan Modra <amodra@gmail.com>
	370
	371	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
	372
2c5c1196 AM	373	2020-01-04 Alan Modra <amodra@gmail.com>
	374
	375	* crx-dis.c (match_opcode): Avoid shift left of signed value.
	376
2e98c6c5 AM	377	2020-01-04 Alan Modra <amodra@gmail.com>
	378
	379	* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
	380
567dfba2 JB	381	2020-01-03 Jan Beulich <jbeulich@suse.com>
567dfba2 JB	382
5437a02a JB	383	* aarch64-tbl.h (aarch64_opcode_table): Use
	384	SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
	385
	386	2020-01-03 Jan Beulich <jbeulich@suse.com>
	387
	388	* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2 JB	389	forms of SUDOT and USDOT.
567dfba2 JB	390
8c45011a JB	391	2020-01-03 Jan Beulich <jbeulich@suse.com>
8c45011a JB	392
5437a02a	393	* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a JB	394	uzip{1,2}.
	395	* opcodes/aarch64-dis-2.c: Re-generate.
	396
f4950f76 JB	397	2020-01-03 Jan Beulich <jbeulich@suse.com>
f4950f76 JB	398
5437a02a	399	* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76 JB	400	FMMLA encoding.
	401	* opcodes/aarch64-dis-2.c: Re-generate.
	402
6655dba2 SB	403	2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
	404
	405	* z80-dis.c: Add support for eZ80 and Z80 instructions.
	406
b14ce8bf AM	407	2020-01-01 Alan Modra <amodra@gmail.com>
	408
	409	Update year range in copyright notice of all files.
	410
0b114740	411	For older changes see ChangeLog-2019
3499769a	412	\f
0b114740	413	Copyright (C) 2020 Free Software Foundation, Inc.
3499769a AM	414
	415	Copying and distribution of this file, with or without modification,
	416	are permitted in any medium without royalty provided the copyright
	417	notice and this notice are preserved.
	418
	419	Local Variables:
	420	mode: change-log
	421	left-margin: 8
	422	fill-column: 74
	423	version-control: never
	424	End: