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2002-03-02 Chris Demetriou <cgd@broadcom.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
c1e8ada4
CD		 12002-03-02 Chris Demetriou <cgd@broadcom.com>
2
3 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
4 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
5 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
6 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
7 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
8 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
9 Don't split opcode fields by hand, use the opcode field values
10 provided by igen.
11
3e1dca16
CD		 122002-03-01 Chris Demetriou <cgd@broadcom.com>
13
14 * mips.igen (do_divu): Fix spacing.
15
16 * mips.igen (do_dsllv): Move to be right before DSLLV,
17 to match the rest of the do_<shift> functions.
18
fff8d27d
CD		 192002-03-01 Chris Demetriou <cgd@broadcom.com>
20
21 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
22 DSRL32, do_dsrlv): Trace inputs and results.
23
0d3e762b
CD		 242002-03-01 Chris Demetriou <cgd@broadcom.com>
25
26 * mips.igen (CACHE): Provide instruction-printing string.
27
28 * interp.c (signal_exception): Comment tokens after #endif.
29
eb5fcf93
CD		 302002-02-28 Chris Demetriou <cgd@broadcom.com>
31
32 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
33 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
34 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
35 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
36 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
37 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
38 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
39 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
40
bb22bd7d
CD		 412002-02-28 Chris Demetriou <cgd@broadcom.com>
42
43 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
44 instruction-printing string.
45 (LWU): Use '64' as the filter flag.
46
91a177cf
CD		 472002-02-28 Chris Demetriou <cgd@broadcom.com>
48
49 * mips.igen (SDXC1): Fix instruction-printing string.
50
387f484a
CD		 512002-02-28 Chris Demetriou <cgd@broadcom.com>
52
53 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
54 filter flags "32,f".
55
3d81f391
CD		 562002-02-27 Chris Demetriou <cgd@broadcom.com>
57
58 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
59 as the filter flag.
60
af5107af
CD		 612002-02-27 Chris Demetriou <cgd@broadcom.com>
62
63 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
64 add a comma) so that it more closely match the MIPS ISA
65 documentation opcode partitioning.
66 (PREF): Put useful names on opcode fields, and include
67 instruction-printing string.
68
ca971540
CD		 692002-02-27 Chris Demetriou <cgd@broadcom.com>
70
71 * mips.igen (check_u64): New function which in the future will
72 check whether 64-bit instructions are usable and signal an
73 exception if not. Currently a no-op.
74 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
75 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
76 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
77 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
78
79 * mips.igen (check_fpu): New function which in the future will
80 check whether FPU instructions are usable and signal an exception
81 if not. Currently a no-op.
82 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
83 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
84 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
85 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
86 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
87 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
88 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
89 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
90
1c47a468
CD		 912002-02-27 Chris Demetriou <cgd@broadcom.com>
92
93 * mips.igen (do_load_left, do_load_right): Move to be immediately
94 following do_load.
95 (do_store_left, do_store_right): Move to be immediately following
96 do_store.
97
603a98e7
CD		 982002-02-27 Chris Demetriou <cgd@broadcom.com>
99
100 * mips.igen (mipsV): New model name. Also, add it to
101 all instructions and functions where it is appropriate.
102
c5d00cc7
CD		 1032002-02-18 Chris Demetriou <cgd@broadcom.com>
104
105 * mips.igen: For all functions and instructions, list model
106 names that support that instruction one per line.
107
074e9cb8
CD		 1082002-02-11 Chris Demetriou <cgd@broadcom.com>
109
110 * mips.igen: Add some additional comments about supported
111 models, and about which instructions go where.
112 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
113 order as is used in the rest of the file.
114
9805e229
CD		 1152002-02-11 Chris Demetriou <cgd@broadcom.com>
116
117 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
118 indicating that ALU32_END or ALU64_END are there to check
119 for overflow.
120 (DADD): Likewise, but also remove previous comment about
121 overflow checking.
122
f701dad2
CD		 1232002-02-10 Chris Demetriou <cgd@broadcom.com>
124
125 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
126 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
127 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
128 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
129 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
130 fields (i.e., add and move commas) so that they more closely
131 match the MIPS ISA documentation opcode partitioning.
132
1332002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 134
135 * mips.igen (ADDI): Print immediate value.
136 (BREAK): Print code.
137 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
138 (SLL): Print "nop" specially, and don't run the code
139 that does the shift for the "nop" case.
140
9e52972e
FF		 1412001-11-17 Fred Fish <fnf@redhat.com>
142
143 * sim-main.h (float_operation): Move enum declaration outside
144 of _sim_cpu struct declaration.
145
c0efbca4
JB		 1462001-04-12 Jim Blandy <jimb@redhat.com>
147
148 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
149 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
150 set of the FCSR.
151 * sim-main.h (COCIDX): Remove definition; this isn't supported by
152 PENDING_FILL, and you can get the intended effect gracefully by
153 calling PENDING_SCHED directly.
154
fb891446
BE		 1552001-02-23 Ben Elliston <bje@redhat.com>
156
157 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
158 already defined elsewhere.
159
8030f857
BE		 1602001-02-19 Ben Elliston <bje@redhat.com>
161
162 * sim-main.h (sim_monitor): Return an int.
163 * interp.c (sim_monitor): Add return values.
164 (signal_exception): Handle error conditions from sim_monitor.
165
56b48a7a
CD		 1662001-02-08 Ben Elliston <bje@redhat.com>
167
168 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
169 (store_memory): Likewise, pass cia to sim_core_write*.
170
d3ee60d9
FCE		 1712000-10-19 Frank Ch. Eigler <fche@redhat.com>
172
173 On advice from Chris G. Demetriou <cgd@sibyte.com>:
174 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
175
071da002
AC		 176Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
177
178 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
179 * Makefile.in: Don't delete *.igen when cleaning directory.
180
a28c02cd
AC		 181Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
182
183 * m16.igen (break): Call SignalException not sim_engine_halt.
184
80ee11fa
AC		 185Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
186
187 From Jason Eckhardt:
188 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
189
673388c0
AC		 190Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
191
192 * mips.igen (MxC1, DMxC1): Fix printf formatting.
193
4c0deff4
NC		 1942000-05-24 Michael Hayes <mhayes@cygnus.com>
195
196 * mips.igen (do_dmultx): Fix typo.
197
eb2d80b4
AC		 198Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
199
200 * configure: Regenerated to track ../common/aclocal.m4 changes.
201
dd37a34b
AC		 202Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
203
204 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
205
4c0deff4
NC		 2062000-04-12 Frank Ch. Eigler <fche@redhat.com>
207
208 * sim-main.h (GPR_CLEAR): Define macro.
209
e30db738
AC		 210Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
211
212 * interp.c (decode_coproc): Output long using %lx and not %s.
213
cb7450ea
FCE		 2142000-03-21 Frank Ch. Eigler <fche@redhat.com>
215
216 * interp.c (sim_open): Sort & extend dummy memory regions for
217 --board=jmr3904 for eCos.
218
a3027dd7
FCE		 2192000-03-02 Frank Ch. Eigler <fche@redhat.com>
220
221 * configure: Regenerated.
222
223Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
224
225 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
226 calls, conditional on the simulator being in verbose mode.
227
dfcd3bfb
JM		 228Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
229
230 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
231 cache don't get ReservedInstruction traps.
232
c2d11a7d
JM		 2331999-11-29 Mark Salter <msalter@cygnus.com>
234
235 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
236 to clear status bits in sdisr register. This is how the hardware works.
237
238 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
239 being used by cygmon.
240
4ce44c66
JM		 2411999-11-11 Andrew Haley <aph@cygnus.com>
242
243 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
244 instructions.
245
cff3e48b
JM		 246Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
247
248 * mips.igen (MULT): Correct previous mis-applied patch.
249
d4f3574e
SS		 250Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
251
252 * mips.igen (delayslot32): Handle sequence like
253 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
254 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
255 (MULT): Actually pass the third register...
256
2571999-09-03 Mark Salter <msalter@cygnus.com>
258
259 * interp.c (sim_open): Added more memory aliases for additional
260 hardware being touched by cygmon on jmr3904 board.
261
262Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
263
264 * configure: Regenerated to track ../common/aclocal.m4 changes.
265
a0b3c4fd
JM		 266Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
267
268 * interp.c (sim_store_register): Handle case where client - GDB -
269 specifies that a 4 byte register is 8 bytes in size.
270 (sim_fetch_register): Ditto.
271
adf40b2e
JM		 2721999-07-14 Frank Ch. Eigler <fche@cygnus.com>
273
274 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
275 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
276 (idt_monitor_base): Base address for IDT monitor traps.
277 (pmon_monitor_base): Ditto for PMON.
278 (lsipmon_monitor_base): Ditto for LSI PMON.
279 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
280 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
281 (sim_firmware_command): New function.
282 (mips_option_handler): Call it for OPTION_FIRMWARE.
283 (sim_open): Allocate memory for idt_monitor region. If "--board"
284 option was given, add no monitor by default. Add BREAK hooks only if
285 monitors are also there.
286
43e526b9
JM		 287Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
288
289 * interp.c (sim_monitor): Flush output before reading input.
290
291Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
292
293 * tconfig.in (SIM_HANDLES_LMA): Always define.
294
295Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
296
297 From Mark Salter <msalter@cygnus.com>:
298 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
299 (sim_open): Add setup for BSP board.
300
9846de1b
JM		 301Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
302
303 * mips.igen (MULT, MULTU): Add syntax for two operand version.
304 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
305 them as unimplemented.
306
cd0fc7c3
SS		 3071999-05-08 Felix Lee <flee@cygnus.com>
308
309 * configure: Regenerated to track ../common/aclocal.m4 changes.
310
7a292a7a
SS		 3111999-04-21 Frank Ch. Eigler <fche@cygnus.com>
312
313 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
314
315Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
316
317 * configure.in: Any mips64vr5*-*-* target should have
318 -DTARGET_ENABLE_FR=1.
319 (default_endian): Any mips64vr*el-*-* target should default to
320 LITTLE_ENDIAN.
321 * configure: Re-generate.
322
3231999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
324
325 * mips.igen (ldl): Extend from _16_, not 32.
326
327Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
328
329 * interp.c (sim_store_register): Force registers written to by GDB
330 into an un-interpreted state.
331
c906108c
SS		 3321999-02-05 Frank Ch. Eigler <fche@cygnus.com>
333
334 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
335 CPU, start periodic background I/O polls.
336 (tx3904sio_poll): New function: periodic I/O poller.
337
3381998-12-30 Frank Ch. Eigler <fche@cygnus.com>
339
340 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
341
342Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
343
344 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
345 case statement.
346
3471998-12-29 Frank Ch. Eigler <fche@cygnus.com>
348
349 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
350 (load_word): Call SIM_CORE_SIGNAL hook on error.
351 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
352 starting. For exception dispatching, pass PC instead of NULL_CIA.
353 (decode_coproc): Use COP0_BADVADDR to store faulting address.
354 * sim-main.h (COP0_BADVADDR): Define.
355 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
356 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
357 (_sim_cpu): Add exc_* fields to store register value snapshots.
358 * mips.igen (*): Replace memory-related SignalException* calls
359 with references to SIM_CORE_SIGNAL hook.
360
361 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
362 fix.
363 * sim-main.c (*): Minor warning cleanups.
364
3651998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
366
367 * m16.igen (DADDIU5): Correct type-o.
368
369Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
370
371 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
372 variables.
373
374Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
375
376 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
377 to include path.
378 (interp.o): Add dependency on itable.h
379 (oengine.c, gencode): Delete remaining references.
380 (BUILT_SRC_FROM_GEN): Clean up.
381
3821998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
383
384 * vr4run.c: New.
385 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
386 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
387 tmp-run-hack) : New.
388 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
389 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
390 Drop the "64" qualifier to get the HACK generator working.
391 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
392 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
393 qualifier to get the hack generator working.
394 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
395 (DSLL): Use do_dsll.
396 (DSLLV): Use do_dsllv.
397 (DSRA): Use do_dsra.
398 (DSRL): Use do_dsrl.
399 (DSRLV): Use do_dsrlv.
400 (BC1): Move *vr4100 to get the HACK generator working.
401 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
402 get the HACK generator working.
403 (MACC) Rename to get the HACK generator working.
404 (DMACC,MACCS,DMACCS): Add the 64.
405
4061998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
407
408 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
409 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
410
4111998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
412
413 * mips/interp.c (DEBUG): Cleanups.
414
4151998-12-10 Frank Ch. Eigler <fche@cygnus.com>
416
417 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
418 (tx3904sio_tickle): fflush after a stdout character output.
419
4201998-12-03 Frank Ch. Eigler <fche@cygnus.com>
421
422 * interp.c (sim_close): Uninstall modules.
423
424Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
425
426 * sim-main.h, interp.c (sim_monitor): Change to global
427 function.
428
429Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
430
431 * configure.in (vr4100): Only include vr4100 instructions in
432 simulator.
433 * configure: Re-generate.
434 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
435
436Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
437
438 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
439 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
440 true alternative.
441
442 * configure.in (sim_default_gen, sim_use_gen): Replace with
443 sim_gen.
444 (--enable-sim-igen): Delete config option. Always using IGEN.
445 * configure: Re-generate.
446
447 * Makefile.in (gencode): Kill, kill, kill.
448 * gencode.c: Ditto.
449
450Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
451
452 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
453 bit mips16 igen simulator.
454 * configure: Re-generate.
455
456 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
457 as part of vr4100 ISA.
458 * vr.igen: Mark all instructions as 64 bit only.
459
460Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
461
462 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
463 Pacify GCC.
464
465Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
466
467 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
468 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
469 * configure: Re-generate.
470
471 * m16.igen (BREAK): Define breakpoint instruction.
472 (JALX32): Mark instruction as mips16 and not r3900.
473 * mips.igen (C.cond.fmt): Fix typo in instruction format.
474
475 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
476
477Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
478
479 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
480 insn as a debug breakpoint.
481
482 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
483 pending.slot_size.
484 (PENDING_SCHED): Clean up trace statement.
485 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
486 (PENDING_FILL): Delay write by only one cycle.
487 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
488
489 * sim-main.c (pending_tick): Clean up trace statements. Add trace
490 of pending writes.
491 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
492 32 & 64.
493 (pending_tick): Move incrementing of index to FOR statement.
494 (pending_tick): Only update PENDING_OUT after a write has occured.
495
496 * configure.in: Add explicit mips-lsi-* target. Use gencode to
497 build simulator.
498 * configure: Re-generate.
499
500 * interp.c (sim_engine_run OLD): Delete explicit call to
501 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
502
503Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
504
505 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
506 interrupt level number to match changed SignalExceptionInterrupt
507 macro.
508
509Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
510
511 * interp.c: #include "itable.h" if WITH_IGEN.
512 (get_insn_name): New function.
513 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
514 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
515
516Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
517
518 * configure: Rebuilt to inhale new common/aclocal.m4.
519
520Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
521
522 * dv-tx3904sio.c: Include sim-assert.h.
523
524Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
525
526 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
527 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
528 Reorganize target-specific sim-hardware checks.
529 * configure: rebuilt.
530 * interp.c (sim_open): For tx39 target boards, set
531 OPERATING_ENVIRONMENT, add tx3904sio devices.
532 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
533 ROM executables. Install dv-sockser into sim-modules list.
534
535 * dv-tx3904irc.c: Compiler warning clean-up.
536 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
537 frequent hw-trace messages.
538
539Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
540
541 * vr.igen (MulAcc): Identify as a vr4100 specific function.
542
543Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
544
545 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
546
547 * vr.igen: New file.
548 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
549 * mips.igen: Define vr4100 model. Include vr.igen.
550Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
551
552 * mips.igen (check_mf_hilo): Correct check.
553
554Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
555
556 * sim-main.h (interrupt_event): Add prototype.
557
558 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
559 register_ptr, register_value.
560 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
561
562 * sim-main.h (tracefh): Make extern.
563
564Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
565
566 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
567 Reduce unnecessarily high timer event frequency.
568 * dv-tx3904cpu.c: Ditto for interrupt event.
569
570Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
571
572 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
573 to allay warnings.
574 (interrupt_event): Made non-static.
575
576 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
577 interchange of configuration values for external vs. internal
578 clock dividers.
579
580Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
581
582 * mips.igen (BREAK): Moved code to here for
583 simulator-reserved break instructions.
584 * gencode.c (build_instruction): Ditto.
585 * interp.c (signal_exception): Code moved from here. Non-
586 reserved instructions now use exception vector, rather
587 than halting sim.
588 * sim-main.h: Moved magic constants to here.
589
590Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
591
592 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
593 register upon non-zero interrupt event level, clear upon zero
594 event value.
595 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
596 by passing zero event value.
597 (*_io_{read,write}_buffer): Endianness fixes.
598 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
599 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
600
601 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
602 serial I/O and timer module at base address 0xFFFF0000.
603
604Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
605
606 * mips.igen (SWC1) : Correct the handling of ReverseEndian
607 and BigEndianCPU.
608
609Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
610
611 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
612 parts.
613 * configure: Update.
614
615Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
616
617 * dv-tx3904tmr.c: New file - implements tx3904 timer.
618 * dv-tx3904{irc,cpu}.c: Mild reformatting.
619 * configure.in: Include tx3904tmr in hw_device list.
620 * configure: Rebuilt.
621 * interp.c (sim_open): Instantiate three timer instances.
622 Fix address typo of tx3904irc instance.
623
624Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
625
626 * interp.c (signal_exception): SystemCall exception now uses
627 the exception vector.
628
629Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
630
631 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
632 to allay warnings.
633
634Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
635
636 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
637
638Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
639
640 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
641
642 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
643 sim-main.h. Declare a struct hw_descriptor instead of struct
644 hw_device_descriptor.
645
646Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
647
648 * mips.igen (do_store_left, do_load_left): Compute nr of left and
649 right bits and then re-align left hand bytes to correct byte
650 lanes. Fix incorrect computation in do_store_left when loading
651 bytes from second word.
652
653Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
654
655 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
656 * interp.c (sim_open): Only create a device tree when HW is
657 enabled.
658
659 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
660 * interp.c (signal_exception): Ditto.
661
662Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
663
664 * gencode.c: Mark BEGEZALL as LIKELY.
665
666Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
667
668 * sim-main.h (ALU32_END): Sign extend 32 bit results.
669 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
670
671Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
672
673 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
674 modules. Recognize TX39 target with "mips*tx39" pattern.
675 * configure: Rebuilt.
676 * sim-main.h (*): Added many macros defining bits in
677 TX39 control registers.
678 (SignalInterrupt): Send actual PC instead of NULL.
679 (SignalNMIReset): New exception type.
680 * interp.c (board): New variable for future use to identify
681 a particular board being simulated.
682 (mips_option_handler,mips_options): Added "--board" option.
683 (interrupt_event): Send actual PC.
684 (sim_open): Make memory layout conditional on board setting.
685 (signal_exception): Initial implementation of hardware interrupt
686 handling. Accept another break instruction variant for simulator
687 exit.
688 (decode_coproc): Implement RFE instruction for TX39.
689 (mips.igen): Decode RFE instruction as such.
690 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
691 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
692 bbegin to implement memory map.
693 * dv-tx3904cpu.c: New file.
694 * dv-tx3904irc.c: New file.
695
696Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
697
698 * mips.igen (check_mt_hilo): Create a separate r3900 version.
699
700Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
701
702 * tx.igen (madd,maddu): Replace calls to check_op_hilo
703 with calls to check_div_hilo.
704
705Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
706
707 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
708 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
709 Add special r3900 version of do_mult_hilo.
710 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
711 with calls to check_mult_hilo.
712 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
713 with calls to check_div_hilo.
714
715Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
716
717 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
718 Document a replacement.
719
720Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
721
722 * interp.c (sim_monitor): Make mon_printf work.
723
724Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
725
726 * sim-main.h (INSN_NAME): New arg `cpu'.
727
728Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
729
730 * configure: Regenerated to track ../common/aclocal.m4 changes.
731
732Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
733
734 * configure: Regenerated to track ../common/aclocal.m4 changes.
735 * config.in: Ditto.
736
737Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
738
739 * acconfig.h: New file.
740 * configure.in: Reverted change of Apr 24; use sinclude again.
741
742Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
743
744 * configure: Regenerated to track ../common/aclocal.m4 changes.
745 * config.in: Ditto.
746
747Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
748
749 * configure.in: Don't call sinclude.
750
751Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
752
753 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
754
755Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
756
757 * mips.igen (ERET): Implement.
758
759 * interp.c (decode_coproc): Return sign-extended EPC.
760
761 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
762
763 * interp.c (signal_exception): Do not ignore Trap.
764 (signal_exception): On TRAP, restart at exception address.
765 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
766 (signal_exception): Update.
767 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
768 so that TRAP instructions are caught.
769
770Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
771
772 * sim-main.h (struct hilo_access, struct hilo_history): Define,
773 contains HI/LO access history.
774 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
775 (HIACCESS, LOACCESS): Delete, replace with
776 (HIHISTORY, LOHISTORY): New macros.
777 (CHECKHILO): Delete all, moved to mips.igen
778
779 * gencode.c (build_instruction): Do not generate checks for
780 correct HI/LO register usage.
781
782 * interp.c (old_engine_run): Delete checks for correct HI/LO
783 register usage.
784
785 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
786 check_mf_cycles): New functions.
787 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
788 do_divu, domultx, do_mult, do_multu): Use.
789
790 * tx.igen ("madd", "maddu"): Use.
791
792Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
793
794 * mips.igen (DSRAV): Use function do_dsrav.
795 (SRAV): Use new function do_srav.
796
797 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
798 (B): Sign extend 11 bit immediate.
799 (EXT-B*): Shift 16 bit immediate left by 1.
800 (ADDIU*): Don't sign extend immediate value.
801
802Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
803
804 * m16run.c (sim_engine_run): Restore CIA after handling an event.
805
806 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
807 functions.
808
809 * mips.igen (delayslot32, nullify_next_insn): New functions.
810 (m16.igen): Always include.
811 (do_*): Add more tracing.
812
813 * m16.igen (delayslot16): Add NIA argument, could be called by a
814 32 bit MIPS16 instruction.
815
816 * interp.c (ifetch16): Move function from here.
817 * sim-main.c (ifetch16): To here.
818
819 * sim-main.c (ifetch16, ifetch32): Update to match current
820 implementations of LH, LW.
821 (signal_exception): Don't print out incorrect hex value of illegal
822 instruction.
823
824Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
825
826 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
827 instruction.
828
829 * m16.igen: Implement MIPS16 instructions.
830
831 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
832 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
833 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
834 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
835 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
836 bodies of corresponding code from 32 bit insn to these. Also used
837 by MIPS16 versions of functions.
838
839 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
840 (IMEM16): Drop NR argument from macro.
841
842Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
843
844 * Makefile.in (SIM_OBJS): Add sim-main.o.
845
846 * sim-main.h (address_translation, load_memory, store_memory,
847 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
848 as INLINE_SIM_MAIN.
849 (pr_addr, pr_uword64): Declare.
850 (sim-main.c): Include when H_REVEALS_MODULE_P.
851
852 * interp.c (address_translation, load_memory, store_memory,
853 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
854 from here.
855 * sim-main.c: To here. Fix compilation problems.
856
857 * configure.in: Enable inlining.
858 * configure: Re-config.
859
860Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
861
862 * configure: Regenerated to track ../common/aclocal.m4 changes.
863
864Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
865
866 * mips.igen: Include tx.igen.
867 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
868 * tx.igen: New file, contains MADD and MADDU.
869
870 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
871 the hardwired constant `7'.
872 (store_memory): Ditto.
873 (LOADDRMASK): Move definition to sim-main.h.
874
875 mips.igen (MTC0): Enable for r3900.
876 (ADDU): Add trace.
877
878 mips.igen (do_load_byte): Delete.
879 (do_load, do_store, do_load_left, do_load_write, do_store_left,
880 do_store_right): New functions.
881 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
882
883 configure.in: Let the tx39 use igen again.
884 configure: Update.
885
886Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
887
888 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
889 not an address sized quantity. Return zero for cache sizes.
890
891Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
892
893 * mips.igen (r3900): r3900 does not support 64 bit integer
894 operations.
895
896Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
897
898 * configure.in (mipstx39*-*-*): Use gencode simulator rather
899 than igen one.
900 * configure : Rebuild.
901
902Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
903
904 * configure: Regenerated to track ../common/aclocal.m4 changes.
905
906Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
907
908 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
909
910Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
911
912 * configure: Regenerated to track ../common/aclocal.m4 changes.
913 * config.in: Regenerated to track ../common/aclocal.m4 changes.
914
915Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
916
917 * configure: Regenerated to track ../common/aclocal.m4 changes.
918
919Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
920
921 * interp.c (Max, Min): Comment out functions. Not yet used.
922
923Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
924
925 * configure: Regenerated to track ../common/aclocal.m4 changes.
926
927Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
928
929 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
930 configurable settings for stand-alone simulator.
931
932 * configure.in: Added X11 search, just in case.
933
934 * configure: Regenerated.
935
936Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
937
938 * interp.c (sim_write, sim_read, load_memory, store_memory):
939 Replace sim_core_*_map with read_map, write_map, exec_map resp.
940
941Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
942
943 * sim-main.h (GETFCC): Return an unsigned value.
944
945Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
946
947 * mips.igen (DIV): Fix check for -1 / MIN_INT.
948 (DADD): Result destination is RD not RT.
949
950Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
951
952 * sim-main.h (HIACCESS, LOACCESS): Always define.
953
954 * mdmx.igen (Maxi, Mini): Rename Max, Min.
955
956 * interp.c (sim_info): Delete.
957
958Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
959
960 * interp.c (DECLARE_OPTION_HANDLER): Use it.
961 (mips_option_handler): New argument `cpu'.
962 (sim_open): Update call to sim_add_option_table.
963
964Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
965
966 * mips.igen (CxC1): Add tracing.
967
968Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
969
970 * sim-main.h (Max, Min): Declare.
971
972 * interp.c (Max, Min): New functions.
973
974 * mips.igen (BC1): Add tracing.
975
976Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
977
978 * interp.c Added memory map for stack in vr4100
979
980Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
981
982 * interp.c (load_memory): Add missing "break"'s.
983
984Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
985
986 * interp.c (sim_store_register, sim_fetch_register): Pass in
987 length parameter. Return -1.
988
989Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
990
991 * interp.c: Added hardware init hook, fixed warnings.
992
993Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
994
995 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
996
997Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
998
999 * interp.c (ifetch16): New function.
1000
1001 * sim-main.h (IMEM32): Rename IMEM.
1002 (IMEM16_IMMED): Define.
1003 (IMEM16): Define.
1004 (DELAY_SLOT): Update.
1005
1006 * m16run.c (sim_engine_run): New file.
1007
1008 * m16.igen: All instructions except LB.
1009 (LB): Call do_load_byte.
1010 * mips.igen (do_load_byte): New function.
1011 (LB): Call do_load_byte.
1012
1013 * mips.igen: Move spec for insn bit size and high bit from here.
1014 * Makefile.in (tmp-igen, tmp-m16): To here.
1015
1016 * m16.dc: New file, decode mips16 instructions.
1017
1018 * Makefile.in (SIM_NO_ALL): Define.
1019 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1020
1021Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1022
1023 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1024 point unit to 32 bit registers.
1025 * configure: Re-generate.
1026
1027Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1028
1029 * configure.in (sim_use_gen): Make IGEN the default simulator
1030 generator for generic 32 and 64 bit mips targets.
1031 * configure: Re-generate.
1032
1033Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1034
1035 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1036 bitsize.
1037
1038 * interp.c (sim_fetch_register, sim_store_register): Read/write
1039 FGR from correct location.
1040 (sim_open): Set size of FGR's according to
1041 WITH_TARGET_FLOATING_POINT_BITSIZE.
1042
1043 * sim-main.h (FGR): Store floating point registers in a separate
1044 array.
1045
1046Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1047
1048 * configure: Regenerated to track ../common/aclocal.m4 changes.
1049
1050Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1051
1052 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1053
1054 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1055
1056 * interp.c (pending_tick): New function. Deliver pending writes.
1057
1058 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1059 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1060 it can handle mixed sized quantites and single bits.
1061
1062Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1063
1064 * interp.c (oengine.h): Do not include when building with IGEN.
1065 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1066 (sim_info): Ditto for PROCESSOR_64BIT.
1067 (sim_monitor): Replace ut_reg with unsigned_word.
1068 (*): Ditto for t_reg.
1069 (LOADDRMASK): Define.
1070 (sim_open): Remove defunct check that host FP is IEEE compliant,
1071 using software to emulate floating point.
1072 (value_fpr, ...): Always compile, was conditional on HASFPU.
1073
1074Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1075
1076 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1077 size.
1078
1079 * interp.c (SD, CPU): Define.
1080 (mips_option_handler): Set flags in each CPU.
1081 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1082 (sim_close): Do not clear STATE, deleted anyway.
1083 (sim_write, sim_read): Assume CPU zero's vm should be used for
1084 data transfers.
1085 (sim_create_inferior): Set the PC for all processors.
1086 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1087 argument.
1088 (mips16_entry): Pass correct nr of args to store_word, load_word.
1089 (ColdReset): Cold reset all cpu's.
1090 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1091 (sim_monitor, load_memory, store_memory, signal_exception): Use
1092 `CPU' instead of STATE_CPU.
1093
1094
1095 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1096 SD or CPU_.
1097
1098 * sim-main.h (signal_exception): Add sim_cpu arg.
1099 (SignalException*): Pass both SD and CPU to signal_exception.
1100 * interp.c (signal_exception): Update.
1101
1102 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1103 Ditto
1104 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1105 address_translation): Ditto
1106 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1107
1108Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1109
1110 * configure: Regenerated to track ../common/aclocal.m4 changes.
1111
1112Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1113
1114 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1115
1116 * mips.igen (model): Map processor names onto BFD name.
1117
1118 * sim-main.h (CPU_CIA): Delete.
1119 (SET_CIA, GET_CIA): Define
1120
1121Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1122
1123 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1124 regiser.
1125
1126 * configure.in (default_endian): Configure a big-endian simulator
1127 by default.
1128 * configure: Re-generate.
1129
1130Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1131
1132 * configure: Regenerated to track ../common/aclocal.m4 changes.
1133
1134Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1135
1136 * interp.c (sim_monitor): Handle Densan monitor outbyte
1137 and inbyte functions.
1138
11391997-12-29 Felix Lee <flee@cygnus.com>
1140
1141 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1142
1143Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1144
1145 * Makefile.in (tmp-igen): Arrange for $zero to always be
1146 reset to zero after every instruction.
1147
1148Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1149
1150 * configure: Regenerated to track ../common/aclocal.m4 changes.
1151 * config.in: Ditto.
1152
1153Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1154
1155 * mips.igen (MSUB): Fix to work like MADD.
1156 * gencode.c (MSUB): Similarly.
1157
1158Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1159
1160 * configure: Regenerated to track ../common/aclocal.m4 changes.
1161
1162Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1163
1164 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1165
1166Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1167
1168 * sim-main.h (sim-fpu.h): Include.
1169
1170 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1171 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1172 using host independant sim_fpu module.
1173
1174Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1175
1176 * interp.c (signal_exception): Report internal errors with SIGABRT
1177 not SIGQUIT.
1178
1179 * sim-main.h (C0_CONFIG): New register.
1180 (signal.h): No longer include.
1181
1182 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1183
1184Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1185
1186 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1187
1188Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1189
1190 * mips.igen: Tag vr5000 instructions.
1191 (ANDI): Was missing mipsIV model, fix assembler syntax.
1192 (do_c_cond_fmt): New function.
1193 (C.cond.fmt): Handle mips I-III which do not support CC field
1194 separatly.
1195 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1196 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1197 in IV3.2 spec.
1198 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1199 vr5000 which saves LO in a GPR separatly.
1200
1201 * configure.in (enable-sim-igen): For vr5000, select vr5000
1202 specific instructions.
1203 * configure: Re-generate.
1204
1205Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1206
1207 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1208
1209 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1210 fmt_uninterpreted_64 bit cases to switch. Convert to
1211 fmt_formatted,
1212
1213 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1214
1215 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1216 as specified in IV3.2 spec.
1217 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1218
1219Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1220
1221 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1222 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1223 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1224 PENDING_FILL versions of instructions. Simplify.
1225 (X): New function.
1226 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1227 instructions.
1228 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1229 a signed value.
1230 (MTHI, MFHI): Disable code checking HI-LO.
1231
1232 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1233 global.
1234 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1235
1236Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1237
1238 * gencode.c (build_mips16_operands): Replace IPC with cia.
1239
1240 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1241 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1242 IPC to `cia'.
1243 (UndefinedResult): Replace function with macro/function
1244 combination.
1245 (sim_engine_run): Don't save PC in IPC.
1246
1247 * sim-main.h (IPC): Delete.
1248
1249
1250 * interp.c (signal_exception, store_word, load_word,
1251 address_translation, load_memory, store_memory, cache_op,
1252 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1253 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1254 current instruction address - cia - argument.
1255 (sim_read, sim_write): Call address_translation directly.
1256 (sim_engine_run): Rename variable vaddr to cia.
1257 (signal_exception): Pass cia to sim_monitor
1258
1259 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1260 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1261 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1262
1263 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1264 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1265 SIM_ASSERT.
1266
1267 * interp.c (signal_exception): Pass restart address to
1268 sim_engine_restart.
1269
1270 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1271 idecode.o): Add dependency.
1272
1273 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1274 Delete definitions
1275 (DELAY_SLOT): Update NIA not PC with branch address.
1276 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1277
1278 * mips.igen: Use CIA not PC in branch calculations.
1279 (illegal): Call SignalException.
1280 (BEQ, ADDIU): Fix assembler.
1281
1282Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1283
1284 * m16.igen (JALX): Was missing.
1285
1286 * configure.in (enable-sim-igen): New configuration option.
1287 * configure: Re-generate.
1288
1289 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1290
1291 * interp.c (load_memory, store_memory): Delete parameter RAW.
1292 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1293 bypassing {load,store}_memory.
1294
1295 * sim-main.h (ByteSwapMem): Delete definition.
1296
1297 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1298
1299 * interp.c (sim_do_command, sim_commands): Delete mips specific
1300 commands. Handled by module sim-options.
1301
1302 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1303 (WITH_MODULO_MEMORY): Define.
1304
1305 * interp.c (sim_info): Delete code printing memory size.
1306
1307 * interp.c (mips_size): Nee sim_size, delete function.
1308 (power2): Delete.
1309 (monitor, monitor_base, monitor_size): Delete global variables.
1310 (sim_open, sim_close): Delete code creating monitor and other
1311 memory regions. Use sim-memopts module, via sim_do_commandf, to
1312 manage memory regions.
1313 (load_memory, store_memory): Use sim-core for memory model.
1314
1315 * interp.c (address_translation): Delete all memory map code
1316 except line forcing 32 bit addresses.
1317
1318Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1319
1320 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1321 trace options.
1322
1323 * interp.c (logfh, logfile): Delete globals.
1324 (sim_open, sim_close): Delete code opening & closing log file.
1325 (mips_option_handler): Delete -l and -n options.
1326 (OPTION mips_options): Ditto.
1327
1328 * interp.c (OPTION mips_options): Rename option trace to dinero.
1329 (mips_option_handler): Update.
1330
1331Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1332
1333 * interp.c (fetch_str): New function.
1334 (sim_monitor): Rewrite using sim_read & sim_write.
1335 (sim_open): Check magic number.
1336 (sim_open): Write monitor vectors into memory using sim_write.
1337 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1338 (sim_read, sim_write): Simplify - transfer data one byte at a
1339 time.
1340 (load_memory, store_memory): Clarify meaning of parameter RAW.
1341
1342 * sim-main.h (isHOST): Defete definition.
1343 (isTARGET): Mark as depreciated.
1344 (address_translation): Delete parameter HOST.
1345
1346 * interp.c (address_translation): Delete parameter HOST.
1347
1348Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1349
1350 * mips.igen:
1351
1352 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1353 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1354
1355Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1356
1357 * mips.igen: Add model filter field to records.
1358
1359Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1360
1361 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1362
1363 interp.c (sim_engine_run): Do not compile function sim_engine_run
1364 when WITH_IGEN == 1.
1365
1366 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1367 target architecture.
1368
1369 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1370 igen. Replace with configuration variables sim_igen_flags /
1371 sim_m16_flags.
1372
1373 * m16.igen: New file. Copy mips16 insns here.
1374 * mips.igen: From here.
1375
1376Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1377
1378 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1379 to top.
1380 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1381
1382Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1383
1384 * gencode.c (build_instruction): Follow sim_write's lead in using
1385 BigEndianMem instead of !ByteSwapMem.
1386
1387Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1388
1389 * configure.in (sim_gen): Dependent on target, select type of
1390 generator. Always select old style generator.
1391
1392 configure: Re-generate.
1393
1394 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1395 targets.
1396 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1397 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1398 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1399 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1400 SIM_@sim_gen@_*, set by autoconf.
1401
1402Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1403
1404 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1405
1406 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1407 CURRENT_FLOATING_POINT instead.
1408
1409 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1410 (address_translation): Raise exception InstructionFetch when
1411 translation fails and isINSTRUCTION.
1412
1413 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1414 sim_engine_run): Change type of of vaddr and paddr to
1415 address_word.
1416 (address_translation, prefetch, load_memory, store_memory,
1417 cache_op): Change type of vAddr and pAddr to address_word.
1418
1419 * gencode.c (build_instruction): Change type of vaddr and paddr to
1420 address_word.
1421
1422Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1423
1424 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1425 macro to obtain result of ALU op.
1426
1427Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1428
1429 * interp.c (sim_info): Call profile_print.
1430
1431Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1432
1433 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1434
1435 * sim-main.h (WITH_PROFILE): Do not define, defined in
1436 common/sim-config.h. Use sim-profile module.
1437 (simPROFILE): Delete defintion.
1438
1439 * interp.c (PROFILE): Delete definition.
1440 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1441 (sim_close): Delete code writing profile histogram.
1442 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1443 Delete.
1444 (sim_engine_run): Delete code profiling the PC.
1445
1446Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1447
1448 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1449
1450 * interp.c (sim_monitor): Make register pointers of type
1451 unsigned_word*.
1452
1453 * sim-main.h: Make registers of type unsigned_word not
1454 signed_word.
1455
1456Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1457
1458 * interp.c (sync_operation): Rename from SyncOperation, make
1459 global, add SD argument.
1460 (prefetch): Rename from Prefetch, make global, add SD argument.
1461 (decode_coproc): Make global.
1462
1463 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1464
1465 * gencode.c (build_instruction): Generate DecodeCoproc not
1466 decode_coproc calls.
1467
1468 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1469 (SizeFGR): Move to sim-main.h
1470 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1471 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1472 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1473 sim-main.h.
1474 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1475 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1476 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1477 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1478 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1479 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1480
1481 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1482 exception.
1483 (sim-alu.h): Include.
1484 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1485 (sim_cia): Typedef to instruction_address.
1486
1487Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1488
1489 * Makefile.in (interp.o): Rename generated file engine.c to
1490 oengine.c.
1491
1492 * interp.c: Update.
1493
1494Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1495
1496 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1497
1498Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1499
1500 * gencode.c (build_instruction): For "FPSQRT", output correct
1501 number of arguments to Recip.
1502
1503Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1504
1505 * Makefile.in (interp.o): Depends on sim-main.h
1506
1507 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1508
1509 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1510 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1511 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1512 STATE, DSSTATE): Define
1513 (GPR, FGRIDX, ..): Define.
1514
1515 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1516 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1517 (GPR, FGRIDX, ...): Delete macros.
1518
1519 * interp.c: Update names to match defines from sim-main.h
1520
1521Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1522
1523 * interp.c (sim_monitor): Add SD argument.
1524 (sim_warning): Delete. Replace calls with calls to
1525 sim_io_eprintf.
1526 (sim_error): Delete. Replace calls with sim_io_error.
1527 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1528 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1529 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1530 argument.
1531 (mips_size): Rename from sim_size. Add SD argument.
1532
1533 * interp.c (simulator): Delete global variable.
1534 (callback): Delete global variable.
1535 (mips_option_handler, sim_open, sim_write, sim_read,
1536 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1537 sim_size,sim_monitor): Use sim_io_* not callback->*.
1538 (sim_open): ZALLOC simulator struct.
1539 (PROFILE): Do not define.
1540
1541Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1542
1543 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1544 support.h with corresponding code.
1545
1546 * sim-main.h (word64, uword64), support.h: Move definition to
1547 sim-main.h.
1548 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1549
1550 * support.h: Delete
1551 * Makefile.in: Update dependencies
1552 * interp.c: Do not include.
1553
1554Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1555
1556 * interp.c (address_translation, load_memory, store_memory,
1557 cache_op): Rename to from AddressTranslation et.al., make global,
1558 add SD argument
1559
1560 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1561 CacheOp): Define.
1562
1563 * interp.c (SignalException): Rename to signal_exception, make
1564 global.
1565
1566 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1567
1568 * sim-main.h (SignalException, SignalExceptionInterrupt,
1569 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1570 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1571 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1572 Define.
1573
1574 * interp.c, support.h: Use.
1575
1576Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1577
1578 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1579 to value_fpr / store_fpr. Add SD argument.
1580 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1581 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1582
1583 * sim-main.h (ValueFPR, StoreFPR): Define.
1584
1585Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1586
1587 * interp.c (sim_engine_run): Check consistency between configure
1588 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1589 and HASFPU.
1590
1591 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1592 (mips_fpu): Configure WITH_FLOATING_POINT.
1593 (mips_endian): Configure WITH_TARGET_ENDIAN.
1594 * configure: Update.
1595
1596Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1597
1598 * configure: Regenerated to track ../common/aclocal.m4 changes.
1599
1600Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1601
1602 * configure: Regenerated.
1603
1604Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1605
1606 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1607
1608Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1609
1610 * gencode.c (print_igen_insn_models): Assume certain architectures
1611 include all mips* instructions.
1612 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1613 instruction.
1614
1615 * Makefile.in (tmp.igen): Add target. Generate igen input from
1616 gencode file.
1617
1618 * gencode.c (FEATURE_IGEN): Define.
1619 (main): Add --igen option. Generate output in igen format.
1620 (process_instructions): Format output according to igen option.
1621 (print_igen_insn_format): New function.
1622 (print_igen_insn_models): New function.
1623 (process_instructions): Only issue warnings and ignore
1624 instructions when no FEATURE_IGEN.
1625
1626Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1627
1628 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1629 MIPS targets.
1630
1631Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632
1633 * configure: Regenerated to track ../common/aclocal.m4 changes.
1634
1635Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1636
1637 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1638 SIM_RESERVED_BITS): Delete, moved to common.
1639 (SIM_EXTRA_CFLAGS): Update.
1640
1641Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1642
1643 * configure.in: Configure non-strict memory alignment.
1644 * configure: Regenerated to track ../common/aclocal.m4 changes.
1645
1646Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1647
1648 * configure: Regenerated to track ../common/aclocal.m4 changes.
1649
1650Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1651
1652 * gencode.c (SDBBP,DERET): Added (3900) insns.
1653 (RFE): Turn on for 3900.
1654 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1655 (dsstate): Made global.
1656 (SUBTARGET_R3900): Added.
1657 (CANCELDELAYSLOT): New.
1658 (SignalException): Ignore SystemCall rather than ignore and
1659 terminate. Add DebugBreakPoint handling.
1660 (decode_coproc): New insns RFE, DERET; and new registers Debug
1661 and DEPC protected by SUBTARGET_R3900.
1662 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1663 bits explicitly.
1664 * Makefile.in,configure.in: Add mips subtarget option.
1665 * configure: Update.
1666
1667Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1668
1669 * gencode.c: Add r3900 (tx39).
1670
1671
1672Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1673
1674 * gencode.c (build_instruction): Don't need to subtract 4 for
1675 JALR, just 2.
1676
1677Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1678
1679 * interp.c: Correct some HASFPU problems.
1680
1681Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1682
1683 * configure: Regenerated to track ../common/aclocal.m4 changes.
1684
1685Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1686
1687 * interp.c (mips_options): Fix samples option short form, should
1688 be `x'.
1689
1690Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1691
1692 * interp.c (sim_info): Enable info code. Was just returning.
1693
1694Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1695
1696 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1697 MFC0.
1698
1699Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1700
1701 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1702 constants.
1703 (build_instruction): Ditto for LL.
1704
1705Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1706
1707 * configure: Regenerated to track ../common/aclocal.m4 changes.
1708
1709Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1710
1711 * configure: Regenerated to track ../common/aclocal.m4 changes.
1712 * config.in: Ditto.
1713
1714Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1715
1716 * interp.c (sim_open): Add call to sim_analyze_program, update
1717 call to sim_config.
1718
1719Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1720
1721 * interp.c (sim_kill): Delete.
1722 (sim_create_inferior): Add ABFD argument. Set PC from same.
1723 (sim_load): Move code initializing trap handlers from here.
1724 (sim_open): To here.
1725 (sim_load): Delete, use sim-hload.c.
1726
1727 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1728
1729Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1730
1731 * configure: Regenerated to track ../common/aclocal.m4 changes.
1732 * config.in: Ditto.
1733
1734Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1735
1736 * interp.c (sim_open): Add ABFD argument.
1737 (sim_load): Move call to sim_config from here.
1738 (sim_open): To here. Check return status.
1739
1740Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1741
1742 * gencode.c (build_instruction): Two arg MADD should
1743 not assign result to $0.
1744
1745Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1746
1747 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1748 * sim/mips/configure.in: Regenerate.
1749
1750Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1751
1752 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1753 signed8, unsigned8 et.al. types.
1754
1755 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1756 hosts when selecting subreg.
1757
1758Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1759
1760 * interp.c (sim_engine_run): Reset the ZERO register to zero
1761 regardless of FEATURE_WARN_ZERO.
1762 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1763
1764Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1765
1766 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1767 (SignalException): For BreakPoints ignore any mode bits and just
1768 save the PC.
1769 (SignalException): Always set the CAUSE register.
1770
1771Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1772
1773 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1774 exception has been taken.
1775
1776 * interp.c: Implement the ERET and mt/f sr instructions.
1777
1778Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1779
1780 * interp.c (SignalException): Don't bother restarting an
1781 interrupt.
1782
1783Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1784
1785 * interp.c (SignalException): Really take an interrupt.
1786 (interrupt_event): Only deliver interrupts when enabled.
1787
1788Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1789
1790 * interp.c (sim_info): Only print info when verbose.
1791 (sim_info) Use sim_io_printf for output.
1792
1793Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1794
1795 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1796 mips architectures.
1797
1798Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1799
1800 * interp.c (sim_do_command): Check for common commands if a
1801 simulator specific command fails.
1802
1803Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1804
1805 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1806 and simBE when DEBUG is defined.
1807
1808Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1809
1810 * interp.c (interrupt_event): New function. Pass exception event
1811 onto exception handler.
1812
1813 * configure.in: Check for stdlib.h.
1814 * configure: Regenerate.
1815
1816 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1817 variable declaration.
1818 (build_instruction): Initialize memval1.
1819 (build_instruction): Add UNUSED attribute to byte, bigend,
1820 reverse.
1821 (build_operands): Ditto.
1822
1823 * interp.c: Fix GCC warnings.
1824 (sim_get_quit_code): Delete.
1825
1826 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1827 * Makefile.in: Ditto.
1828 * configure: Re-generate.
1829
1830 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1831
1832Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1833
1834 * interp.c (mips_option_handler): New function parse argumes using
1835 sim-options.
1836 (myname): Replace with STATE_MY_NAME.
1837 (sim_open): Delete check for host endianness - performed by
1838 sim_config.
1839 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1840 (sim_open): Move much of the initialization from here.
1841 (sim_load): To here. After the image has been loaded and
1842 endianness set.
1843 (sim_open): Move ColdReset from here.
1844 (sim_create_inferior): To here.
1845 (sim_open): Make FP check less dependant on host endianness.
1846
1847 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1848 run.
1849 * interp.c (sim_set_callbacks): Delete.
1850
1851 * interp.c (membank, membank_base, membank_size): Replace with
1852 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1853 (sim_open): Remove call to callback->init. gdb/run do this.
1854
1855 * interp.c: Update
1856
1857 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1858
1859 * interp.c (big_endian_p): Delete, replaced by
1860 current_target_byte_order.
1861
1862Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1863
1864 * interp.c (host_read_long, host_read_word, host_swap_word,
1865 host_swap_long): Delete. Using common sim-endian.
1866 (sim_fetch_register, sim_store_register): Use H2T.
1867 (pipeline_ticks): Delete. Handled by sim-events.
1868 (sim_info): Update.
1869 (sim_engine_run): Update.
1870
1871Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1872
1873 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1874 reason from here.
1875 (SignalException): To here. Signal using sim_engine_halt.
1876 (sim_stop_reason): Delete, moved to common.
1877
1878Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1879
1880 * interp.c (sim_open): Add callback argument.
1881 (sim_set_callbacks): Delete SIM_DESC argument.
1882 (sim_size): Ditto.
1883
1884Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1885
1886 * Makefile.in (SIM_OBJS): Add common modules.
1887
1888 * interp.c (sim_set_callbacks): Also set SD callback.
1889 (set_endianness, xfer_*, swap_*): Delete.
1890 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1891 Change to functions using sim-endian macros.
1892 (control_c, sim_stop): Delete, use common version.
1893 (simulate): Convert into.
1894 (sim_engine_run): This function.
1895 (sim_resume): Delete.
1896
1897 * interp.c (simulation): New variable - the simulator object.
1898 (sim_kind): Delete global - merged into simulation.
1899 (sim_load): Cleanup. Move PC assignment from here.
1900 (sim_create_inferior): To here.
1901
1902 * sim-main.h: New file.
1903 * interp.c (sim-main.h): Include.
1904
1905Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1906
1907 * configure: Regenerated to track ../common/aclocal.m4 changes.
1908
1909Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1910
1911 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1912
1913Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1914
1915 * gencode.c (build_instruction): DIV instructions: check
1916 for division by zero and integer overflow before using
1917 host's division operation.
1918
1919Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1920
1921 * Makefile.in (SIM_OBJS): Add sim-load.o.
1922 * interp.c: #include bfd.h.
1923 (target_byte_order): Delete.
1924 (sim_kind, myname, big_endian_p): New static locals.
1925 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1926 after argument parsing. Recognize -E arg, set endianness accordingly.
1927 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1928 load file into simulator. Set PC from bfd.
1929 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1930 (set_endianness): Use big_endian_p instead of target_byte_order.
1931
1932Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1933
1934 * interp.c (sim_size): Delete prototype - conflicts with
1935 definition in remote-sim.h. Correct definition.
1936
1937Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1938
1939 * configure: Regenerated to track ../common/aclocal.m4 changes.
1940 * config.in: Ditto.
1941
1942Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1943
1944 * interp.c (sim_open): New arg `kind'.
1945
1946 * configure: Regenerated to track ../common/aclocal.m4 changes.
1947
1948Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1949
1950 * configure: Regenerated to track ../common/aclocal.m4 changes.
1951
1952Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1953
1954 * interp.c (sim_open): Set optind to 0 before calling getopt.
1955
1956Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1957
1958 * configure: Regenerated to track ../common/aclocal.m4 changes.
1959
1960Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1961
1962 * interp.c : Replace uses of pr_addr with pr_uword64
1963 where the bit length is always 64 independent of SIM_ADDR.
1964 (pr_uword64) : added.
1965
1966Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1967
1968 * configure: Re-generate.
1969
1970Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1971
1972 * configure: Regenerate to track ../common/aclocal.m4 changes.
1973
1974Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1975
1976 * interp.c (sim_open): New SIM_DESC result. Argument is now
1977 in argv form.
1978 (other sim_*): New SIM_DESC argument.
1979
1980Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1981
1982 * interp.c: Fix printing of addresses for non-64-bit targets.
1983 (pr_addr): Add function to print address based on size.
1984
1985Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1986
1987 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1988
1989Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1990
1991 * gencode.c (build_mips16_operands): Correct computation of base
1992 address for extended PC relative instruction.
1993
1994Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1995
1996 * interp.c (mips16_entry): Add support for floating point cases.
1997 (SignalException): Pass floating point cases to mips16_entry.
1998 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1999 registers.
2000 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2001 or fmt_word.
2002 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2003 and then set the state to fmt_uninterpreted.
2004 (COP_SW): Temporarily set the state to fmt_word while calling
2005 ValueFPR.
2006
2007Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2008
2009 * gencode.c (build_instruction): The high order may be set in the
2010 comparison flags at any ISA level, not just ISA 4.
2011
2012Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2013
2014 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2015 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2016 * configure.in: sinclude ../common/aclocal.m4.
2017 * configure: Regenerated.
2018
2019Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2020
2021 * configure: Rebuild after change to aclocal.m4.
2022
2023Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2024
2025 * configure configure.in Makefile.in: Update to new configure
2026 scheme which is more compatible with WinGDB builds.
2027 * configure.in: Improve comment on how to run autoconf.
2028 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2029 * Makefile.in: Use autoconf substitution to install common
2030 makefile fragment.
2031
2032Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2033
2034 * gencode.c (build_instruction): Use BigEndianCPU instead of
2035 ByteSwapMem.
2036
2037Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2038
2039 * interp.c (sim_monitor): Make output to stdout visible in
2040 wingdb's I/O log window.
2041
2042Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2043
2044 * support.h: Undo previous change to SIGTRAP
2045 and SIGQUIT values.
2046
2047Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2048
2049 * interp.c (store_word, load_word): New static functions.
2050 (mips16_entry): New static function.
2051 (SignalException): Look for mips16 entry and exit instructions.
2052 (simulate): Use the correct index when setting fpr_state after
2053 doing a pending move.
2054
2055Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2056
2057 * interp.c: Fix byte-swapping code throughout to work on
2058 both little- and big-endian hosts.
2059
2060Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2061
2062 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2063 with gdb/config/i386/xm-windows.h.
2064
2065Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2066
2067 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2068 that messes up arithmetic shifts.
2069
2070Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2071
2072 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2073 SIGTRAP and SIGQUIT for _WIN32.
2074
2075Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2076
2077 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2078 force a 64 bit multiplication.
2079 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2080 destination register is 0, since that is the default mips16 nop
2081 instruction.
2082
2083Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2084
2085 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2086 (build_endian_shift): Don't check proc64.
2087 (build_instruction): Always set memval to uword64. Cast op2 to
2088 uword64 when shifting it left in memory instructions. Always use
2089 the same code for stores--don't special case proc64.
2090
2091 * gencode.c (build_mips16_operands): Fix base PC value for PC
2092 relative operands.
2093 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2094 jal instruction.
2095 * interp.c (simJALDELAYSLOT): Define.
2096 (JALDELAYSLOT): Define.
2097 (INDELAYSLOT, INJALDELAYSLOT): Define.
2098 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2099
2100Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2101
2102 * interp.c (sim_open): add flush_cache as a PMON routine
2103 (sim_monitor): handle flush_cache by ignoring it
2104
2105Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2106
2107 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2108 BigEndianMem.
2109 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2110 (BigEndianMem): Rename to ByteSwapMem and change sense.
2111 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2112 BigEndianMem references to !ByteSwapMem.
2113 (set_endianness): New function, with prototype.
2114 (sim_open): Call set_endianness.
2115 (sim_info): Use simBE instead of BigEndianMem.
2116 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2117 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2118 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2119 ifdefs, keeping the prototype declaration.
2120 (swap_word): Rewrite correctly.
2121 (ColdReset): Delete references to CONFIG. Delete endianness related
2122 code; moved to set_endianness.
2123
2124Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2125
2126 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2127 * interp.c (CHECKHILO): Define away.
2128 (simSIGINT): New macro.
2129 (membank_size): Increase from 1MB to 2MB.
2130 (control_c): New function.
2131 (sim_resume): Rename parameter signal to signal_number. Add local
2132 variable prev. Call signal before and after simulate.
2133 (sim_stop_reason): Add simSIGINT support.
2134 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2135 functions always.
2136 (sim_warning): Delete call to SignalException. Do call printf_filtered
2137 if logfh is NULL.
2138 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2139 a call to sim_warning.
2140
2141Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2142
2143 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2144 16 bit instructions.
2145
2146Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2147
2148 Add support for mips16 (16 bit MIPS implementation):
2149 * gencode.c (inst_type): Add mips16 instruction encoding types.
2150 (GETDATASIZEINSN): Define.
2151 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2152 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2153 mtlo.
2154 (MIPS16_DECODE): New table, for mips16 instructions.
2155 (bitmap_val): New static function.
2156 (struct mips16_op): Define.
2157 (mips16_op_table): New table, for mips16 operands.
2158 (build_mips16_operands): New static function.
2159 (process_instructions): If PC is odd, decode a mips16
2160 instruction. Break out instruction handling into new
2161 build_instruction function.
2162 (build_instruction): New static function, broken out of
2163 process_instructions. Check modifiers rather than flags for SHIFT
2164 bit count and m[ft]{hi,lo} direction.
2165 (usage): Pass program name to fprintf.
2166 (main): Remove unused variable this_option_optind. Change
2167 ``*loptarg++'' to ``loptarg++''.
2168 (my_strtoul): Parenthesize && within ||.
2169 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2170 (simulate): If PC is odd, fetch a 16 bit instruction, and
2171 increment PC by 2 rather than 4.
2172 * configure.in: Add case for mips16*-*-*.
2173 * configure: Rebuild.
2174
2175Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2176
2177 * interp.c: Allow -t to enable tracing in standalone simulator.
2178 Fix garbage output in trace file and error messages.
2179
2180Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2181
2182 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2183 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2184 * configure.in: Simplify using macros in ../common/aclocal.m4.
2185 * configure: Regenerated.
2186 * tconfig.in: New file.
2187
2188Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2189
2190 * interp.c: Fix bugs in 64-bit port.
2191 Use ansi function declarations for msvc compiler.
2192 Initialize and test file pointer in trace code.
2193 Prevent duplicate definition of LAST_EMED_REGNUM.
2194
2195Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2196
2197 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2198
2199Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2200
2201 * interp.c (SignalException): Check for explicit terminating
2202 breakpoint value.
2203 * gencode.c: Pass instruction value through SignalException()
2204 calls for Trap, Breakpoint and Syscall.
2205
2206Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2207
2208 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2209 only used on those hosts that provide it.
2210 * configure.in: Add sqrt() to list of functions to be checked for.
2211 * config.in: Re-generated.
2212 * configure: Re-generated.
2213
2214Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2215
2216 * gencode.c (process_instructions): Call build_endian_shift when
2217 expanding STORE RIGHT, to fix swr.
2218 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2219 clear the high bits.
2220 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2221 Fix float to int conversions to produce signed values.
2222
2223Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2224
2225 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2226 (process_instructions): Correct handling of nor instruction.
2227 Correct shift count for 32 bit shift instructions. Correct sign
2228 extension for arithmetic shifts to not shift the number of bits in
2229 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2230 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2231 Fix madd.
2232 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2233 It's OK to have a mult follow a mult. What's not OK is to have a
2234 mult follow an mfhi.
2235 (Convert): Comment out incorrect rounding code.
2236
2237Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2238
2239 * interp.c (sim_monitor): Improved monitor printf
2240 simulation. Tidied up simulator warnings, and added "--log" option
2241 for directing warning message output.
2242 * gencode.c: Use sim_warning() rather than WARNING macro.
2243
2244Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2245
2246 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2247 getopt1.o, rather than on gencode.c. Link objects together.
2248 Don't link against -liberty.
2249 (gencode.o, getopt.o, getopt1.o): New targets.
2250 * gencode.c: Include <ctype.h> and "ansidecl.h".
2251 (AND): Undefine after including "ansidecl.h".
2252 (ULONG_MAX): Define if not defined.
2253 (OP_*): Don't define macros; now defined in opcode/mips.h.
2254 (main): Call my_strtoul rather than strtoul.
2255 (my_strtoul): New static function.
2256
2257Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2258
2259 * gencode.c (process_instructions): Generate word64 and uword64
2260 instead of `long long' and `unsigned long long' data types.
2261 * interp.c: #include sysdep.h to get signals, and define default
2262 for SIGBUS.
2263 * (Convert): Work around for Visual-C++ compiler bug with type
2264 conversion.
2265 * support.h: Make things compile under Visual-C++ by using
2266 __int64 instead of `long long'. Change many refs to long long
2267 into word64/uword64 typedefs.
2268
2269Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2270
2271 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2272 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2273 (docdir): Removed.
2274 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2275 (AC_PROG_INSTALL): Added.
2276 (AC_PROG_CC): Moved to before configure.host call.
2277 * configure: Rebuilt.
2278
2279Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2280
2281 * configure.in: Define @SIMCONF@ depending on mips target.
2282 * configure: Rebuild.
2283 * Makefile.in (run): Add @SIMCONF@ to control simulator
2284 construction.
2285 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2286 * interp.c: Remove some debugging, provide more detailed error
2287 messages, update memory accesses to use LOADDRMASK.
2288
2289Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2290
2291 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2292 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2293 stamp-h.
2294 * configure: Rebuild.
2295 * config.in: New file, generated by autoheader.
2296 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2297 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2298 HAVE_ANINT and HAVE_AINT, as appropriate.
2299 * Makefile.in (run): Use @LIBS@ rather than -lm.
2300 (interp.o): Depend upon config.h.
2301 (Makefile): Just rebuild Makefile.
2302 (clean): Remove stamp-h.
2303 (mostlyclean): Make the same as clean, not as distclean.
2304 (config.h, stamp-h): New targets.
2305
2306Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2307
2308 * interp.c (ColdReset): Fix boolean test. Make all simulator
2309 globals static.
2310
2311Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2312
2313 * interp.c (xfer_direct_word, xfer_direct_long,
2314 swap_direct_word, swap_direct_long, xfer_big_word,
2315 xfer_big_long, xfer_little_word, xfer_little_long,
2316 swap_word,swap_long): Added.
2317 * interp.c (ColdReset): Provide function indirection to
2318 host<->simulated_target transfer routines.
2319 * interp.c (sim_store_register, sim_fetch_register): Updated to
2320 make use of indirected transfer routines.
2321
2322Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2323
2324 * gencode.c (process_instructions): Ensure FP ABS instruction
2325 recognised.
2326 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2327 system call support.
2328
2329Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2330
2331 * interp.c (sim_do_command): Complain if callback structure not
2332 initialised.
2333
2334Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2335
2336 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2337 support for Sun hosts.
2338 * Makefile.in (gencode): Ensure the host compiler and libraries
2339 used for cross-hosted build.
2340
2341Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2342
2343 * interp.c, gencode.c: Some more (TODO) tidying.
2344
2345Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2346
2347 * gencode.c, interp.c: Replaced explicit long long references with
2348 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2349 * support.h (SET64LO, SET64HI): Macros added.
2350
2351Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2352
2353 * configure: Regenerate with autoconf 2.7.
2354
2355Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2356
2357 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2358 * support.h: Remove superfluous "1" from #if.
2359 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2360
2361Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2362
2363 * interp.c (StoreFPR): Control UndefinedResult() call on
2364 WARN_RESULT manifest.
2365
2366Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2367
2368 * gencode.c: Tidied instruction decoding, and added FP instruction
2369 support.
2370
2371 * interp.c: Added dineroIII, and BSD profiling support. Also
2372 run-time FP handling.
2373
2374Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2375
2376 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2377 gencode.c, interp.c, support.h: created.
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