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x86/kvm/vmx: do not use vm-exit instruction length for fast MMIO when running nested
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
9ed96e87
MT		 110unsigned int min_timer_period_us = 500;
111module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
112
630994b3
MT		 113static bool __read_mostly kvmclock_periodic_sync = true;
114module_param(kvmclock_periodic_sync, bool, S_IRUGO);
115
893590c7 116bool __read_mostly kvm_has_tsc_control;
92a1f12d 117EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 118u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 119EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 120u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
121EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
122u64 __read_mostly kvm_max_tsc_scaling_ratio;
123EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 124u64 __read_mostly kvm_default_tsc_scaling_ratio;
125EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 126
cc578287 127/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 128static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 129module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
130
d0659d94 131/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 132unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 133module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
134
52004014
FW		 135static bool __read_mostly vector_hashing = true;
136module_param(vector_hashing, bool, S_IRUGO);
137
18863bdd
AK		 138#define KVM_NR_SHARED_MSRS 16
139
140struct kvm_shared_msrs_global {
141 int nr;
2bf78fa7 142 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 143};
144
145struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
2bf78fa7
SY		 148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 152};
153
154static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 155static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 156
417bc304 157struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 168 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 173 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 181 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 182 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 183 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 184 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
185 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
186 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
187 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
188 { "mmu_flooded", VM_STAT(mmu_flooded) },
189 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 190 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 191 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 192 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 193 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 194 { "max_mmu_page_hash_collisions",
195 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 196 { NULL }
197};
198
2acf923e
DC		 199u64 __read_mostly host_xcr0;
200
b6785def 201static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 202
af585b92
GN		 203static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
204{
205 int i;
206 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
207 vcpu->arch.apf.gfns[i] = ~0;
208}
209
18863bdd
AK		 210static void kvm_on_user_return(struct user_return_notifier *urn)
211{
212 unsigned slot;
18863bdd
AK		 213 struct kvm_shared_msrs *locals
214 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 215 struct kvm_shared_msr_values *values;
1650b4eb
IA		 216 unsigned long flags;
217
218 /*
219 * Disabling irqs at this point since the following code could be
220 * interrupted and executed through kvm_arch_hardware_disable()
221 */
222 local_irq_save(flags);
223 if (locals->registered) {
224 locals->registered = false;
225 user_return_notifier_unregister(urn);
226 }
227 local_irq_restore(flags);
18863bdd 228 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 229 values = &locals->values[slot];
230 if (values->host != values->curr) {
231 wrmsrl(shared_msrs_global.msrs[slot], values->host);
232 values->curr = values->host;
18863bdd
AK		 233 }
234 }
18863bdd
AK		 235}
236
2bf78fa7 237static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 238{
18863bdd 239 u64 value;
013f6a5d
MT		 240 unsigned int cpu = smp_processor_id();
241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 242
2bf78fa7
SY		 243 /* only read, and nobody should modify it at this time,
244 * so don't need lock */
245 if (slot >= shared_msrs_global.nr) {
246 printk(KERN_ERR "kvm: invalid MSR slot!");
247 return;
248 }
249 rdmsrl_safe(msr, &value);
250 smsr->values[slot].host = value;
251 smsr->values[slot].curr = value;
252}
253
254void kvm_define_shared_msr(unsigned slot, u32 msr)
255{
0123be42 256 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 257 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 258 if (slot >= shared_msrs_global.nr)
259 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 260}
261EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
262
263static void kvm_shared_msr_cpu_online(void)
264{
265 unsigned i;
18863bdd
AK		 266
267 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 268 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 269}
270
8b3c3104 271int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 272{
013f6a5d
MT		 273 unsigned int cpu = smp_processor_id();
274 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 275 int err;
18863bdd 276
2bf78fa7 277 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 278 return 0;
2bf78fa7 279 smsr->values[slot].curr = value;
8b3c3104
AH		 280 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
281 if (err)
282 return 1;
283
18863bdd
AK		 284 if (!smsr->registered) {
285 smsr->urn.on_user_return = kvm_on_user_return;
286 user_return_notifier_register(&smsr->urn);
287 smsr->registered = true;
288 }
8b3c3104 289 return 0;
18863bdd
AK		 290}
291EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
292
13a34e06 293static void drop_user_return_notifiers(void)
3548bab5 294{
013f6a5d
MT		 295 unsigned int cpu = smp_processor_id();
296 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 297
298 if (smsr->registered)
299 kvm_on_user_return(&smsr->urn);
300}
301
6866b83e
CO		 302u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
303{
8a5a87d9 304 return vcpu->arch.apic_base;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_get_apic_base);
307
58cb628d
JK		 308int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
309{
310 u64 old_state = vcpu->arch.apic_base &
311 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
312 u64 new_state = msr_info->data &
313 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 314 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
315 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 316
d3802286
JM		 317 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
318 return 1;
58cb628d 319 if (!msr_info->host_initiated &&
d3802286 320 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 321 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
322 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
323 old_state == 0)))
324 return 1;
325
326 kvm_lapic_set_base(vcpu, msr_info->data);
327 return 0;
6866b83e
CO		 328}
329EXPORT_SYMBOL_GPL(kvm_set_apic_base);
330
2605fc21 331asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 332{
333 /* Fault while not rebooting. We want the trace. */
334 BUG();
335}
336EXPORT_SYMBOL_GPL(kvm_spurious_fault);
337
3fd28fce
ED		 338#define EXCPT_BENIGN 0
339#define EXCPT_CONTRIBUTORY 1
340#define EXCPT_PF 2
341
342static int exception_class(int vector)
343{
344 switch (vector) {
345 case PF_VECTOR:
346 return EXCPT_PF;
347 case DE_VECTOR:
348 case TS_VECTOR:
349 case NP_VECTOR:
350 case SS_VECTOR:
351 case GP_VECTOR:
352 return EXCPT_CONTRIBUTORY;
353 default:
354 break;
355 }
356 return EXCPT_BENIGN;
357}
358
d6e8c854
NA		 359#define EXCPT_FAULT 0
360#define EXCPT_TRAP 1
361#define EXCPT_ABORT 2
362#define EXCPT_INTERRUPT 3
363
364static int exception_type(int vector)
365{
366 unsigned int mask;
367
368 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
369 return EXCPT_INTERRUPT;
370
371 mask = 1 << vector;
372
373 /* #DB is trap, as instruction watchpoints are handled elsewhere */
374 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
375 return EXCPT_TRAP;
376
377 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
378 return EXCPT_ABORT;
379
380 /* Reserved exceptions will result in fault */
381 return EXCPT_FAULT;
382}
383
3fd28fce 384static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 385 unsigned nr, bool has_error, u32 error_code,
386 bool reinject)
3fd28fce
ED		 387{
388 u32 prev_nr;
389 int class1, class2;
390
3842d135
AK		 391 kvm_make_request(KVM_REQ_EVENT, vcpu);
392
664f8e26 393 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 394 queue:
3ffb2468
NA		 395 if (has_error && !is_protmode(vcpu))
396 has_error = false;
664f8e26
WL		 397 if (reinject) {
398 /*
399 * On vmentry, vcpu->arch.exception.pending is only
400 * true if an event injection was blocked by
401 * nested_run_pending. In that case, however,
402 * vcpu_enter_guest requests an immediate exit,
403 * and the guest shouldn't proceed far enough to
404 * need reinjection.
405 */
406 WARN_ON_ONCE(vcpu->arch.exception.pending);
407 vcpu->arch.exception.injected = true;
408 } else {
409 vcpu->arch.exception.pending = true;
410 vcpu->arch.exception.injected = false;
411 }
3fd28fce
ED		 412 vcpu->arch.exception.has_error_code = has_error;
413 vcpu->arch.exception.nr = nr;
414 vcpu->arch.exception.error_code = error_code;
415 return;
416 }
417
418 /* to check exception */
419 prev_nr = vcpu->arch.exception.nr;
420 if (prev_nr == DF_VECTOR) {
421 /* triple fault -> shutdown */
a8eeb04a 422 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 423 return;
424 }
425 class1 = exception_class(prev_nr);
426 class2 = exception_class(nr);
427 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
428 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 429 /*
430 * Generate double fault per SDM Table 5-5. Set
431 * exception.pending = true so that the double fault
432 * can trigger a nested vmexit.
433 */
3fd28fce 434 vcpu->arch.exception.pending = true;
664f8e26 435 vcpu->arch.exception.injected = false;
3fd28fce
ED		 436 vcpu->arch.exception.has_error_code = true;
437 vcpu->arch.exception.nr = DF_VECTOR;
438 vcpu->arch.exception.error_code = 0;
439 } else
440 /* replace previous exception with a new one in a hope
441 that instruction re-execution will regenerate lost
442 exception */
443 goto queue;
444}
445
298101da
AK		 446void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
447{
ce7ddec4 448 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 449}
450EXPORT_SYMBOL_GPL(kvm_queue_exception);
451
ce7ddec4
JR		 452void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
453{
454 kvm_multiple_exception(vcpu, nr, false, 0, true);
455}
456EXPORT_SYMBOL_GPL(kvm_requeue_exception);
457
6affcbed 458int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 459{
db8fcefa
AP		 460 if (err)
461 kvm_inject_gp(vcpu, 0);
462 else
6affcbed
KH		 463 return kvm_skip_emulated_instruction(vcpu);
464
465 return 1;
db8fcefa
AP		 466}
467EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 468
6389ee94 469void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 470{
471 ++vcpu->stat.pf_guest;
adfe20fb
WL		 472 vcpu->arch.exception.nested_apf =
473 is_guest_mode(vcpu) && fault->async_page_fault;
474 if (vcpu->arch.exception.nested_apf)
475 vcpu->arch.apf.nested_apf_token = fault->address;
476 else
477 vcpu->arch.cr2 = fault->address;
6389ee94 478 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 479}
27d6c865 480EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 481
ef54bcfe 482static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 483{
6389ee94
AK		 484 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
485 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 486 else
6389ee94 487 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 488
489 return fault->nested_page_fault;
d4f8cf66
JR		 490}
491
3419ffc8
SY		 492void kvm_inject_nmi(struct kvm_vcpu *vcpu)
493{
7460fb4a
AK		 494 atomic_inc(&vcpu->arch.nmi_queued);
495 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 496}
497EXPORT_SYMBOL_GPL(kvm_inject_nmi);
498
298101da
AK		 499void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
500{
ce7ddec4 501 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 502}
503EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
504
ce7ddec4
JR		 505void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
506{
507 kvm_multiple_exception(vcpu, nr, true, error_code, true);
508}
509EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
510
0a79b009
AK		 511/*
512 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
513 * a #GP and return false.
514 */
515bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 516{
0a79b009
AK		 517 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
518 return true;
519 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
520 return false;
298101da 521}
0a79b009 522EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 523
16f8a6f9
NA		 524bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
525{
526 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
527 return true;
528
529 kvm_queue_exception(vcpu, UD_VECTOR);
530 return false;
531}
532EXPORT_SYMBOL_GPL(kvm_require_dr);
533
ec92fe44
JR		 534/*
535 * This function will be used to read from the physical memory of the currently
54bf36aa 536 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 537 * can read from guest physical or from the guest's guest physical memory.
538 */
539int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
540 gfn_t ngfn, void *data, int offset, int len,
541 u32 access)
542{
54987b7a 543 struct x86_exception exception;
ec92fe44
JR		 544 gfn_t real_gfn;
545 gpa_t ngpa;
546
547 ngpa = gfn_to_gpa(ngfn);
54987b7a 548 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 549 if (real_gfn == UNMAPPED_GVA)
550 return -EFAULT;
551
552 real_gfn = gpa_to_gfn(real_gfn);
553
54bf36aa 554 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 555}
556EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
557
69b0049a 558static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 559 void *data, int offset, int len, u32 access)
560{
561 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
562 data, offset, len, access);
563}
564
a03490ed
CO		 565/*
566 * Load the pae pdptrs. Return true is they are all valid.
567 */
ff03a073 568int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 569{
570 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
571 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
572 int i;
573 int ret;
ff03a073 574 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 575
ff03a073
JR		 576 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
577 offset * sizeof(u64), sizeof(pdpte),
578 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 579 if (ret < 0) {
580 ret = 0;
581 goto out;
582 }
583 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 584 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 585 (pdpte[i] &
586 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 587 ret = 0;
588 goto out;
589 }
590 }
591 ret = 1;
592
ff03a073 593 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 594 __set_bit(VCPU_EXREG_PDPTR,
595 (unsigned long *)&vcpu->arch.regs_avail);
596 __set_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 598out:
a03490ed
CO		 599
600 return ret;
601}
cc4b6871 602EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 603
9ed38ffa 604bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 605{
ff03a073 606 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 607 bool changed = true;
3d06b8bf
JR		 608 int offset;
609 gfn_t gfn;
d835dfec
AK		 610 int r;
611
612 if (is_long_mode(vcpu) || !is_pae(vcpu))
613 return false;
614
6de4f3ad
AK		 615 if (!test_bit(VCPU_EXREG_PDPTR,
616 (unsigned long *)&vcpu->arch.regs_avail))
617 return true;
618
a512177e
PB		 619 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
620 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 621 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
622 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 623 if (r < 0)
624 goto out;
ff03a073 625 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 626out:
d835dfec
AK		 627
628 return changed;
629}
9ed38ffa 630EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 631
49a9b07e 632int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 633{
aad82703 634 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 635 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 636
f9a48e6a
AK		 637 cr0 |= X86_CR0_ET;
638
ab344828 639#ifdef CONFIG_X86_64
0f12244f
GN		 640 if (cr0 & 0xffffffff00000000UL)
641 return 1;
ab344828
GN		 642#endif
643
644 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 645
0f12244f
GN		 646 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
647 return 1;
a03490ed 648
0f12244f
GN		 649 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
650 return 1;
a03490ed
CO		 651
652 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
653#ifdef CONFIG_X86_64
f6801dff 654 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 655 int cs_db, cs_l;
656
0f12244f
GN		 657 if (!is_pae(vcpu))
658 return 1;
a03490ed 659 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 660 if (cs_l)
661 return 1;
a03490ed
CO		 662 } else
663#endif
ff03a073 664 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 665 kvm_read_cr3(vcpu)))
0f12244f 666 return 1;
a03490ed
CO		 667 }
668
ad756a16
MJ		 669 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
670 return 1;
671
a03490ed 672 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 673
d170c419 674 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 675 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 676 kvm_async_pf_hash_reset(vcpu);
677 }
e5f3f027 678
aad82703
SY		 679 if ((cr0 ^ old_cr0) & update_bits)
680 kvm_mmu_reset_context(vcpu);
b18d5431 681
879ae188
LE		 682 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
683 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
684 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 685 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
686
0f12244f
GN		 687 return 0;
688}
2d3ad1f4 689EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 690
2d3ad1f4 691void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 692{
49a9b07e 693 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 696
42bdf991
MT		 697static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
698{
699 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
700 !vcpu->guest_xcr0_loaded) {
701 /* kvm_set_xcr() also depends on this */
702 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
703 vcpu->guest_xcr0_loaded = 1;
704 }
705}
706
707static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
708{
709 if (vcpu->guest_xcr0_loaded) {
710 if (vcpu->arch.xcr0 != host_xcr0)
711 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
712 vcpu->guest_xcr0_loaded = 0;
713 }
714}
715
69b0049a 716static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 717{
56c103ec
LJ		 718 u64 xcr0 = xcr;
719 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 720 u64 valid_bits;
2acf923e
DC		 721
722 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
723 if (index != XCR_XFEATURE_ENABLED_MASK)
724 return 1;
d91cab78 725 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 726 return 1;
d91cab78 727 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 728 return 1;
46c34cb0
PB		 729
730 /*
731 * Do not allow the guest to set bits that we do not support
732 * saving. However, xcr0 bit 0 is always set, even if the
733 * emulated CPU does not support XSAVE (see fx_init).
734 */
d91cab78 735 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 736 if (xcr0 & ~valid_bits)
2acf923e 737 return 1;
46c34cb0 738
d91cab78
DH		 739 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
740 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 741 return 1;
742
d91cab78
DH		 743 if (xcr0 & XFEATURE_MASK_AVX512) {
744 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 745 return 1;
d91cab78 746 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 747 return 1;
748 }
2acf923e 749 vcpu->arch.xcr0 = xcr0;
56c103ec 750
d91cab78 751 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 752 kvm_update_cpuid(vcpu);
2acf923e
DC		 753 return 0;
754}
755
756int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
757{
764bcbc5
Z		 758 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
759 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 760 kvm_inject_gp(vcpu, 0);
761 return 1;
762 }
763 return 0;
764}
765EXPORT_SYMBOL_GPL(kvm_set_xcr);
766
a83b29c6 767int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 768{
fc78f519 769 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 770 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 771 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 772
0f12244f
GN		 773 if (cr4 & CR4_RESERVED_BITS)
774 return 1;
a03490ed 775
d6321d49 776 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 777 return 1;
778
d6321d49 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 780 return 1;
781
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 783 return 1;
784
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 786 return 1;
787
d6321d49 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 789 return 1;
790
fd8cb433 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 792 return 1;
793
a03490ed 794 if (is_long_mode(vcpu)) {
0f12244f
GN		 795 if (!(cr4 & X86_CR4_PAE))
796 return 1;
a2edf57f
AK		 797 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
798 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 799 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
800 kvm_read_cr3(vcpu)))
0f12244f
GN		 801 return 1;
802
ad756a16 803 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 804 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 805 return 1;
806
807 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
808 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
809 return 1;
810 }
811
5e1746d6 812 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 813 return 1;
a03490ed 814
ad756a16
MJ		 815 if (((cr4 ^ old_cr4) & pdptr_bits) ||
816 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 817 kvm_mmu_reset_context(vcpu);
0f12244f 818
b9baba86 819 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 820 kvm_update_cpuid(vcpu);
2acf923e 821
0f12244f
GN		 822 return 0;
823}
2d3ad1f4 824EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 825
2390218b 826int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 827{
ac146235 828#ifdef CONFIG_X86_64
9d88fca7 829 cr3 &= ~CR3_PCID_INVD;
ac146235 830#endif
9d88fca7 831
9f8fe504 832 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 833 kvm_mmu_sync_roots(vcpu);
77c3913b 834 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 835 return 0;
d835dfec
AK		 836 }
837
d1cd3ce9
YZ		 838 if (is_long_mode(vcpu) &&
839 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
840 return 1;
841 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 842 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 843 return 1;
a03490ed 844
0f12244f 845 vcpu->arch.cr3 = cr3;
aff48baa 846 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 847 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 848 return 0;
849}
2d3ad1f4 850EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 851
eea1cff9 852int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 853{
0f12244f
GN		 854 if (cr8 & CR8_RESERVED_BITS)
855 return 1;
35754c98 856 if (lapic_in_kernel(vcpu))
a03490ed
CO		 857 kvm_lapic_set_tpr(vcpu, cr8);
858 else
ad312c7c 859 vcpu->arch.cr8 = cr8;
0f12244f
GN		 860 return 0;
861}
2d3ad1f4 862EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 863
2d3ad1f4 864unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 865{
35754c98 866 if (lapic_in_kernel(vcpu))
a03490ed
CO		 867 return kvm_lapic_get_cr8(vcpu);
868 else
ad312c7c 869 return vcpu->arch.cr8;
a03490ed 870}
2d3ad1f4 871EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 872
ae561ede
NA		 873static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
874{
875 int i;
876
877 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
878 for (i = 0; i < KVM_NR_DB_REGS; i++)
879 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
880 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
881 }
882}
883
73aaf249
JK		 884static void kvm_update_dr6(struct kvm_vcpu *vcpu)
885{
886 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
887 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
888}
889
c8639010
JK		 890static void kvm_update_dr7(struct kvm_vcpu *vcpu)
891{
892 unsigned long dr7;
893
894 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
895 dr7 = vcpu->arch.guest_debug_dr7;
896 else
897 dr7 = vcpu->arch.dr7;
898 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 899 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
900 if (dr7 & DR7_BP_EN_MASK)
901 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 902}
903
6f43ed01
NA		 904static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
905{
906 u64 fixed = DR6_FIXED_1;
907
d6321d49 908 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 909 fixed |= DR6_RTM;
910 return fixed;
911}
912
338dbc97 913static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 914{
915 switch (dr) {
916 case 0 ... 3:
917 vcpu->arch.db[dr] = val;
918 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
919 vcpu->arch.eff_db[dr] = val;
920 break;
921 case 4:
020df079
GN		 922 /* fall through */
923 case 6:
338dbc97
GN		 924 if (val & 0xffffffff00000000ULL)
925 return -1; /* #GP */
6f43ed01 926 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 927 kvm_update_dr6(vcpu);
020df079
GN		 928 break;
929 case 5:
020df079
GN		 930 /* fall through */
931 default: /* 7 */
338dbc97
GN		 932 if (val & 0xffffffff00000000ULL)
933 return -1; /* #GP */
020df079 934 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 935 kvm_update_dr7(vcpu);
020df079
GN		 936 break;
937 }
938
939 return 0;
940}
338dbc97
GN		 941
942int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
943{
16f8a6f9 944 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 945 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 946 return 1;
947 }
948 return 0;
338dbc97 949}
020df079
GN		 950EXPORT_SYMBOL_GPL(kvm_set_dr);
951
16f8a6f9 952int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 953{
954 switch (dr) {
955 case 0 ... 3:
956 *val = vcpu->arch.db[dr];
957 break;
958 case 4:
020df079
GN		 959 /* fall through */
960 case 6:
73aaf249
JK		 961 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
962 *val = vcpu->arch.dr6;
963 else
964 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 965 break;
966 case 5:
020df079
GN		 967 /* fall through */
968 default: /* 7 */
969 *val = vcpu->arch.dr7;
970 break;
971 }
338dbc97
GN		 972 return 0;
973}
020df079
GN		 974EXPORT_SYMBOL_GPL(kvm_get_dr);
975
022cd0e8
AK		 976bool kvm_rdpmc(struct kvm_vcpu *vcpu)
977{
978 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
979 u64 data;
980 int err;
981
c6702c9d 982 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 983 if (err)
984 return err;
985 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
986 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
987 return err;
988}
989EXPORT_SYMBOL_GPL(kvm_rdpmc);
990
043405e1
CO		 991/*
992 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
993 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
994 *
995 * This list is modified at module load time to reflect the
e3267cbb 996 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 997 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
998 * may depend on host virtualization features rather than host cpu features.
043405e1 999 */
e3267cbb 1000
043405e1
CO		 1001static u32 msrs_to_save[] = {
1002 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1003 MSR_STAR,
043405e1
CO		 1004#ifdef CONFIG_X86_64
1005 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1006#endif
b3897a49 1007 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1008 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
4a82531c 1009 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1010};
1011
1012static unsigned num_msrs_to_save;
1013
62ef68bb
PB		 1014static u32 emulated_msrs[] = {
1015 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1016 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1017 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1018 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1019 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1020 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1021 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1022 HV_X64_MSR_RESET,
11c4b1ca 1023 HV_X64_MSR_VP_INDEX,
9eec50b8 1024 HV_X64_MSR_VP_RUNTIME,
5c919412 1025 HV_X64_MSR_SCONTROL,
1f4b34f8 1026 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1027 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1028 MSR_KVM_PV_EOI_EN,
1029
ba904635 1030 MSR_IA32_TSC_ADJUST,
a3e06bbe 1031 MSR_IA32_TSCDEADLINE,
043405e1 1032 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1033 MSR_IA32_MCG_STATUS,
1034 MSR_IA32_MCG_CTL,
c45dcc71 1035 MSR_IA32_MCG_EXT_CTL,
64d60670 1036 MSR_IA32_SMBASE,
db2336a8
KH		 1037 MSR_PLATFORM_INFO,
1038 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1039};
1040
62ef68bb
PB		 1041static unsigned num_emulated_msrs;
1042
384bb783 1043bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1044{
b69e8cae 1045 if (efer & efer_reserved_bits)
384bb783 1046 return false;
15c4a640 1047
1b4d56b8 1048 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1049 return false;
1b2fd70c 1050
1b4d56b8 1051 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1052 return false;
d8017474 1053
384bb783
JK		 1054 return true;
1055}
1056EXPORT_SYMBOL_GPL(kvm_valid_efer);
1057
1058static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1059{
1060 u64 old_efer = vcpu->arch.efer;
1061
1062 if (!kvm_valid_efer(vcpu, efer))
1063 return 1;
1064
1065 if (is_paging(vcpu)
1066 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1067 return 1;
1068
15c4a640 1069 efer &= ~EFER_LMA;
f6801dff 1070 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1071
a3d204e2
SY		 1072 kvm_x86_ops->set_efer(vcpu, efer);
1073
aad82703
SY		 1074 /* Update reserved bits */
1075 if ((efer ^ old_efer) & EFER_NX)
1076 kvm_mmu_reset_context(vcpu);
1077
b69e8cae 1078 return 0;
15c4a640
CO		 1079}
1080
f2b4b7dd
JR		 1081void kvm_enable_efer_bits(u64 mask)
1082{
1083 efer_reserved_bits &= ~mask;
1084}
1085EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1086
15c4a640
CO		 1087/*
1088 * Writes msr value into into the appropriate "register".
1089 * Returns 0 on success, non-0 otherwise.
1090 * Assumes vcpu_load() was already called.
1091 */
8fe8ab46 1092int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1093{
854e8bb1
NA		 1094 switch (msr->index) {
1095 case MSR_FS_BASE:
1096 case MSR_GS_BASE:
1097 case MSR_KERNEL_GS_BASE:
1098 case MSR_CSTAR:
1099 case MSR_LSTAR:
fd8cb433 1100 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1101 return 1;
1102 break;
1103 case MSR_IA32_SYSENTER_EIP:
1104 case MSR_IA32_SYSENTER_ESP:
1105 /*
1106 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1107 * non-canonical address is written on Intel but not on
1108 * AMD (which ignores the top 32-bits, because it does
1109 * not implement 64-bit SYSENTER).
1110 *
1111 * 64-bit code should hence be able to write a non-canonical
1112 * value on AMD. Making the address canonical ensures that
1113 * vmentry does not fail on Intel after writing a non-canonical
1114 * value, and that something deterministic happens if the guest
1115 * invokes 64-bit SYSENTER.
1116 */
fd8cb433 1117 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1118 }
8fe8ab46 1119 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1120}
854e8bb1 1121EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1122
313a3dc7
CO		 1123/*
1124 * Adapt set_msr() to msr_io()'s calling convention
1125 */
609e36d3
PB		 1126static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1127{
1128 struct msr_data msr;
1129 int r;
1130
1131 msr.index = index;
1132 msr.host_initiated = true;
1133 r = kvm_get_msr(vcpu, &msr);
1134 if (r)
1135 return r;
1136
1137 *data = msr.data;
1138 return 0;
1139}
1140
313a3dc7
CO		 1141static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1142{
8fe8ab46
WA		 1143 struct msr_data msr;
1144
1145 msr.data = *data;
1146 msr.index = index;
1147 msr.host_initiated = true;
1148 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1149}
1150
16e8d74d
MT		 1151#ifdef CONFIG_X86_64
1152struct pvclock_gtod_data {
1153 seqcount_t seq;
1154
1155 struct { /* extract of a clocksource struct */
1156 int vclock_mode;
a5a1d1c2
TG		 1157 u64 cycle_last;
1158 u64 mask;
16e8d74d
MT		 1159 u32 mult;
1160 u32 shift;
1161 } clock;
1162
cbcf2dd3
TG		 1163 u64 boot_ns;
1164 u64 nsec_base;
55dd00a7 1165 u64 wall_time_sec;
16e8d74d
MT		 1166};
1167
1168static struct pvclock_gtod_data pvclock_gtod_data;
1169
1170static void update_pvclock_gtod(struct timekeeper *tk)
1171{
1172 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1173 u64 boot_ns;
1174
876e7881 1175 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1176
1177 write_seqcount_begin(&vdata->seq);
1178
1179 /* copy pvclock gtod data */
876e7881
PZ		 1180 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1181 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1182 vdata->clock.mask = tk->tkr_mono.mask;
1183 vdata->clock.mult = tk->tkr_mono.mult;
1184 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1185
cbcf2dd3 1186 vdata->boot_ns = boot_ns;
876e7881 1187 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1188
55dd00a7
MT		 1189 vdata->wall_time_sec = tk->xtime_sec;
1190
16e8d74d
MT		 1191 write_seqcount_end(&vdata->seq);
1192}
1193#endif
1194
bab5bb39
NK		 1195void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1196{
1197 /*
1198 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1199 * vcpu_enter_guest. This function is only called from
1200 * the physical CPU that is running vcpu.
1201 */
1202 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1203}
16e8d74d 1204
18068523
GOC		 1205static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1206{
9ed3c444
AK		 1207 int version;
1208 int r;
50d0a0f9 1209 struct pvclock_wall_clock wc;
87aeb54f 1210 struct timespec64 boot;
18068523
GOC		 1211
1212 if (!wall_clock)
1213 return;
1214
9ed3c444
AK		 1215 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1216 if (r)
1217 return;
1218
1219 if (version & 1)
1220 ++version; /* first time write, random junk */
1221
1222 ++version;
18068523 1223
1dab1345
NK		 1224 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1225 return;
18068523 1226
50d0a0f9
GH		 1227 /*
1228 * The guest calculates current wall clock time by adding
34c238a1 1229 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1230 * wall clock specified here. guest system time equals host
1231 * system time for us, thus we must fill in host boot time here.
1232 */
87aeb54f 1233 getboottime64(&boot);
50d0a0f9 1234
4b648665 1235 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1236 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1237 boot = timespec64_sub(boot, ts);
4b648665 1238 }
87aeb54f 1239 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1240 wc.nsec = boot.tv_nsec;
1241 wc.version = version;
18068523
GOC		 1242
1243 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1244
1245 version++;
1246 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1247}
1248
50d0a0f9
GH		 1249static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1250{
b51012de
PB		 1251 do_shl32_div32(dividend, divisor);
1252 return dividend;
50d0a0f9
GH		 1253}
1254
3ae13faa 1255static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1256 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1257{
5f4e3f88 1258 uint64_t scaled64;
50d0a0f9
GH		 1259 int32_t shift = 0;
1260 uint64_t tps64;
1261 uint32_t tps32;
1262
3ae13faa
PB		 1263 tps64 = base_hz;
1264 scaled64 = scaled_hz;
50933623 1265 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1266 tps64 >>= 1;
1267 shift--;
1268 }
1269
1270 tps32 = (uint32_t)tps64;
50933623
JK		 1271 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1272 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1273 scaled64 >>= 1;
1274 else
1275 tps32 <<= 1;
50d0a0f9
GH		 1276 shift++;
1277 }
1278
5f4e3f88
ZA		 1279 *pshift = shift;
1280 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1281
3ae13faa
PB		 1282 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1283 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1284}
1285
d828199e 1286#ifdef CONFIG_X86_64
16e8d74d 1287static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1288#endif
16e8d74d 1289
c8076604 1290static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1291static unsigned long max_tsc_khz;
c8076604 1292
cc578287 1293static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1294{
cc578287
ZA		 1295 u64 v = (u64)khz * (1000000 + ppm);
1296 do_div(v, 1000000);
1297 return v;
1e993611
JR		 1298}
1299
381d585c
HZ		 1300static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1301{
1302 u64 ratio;
1303
1304 /* Guest TSC same frequency as host TSC? */
1305 if (!scale) {
1306 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1307 return 0;
1308 }
1309
1310 /* TSC scaling supported? */
1311 if (!kvm_has_tsc_control) {
1312 if (user_tsc_khz > tsc_khz) {
1313 vcpu->arch.tsc_catchup = 1;
1314 vcpu->arch.tsc_always_catchup = 1;
1315 return 0;
1316 } else {
1317 WARN(1, "user requested TSC rate below hardware speed\n");
1318 return -1;
1319 }
1320 }
1321
1322 /* TSC scaling required - calculate ratio */
1323 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1324 user_tsc_khz, tsc_khz);
1325
1326 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1327 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1328 user_tsc_khz);
1329 return -1;
1330 }
1331
1332 vcpu->arch.tsc_scaling_ratio = ratio;
1333 return 0;
1334}
1335
4941b8cb 1336static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1337{
cc578287
ZA		 1338 u32 thresh_lo, thresh_hi;
1339 int use_scaling = 0;
217fc9cf 1340
03ba32ca 1341 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1342 if (user_tsc_khz == 0) {
ad721883
HZ		 1343 /* set tsc_scaling_ratio to a safe value */
1344 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1345 return -1;
ad721883 1346 }
03ba32ca 1347
c285545f 1348 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1349 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1350 &vcpu->arch.virtual_tsc_shift,
1351 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1352 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1353
1354 /*
1355 * Compute the variation in TSC rate which is acceptable
1356 * within the range of tolerance and decide if the
1357 * rate being applied is within that bounds of the hardware
1358 * rate. If so, no scaling or compensation need be done.
1359 */
1360 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1361 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1362 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1363 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1364 use_scaling = 1;
1365 }
4941b8cb 1366 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1367}
1368
1369static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1370{
e26101b1 1371 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1372 vcpu->arch.virtual_tsc_mult,
1373 vcpu->arch.virtual_tsc_shift);
e26101b1 1374 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1375 return tsc;
1376}
1377
69b0049a 1378static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1379{
1380#ifdef CONFIG_X86_64
1381 bool vcpus_matched;
b48aa97e
MT		 1382 struct kvm_arch *ka = &vcpu->kvm->arch;
1383 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1384
1385 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1386 atomic_read(&vcpu->kvm->online_vcpus));
1387
7f187922
MT		 1388 /*
1389 * Once the masterclock is enabled, always perform request in
1390 * order to update it.
1391 *
1392 * In order to enable masterclock, the host clocksource must be TSC
1393 * and the vcpus need to have matched TSCs. When that happens,
1394 * perform request to enable masterclock.
1395 */
1396 if (ka->use_master_clock ||
1397 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1398 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1399
1400 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1401 atomic_read(&vcpu->kvm->online_vcpus),
1402 ka->use_master_clock, gtod->clock.vclock_mode);
1403#endif
1404}
1405
ba904635
WA		 1406static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1407{
3e3f5026 1408 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1409 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1410}
1411
35181e86
HZ		 1412/*
1413 * Multiply tsc by a fixed point number represented by ratio.
1414 *
1415 * The most significant 64-N bits (mult) of ratio represent the
1416 * integral part of the fixed point number; the remaining N bits
1417 * (frac) represent the fractional part, ie. ratio represents a fixed
1418 * point number (mult + frac * 2^(-N)).
1419 *
1420 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1421 */
1422static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1423{
1424 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1425}
1426
1427u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1428{
1429 u64 _tsc = tsc;
1430 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1431
1432 if (ratio != kvm_default_tsc_scaling_ratio)
1433 _tsc = __scale_tsc(ratio, tsc);
1434
1435 return _tsc;
1436}
1437EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1438
07c1419a
HZ		 1439static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1440{
1441 u64 tsc;
1442
1443 tsc = kvm_scale_tsc(vcpu, rdtsc());
1444
1445 return target_tsc - tsc;
1446}
1447
4ba76538
HZ		 1448u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1449{
ea26e4ec 1450 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1451}
1452EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1453
a545ab6a
LC		 1454static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1455{
1456 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1457 vcpu->arch.tsc_offset = offset;
1458}
1459
8fe8ab46 1460void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1461{
1462 struct kvm *kvm = vcpu->kvm;
f38e098f 1463 u64 offset, ns, elapsed;
99e3e30a 1464 unsigned long flags;
b48aa97e 1465 bool matched;
0d3da0d2 1466 bool already_matched;
8fe8ab46 1467 u64 data = msr->data;
c5e8ec8e 1468 bool synchronizing = false;
99e3e30a 1469
038f8c11 1470 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1471 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1472 ns = ktime_get_boot_ns();
f38e098f 1473 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1474
03ba32ca 1475 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1476 if (data == 0 && msr->host_initiated) {
1477 /*
1478 * detection of vcpu initialization -- need to sync
1479 * with other vCPUs. This particularly helps to keep
1480 * kvm_clock stable after CPU hotplug
1481 */
1482 synchronizing = true;
1483 } else {
1484 u64 tsc_exp = kvm->arch.last_tsc_write +
1485 nsec_to_cycles(vcpu, elapsed);
1486 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1487 /*
1488 * Special case: TSC write with a small delta (1 second)
1489 * of virtual cycle time against real time is
1490 * interpreted as an attempt to synchronize the CPU.
1491 */
1492 synchronizing = data < tsc_exp + tsc_hz &&
1493 data + tsc_hz > tsc_exp;
1494 }
c5e8ec8e 1495 }
f38e098f
ZA		 1496
1497 /*
5d3cb0f6
ZA		 1498 * For a reliable TSC, we can match TSC offsets, and for an unstable
1499 * TSC, we add elapsed time in this computation. We could let the
1500 * compensation code attempt to catch up if we fall behind, but
1501 * it's better to try to match offsets from the beginning.
1502 */
c5e8ec8e 1503 if (synchronizing &&
5d3cb0f6 1504 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1505 if (!check_tsc_unstable()) {
e26101b1 1506 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1507 pr_debug("kvm: matched tsc offset for %llu\n", data);
1508 } else {
857e4099 1509 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1510 data += delta;
07c1419a 1511 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1512 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1513 }
b48aa97e 1514 matched = true;
0d3da0d2 1515 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1516 } else {
1517 /*
1518 * We split periods of matched TSC writes into generations.
1519 * For each generation, we track the original measured
1520 * nanosecond time, offset, and write, so if TSCs are in
1521 * sync, we can match exact offset, and if not, we can match
4a969980 1522 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1523 *
1524 * These values are tracked in kvm->arch.cur_xxx variables.
1525 */
1526 kvm->arch.cur_tsc_generation++;
1527 kvm->arch.cur_tsc_nsec = ns;
1528 kvm->arch.cur_tsc_write = data;
1529 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1530 matched = false;
0d3da0d2 1531 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1532 kvm->arch.cur_tsc_generation, data);
f38e098f 1533 }
e26101b1
ZA		 1534
1535 /*
1536 * We also track th most recent recorded KHZ, write and time to
1537 * allow the matching interval to be extended at each write.
1538 */
f38e098f
ZA		 1539 kvm->arch.last_tsc_nsec = ns;
1540 kvm->arch.last_tsc_write = data;
5d3cb0f6 1541 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1542
b183aa58 1543 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1544
1545 /* Keep track of which generation this VCPU has synchronized to */
1546 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1547 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1548 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1549
d6321d49 1550 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1551 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1552
a545ab6a 1553 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1554 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1555
1556 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1557 if (!matched) {
b48aa97e 1558 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1559 } else if (!already_matched) {
1560 kvm->arch.nr_vcpus_matched_tsc++;
1561 }
b48aa97e
MT		 1562
1563 kvm_track_tsc_matching(vcpu);
1564 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1565}
e26101b1 1566
99e3e30a
ZA		 1567EXPORT_SYMBOL_GPL(kvm_write_tsc);
1568
58ea6767
HZ		 1569static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1570 s64 adjustment)
1571{
ea26e4ec 1572 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1573}
1574
1575static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1576{
1577 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1578 WARN_ON(adjustment < 0);
1579 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1580 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1581}
1582
d828199e
MT		 1583#ifdef CONFIG_X86_64
1584
a5a1d1c2 1585static u64 read_tsc(void)
d828199e 1586{
a5a1d1c2 1587 u64 ret = (u64)rdtsc_ordered();
03b9730b 1588 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1589
1590 if (likely(ret >= last))
1591 return ret;
1592
1593 /*
1594 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1595 * predictable (it's just a function of time and the likely is
d828199e
MT		 1596 * very likely) and there's a data dependence, so force GCC
1597 * to generate a branch instead. I don't barrier() because
1598 * we don't actually need a barrier, and if this function
1599 * ever gets inlined it will generate worse code.
1600 */
1601 asm volatile ("");
1602 return last;
1603}
1604
a5a1d1c2 1605static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1606{
1607 long v;
1608 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1609
1610 *cycle_now = read_tsc();
1611
1612 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1613 return v * gtod->clock.mult;
1614}
1615
a5a1d1c2 1616static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1617{
cbcf2dd3 1618 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1619 unsigned long seq;
d828199e 1620 int mode;
cbcf2dd3 1621 u64 ns;
d828199e 1622
d828199e
MT		 1623 do {
1624 seq = read_seqcount_begin(&gtod->seq);
1625 mode = gtod->clock.vclock_mode;
cbcf2dd3 1626 ns = gtod->nsec_base;
d828199e
MT		 1627 ns += vgettsc(cycle_now);
1628 ns >>= gtod->clock.shift;
cbcf2dd3 1629 ns += gtod->boot_ns;
d828199e 1630 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1631 *t = ns;
d828199e
MT		 1632
1633 return mode;
1634}
1635
55dd00a7
MT		 1636static int do_realtime(struct timespec *ts, u64 *cycle_now)
1637{
1638 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1639 unsigned long seq;
1640 int mode;
1641 u64 ns;
1642
1643 do {
1644 seq = read_seqcount_begin(&gtod->seq);
1645 mode = gtod->clock.vclock_mode;
1646 ts->tv_sec = gtod->wall_time_sec;
1647 ns = gtod->nsec_base;
1648 ns += vgettsc(cycle_now);
1649 ns >>= gtod->clock.shift;
1650 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1651
1652 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1653 ts->tv_nsec = ns;
1654
1655 return mode;
1656}
1657
d828199e 1658/* returns true if host is using tsc clocksource */
a5a1d1c2 1659static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1660{
d828199e
MT		 1661 /* checked again under seqlock below */
1662 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1663 return false;
1664
cbcf2dd3 1665 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1666}
55dd00a7
MT		 1667
1668/* returns true if host is using tsc clocksource */
1669static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1670 u64 *cycle_now)
1671{
1672 /* checked again under seqlock below */
1673 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1674 return false;
1675
1676 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1677}
d828199e
MT		 1678#endif
1679
1680/*
1681 *
b48aa97e
MT		 1682 * Assuming a stable TSC across physical CPUS, and a stable TSC
1683 * across virtual CPUs, the following condition is possible.
1684 * Each numbered line represents an event visible to both
d828199e
MT		 1685 * CPUs at the next numbered event.
1686 *
1687 * "timespecX" represents host monotonic time. "tscX" represents
1688 * RDTSC value.
1689 *
1690 * VCPU0 on CPU0 | VCPU1 on CPU1
1691 *
1692 * 1. read timespec0,tsc0
1693 * 2. | timespec1 = timespec0 + N
1694 * | tsc1 = tsc0 + M
1695 * 3. transition to guest | transition to guest
1696 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1697 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1698 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1699 *
1700 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1701 *
1702 * - ret0 < ret1
1703 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1704 * ...
1705 * - 0 < N - M => M < N
1706 *
1707 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1708 * always the case (the difference between two distinct xtime instances
1709 * might be smaller then the difference between corresponding TSC reads,
1710 * when updating guest vcpus pvclock areas).
1711 *
1712 * To avoid that problem, do not allow visibility of distinct
1713 * system_timestamp/tsc_timestamp values simultaneously: use a master
1714 * copy of host monotonic time values. Update that master copy
1715 * in lockstep.
1716 *
b48aa97e 1717 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1718 *
1719 */
1720
1721static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1722{
1723#ifdef CONFIG_X86_64
1724 struct kvm_arch *ka = &kvm->arch;
1725 int vclock_mode;
b48aa97e
MT		 1726 bool host_tsc_clocksource, vcpus_matched;
1727
1728 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1729 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1730
1731 /*
1732 * If the host uses TSC clock, then passthrough TSC as stable
1733 * to the guest.
1734 */
b48aa97e 1735 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1736 &ka->master_kernel_ns,
1737 &ka->master_cycle_now);
1738
16a96021 1739 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1740 && !ka->backwards_tsc_observed
54750f2c 1741 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1742
d828199e
MT		 1743 if (ka->use_master_clock)
1744 atomic_set(&kvm_guest_has_master_clock, 1);
1745
1746 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1747 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1748 vcpus_matched);
d828199e
MT		 1749#endif
1750}
1751
2860c4b1
PB		 1752void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1753{
1754 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1755}
1756
2e762ff7
MT		 1757static void kvm_gen_update_masterclock(struct kvm *kvm)
1758{
1759#ifdef CONFIG_X86_64
1760 int i;
1761 struct kvm_vcpu *vcpu;
1762 struct kvm_arch *ka = &kvm->arch;
1763
1764 spin_lock(&ka->pvclock_gtod_sync_lock);
1765 kvm_make_mclock_inprogress_request(kvm);
1766 /* no guest entries from this point */
1767 pvclock_update_vm_gtod_copy(kvm);
1768
1769 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1770 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1771
1772 /* guest entries allowed */
1773 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1774 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1775
1776 spin_unlock(&ka->pvclock_gtod_sync_lock);
1777#endif
1778}
1779
e891a32e 1780u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1781{
108b249c 1782 struct kvm_arch *ka = &kvm->arch;
8b953440 1783 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1784 u64 ret;
108b249c 1785
8b953440
PB		 1786 spin_lock(&ka->pvclock_gtod_sync_lock);
1787 if (!ka->use_master_clock) {
1788 spin_unlock(&ka->pvclock_gtod_sync_lock);
1789 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1790 }
1791
8b953440
PB		 1792 hv_clock.tsc_timestamp = ka->master_cycle_now;
1793 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1794 spin_unlock(&ka->pvclock_gtod_sync_lock);
1795
e2c2206a
WL		 1796 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1797 get_cpu();
1798
2f1b5183
WL		 1799 if (__this_cpu_read(cpu_tsc_khz)) {
1800 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1801 &hv_clock.tsc_shift,
1802 &hv_clock.tsc_to_system_mul);
1803 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1804 } else
1805 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1806
1807 put_cpu();
1808
1809 return ret;
108b249c
PB		 1810}
1811
0d6dd2ff
PB		 1812static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1813{
1814 struct kvm_vcpu_arch *vcpu = &v->arch;
1815 struct pvclock_vcpu_time_info guest_hv_clock;
1816
4e335d9e 1817 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1818 &guest_hv_clock, sizeof(guest_hv_clock))))
1819 return;
1820
1821 /* This VCPU is paused, but it's legal for a guest to read another
1822 * VCPU's kvmclock, so we really have to follow the specification where
1823 * it says that version is odd if data is being modified, and even after
1824 * it is consistent.
1825 *
1826 * Version field updates must be kept separate. This is because
1827 * kvm_write_guest_cached might use a "rep movs" instruction, and
1828 * writes within a string instruction are weakly ordered. So there
1829 * are three writes overall.
1830 *
1831 * As a small optimization, only write the version field in the first
1832 * and third write. The vcpu->pv_time cache is still valid, because the
1833 * version field is the first in the struct.
1834 */
1835 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1836
6c4eaffb
LA		 1837 if (guest_hv_clock.version & 1)
1838 ++guest_hv_clock.version; /* first time write, random junk */
1839
0d6dd2ff 1840 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1841 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1842 &vcpu->hv_clock,
1843 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1844
1845 smp_wmb();
1846
1847 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1848 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1849
1850 if (vcpu->pvclock_set_guest_stopped_request) {
1851 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1852 vcpu->pvclock_set_guest_stopped_request = false;
1853 }
1854
1855 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1856
4e335d9e
PB		 1857 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1858 &vcpu->hv_clock,
1859 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1860
1861 smp_wmb();
1862
1863 vcpu->hv_clock.version++;
4e335d9e
PB		 1864 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1865 &vcpu->hv_clock,
1866 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1867}
1868
34c238a1 1869static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1870{
78db6a50 1871 unsigned long flags, tgt_tsc_khz;
18068523 1872 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1873 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1874 s64 kernel_ns;
d828199e 1875 u64 tsc_timestamp, host_tsc;
51d59c6b 1876 u8 pvclock_flags;
d828199e
MT		 1877 bool use_master_clock;
1878
1879 kernel_ns = 0;
1880 host_tsc = 0;
18068523 1881
d828199e
MT		 1882 /*
1883 * If the host uses TSC clock, then passthrough TSC as stable
1884 * to the guest.
1885 */
1886 spin_lock(&ka->pvclock_gtod_sync_lock);
1887 use_master_clock = ka->use_master_clock;
1888 if (use_master_clock) {
1889 host_tsc = ka->master_cycle_now;
1890 kernel_ns = ka->master_kernel_ns;
1891 }
1892 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1893
1894 /* Keep irq disabled to prevent changes to the clock */
1895 local_irq_save(flags);
78db6a50
PB		 1896 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1897 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1898 local_irq_restore(flags);
1899 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1900 return 1;
1901 }
d828199e 1902 if (!use_master_clock) {
4ea1636b 1903 host_tsc = rdtsc();
108b249c 1904 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1905 }
1906
4ba76538 1907 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1908
c285545f
ZA		 1909 /*
1910 * We may have to catch up the TSC to match elapsed wall clock
1911 * time for two reasons, even if kvmclock is used.
1912 * 1) CPU could have been running below the maximum TSC rate
1913 * 2) Broken TSC compensation resets the base at each VCPU
1914 * entry to avoid unknown leaps of TSC even when running
1915 * again on the same CPU. This may cause apparent elapsed
1916 * time to disappear, and the guest to stand still or run
1917 * very slowly.
1918 */
1919 if (vcpu->tsc_catchup) {
1920 u64 tsc = compute_guest_tsc(v, kernel_ns);
1921 if (tsc > tsc_timestamp) {
f1e2b260 1922 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1923 tsc_timestamp = tsc;
1924 }
50d0a0f9
GH		 1925 }
1926
18068523
GOC		 1927 local_irq_restore(flags);
1928
0d6dd2ff 1929 /* With all the info we got, fill in the values */
18068523 1930
78db6a50
PB		 1931 if (kvm_has_tsc_control)
1932 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1933
1934 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1935 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1936 &vcpu->hv_clock.tsc_shift,
1937 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1938 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1939 }
1940
1d5f066e 1941 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1942 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1943 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1944
d828199e 1945 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1946 pvclock_flags = 0;
d828199e
MT		 1947 if (use_master_clock)
1948 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1949
78c0337a
MT		 1950 vcpu->hv_clock.flags = pvclock_flags;
1951
095cf55d
PB		 1952 if (vcpu->pv_time_enabled)
1953 kvm_setup_pvclock_page(v);
1954 if (v == kvm_get_vcpu(v->kvm, 0))
1955 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1956 return 0;
c8076604
GH		 1957}
1958
0061d53d
MT		 1959/*
1960 * kvmclock updates which are isolated to a given vcpu, such as
1961 * vcpu->cpu migration, should not allow system_timestamp from
1962 * the rest of the vcpus to remain static. Otherwise ntp frequency
1963 * correction applies to one vcpu's system_timestamp but not
1964 * the others.
1965 *
1966 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1967 * We need to rate-limit these requests though, as they can
1968 * considerably slow guests that have a large number of vcpus.
1969 * The time for a remote vcpu to update its kvmclock is bound
1970 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1971 */
1972
7e44e449
AJ		 1973#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1974
1975static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1976{
1977 int i;
7e44e449
AJ		 1978 struct delayed_work *dwork = to_delayed_work(work);
1979 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1980 kvmclock_update_work);
1981 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1982 struct kvm_vcpu *vcpu;
1983
1984 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1985 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1986 kvm_vcpu_kick(vcpu);
1987 }
1988}
1989
7e44e449
AJ		 1990static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1991{
1992 struct kvm *kvm = v->kvm;
1993
105b21bb 1994 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1995 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1996 KVMCLOCK_UPDATE_DELAY);
1997}
1998
332967a3
AJ		 1999#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2000
2001static void kvmclock_sync_fn(struct work_struct *work)
2002{
2003 struct delayed_work *dwork = to_delayed_work(work);
2004 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2005 kvmclock_sync_work);
2006 struct kvm *kvm = container_of(ka, struct kvm, arch);
2007
630994b3
MT		 2008 if (!kvmclock_periodic_sync)
2009 return;
2010
332967a3
AJ		 2011 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2012 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2013 KVMCLOCK_SYNC_PERIOD);
2014}
2015
890ca9ae 2016static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 2017{
890ca9ae
HY		 2018 u64 mcg_cap = vcpu->arch.mcg_cap;
2019 unsigned bank_num = mcg_cap & 0xff;
2020
15c4a640 2021 switch (msr) {
15c4a640 2022 case MSR_IA32_MCG_STATUS:
890ca9ae 2023 vcpu->arch.mcg_status = data;
15c4a640 2024 break;
c7ac679c 2025 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2026 if (!(mcg_cap & MCG_CTL_P))
2027 return 1;
2028 if (data != 0 && data != ~(u64)0)
2029 return -1;
2030 vcpu->arch.mcg_ctl = data;
2031 break;
2032 default:
2033 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2034 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2035 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2036 /* only 0 or all 1s can be written to IA32_MCi_CTL
2037 * some Linux kernels though clear bit 10 in bank 4 to
2038 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2039 * this to avoid an uncatched #GP in the guest
2040 */
890ca9ae 2041 if ((offset & 0x3) == 0 &&
114be429 2042 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2043 return -1;
2044 vcpu->arch.mce_banks[offset] = data;
2045 break;
2046 }
2047 return 1;
2048 }
2049 return 0;
2050}
2051
ffde22ac
ES		 2052static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2053{
2054 struct kvm *kvm = vcpu->kvm;
2055 int lm = is_long_mode(vcpu);
2056 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2057 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2058 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2059 : kvm->arch.xen_hvm_config.blob_size_32;
2060 u32 page_num = data & ~PAGE_MASK;
2061 u64 page_addr = data & PAGE_MASK;
2062 u8 *page;
2063 int r;
2064
2065 r = -E2BIG;
2066 if (page_num >= blob_size)
2067 goto out;
2068 r = -ENOMEM;
ff5c2c03
SL		 2069 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2070 if (IS_ERR(page)) {
2071 r = PTR_ERR(page);
ffde22ac 2072 goto out;
ff5c2c03 2073 }
54bf36aa 2074 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2075 goto out_free;
2076 r = 0;
2077out_free:
2078 kfree(page);
2079out:
2080 return r;
2081}
2082
344d9588
GN		 2083static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2084{
2085 gpa_t gpa = data & ~0x3f;
2086
52a5c155
WL		 2087 /* Bits 3:5 are reserved, Should be zero */
2088 if (data & 0x38)
344d9588
GN		 2089 return 1;
2090
2091 vcpu->arch.apf.msr_val = data;
2092
2093 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2094 kvm_clear_async_pf_completion_queue(vcpu);
2095 kvm_async_pf_hash_reset(vcpu);
2096 return 0;
2097 }
2098
4e335d9e 2099 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2100 sizeof(u32)))
344d9588
GN		 2101 return 1;
2102
6adba527 2103 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2104 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2105 kvm_async_pf_wakeup_all(vcpu);
2106 return 0;
2107}
2108
12f9a48f
GC		 2109static void kvmclock_reset(struct kvm_vcpu *vcpu)
2110{
0b79459b 2111 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2112}
2113
c9aaa895
GC		 2114static void record_steal_time(struct kvm_vcpu *vcpu)
2115{
2116 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2117 return;
2118
4e335d9e 2119 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2120 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2121 return;
2122
0b9f6c46
PX		 2123 vcpu->arch.st.steal.preempted = 0;
2124
35f3fae1
WL		 2125 if (vcpu->arch.st.steal.version & 1)
2126 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2127
2128 vcpu->arch.st.steal.version += 1;
2129
4e335d9e 2130 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2131 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2132
2133 smp_wmb();
2134
c54cdf14
LC		 2135 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2136 vcpu->arch.st.last_steal;
2137 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2138
4e335d9e 2139 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2140 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2141
2142 smp_wmb();
2143
2144 vcpu->arch.st.steal.version += 1;
c9aaa895 2145
4e335d9e 2146 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2147 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2148}
2149
8fe8ab46 2150int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2151{
5753785f 2152 bool pr = false;
8fe8ab46
WA		 2153 u32 msr = msr_info->index;
2154 u64 data = msr_info->data;
5753785f 2155
15c4a640 2156 switch (msr) {
2e32b719
BP		 2157 case MSR_AMD64_NB_CFG:
2158 case MSR_IA32_UCODE_REV:
2159 case MSR_IA32_UCODE_WRITE:
2160 case MSR_VM_HSAVE_PA:
2161 case MSR_AMD64_PATCH_LOADER:
2162 case MSR_AMD64_BU_CFG2:
405a353a 2163 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2164 break;
2165
15c4a640 2166 case MSR_EFER:
b69e8cae 2167 return set_efer(vcpu, data);
8f1589d9
AP		 2168 case MSR_K7_HWCR:
2169 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2170 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2171 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2172 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2173 if (data != 0) {
a737f256
CD		 2174 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2175 data);
8f1589d9
AP		 2176 return 1;
2177 }
15c4a640 2178 break;
f7c6d140
AP		 2179 case MSR_FAM10H_MMIO_CONF_BASE:
2180 if (data != 0) {
a737f256
CD		 2181 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2182 "0x%llx\n", data);
f7c6d140
AP		 2183 return 1;
2184 }
15c4a640 2185 break;
b5e2fec0
AG		 2186 case MSR_IA32_DEBUGCTLMSR:
2187 if (!data) {
2188 /* We support the non-activated case already */
2189 break;
2190 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2191 /* Values other than LBR and BTF are vendor-specific,
2192 thus reserved and should throw a #GP */
2193 return 1;
2194 }
a737f256
CD		 2195 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2196 __func__, data);
b5e2fec0 2197 break;
9ba075a6 2198 case 0x200 ... 0x2ff:
ff53604b 2199 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2200 case MSR_IA32_APICBASE:
58cb628d 2201 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2202 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2203 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2204 case MSR_IA32_TSCDEADLINE:
2205 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2206 break;
ba904635 2207 case MSR_IA32_TSC_ADJUST:
d6321d49 2208 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2209 if (!msr_info->host_initiated) {
d913b904 2210 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2211 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2212 }
2213 vcpu->arch.ia32_tsc_adjust_msr = data;
2214 }
2215 break;
15c4a640 2216 case MSR_IA32_MISC_ENABLE:
ad312c7c 2217 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2218 break;
64d60670
PB		 2219 case MSR_IA32_SMBASE:
2220 if (!msr_info->host_initiated)
2221 return 1;
2222 vcpu->arch.smbase = data;
2223 break;
11c6bffa 2224 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2225 case MSR_KVM_WALL_CLOCK:
2226 vcpu->kvm->arch.wall_clock = data;
2227 kvm_write_wall_clock(vcpu->kvm, data);
2228 break;
11c6bffa 2229 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2230 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2231 struct kvm_arch *ka = &vcpu->kvm->arch;
2232
12f9a48f 2233 kvmclock_reset(vcpu);
18068523 2234
54750f2c
MT		 2235 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2236 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2237
2238 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2239 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2240
2241 ka->boot_vcpu_runs_old_kvmclock = tmp;
2242 }
2243
18068523 2244 vcpu->arch.time = data;
0061d53d 2245 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2246
2247 /* we verify if the enable bit is set... */
2248 if (!(data & 1))
2249 break;
2250
4e335d9e 2251 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2252 &vcpu->arch.pv_time, data & ~1ULL,
2253 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2254 vcpu->arch.pv_time_enabled = false;
2255 else
2256 vcpu->arch.pv_time_enabled = true;
32cad84f 2257
18068523
GOC		 2258 break;
2259 }
344d9588
GN		 2260 case MSR_KVM_ASYNC_PF_EN:
2261 if (kvm_pv_enable_async_pf(vcpu, data))
2262 return 1;
2263 break;
c9aaa895
GC		 2264 case MSR_KVM_STEAL_TIME:
2265
2266 if (unlikely(!sched_info_on()))
2267 return 1;
2268
2269 if (data & KVM_STEAL_RESERVED_MASK)
2270 return 1;
2271
4e335d9e 2272 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2273 data & KVM_STEAL_VALID_BITS,
2274 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2275 return 1;
2276
2277 vcpu->arch.st.msr_val = data;
2278
2279 if (!(data & KVM_MSR_ENABLED))
2280 break;
2281
c9aaa895
GC		 2282 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2283
2284 break;
ae7a2a3f
MT		 2285 case MSR_KVM_PV_EOI_EN:
2286 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2287 return 1;
2288 break;
c9aaa895 2289
890ca9ae
HY		 2290 case MSR_IA32_MCG_CTL:
2291 case MSR_IA32_MCG_STATUS:
81760dcc 2292 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2293 return set_msr_mce(vcpu, msr, data);
71db6023 2294
6912ac32
WH		 2295 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2296 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2297 pr = true; /* fall through */
2298 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2299 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2300 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2301 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2302
2303 if (pr || data != 0)
a737f256
CD		 2304 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2305 "0x%x data 0x%llx\n", msr, data);
5753785f 2306 break;
84e0cefa
JS		 2307 case MSR_K7_CLK_CTL:
2308 /*
2309 * Ignore all writes to this no longer documented MSR.
2310 * Writes are only relevant for old K7 processors,
2311 * all pre-dating SVM, but a recommended workaround from
4a969980 2312 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2313 * affected processor models on the command line, hence
2314 * the need to ignore the workaround.
2315 */
2316 break;
55cd8e5a 2317 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2318 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2319 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2320 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2321 return kvm_hv_set_msr_common(vcpu, msr, data,
2322 msr_info->host_initiated);
91c9c3ed 2323 case MSR_IA32_BBL_CR_CTL3:
2324 /* Drop writes to this legacy MSR -- see rdmsr
2325 * counterpart for further detail.
2326 */
796f4687 2327 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2328 break;
2b036c6b 2329 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2330 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2331 return 1;
2332 vcpu->arch.osvw.length = data;
2333 break;
2334 case MSR_AMD64_OSVW_STATUS:
d6321d49 2335 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2336 return 1;
2337 vcpu->arch.osvw.status = data;
2338 break;
db2336a8
KH		 2339 case MSR_PLATFORM_INFO:
2340 if (!msr_info->host_initiated ||
2341 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2342 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2343 cpuid_fault_enabled(vcpu)))
2344 return 1;
2345 vcpu->arch.msr_platform_info = data;
2346 break;
2347 case MSR_MISC_FEATURES_ENABLES:
2348 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2349 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2350 !supports_cpuid_fault(vcpu)))
2351 return 1;
2352 vcpu->arch.msr_misc_features_enables = data;
2353 break;
15c4a640 2354 default:
ffde22ac
ES		 2355 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2356 return xen_hvm_config(vcpu, data);
c6702c9d 2357 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2358 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2359 if (!ignore_msrs) {
ae0f5499 2360 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2361 msr, data);
ed85c068
AP		 2362 return 1;
2363 } else {
796f4687 2364 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2365 msr, data);
ed85c068
AP		 2366 break;
2367 }
15c4a640
CO		 2368 }
2369 return 0;
2370}
2371EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2372
2373
2374/*
2375 * Reads an msr value (of 'msr_index') into 'pdata'.
2376 * Returns 0 on success, non-0 otherwise.
2377 * Assumes vcpu_load() was already called.
2378 */
609e36d3 2379int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2380{
609e36d3 2381 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2382}
ff651cb6 2383EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2384
890ca9ae 2385static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2386{
2387 u64 data;
890ca9ae
HY		 2388 u64 mcg_cap = vcpu->arch.mcg_cap;
2389 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2390
2391 switch (msr) {
15c4a640
CO		 2392 case MSR_IA32_P5_MC_ADDR:
2393 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2394 data = 0;
2395 break;
15c4a640 2396 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2397 data = vcpu->arch.mcg_cap;
2398 break;
c7ac679c 2399 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2400 if (!(mcg_cap & MCG_CTL_P))
2401 return 1;
2402 data = vcpu->arch.mcg_ctl;
2403 break;
2404 case MSR_IA32_MCG_STATUS:
2405 data = vcpu->arch.mcg_status;
2406 break;
2407 default:
2408 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2409 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2410 u32 offset = msr - MSR_IA32_MC0_CTL;
2411 data = vcpu->arch.mce_banks[offset];
2412 break;
2413 }
2414 return 1;
2415 }
2416 *pdata = data;
2417 return 0;
2418}
2419
609e36d3 2420int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2421{
609e36d3 2422 switch (msr_info->index) {
890ca9ae 2423 case MSR_IA32_PLATFORM_ID:
15c4a640 2424 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2425 case MSR_IA32_DEBUGCTLMSR:
2426 case MSR_IA32_LASTBRANCHFROMIP:
2427 case MSR_IA32_LASTBRANCHTOIP:
2428 case MSR_IA32_LASTINTFROMIP:
2429 case MSR_IA32_LASTINTTOIP:
60af2ecd 2430 case MSR_K8_SYSCFG:
3afb1121
PB		 2431 case MSR_K8_TSEG_ADDR:
2432 case MSR_K8_TSEG_MASK:
60af2ecd 2433 case MSR_K7_HWCR:
61a6bd67 2434 case MSR_VM_HSAVE_PA:
1fdbd48c 2435 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2436 case MSR_AMD64_NB_CFG:
f7c6d140 2437 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2438 case MSR_AMD64_BU_CFG2:
0c2df2a1 2439 case MSR_IA32_PERF_CTL:
405a353a 2440 case MSR_AMD64_DC_CFG:
609e36d3 2441 msr_info->data = 0;
15c4a640 2442 break;
6912ac32
WH		 2443 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2444 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2445 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2446 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2447 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2448 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2449 msr_info->data = 0;
5753785f 2450 break;
742bc670 2451 case MSR_IA32_UCODE_REV:
609e36d3 2452 msr_info->data = 0x100000000ULL;
742bc670 2453 break;
9ba075a6 2454 case MSR_MTRRcap:
9ba075a6 2455 case 0x200 ... 0x2ff:
ff53604b 2456 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2457 case 0xcd: /* fsb frequency */
609e36d3 2458 msr_info->data = 3;
15c4a640 2459 break;
7b914098
JS		 2460 /*
2461 * MSR_EBC_FREQUENCY_ID
2462 * Conservative value valid for even the basic CPU models.
2463 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2464 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2465 * and 266MHz for model 3, or 4. Set Core Clock
2466 * Frequency to System Bus Frequency Ratio to 1 (bits
2467 * 31:24) even though these are only valid for CPU
2468 * models > 2, however guests may end up dividing or
2469 * multiplying by zero otherwise.
2470 */
2471 case MSR_EBC_FREQUENCY_ID:
609e36d3 2472 msr_info->data = 1 << 24;
7b914098 2473 break;
15c4a640 2474 case MSR_IA32_APICBASE:
609e36d3 2475 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2476 break;
0105d1a5 2477 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2478 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2479 break;
a3e06bbe 2480 case MSR_IA32_TSCDEADLINE:
609e36d3 2481 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2482 break;
ba904635 2483 case MSR_IA32_TSC_ADJUST:
609e36d3 2484 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2485 break;
15c4a640 2486 case MSR_IA32_MISC_ENABLE:
609e36d3 2487 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2488 break;
64d60670
PB		 2489 case MSR_IA32_SMBASE:
2490 if (!msr_info->host_initiated)
2491 return 1;
2492 msr_info->data = vcpu->arch.smbase;
15c4a640 2493 break;
847f0ad8
AG		 2494 case MSR_IA32_PERF_STATUS:
2495 /* TSC increment by tick */
609e36d3 2496 msr_info->data = 1000ULL;
847f0ad8 2497 /* CPU multiplier */
b0996ae4 2498 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2499 break;
15c4a640 2500 case MSR_EFER:
609e36d3 2501 msr_info->data = vcpu->arch.efer;
15c4a640 2502 break;
18068523 2503 case MSR_KVM_WALL_CLOCK:
11c6bffa 2504 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2505 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2506 break;
2507 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2508 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2509 msr_info->data = vcpu->arch.time;
18068523 2510 break;
344d9588 2511 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2512 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2513 break;
c9aaa895 2514 case MSR_KVM_STEAL_TIME:
609e36d3 2515 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2516 break;
1d92128f 2517 case MSR_KVM_PV_EOI_EN:
609e36d3 2518 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2519 break;
890ca9ae
HY		 2520 case MSR_IA32_P5_MC_ADDR:
2521 case MSR_IA32_P5_MC_TYPE:
2522 case MSR_IA32_MCG_CAP:
2523 case MSR_IA32_MCG_CTL:
2524 case MSR_IA32_MCG_STATUS:
81760dcc 2525 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2526 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2527 case MSR_K7_CLK_CTL:
2528 /*
2529 * Provide expected ramp-up count for K7. All other
2530 * are set to zero, indicating minimum divisors for
2531 * every field.
2532 *
2533 * This prevents guest kernels on AMD host with CPU
2534 * type 6, model 8 and higher from exploding due to
2535 * the rdmsr failing.
2536 */
609e36d3 2537 msr_info->data = 0x20000000;
84e0cefa 2538 break;
55cd8e5a 2539 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2540 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2541 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2542 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2543 return kvm_hv_get_msr_common(vcpu,
2544 msr_info->index, &msr_info->data);
55cd8e5a 2545 break;
91c9c3ed 2546 case MSR_IA32_BBL_CR_CTL3:
2547 /* This legacy MSR exists but isn't fully documented in current
2548 * silicon. It is however accessed by winxp in very narrow
2549 * scenarios where it sets bit #19, itself documented as
2550 * a "reserved" bit. Best effort attempt to source coherent
2551 * read data here should the balance of the register be
2552 * interpreted by the guest:
2553 *
2554 * L2 cache control register 3: 64GB range, 256KB size,
2555 * enabled, latency 0x1, configured
2556 */
609e36d3 2557 msr_info->data = 0xbe702111;
91c9c3ed 2558 break;
2b036c6b 2559 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2560 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2561 return 1;
609e36d3 2562 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2563 break;
2564 case MSR_AMD64_OSVW_STATUS:
d6321d49 2565 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2566 return 1;
609e36d3 2567 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2568 break;
db2336a8
KH		 2569 case MSR_PLATFORM_INFO:
2570 msr_info->data = vcpu->arch.msr_platform_info;
2571 break;
2572 case MSR_MISC_FEATURES_ENABLES:
2573 msr_info->data = vcpu->arch.msr_misc_features_enables;
2574 break;
15c4a640 2575 default:
c6702c9d 2576 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2577 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2578 if (!ignore_msrs) {
ae0f5499
BD		 2579 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2580 msr_info->index);
ed85c068
AP		 2581 return 1;
2582 } else {
609e36d3
PB		 2583 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2584 msr_info->data = 0;
ed85c068
AP		 2585 }
2586 break;
15c4a640 2587 }
15c4a640
CO		 2588 return 0;
2589}
2590EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2591
313a3dc7
CO		 2592/*
2593 * Read or write a bunch of msrs. All parameters are kernel addresses.
2594 *
2595 * @return number of msrs set successfully.
2596 */
2597static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2598 struct kvm_msr_entry *entries,
2599 int (*do_msr)(struct kvm_vcpu *vcpu,
2600 unsigned index, u64 *data))
2601{
f656ce01 2602 int i, idx;
313a3dc7 2603
f656ce01 2604 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2605 for (i = 0; i < msrs->nmsrs; ++i)
2606 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2607 break;
f656ce01 2608 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2609
313a3dc7
CO		 2610 return i;
2611}
2612
2613/*
2614 * Read or write a bunch of msrs. Parameters are user addresses.
2615 *
2616 * @return number of msrs set successfully.
2617 */
2618static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2619 int (*do_msr)(struct kvm_vcpu *vcpu,
2620 unsigned index, u64 *data),
2621 int writeback)
2622{
2623 struct kvm_msrs msrs;
2624 struct kvm_msr_entry *entries;
2625 int r, n;
2626 unsigned size;
2627
2628 r = -EFAULT;
2629 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2630 goto out;
2631
2632 r = -E2BIG;
2633 if (msrs.nmsrs >= MAX_IO_MSRS)
2634 goto out;
2635
313a3dc7 2636 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2637 entries = memdup_user(user_msrs->entries, size);
2638 if (IS_ERR(entries)) {
2639 r = PTR_ERR(entries);
313a3dc7 2640 goto out;
ff5c2c03 2641 }
313a3dc7
CO		 2642
2643 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2644 if (r < 0)
2645 goto out_free;
2646
2647 r = -EFAULT;
2648 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2649 goto out_free;
2650
2651 r = n;
2652
2653out_free:
7a73c028 2654 kfree(entries);
313a3dc7
CO		 2655out:
2656 return r;
2657}
2658
784aa3d7 2659int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2660{
2661 int r;
2662
2663 switch (ext) {
2664 case KVM_CAP_IRQCHIP:
2665 case KVM_CAP_HLT:
2666 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2667 case KVM_CAP_SET_TSS_ADDR:
07716717 2668 case KVM_CAP_EXT_CPUID:
9c15bb1d 2669 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2670 case KVM_CAP_CLOCKSOURCE:
7837699f 2671 case KVM_CAP_PIT:
a28e4f5a 2672 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2673 case KVM_CAP_MP_STATE:
ed848624 2674 case KVM_CAP_SYNC_MMU:
a355c85c 2675 case KVM_CAP_USER_NMI:
52d939a0 2676 case KVM_CAP_REINJECT_CONTROL:
4925663a 2677 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2678 case KVM_CAP_IOEVENTFD:
f848a5a8 2679 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2680 case KVM_CAP_PIT2:
e9f42757 2681 case KVM_CAP_PIT_STATE2:
b927a3ce 2682 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2683 case KVM_CAP_XEN_HVM:
3cfc3092 2684 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2685 case KVM_CAP_HYPERV:
10388a07 2686 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2687 case KVM_CAP_HYPERV_SPIN:
5c919412 2688 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2689 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2690 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2691 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2692 case KVM_CAP_DEBUGREGS:
d2be1651 2693 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2694 case KVM_CAP_XSAVE:
344d9588 2695 case KVM_CAP_ASYNC_PF:
92a1f12d 2696 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2697 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2698 case KVM_CAP_READONLY_MEM:
5f66b620 2699 case KVM_CAP_HYPERV_TIME:
100943c5 2700 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2701 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2702 case KVM_CAP_ENABLE_CAP_VM:
2703 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2704 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2705 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2706 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2707 r = 1;
2708 break;
e3fd9a93
PB		 2709 case KVM_CAP_ADJUST_CLOCK:
2710 r = KVM_CLOCK_TSC_STABLE;
2711 break;
668fffa3
MT		 2712 case KVM_CAP_X86_GUEST_MWAIT:
2713 r = kvm_mwait_in_guest();
2714 break;
6d396b55
PB		 2715 case KVM_CAP_X86_SMM:
2716 /* SMBASE is usually relocated above 1M on modern chipsets,
2717 * and SMM handlers might indeed rely on 4G segment limits,
2718 * so do not report SMM to be available if real mode is
2719 * emulated via vm86 mode. Still, do not go to great lengths
2720 * to avoid userspace's usage of the feature, because it is a
2721 * fringe case that is not enabled except via specific settings
2722 * of the module parameters.
2723 */
2724 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2725 break;
774ead3a
AK		 2726 case KVM_CAP_VAPIC:
2727 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2728 break;
f725230a 2729 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2730 r = KVM_SOFT_MAX_VCPUS;
2731 break;
2732 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2733 r = KVM_MAX_VCPUS;
2734 break;
a988b910 2735 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2736 r = KVM_USER_MEM_SLOTS;
a988b910 2737 break;
a68a6a72
MT		 2738 case KVM_CAP_PV_MMU: /* obsolete */
2739 r = 0;
2f333bcb 2740 break;
890ca9ae
HY		 2741 case KVM_CAP_MCE:
2742 r = KVM_MAX_MCE_BANKS;
2743 break;
2d5b5a66 2744 case KVM_CAP_XCRS:
d366bf7e 2745 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2746 break;
92a1f12d
JR		 2747 case KVM_CAP_TSC_CONTROL:
2748 r = kvm_has_tsc_control;
2749 break;
37131313
RK		 2750 case KVM_CAP_X2APIC_API:
2751 r = KVM_X2APIC_API_VALID_FLAGS;
2752 break;
018d00d2
ZX		 2753 default:
2754 r = 0;
2755 break;
2756 }
2757 return r;
2758
2759}
2760
043405e1
CO		 2761long kvm_arch_dev_ioctl(struct file *filp,
2762 unsigned int ioctl, unsigned long arg)
2763{
2764 void __user *argp = (void __user *)arg;
2765 long r;
2766
2767 switch (ioctl) {
2768 case KVM_GET_MSR_INDEX_LIST: {
2769 struct kvm_msr_list __user *user_msr_list = argp;
2770 struct kvm_msr_list msr_list;
2771 unsigned n;
2772
2773 r = -EFAULT;
2774 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2775 goto out;
2776 n = msr_list.nmsrs;
62ef68bb 2777 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2778 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2779 goto out;
2780 r = -E2BIG;
e125e7b6 2781 if (n < msr_list.nmsrs)
043405e1
CO		 2782 goto out;
2783 r = -EFAULT;
2784 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2785 num_msrs_to_save * sizeof(u32)))
2786 goto out;
e125e7b6 2787 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2788 &emulated_msrs,
62ef68bb 2789 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2790 goto out;
2791 r = 0;
2792 break;
2793 }
9c15bb1d
BP		 2794 case KVM_GET_SUPPORTED_CPUID:
2795 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2796 struct kvm_cpuid2 __user *cpuid_arg = argp;
2797 struct kvm_cpuid2 cpuid;
2798
2799 r = -EFAULT;
2800 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2801 goto out;
9c15bb1d
BP		 2802
2803 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2804 ioctl);
674eea0f
AK		 2805 if (r)
2806 goto out;
2807
2808 r = -EFAULT;
2809 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2810 goto out;
2811 r = 0;
2812 break;
2813 }
890ca9ae 2814 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2815 r = -EFAULT;
c45dcc71
AR		 2816 if (copy_to_user(argp, &kvm_mce_cap_supported,
2817 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2818 goto out;
2819 r = 0;
2820 break;
2821 }
043405e1
CO		 2822 default:
2823 r = -EINVAL;
2824 }
2825out:
2826 return r;
2827}
2828
f5f48ee1
SY		 2829static void wbinvd_ipi(void *garbage)
2830{
2831 wbinvd();
2832}
2833
2834static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2835{
e0f0bbc5 2836 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2837}
2838
313a3dc7
CO		 2839void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2840{
f5f48ee1
SY		 2841 /* Address WBINVD may be executed by guest */
2842 if (need_emulate_wbinvd(vcpu)) {
2843 if (kvm_x86_ops->has_wbinvd_exit())
2844 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2845 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2846 smp_call_function_single(vcpu->cpu,
2847 wbinvd_ipi, NULL, 1);
2848 }
2849
313a3dc7 2850 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2851
0dd6a6ed
ZA		 2852 /* Apply any externally detected TSC adjustments (due to suspend) */
2853 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2854 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2855 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2856 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2857 }
8f6055cb 2858
48434c20 2859 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2860 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2861 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2862 if (tsc_delta < 0)
2863 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2864
c285545f 2865 if (check_tsc_unstable()) {
07c1419a 2866 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2867 vcpu->arch.last_guest_tsc);
a545ab6a 2868 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2869 vcpu->arch.tsc_catchup = 1;
c285545f 2870 }
a749e247
PB		 2871
2872 if (kvm_lapic_hv_timer_in_use(vcpu))
2873 kvm_lapic_restart_hv_timer(vcpu);
2874
d98d07ca
MT		 2875 /*
2876 * On a host with synchronized TSC, there is no need to update
2877 * kvmclock on vcpu->cpu migration
2878 */
2879 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2880 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2881 if (vcpu->cpu != cpu)
1bd2009e 2882 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2883 vcpu->cpu = cpu;
6b7d7e76 2884 }
c9aaa895 2885
c9aaa895 2886 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2887}
2888
0b9f6c46
PX		 2889static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2890{
2891 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2892 return;
2893
2894 vcpu->arch.st.steal.preempted = 1;
2895
4e335d9e 2896 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2897 &vcpu->arch.st.steal.preempted,
2898 offsetof(struct kvm_steal_time, preempted),
2899 sizeof(vcpu->arch.st.steal.preempted));
2900}
2901
313a3dc7
CO		 2902void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2903{
cc0d907c 2904 int idx;
de63ad4c
LM		 2905
2906 if (vcpu->preempted)
2907 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2908
931f261b
AA		 2909 /*
2910 * Disable page faults because we're in atomic context here.
2911 * kvm_write_guest_offset_cached() would call might_fault()
2912 * that relies on pagefault_disable() to tell if there's a
2913 * bug. NOTE: the write to guest memory may not go through if
2914 * during postcopy live migration or if there's heavy guest
2915 * paging.
2916 */
2917 pagefault_disable();
cc0d907c
AA		 2918 /*
2919 * kvm_memslots() will be called by
2920 * kvm_write_guest_offset_cached() so take the srcu lock.
2921 */
2922 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2923 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2924 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2925 pagefault_enable();
02daab21 2926 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2927 kvm_put_guest_fpu(vcpu);
4ea1636b 2928 vcpu->arch.last_host_tsc = rdtsc();
7b5ec550
WL		 2929 /*
2930 * If userspace has set any breakpoints or watchpoints, dr6 is restored
2931 * on every vmexit, but if not, we might have a stale dr6 from the
2932 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
2933 */
2934 set_debugreg(0, 6);
313a3dc7
CO		 2935}
2936
313a3dc7
CO		 2937static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2938 struct kvm_lapic_state *s)
2939{
76dfafd5 2940 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2941 kvm_x86_ops->sync_pir_to_irr(vcpu);
2942
a92e2543 2943 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2944}
2945
2946static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2947 struct kvm_lapic_state *s)
2948{
a92e2543
RK		 2949 int r;
2950
2951 r = kvm_apic_set_state(vcpu, s);
2952 if (r)
2953 return r;
cb142eb7 2954 update_cr8_intercept(vcpu);
313a3dc7
CO		 2955
2956 return 0;
2957}
2958
127a457a
MG		 2959static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2960{
2961 return (!lapic_in_kernel(vcpu) ||
2962 kvm_apic_accept_pic_intr(vcpu));
2963}
2964
782d422b
MG		 2965/*
2966 * if userspace requested an interrupt window, check that the
2967 * interrupt window is open.
2968 *
2969 * No need to exit to userspace if we already have an interrupt queued.
2970 */
2971static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2972{
2973 return kvm_arch_interrupt_allowed(vcpu) &&
2974 !kvm_cpu_has_interrupt(vcpu) &&
2975 !kvm_event_needs_reinjection(vcpu) &&
2976 kvm_cpu_accept_dm_intr(vcpu);
2977}
2978
f77bc6a4
ZX		 2979static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2980 struct kvm_interrupt *irq)
2981{
02cdb50f 2982 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2983 return -EINVAL;
1c1a9ce9
SR		 2984
2985 if (!irqchip_in_kernel(vcpu->kvm)) {
2986 kvm_queue_interrupt(vcpu, irq->irq, false);
2987 kvm_make_request(KVM_REQ_EVENT, vcpu);
2988 return 0;
2989 }
2990
2991 /*
2992 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2993 * fail for in-kernel 8259.
2994 */
2995 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2996 return -ENXIO;
f77bc6a4 2997
1c1a9ce9
SR		 2998 if (vcpu->arch.pending_external_vector != -1)
2999 return -EEXIST;
f77bc6a4 3000
1c1a9ce9 3001 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3002 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3003 return 0;
3004}
3005
c4abb7c9
JK		 3006static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3007{
c4abb7c9 3008 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3009
3010 return 0;
3011}
3012
f077825a
PB		 3013static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3014{
64d60670
PB		 3015 kvm_make_request(KVM_REQ_SMI, vcpu);
3016
f077825a
PB		 3017 return 0;
3018}
3019
b209749f
AK		 3020static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3021 struct kvm_tpr_access_ctl *tac)
3022{
3023 if (tac->flags)
3024 return -EINVAL;
3025 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3026 return 0;
3027}
3028
890ca9ae
HY		 3029static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3030 u64 mcg_cap)
3031{
3032 int r;
3033 unsigned bank_num = mcg_cap & 0xff, bank;
3034
3035 r = -EINVAL;
a9e38c3e 3036 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3037 goto out;
c45dcc71 3038 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3039 goto out;
3040 r = 0;
3041 vcpu->arch.mcg_cap = mcg_cap;
3042 /* Init IA32_MCG_CTL to all 1s */
3043 if (mcg_cap & MCG_CTL_P)
3044 vcpu->arch.mcg_ctl = ~(u64)0;
3045 /* Init IA32_MCi_CTL to all 1s */
3046 for (bank = 0; bank < bank_num; bank++)
3047 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3048
3049 if (kvm_x86_ops->setup_mce)
3050 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3051out:
3052 return r;
3053}
3054
3055static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3056 struct kvm_x86_mce *mce)
3057{
3058 u64 mcg_cap = vcpu->arch.mcg_cap;
3059 unsigned bank_num = mcg_cap & 0xff;
3060 u64 *banks = vcpu->arch.mce_banks;
3061
3062 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3063 return -EINVAL;
3064 /*
3065 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3066 * reporting is disabled
3067 */
3068 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3069 vcpu->arch.mcg_ctl != ~(u64)0)
3070 return 0;
3071 banks += 4 * mce->bank;
3072 /*
3073 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3074 * reporting is disabled for the bank
3075 */
3076 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3077 return 0;
3078 if (mce->status & MCI_STATUS_UC) {
3079 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3080 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3081 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3082 return 0;
3083 }
3084 if (banks[1] & MCI_STATUS_VAL)
3085 mce->status |= MCI_STATUS_OVER;
3086 banks[2] = mce->addr;
3087 banks[3] = mce->misc;
3088 vcpu->arch.mcg_status = mce->mcg_status;
3089 banks[1] = mce->status;
3090 kvm_queue_exception(vcpu, MC_VECTOR);
3091 } else if (!(banks[1] & MCI_STATUS_VAL)
3092 || !(banks[1] & MCI_STATUS_UC)) {
3093 if (banks[1] & MCI_STATUS_VAL)
3094 mce->status |= MCI_STATUS_OVER;
3095 banks[2] = mce->addr;
3096 banks[3] = mce->misc;
3097 banks[1] = mce->status;
3098 } else
3099 banks[1] |= MCI_STATUS_OVER;
3100 return 0;
3101}
3102
3cfc3092
JK		 3103static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3104 struct kvm_vcpu_events *events)
3105{
7460fb4a 3106 process_nmi(vcpu);
664f8e26
WL		 3107 /*
3108 * FIXME: pass injected and pending separately. This is only
3109 * needed for nested virtualization, whose state cannot be
3110 * migrated yet. For now we can combine them.
3111 */
03b82a30 3112 events->exception.injected =
664f8e26
WL		 3113 (vcpu->arch.exception.pending ||
3114 vcpu->arch.exception.injected) &&
03b82a30 3115 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3116 events->exception.nr = vcpu->arch.exception.nr;
3117 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3118 events->exception.pad = 0;
3cfc3092
JK		 3119 events->exception.error_code = vcpu->arch.exception.error_code;
3120
03b82a30
JK		 3121 events->interrupt.injected =
3122 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3123 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3124 events->interrupt.soft = 0;
37ccdcbe 3125 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3126
3127 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3128 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3129 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3130 events->nmi.pad = 0;
3cfc3092 3131
66450a21 3132 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3133
f077825a
PB		 3134 events->smi.smm = is_smm(vcpu);
3135 events->smi.pending = vcpu->arch.smi_pending;
3136 events->smi.smm_inside_nmi =
3137 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3138 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3139
dab4b911 3140 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3141 | KVM_VCPUEVENT_VALID_SHADOW
3142 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3143 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3144}
3145
6ef4e07e
XG		 3146static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3147
3cfc3092
JK		 3148static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3149 struct kvm_vcpu_events *events)
3150{
dab4b911 3151 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3152 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3153 | KVM_VCPUEVENT_VALID_SHADOW
3154 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3155 return -EINVAL;
3156
78e546c8 3157 if (events->exception.injected &&
28d06353
JM		 3158 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3159 is_guest_mode(vcpu)))
78e546c8
PB		 3160 return -EINVAL;
3161
28bf2888
DH		 3162 /* INITs are latched while in SMM */
3163 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3164 (events->smi.smm || events->smi.pending) &&
3165 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3166 return -EINVAL;
3167
7460fb4a 3168 process_nmi(vcpu);
664f8e26 3169 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3170 vcpu->arch.exception.pending = events->exception.injected;
3171 vcpu->arch.exception.nr = events->exception.nr;
3172 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3173 vcpu->arch.exception.error_code = events->exception.error_code;
3174
3175 vcpu->arch.interrupt.pending = events->interrupt.injected;
3176 vcpu->arch.interrupt.nr = events->interrupt.nr;
3177 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3178 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3179 kvm_x86_ops->set_interrupt_shadow(vcpu,
3180 events->interrupt.shadow);
3cfc3092
JK		 3181
3182 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3183 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3184 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3185 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3186
66450a21 3187 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3188 lapic_in_kernel(vcpu))
66450a21 3189 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3190
f077825a 3191 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3192 u32 hflags = vcpu->arch.hflags;
f077825a 3193 if (events->smi.smm)
6ef4e07e 3194 hflags |= HF_SMM_MASK;
f077825a 3195 else
6ef4e07e
XG		 3196 hflags &= ~HF_SMM_MASK;
3197 kvm_set_hflags(vcpu, hflags);
3198
f077825a 3199 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3200
3201 if (events->smi.smm) {
3202 if (events->smi.smm_inside_nmi)
3203 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3204 else
f4ef1910
WL		 3205 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3206 if (lapic_in_kernel(vcpu)) {
3207 if (events->smi.latched_init)
3208 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3209 else
3210 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3211 }
f077825a
PB		 3212 }
3213 }
3214
3842d135
AK		 3215 kvm_make_request(KVM_REQ_EVENT, vcpu);
3216
3cfc3092
JK		 3217 return 0;
3218}
3219
a1efbe77
JK		 3220static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3221 struct kvm_debugregs *dbgregs)
3222{
73aaf249
JK		 3223 unsigned long val;
3224
a1efbe77 3225 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3226 kvm_get_dr(vcpu, 6, &val);
73aaf249 3227 dbgregs->dr6 = val;
a1efbe77
JK		 3228 dbgregs->dr7 = vcpu->arch.dr7;
3229 dbgregs->flags = 0;
97e69aa6 3230 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3231}
3232
3233static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3234 struct kvm_debugregs *dbgregs)
3235{
3236 if (dbgregs->flags)
3237 return -EINVAL;
3238
d14bdb55
PB		 3239 if (dbgregs->dr6 & ~0xffffffffull)
3240 return -EINVAL;
3241 if (dbgregs->dr7 & ~0xffffffffull)
3242 return -EINVAL;
3243
a1efbe77 3244 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3245 kvm_update_dr0123(vcpu);
a1efbe77 3246 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3247 kvm_update_dr6(vcpu);
a1efbe77 3248 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3249 kvm_update_dr7(vcpu);
a1efbe77 3250
a1efbe77
JK		 3251 return 0;
3252}
3253
df1daba7
PB		 3254#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3255
3256static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3257{
c47ada30 3258 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3259 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3260 u64 valid;
3261
3262 /*
3263 * Copy legacy XSAVE area, to avoid complications with CPUID
3264 * leaves 0 and 1 in the loop below.
3265 */
3266 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3267
3268 /* Set XSTATE_BV */
00c87e9a 3269 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3270 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3271
3272 /*
3273 * Copy each region from the possibly compacted offset to the
3274 * non-compacted offset.
3275 */
d91cab78 3276 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3277 while (valid) {
3278 u64 feature = valid & -valid;
3279 int index = fls64(feature) - 1;
3280 void *src = get_xsave_addr(xsave, feature);
3281
3282 if (src) {
3283 u32 size, offset, ecx, edx;
3284 cpuid_count(XSTATE_CPUID, index,
3285 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3286 if (feature == XFEATURE_MASK_PKRU)
3287 memcpy(dest + offset, &vcpu->arch.pkru,
3288 sizeof(vcpu->arch.pkru));
3289 else
3290 memcpy(dest + offset, src, size);
3291
df1daba7
PB		 3292 }
3293
3294 valid -= feature;
3295 }
3296}
3297
3298static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3299{
c47ada30 3300 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3301 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3302 u64 valid;
3303
3304 /*
3305 * Copy legacy XSAVE area, to avoid complications with CPUID
3306 * leaves 0 and 1 in the loop below.
3307 */
3308 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3309
3310 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3311 xsave->header.xfeatures = xstate_bv;
782511b0 3312 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3313 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3314
3315 /*
3316 * Copy each region from the non-compacted offset to the
3317 * possibly compacted offset.
3318 */
d91cab78 3319 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3320 while (valid) {
3321 u64 feature = valid & -valid;
3322 int index = fls64(feature) - 1;
3323 void *dest = get_xsave_addr(xsave, feature);
3324
3325 if (dest) {
3326 u32 size, offset, ecx, edx;
3327 cpuid_count(XSTATE_CPUID, index,
3328 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3329 if (feature == XFEATURE_MASK_PKRU)
3330 memcpy(&vcpu->arch.pkru, src + offset,
3331 sizeof(vcpu->arch.pkru));
3332 else
3333 memcpy(dest, src + offset, size);
ee4100da 3334 }
df1daba7
PB		 3335
3336 valid -= feature;
3337 }
3338}
3339
2d5b5a66
SY		 3340static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3341 struct kvm_xsave *guest_xsave)
3342{
d366bf7e 3343 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3344 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3345 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3346 } else {
2d5b5a66 3347 memcpy(guest_xsave->region,
7366ed77 3348 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3349 sizeof(struct fxregs_state));
2d5b5a66 3350 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3351 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3352 }
3353}
3354
a575813b
WL		 3355#define XSAVE_MXCSR_OFFSET 24
3356
2d5b5a66
SY		 3357static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3358 struct kvm_xsave *guest_xsave)
3359{
3360 u64 xstate_bv =
3361 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3362 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3363
d366bf7e 3364 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3365 /*
3366 * Here we allow setting states that are not present in
3367 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3368 * with old userspace.
3369 */
a575813b
WL		 3370 if (xstate_bv & ~kvm_supported_xcr0() ||
3371 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3372 return -EINVAL;
df1daba7 3373 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3374 } else {
a575813b
WL		 3375 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3376 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3377 return -EINVAL;
7366ed77 3378 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3379 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3380 }
3381 return 0;
3382}
3383
3384static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3385 struct kvm_xcrs *guest_xcrs)
3386{
d366bf7e 3387 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3388 guest_xcrs->nr_xcrs = 0;
3389 return;
3390 }
3391
3392 guest_xcrs->nr_xcrs = 1;
3393 guest_xcrs->flags = 0;
3394 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3395 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3396}
3397
3398static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3399 struct kvm_xcrs *guest_xcrs)
3400{
3401 int i, r = 0;
3402
d366bf7e 3403 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3404 return -EINVAL;
3405
3406 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3407 return -EINVAL;
3408
3409 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3410 /* Only support XCR0 currently */
c67a04cb 3411 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3412 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3413 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3414 break;
3415 }
3416 if (r)
3417 r = -EINVAL;
3418 return r;
3419}
3420
1c0b28c2
EM		 3421/*
3422 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3423 * stopped by the hypervisor. This function will be called from the host only.
3424 * EINVAL is returned when the host attempts to set the flag for a guest that
3425 * does not support pv clocks.
3426 */
3427static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3428{
0b79459b 3429 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3430 return -EINVAL;
51d59c6b 3431 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3432 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3433 return 0;
3434}
3435
5c919412
AS		 3436static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3437 struct kvm_enable_cap *cap)
3438{
3439 if (cap->flags)
3440 return -EINVAL;
3441
3442 switch (cap->cap) {
efc479e6
RK		 3443 case KVM_CAP_HYPERV_SYNIC2:
3444 if (cap->args[0])
3445 return -EINVAL;
5c919412 3446 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3447 if (!irqchip_in_kernel(vcpu->kvm))
3448 return -EINVAL;
efc479e6
RK		 3449 return kvm_hv_activate_synic(vcpu, cap->cap ==
3450 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3451 default:
3452 return -EINVAL;
3453 }
3454}
3455
313a3dc7
CO		 3456long kvm_arch_vcpu_ioctl(struct file *filp,
3457 unsigned int ioctl, unsigned long arg)
3458{
3459 struct kvm_vcpu *vcpu = filp->private_data;
3460 void __user *argp = (void __user *)arg;
3461 int r;
d1ac91d8
AK		 3462 union {
3463 struct kvm_lapic_state *lapic;
3464 struct kvm_xsave *xsave;
3465 struct kvm_xcrs *xcrs;
3466 void *buffer;
3467 } u;
3468
3469 u.buffer = NULL;
313a3dc7
CO		 3470 switch (ioctl) {
3471 case KVM_GET_LAPIC: {
2204ae3c 3472 r = -EINVAL;
bce87cce 3473 if (!lapic_in_kernel(vcpu))
2204ae3c 3474 goto out;
d1ac91d8 3475 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3476
b772ff36 3477 r = -ENOMEM;
d1ac91d8 3478 if (!u.lapic)
b772ff36 3479 goto out;
d1ac91d8 3480 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3481 if (r)
3482 goto out;
3483 r = -EFAULT;
d1ac91d8 3484 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3485 goto out;
3486 r = 0;
3487 break;
3488 }
3489 case KVM_SET_LAPIC: {
2204ae3c 3490 r = -EINVAL;
bce87cce 3491 if (!lapic_in_kernel(vcpu))
2204ae3c 3492 goto out;
ff5c2c03 3493 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3494 if (IS_ERR(u.lapic))
3495 return PTR_ERR(u.lapic);
ff5c2c03 3496
d1ac91d8 3497 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3498 break;
3499 }
f77bc6a4
ZX		 3500 case KVM_INTERRUPT: {
3501 struct kvm_interrupt irq;
3502
3503 r = -EFAULT;
3504 if (copy_from_user(&irq, argp, sizeof irq))
3505 goto out;
3506 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3507 break;
3508 }
c4abb7c9
JK		 3509 case KVM_NMI: {
3510 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3511 break;
3512 }
f077825a
PB		 3513 case KVM_SMI: {
3514 r = kvm_vcpu_ioctl_smi(vcpu);
3515 break;
3516 }
313a3dc7
CO		 3517 case KVM_SET_CPUID: {
3518 struct kvm_cpuid __user *cpuid_arg = argp;
3519 struct kvm_cpuid cpuid;
3520
3521 r = -EFAULT;
3522 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3523 goto out;
3524 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3525 break;
3526 }
07716717
DK		 3527 case KVM_SET_CPUID2: {
3528 struct kvm_cpuid2 __user *cpuid_arg = argp;
3529 struct kvm_cpuid2 cpuid;
3530
3531 r = -EFAULT;
3532 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3533 goto out;
3534 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3535 cpuid_arg->entries);
07716717
DK		 3536 break;
3537 }
3538 case KVM_GET_CPUID2: {
3539 struct kvm_cpuid2 __user *cpuid_arg = argp;
3540 struct kvm_cpuid2 cpuid;
3541
3542 r = -EFAULT;
3543 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3544 goto out;
3545 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3546 cpuid_arg->entries);
07716717
DK		 3547 if (r)
3548 goto out;
3549 r = -EFAULT;
3550 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3551 goto out;
3552 r = 0;
3553 break;
3554 }
313a3dc7 3555 case KVM_GET_MSRS:
609e36d3 3556 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3557 break;
3558 case KVM_SET_MSRS:
3559 r = msr_io(vcpu, argp, do_set_msr, 0);
3560 break;
b209749f
AK		 3561 case KVM_TPR_ACCESS_REPORTING: {
3562 struct kvm_tpr_access_ctl tac;
3563
3564 r = -EFAULT;
3565 if (copy_from_user(&tac, argp, sizeof tac))
3566 goto out;
3567 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3568 if (r)
3569 goto out;
3570 r = -EFAULT;
3571 if (copy_to_user(argp, &tac, sizeof tac))
3572 goto out;
3573 r = 0;
3574 break;
3575 };
b93463aa
AK		 3576 case KVM_SET_VAPIC_ADDR: {
3577 struct kvm_vapic_addr va;
7301d6ab 3578 int idx;
b93463aa
AK		 3579
3580 r = -EINVAL;
35754c98 3581 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3582 goto out;
3583 r = -EFAULT;
3584 if (copy_from_user(&va, argp, sizeof va))
3585 goto out;
7301d6ab 3586 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3587 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3588 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3589 break;
3590 }
890ca9ae
HY		 3591 case KVM_X86_SETUP_MCE: {
3592 u64 mcg_cap;
3593
3594 r = -EFAULT;
3595 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3596 goto out;
3597 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3598 break;
3599 }
3600 case KVM_X86_SET_MCE: {
3601 struct kvm_x86_mce mce;
3602
3603 r = -EFAULT;
3604 if (copy_from_user(&mce, argp, sizeof mce))
3605 goto out;
3606 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3607 break;
3608 }
3cfc3092
JK		 3609 case KVM_GET_VCPU_EVENTS: {
3610 struct kvm_vcpu_events events;
3611
3612 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3613
3614 r = -EFAULT;
3615 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3616 break;
3617 r = 0;
3618 break;
3619 }
3620 case KVM_SET_VCPU_EVENTS: {
3621 struct kvm_vcpu_events events;
3622
3623 r = -EFAULT;
3624 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3625 break;
3626
3627 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3628 break;
3629 }
a1efbe77
JK		 3630 case KVM_GET_DEBUGREGS: {
3631 struct kvm_debugregs dbgregs;
3632
3633 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3634
3635 r = -EFAULT;
3636 if (copy_to_user(argp, &dbgregs,
3637 sizeof(struct kvm_debugregs)))
3638 break;
3639 r = 0;
3640 break;
3641 }
3642 case KVM_SET_DEBUGREGS: {
3643 struct kvm_debugregs dbgregs;
3644
3645 r = -EFAULT;
3646 if (copy_from_user(&dbgregs, argp,
3647 sizeof(struct kvm_debugregs)))
3648 break;
3649
3650 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3651 break;
3652 }
2d5b5a66 3653 case KVM_GET_XSAVE: {
d1ac91d8 3654 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3655 r = -ENOMEM;
d1ac91d8 3656 if (!u.xsave)
2d5b5a66
SY		 3657 break;
3658
d1ac91d8 3659 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3660
3661 r = -EFAULT;
d1ac91d8 3662 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3663 break;
3664 r = 0;
3665 break;
3666 }
3667 case KVM_SET_XSAVE: {
ff5c2c03 3668 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3669 if (IS_ERR(u.xsave))
3670 return PTR_ERR(u.xsave);
2d5b5a66 3671
d1ac91d8 3672 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3673 break;
3674 }
3675 case KVM_GET_XCRS: {
d1ac91d8 3676 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3677 r = -ENOMEM;
d1ac91d8 3678 if (!u.xcrs)
2d5b5a66
SY		 3679 break;
3680
d1ac91d8 3681 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3682
3683 r = -EFAULT;
d1ac91d8 3684 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3685 sizeof(struct kvm_xcrs)))
3686 break;
3687 r = 0;
3688 break;
3689 }
3690 case KVM_SET_XCRS: {
ff5c2c03 3691 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3692 if (IS_ERR(u.xcrs))
3693 return PTR_ERR(u.xcrs);
2d5b5a66 3694
d1ac91d8 3695 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3696 break;
3697 }
92a1f12d
JR		 3698 case KVM_SET_TSC_KHZ: {
3699 u32 user_tsc_khz;
3700
3701 r = -EINVAL;
92a1f12d
JR		 3702 user_tsc_khz = (u32)arg;
3703
3704 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3705 goto out;
3706
cc578287
ZA		 3707 if (user_tsc_khz == 0)
3708 user_tsc_khz = tsc_khz;
3709
381d585c
HZ		 3710 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3711 r = 0;
92a1f12d 3712
92a1f12d
JR		 3713 goto out;
3714 }
3715 case KVM_GET_TSC_KHZ: {
cc578287 3716 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3717 goto out;
3718 }
1c0b28c2
EM		 3719 case KVM_KVMCLOCK_CTRL: {
3720 r = kvm_set_guest_paused(vcpu);
3721 goto out;
3722 }
5c919412
AS		 3723 case KVM_ENABLE_CAP: {
3724 struct kvm_enable_cap cap;
3725
3726 r = -EFAULT;
3727 if (copy_from_user(&cap, argp, sizeof(cap)))
3728 goto out;
3729 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3730 break;
3731 }
313a3dc7
CO		 3732 default:
3733 r = -EINVAL;
3734 }
3735out:
d1ac91d8 3736 kfree(u.buffer);
313a3dc7
CO		 3737 return r;
3738}
3739
5b1c1493
CO		 3740int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3741{
3742 return VM_FAULT_SIGBUS;
3743}
3744
1fe779f8
CO		 3745static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3746{
3747 int ret;
3748
3749 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3750 return -EINVAL;
1fe779f8
CO		 3751 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3752 return ret;
3753}
3754
b927a3ce
SY		 3755static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3756 u64 ident_addr)
3757{
3758 kvm->arch.ept_identity_map_addr = ident_addr;
3759 return 0;
3760}
3761
1fe779f8
CO		 3762static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3763 u32 kvm_nr_mmu_pages)
3764{
3765 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3766 return -EINVAL;
3767
79fac95e 3768 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3769
3770 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3771 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3772
79fac95e 3773 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3774 return 0;
3775}
3776
3777static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3778{
39de71ec 3779 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3780}
3781
1fe779f8
CO		 3782static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3783{
90bca052 3784 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3785 int r;
3786
3787 r = 0;
3788 switch (chip->chip_id) {
3789 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3790 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3791 sizeof(struct kvm_pic_state));
3792 break;
3793 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3794 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3795 sizeof(struct kvm_pic_state));
3796 break;
3797 case KVM_IRQCHIP_IOAPIC:
33392b49 3798 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3799 break;
3800 default:
3801 r = -EINVAL;
3802 break;
3803 }
3804 return r;
3805}
3806
3807static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3808{
90bca052 3809 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3810 int r;
3811
3812 r = 0;
3813 switch (chip->chip_id) {
3814 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3815 spin_lock(&pic->lock);
3816 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3817 sizeof(struct kvm_pic_state));
90bca052 3818 spin_unlock(&pic->lock);
1fe779f8
CO		 3819 break;
3820 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3821 spin_lock(&pic->lock);
3822 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3823 sizeof(struct kvm_pic_state));
90bca052 3824 spin_unlock(&pic->lock);
1fe779f8
CO		 3825 break;
3826 case KVM_IRQCHIP_IOAPIC:
33392b49 3827 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3828 break;
3829 default:
3830 r = -EINVAL;
3831 break;
3832 }
90bca052 3833 kvm_pic_update_irq(pic);
1fe779f8
CO		 3834 return r;
3835}
3836
e0f63cb9
SY		 3837static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3838{
34f3941c
RK		 3839 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3840
3841 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3842
3843 mutex_lock(&kps->lock);
3844 memcpy(ps, &kps->channels, sizeof(*ps));
3845 mutex_unlock(&kps->lock);
2da29bcc 3846 return 0;
e0f63cb9
SY		 3847}
3848
3849static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3850{
0185604c 3851 int i;
09edea72
RK		 3852 struct kvm_pit *pit = kvm->arch.vpit;
3853
3854 mutex_lock(&pit->pit_state.lock);
34f3941c 3855 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3856 for (i = 0; i < 3; i++)
09edea72
RK		 3857 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3858 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3859 return 0;
e9f42757
BK		 3860}
3861
3862static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3863{
e9f42757
BK		 3864 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3865 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3866 sizeof(ps->channels));
3867 ps->flags = kvm->arch.vpit->pit_state.flags;
3868 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3869 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3870 return 0;
e9f42757
BK		 3871}
3872
3873static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3874{
2da29bcc 3875 int start = 0;
0185604c 3876 int i;
e9f42757 3877 u32 prev_legacy, cur_legacy;
09edea72
RK		 3878 struct kvm_pit *pit = kvm->arch.vpit;
3879
3880 mutex_lock(&pit->pit_state.lock);
3881 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3882 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3883 if (!prev_legacy && cur_legacy)
3884 start = 1;
09edea72
RK		 3885 memcpy(&pit->pit_state.channels, &ps->channels,
3886 sizeof(pit->pit_state.channels));
3887 pit->pit_state.flags = ps->flags;
0185604c 3888 for (i = 0; i < 3; i++)
09edea72 3889 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3890 start && i == 0);
09edea72 3891 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3892 return 0;
e0f63cb9
SY		 3893}
3894
52d939a0
MT		 3895static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3896 struct kvm_reinject_control *control)
3897{
71474e2f
RK		 3898 struct kvm_pit *pit = kvm->arch.vpit;
3899
3900 if (!pit)
52d939a0 3901 return -ENXIO;
b39c90b6 3902
71474e2f
RK		 3903 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3904 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3905 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3906 */
3907 mutex_lock(&pit->pit_state.lock);
3908 kvm_pit_set_reinject(pit, control->pit_reinject);
3909 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3910
52d939a0
MT		 3911 return 0;
3912}
3913
95d4c16c 3914/**
60c34612
TY		 3915 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3916 * @kvm: kvm instance
3917 * @log: slot id and address to which we copy the log
95d4c16c 3918 *
e108ff2f
PB		 3919 * Steps 1-4 below provide general overview of dirty page logging. See
3920 * kvm_get_dirty_log_protect() function description for additional details.
3921 *
3922 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3923 * always flush the TLB (step 4) even if previous step failed and the dirty
3924 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3925 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3926 * writes will be marked dirty for next log read.
95d4c16c 3927 *
60c34612
TY		 3928 * 1. Take a snapshot of the bit and clear it if needed.
3929 * 2. Write protect the corresponding page.
e108ff2f
PB		 3930 * 3. Copy the snapshot to the userspace.
3931 * 4. Flush TLB's if needed.
5bb064dc 3932 */
60c34612 3933int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3934{
60c34612 3935 bool is_dirty = false;
e108ff2f 3936 int r;
5bb064dc 3937
79fac95e 3938 mutex_lock(&kvm->slots_lock);
5bb064dc 3939
88178fd4
KH		 3940 /*
3941 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3942 */
3943 if (kvm_x86_ops->flush_log_dirty)
3944 kvm_x86_ops->flush_log_dirty(kvm);
3945
e108ff2f 3946 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3947
3948 /*
3949 * All the TLBs can be flushed out of mmu lock, see the comments in
3950 * kvm_mmu_slot_remove_write_access().
3951 */
e108ff2f 3952 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3953 if (is_dirty)
3954 kvm_flush_remote_tlbs(kvm);
3955
79fac95e 3956 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3957 return r;
3958}
3959
aa2fbe6d
YZ		 3960int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3961 bool line_status)
23d43cf9
CD		 3962{
3963 if (!irqchip_in_kernel(kvm))
3964 return -ENXIO;
3965
3966 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3967 irq_event->irq, irq_event->level,
3968 line_status);
23d43cf9
CD		 3969 return 0;
3970}
3971
90de4a18
NA		 3972static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3973 struct kvm_enable_cap *cap)
3974{
3975 int r;
3976
3977 if (cap->flags)
3978 return -EINVAL;
3979
3980 switch (cap->cap) {
3981 case KVM_CAP_DISABLE_QUIRKS:
3982 kvm->arch.disabled_quirks = cap->args[0];
3983 r = 0;
3984 break;
49df6397
SR		 3985 case KVM_CAP_SPLIT_IRQCHIP: {
3986 mutex_lock(&kvm->lock);
b053b2ae
SR		 3987 r = -EINVAL;
3988 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3989 goto split_irqchip_unlock;
49df6397
SR		 3990 r = -EEXIST;
3991 if (irqchip_in_kernel(kvm))
3992 goto split_irqchip_unlock;
557abc40 3993 if (kvm->created_vcpus)
49df6397
SR		 3994 goto split_irqchip_unlock;
3995 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3996 if (r)
49df6397
SR		 3997 goto split_irqchip_unlock;
3998 /* Pairs with irqchip_in_kernel. */
3999 smp_wmb();
49776faf 4000 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4001 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4002 r = 0;
4003split_irqchip_unlock:
4004 mutex_unlock(&kvm->lock);
4005 break;
4006 }
37131313
RK		 4007 case KVM_CAP_X2APIC_API:
4008 r = -EINVAL;
4009 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4010 break;
4011
4012 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4013 kvm->arch.x2apic_format = true;
c519265f
RK		 4014 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4015 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4016
4017 r = 0;
4018 break;
90de4a18
NA		 4019 default:
4020 r = -EINVAL;
4021 break;
4022 }
4023 return r;
4024}
4025
1fe779f8
CO		 4026long kvm_arch_vm_ioctl(struct file *filp,
4027 unsigned int ioctl, unsigned long arg)
4028{
4029 struct kvm *kvm = filp->private_data;
4030 void __user *argp = (void __user *)arg;
367e1319 4031 int r = -ENOTTY;
f0d66275
DH		 4032 /*
4033 * This union makes it completely explicit to gcc-3.x
4034 * that these two variables' stack usage should be
4035 * combined, not added together.
4036 */
4037 union {
4038 struct kvm_pit_state ps;
e9f42757 4039 struct kvm_pit_state2 ps2;
c5ff41ce 4040 struct kvm_pit_config pit_config;
f0d66275 4041 } u;
1fe779f8
CO		 4042
4043 switch (ioctl) {
4044 case KVM_SET_TSS_ADDR:
4045 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4046 break;
b927a3ce
SY		 4047 case KVM_SET_IDENTITY_MAP_ADDR: {
4048 u64 ident_addr;
4049
4050 r = -EFAULT;
4051 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4052 goto out;
4053 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4054 break;
4055 }
1fe779f8
CO		 4056 case KVM_SET_NR_MMU_PAGES:
4057 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4058 break;
4059 case KVM_GET_NR_MMU_PAGES:
4060 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4061 break;
3ddea128 4062 case KVM_CREATE_IRQCHIP: {
3ddea128 4063 mutex_lock(&kvm->lock);
09941366 4064
3ddea128 4065 r = -EEXIST;
35e6eaa3 4066 if (irqchip_in_kernel(kvm))
3ddea128 4067 goto create_irqchip_unlock;
09941366 4068
3e515705 4069 r = -EINVAL;
557abc40 4070 if (kvm->created_vcpus)
3e515705 4071 goto create_irqchip_unlock;
09941366
RK		 4072
4073 r = kvm_pic_init(kvm);
4074 if (r)
3ddea128 4075 goto create_irqchip_unlock;
09941366
RK		 4076
4077 r = kvm_ioapic_init(kvm);
4078 if (r) {
09941366 4079 kvm_pic_destroy(kvm);
3ddea128 4080 goto create_irqchip_unlock;
09941366
RK		 4081 }
4082
399ec807
AK		 4083 r = kvm_setup_default_irq_routing(kvm);
4084 if (r) {
72bb2fcd 4085 kvm_ioapic_destroy(kvm);
09941366 4086 kvm_pic_destroy(kvm);
71ba994c 4087 goto create_irqchip_unlock;
399ec807 4088 }
49776faf 4089 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4090 smp_wmb();
49776faf 4091 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4092 create_irqchip_unlock:
4093 mutex_unlock(&kvm->lock);
1fe779f8 4094 break;
3ddea128 4095 }
7837699f 4096 case KVM_CREATE_PIT:
c5ff41ce
JK		 4097 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4098 goto create_pit;
4099 case KVM_CREATE_PIT2:
4100 r = -EFAULT;
4101 if (copy_from_user(&u.pit_config, argp,
4102 sizeof(struct kvm_pit_config)))
4103 goto out;
4104 create_pit:
250715a6 4105 mutex_lock(&kvm->lock);
269e05e4
AK		 4106 r = -EEXIST;
4107 if (kvm->arch.vpit)
4108 goto create_pit_unlock;
7837699f 4109 r = -ENOMEM;
c5ff41ce 4110 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4111 if (kvm->arch.vpit)
4112 r = 0;
269e05e4 4113 create_pit_unlock:
250715a6 4114 mutex_unlock(&kvm->lock);
7837699f 4115 break;
1fe779f8
CO		 4116 case KVM_GET_IRQCHIP: {
4117 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4118 struct kvm_irqchip *chip;
1fe779f8 4119
ff5c2c03
SL		 4120 chip = memdup_user(argp, sizeof(*chip));
4121 if (IS_ERR(chip)) {
4122 r = PTR_ERR(chip);
1fe779f8 4123 goto out;
ff5c2c03
SL		 4124 }
4125
1fe779f8 4126 r = -ENXIO;
826da321 4127 if (!irqchip_kernel(kvm))
f0d66275
DH		 4128 goto get_irqchip_out;
4129 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4130 if (r)
f0d66275 4131 goto get_irqchip_out;
1fe779f8 4132 r = -EFAULT;
f0d66275
DH		 4133 if (copy_to_user(argp, chip, sizeof *chip))
4134 goto get_irqchip_out;
1fe779f8 4135 r = 0;
f0d66275
DH		 4136 get_irqchip_out:
4137 kfree(chip);
1fe779f8
CO		 4138 break;
4139 }
4140 case KVM_SET_IRQCHIP: {
4141 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4142 struct kvm_irqchip *chip;
1fe779f8 4143
ff5c2c03
SL		 4144 chip = memdup_user(argp, sizeof(*chip));
4145 if (IS_ERR(chip)) {
4146 r = PTR_ERR(chip);
1fe779f8 4147 goto out;
ff5c2c03
SL		 4148 }
4149
1fe779f8 4150 r = -ENXIO;
826da321 4151 if (!irqchip_kernel(kvm))
f0d66275
DH		 4152 goto set_irqchip_out;
4153 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4154 if (r)
f0d66275 4155 goto set_irqchip_out;
1fe779f8 4156 r = 0;
f0d66275
DH		 4157 set_irqchip_out:
4158 kfree(chip);
1fe779f8
CO		 4159 break;
4160 }
e0f63cb9 4161 case KVM_GET_PIT: {
e0f63cb9 4162 r = -EFAULT;
f0d66275 4163 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4164 goto out;
4165 r = -ENXIO;
4166 if (!kvm->arch.vpit)
4167 goto out;
f0d66275 4168 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4169 if (r)
4170 goto out;
4171 r = -EFAULT;
f0d66275 4172 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4173 goto out;
4174 r = 0;
4175 break;
4176 }
4177 case KVM_SET_PIT: {
e0f63cb9 4178 r = -EFAULT;
f0d66275 4179 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4180 goto out;
4181 r = -ENXIO;
4182 if (!kvm->arch.vpit)
4183 goto out;
f0d66275 4184 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4185 break;
4186 }
e9f42757
BK		 4187 case KVM_GET_PIT2: {
4188 r = -ENXIO;
4189 if (!kvm->arch.vpit)
4190 goto out;
4191 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4192 if (r)
4193 goto out;
4194 r = -EFAULT;
4195 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4196 goto out;
4197 r = 0;
4198 break;
4199 }
4200 case KVM_SET_PIT2: {
4201 r = -EFAULT;
4202 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4203 goto out;
4204 r = -ENXIO;
4205 if (!kvm->arch.vpit)
4206 goto out;
4207 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4208 break;
4209 }
52d939a0
MT		 4210 case KVM_REINJECT_CONTROL: {
4211 struct kvm_reinject_control control;
4212 r = -EFAULT;
4213 if (copy_from_user(&control, argp, sizeof(control)))
4214 goto out;
4215 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4216 break;
4217 }
d71ba788
PB		 4218 case KVM_SET_BOOT_CPU_ID:
4219 r = 0;
4220 mutex_lock(&kvm->lock);
557abc40 4221 if (kvm->created_vcpus)
d71ba788
PB		 4222 r = -EBUSY;
4223 else
4224 kvm->arch.bsp_vcpu_id = arg;
4225 mutex_unlock(&kvm->lock);
4226 break;
ffde22ac 4227 case KVM_XEN_HVM_CONFIG: {
8e40eae1 4228 struct kvm_xen_hvm_config xhc;
ffde22ac 4229 r = -EFAULT;
8e40eae1 4230 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4231 goto out;
4232 r = -EINVAL;
8e40eae1 4233 if (xhc.flags)
ffde22ac 4234 goto out;
8e40eae1 4235 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4236 r = 0;
4237 break;
4238 }
afbcf7ab 4239 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4240 struct kvm_clock_data user_ns;
4241 u64 now_ns;
afbcf7ab
GC		 4242
4243 r = -EFAULT;
4244 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4245 goto out;
4246
4247 r = -EINVAL;
4248 if (user_ns.flags)
4249 goto out;
4250
4251 r = 0;
0bc48bea
RK		 4252 /*
4253 * TODO: userspace has to take care of races with VCPU_RUN, so
4254 * kvm_gen_update_masterclock() can be cut down to locked
4255 * pvclock_update_vm_gtod_copy().
4256 */
4257 kvm_gen_update_masterclock(kvm);
e891a32e 4258 now_ns = get_kvmclock_ns(kvm);
108b249c 4259 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4260 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4261 break;
4262 }
4263 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4264 struct kvm_clock_data user_ns;
4265 u64 now_ns;
4266
e891a32e 4267 now_ns = get_kvmclock_ns(kvm);
108b249c 4268 user_ns.clock = now_ns;
e3fd9a93 4269 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4270 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4271
4272 r = -EFAULT;
4273 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4274 goto out;
4275 r = 0;
4276 break;
4277 }
90de4a18
NA		 4278 case KVM_ENABLE_CAP: {
4279 struct kvm_enable_cap cap;
afbcf7ab 4280
90de4a18
NA		 4281 r = -EFAULT;
4282 if (copy_from_user(&cap, argp, sizeof(cap)))
4283 goto out;
4284 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4285 break;
4286 }
1fe779f8 4287 default:
ad6260da 4288 r = -ENOTTY;
1fe779f8
CO		 4289 }
4290out:
4291 return r;
4292}
4293
a16b043c 4294static void kvm_init_msr_list(void)
043405e1
CO		 4295{
4296 u32 dummy[2];
4297 unsigned i, j;
4298
62ef68bb 4299 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4300 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4301 continue;
93c4adc7
PB		 4302
4303 /*
4304 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4305 * to the guests in some cases.
93c4adc7
PB		 4306 */
4307 switch (msrs_to_save[i]) {
4308 case MSR_IA32_BNDCFGS:
4309 if (!kvm_x86_ops->mpx_supported())
4310 continue;
4311 break;
9dbe6cf9
PB		 4312 case MSR_TSC_AUX:
4313 if (!kvm_x86_ops->rdtscp_supported())
4314 continue;
4315 break;
93c4adc7
PB		 4316 default:
4317 break;
4318 }
4319
043405e1
CO		 4320 if (j < i)
4321 msrs_to_save[j] = msrs_to_save[i];
4322 j++;
4323 }
4324 num_msrs_to_save = j;
62ef68bb
PB		 4325
4326 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4327 switch (emulated_msrs[i]) {
6d396b55
PB		 4328 case MSR_IA32_SMBASE:
4329 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4330 continue;
4331 break;
62ef68bb
PB		 4332 default:
4333 break;
4334 }
4335
4336 if (j < i)
4337 emulated_msrs[j] = emulated_msrs[i];
4338 j++;
4339 }
4340 num_emulated_msrs = j;
043405e1
CO		 4341}
4342
bda9020e
MT		 4343static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4344 const void *v)
bbd9b64e 4345{
70252a10
AK		 4346 int handled = 0;
4347 int n;
4348
4349 do {
4350 n = min(len, 8);
bce87cce 4351 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4352 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4353 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4354 break;
4355 handled += n;
4356 addr += n;
4357 len -= n;
4358 v += n;
4359 } while (len);
bbd9b64e 4360
70252a10 4361 return handled;
bbd9b64e
CO		 4362}
4363
bda9020e 4364static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4365{
70252a10
AK		 4366 int handled = 0;
4367 int n;
4368
4369 do {
4370 n = min(len, 8);
bce87cce 4371 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4372 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4373 addr, n, v))
4374 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4375 break;
653c41ac 4376 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4377 handled += n;
4378 addr += n;
4379 len -= n;
4380 v += n;
4381 } while (len);
bbd9b64e 4382
70252a10 4383 return handled;
bbd9b64e
CO		 4384}
4385
2dafc6c2
GN		 4386static void kvm_set_segment(struct kvm_vcpu *vcpu,
4387 struct kvm_segment *var, int seg)
4388{
4389 kvm_x86_ops->set_segment(vcpu, var, seg);
4390}
4391
4392void kvm_get_segment(struct kvm_vcpu *vcpu,
4393 struct kvm_segment *var, int seg)
4394{
4395 kvm_x86_ops->get_segment(vcpu, var, seg);
4396}
4397
54987b7a
PB		 4398gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4399 struct x86_exception *exception)
02f59dc9
JR		 4400{
4401 gpa_t t_gpa;
02f59dc9
JR		 4402
4403 BUG_ON(!mmu_is_nested(vcpu));
4404
4405 /* NPT walks are always user-walks */
4406 access |= PFERR_USER_MASK;
54987b7a 4407 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4408
4409 return t_gpa;
4410}
4411
ab9ae313
AK		 4412gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4413 struct x86_exception *exception)
1871c602
GN		 4414{
4415 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4416 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4417}
4418
ab9ae313
AK		 4419 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4420 struct x86_exception *exception)
1871c602
GN		 4421{
4422 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4423 access |= PFERR_FETCH_MASK;
ab9ae313 4424 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4425}
4426
ab9ae313
AK		 4427gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4428 struct x86_exception *exception)
1871c602
GN		 4429{
4430 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4431 access |= PFERR_WRITE_MASK;
ab9ae313 4432 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4433}
4434
4435/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4436gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4437 struct x86_exception *exception)
1871c602 4438{
ab9ae313 4439 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4440}
4441
4442static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4443 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4444 struct x86_exception *exception)
bbd9b64e
CO		 4445{
4446 void *data = val;
10589a46 4447 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4448
4449 while (bytes) {
14dfe855 4450 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4451 exception);
bbd9b64e 4452 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4453 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4454 int ret;
4455
bcc55cba 4456 if (gpa == UNMAPPED_GVA)
ab9ae313 4457 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4458 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4459 offset, toread);
10589a46 4460 if (ret < 0) {
c3cd7ffa 4461 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4462 goto out;
4463 }
bbd9b64e 4464
77c2002e
IE		 4465 bytes -= toread;
4466 data += toread;
4467 addr += toread;
bbd9b64e 4468 }
10589a46 4469out:
10589a46 4470 return r;
bbd9b64e 4471}
77c2002e 4472
1871c602 4473/* used for instruction fetching */
0f65dd70
AK		 4474static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4475 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4476 struct x86_exception *exception)
1871c602 4477{
0f65dd70 4478 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4479 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4480 unsigned offset;
4481 int ret;
0f65dd70 4482
44583cba
PB		 4483 /* Inline kvm_read_guest_virt_helper for speed. */
4484 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4485 exception);
4486 if (unlikely(gpa == UNMAPPED_GVA))
4487 return X86EMUL_PROPAGATE_FAULT;
4488
4489 offset = addr & (PAGE_SIZE-1);
4490 if (WARN_ON(offset + bytes > PAGE_SIZE))
4491 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4492 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4493 offset, bytes);
44583cba
PB		 4494 if (unlikely(ret < 0))
4495 return X86EMUL_IO_NEEDED;
4496
4497 return X86EMUL_CONTINUE;
1871c602
GN		 4498}
4499
064aea77 4500int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4501 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4502 struct x86_exception *exception)
1871c602 4503{
0f65dd70 4504 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4505 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4506
1871c602 4507 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4508 exception);
1871c602 4509}
064aea77 4510EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4511
0f65dd70
AK		 4512static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4513 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4514 struct x86_exception *exception)
1871c602 4515{
0f65dd70 4516 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4517 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4518}
4519
7a036a6f
RK		 4520static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4521 unsigned long addr, void *val, unsigned int bytes)
4522{
4523 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4524 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4525
4526 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4527}
4528
6a4d7550 4529int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4530 gva_t addr, void *val,
2dafc6c2 4531 unsigned int bytes,
bcc55cba 4532 struct x86_exception *exception)
77c2002e 4533{
0f65dd70 4534 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4535 void *data = val;
4536 int r = X86EMUL_CONTINUE;
4537
4538 while (bytes) {
14dfe855
JR		 4539 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4540 PFERR_WRITE_MASK,
ab9ae313 4541 exception);
77c2002e
IE		 4542 unsigned offset = addr & (PAGE_SIZE-1);
4543 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4544 int ret;
4545
bcc55cba 4546 if (gpa == UNMAPPED_GVA)
ab9ae313 4547 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4548 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4549 if (ret < 0) {
c3cd7ffa 4550 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4551 goto out;
4552 }
4553
4554 bytes -= towrite;
4555 data += towrite;
4556 addr += towrite;
4557 }
4558out:
4559 return r;
4560}
6a4d7550 4561EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4562
0f89b207
TL		 4563static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4564 gpa_t gpa, bool write)
4565{
4566 /* For APIC access vmexit */
4567 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4568 return 1;
4569
4570 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4571 trace_vcpu_match_mmio(gva, gpa, write, true);
4572 return 1;
4573 }
4574
4575 return 0;
4576}
4577
af7cc7d1
XG		 4578static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4579 gpa_t *gpa, struct x86_exception *exception,
4580 bool write)
4581{
97d64b78
AK		 4582 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4583 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4584
be94f6b7
HH		 4585 /*
4586 * currently PKRU is only applied to ept enabled guest so
4587 * there is no pkey in EPT page table for L1 guest or EPT
4588 * shadow page table for L2 guest.
4589 */
97d64b78 4590 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4591 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4592 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4593 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4594 (gva & (PAGE_SIZE - 1));
4f022648 4595 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4596 return 1;
4597 }
4598
af7cc7d1
XG		 4599 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4600
4601 if (*gpa == UNMAPPED_GVA)
4602 return -1;
4603
0f89b207 4604 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4605}
4606
3200f405 4607int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4608 const void *val, int bytes)
bbd9b64e
CO		 4609{
4610 int ret;
4611
54bf36aa 4612 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4613 if (ret < 0)
bbd9b64e 4614 return 0;
0eb05bf2 4615 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4616 return 1;
4617}
4618
77d197b2
XG		 4619struct read_write_emulator_ops {
4620 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4621 int bytes);
4622 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4623 void *val, int bytes);
4624 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4625 int bytes, void *val);
4626 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4627 void *val, int bytes);
4628 bool write;
4629};
4630
4631static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4632{
4633 if (vcpu->mmio_read_completed) {
77d197b2 4634 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
653c41ac 4635 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4636 vcpu->mmio_read_completed = 0;
4637 return 1;
4638 }
4639
4640 return 0;
4641}
4642
4643static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4644 void *val, int bytes)
4645{
54bf36aa 4646 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4647}
4648
4649static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4650 void *val, int bytes)
4651{
4652 return emulator_write_phys(vcpu, gpa, val, bytes);
4653}
4654
4655static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4656{
653c41ac 4657 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4658 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4659}
4660
4661static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4662 void *val, int bytes)
4663{
653c41ac 4664 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4665 return X86EMUL_IO_NEEDED;
4666}
4667
4668static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4669 void *val, int bytes)
4670{
f78146b0
AK		 4671 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4672
87da7e66 4673 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4674 return X86EMUL_CONTINUE;
4675}
4676
0fbe9b0b 4677static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4678 .read_write_prepare = read_prepare,
4679 .read_write_emulate = read_emulate,
4680 .read_write_mmio = vcpu_mmio_read,
4681 .read_write_exit_mmio = read_exit_mmio,
4682};
4683
0fbe9b0b 4684static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4685 .read_write_emulate = write_emulate,
4686 .read_write_mmio = write_mmio,
4687 .read_write_exit_mmio = write_exit_mmio,
4688 .write = true,
4689};
4690
22388a3c
XG		 4691static int emulator_read_write_onepage(unsigned long addr, void *val,
4692 unsigned int bytes,
4693 struct x86_exception *exception,
4694 struct kvm_vcpu *vcpu,
0fbe9b0b 4695 const struct read_write_emulator_ops *ops)
bbd9b64e 4696{
af7cc7d1
XG		 4697 gpa_t gpa;
4698 int handled, ret;
22388a3c 4699 bool write = ops->write;
f78146b0 4700 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4701 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4702
4703 /*
4704 * If the exit was due to a NPF we may already have a GPA.
4705 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4706 * Note, this cannot be used on string operations since string
4707 * operation using rep will only have the initial GPA from the NPF
4708 * occurred.
4709 */
4710 if (vcpu->arch.gpa_available &&
4711 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4712 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4713 gpa = vcpu->arch.gpa_val;
4714 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4715 } else {
4716 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4717 if (ret < 0)
4718 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4719 }
10589a46 4720
618232e2 4721 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4722 return X86EMUL_CONTINUE;
4723
bbd9b64e
CO		 4724 /*
4725 * Is this MMIO handled locally?
4726 */
22388a3c 4727 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4728 if (handled == bytes)
bbd9b64e 4729 return X86EMUL_CONTINUE;
bbd9b64e 4730
70252a10
AK		 4731 gpa += handled;
4732 bytes -= handled;
4733 val += handled;
4734
87da7e66
XG		 4735 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4736 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4737 frag->gpa = gpa;
4738 frag->data = val;
4739 frag->len = bytes;
f78146b0 4740 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4741}
4742
52eb5a6d
XL		 4743static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4744 unsigned long addr,
22388a3c
XG		 4745 void *val, unsigned int bytes,
4746 struct x86_exception *exception,
0fbe9b0b 4747 const struct read_write_emulator_ops *ops)
bbd9b64e 4748{
0f65dd70 4749 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4750 gpa_t gpa;
4751 int rc;
4752
4753 if (ops->read_write_prepare &&
4754 ops->read_write_prepare(vcpu, val, bytes))
4755 return X86EMUL_CONTINUE;
4756
4757 vcpu->mmio_nr_fragments = 0;
0f65dd70 4758
bbd9b64e
CO		 4759 /* Crossing a page boundary? */
4760 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4761 int now;
bbd9b64e
CO		 4762
4763 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4764 rc = emulator_read_write_onepage(addr, val, now, exception,
4765 vcpu, ops);
4766
bbd9b64e
CO		 4767 if (rc != X86EMUL_CONTINUE)
4768 return rc;
4769 addr += now;
bac15531
NA		 4770 if (ctxt->mode != X86EMUL_MODE_PROT64)
4771 addr = (u32)addr;
bbd9b64e
CO		 4772 val += now;
4773 bytes -= now;
4774 }
22388a3c 4775
f78146b0
AK		 4776 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4777 vcpu, ops);
4778 if (rc != X86EMUL_CONTINUE)
4779 return rc;
4780
4781 if (!vcpu->mmio_nr_fragments)
4782 return rc;
4783
4784 gpa = vcpu->mmio_fragments[0].gpa;
4785
4786 vcpu->mmio_needed = 1;
4787 vcpu->mmio_cur_fragment = 0;
4788
87da7e66 4789 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4790 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4791 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4792 vcpu->run->mmio.phys_addr = gpa;
4793
4794 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4795}
4796
4797static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4798 unsigned long addr,
4799 void *val,
4800 unsigned int bytes,
4801 struct x86_exception *exception)
4802{
4803 return emulator_read_write(ctxt, addr, val, bytes,
4804 exception, &read_emultor);
4805}
4806
52eb5a6d 4807static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4808 unsigned long addr,
4809 const void *val,
4810 unsigned int bytes,
4811 struct x86_exception *exception)
4812{
4813 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4814 exception, &write_emultor);
bbd9b64e 4815}
bbd9b64e 4816
daea3e73
AK		 4817#define CMPXCHG_TYPE(t, ptr, old, new) \
4818 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4819
4820#ifdef CONFIG_X86_64
4821# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4822#else
4823# define CMPXCHG64(ptr, old, new) \
9749a6c0 4824 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4825#endif
4826
0f65dd70
AK		 4827static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4828 unsigned long addr,
bbd9b64e
CO		 4829 const void *old,
4830 const void *new,
4831 unsigned int bytes,
0f65dd70 4832 struct x86_exception *exception)
bbd9b64e 4833{
0f65dd70 4834 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4835 gpa_t gpa;
4836 struct page *page;
4837 char *kaddr;
4838 bool exchanged;
2bacc55c 4839
daea3e73
AK		 4840 /* guests cmpxchg8b have to be emulated atomically */
4841 if (bytes > 8 || (bytes & (bytes - 1)))
4842 goto emul_write;
10589a46 4843
daea3e73 4844 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4845
daea3e73
AK		 4846 if (gpa == UNMAPPED_GVA ||
4847 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4848 goto emul_write;
2bacc55c 4849
daea3e73
AK		 4850 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4851 goto emul_write;
72dc67a6 4852
54bf36aa 4853 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4854 if (is_error_page(page))
c19b8bd6 4855 goto emul_write;
72dc67a6 4856
8fd75e12 4857 kaddr = kmap_atomic(page);
daea3e73
AK		 4858 kaddr += offset_in_page(gpa);
4859 switch (bytes) {
4860 case 1:
4861 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4862 break;
4863 case 2:
4864 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4865 break;
4866 case 4:
4867 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4868 break;
4869 case 8:
4870 exchanged = CMPXCHG64(kaddr, old, new);
4871 break;
4872 default:
4873 BUG();
2bacc55c 4874 }
8fd75e12 4875 kunmap_atomic(kaddr);
daea3e73
AK		 4876 kvm_release_page_dirty(page);
4877
4878 if (!exchanged)
4879 return X86EMUL_CMPXCHG_FAILED;
4880
54bf36aa 4881 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4882 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4883
4884 return X86EMUL_CONTINUE;
4a5f48f6 4885
3200f405 4886emul_write:
daea3e73 4887 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4888
0f65dd70 4889 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4890}
4891
cf8f70bf
GN		 4892static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4893{
cbfc6c91 4894 int r = 0, i;
cf8f70bf 4895
cbfc6c91
WL		 4896 for (i = 0; i < vcpu->arch.pio.count; i++) {
4897 if (vcpu->arch.pio.in)
4898 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4899 vcpu->arch.pio.size, pd);
4900 else
4901 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4902 vcpu->arch.pio.port, vcpu->arch.pio.size,
4903 pd);
4904 if (r)
4905 break;
4906 pd += vcpu->arch.pio.size;
4907 }
cf8f70bf
GN		 4908 return r;
4909}
4910
6f6fbe98
XG		 4911static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4912 unsigned short port, void *val,
4913 unsigned int count, bool in)
cf8f70bf 4914{
cf8f70bf 4915 vcpu->arch.pio.port = port;
6f6fbe98 4916 vcpu->arch.pio.in = in;
7972995b 4917 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4918 vcpu->arch.pio.size = size;
4919
4920 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4921 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4922 return 1;
4923 }
4924
4925 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4926 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4927 vcpu->run->io.size = size;
4928 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4929 vcpu->run->io.count = count;
4930 vcpu->run->io.port = port;
4931
4932 return 0;
4933}
4934
6f6fbe98
XG		 4935static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4936 int size, unsigned short port, void *val,
4937 unsigned int count)
cf8f70bf 4938{
ca1d4a9e 4939 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4940 int ret;
ca1d4a9e 4941
6f6fbe98
XG		 4942 if (vcpu->arch.pio.count)
4943 goto data_avail;
cf8f70bf 4944
cbfc6c91
WL		 4945 memset(vcpu->arch.pio_data, 0, size * count);
4946
6f6fbe98
XG		 4947 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4948 if (ret) {
4949data_avail:
4950 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4951 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4952 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4953 return 1;
4954 }
4955
cf8f70bf
GN		 4956 return 0;
4957}
4958
6f6fbe98
XG		 4959static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4960 int size, unsigned short port,
4961 const void *val, unsigned int count)
4962{
4963 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4964
4965 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4966 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4967 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4968}
4969
bbd9b64e
CO		 4970static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4971{
4972 return kvm_x86_ops->get_segment_base(vcpu, seg);
4973}
4974
3cb16fe7 4975static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4976{
3cb16fe7 4977 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4978}
4979
ae6a2375 4980static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4981{
4982 if (!need_emulate_wbinvd(vcpu))
4983 return X86EMUL_CONTINUE;
4984
4985 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4986 int cpu = get_cpu();
4987
4988 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4989 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4990 wbinvd_ipi, NULL, 1);
2eec7343 4991 put_cpu();
f5f48ee1 4992 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4993 } else
4994 wbinvd();
f5f48ee1
SY		 4995 return X86EMUL_CONTINUE;
4996}
5cb56059
JS		 4997
4998int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4999{
6affcbed
KH		 5000 kvm_emulate_wbinvd_noskip(vcpu);
5001 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5002}
f5f48ee1
SY		 5003EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5004
5cb56059
JS		 5005
5006
bcaf5cc5
AK		 5007static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5008{
5cb56059 5009 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5010}
5011
52eb5a6d
XL		 5012static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5013 unsigned long *dest)
bbd9b64e 5014{
16f8a6f9 5015 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5016}
5017
52eb5a6d
XL		 5018static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5019 unsigned long value)
bbd9b64e 5020{
338dbc97 5021
717746e3 5022 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5023}
5024
52a46617 5025static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5026{
52a46617 5027 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5028}
5029
717746e3 5030static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5031{
717746e3 5032 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5033 unsigned long value;
5034
5035 switch (cr) {
5036 case 0:
5037 value = kvm_read_cr0(vcpu);
5038 break;
5039 case 2:
5040 value = vcpu->arch.cr2;
5041 break;
5042 case 3:
9f8fe504 5043 value = kvm_read_cr3(vcpu);
52a46617
GN		 5044 break;
5045 case 4:
5046 value = kvm_read_cr4(vcpu);
5047 break;
5048 case 8:
5049 value = kvm_get_cr8(vcpu);
5050 break;
5051 default:
a737f256 5052 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5053 return 0;
5054 }
5055
5056 return value;
5057}
5058
717746e3 5059static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5060{
717746e3 5061 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5062 int res = 0;
5063
52a46617
GN		 5064 switch (cr) {
5065 case 0:
49a9b07e 5066 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5067 break;
5068 case 2:
5069 vcpu->arch.cr2 = val;
5070 break;
5071 case 3:
2390218b 5072 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5073 break;
5074 case 4:
a83b29c6 5075 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5076 break;
5077 case 8:
eea1cff9 5078 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5079 break;
5080 default:
a737f256 5081 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5082 res = -1;
52a46617 5083 }
0f12244f
GN		 5084
5085 return res;
52a46617
GN		 5086}
5087
717746e3 5088static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5089{
717746e3 5090 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5091}
5092
4bff1e86 5093static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5094{
4bff1e86 5095 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5096}
5097
4bff1e86 5098static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5099{
4bff1e86 5100 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5101}
5102
1ac9d0cf
AK		 5103static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5104{
5105 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5106}
5107
5108static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5109{
5110 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5111}
5112
4bff1e86
AK		 5113static unsigned long emulator_get_cached_segment_base(
5114 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5115{
4bff1e86 5116 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5117}
5118
1aa36616
AK		 5119static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5120 struct desc_struct *desc, u32 *base3,
5121 int seg)
2dafc6c2
GN		 5122{
5123 struct kvm_segment var;
5124
4bff1e86 5125 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5126 *selector = var.selector;
2dafc6c2 5127
378a8b09
GN		 5128 if (var.unusable) {
5129 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5130 if (base3)
5131 *base3 = 0;
2dafc6c2 5132 return false;
378a8b09 5133 }
2dafc6c2
GN		 5134
5135 if (var.g)
5136 var.limit >>= 12;
5137 set_desc_limit(desc, var.limit);
5138 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5139#ifdef CONFIG_X86_64
5140 if (base3)
5141 *base3 = var.base >> 32;
5142#endif
2dafc6c2
GN		 5143 desc->type = var.type;
5144 desc->s = var.s;
5145 desc->dpl = var.dpl;
5146 desc->p = var.present;
5147 desc->avl = var.avl;
5148 desc->l = var.l;
5149 desc->d = var.db;
5150 desc->g = var.g;
5151
5152 return true;
5153}
5154
1aa36616
AK		 5155static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5156 struct desc_struct *desc, u32 base3,
5157 int seg)
2dafc6c2 5158{
4bff1e86 5159 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5160 struct kvm_segment var;
5161
1aa36616 5162 var.selector = selector;
2dafc6c2 5163 var.base = get_desc_base(desc);
5601d05b
GN		 5164#ifdef CONFIG_X86_64
5165 var.base |= ((u64)base3) << 32;
5166#endif
2dafc6c2
GN		 5167 var.limit = get_desc_limit(desc);
5168 if (desc->g)
5169 var.limit = (var.limit << 12) | 0xfff;
5170 var.type = desc->type;
2dafc6c2
GN		 5171 var.dpl = desc->dpl;
5172 var.db = desc->d;
5173 var.s = desc->s;
5174 var.l = desc->l;
5175 var.g = desc->g;
5176 var.avl = desc->avl;
5177 var.present = desc->p;
5178 var.unusable = !var.present;
5179 var.padding = 0;
5180
5181 kvm_set_segment(vcpu, &var, seg);
5182 return;
5183}
5184
717746e3
AK		 5185static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5186 u32 msr_index, u64 *pdata)
5187{
609e36d3
PB		 5188 struct msr_data msr;
5189 int r;
5190
5191 msr.index = msr_index;
5192 msr.host_initiated = false;
5193 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5194 if (r)
5195 return r;
5196
5197 *pdata = msr.data;
5198 return 0;
717746e3
AK		 5199}
5200
5201static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5202 u32 msr_index, u64 data)
5203{
8fe8ab46
WA		 5204 struct msr_data msr;
5205
5206 msr.data = data;
5207 msr.index = msr_index;
5208 msr.host_initiated = false;
5209 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5210}
5211
64d60670
PB		 5212static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5213{
5214 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5215
5216 return vcpu->arch.smbase;
5217}
5218
5219static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5220{
5221 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5222
5223 vcpu->arch.smbase = smbase;
5224}
5225
67f4d428
NA		 5226static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5227 u32 pmc)
5228{
c6702c9d 5229 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5230}
5231
222d21aa
AK		 5232static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5233 u32 pmc, u64 *pdata)
5234{
c6702c9d 5235 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5236}
5237
6c3287f7
AK		 5238static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5239{
5240 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5241}
5242
5037f6f3
AK		 5243static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5244{
5245 preempt_disable();
5197b808 5246 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5247}
5248
5249static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5250{
5251 preempt_enable();
5252}
5253
2953538e 5254static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5255 struct x86_instruction_info *info,
c4f035c6
AK		 5256 enum x86_intercept_stage stage)
5257{
2953538e 5258 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5259}
5260
e911eb3b
YZ		 5261static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5262 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5263{
e911eb3b 5264 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5265}
5266
dd856efa
AK		 5267static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5268{
5269 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5270}
5271
5272static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5273{
5274 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5275}
5276
801806d9
NA		 5277static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5278{
5279 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5280}
5281
6ed071f0
LP		 5282static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5283{
5284 return emul_to_vcpu(ctxt)->arch.hflags;
5285}
5286
5287static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5288{
5289 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5290}
5291
0225fb50 5292static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5293 .read_gpr = emulator_read_gpr,
5294 .write_gpr = emulator_write_gpr,
1871c602 5295 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5296 .write_std = kvm_write_guest_virt_system,
7a036a6f 5297 .read_phys = kvm_read_guest_phys_system,
1871c602 5298 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5299 .read_emulated = emulator_read_emulated,
5300 .write_emulated = emulator_write_emulated,
5301 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5302 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5303 .pio_in_emulated = emulator_pio_in_emulated,
5304 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5305 .get_segment = emulator_get_segment,
5306 .set_segment = emulator_set_segment,
5951c442 5307 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5308 .get_gdt = emulator_get_gdt,
160ce1f1 5309 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5310 .set_gdt = emulator_set_gdt,
5311 .set_idt = emulator_set_idt,
52a46617
GN		 5312 .get_cr = emulator_get_cr,
5313 .set_cr = emulator_set_cr,
9c537244 5314 .cpl = emulator_get_cpl,
35aa5375
GN		 5315 .get_dr = emulator_get_dr,
5316 .set_dr = emulator_set_dr,
64d60670
PB		 5317 .get_smbase = emulator_get_smbase,
5318 .set_smbase = emulator_set_smbase,
717746e3
AK		 5319 .set_msr = emulator_set_msr,
5320 .get_msr = emulator_get_msr,
67f4d428 5321 .check_pmc = emulator_check_pmc,
222d21aa 5322 .read_pmc = emulator_read_pmc,
6c3287f7 5323 .halt = emulator_halt,
bcaf5cc5 5324 .wbinvd = emulator_wbinvd,
d6aa1000 5325 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5326 .get_fpu = emulator_get_fpu,
5327 .put_fpu = emulator_put_fpu,
c4f035c6 5328 .intercept = emulator_intercept,
bdb42f5a 5329 .get_cpuid = emulator_get_cpuid,
801806d9 5330 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5331 .get_hflags = emulator_get_hflags,
5332 .set_hflags = emulator_set_hflags,
bbd9b64e
CO		 5333};
5334
95cb2295
GN		 5335static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5336{
37ccdcbe 5337 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5338 /*
5339 * an sti; sti; sequence only disable interrupts for the first
5340 * instruction. So, if the last instruction, be it emulated or
5341 * not, left the system with the INT_STI flag enabled, it
5342 * means that the last instruction is an sti. We should not
5343 * leave the flag on in this case. The same goes for mov ss
5344 */
37ccdcbe
PB		 5345 if (int_shadow & mask)
5346 mask = 0;
6addfc42 5347 if (unlikely(int_shadow || mask)) {
95cb2295 5348 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5349 if (!mask)
5350 kvm_make_request(KVM_REQ_EVENT, vcpu);
5351 }
95cb2295
GN		 5352}
5353
ef54bcfe 5354static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5355{
5356 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5357 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5358 return kvm_propagate_fault(vcpu, &ctxt->exception);
5359
5360 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5361 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5362 ctxt->exception.error_code);
54b8486f 5363 else
da9cb575 5364 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5365 return false;
54b8486f
GN		 5366}
5367
8ec4722d
MG		 5368static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5369{
adf52235 5370 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5371 int cs_db, cs_l;
5372
8ec4722d
MG		 5373 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5374
adf52235 5375 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5376 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5377
adf52235
TY		 5378 ctxt->eip = kvm_rip_read(vcpu);
5379 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5380 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5381 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5382 cs_db ? X86EMUL_MODE_PROT32 :
5383 X86EMUL_MODE_PROT16;
a584539b 5384 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5385 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5386 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5387
dd856efa 5388 init_decode_cache(ctxt);
7ae441ea 5389 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5390}
5391
71f9833b 5392int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5393{
9d74191a 5394 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5395 int ret;
5396
5397 init_emulate_ctxt(vcpu);
5398
9dac77fa
AK		 5399 ctxt->op_bytes = 2;
5400 ctxt->ad_bytes = 2;
5401 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5402 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5403
5404 if (ret != X86EMUL_CONTINUE)
5405 return EMULATE_FAIL;
5406
9dac77fa 5407 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5408 kvm_rip_write(vcpu, ctxt->eip);
5409 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5410
5411 if (irq == NMI_VECTOR)
7460fb4a 5412 vcpu->arch.nmi_pending = 0;
63995653
MG		 5413 else
5414 vcpu->arch.interrupt.pending = false;
5415
5416 return EMULATE_DONE;
5417}
5418EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5419
6d77dbfc
GN		 5420static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5421{
fc3a9157
JR		 5422 int r = EMULATE_DONE;
5423
6d77dbfc
GN		 5424 ++vcpu->stat.insn_emulation_fail;
5425 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5426 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5427 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5428 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5429 vcpu->run->internal.ndata = 0;
fbd81f09 5430 r = EMULATE_USER_EXIT;
fc3a9157 5431 }
6d77dbfc 5432 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5433
5434 return r;
6d77dbfc
GN		 5435}
5436
93c05d3e 5437static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5438 bool write_fault_to_shadow_pgtable,
5439 int emulation_type)
a6f177ef 5440{
95b3cf69 5441 gpa_t gpa = cr2;
ba049e93 5442 kvm_pfn_t pfn;
a6f177ef 5443
991eebf9
GN		 5444 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5445 return false;
5446
95b3cf69
XG		 5447 if (!vcpu->arch.mmu.direct_map) {
5448 /*
5449 * Write permission should be allowed since only
5450 * write access need to be emulated.
5451 */
5452 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5453
95b3cf69
XG		 5454 /*
5455 * If the mapping is invalid in guest, let cpu retry
5456 * it to generate fault.
5457 */
5458 if (gpa == UNMAPPED_GVA)
5459 return true;
5460 }
a6f177ef 5461
8e3d9d06
XG		 5462 /*
5463 * Do not retry the unhandleable instruction if it faults on the
5464 * readonly host memory, otherwise it will goto a infinite loop:
5465 * retry instruction -> write #PF -> emulation fail -> retry
5466 * instruction -> ...
5467 */
5468 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5469
5470 /*
5471 * If the instruction failed on the error pfn, it can not be fixed,
5472 * report the error to userspace.
5473 */
5474 if (is_error_noslot_pfn(pfn))
5475 return false;
5476
5477 kvm_release_pfn_clean(pfn);
5478
5479 /* The instructions are well-emulated on direct mmu. */
5480 if (vcpu->arch.mmu.direct_map) {
5481 unsigned int indirect_shadow_pages;
5482
5483 spin_lock(&vcpu->kvm->mmu_lock);
5484 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5485 spin_unlock(&vcpu->kvm->mmu_lock);
5486
5487 if (indirect_shadow_pages)
5488 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5489
a6f177ef 5490 return true;
8e3d9d06 5491 }
a6f177ef 5492
95b3cf69
XG		 5493 /*
5494 * if emulation was due to access to shadowed page table
5495 * and it failed try to unshadow page and re-enter the
5496 * guest to let CPU execute the instruction.
5497 */
5498 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5499
5500 /*
5501 * If the access faults on its page table, it can not
5502 * be fixed by unprotecting shadow page and it should
5503 * be reported to userspace.
5504 */
5505 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5506}
5507
1cb3f3ae
XG		 5508static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5509 unsigned long cr2, int emulation_type)
5510{
5511 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5512 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5513
5514 last_retry_eip = vcpu->arch.last_retry_eip;
5515 last_retry_addr = vcpu->arch.last_retry_addr;
5516
5517 /*
5518 * If the emulation is caused by #PF and it is non-page_table
5519 * writing instruction, it means the VM-EXIT is caused by shadow
5520 * page protected, we can zap the shadow page and retry this
5521 * instruction directly.
5522 *
5523 * Note: if the guest uses a non-page-table modifying instruction
5524 * on the PDE that points to the instruction, then we will unmap
5525 * the instruction and go to an infinite loop. So, we cache the
5526 * last retried eip and the last fault address, if we meet the eip
5527 * and the address again, we can break out of the potential infinite
5528 * loop.
5529 */
5530 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5531
5532 if (!(emulation_type & EMULTYPE_RETRY))
5533 return false;
5534
5535 if (x86_page_table_writing_insn(ctxt))
5536 return false;
5537
5538 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5539 return false;
5540
5541 vcpu->arch.last_retry_eip = ctxt->eip;
5542 vcpu->arch.last_retry_addr = cr2;
5543
5544 if (!vcpu->arch.mmu.direct_map)
5545 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5546
22368028 5547 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5548
5549 return true;
5550}
5551
716d51ab
GN		 5552static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5553static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5554
64d60670 5555static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5556{
64d60670 5557 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5558 /* This is a good place to trace that we are exiting SMM. */
5559 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5560
c43203ca
PB		 5561 /* Process a latched INIT or SMI, if any. */
5562 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5563 }
699023e2
PB		 5564
5565 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5566}
5567
5568static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5569{
5570 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5571
a584539b 5572 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5573
5574 if (changed & HF_SMM_MASK)
5575 kvm_smm_changed(vcpu);
a584539b
PB		 5576}
5577
4a1e10d5
PB		 5578static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5579 unsigned long *db)
5580{
5581 u32 dr6 = 0;
5582 int i;
5583 u32 enable, rwlen;
5584
5585 enable = dr7;
5586 rwlen = dr7 >> 16;
5587 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5588 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5589 dr6 |= (1 << i);
5590 return dr6;
5591}
5592
c8401dda 5593static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5594{
5595 struct kvm_run *kvm_run = vcpu->run;
5596
c8401dda
PB		 5597 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5598 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5599 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5600 kvm_run->debug.arch.exception = DB_VECTOR;
5601 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5602 *r = EMULATE_USER_EXIT;
5603 } else {
5604 /*
5605 * "Certain debug exceptions may clear bit 0-3. The
5606 * remaining contents of the DR6 register are never
5607 * cleared by the processor".
5608 */
5609 vcpu->arch.dr6 &= ~15;
5610 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5611 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5612 }
5613}
5614
6affcbed
KH		 5615int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5616{
5617 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5618 int r = EMULATE_DONE;
5619
5620 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5621
5622 /*
5623 * rflags is the old, "raw" value of the flags. The new value has
5624 * not been saved yet.
5625 *
5626 * This is correct even for TF set by the guest, because "the
5627 * processor will not generate this exception after the instruction
5628 * that sets the TF flag".
5629 */
5630 if (unlikely(rflags & X86_EFLAGS_TF))
5631 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5632 return r == EMULATE_DONE;
5633}
5634EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5635
4a1e10d5
PB		 5636static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5637{
4a1e10d5
PB		 5638 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5639 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5640 struct kvm_run *kvm_run = vcpu->run;
5641 unsigned long eip = kvm_get_linear_rip(vcpu);
5642 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5643 vcpu->arch.guest_debug_dr7,
5644 vcpu->arch.eff_db);
5645
5646 if (dr6 != 0) {
6f43ed01 5647 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5648 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5649 kvm_run->debug.arch.exception = DB_VECTOR;
5650 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5651 *r = EMULATE_USER_EXIT;
5652 return true;
5653 }
5654 }
5655
4161a569
NA		 5656 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5657 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5658 unsigned long eip = kvm_get_linear_rip(vcpu);
5659 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5660 vcpu->arch.dr7,
5661 vcpu->arch.db);
5662
5663 if (dr6 != 0) {
5664 vcpu->arch.dr6 &= ~15;
6f43ed01 5665 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5666 kvm_queue_exception(vcpu, DB_VECTOR);
5667 *r = EMULATE_DONE;
5668 return true;
5669 }
5670 }
5671
5672 return false;
5673}
5674
51d8b661
AP		 5675int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5676 unsigned long cr2,
dc25e89e
AP		 5677 int emulation_type,
5678 void *insn,
5679 int insn_len)
bbd9b64e 5680{
95cb2295 5681 int r;
9d74191a 5682 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5683 bool writeback = true;
93c05d3e 5684 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5685
93c05d3e
XG		 5686 /*
5687 * Clear write_fault_to_shadow_pgtable here to ensure it is
5688 * never reused.
5689 */
5690 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5691 kvm_clear_exception_queue(vcpu);
8d7d8102 5692
571008da 5693 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5694 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5695
5696 /*
5697 * We will reenter on the same instruction since
5698 * we do not set complete_userspace_io. This does not
5699 * handle watchpoints yet, those would be handled in
5700 * the emulate_ops.
5701 */
cc0600da
VK		 5702 if (!(emulation_type & EMULTYPE_SKIP) &&
5703 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 5704 return r;
5705
9d74191a
TY		 5706 ctxt->interruptibility = 0;
5707 ctxt->have_exception = false;
e0ad0b47 5708 ctxt->exception.vector = -1;
9d74191a 5709 ctxt->perm_ok = false;
bbd9b64e 5710
b51e974f 5711 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5712
9d74191a 5713 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5714
e46479f8 5715 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5716 ++vcpu->stat.insn_emulation;
1d2887e2 5717 if (r != EMULATION_OK) {
4005996e
AK		 5718 if (emulation_type & EMULTYPE_TRAP_UD)
5719 return EMULATE_FAIL;
991eebf9
GN		 5720 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5721 emulation_type))
bbd9b64e 5722 return EMULATE_DONE;
bb98bd97
PB		 5723 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5724 return EMULATE_DONE;
6d77dbfc
GN		 5725 if (emulation_type & EMULTYPE_SKIP)
5726 return EMULATE_FAIL;
5727 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5728 }
5729 }
5730
ba8afb6b 5731 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5732 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5733 if (ctxt->eflags & X86_EFLAGS_RF)
5734 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5735 return EMULATE_DONE;
5736 }
5737
1cb3f3ae
XG		 5738 if (retry_instruction(ctxt, cr2, emulation_type))
5739 return EMULATE_DONE;
5740
7ae441ea 5741 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5742 changes registers values during IO operation */
7ae441ea
GN		 5743 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5744 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5745 emulator_invalidate_register_cache(ctxt);
7ae441ea 5746 }
4d2179e1 5747
5cd21917 5748restart:
0f89b207
TL		 5749 /* Save the faulting GPA (cr2) in the address field */
5750 ctxt->exception.address = cr2;
5751
9d74191a 5752 r = x86_emulate_insn(ctxt);
bbd9b64e 5753
775fde86
JR		 5754 if (r == EMULATION_INTERCEPTED)
5755 return EMULATE_DONE;
5756
d2ddd1c4 5757 if (r == EMULATION_FAILED) {
991eebf9
GN		 5758 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5759 emulation_type))
c3cd7ffa
GN		 5760 return EMULATE_DONE;
5761
6d77dbfc 5762 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5763 }
5764
9d74191a 5765 if (ctxt->have_exception) {
d2ddd1c4 5766 r = EMULATE_DONE;
ef54bcfe
PB		 5767 if (inject_emulated_exception(vcpu))
5768 return r;
d2ddd1c4 5769 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5770 if (!vcpu->arch.pio.in) {
5771 /* FIXME: return into emulator if single-stepping. */
3457e419 5772 vcpu->arch.pio.count = 0;
0912c977 5773 } else {
7ae441ea 5774 writeback = false;
716d51ab
GN		 5775 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5776 }
ac0a48c3 5777 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5778 } else if (vcpu->mmio_needed) {
5779 if (!vcpu->mmio_is_write)
5780 writeback = false;
ac0a48c3 5781 r = EMULATE_USER_EXIT;
716d51ab 5782 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5783 } else if (r == EMULATION_RESTART)
5cd21917 5784 goto restart;
d2ddd1c4
GN		 5785 else
5786 r = EMULATE_DONE;
f850e2e6 5787
7ae441ea 5788 if (writeback) {
6addfc42 5789 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5790 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5791 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5792 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5793 if (r == EMULATE_DONE &&
5794 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5795 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5796 if (!ctxt->have_exception ||
5797 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5798 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5799
5800 /*
5801 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5802 * do nothing, and it will be requested again as soon as
5803 * the shadow expires. But we still need to check here,
5804 * because POPF has no interrupt shadow.
5805 */
5806 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5807 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5808 } else
5809 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5810
5811 return r;
de7d789a 5812}
51d8b661 5813EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5814
cf8f70bf 5815int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5816{
cf8f70bf 5817 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5818 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5819 size, port, &val, 1);
cf8f70bf 5820 /* do not return to emulator after return from userspace */
7972995b 5821 vcpu->arch.pio.count = 0;
de7d789a
CO		 5822 return ret;
5823}
cf8f70bf 5824EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5825
8370c3d0
TL		 5826static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5827{
5828 unsigned long val;
5829
5830 /* We should only ever be called with arch.pio.count equal to 1 */
5831 BUG_ON(vcpu->arch.pio.count != 1);
5832
5833 /* For size less than 4 we merge, else we zero extend */
5834 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5835 : 0;
5836
5837 /*
5838 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5839 * the copy and tracing
5840 */
5841 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5842 vcpu->arch.pio.port, &val, 1);
5843 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5844
5845 return 1;
5846}
5847
5848int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5849{
5850 unsigned long val;
5851 int ret;
5852
5853 /* For size less than 4 we merge, else we zero extend */
5854 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5855
5856 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5857 &val, 1);
5858 if (ret) {
5859 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5860 return ret;
5861 }
5862
5863 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5864
5865 return 0;
5866}
5867EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5868
251a5fd6 5869static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5870{
0a3aee0d 5871 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5872 return 0;
8cfdc000
ZA		 5873}
5874
5875static void tsc_khz_changed(void *data)
c8076604 5876{
8cfdc000
ZA		 5877 struct cpufreq_freqs *freq = data;
5878 unsigned long khz = 0;
5879
5880 if (data)
5881 khz = freq->new;
5882 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5883 khz = cpufreq_quick_get(raw_smp_processor_id());
5884 if (!khz)
5885 khz = tsc_khz;
0a3aee0d 5886 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5887}
5888
c8076604
GH		 5889static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5890 void *data)
5891{
5892 struct cpufreq_freqs *freq = data;
5893 struct kvm *kvm;
5894 struct kvm_vcpu *vcpu;
5895 int i, send_ipi = 0;
5896
8cfdc000
ZA		 5897 /*
5898 * We allow guests to temporarily run on slowing clocks,
5899 * provided we notify them after, or to run on accelerating
5900 * clocks, provided we notify them before. Thus time never
5901 * goes backwards.
5902 *
5903 * However, we have a problem. We can't atomically update
5904 * the frequency of a given CPU from this function; it is
5905 * merely a notifier, which can be called from any CPU.
5906 * Changing the TSC frequency at arbitrary points in time
5907 * requires a recomputation of local variables related to
5908 * the TSC for each VCPU. We must flag these local variables
5909 * to be updated and be sure the update takes place with the
5910 * new frequency before any guests proceed.
5911 *
5912 * Unfortunately, the combination of hotplug CPU and frequency
5913 * change creates an intractable locking scenario; the order
5914 * of when these callouts happen is undefined with respect to
5915 * CPU hotplug, and they can race with each other. As such,
5916 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5917 * undefined; you can actually have a CPU frequency change take
5918 * place in between the computation of X and the setting of the
5919 * variable. To protect against this problem, all updates of
5920 * the per_cpu tsc_khz variable are done in an interrupt
5921 * protected IPI, and all callers wishing to update the value
5922 * must wait for a synchronous IPI to complete (which is trivial
5923 * if the caller is on the CPU already). This establishes the
5924 * necessary total order on variable updates.
5925 *
5926 * Note that because a guest time update may take place
5927 * anytime after the setting of the VCPU's request bit, the
5928 * correct TSC value must be set before the request. However,
5929 * to ensure the update actually makes it to any guest which
5930 * starts running in hardware virtualization between the set
5931 * and the acquisition of the spinlock, we must also ping the
5932 * CPU after setting the request bit.
5933 *
5934 */
5935
c8076604
GH		 5936 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5937 return 0;
5938 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5939 return 0;
8cfdc000
ZA		 5940
5941 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5942
2f303b74 5943 spin_lock(&kvm_lock);
c8076604 5944 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5945 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5946 if (vcpu->cpu != freq->cpu)
5947 continue;
c285545f 5948 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5949 if (vcpu->cpu != smp_processor_id())
8cfdc000 5950 send_ipi = 1;
c8076604
GH		 5951 }
5952 }
2f303b74 5953 spin_unlock(&kvm_lock);
c8076604
GH		 5954
5955 if (freq->old < freq->new && send_ipi) {
5956 /*
5957 * We upscale the frequency. Must make the guest
5958 * doesn't see old kvmclock values while running with
5959 * the new frequency, otherwise we risk the guest sees
5960 * time go backwards.
5961 *
5962 * In case we update the frequency for another cpu
5963 * (which might be in guest context) send an interrupt
5964 * to kick the cpu out of guest context. Next time
5965 * guest context is entered kvmclock will be updated,
5966 * so the guest will not see stale values.
5967 */
8cfdc000 5968 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5969 }
5970 return 0;
5971}
5972
5973static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5974 .notifier_call = kvmclock_cpufreq_notifier
5975};
5976
251a5fd6 5977static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5978{
251a5fd6
SAS		 5979 tsc_khz_changed(NULL);
5980 return 0;
8cfdc000
ZA		 5981}
5982
b820cc0c
ZA		 5983static void kvm_timer_init(void)
5984{
c285545f 5985 max_tsc_khz = tsc_khz;
460dd42e 5986
b820cc0c 5987 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5988#ifdef CONFIG_CPU_FREQ
5989 struct cpufreq_policy policy;
758f588d
BP		 5990 int cpu;
5991
c285545f 5992 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5993 cpu = get_cpu();
5994 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5995 if (policy.cpuinfo.max_freq)
5996 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5997 put_cpu();
c285545f 5998#endif
b820cc0c
ZA		 5999 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6000 CPUFREQ_TRANSITION_NOTIFIER);
6001 }
c285545f 6002 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6003
73c1b41e 6004 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6005 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6006}
6007
ff9d07a0
ZY		 6008static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6009
f5132b01 6010int kvm_is_in_guest(void)
ff9d07a0 6011{
086c9855 6012 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6013}
6014
6015static int kvm_is_user_mode(void)
6016{
6017 int user_mode = 3;
dcf46b94 6018
086c9855
AS		 6019 if (__this_cpu_read(current_vcpu))
6020 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6021
ff9d07a0
ZY		 6022 return user_mode != 0;
6023}
6024
6025static unsigned long kvm_get_guest_ip(void)
6026{
6027 unsigned long ip = 0;
dcf46b94 6028
086c9855
AS		 6029 if (__this_cpu_read(current_vcpu))
6030 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6031
ff9d07a0
ZY		 6032 return ip;
6033}
6034
6035static struct perf_guest_info_callbacks kvm_guest_cbs = {
6036 .is_in_guest = kvm_is_in_guest,
6037 .is_user_mode = kvm_is_user_mode,
6038 .get_guest_ip = kvm_get_guest_ip,
6039};
6040
6041void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6042{
086c9855 6043 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6044}
6045EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6046
6047void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6048{
086c9855 6049 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6050}
6051EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6052
ce88decf
XG		 6053static void kvm_set_mmio_spte_mask(void)
6054{
6055 u64 mask;
6056 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6057
6058 /*
6059 * Set the reserved bits and the present bit of an paging-structure
6060 * entry to generate page fault with PFER.RSV = 1.
6061 */
885032b9 6062 /* Mask the reserved physical address bits. */
d1431483 6063 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6064
885032b9 6065 /* Set the present bit. */
ce88decf
XG		 6066 mask |= 1ull;
6067
6068#ifdef CONFIG_X86_64
6069 /*
6070 * If reserved bit is not supported, clear the present bit to disable
6071 * mmio page fault.
6072 */
6073 if (maxphyaddr == 52)
6074 mask &= ~1ull;
6075#endif
6076
dcdca5fe 6077 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6078}
6079
16e8d74d
MT		 6080#ifdef CONFIG_X86_64
6081static void pvclock_gtod_update_fn(struct work_struct *work)
6082{
d828199e
MT		 6083 struct kvm *kvm;
6084
6085 struct kvm_vcpu *vcpu;
6086 int i;
6087
2f303b74 6088 spin_lock(&kvm_lock);
d828199e
MT		 6089 list_for_each_entry(kvm, &vm_list, vm_list)
6090 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6091 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6092 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6093 spin_unlock(&kvm_lock);
16e8d74d
MT		 6094}
6095
6096static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6097
6098/*
6099 * Notification about pvclock gtod data update.
6100 */
6101static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6102 void *priv)
6103{
6104 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6105 struct timekeeper *tk = priv;
6106
6107 update_pvclock_gtod(tk);
6108
6109 /* disable master clock if host does not trust, or does not
6110 * use, TSC clocksource
6111 */
6112 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6113 atomic_read(&kvm_guest_has_master_clock) != 0)
6114 queue_work(system_long_wq, &pvclock_gtod_work);
6115
6116 return 0;
6117}
6118
6119static struct notifier_block pvclock_gtod_notifier = {
6120 .notifier_call = pvclock_gtod_notify,
6121};
6122#endif
6123
f8c16bba 6124int kvm_arch_init(void *opaque)
043405e1 6125{
b820cc0c 6126 int r;
6b61edf7 6127 struct kvm_x86_ops *ops = opaque;
f8c16bba 6128
f8c16bba
ZX		 6129 if (kvm_x86_ops) {
6130 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6131 r = -EEXIST;
6132 goto out;
f8c16bba
ZX		 6133 }
6134
6135 if (!ops->cpu_has_kvm_support()) {
6136 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6137 r = -EOPNOTSUPP;
6138 goto out;
f8c16bba
ZX		 6139 }
6140 if (ops->disabled_by_bios()) {
6141 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6142 r = -EOPNOTSUPP;
6143 goto out;
f8c16bba
ZX		 6144 }
6145
013f6a5d
MT		 6146 r = -ENOMEM;
6147 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6148 if (!shared_msrs) {
6149 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6150 goto out;
6151 }
6152
97db56ce
AK		 6153 r = kvm_mmu_module_init();
6154 if (r)
013f6a5d 6155 goto out_free_percpu;
97db56ce 6156
ce88decf 6157 kvm_set_mmio_spte_mask();
97db56ce 6158
f8c16bba 6159 kvm_x86_ops = ops;
920c8377 6160
7b52345e 6161 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6162 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6163 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6164 kvm_timer_init();
c8076604 6165
ff9d07a0
ZY		 6166 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6167
d366bf7e 6168 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6169 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6170
c5cc421b 6171 kvm_lapic_init();
16e8d74d
MT		 6172#ifdef CONFIG_X86_64
6173 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6174#endif
6175
f8c16bba 6176 return 0;
56c6d28a 6177
013f6a5d
MT		 6178out_free_percpu:
6179 free_percpu(shared_msrs);
56c6d28a 6180out:
56c6d28a 6181 return r;
043405e1 6182}
8776e519 6183
f8c16bba
ZX		 6184void kvm_arch_exit(void)
6185{
cef84c30 6186 kvm_lapic_exit();
ff9d07a0
ZY		 6187 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6188
888d256e
JK		 6189 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6190 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6191 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6192 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6193#ifdef CONFIG_X86_64
6194 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6195#endif
f8c16bba 6196 kvm_x86_ops = NULL;
56c6d28a 6197 kvm_mmu_module_exit();
013f6a5d 6198 free_percpu(shared_msrs);
56c6d28a 6199}
f8c16bba 6200
5cb56059 6201int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6202{
6203 ++vcpu->stat.halt_exits;
35754c98 6204 if (lapic_in_kernel(vcpu)) {
a4535290 6205 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6206 return 1;
6207 } else {
6208 vcpu->run->exit_reason = KVM_EXIT_HLT;
6209 return 0;
6210 }
6211}
5cb56059
JS		 6212EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6213
6214int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6215{
6affcbed
KH		 6216 int ret = kvm_skip_emulated_instruction(vcpu);
6217 /*
6218 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6219 * KVM_EXIT_DEBUG here.
6220 */
6221 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6222}
8776e519
HB		 6223EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6224
8ef81a9a 6225#ifdef CONFIG_X86_64
55dd00a7
MT		 6226static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6227 unsigned long clock_type)
6228{
6229 struct kvm_clock_pairing clock_pairing;
6230 struct timespec ts;
80fbd89c 6231 u64 cycle;
55dd00a7
MT		 6232 int ret;
6233
6234 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6235 return -KVM_EOPNOTSUPP;
6236
6237 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6238 return -KVM_EOPNOTSUPP;
6239
6240 clock_pairing.sec = ts.tv_sec;
6241 clock_pairing.nsec = ts.tv_nsec;
6242 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6243 clock_pairing.flags = 0;
6244
6245 ret = 0;
6246 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6247 sizeof(struct kvm_clock_pairing)))
6248 ret = -KVM_EFAULT;
6249
6250 return ret;
6251}
8ef81a9a 6252#endif
55dd00a7 6253
6aef266c
SV		 6254/*
6255 * kvm_pv_kick_cpu_op: Kick a vcpu.
6256 *
6257 * @apicid - apicid of vcpu to be kicked.
6258 */
6259static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6260{
24d2166b 6261 struct kvm_lapic_irq lapic_irq;
6aef266c 6262
24d2166b
R		 6263 lapic_irq.shorthand = 0;
6264 lapic_irq.dest_mode = 0;
ebd28fcb 6265 lapic_irq.level = 0;
24d2166b 6266 lapic_irq.dest_id = apicid;
93bbf0b8 6267 lapic_irq.msi_redir_hint = false;
6aef266c 6268
24d2166b 6269 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6270 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6271}
6272
d62caabb
AS		 6273void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6274{
6275 vcpu->arch.apicv_active = false;
6276 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6277}
6278
8776e519
HB		 6279int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6280{
6281 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6282 int op_64_bit, r;
8776e519 6283
6affcbed 6284 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6285
55cd8e5a
GN		 6286 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6287 return kvm_hv_hypercall(vcpu);
6288
5fdbf976
MT		 6289 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6290 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6291 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6292 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6293 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6294
229456fc 6295 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6296
a449c7aa
NA		 6297 op_64_bit = is_64_bit_mode(vcpu);
6298 if (!op_64_bit) {
8776e519
HB		 6299 nr &= 0xFFFFFFFF;
6300 a0 &= 0xFFFFFFFF;
6301 a1 &= 0xFFFFFFFF;
6302 a2 &= 0xFFFFFFFF;
6303 a3 &= 0xFFFFFFFF;
6304 }
6305
07708c4a
JK		 6306 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6307 ret = -KVM_EPERM;
6308 goto out;
6309 }
6310
8776e519 6311 switch (nr) {
b93463aa
AK		 6312 case KVM_HC_VAPIC_POLL_IRQ:
6313 ret = 0;
6314 break;
6aef266c
SV		 6315 case KVM_HC_KICK_CPU:
6316 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6317 ret = 0;
6318 break;
8ef81a9a 6319#ifdef CONFIG_X86_64
55dd00a7
MT		 6320 case KVM_HC_CLOCK_PAIRING:
6321 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6322 break;
8ef81a9a 6323#endif
8776e519
HB		 6324 default:
6325 ret = -KVM_ENOSYS;
6326 break;
6327 }
07708c4a 6328out:
a449c7aa
NA		 6329 if (!op_64_bit)
6330 ret = (u32)ret;
5fdbf976 6331 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6332 ++vcpu->stat.hypercalls;
2f333bcb 6333 return r;
8776e519
HB		 6334}
6335EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6336
b6785def 6337static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6338{
d6aa1000 6339 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6340 char instruction[3];
5fdbf976 6341 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6342
8776e519 6343 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6344
ce2e852e
DV		 6345 return emulator_write_emulated(ctxt, rip, instruction, 3,
6346 &ctxt->exception);
8776e519
HB		 6347}
6348
851ba692 6349static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6350{
782d422b
MG		 6351 return vcpu->run->request_interrupt_window &&
6352 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6353}
6354
851ba692 6355static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6356{
851ba692
AK		 6357 struct kvm_run *kvm_run = vcpu->run;
6358
91586a3b 6359 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6360 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6361 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6362 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6363 kvm_run->ready_for_interrupt_injection =
6364 pic_in_kernel(vcpu->kvm) ||
782d422b 6365 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6366}
6367
95ba8273
GN		 6368static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6369{
6370 int max_irr, tpr;
6371
6372 if (!kvm_x86_ops->update_cr8_intercept)
6373 return;
6374
bce87cce 6375 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6376 return;
6377
d62caabb
AS		 6378 if (vcpu->arch.apicv_active)
6379 return;
6380
8db3baa2
GN		 6381 if (!vcpu->arch.apic->vapic_addr)
6382 max_irr = kvm_lapic_find_highest_irr(vcpu);
6383 else
6384 max_irr = -1;
95ba8273
GN		 6385
6386 if (max_irr != -1)
6387 max_irr >>= 4;
6388
6389 tpr = kvm_lapic_get_cr8(vcpu);
6390
6391 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6392}
6393
b6b8a145 6394static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6395{
b6b8a145
JK		 6396 int r;
6397
95ba8273 6398 /* try to reinject previous events if any */
664f8e26
WL		 6399 if (vcpu->arch.exception.injected) {
6400 kvm_x86_ops->queue_exception(vcpu);
6401 return 0;
6402 }
6403
6404 /*
6405 * Exceptions must be injected immediately, or the exception
6406 * frame will have the address of the NMI or interrupt handler.
6407 */
6408 if (!vcpu->arch.exception.pending) {
6409 if (vcpu->arch.nmi_injected) {
6410 kvm_x86_ops->set_nmi(vcpu);
6411 return 0;
6412 }
6413
6414 if (vcpu->arch.interrupt.pending) {
6415 kvm_x86_ops->set_irq(vcpu);
6416 return 0;
6417 }
6418 }
6419
6420 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6421 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6422 if (r != 0)
6423 return r;
6424 }
6425
6426 /* try to inject new event if pending */
b59bb7bd 6427 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6428 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6429 vcpu->arch.exception.has_error_code,
6430 vcpu->arch.exception.error_code);
d6e8c854 6431
664f8e26
WL		 6432 vcpu->arch.exception.pending = false;
6433 vcpu->arch.exception.injected = true;
6434
d6e8c854
NA		 6435 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6436 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6437 X86_EFLAGS_RF);
6438
6bdf0662
NA		 6439 if (vcpu->arch.exception.nr == DB_VECTOR &&
6440 (vcpu->arch.dr7 & DR7_GD)) {
6441 vcpu->arch.dr7 &= ~DR7_GD;
6442 kvm_update_dr7(vcpu);
6443 }
6444
cfcd20e5 6445 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6446 } else if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
c43203ca 6447 vcpu->arch.smi_pending = false;
ee2cd4b7 6448 enter_smm(vcpu);
c43203ca 6449 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6450 --vcpu->arch.nmi_pending;
6451 vcpu->arch.nmi_injected = true;
6452 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6453 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6454 /*
6455 * Because interrupts can be injected asynchronously, we are
6456 * calling check_nested_events again here to avoid a race condition.
6457 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6458 * proposal and current concerns. Perhaps we should be setting
6459 * KVM_REQ_EVENT only on certain events and not unconditionally?
6460 */
6461 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6462 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6463 if (r != 0)
6464 return r;
6465 }
95ba8273 6466 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6467 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6468 false);
6469 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6470 }
6471 }
ee2cd4b7 6472
b6b8a145 6473 return 0;
95ba8273
GN		 6474}
6475
7460fb4a
AK		 6476static void process_nmi(struct kvm_vcpu *vcpu)
6477{
6478 unsigned limit = 2;
6479
6480 /*
6481 * x86 is limited to one NMI running, and one NMI pending after it.
6482 * If an NMI is already in progress, limit further NMIs to just one.
6483 * Otherwise, allow two (and we'll inject the first one immediately).
6484 */
6485 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6486 limit = 1;
6487
6488 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6489 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6490 kvm_make_request(KVM_REQ_EVENT, vcpu);
6491}
6492
660a5d51
PB		 6493#define put_smstate(type, buf, offset, val) \
6494 *(type *)((buf) + (offset) - 0x7e00) = val
6495
ee2cd4b7 6496static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6497{
6498 u32 flags = 0;
6499 flags |= seg->g << 23;
6500 flags |= seg->db << 22;
6501 flags |= seg->l << 21;
6502 flags |= seg->avl << 20;
6503 flags |= seg->present << 15;
6504 flags |= seg->dpl << 13;
6505 flags |= seg->s << 12;
6506 flags |= seg->type << 8;
6507 return flags;
6508}
6509
ee2cd4b7 6510static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6511{
6512 struct kvm_segment seg;
6513 int offset;
6514
6515 kvm_get_segment(vcpu, &seg, n);
6516 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6517
6518 if (n < 3)
6519 offset = 0x7f84 + n * 12;
6520 else
6521 offset = 0x7f2c + (n - 3) * 12;
6522
6523 put_smstate(u32, buf, offset + 8, seg.base);
6524 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6525 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6526}
6527
efbb288a 6528#ifdef CONFIG_X86_64
ee2cd4b7 6529static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6530{
6531 struct kvm_segment seg;
6532 int offset;
6533 u16 flags;
6534
6535 kvm_get_segment(vcpu, &seg, n);
6536 offset = 0x7e00 + n * 16;
6537
ee2cd4b7 6538 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6539 put_smstate(u16, buf, offset, seg.selector);
6540 put_smstate(u16, buf, offset + 2, flags);
6541 put_smstate(u32, buf, offset + 4, seg.limit);
6542 put_smstate(u64, buf, offset + 8, seg.base);
6543}
efbb288a 6544#endif
660a5d51 6545
ee2cd4b7 6546static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6547{
6548 struct desc_ptr dt;
6549 struct kvm_segment seg;
6550 unsigned long val;
6551 int i;
6552
6553 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6554 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6555 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6556 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6557
6558 for (i = 0; i < 8; i++)
6559 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6560
6561 kvm_get_dr(vcpu, 6, &val);
6562 put_smstate(u32, buf, 0x7fcc, (u32)val);
6563 kvm_get_dr(vcpu, 7, &val);
6564 put_smstate(u32, buf, 0x7fc8, (u32)val);
6565
6566 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6567 put_smstate(u32, buf, 0x7fc4, seg.selector);
6568 put_smstate(u32, buf, 0x7f64, seg.base);
6569 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6570 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6571
6572 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6573 put_smstate(u32, buf, 0x7fc0, seg.selector);
6574 put_smstate(u32, buf, 0x7f80, seg.base);
6575 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6576 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6577
6578 kvm_x86_ops->get_gdt(vcpu, &dt);
6579 put_smstate(u32, buf, 0x7f74, dt.address);
6580 put_smstate(u32, buf, 0x7f70, dt.size);
6581
6582 kvm_x86_ops->get_idt(vcpu, &dt);
6583 put_smstate(u32, buf, 0x7f58, dt.address);
6584 put_smstate(u32, buf, 0x7f54, dt.size);
6585
6586 for (i = 0; i < 6; i++)
ee2cd4b7 6587 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6588
6589 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6590
6591 /* revision id */
6592 put_smstate(u32, buf, 0x7efc, 0x00020000);
6593 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6594}
6595
ee2cd4b7 6596static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6597{
6598#ifdef CONFIG_X86_64
6599 struct desc_ptr dt;
6600 struct kvm_segment seg;
6601 unsigned long val;
6602 int i;
6603
6604 for (i = 0; i < 16; i++)
6605 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6606
6607 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6608 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6609
6610 kvm_get_dr(vcpu, 6, &val);
6611 put_smstate(u64, buf, 0x7f68, val);
6612 kvm_get_dr(vcpu, 7, &val);
6613 put_smstate(u64, buf, 0x7f60, val);
6614
6615 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6616 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6617 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6618
6619 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6620
6621 /* revision id */
6622 put_smstate(u32, buf, 0x7efc, 0x00020064);
6623
6624 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6625
6626 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6627 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6628 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6629 put_smstate(u32, buf, 0x7e94, seg.limit);
6630 put_smstate(u64, buf, 0x7e98, seg.base);
6631
6632 kvm_x86_ops->get_idt(vcpu, &dt);
6633 put_smstate(u32, buf, 0x7e84, dt.size);
6634 put_smstate(u64, buf, 0x7e88, dt.address);
6635
6636 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6637 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6638 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6639 put_smstate(u32, buf, 0x7e74, seg.limit);
6640 put_smstate(u64, buf, 0x7e78, seg.base);
6641
6642 kvm_x86_ops->get_gdt(vcpu, &dt);
6643 put_smstate(u32, buf, 0x7e64, dt.size);
6644 put_smstate(u64, buf, 0x7e68, dt.address);
6645
6646 for (i = 0; i < 6; i++)
ee2cd4b7 6647 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6648#else
6649 WARN_ON_ONCE(1);
6650#endif
6651}
6652
ee2cd4b7 6653static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6654{
660a5d51 6655 struct kvm_segment cs, ds;
18c3626e 6656 struct desc_ptr dt;
660a5d51
PB		 6657 char buf[512];
6658 u32 cr0;
6659
660a5d51
PB		 6660 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6661 vcpu->arch.hflags |= HF_SMM_MASK;
6662 memset(buf, 0, 512);
d6321d49 6663 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6664 enter_smm_save_state_64(vcpu, buf);
660a5d51 6665 else
ee2cd4b7 6666 enter_smm_save_state_32(vcpu, buf);
660a5d51 6667
54bf36aa 6668 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6669
6670 if (kvm_x86_ops->get_nmi_mask(vcpu))
6671 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6672 else
6673 kvm_x86_ops->set_nmi_mask(vcpu, true);
6674
6675 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6676 kvm_rip_write(vcpu, 0x8000);
6677
6678 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6679 kvm_x86_ops->set_cr0(vcpu, cr0);
6680 vcpu->arch.cr0 = cr0;
6681
6682 kvm_x86_ops->set_cr4(vcpu, 0);
6683
18c3626e
PB		 6684 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6685 dt.address = dt.size = 0;
6686 kvm_x86_ops->set_idt(vcpu, &dt);
6687
660a5d51
PB		 6688 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6689
6690 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6691 cs.base = vcpu->arch.smbase;
6692
6693 ds.selector = 0;
6694 ds.base = 0;
6695
6696 cs.limit = ds.limit = 0xffffffff;
6697 cs.type = ds.type = 0x3;
6698 cs.dpl = ds.dpl = 0;
6699 cs.db = ds.db = 0;
6700 cs.s = ds.s = 1;
6701 cs.l = ds.l = 0;
6702 cs.g = ds.g = 1;
6703 cs.avl = ds.avl = 0;
6704 cs.present = ds.present = 1;
6705 cs.unusable = ds.unusable = 0;
6706 cs.padding = ds.padding = 0;
6707
6708 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6709 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6710 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6711 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6712 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6713 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6714
d6321d49 6715 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6716 kvm_x86_ops->set_efer(vcpu, 0);
6717
6718 kvm_update_cpuid(vcpu);
6719 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6720}
6721
ee2cd4b7 6722static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6723{
6724 vcpu->arch.smi_pending = true;
6725 kvm_make_request(KVM_REQ_EVENT, vcpu);
6726}
6727
2860c4b1
PB		 6728void kvm_make_scan_ioapic_request(struct kvm *kvm)
6729{
6730 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6731}
6732
3d81bc7e 6733static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6734{
5c919412
AS		 6735 u64 eoi_exit_bitmap[4];
6736
3d81bc7e
YZ		 6737 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6738 return;
c7c9c56c 6739
6308630b 6740 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6741
b053b2ae 6742 if (irqchip_split(vcpu->kvm))
6308630b 6743 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6744 else {
76dfafd5 6745 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6746 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6747 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6748 }
5c919412
AS		 6749 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6750 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6751 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6752}
6753
a70656b6
RK		 6754static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6755{
6756 ++vcpu->stat.tlb_flush;
6757 kvm_x86_ops->tlb_flush(vcpu);
6758}
6759
58582f04
RK		 6760void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6761 unsigned long start, unsigned long end)
6762{
6763 unsigned long apic_address;
6764
6765 /*
6766 * The physical address of apic access page is stored in the VMCS.
6767 * Update it when it becomes invalid.
6768 */
6769 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6770 if (start <= apic_address && apic_address < end)
6771 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6772}
6773
4256f43f
TC		 6774void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6775{
c24ae0dc
TC		 6776 struct page *page = NULL;
6777
35754c98 6778 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6779 return;
6780
4256f43f
TC		 6781 if (!kvm_x86_ops->set_apic_access_page_addr)
6782 return;
6783
c24ae0dc 6784 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6785 if (is_error_page(page))
6786 return;
c24ae0dc
TC		 6787 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6788
6789 /*
6790 * Do not pin apic access page in memory, the MMU notifier
6791 * will call us again if it is migrated or swapped out.
6792 */
6793 put_page(page);
4256f43f
TC		 6794}
6795EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6796
9357d939 6797/*
362c698f 6798 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6799 * exiting to the userspace. Otherwise, the value will be returned to the
6800 * userspace.
6801 */
851ba692 6802static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6803{
6804 int r;
62a193ed
MG		 6805 bool req_int_win =
6806 dm_request_for_irq_injection(vcpu) &&
6807 kvm_cpu_accept_dm_intr(vcpu);
6808
730dca42 6809 bool req_immediate_exit = false;
b6c7a5dc 6810
2fa6e1e1 6811 if (kvm_request_pending(vcpu)) {
a8eeb04a 6812 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6813 kvm_mmu_unload(vcpu);
a8eeb04a 6814 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6815 __kvm_migrate_timers(vcpu);
d828199e
MT		 6816 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6817 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6818 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6819 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6820 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6821 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6822 if (unlikely(r))
6823 goto out;
6824 }
a8eeb04a 6825 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6826 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6827 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6828 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6829 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6830 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6831 r = 0;
6832 goto out;
6833 }
a8eeb04a 6834 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6835 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6836 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6837 r = 0;
6838 goto out;
6839 }
af585b92
GN		 6840 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6841 /* Page is swapped out. Do synthetic halt */
6842 vcpu->arch.apf.halted = true;
6843 r = 1;
6844 goto out;
6845 }
c9aaa895
GC		 6846 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6847 record_steal_time(vcpu);
64d60670
PB		 6848 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6849 process_smi(vcpu);
7460fb4a
AK		 6850 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6851 process_nmi(vcpu);
f5132b01 6852 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6853 kvm_pmu_handle_event(vcpu);
f5132b01 6854 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6855 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6856 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6857 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6858 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6859 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6860 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6861 vcpu->run->eoi.vector =
6862 vcpu->arch.pending_ioapic_eoi;
6863 r = 0;
6864 goto out;
6865 }
6866 }
3d81bc7e
YZ		 6867 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6868 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6869 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6870 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6871 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6872 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6873 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6874 r = 0;
6875 goto out;
6876 }
e516cebb
AS		 6877 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6878 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6879 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6880 r = 0;
6881 goto out;
6882 }
db397571
AS		 6883 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6884 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6885 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6886 r = 0;
6887 goto out;
6888 }
f3b138c5
AS		 6889
6890 /*
6891 * KVM_REQ_HV_STIMER has to be processed after
6892 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6893 * depend on the guest clock being up-to-date
6894 */
1f4b34f8
AS		 6895 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6896 kvm_hv_process_stimers(vcpu);
2f52d58c 6897 }
b93463aa 6898
b463a6f7 6899 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6900 ++vcpu->stat.req_event;
66450a21
JK		 6901 kvm_apic_accept_events(vcpu);
6902 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6903 r = 1;
6904 goto out;
6905 }
6906
b6b8a145
JK		 6907 if (inject_pending_event(vcpu, req_int_win) != 0)
6908 req_immediate_exit = true;
321c5658 6909 else {
c43203ca
PB		 6910 /* Enable NMI/IRQ window open exits if needed.
6911 *
6912 * SMIs have two cases: 1) they can be nested, and
6913 * then there is nothing to do here because RSM will
6914 * cause a vmexit anyway; 2) or the SMI can be pending
6915 * because inject_pending_event has completed the
6916 * injection of an IRQ or NMI from the previous vmexit,
6917 * and then we request an immediate exit to inject the SMI.
6918 */
6919 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6920 req_immediate_exit = true;
321c5658
YS		 6921 if (vcpu->arch.nmi_pending)
6922 kvm_x86_ops->enable_nmi_window(vcpu);
6923 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6924 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6925 WARN_ON(vcpu->arch.exception.pending);
321c5658 6926 }
b463a6f7
AK		 6927
6928 if (kvm_lapic_enabled(vcpu)) {
6929 update_cr8_intercept(vcpu);
6930 kvm_lapic_sync_to_vapic(vcpu);
6931 }
6932 }
6933
d8368af8
AK		 6934 r = kvm_mmu_reload(vcpu);
6935 if (unlikely(r)) {
d905c069 6936 goto cancel_injection;
d8368af8
AK		 6937 }
6938
b6c7a5dc
HB		 6939 preempt_disable();
6940
6941 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6942 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6943
6944 /*
6945 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6946 * IPI are then delayed after guest entry, which ensures that they
6947 * result in virtual interrupt delivery.
6948 */
6949 local_irq_disable();
6b7e2d09
XG		 6950 vcpu->mode = IN_GUEST_MODE;
6951
01b71917
MT		 6952 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6953
0f127d12 6954 /*
b95234c8 6955 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6956 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6957 *
6958 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6959 * pairs with the memory barrier implicit in pi_test_and_set_on
6960 * (see vmx_deliver_posted_interrupt).
6961 *
6962 * 3) This also orders the write to mode from any reads to the page
6963 * tables done while the VCPU is running. Please see the comment
6964 * in kvm_flush_remote_tlbs.
6b7e2d09 6965 */
01b71917 6966 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6967
b95234c8
PB		 6968 /*
6969 * This handles the case where a posted interrupt was
6970 * notified with kvm_vcpu_kick.
6971 */
6972 if (kvm_lapic_enabled(vcpu)) {
6973 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6974 kvm_x86_ops->sync_pir_to_irr(vcpu);
6975 }
32f88400 6976
2fa6e1e1 6977 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6978 || need_resched() || signal_pending(current)) {
6b7e2d09 6979 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6980 smp_wmb();
6c142801
AK		 6981 local_irq_enable();
6982 preempt_enable();
01b71917 6983 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6984 r = 1;
d905c069 6985 goto cancel_injection;
6c142801
AK		 6986 }
6987
fc5b7f3b
DM		 6988 kvm_load_guest_xcr0(vcpu);
6989
c43203ca
PB		 6990 if (req_immediate_exit) {
6991 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6992 smp_send_reschedule(vcpu->cpu);
c43203ca 6993 }
d6185f20 6994
8b89fe1f
PB		 6995 trace_kvm_entry(vcpu->vcpu_id);
6996 wait_lapic_expire(vcpu);
6edaa530 6997 guest_enter_irqoff();
b6c7a5dc 6998
42dbaa5a 6999 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7000 set_debugreg(0, 7);
7001 set_debugreg(vcpu->arch.eff_db[0], 0);
7002 set_debugreg(vcpu->arch.eff_db[1], 1);
7003 set_debugreg(vcpu->arch.eff_db[2], 2);
7004 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7005 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7006 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7007 }
b6c7a5dc 7008
851ba692 7009 kvm_x86_ops->run(vcpu);
b6c7a5dc 7010
c77fb5fe
PB		 7011 /*
7012 * Do this here before restoring debug registers on the host. And
7013 * since we do this before handling the vmexit, a DR access vmexit
7014 * can (a) read the correct value of the debug registers, (b) set
7015 * KVM_DEBUGREG_WONT_EXIT again.
7016 */
7017 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7018 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7019 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7020 kvm_update_dr0123(vcpu);
7021 kvm_update_dr6(vcpu);
7022 kvm_update_dr7(vcpu);
7023 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7024 }
7025
24f1e32c
FW		 7026 /*
7027 * If the guest has used debug registers, at least dr7
7028 * will be disabled while returning to the host.
7029 * If we don't have active breakpoints in the host, we don't
7030 * care about the messed up debug address registers. But if
7031 * we have some of them active, restore the old state.
7032 */
59d8eb53 7033 if (hw_breakpoint_active())
24f1e32c 7034 hw_breakpoint_restore();
42dbaa5a 7035
4ba76538 7036 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7037
6b7e2d09 7038 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7039 smp_wmb();
a547c6db 7040
fc5b7f3b
DM		 7041 kvm_put_guest_xcr0(vcpu);
7042
a547c6db 7043 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7044
7045 ++vcpu->stat.exits;
7046
f2485b3e 7047 guest_exit_irqoff();
b6c7a5dc 7048
f2485b3e 7049 local_irq_enable();
b6c7a5dc
HB		 7050 preempt_enable();
7051
f656ce01 7052 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7053
b6c7a5dc
HB		 7054 /*
7055 * Profile KVM exit RIPs:
7056 */
7057 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7058 unsigned long rip = kvm_rip_read(vcpu);
7059 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7060 }
7061
cc578287
ZA		 7062 if (unlikely(vcpu->arch.tsc_always_catchup))
7063 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7064
5cfb1d5a
MT		 7065 if (vcpu->arch.apic_attention)
7066 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7067
618232e2 7068 vcpu->arch.gpa_available = false;
851ba692 7069 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7070 return r;
7071
7072cancel_injection:
7073 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7074 if (unlikely(vcpu->arch.apic_attention))
7075 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7076out:
7077 return r;
7078}
b6c7a5dc 7079
362c698f
PB		 7080static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7081{
bf9f6ac8
FW		 7082 if (!kvm_arch_vcpu_runnable(vcpu) &&
7083 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7084 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7085 kvm_vcpu_block(vcpu);
7086 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7087
7088 if (kvm_x86_ops->post_block)
7089 kvm_x86_ops->post_block(vcpu);
7090
9c8fd1ba
PB		 7091 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7092 return 1;
7093 }
362c698f
PB		 7094
7095 kvm_apic_accept_events(vcpu);
7096 switch(vcpu->arch.mp_state) {
7097 case KVM_MP_STATE_HALTED:
7098 vcpu->arch.pv.pv_unhalted = false;
7099 vcpu->arch.mp_state =
7100 KVM_MP_STATE_RUNNABLE;
7101 case KVM_MP_STATE_RUNNABLE:
7102 vcpu->arch.apf.halted = false;
7103 break;
7104 case KVM_MP_STATE_INIT_RECEIVED:
7105 break;
7106 default:
7107 return -EINTR;
7108 break;
7109 }
7110 return 1;
7111}
09cec754 7112
5d9bc648
PB		 7113static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7114{
0ad3bed6
PB		 7115 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7116 kvm_x86_ops->check_nested_events(vcpu, false);
7117
5d9bc648
PB		 7118 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7119 !vcpu->arch.apf.halted);
7120}
7121
362c698f 7122static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7123{
7124 int r;
f656ce01 7125 struct kvm *kvm = vcpu->kvm;
d7690175 7126
f656ce01 7127 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7128
362c698f 7129 for (;;) {
58f800d5 7130 if (kvm_vcpu_running(vcpu)) {
851ba692 7131 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7132 } else {
362c698f 7133 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7134 }
7135
09cec754
GN		 7136 if (r <= 0)
7137 break;
7138
72875d8a 7139 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7140 if (kvm_cpu_has_pending_timer(vcpu))
7141 kvm_inject_pending_timer_irqs(vcpu);
7142
782d422b
MG		 7143 if (dm_request_for_irq_injection(vcpu) &&
7144 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7145 r = 0;
7146 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7147 ++vcpu->stat.request_irq_exits;
362c698f 7148 break;
09cec754 7149 }
af585b92
GN		 7150
7151 kvm_check_async_pf_completion(vcpu);
7152
09cec754
GN		 7153 if (signal_pending(current)) {
7154 r = -EINTR;
851ba692 7155 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7156 ++vcpu->stat.signal_exits;
362c698f 7157 break;
09cec754
GN		 7158 }
7159 if (need_resched()) {
f656ce01 7160 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7161 cond_resched();
f656ce01 7162 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7163 }
b6c7a5dc
HB		 7164 }
7165
f656ce01 7166 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7167
7168 return r;
7169}
7170
716d51ab
GN		 7171static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7172{
7173 int r;
7174 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7175 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7176 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7177 if (r != EMULATE_DONE)
7178 return 0;
7179 return 1;
7180}
7181
7182static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7183{
7184 BUG_ON(!vcpu->arch.pio.count);
7185
7186 return complete_emulated_io(vcpu);
7187}
7188
f78146b0
AK		 7189/*
7190 * Implements the following, as a state machine:
7191 *
7192 * read:
7193 * for each fragment
87da7e66
XG		 7194 * for each mmio piece in the fragment
7195 * write gpa, len
7196 * exit
7197 * copy data
f78146b0
AK		 7198 * execute insn
7199 *
7200 * write:
7201 * for each fragment
87da7e66
XG		 7202 * for each mmio piece in the fragment
7203 * write gpa, len
7204 * copy data
7205 * exit
f78146b0 7206 */
716d51ab 7207static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7208{
7209 struct kvm_run *run = vcpu->run;
f78146b0 7210 struct kvm_mmio_fragment *frag;
87da7e66 7211 unsigned len;
5287f194 7212
716d51ab 7213 BUG_ON(!vcpu->mmio_needed);
5287f194 7214
716d51ab 7215 /* Complete previous fragment */
87da7e66
XG		 7216 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7217 len = min(8u, frag->len);
716d51ab 7218 if (!vcpu->mmio_is_write)
87da7e66
XG		 7219 memcpy(frag->data, run->mmio.data, len);
7220
7221 if (frag->len <= 8) {
7222 /* Switch to the next fragment. */
7223 frag++;
7224 vcpu->mmio_cur_fragment++;
7225 } else {
7226 /* Go forward to the next mmio piece. */
7227 frag->data += len;
7228 frag->gpa += len;
7229 frag->len -= len;
7230 }
7231
a08d3b3b 7232 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7233 vcpu->mmio_needed = 0;
0912c977
PB		 7234
7235 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7236 if (vcpu->mmio_is_write)
716d51ab
GN		 7237 return 1;
7238 vcpu->mmio_read_completed = 1;
7239 return complete_emulated_io(vcpu);
7240 }
87da7e66 7241
716d51ab
GN		 7242 run->exit_reason = KVM_EXIT_MMIO;
7243 run->mmio.phys_addr = frag->gpa;
7244 if (vcpu->mmio_is_write)
87da7e66
XG		 7245 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7246 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7247 run->mmio.is_write = vcpu->mmio_is_write;
7248 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7249 return 0;
5287f194
AK		 7250}
7251
716d51ab 7252
b6c7a5dc
HB		 7253int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7254{
c5bedc68 7255 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc 7256 int r;
b6c7a5dc 7257
2ce03d85 7258 fpu__initialize(fpu);
e5c30142 7259
40ba283e 7260 kvm_sigset_activate(vcpu);
ac9f6dc0 7261
a4535290 7262 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7263 if (kvm_run->immediate_exit) {
7264 r = -EINTR;
7265 goto out;
7266 }
b6c7a5dc 7267 kvm_vcpu_block(vcpu);
66450a21 7268 kvm_apic_accept_events(vcpu);
72875d8a 7269 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7270 r = -EAGAIN;
a0595000
JS		 7271 if (signal_pending(current)) {
7272 r = -EINTR;
7273 vcpu->run->exit_reason = KVM_EXIT_INTR;
7274 ++vcpu->stat.signal_exits;
7275 }
ac9f6dc0 7276 goto out;
b6c7a5dc
HB		 7277 }
7278
b6c7a5dc 7279 /* re-sync apic's tpr */
35754c98 7280 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7281 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7282 r = -EINVAL;
7283 goto out;
7284 }
7285 }
b6c7a5dc 7286
716d51ab
GN		 7287 if (unlikely(vcpu->arch.complete_userspace_io)) {
7288 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7289 vcpu->arch.complete_userspace_io = NULL;
7290 r = cui(vcpu);
7291 if (r <= 0)
7292 goto out;
7293 } else
7294 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7295
460df4c1
PB		 7296 if (kvm_run->immediate_exit)
7297 r = -EINTR;
7298 else
7299 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7300
7301out:
f1d86e46 7302 post_kvm_run_save(vcpu);
40ba283e 7303 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7304
b6c7a5dc
HB		 7305 return r;
7306}
7307
7308int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7309{
7ae441ea
GN		 7310 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7311 /*
7312 * We are here if userspace calls get_regs() in the middle of
7313 * instruction emulation. Registers state needs to be copied
4a969980 7314 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7315 * that usually, but some bad designed PV devices (vmware
7316 * backdoor interface) need this to work
7317 */
dd856efa 7318 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7319 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7320 }
5fdbf976
MT		 7321 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7322 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7323 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7324 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7325 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7326 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7327 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7328 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7329#ifdef CONFIG_X86_64
5fdbf976
MT		 7330 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7331 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7332 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7333 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7334 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7335 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7336 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7337 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7338#endif
7339
5fdbf976 7340 regs->rip = kvm_rip_read(vcpu);
91586a3b 7341 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7342
b6c7a5dc
HB		 7343 return 0;
7344}
7345
7346int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7347{
7ae441ea
GN		 7348 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7349 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7350
5fdbf976
MT		 7351 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7352 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7353 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7354 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7355 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7356 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7357 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7358 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7359#ifdef CONFIG_X86_64
5fdbf976
MT		 7360 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7361 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7362 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7363 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7364 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7365 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7366 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7367 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7368#endif
7369
5fdbf976 7370 kvm_rip_write(vcpu, regs->rip);
6cc3f6f1 7371 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7372
b4f14abd
JK		 7373 vcpu->arch.exception.pending = false;
7374
3842d135
AK		 7375 kvm_make_request(KVM_REQ_EVENT, vcpu);
7376
b6c7a5dc
HB		 7377 return 0;
7378}
7379
b6c7a5dc
HB		 7380void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7381{
7382 struct kvm_segment cs;
7383
3e6e0aab 7384 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7385 *db = cs.db;
7386 *l = cs.l;
7387}
7388EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7389
7390int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7391 struct kvm_sregs *sregs)
7392{
89a27f4d 7393 struct desc_ptr dt;
b6c7a5dc 7394
3e6e0aab
GT		 7395 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7396 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7397 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7398 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7399 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7400 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7401
3e6e0aab
GT		 7402 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7403 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7404
7405 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7406 sregs->idt.limit = dt.size;
7407 sregs->idt.base = dt.address;
b6c7a5dc 7408 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7409 sregs->gdt.limit = dt.size;
7410 sregs->gdt.base = dt.address;
b6c7a5dc 7411
4d4ec087 7412 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7413 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7414 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7415 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7416 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7417 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7418 sregs->apic_base = kvm_get_apic_base(vcpu);
7419
923c61bb 7420 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7421
36752c9b 7422 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7423 set_bit(vcpu->arch.interrupt.nr,
7424 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7425
b6c7a5dc
HB		 7426 return 0;
7427}
7428
62d9f0db
MT		 7429int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7430 struct kvm_mp_state *mp_state)
7431{
66450a21 7432 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7433 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7434 vcpu->arch.pv.pv_unhalted)
7435 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7436 else
7437 mp_state->mp_state = vcpu->arch.mp_state;
7438
62d9f0db
MT		 7439 return 0;
7440}
7441
7442int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7443 struct kvm_mp_state *mp_state)
7444{
bce87cce 7445 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7446 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7447 return -EINVAL;
7448
28bf2888
DH		 7449 /* INITs are latched while in SMM */
7450 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7451 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7452 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7453 return -EINVAL;
7454
66450a21
JK		 7455 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7456 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7457 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7458 } else
7459 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7460 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7461 return 0;
7462}
7463
7f3d35fd
KW		 7464int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7465 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7466{
9d74191a 7467 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7468 int ret;
e01c2426 7469
8ec4722d 7470 init_emulate_ctxt(vcpu);
c697518a 7471
7f3d35fd 7472 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7473 has_error_code, error_code);
c697518a 7474
c697518a 7475 if (ret)
19d04437 7476 return EMULATE_FAIL;
37817f29 7477
9d74191a
TY		 7478 kvm_rip_write(vcpu, ctxt->eip);
7479 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7480 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7481 return EMULATE_DONE;
37817f29
IE		 7482}
7483EXPORT_SYMBOL_GPL(kvm_task_switch);
7484
846666fa
LT		 7485int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7486{
61546237 7487 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
846666fa
LT		 7488 /*
7489 * When EFER.LME and CR0.PG are set, the processor is in
7490 * 64-bit mode (though maybe in a 32-bit code segment).
7491 * CR4.PAE and EFER.LMA must be set.
7492 */
61546237 7493 if (!(sregs->cr4 & X86_CR4_PAE)
846666fa
LT		 7494 || !(sregs->efer & EFER_LMA))
7495 return -EINVAL;
7496 } else {
7497 /*
7498 * Not in 64-bit mode: EFER.LMA is clear and the code
7499 * segment cannot be 64-bit.
7500 */
7501 if (sregs->efer & EFER_LMA || sregs->cs.l)
7502 return -EINVAL;
7503 }
7504
7505 return 0;
7506}
7507
b6c7a5dc
HB		 7508int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7509 struct kvm_sregs *sregs)
7510{
58cb628d 7511 struct msr_data apic_base_msr;
b6c7a5dc 7512 int mmu_reset_needed = 0;
63f42e02 7513 int pending_vec, max_bits, idx;
89a27f4d 7514 struct desc_ptr dt;
b6c7a5dc 7515
d6321d49
RK		 7516 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7517 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7518 return -EINVAL;
7519
846666fa
LT		 7520 if (kvm_valid_sregs(vcpu, sregs))
7521 return -EINVAL;
7522
d3802286
JM		 7523 apic_base_msr.data = sregs->apic_base;
7524 apic_base_msr.host_initiated = true;
7525 if (kvm_set_apic_base(vcpu, &apic_base_msr))
6d1068b3
PM		 7526 return -EINVAL;
7527
89a27f4d
GN		 7528 dt.size = sregs->idt.limit;
7529 dt.address = sregs->idt.base;
b6c7a5dc 7530 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7531 dt.size = sregs->gdt.limit;
7532 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7533 kvm_x86_ops->set_gdt(vcpu, &dt);
7534
ad312c7c 7535 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7536 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7537 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7538 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7539
2d3ad1f4 7540 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7541
f6801dff 7542 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7543 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7544
4d4ec087 7545 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7546 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7547 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7548
fc78f519 7549 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7550 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7551 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7552 kvm_update_cpuid(vcpu);
63f42e02
XG		 7553
7554 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7555 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7556 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7557 mmu_reset_needed = 1;
7558 }
63f42e02 7559 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7560
7561 if (mmu_reset_needed)
7562 kvm_mmu_reset_context(vcpu);
7563
a50abc3b 7564 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7565 pending_vec = find_first_bit(
7566 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7567 if (pending_vec < max_bits) {
66fd3f7f 7568 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7569 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7570 }
7571
3e6e0aab
GT		 7572 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7573 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7574 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7575 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7576 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7577 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7578
3e6e0aab
GT		 7579 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7580 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7581
5f0269f5
ME		 7582 update_cr8_intercept(vcpu);
7583
9c3e4aab 7584 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7585 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7586 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7587 !is_protmode(vcpu))
9c3e4aab
MT		 7588 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7589
3842d135
AK		 7590 kvm_make_request(KVM_REQ_EVENT, vcpu);
7591
b6c7a5dc
HB		 7592 return 0;
7593}
7594
d0bfb940
JK		 7595int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7596 struct kvm_guest_debug *dbg)
b6c7a5dc 7597{
355be0b9 7598 unsigned long rflags;
ae675ef0 7599 int i, r;
b6c7a5dc 7600
4f926bf2
JK		 7601 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7602 r = -EBUSY;
7603 if (vcpu->arch.exception.pending)
2122ff5e 7604 goto out;
4f926bf2
JK		 7605 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7606 kvm_queue_exception(vcpu, DB_VECTOR);
7607 else
7608 kvm_queue_exception(vcpu, BP_VECTOR);
7609 }
7610
91586a3b
JK		 7611 /*
7612 * Read rflags as long as potentially injected trace flags are still
7613 * filtered out.
7614 */
7615 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7616
7617 vcpu->guest_debug = dbg->control;
7618 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7619 vcpu->guest_debug = 0;
7620
7621 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7622 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7623 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7624 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7625 } else {
7626 for (i = 0; i < KVM_NR_DB_REGS; i++)
7627 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7628 }
c8639010 7629 kvm_update_dr7(vcpu);
ae675ef0 7630
f92653ee
JK		 7631 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7632 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7633 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7634
91586a3b
JK		 7635 /*
7636 * Trigger an rflags update that will inject or remove the trace
7637 * flags.
7638 */
7639 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7640
a96036b8 7641 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7642
4f926bf2 7643 r = 0;
d0bfb940 7644
2122ff5e 7645out:
b6c7a5dc
HB		 7646
7647 return r;
7648}
7649
8b006791
ZX		 7650/*
7651 * Translate a guest virtual address to a guest physical address.
7652 */
7653int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7654 struct kvm_translation *tr)
7655{
7656 unsigned long vaddr = tr->linear_address;
7657 gpa_t gpa;
f656ce01 7658 int idx;
8b006791 7659
f656ce01 7660 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7661 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7662 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7663 tr->physical_address = gpa;
7664 tr->valid = gpa != UNMAPPED_GVA;
7665 tr->writeable = 1;
7666 tr->usermode = 0;
8b006791
ZX		 7667
7668 return 0;
7669}
7670
d0752060
HB		 7671int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7672{
c47ada30 7673 struct fxregs_state *fxsave =
7366ed77 7674 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7675
d0752060
HB		 7676 memcpy(fpu->fpr, fxsave->st_space, 128);
7677 fpu->fcw = fxsave->cwd;
7678 fpu->fsw = fxsave->swd;
7679 fpu->ftwx = fxsave->twd;
7680 fpu->last_opcode = fxsave->fop;
7681 fpu->last_ip = fxsave->rip;
7682 fpu->last_dp = fxsave->rdp;
7683 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7684
d0752060
HB		 7685 return 0;
7686}
7687
7688int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7689{
c47ada30 7690 struct fxregs_state *fxsave =
7366ed77 7691 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7692
d0752060
HB		 7693 memcpy(fxsave->st_space, fpu->fpr, 128);
7694 fxsave->cwd = fpu->fcw;
7695 fxsave->swd = fpu->fsw;
7696 fxsave->twd = fpu->ftwx;
7697 fxsave->fop = fpu->last_opcode;
7698 fxsave->rip = fpu->last_ip;
7699 fxsave->rdp = fpu->last_dp;
7700 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7701
d0752060
HB		 7702 return 0;
7703}
7704
0ee6a517 7705static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7706{
bf935b0b 7707 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7708 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7709 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7710 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7711
2acf923e
DC		 7712 /*
7713 * Ensure guest xcr0 is valid for loading
7714 */
d91cab78 7715 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7716
ad312c7c 7717 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7718}
d0752060
HB		 7719
7720void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7721{
2608d7a1 7722 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7723 return;
7724
2acf923e
DC		 7725 /*
7726 * Restore all possible states in the guest,
7727 * and assume host would use all available bits.
7728 * Guest xcr0 would be loaded later.
7729 */
d0752060 7730 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7731 __kernel_fpu_begin();
38cfd5e3
PB		 7732 /* PKRU is separately restored in kvm_x86_ops->run. */
7733 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7734 ~XFEATURE_MASK_PKRU);
0c04851c 7735 trace_kvm_fpu(1);
d0752060 7736}
d0752060
HB		 7737
7738void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7739{
3d42de25 7740 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7741 return;
7742
7743 vcpu->guest_fpu_loaded = 0;
4f836347 7744 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7745 __kernel_fpu_end();
f096ed85 7746 ++vcpu->stat.fpu_reload;
0c04851c 7747 trace_kvm_fpu(0);
d0752060 7748}
e9b11c17
ZX		 7749
7750void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7751{
bd768e14
IY		 7752 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7753
12f9a48f 7754 kvmclock_reset(vcpu);
7f1ea208 7755
e9b11c17 7756 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7757 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7758}
7759
7760struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7761 unsigned int id)
7762{
c447e76b
LL		 7763 struct kvm_vcpu *vcpu;
7764
6755bae8
ZA		 7765 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7766 printk_once(KERN_WARNING
7767 "kvm: SMP vm created on host with unstable TSC; "
7768 "guest TSC will not be reliable\n");
c447e76b
LL		 7769
7770 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7771
c447e76b 7772 return vcpu;
26e5215f 7773}
e9b11c17 7774
26e5215f
AK		 7775int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7776{
7777 int r;
e9b11c17 7778
19efffa2 7779 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7780 r = vcpu_load(vcpu);
7781 if (r)
7782 return r;
d28bc9dd 7783 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7784 kvm_mmu_setup(vcpu);
e9b11c17 7785 vcpu_put(vcpu);
26e5215f 7786 return r;
e9b11c17
ZX		 7787}
7788
31928aa5 7789void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7790{
8fe8ab46 7791 struct msr_data msr;
332967a3 7792 struct kvm *kvm = vcpu->kvm;
42897d86 7793
d3457c87
RK		 7794 kvm_hv_vcpu_postcreate(vcpu);
7795
31928aa5
DD		 7796 if (vcpu_load(vcpu))
7797 return;
8fe8ab46
WA		 7798 msr.data = 0x0;
7799 msr.index = MSR_IA32_TSC;
7800 msr.host_initiated = true;
7801 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7802 vcpu_put(vcpu);
7803
630994b3
MT		 7804 if (!kvmclock_periodic_sync)
7805 return;
7806
332967a3
AJ		 7807 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7808 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7809}
7810
d40ccc62 7811void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7812{
9fc77441 7813 int r;
344d9588
GN		 7814 vcpu->arch.apf.msr_val = 0;
7815
9fc77441
MT		 7816 r = vcpu_load(vcpu);
7817 BUG_ON(r);
e9b11c17
ZX		 7818 kvm_mmu_unload(vcpu);
7819 vcpu_put(vcpu);
7820
7821 kvm_x86_ops->vcpu_free(vcpu);
7822}
7823
d28bc9dd 7824void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7825{
b4830f3a
RK		 7826 kvm_lapic_reset(vcpu, init_event);
7827
e69fab5d
PB		 7828 vcpu->arch.hflags = 0;
7829
c43203ca 7830 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7831 atomic_set(&vcpu->arch.nmi_queued, 0);
7832 vcpu->arch.nmi_pending = 0;
448fa4a9 7833 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7834 kvm_clear_interrupt_queue(vcpu);
7835 kvm_clear_exception_queue(vcpu);
664f8e26 7836 vcpu->arch.exception.pending = false;
448fa4a9 7837
42dbaa5a 7838 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7839 kvm_update_dr0123(vcpu);
6f43ed01 7840 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7841 kvm_update_dr6(vcpu);
42dbaa5a 7842 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7843 kvm_update_dr7(vcpu);
42dbaa5a 7844
1119022c
NA		 7845 vcpu->arch.cr2 = 0;
7846
3842d135 7847 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7848 vcpu->arch.apf.msr_val = 0;
c9aaa895 7849 vcpu->arch.st.msr_val = 0;
3842d135 7850
12f9a48f
GC		 7851 kvmclock_reset(vcpu);
7852
af585b92
GN		 7853 kvm_clear_async_pf_completion_queue(vcpu);
7854 kvm_async_pf_hash_reset(vcpu);
7855 vcpu->arch.apf.halted = false;
3842d135 7856
64d60670 7857 if (!init_event) {
d28bc9dd 7858 kvm_pmu_reset(vcpu);
64d60670 7859 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7860
7861 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7862 vcpu->arch.msr_misc_features_enables = 0;
64d60670 7863 }
f5132b01 7864
66f7b72e
JS		 7865 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7866 vcpu->arch.regs_avail = ~0;
7867 vcpu->arch.regs_dirty = ~0;
7868
d28bc9dd 7869 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7870}
7871
2b4a273b 7872void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7873{
7874 struct kvm_segment cs;
7875
7876 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7877 cs.selector = vector << 8;
7878 cs.base = vector << 12;
7879 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7880 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7881}
7882
13a34e06 7883int kvm_arch_hardware_enable(void)
e9b11c17 7884{
ca84d1a2
ZA		 7885 struct kvm *kvm;
7886 struct kvm_vcpu *vcpu;
7887 int i;
0dd6a6ed
ZA		 7888 int ret;
7889 u64 local_tsc;
7890 u64 max_tsc = 0;
7891 bool stable, backwards_tsc = false;
18863bdd
AK		 7892
7893 kvm_shared_msr_cpu_online();
13a34e06 7894 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7895 if (ret != 0)
7896 return ret;
7897
4ea1636b 7898 local_tsc = rdtsc();
0dd6a6ed
ZA		 7899 stable = !check_tsc_unstable();
7900 list_for_each_entry(kvm, &vm_list, vm_list) {
7901 kvm_for_each_vcpu(i, vcpu, kvm) {
7902 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7903 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7904 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7905 backwards_tsc = true;
7906 if (vcpu->arch.last_host_tsc > max_tsc)
7907 max_tsc = vcpu->arch.last_host_tsc;
7908 }
7909 }
7910 }
7911
7912 /*
7913 * Sometimes, even reliable TSCs go backwards. This happens on
7914 * platforms that reset TSC during suspend or hibernate actions, but
7915 * maintain synchronization. We must compensate. Fortunately, we can
7916 * detect that condition here, which happens early in CPU bringup,
7917 * before any KVM threads can be running. Unfortunately, we can't
7918 * bring the TSCs fully up to date with real time, as we aren't yet far
7919 * enough into CPU bringup that we know how much real time has actually
108b249c 7920 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7921 * variables that haven't been updated yet.
7922 *
7923 * So we simply find the maximum observed TSC above, then record the
7924 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7925 * the adjustment will be applied. Note that we accumulate
7926 * adjustments, in case multiple suspend cycles happen before some VCPU
7927 * gets a chance to run again. In the event that no KVM threads get a
7928 * chance to run, we will miss the entire elapsed period, as we'll have
7929 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7930 * loose cycle time. This isn't too big a deal, since the loss will be
7931 * uniform across all VCPUs (not to mention the scenario is extremely
7932 * unlikely). It is possible that a second hibernate recovery happens
7933 * much faster than a first, causing the observed TSC here to be
7934 * smaller; this would require additional padding adjustment, which is
7935 * why we set last_host_tsc to the local tsc observed here.
7936 *
7937 * N.B. - this code below runs only on platforms with reliable TSC,
7938 * as that is the only way backwards_tsc is set above. Also note
7939 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7940 * have the same delta_cyc adjustment applied if backwards_tsc
7941 * is detected. Note further, this adjustment is only done once,
7942 * as we reset last_host_tsc on all VCPUs to stop this from being
7943 * called multiple times (one for each physical CPU bringup).
7944 *
4a969980 7945 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7946 * will be compensated by the logic in vcpu_load, which sets the TSC to
7947 * catchup mode. This will catchup all VCPUs to real time, but cannot
7948 * guarantee that they stay in perfect synchronization.
7949 */
7950 if (backwards_tsc) {
7951 u64 delta_cyc = max_tsc - local_tsc;
7952 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7953 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7954 kvm_for_each_vcpu(i, vcpu, kvm) {
7955 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7956 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7957 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7958 }
7959
7960 /*
7961 * We have to disable TSC offset matching.. if you were
7962 * booting a VM while issuing an S4 host suspend....
7963 * you may have some problem. Solving this issue is
7964 * left as an exercise to the reader.
7965 */
7966 kvm->arch.last_tsc_nsec = 0;
7967 kvm->arch.last_tsc_write = 0;
7968 }
7969
7970 }
7971 return 0;
e9b11c17
ZX		 7972}
7973
13a34e06 7974void kvm_arch_hardware_disable(void)
e9b11c17 7975{
13a34e06
RK		 7976 kvm_x86_ops->hardware_disable();
7977 drop_user_return_notifiers();
e9b11c17
ZX		 7978}
7979
7980int kvm_arch_hardware_setup(void)
7981{
9e9c3fe4
NA		 7982 int r;
7983
7984 r = kvm_x86_ops->hardware_setup();
7985 if (r != 0)
7986 return r;
7987
35181e86
HZ		 7988 if (kvm_has_tsc_control) {
7989 /*
7990 * Make sure the user can only configure tsc_khz values that
7991 * fit into a signed integer.
7992 * A min value is not calculated needed because it will always
7993 * be 1 on all machines.
7994 */
7995 u64 max = min(0x7fffffffULL,
7996 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7997 kvm_max_guest_tsc_khz = max;
7998
ad721883 7999 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8000 }
ad721883 8001
9e9c3fe4
NA		 8002 kvm_init_msr_list();
8003 return 0;
e9b11c17
ZX		 8004}
8005
8006void kvm_arch_hardware_unsetup(void)
8007{
8008 kvm_x86_ops->hardware_unsetup();
8009}
8010
8011void kvm_arch_check_processor_compat(void *rtn)
8012{
8013 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8014}
8015
8016bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8017{
8018 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8019}
8020EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8021
8022bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8023{
8024 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8025}
8026
54e9818f 8027struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8028EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8029
e9b11c17
ZX		 8030int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8031{
8032 struct page *page;
8033 struct kvm *kvm;
8034 int r;
8035
8036 BUG_ON(vcpu->kvm == NULL);
8037 kvm = vcpu->kvm;
8038
b2a05fef 8039 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
6aef266c 8040 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 8041 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 8042 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8043 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8044 else
a4535290 8045 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8046
8047 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8048 if (!page) {
8049 r = -ENOMEM;
8050 goto fail;
8051 }
ad312c7c 8052 vcpu->arch.pio_data = page_address(page);
e9b11c17 8053
cc578287 8054 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8055
e9b11c17
ZX		 8056 r = kvm_mmu_create(vcpu);
8057 if (r < 0)
8058 goto fail_free_pio_data;
8059
8060 if (irqchip_in_kernel(kvm)) {
8061 r = kvm_create_lapic(vcpu);
8062 if (r < 0)
8063 goto fail_mmu_destroy;
54e9818f
GN		 8064 } else
8065 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8066
890ca9ae
HY		 8067 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8068 GFP_KERNEL);
8069 if (!vcpu->arch.mce_banks) {
8070 r = -ENOMEM;
443c39bc 8071 goto fail_free_lapic;
890ca9ae
HY		 8072 }
8073 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8074
f1797359
WY		 8075 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8076 r = -ENOMEM;
f5f48ee1 8077 goto fail_free_mce_banks;
f1797359 8078 }
f5f48ee1 8079
0ee6a517 8080 fx_init(vcpu);
66f7b72e 8081
ba904635 8082 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 8083 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 8084
8085 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 8086 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8087
5a4f55cd
EK		 8088 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8089
74545705
RK		 8090 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8091
af585b92 8092 kvm_async_pf_hash_reset(vcpu);
f5132b01 8093 kvm_pmu_init(vcpu);
af585b92 8094
1c1a9ce9 8095 vcpu->arch.pending_external_vector = -1;
de63ad4c 8096 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8097
5c919412
AS		 8098 kvm_hv_vcpu_init(vcpu);
8099
e9b11c17 8100 return 0;
0ee6a517 8101
f5f48ee1
SY		 8102fail_free_mce_banks:
8103 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8104fail_free_lapic:
8105 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8106fail_mmu_destroy:
8107 kvm_mmu_destroy(vcpu);
8108fail_free_pio_data:
ad312c7c 8109 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8110fail:
8111 return r;
8112}
8113
8114void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8115{
f656ce01
MT		 8116 int idx;
8117
1f4b34f8 8118 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8119 kvm_pmu_destroy(vcpu);
36cb93fd 8120 kfree(vcpu->arch.mce_banks);
e9b11c17 8121 kvm_free_lapic(vcpu);
f656ce01 8122 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8123 kvm_mmu_destroy(vcpu);
f656ce01 8124 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8125 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8126 if (!lapic_in_kernel(vcpu))
54e9818f 8127 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8128}
d19a9cd2 8129
e790d9ef
RK		 8130void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8131{
ae97a3b8 8132 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8133}
8134
e08b9637 8135int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8136{
e08b9637
CO		 8137 if (type)
8138 return -EINVAL;
8139
6ef768fa 8140 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8141 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8142 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8143 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8144 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8145
5550af4d
SY		 8146 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8147 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8148 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8149 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8150 &kvm->arch.irq_sources_bitmap);
5550af4d 8151
038f8c11 8152 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8153 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8154 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8155 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8156
108b249c 8157 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8158 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8159
7e44e449 8160 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8161 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8162
0eb05bf2 8163 kvm_page_track_init(kvm);
13d268ca 8164 kvm_mmu_init_vm(kvm);
0eb05bf2 8165
03543133
SS		 8166 if (kvm_x86_ops->vm_init)
8167 return kvm_x86_ops->vm_init(kvm);
8168
d89f5eff 8169 return 0;
d19a9cd2
ZX		 8170}
8171
8172static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8173{
9fc77441
MT		 8174 int r;
8175 r = vcpu_load(vcpu);
8176 BUG_ON(r);
d19a9cd2
ZX		 8177 kvm_mmu_unload(vcpu);
8178 vcpu_put(vcpu);
8179}
8180
8181static void kvm_free_vcpus(struct kvm *kvm)
8182{
8183 unsigned int i;
988a2cae 8184 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8185
8186 /*
8187 * Unpin any mmu pages first.
8188 */
af585b92
GN		 8189 kvm_for_each_vcpu(i, vcpu, kvm) {
8190 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8191 kvm_unload_vcpu_mmu(vcpu);
af585b92 8192 }
988a2cae
GN		 8193 kvm_for_each_vcpu(i, vcpu, kvm)
8194 kvm_arch_vcpu_free(vcpu);
8195
8196 mutex_lock(&kvm->lock);
8197 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8198 kvm->vcpus[i] = NULL;
d19a9cd2 8199
988a2cae
GN		 8200 atomic_set(&kvm->online_vcpus, 0);
8201 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8202}
8203
ad8ba2cd
SY		 8204void kvm_arch_sync_events(struct kvm *kvm)
8205{
332967a3 8206 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8207 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8208 kvm_free_pit(kvm);
ad8ba2cd
SY		 8209}
8210
1d8007bd 8211int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8212{
8213 int i, r;
25188b99 8214 unsigned long hva;
f0d648bd
PB		 8215 struct kvm_memslots *slots = kvm_memslots(kvm);
8216 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8217
8218 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8219 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8220 return -EINVAL;
9da0e4d5 8221
f0d648bd
PB		 8222 slot = id_to_memslot(slots, id);
8223 if (size) {
b21629da 8224 if (slot->npages)
f0d648bd
PB		 8225 return -EEXIST;
8226
8227 /*
8228 * MAP_SHARED to prevent internal slot pages from being moved
8229 * by fork()/COW.
8230 */
8231 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8232 MAP_SHARED | MAP_ANONYMOUS, 0);
8233 if (IS_ERR((void *)hva))
8234 return PTR_ERR((void *)hva);
8235 } else {
8236 if (!slot->npages)
8237 return 0;
8238
8239 hva = 0;
8240 }
8241
8242 old = *slot;
9da0e4d5 8243 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8244 struct kvm_userspace_memory_region m;
9da0e4d5 8245
1d8007bd
PB		 8246 m.slot = id | (i << 16);
8247 m.flags = 0;
8248 m.guest_phys_addr = gpa;
f0d648bd 8249 m.userspace_addr = hva;
1d8007bd 8250 m.memory_size = size;
9da0e4d5
PB		 8251 r = __kvm_set_memory_region(kvm, &m);
8252 if (r < 0)
8253 return r;
8254 }
8255
b95f8ca8
EB		 8256 if (!size)
8257 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8258
9da0e4d5
PB		 8259 return 0;
8260}
8261EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8262
1d8007bd 8263int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8264{
8265 int r;
8266
8267 mutex_lock(&kvm->slots_lock);
1d8007bd 8268 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8269 mutex_unlock(&kvm->slots_lock);
8270
8271 return r;
8272}
8273EXPORT_SYMBOL_GPL(x86_set_memory_region);
8274
d19a9cd2
ZX		 8275void kvm_arch_destroy_vm(struct kvm *kvm)
8276{
27469d29
AH		 8277 if (current->mm == kvm->mm) {
8278 /*
8279 * Free memory regions allocated on behalf of userspace,
8280 * unless the the memory map has changed due to process exit
8281 * or fd copying.
8282 */
1d8007bd
PB		 8283 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8284 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8285 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8286 }
03543133
SS		 8287 if (kvm_x86_ops->vm_destroy)
8288 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8289 kvm_pic_destroy(kvm);
8290 kvm_ioapic_destroy(kvm);
d19a9cd2 8291 kvm_free_vcpus(kvm);
af1bae54 8292 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8293 kvm_mmu_uninit_vm(kvm);
2beb6dad 8294 kvm_page_track_cleanup(kvm);
d19a9cd2 8295}
0de10343 8296
5587027c 8297void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8298 struct kvm_memory_slot *dont)
8299{
8300 int i;
8301
d89cc617
TY		 8302 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8303 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8304 kvfree(free->arch.rmap[i]);
d89cc617 8305 free->arch.rmap[i] = NULL;
77d11309 8306 }
d89cc617
TY		 8307 if (i == 0)
8308 continue;
8309
8310 if (!dont || free->arch.lpage_info[i - 1] !=
8311 dont->arch.lpage_info[i - 1]) {
548ef284 8312 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8313 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8314 }
8315 }
21ebbeda
XG		 8316
8317 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8318}
8319
5587027c
AK		 8320int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8321 unsigned long npages)
db3fe4eb
TY		 8322{
8323 int i;
8324
d89cc617 8325 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8326 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8327 unsigned long ugfn;
8328 int lpages;
d89cc617 8329 int level = i + 1;
db3fe4eb
TY		 8330
8331 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8332 slot->base_gfn, level) + 1;
8333
d89cc617 8334 slot->arch.rmap[i] =
a7c3e901 8335 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8336 if (!slot->arch.rmap[i])
77d11309 8337 goto out_free;
d89cc617
TY		 8338 if (i == 0)
8339 continue;
77d11309 8340
a7c3e901 8341 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8342 if (!linfo)
db3fe4eb
TY		 8343 goto out_free;
8344
92f94f1e
XG		 8345 slot->arch.lpage_info[i - 1] = linfo;
8346
db3fe4eb 8347 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8348 linfo[0].disallow_lpage = 1;
db3fe4eb 8349 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8350 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8351 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8352 /*
8353 * If the gfn and userspace address are not aligned wrt each
8354 * other, or if explicitly asked to, disable large page
8355 * support for this slot
8356 */
8357 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8358 !kvm_largepages_enabled()) {
8359 unsigned long j;
8360
8361 for (j = 0; j < lpages; ++j)
92f94f1e 8362 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8363 }
8364 }
8365
21ebbeda
XG		 8366 if (kvm_page_track_create_memslot(slot, npages))
8367 goto out_free;
8368
db3fe4eb
TY		 8369 return 0;
8370
8371out_free:
d89cc617 8372 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8373 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8374 slot->arch.rmap[i] = NULL;
8375 if (i == 0)
8376 continue;
8377
548ef284 8378 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8379 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8380 }
8381 return -ENOMEM;
8382}
8383
15f46015 8384void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8385{
e6dff7d1
TY		 8386 /*
8387 * memslots->generation has been incremented.
8388 * mmio generation may have reached its maximum value.
8389 */
54bf36aa 8390 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8391}
8392
f7784b8e
MT		 8393int kvm_arch_prepare_memory_region(struct kvm *kvm,
8394 struct kvm_memory_slot *memslot,
09170a49 8395 const struct kvm_userspace_memory_region *mem,
7b6195a9 8396 enum kvm_mr_change change)
0de10343 8397{
f7784b8e
MT		 8398 return 0;
8399}
8400
88178fd4
KH		 8401static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8402 struct kvm_memory_slot *new)
8403{
8404 /* Still write protect RO slot */
8405 if (new->flags & KVM_MEM_READONLY) {
8406 kvm_mmu_slot_remove_write_access(kvm, new);
8407 return;
8408 }
8409
8410 /*
8411 * Call kvm_x86_ops dirty logging hooks when they are valid.
8412 *
8413 * kvm_x86_ops->slot_disable_log_dirty is called when:
8414 *
8415 * - KVM_MR_CREATE with dirty logging is disabled
8416 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8417 *
8418 * The reason is, in case of PML, we need to set D-bit for any slots
8419 * with dirty logging disabled in order to eliminate unnecessary GPA
8420 * logging in PML buffer (and potential PML buffer full VMEXT). This
8421 * guarantees leaving PML enabled during guest's lifetime won't have
8422 * any additonal overhead from PML when guest is running with dirty
8423 * logging disabled for memory slots.
8424 *
8425 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8426 * to dirty logging mode.
8427 *
8428 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8429 *
8430 * In case of write protect:
8431 *
8432 * Write protect all pages for dirty logging.
8433 *
8434 * All the sptes including the large sptes which point to this
8435 * slot are set to readonly. We can not create any new large
8436 * spte on this slot until the end of the logging.
8437 *
8438 * See the comments in fast_page_fault().
8439 */
8440 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8441 if (kvm_x86_ops->slot_enable_log_dirty)
8442 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8443 else
8444 kvm_mmu_slot_remove_write_access(kvm, new);
8445 } else {
8446 if (kvm_x86_ops->slot_disable_log_dirty)
8447 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8448 }
8449}
8450
f7784b8e 8451void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8452 const struct kvm_userspace_memory_region *mem,
8482644a 8453 const struct kvm_memory_slot *old,
f36f3f28 8454 const struct kvm_memory_slot *new,
8482644a 8455 enum kvm_mr_change change)
f7784b8e 8456{
8482644a 8457 int nr_mmu_pages = 0;
f7784b8e 8458
48c0e4e9
XG		 8459 if (!kvm->arch.n_requested_mmu_pages)
8460 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8461
48c0e4e9 8462 if (nr_mmu_pages)
0de10343 8463 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8464
3ea3b7fa
WL		 8465 /*
8466 * Dirty logging tracks sptes in 4k granularity, meaning that large
8467 * sptes have to be split. If live migration is successful, the guest
8468 * in the source machine will be destroyed and large sptes will be
8469 * created in the destination. However, if the guest continues to run
8470 * in the source machine (for example if live migration fails), small
8471 * sptes will remain around and cause bad performance.
8472 *
8473 * Scan sptes if dirty logging has been stopped, dropping those
8474 * which can be collapsed into a single large-page spte. Later
8475 * page faults will create the large-page sptes.
8476 */
8477 if ((change != KVM_MR_DELETE) &&
8478 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8479 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8480 kvm_mmu_zap_collapsible_sptes(kvm, new);
8481
c972f3b1 8482 /*
88178fd4 8483 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8484 *
88178fd4
KH		 8485 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8486 * been zapped so no dirty logging staff is needed for old slot. For
8487 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8488 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8489 *
8490 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8491 */
88178fd4 8492 if (change != KVM_MR_DELETE)
f36f3f28 8493 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8494}
1d737c8a 8495
2df72e9b 8496void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8497{
6ca18b69 8498 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8499}
8500
2df72e9b
MT		 8501void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8502 struct kvm_memory_slot *slot)
8503{
ae7cd873 8504 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8505}
8506
5d9bc648
PB		 8507static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8508{
8509 if (!list_empty_careful(&vcpu->async_pf.done))
8510 return true;
8511
8512 if (kvm_apic_has_events(vcpu))
8513 return true;
8514
8515 if (vcpu->arch.pv.pv_unhalted)
8516 return true;
8517
a5f01f8e
WL		 8518 if (vcpu->arch.exception.pending)
8519 return true;
8520
47a66eed
Z		 8521 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8522 (vcpu->arch.nmi_pending &&
8523 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8524 return true;
8525
47a66eed
Z		 8526 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8527 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8528 return true;
8529
5d9bc648
PB		 8530 if (kvm_arch_interrupt_allowed(vcpu) &&
8531 kvm_cpu_has_interrupt(vcpu))
8532 return true;
8533
1f4b34f8
AS		 8534 if (kvm_hv_has_stimer_pending(vcpu))
8535 return true;
8536
5d9bc648
PB		 8537 return false;
8538}
8539
1d737c8a
ZX		 8540int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8541{
5d9bc648 8542 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8543}
5736199a 8544
199b5763
LM		 8545bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8546{
de63ad4c 8547 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8548}
8549
b6d33834 8550int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8551{
b6d33834 8552 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8553}
78646121
GN		 8554
8555int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8556{
8557 return kvm_x86_ops->interrupt_allowed(vcpu);
8558}
229456fc 8559
82b32774 8560unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8561{
82b32774
NA		 8562 if (is_64_bit_mode(vcpu))
8563 return kvm_rip_read(vcpu);
8564 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8565 kvm_rip_read(vcpu));
8566}
8567EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8568
82b32774
NA		 8569bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8570{
8571 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8572}
8573EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8574
94fe45da
JK		 8575unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8576{
8577 unsigned long rflags;
8578
8579 rflags = kvm_x86_ops->get_rflags(vcpu);
8580 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8581 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8582 return rflags;
8583}
8584EXPORT_SYMBOL_GPL(kvm_get_rflags);
8585
6addfc42 8586static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8587{
8588 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8589 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8590 rflags |= X86_EFLAGS_TF;
94fe45da 8591 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8592}
8593
8594void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8595{
8596 __kvm_set_rflags(vcpu, rflags);
3842d135 8597 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8598}
8599EXPORT_SYMBOL_GPL(kvm_set_rflags);
8600
56028d08
GN		 8601void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8602{
8603 int r;
8604
fb67e14f 8605 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8606 work->wakeup_all)
56028d08
GN		 8607 return;
8608
8609 r = kvm_mmu_reload(vcpu);
8610 if (unlikely(r))
8611 return;
8612
fb67e14f
XG		 8613 if (!vcpu->arch.mmu.direct_map &&
8614 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8615 return;
8616
56028d08
GN		 8617 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8618}
8619
af585b92
GN		 8620static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8621{
8622 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8623}
8624
8625static inline u32 kvm_async_pf_next_probe(u32 key)
8626{
8627 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8628}
8629
8630static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8631{
8632 u32 key = kvm_async_pf_hash_fn(gfn);
8633
8634 while (vcpu->arch.apf.gfns[key] != ~0)
8635 key = kvm_async_pf_next_probe(key);
8636
8637 vcpu->arch.apf.gfns[key] = gfn;
8638}
8639
8640static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8641{
8642 int i;
8643 u32 key = kvm_async_pf_hash_fn(gfn);
8644
8645 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8646 (vcpu->arch.apf.gfns[key] != gfn &&
8647 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8648 key = kvm_async_pf_next_probe(key);
8649
8650 return key;
8651}
8652
8653bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8654{
8655 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8656}
8657
8658static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8659{
8660 u32 i, j, k;
8661
8662 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8663 while (true) {
8664 vcpu->arch.apf.gfns[i] = ~0;
8665 do {
8666 j = kvm_async_pf_next_probe(j);
8667 if (vcpu->arch.apf.gfns[j] == ~0)
8668 return;
8669 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8670 /*
8671 * k lies cyclically in ]i,j]
8672 * | i.k.j |
8673 * |....j i.k.| or |.k..j i...|
8674 */
8675 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8676 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8677 i = j;
8678 }
8679}
8680
7c90705b
GN		 8681static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8682{
4e335d9e
PB		 8683
8684 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8685 sizeof(val));
7c90705b
GN		 8686}
8687
9a6e7c39
WL		 8688static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8689{
8690
8691 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8692 sizeof(u32));
8693}
8694
af585b92
GN		 8695void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8696 struct kvm_async_pf *work)
8697{
6389ee94
AK		 8698 struct x86_exception fault;
8699
7c90705b 8700 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8701 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8702
8703 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8704 (vcpu->arch.apf.send_user_only &&
8705 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8706 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8707 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8708 fault.vector = PF_VECTOR;
8709 fault.error_code_valid = true;
8710 fault.error_code = 0;
8711 fault.nested_page_fault = false;
8712 fault.address = work->arch.token;
adfe20fb 8713 fault.async_page_fault = true;
6389ee94 8714 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8715 }
af585b92
GN		 8716}
8717
8718void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8719 struct kvm_async_pf *work)
8720{
6389ee94 8721 struct x86_exception fault;
9a6e7c39 8722 u32 val;
6389ee94 8723
f2e10669 8724 if (work->wakeup_all)
7c90705b
GN		 8725 work->arch.token = ~0; /* broadcast wakeup */
8726 else
8727 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8728 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8729
9a6e7c39
WL		 8730 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8731 !apf_get_user(vcpu, &val)) {
8732 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8733 vcpu->arch.exception.pending &&
8734 vcpu->arch.exception.nr == PF_VECTOR &&
8735 !apf_put_user(vcpu, 0)) {
8736 vcpu->arch.exception.injected = false;
8737 vcpu->arch.exception.pending = false;
8738 vcpu->arch.exception.nr = 0;
8739 vcpu->arch.exception.has_error_code = false;
8740 vcpu->arch.exception.error_code = 0;
8741 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8742 fault.vector = PF_VECTOR;
8743 fault.error_code_valid = true;
8744 fault.error_code = 0;
8745 fault.nested_page_fault = false;
8746 fault.address = work->arch.token;
8747 fault.async_page_fault = true;
8748 kvm_inject_page_fault(vcpu, &fault);
8749 }
7c90705b 8750 }
e6d53e3b 8751 vcpu->arch.apf.halted = false;
a4fa1635 8752 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8753}
8754
8755bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8756{
8757 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8758 return true;
8759 else
9bc1f09f 8760 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8761}
8762
5544eb9b
PB		 8763void kvm_arch_start_assignment(struct kvm *kvm)
8764{
8765 atomic_inc(&kvm->arch.assigned_device_count);
8766}
8767EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8768
8769void kvm_arch_end_assignment(struct kvm *kvm)
8770{
8771 atomic_dec(&kvm->arch.assigned_device_count);
8772}
8773EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8774
8775bool kvm_arch_has_assigned_device(struct kvm *kvm)
8776{
8777 return atomic_read(&kvm->arch.assigned_device_count);
8778}
8779EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8780
e0f0bbc5
AW		 8781void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8782{
8783 atomic_inc(&kvm->arch.noncoherent_dma_count);
8784}
8785EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8786
8787void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8788{
8789 atomic_dec(&kvm->arch.noncoherent_dma_count);
8790}
8791EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8792
8793bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8794{
8795 return atomic_read(&kvm->arch.noncoherent_dma_count);
8796}
8797EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8798
14717e20
AW		 8799bool kvm_arch_has_irq_bypass(void)
8800{
8801 return kvm_x86_ops->update_pi_irte != NULL;
8802}
8803
87276880
FW		 8804int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8805 struct irq_bypass_producer *prod)
8806{
8807 struct kvm_kernel_irqfd *irqfd =
8808 container_of(cons, struct kvm_kernel_irqfd, consumer);
8809
14717e20 8810 irqfd->producer = prod;
87276880 8811
14717e20
AW		 8812 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8813 prod->irq, irqfd->gsi, 1);
87276880
FW		 8814}
8815
8816void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8817 struct irq_bypass_producer *prod)
8818{
8819 int ret;
8820 struct kvm_kernel_irqfd *irqfd =
8821 container_of(cons, struct kvm_kernel_irqfd, consumer);
8822
87276880
FW		 8823 WARN_ON(irqfd->producer != prod);
8824 irqfd->producer = NULL;
8825
8826 /*
8827 * When producer of consumer is unregistered, we change back to
8828 * remapped mode, so we can re-use the current implementation
bb3541f1 8829 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8830 * int this case doesn't want to receive the interrupts.
8831 */
8832 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8833 if (ret)
8834 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8835 " fails: %d\n", irqfd->consumer.token, ret);
8836}
8837
8838int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8839 uint32_t guest_irq, bool set)
8840{
8841 if (!kvm_x86_ops->update_pi_irte)
8842 return -EINVAL;
8843
8844 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8845}
8846
52004014
FW		 8847bool kvm_vector_hashing_enabled(void)
8848{
8849 return vector_hashing;
8850}
8851EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8852
229456fc 8853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8854EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8855EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8856EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8857EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8858EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8859EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8860EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8861EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8862EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8863EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8864EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8865EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8866EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8867EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8868EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8869EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8870EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8871EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git