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5894ca00 | 1 | /* |
e8a92932 MY |
2 | * Copyright (C) 2012-2015 Panasonic Corporation |
3 | * Copyright (C) 2015-2016 Socionext Inc. | |
4 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
5894ca00 MY |
5 | * |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
a187559e | 9 | /* U-Boot - Common settings for UniPhier Family */ |
5894ca00 MY |
10 | |
11 | #ifndef __CONFIG_UNIPHIER_COMMON_H__ | |
12 | #define __CONFIG_UNIPHIER_COMMON_H__ | |
13 | ||
928f3248 | 14 | #define CONFIG_ARMV7_PSCI_1_0 |
e8a92932 | 15 | |
233e42a9 MY |
16 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
17 | ||
5894ca00 MY |
18 | /*----------------------------------------------------------------------- |
19 | * MMU and Cache Setting | |
20 | *----------------------------------------------------------------------*/ | |
21 | ||
22 | /* Comment out the following to enable L1 cache */ | |
23 | /* #define CONFIG_SYS_ICACHE_OFF */ | |
24 | /* #define CONFIG_SYS_DCACHE_OFF */ | |
25 | ||
5894ca00 MY |
26 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
27 | ||
28 | #define CONFIG_TIMESTAMP | |
29 | ||
30 | /* FLASH related */ | |
31 | #define CONFIG_MTD_DEVICE | |
32 | ||
f1d9a9ed MY |
33 | #define CONFIG_SMC911X_32_BIT |
34 | /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ | |
35 | #define CONFIG_SMC911X_BASE 0 | |
36 | ||
37 | #ifdef CONFIG_MICRO_SUPPORT_CARD | |
38 | #define CONFIG_SMC911X | |
f4c93a4f | 39 | #endif |
5894ca00 MY |
40 | |
41 | #define CONFIG_FLASH_CFI_DRIVER | |
42 | #define CONFIG_SYS_FLASH_CFI | |
43 | ||
44 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
45 | #define CONFIG_SYS_MONITOR_BASE 0 | |
d085ecd6 | 46 | #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ |
5894ca00 MY |
47 | #define CONFIG_SYS_FLASH_BASE 0 |
48 | ||
49 | /* | |
66deb91e | 50 | * flash_toggle does not work for our support card. |
5894ca00 MY |
51 | * We need to use flash_status_poll. |
52 | */ | |
53 | #define CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
54 | ||
55 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
56 | ||
9879842c | 57 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 |
5894ca00 MY |
58 | |
59 | /* serial console configuration */ | |
5894ca00 | 60 | |
5894ca00 MY |
61 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
62 | ||
63 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
5894ca00 MY |
64 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
65 | /* Print Buffer Size */ | |
66 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
67 | #define CONFIG_SYS_MAXARGS 16 /* max number of command */ | |
68 | /* Boot Argument Buffer Size */ | |
69 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
70 | ||
71 | #define CONFIG_CONS_INDEX 1 | |
72 | ||
aa8a9348 | 73 | /* #define CONFIG_ENV_IS_NOWHERE */ |
5894ca00 | 74 | /* #define CONFIG_ENV_IS_IN_NAND */ |
aa8a9348 | 75 | #define CONFIG_ENV_IS_IN_MMC |
0b93e3de | 76 | #define CONFIG_ENV_OFFSET 0x100000 |
5894ca00 | 77 | #define CONFIG_ENV_SIZE 0x2000 |
5894ca00 MY |
78 | /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ |
79 | ||
aa8a9348 MY |
80 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
81 | #define CONFIG_SYS_MMC_ENV_PART 1 | |
82 | ||
561ca649 | 83 | #ifdef CONFIG_ARMV8_MULTIENTRY |
50862a51 | 84 | #define CPU_RELEASE_ADDR 0x80000000 |
9d0c2ceb MY |
85 | #define COUNTER_FREQUENCY 50000000 |
86 | #define CONFIG_GICV3 | |
87 | #define GICD_BASE 0x5fe00000 | |
667dbcd0 MY |
88 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
89 | #define GICR_BASE 0x5fe40000 | |
90 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb | 91 | #define GICR_BASE 0x5fe80000 |
667dbcd0 | 92 | #endif |
561ca649 | 93 | #elif !defined(CONFIG_ARM64) |
5894ca00 MY |
94 | /* Time clock 1MHz */ |
95 | #define CONFIG_SYS_TIMER_RATE 1000000 | |
9d0c2ceb MY |
96 | #endif |
97 | ||
5894ca00 MY |
98 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
99 | #define CONFIG_SYS_NAND_MAX_CHIPS 2 | |
100 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
101 | ||
102 | #define CONFIG_NAND_DENALI_ECC_SIZE 1024 | |
103 | ||
ea65c980 | 104 | #ifdef CONFIG_ARCH_UNIPHIER_SLD3 |
3365b4eb MY |
105 | #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 |
106 | #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 | |
107 | #else | |
5894ca00 MY |
108 | #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 |
109 | #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 | |
3365b4eb | 110 | #endif |
5894ca00 MY |
111 | |
112 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) | |
113 | ||
114 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
115 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
116 | ||
495deb44 | 117 | /* USB */ |
53c45d4e | 118 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 |
495deb44 | 119 | #define CONFIG_FAT_WRITE |
495deb44 | 120 | |
4aceb3f8 | 121 | /* SD/MMC */ |
a55d9fee | 122 | #define CONFIG_SUPPORT_EMMC_BOOT |
4aceb3f8 | 123 | |
5894ca00 MY |
124 | /* memtest works on */ |
125 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
126 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) | |
127 | ||
5894ca00 MY |
128 | /* |
129 | * Network Configuration | |
130 | */ | |
5894ca00 MY |
131 | #define CONFIG_SERVERIP 192.168.11.1 |
132 | #define CONFIG_IPADDR 192.168.11.10 | |
133 | #define CONFIG_GATEWAYIP 192.168.11.1 | |
134 | #define CONFIG_NETMASK 255.255.255.0 | |
135 | ||
136 | #define CONFIG_LOADADDR 0x84000000 | |
137 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
5894ca00 MY |
138 | |
139 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
140 | ||
b7b43036 MY |
141 | #if defined(CONFIG_ARM64) && !defined(CONFIG_ARMV8_MULTIENTRY) |
142 | /* ARM Trusted Firmware */ | |
143 | #define BOOT_IMAGES \ | |
7728f0c6 | 144 | "second_image=unph_bl.bin\0" \ |
b7b43036 MY |
145 | "third_image=fip.bin\0" |
146 | #else | |
147 | #define BOOT_IMAGES \ | |
148 | "second_image=u-boot-spl.bin\0" \ | |
149 | "third_image=u-boot.bin\0" | |
150 | #endif | |
151 | ||
5894ca00 MY |
152 | #define CONFIG_BOOTCOMMAND "run $bootmode" |
153 | ||
154 | #define CONFIG_ROOTPATH "/nfs/root/path" | |
155 | #define CONFIG_NFSBOOTCOMMAND \ | |
156 | "setenv bootargs $bootargs root=/dev/nfs rw " \ | |
157 | "nfsroot=$serverip:$rootpath " \ | |
158 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ | |
d566f754 | 159 | "run __nfsboot" |
5894ca00 | 160 | |
421376ae MY |
161 | #ifdef CONFIG_FIT |
162 | #define CONFIG_BOOTFILE "fitImage" | |
163 | #define LINUXBOOT_ENV_SETTINGS \ | |
164 | "fit_addr=0x00100000\0" \ | |
165 | "fit_addr_r=0x84100000\0" \ | |
166 | "fit_size=0x00f00000\0" \ | |
5451b777 | 167 | "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ |
421376ae | 168 | "bootm $fit_addr\0" \ |
5451b777 | 169 | "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ |
e037db0c | 170 | "bootm $fit_addr_r\0" \ |
5451b777 | 171 | "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ |
d566f754 MY |
172 | "bootm $fit_addr_r\0" \ |
173 | "__nfsboot=run tftpboot\0" | |
421376ae | 174 | #else |
9d0c2ceb | 175 | #ifdef CONFIG_ARM64 |
99b85170 | 176 | #define CONFIG_BOOTFILE "Image.gz" |
9d0c2ceb | 177 | #define LINUXBOOT_CMD "booti" |
99b85170 | 178 | #define KERNEL_ADDR_LOAD "kernel_addr_load=0x84200000\0" |
9d0c2ceb | 179 | #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" |
9d0c2ceb | 180 | #else |
89835b35 | 181 | #define CONFIG_BOOTFILE "zImage" |
9d0c2ceb | 182 | #define LINUXBOOT_CMD "bootz" |
99b85170 | 183 | #define KERNEL_ADDR_LOAD "kernel_addr_load=0x80208000\0" |
9d0c2ceb | 184 | #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" |
9d0c2ceb | 185 | #endif |
421376ae MY |
186 | #define LINUXBOOT_ENV_SETTINGS \ |
187 | "fdt_addr=0x00100000\0" \ | |
188 | "fdt_addr_r=0x84100000\0" \ | |
189 | "fdt_size=0x00008000\0" \ | |
190 | "kernel_addr=0x00200000\0" \ | |
99b85170 | 191 | KERNEL_ADDR_LOAD \ |
9d0c2ceb | 192 | KERNEL_ADDR_R \ |
99b85170 MY |
193 | "kernel_size=0x00800000\0" \ |
194 | "ramdisk_addr=0x00a00000\0" \ | |
421376ae MY |
195 | "ramdisk_addr_r=0x84a00000\0" \ |
196 | "ramdisk_size=0x00600000\0" \ | |
e037db0c | 197 | "ramdisk_file=rootfs.cpio.uboot\0" \ |
99b85170 MY |
198 | "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \ |
199 | "if test $kernel_addr_load = $kernel_addr_r; then " \ | |
200 | "true; " \ | |
201 | "else " \ | |
202 | "unzip $kernel_addr_load $kernel_addr_r; " \ | |
203 | "fi && " \ | |
9d0c2ceb | 204 | LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ |
99b85170 MY |
205 | "norboot=setexpr kernel_addr_nor $nor_base + $kernel_addr && " \ |
206 | "setexpr kernel_size_div4 $kernel_size / 4 && " \ | |
207 | "cp $kernel_addr_nor $kernel_addr_load $kernel_size_div4 && " \ | |
c0df1faf MY |
208 | "setexpr ramdisk_addr_nor $nor_base + $ramdisk_addr && " \ |
209 | "setexpr ramdisk_size_div4 $ramdisk_size / 4 && " \ | |
210 | "cp $ramdisk_addr_nor $ramdisk_addr_r $ramdisk_size_div4 && " \ | |
211 | "setexpr fdt_addr_nor $nor_base + $fdt_addr && " \ | |
212 | "setexpr fdt_size_div4 $fdt_size / 4 && " \ | |
213 | "cp $fdt_addr_nor $fdt_addr_r $fdt_size_div4 && " \ | |
cd5d9565 | 214 | "run boot_common\0" \ |
99b85170 | 215 | "nandboot=nand read $kernel_addr_load $kernel_addr $kernel_size && " \ |
421376ae MY |
216 | "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ |
217 | "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ | |
cd5d9565 | 218 | "run boot_common\0" \ |
99b85170 | 219 | "tftpboot=tftpboot $kernel_addr_load $bootfile && " \ |
e037db0c MY |
220 | "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ |
221 | "tftpboot $fdt_addr_r $fdt_file &&" \ | |
d566f754 | 222 | "run boot_common\0" \ |
99b85170 | 223 | "__nfsboot=tftpboot $kernel_addr_load $bootfile && " \ |
d566f754 MY |
224 | "tftpboot $fdt_addr_r $fdt_file &&" \ |
225 | "setenv ramdisk_addr_r - &&" \ | |
cd5d9565 | 226 | "run boot_common\0" |
421376ae MY |
227 | #endif |
228 | ||
229 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
230 | "netdev=eth0\0" \ | |
231 | "verify=n\0" \ | |
c0df1faf | 232 | "initrd_high=0xffffffffffffffff\0" \ |
90a6e929 | 233 | "nor_base=0x42000000\0" \ |
61a4f5bd | 234 | "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ |
b7b43036 | 235 | "tftpboot $tmp_addr $second_image && " \ |
c0efc314 | 236 | "setexpr tmp_addr $nor_base + 0x70000 && " \ |
b7b43036 | 237 | "tftpboot $tmp_addr $third_image\0" \ |
c231c436 MY |
238 | "emmcupdate=mmcsetn &&" \ |
239 | "mmc partconf $mmc_first_dev 0 1 1 &&" \ | |
b7b43036 | 240 | "tftpboot $second_image && " \ |
c0efc314 | 241 | "mmc write $loadaddr 0 100 && " \ |
b7b43036 | 242 | "tftpboot $third_image && " \ |
c0efc314 | 243 | "mmc write $loadaddr 100 700\0" \ |
421376ae | 244 | "nandupdate=nand erase 0 0x00100000 &&" \ |
b7b43036 | 245 | "tftpboot $second_image && " \ |
c0efc314 | 246 | "nand write $loadaddr 0 0x00020000 && " \ |
b7b43036 | 247 | "tftpboot $third_image && " \ |
c0efc314 | 248 | "nand write $loadaddr 0x00020000 0x000e0000\0" \ |
b7b43036 | 249 | BOOT_IMAGES \ |
421376ae | 250 | LINUXBOOT_ENV_SETTINGS |
5894ca00 | 251 | |
17bd4a21 MY |
252 | #define CONFIG_SYS_BOOTMAPSZ 0x20000000 |
253 | ||
cf88affa | 254 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
3e9952be | 255 | #define CONFIG_NR_DRAM_BANKS 3 |
23869698 MY |
256 | /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ |
257 | #define CONFIG_SYS_MEM_TOP_HIDE 64 | |
5894ca00 | 258 | |
3e0cfaa0 MY |
259 | #define CONFIG_PANIC_HANG |
260 | ||
261 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) | |
262 | ||
263 | /* only for SPL */ | |
9d0c2ceb MY |
264 | #if defined(CONFIG_ARM64) |
265 | #define CONFIG_SPL_TEXT_BASE 0x30000000 | |
266 | #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ | |
267 | defined(CONFIG_ARCH_UNIPHIER_LD4) || \ | |
ea65c980 | 268 | defined(CONFIG_ARCH_UNIPHIER_SLD8) |
f5d0b9b2 | 269 | #define CONFIG_SPL_TEXT_BASE 0x00040000 |
323d1f9d | 270 | #else |
f5d0b9b2 MY |
271 | #define CONFIG_SPL_TEXT_BASE 0x00100000 |
272 | #endif | |
273 | ||
667dbcd0 MY |
274 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
275 | #define CONFIG_SPL_STACK (0x30014c00) | |
276 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb MY |
277 | #define CONFIG_SPL_STACK (0x3001c000) |
278 | #else | |
755c7d9a | 279 | #define CONFIG_SPL_STACK (0x00100000) |
9d0c2ceb | 280 | #endif |
a286039b | 281 | |
5894ca00 | 282 | #define CONFIG_SPL_FRAMEWORK |
adb3928f MY |
283 | #ifdef CONFIG_ARM64 |
284 | #define CONFIG_SPL_BOARD_LOAD_IMAGE | |
9d0c2ceb | 285 | #endif |
5894ca00 | 286 | |
5894ca00 MY |
287 | #define CONFIG_SPL_BOARD_INIT |
288 | ||
c0efc314 | 289 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 |
cbbc2d80 | 290 | |
d085ecd6 | 291 | /* subtract sizeof(struct image_header) */ |
c0efc314 | 292 | #define CONFIG_SYS_UBOOT_BASE (0x70000 - 0x40) |
5894ca00 | 293 | |
d085ecd6 | 294 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
6a3cffe8 | 295 | #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 |
c0efc314 MY |
296 | #if defined(CONFIG_ARCH_UNIPHIER_LD20) |
297 | #define CONFIG_SPL_MAX_SIZE 0x14000 | |
298 | #else | |
86c3345a | 299 | #define CONFIG_SPL_MAX_SIZE 0x10000 |
c0efc314 | 300 | #endif |
667dbcd0 MY |
301 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
302 | #define CONFIG_SPL_BSS_START_ADDR 0x30012000 | |
303 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb | 304 | #define CONFIG_SPL_BSS_START_ADDR 0x30016000 |
667dbcd0 | 305 | #endif |
9d0c2ceb | 306 | #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 |
6a3cffe8 | 307 | |
c0efc314 MY |
308 | #define CONFIG_SPL_PAD_TO 0x20000 |
309 | ||
5894ca00 | 310 | #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ |