[people/ms/u-boot.git] / include / configs / uniphier.h

/*
 * Copyright (C) 2012-2015 Panasonic Corporation
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* U-Boot - Common settings for UniPhier Family */

#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__

#define CONFIG_ARMV7_PSCI_1_0

#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10

/*-----------------------------------------------------------------------
 * MMU and Cache Setting
 *----------------------------------------------------------------------*/

/* Comment out the following to enable L1 cache */
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */

#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

#define CONFIG_TIMESTAMP

/* FLASH related */
#define CONFIG_MTD_DEVICE

#define CONFIG_SMC911X_32_BIT
/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
#define CONFIG_SMC911X_BASE	0

#ifdef CONFIG_MICRO_SUPPORT_CARD
#define CONFIG_SMC911X
#endif

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI

#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MONITOR_BASE		0
#define CONFIG_SYS_MONITOR_LEN		0x00080000	/* 512KB */
#define CONFIG_SYS_FLASH_BASE		0

/*
 * flash_toggle does not work for our support card.
 * We need to use flash_status_poll.
 */
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1

/* serial console configuration */

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_CONS_INDEX		1

/* #define CONFIG_ENV_IS_NOWHERE */
/* #define CONFIG_ENV_IS_IN_NAND */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET			0x100000
#define CONFIG_ENV_SIZE				0x2000
/* #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */

#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_SYS_MMC_ENV_PART		1

#ifdef CONFIG_ARMV8_MULTIENTRY
#define CPU_RELEASE_ADDR			0x80000000
#define COUNTER_FREQUENCY			50000000
#define CONFIG_GICV3
#define GICD_BASE				0x5fe00000
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define GICR_BASE				0x5fe40000
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define GICR_BASE				0x5fe80000
#endif
#elif !defined(CONFIG_ARM64)
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE			1000000
#endif

#define CONFIG_SYS_MAX_NAND_DEVICE			1
#define CONFIG_SYS_NAND_MAX_CHIPS			2
#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_NAND_DENALI_ECC_SIZE			1024

#ifdef CONFIG_ARCH_UNIPHIER_SLD3
#define CONFIG_SYS_NAND_REGS_BASE			0xf8100000
#define CONFIG_SYS_NAND_DATA_BASE			0xf8000000
#else
#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
#endif

#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)

#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS			0

/* USB */
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	4
#define CONFIG_FAT_WRITE

/* SD/MMC */
#define CONFIG_SUPPORT_EMMC_BOOT

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)

/*
 * Network Configuration
 */
#define CONFIG_SERVERIP			192.168.11.1
#define CONFIG_IPADDR			192.168.11.10
#define CONFIG_GATEWAYIP		192.168.11.1
#define CONFIG_NETMASK			255.255.255.0

#define CONFIG_LOADADDR			0x84000000
#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/

#if defined(CONFIG_ARM64) && !defined(CONFIG_ARMV8_MULTIENTRY)
/* ARM Trusted Firmware */
#define BOOT_IMAGES \
	"second_image=unph_bl.bin\0" \
	"third_image=fip.bin\0"
#else
#define BOOT_IMAGES \
	"second_image=u-boot-spl.bin\0" \
	"third_image=u-boot.bin\0"
#endif

#define CONFIG_BOOTCOMMAND		"run $bootmode"

#define CONFIG_ROOTPATH			"/nfs/root/path"
#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs $bootargs root=/dev/nfs rw "			\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
		"run __nfsboot"

#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE			"fitImage"
#define LINUXBOOT_ENV_SETTINGS \
	"fit_addr=0x00100000\0" \
	"fit_addr_r=0x84100000\0" \
	"fit_size=0x00f00000\0" \
	"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
		"bootm $fit_addr\0" \
	"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
		"bootm $fit_addr_r\0" \
	"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
		"bootm $fit_addr_r\0" \
	"__nfsboot=run tftpboot\0"
#else
#ifdef CONFIG_ARM64
#define CONFIG_BOOTFILE			"Image.gz"
#define LINUXBOOT_CMD			"booti"
#define KERNEL_ADDR_LOAD		"kernel_addr_load=0x84200000\0"
#define KERNEL_ADDR_R			"kernel_addr_r=0x80080000\0"
#else
#define CONFIG_BOOTFILE			"zImage"
#define LINUXBOOT_CMD			"bootz"
#define KERNEL_ADDR_LOAD		"kernel_addr_load=0x80208000\0"
#define KERNEL_ADDR_R			"kernel_addr_r=0x80208000\0"
#endif
#define LINUXBOOT_ENV_SETTINGS \
	"fdt_addr=0x00100000\0" \
	"fdt_addr_r=0x84100000\0" \
	"fdt_size=0x00008000\0" \
	"kernel_addr=0x00200000\0" \
	KERNEL_ADDR_LOAD \
	KERNEL_ADDR_R \
	"kernel_size=0x00800000\0" \
	"ramdisk_addr=0x00a00000\0" \
	"ramdisk_addr_r=0x84a00000\0" \
	"ramdisk_size=0x00600000\0" \
	"ramdisk_file=rootfs.cpio.uboot\0" \
	"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \
		"if test $kernel_addr_load = $kernel_addr_r; then " \
			"true; " \
		"else " \
			"unzip $kernel_addr_load $kernel_addr_r; " \
		"fi && " \
		LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
	"norboot=setexpr kernel_addr_nor $nor_base + $kernel_addr && " \
		"setexpr kernel_size_div4 $kernel_size / 4 && " \
		"cp $kernel_addr_nor $kernel_addr_load $kernel_size_div4 && " \
		"setexpr ramdisk_addr_nor $nor_base + $ramdisk_addr && " \
		"setexpr ramdisk_size_div4 $ramdisk_size / 4 && " \
		"cp $ramdisk_addr_nor $ramdisk_addr_r $ramdisk_size_div4 && " \
		"setexpr fdt_addr_nor $nor_base + $fdt_addr && " \
		"setexpr fdt_size_div4 $fdt_size / 4 && " \
		"cp $fdt_addr_nor $fdt_addr_r $fdt_size_div4 && " \
		"run boot_common\0" \
	"nandboot=nand read $kernel_addr_load $kernel_addr $kernel_size && " \
		"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
		"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
		"run boot_common\0" \
	"tftpboot=tftpboot $kernel_addr_load $bootfile && " \
		"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
		"tftpboot $fdt_addr_r $fdt_file &&" \
		"run boot_common\0" \
	"__nfsboot=tftpboot $kernel_addr_load $bootfile && " \
		"tftpboot $fdt_addr_r $fdt_file &&" \
		"setenv ramdisk_addr_r - &&" \
		"run boot_common\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"						\
	"verify=n\0"						\
	"initrd_high=0xffffffffffffffff\0"			\
	"nor_base=0x42000000\0"					\
	"sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&"	\
		"tftpboot $tmp_addr $second_image && " \
		"setexpr tmp_addr $nor_base + 0x70000 && " \
		"tftpboot $tmp_addr $third_image\0" \
	"emmcupdate=mmcsetn &&"					\
		"mmc partconf $mmc_first_dev 0 1 1 &&"		\
		"tftpboot $second_image && " \
		"mmc write $loadaddr 0 100 && " \
		"tftpboot $third_image && " \
		"mmc write $loadaddr 100 700\0" \
	"nandupdate=nand erase 0 0x00100000 &&"			\
		"tftpboot $second_image && " \
		"nand write $loadaddr 0 0x00020000 && " \
		"tftpboot $third_image && " \
		"nand write $loadaddr 0x00020000 0x000e0000\0" \
	"usbupdate=usb start &&" \
		"tftpboot $second_image && " \
		"usb write $loadaddr 0 100 && " \
		"tftpboot $third_image && " \
		"usb write $loadaddr 100 700\0" \
	BOOT_IMAGES \
	LINUXBOOT_ENV_SETTINGS

#define CONFIG_SYS_BOOTMAPSZ			0x20000000

#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_NR_DRAM_BANKS		3
/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
#define CONFIG_SYS_MEM_TOP_HIDE		64

#define CONFIG_PANIC_HANG

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)

/* only for SPL */
#if defined(CONFIG_ARM64)
#define CONFIG_SPL_TEXT_BASE		0x30000000
#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
	defined(CONFIG_ARCH_UNIPHIER_LD4) || \
	defined(CONFIG_ARCH_UNIPHIER_SLD8)
#define CONFIG_SPL_TEXT_BASE		0x00040000
#else
#define CONFIG_SPL_TEXT_BASE		0x00100000
#endif

#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define CONFIG_SPL_STACK		(0x30014c00)
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_STACK		(0x3001c000)
#else
#define CONFIG_SPL_STACK		(0x00100000)
#endif

#define CONFIG_SPL_FRAMEWORK
#ifdef CONFIG_ARM64
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#endif

#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x20000

/* subtract sizeof(struct image_header) */
#define CONFIG_SYS_UBOOT_BASE			(0x70000 - 0x40)

#define CONFIG_SPL_TARGET			"u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT		0x10000
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_MAX_SIZE			0x14000
#else
#define CONFIG_SPL_MAX_SIZE			0x10000
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
#define CONFIG_SPL_BSS_START_ADDR		0x30012000
#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_BSS_START_ADDR		0x30016000
#endif
#define CONFIG_SPL_BSS_MAX_SIZE			0x2000

#define CONFIG_SPL_PAD_TO			0x20000

#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
Commit	Line	Data
5894ca00	1	/*
e8a92932 MY	2	* Copyright (C) 2012-2015 Panasonic Corporation
	3	* Copyright (C) 2015-2016 Socionext Inc.
	4	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5894ca00 MY	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
a187559e	9	/* U-Boot - Common settings for UniPhier Family */
5894ca00 MY	10
	11	#ifndef __CONFIG_UNIPHIER_COMMON_H__
	12	#define __CONFIG_UNIPHIER_COMMON_H__
	13
928f3248	14	#define CONFIG_ARMV7_PSCI_1_0
e8a92932	15
233e42a9 MY	16	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
233e42a9 MY	17
5894ca00 MY	18	/*-----------------------------------------------------------------------
	19	* MMU and Cache Setting
	20	----------------------------------------------------------------------/
	21
	22	/* Comment out the following to enable L1 cache */
	23	/* #define CONFIG_SYS_ICACHE_OFF */
	24	/* #define CONFIG_SYS_DCACHE_OFF */
	25
5894ca00 MY	26	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	27
	28	#define CONFIG_TIMESTAMP
	29
	30	/* FLASH related */
	31	#define CONFIG_MTD_DEVICE
	32
f1d9a9ed MY	33	#define CONFIG_SMC911X_32_BIT
	34	/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
	35	#define CONFIG_SMC911X_BASE 0
	36
	37	#ifdef CONFIG_MICRO_SUPPORT_CARD
	38	#define CONFIG_SMC911X
f4c93a4f	39	#endif
5894ca00 MY	40
	41	#define CONFIG_FLASH_CFI_DRIVER
	42	#define CONFIG_SYS_FLASH_CFI
	43
	44	#define CONFIG_SYS_MAX_FLASH_SECT 256
	45	#define CONFIG_SYS_MONITOR_BASE 0
d085ecd6	46	#define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
5894ca00 MY	47	#define CONFIG_SYS_FLASH_BASE 0
	48
	49	/*
66deb91e	50	* flash_toggle does not work for our support card.
5894ca00 MY	51	* We need to use flash_status_poll.
	52	*/
	53	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
	54
	55	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	56
9879842c	57	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
5894ca00 MY	58
5894ca00 MY	59	/* serial console configuration */
5894ca00	60
5894ca00 MY	61	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	62
	63	#define CONFIG_CMDLINE_EDITING /* add command line history */
5894ca00 MY	64	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	65	/* Print Buffer Size */
	66	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	67	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	68	/* Boot Argument Buffer Size */
	69	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	70
	71	#define CONFIG_CONS_INDEX 1
	72
aa8a9348	73	/* #define CONFIG_ENV_IS_NOWHERE */
5894ca00	74	/* #define CONFIG_ENV_IS_IN_NAND */
aa8a9348	75	#define CONFIG_ENV_IS_IN_MMC
0b93e3de	76	#define CONFIG_ENV_OFFSET 0x100000
5894ca00	77	#define CONFIG_ENV_SIZE 0x2000
5894ca00 MY	78	/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
5894ca00 MY	79
aa8a9348 MY	80	#define CONFIG_SYS_MMC_ENV_DEV 0
	81	#define CONFIG_SYS_MMC_ENV_PART 1
	82
561ca649	83	#ifdef CONFIG_ARMV8_MULTIENTRY
50862a51	84	#define CPU_RELEASE_ADDR 0x80000000
9d0c2ceb MY	85	#define COUNTER_FREQUENCY 50000000
	86	#define CONFIG_GICV3
	87	#define GICD_BASE 0x5fe00000
667dbcd0 MY	88	#if defined(CONFIG_ARCH_UNIPHIER_LD11)
	89	#define GICR_BASE 0x5fe40000
	90	#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
9d0c2ceb	91	#define GICR_BASE 0x5fe80000
667dbcd0	92	#endif
561ca649	93	#elif !defined(CONFIG_ARM64)
5894ca00 MY	94	/* Time clock 1MHz */
5894ca00 MY	95	#define CONFIG_SYS_TIMER_RATE 1000000
9d0c2ceb MY	96	#endif
9d0c2ceb MY	97
5894ca00 MY	98	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	99	#define CONFIG_SYS_NAND_MAX_CHIPS 2
	100	#define CONFIG_SYS_NAND_ONFI_DETECTION
	101
	102	#define CONFIG_NAND_DENALI_ECC_SIZE 1024
	103
ea65c980	104	#ifdef CONFIG_ARCH_UNIPHIER_SLD3
3365b4eb MY	105	#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
	106	#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
	107	#else
5894ca00 MY	108	#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
5894ca00 MY	109	#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
3365b4eb	110	#endif
5894ca00 MY	111
	112	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
	113
	114	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	115	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	116
495deb44	117	/* USB */
53c45d4e	118	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
495deb44	119	#define CONFIG_FAT_WRITE
495deb44	120
4aceb3f8	121	/* SD/MMC */
a55d9fee	122	#define CONFIG_SUPPORT_EMMC_BOOT
4aceb3f8	123
5894ca00 MY	124	/* memtest works on */
	125	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	126	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
	127
5894ca00 MY	128	/*
	129	* Network Configuration
	130	*/
5894ca00 MY	131	#define CONFIG_SERVERIP 192.168.11.1
	132	#define CONFIG_IPADDR 192.168.11.10
	133	#define CONFIG_GATEWAYIP 192.168.11.1
	134	#define CONFIG_NETMASK 255.255.255.0
	135
	136	#define CONFIG_LOADADDR 0x84000000
	137	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
5894ca00 MY	138
	139	#define CONFIG_CMDLINE_EDITING /* add command line history */
	140
b7b43036 MY	141	#if defined(CONFIG_ARM64) && !defined(CONFIG_ARMV8_MULTIENTRY)
	142	/* ARM Trusted Firmware */
	143	#define BOOT_IMAGES \
7728f0c6	144	"second_image=unph_bl.bin\0" \
b7b43036 MY	145	"third_image=fip.bin\0"
	146	#else
	147	#define BOOT_IMAGES \
	148	"second_image=u-boot-spl.bin\0" \
	149	"third_image=u-boot.bin\0"
	150	#endif
	151
5894ca00 MY	152	#define CONFIG_BOOTCOMMAND "run $bootmode"
	153
	154	#define CONFIG_ROOTPATH "/nfs/root/path"
	155	#define CONFIG_NFSBOOTCOMMAND \
	156	"setenv bootargs $bootargs root=/dev/nfs rw " \
	157	"nfsroot=$serverip:$rootpath " \
	158	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
d566f754	159	"run __nfsboot"
5894ca00	160
421376ae MY	161	#ifdef CONFIG_FIT
	162	#define CONFIG_BOOTFILE "fitImage"
	163	#define LINUXBOOT_ENV_SETTINGS \
	164	"fit_addr=0x00100000\0" \
	165	"fit_addr_r=0x84100000\0" \
	166	"fit_size=0x00f00000\0" \
5451b777	167	"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
421376ae	168	"bootm $fit_addr\0" \
5451b777	169	"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
e037db0c	170	"bootm $fit_addr_r\0" \
5451b777	171	"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
d566f754 MY	172	"bootm $fit_addr_r\0" \
d566f754 MY	173	"__nfsboot=run tftpboot\0"
421376ae	174	#else
9d0c2ceb	175	#ifdef CONFIG_ARM64
99b85170	176	#define CONFIG_BOOTFILE "Image.gz"
9d0c2ceb	177	#define LINUXBOOT_CMD "booti"
99b85170	178	#define KERNEL_ADDR_LOAD "kernel_addr_load=0x84200000\0"
9d0c2ceb	179	#define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0"
9d0c2ceb	180	#else
89835b35	181	#define CONFIG_BOOTFILE "zImage"
9d0c2ceb	182	#define LINUXBOOT_CMD "bootz"
99b85170	183	#define KERNEL_ADDR_LOAD "kernel_addr_load=0x80208000\0"
9d0c2ceb	184	#define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0"
9d0c2ceb	185	#endif
421376ae MY	186	#define LINUXBOOT_ENV_SETTINGS \
	187	"fdt_addr=0x00100000\0" \
	188	"fdt_addr_r=0x84100000\0" \
	189	"fdt_size=0x00008000\0" \
	190	"kernel_addr=0x00200000\0" \
99b85170	191	KERNEL_ADDR_LOAD \
9d0c2ceb	192	KERNEL_ADDR_R \
99b85170 MY	193	"kernel_size=0x00800000\0" \
99b85170 MY	194	"ramdisk_addr=0x00a00000\0" \
421376ae MY	195	"ramdisk_addr_r=0x84a00000\0" \
421376ae MY	196	"ramdisk_size=0x00600000\0" \
e037db0c	197	"ramdisk_file=rootfs.cpio.uboot\0" \
99b85170 MY	198	"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \
	199	"if test $kernel_addr_load = $kernel_addr_r; then " \
	200	"true; " \
	201	"else " \
	202	"unzip $kernel_addr_load $kernel_addr_r; " \
	203	"fi && " \
9d0c2ceb	204	LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
99b85170 MY	205	"norboot=setexpr kernel_addr_nor $nor_base + $kernel_addr && " \
	206	"setexpr kernel_size_div4 $kernel_size / 4 && " \
	207	"cp $kernel_addr_nor $kernel_addr_load $kernel_size_div4 && " \
c0df1faf MY	208	"setexpr ramdisk_addr_nor $nor_base + $ramdisk_addr && " \
	209	"setexpr ramdisk_size_div4 $ramdisk_size / 4 && " \
	210	"cp $ramdisk_addr_nor $ramdisk_addr_r $ramdisk_size_div4 && " \
	211	"setexpr fdt_addr_nor $nor_base + $fdt_addr && " \
	212	"setexpr fdt_size_div4 $fdt_size / 4 && " \
	213	"cp $fdt_addr_nor $fdt_addr_r $fdt_size_div4 && " \
cd5d9565	214	"run boot_common\0" \
99b85170	215	"nandboot=nand read $kernel_addr_load $kernel_addr $kernel_size && " \
421376ae MY	216	"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
421376ae MY	217	"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
cd5d9565	218	"run boot_common\0" \
99b85170	219	"tftpboot=tftpboot $kernel_addr_load $bootfile && " \
e037db0c MY	220	"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
e037db0c MY	221	"tftpboot $fdt_addr_r $fdt_file &&" \
d566f754	222	"run boot_common\0" \
99b85170	223	"__nfsboot=tftpboot $kernel_addr_load $bootfile && " \
d566f754 MY	224	"tftpboot $fdt_addr_r $fdt_file &&" \
d566f754 MY	225	"setenv ramdisk_addr_r - &&" \
cd5d9565	226	"run boot_common\0"
421376ae MY	227	#endif
	228
	229	#define CONFIG_EXTRA_ENV_SETTINGS \
	230	"netdev=eth0\0" \
	231	"verify=n\0" \
c0df1faf	232	"initrd_high=0xffffffffffffffff\0" \
90a6e929	233	"nor_base=0x42000000\0" \
61a4f5bd	234	"sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
b7b43036	235	"tftpboot $tmp_addr $second_image && " \
c0efc314	236	"setexpr tmp_addr $nor_base + 0x70000 && " \
b7b43036	237	"tftpboot $tmp_addr $third_image\0" \
c231c436 MY	238	"emmcupdate=mmcsetn &&" \
c231c436 MY	239	"mmc partconf $mmc_first_dev 0 1 1 &&" \
b7b43036	240	"tftpboot $second_image && " \
c0efc314	241	"mmc write $loadaddr 0 100 && " \
b7b43036	242	"tftpboot $third_image && " \
c0efc314	243	"mmc write $loadaddr 100 700\0" \
421376ae	244	"nandupdate=nand erase 0 0x00100000 &&" \
b7b43036	245	"tftpboot $second_image && " \
c0efc314	246	"nand write $loadaddr 0 0x00020000 && " \
b7b43036	247	"tftpboot $third_image && " \
c0efc314	248	"nand write $loadaddr 0x00020000 0x000e0000\0" \
8d3064d9 MY	249	"usbupdate=usb start &&" \
	250	"tftpboot $second_image && " \
	251	"usb write $loadaddr 0 100 && " \
	252	"tftpboot $third_image && " \
	253	"usb write $loadaddr 100 700\0" \
b7b43036	254	BOOT_IMAGES \
421376ae	255	LINUXBOOT_ENV_SETTINGS
5894ca00	256
17bd4a21 MY	257	#define CONFIG_SYS_BOOTMAPSZ 0x20000000
17bd4a21 MY	258
cf88affa	259	#define CONFIG_SYS_SDRAM_BASE 0x80000000
3e9952be	260	#define CONFIG_NR_DRAM_BANKS 3
23869698 MY	261	/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
23869698 MY	262	#define CONFIG_SYS_MEM_TOP_HIDE 64
5894ca00	263
3e0cfaa0 MY	264	#define CONFIG_PANIC_HANG
	265
	266	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
	267
	268	/* only for SPL */
9d0c2ceb MY	269	#if defined(CONFIG_ARM64)
	270	#define CONFIG_SPL_TEXT_BASE 0x30000000
	271	#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) \|\| \
	272	defined(CONFIG_ARCH_UNIPHIER_LD4) \|\| \
ea65c980	273	defined(CONFIG_ARCH_UNIPHIER_SLD8)
f5d0b9b2	274	#define CONFIG_SPL_TEXT_BASE 0x00040000
323d1f9d	275	#else
f5d0b9b2 MY	276	#define CONFIG_SPL_TEXT_BASE 0x00100000
	277	#endif
	278
667dbcd0 MY	279	#if defined(CONFIG_ARCH_UNIPHIER_LD11)
	280	#define CONFIG_SPL_STACK (0x30014c00)
	281	#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
9d0c2ceb MY	282	#define CONFIG_SPL_STACK (0x3001c000)
9d0c2ceb MY	283	#else
755c7d9a	284	#define CONFIG_SPL_STACK (0x00100000)
9d0c2ceb	285	#endif
a286039b	286
5894ca00	287	#define CONFIG_SPL_FRAMEWORK
adb3928f MY	288	#ifdef CONFIG_ARM64
adb3928f MY	289	#define CONFIG_SPL_BOARD_LOAD_IMAGE
9d0c2ceb	290	#endif
5894ca00	291
5894ca00 MY	292	#define CONFIG_SPL_BOARD_INIT
5894ca00 MY	293
c0efc314	294	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
cbbc2d80	295
d085ecd6	296	/* subtract sizeof(struct image_header) */
c0efc314	297	#define CONFIG_SYS_UBOOT_BASE (0x70000 - 0x40)
5894ca00	298
d085ecd6	299	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
6a3cffe8	300	#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
c0efc314 MY	301	#if defined(CONFIG_ARCH_UNIPHIER_LD20)
	302	#define CONFIG_SPL_MAX_SIZE 0x14000
	303	#else
86c3345a	304	#define CONFIG_SPL_MAX_SIZE 0x10000
c0efc314	305	#endif
667dbcd0 MY	306	#if defined(CONFIG_ARCH_UNIPHIER_LD11)
	307	#define CONFIG_SPL_BSS_START_ADDR 0x30012000
	308	#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
9d0c2ceb	309	#define CONFIG_SPL_BSS_START_ADDR 0x30016000
667dbcd0	310	#endif
9d0c2ceb	311	#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
6a3cffe8	312
c0efc314 MY	313	#define CONFIG_SPL_PAD_TO 0x20000
c0efc314 MY	314
5894ca00	315	#endif /* __CONFIG_UNIPHIER_COMMON_H__ */