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mmc: omap_hsmmc: cleanup clock configuration
[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c
CommitLineData
de941241
SG		 1/*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <common.h>
93bfd616 27#include <malloc.h>
f0d53e88 28#include <memalign.h>
de941241
SG		 29#include <mmc.h>
30#include <part.h>
31#include <i2c.h>
339d5789 32#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
cb199102 33#include <palmas.h>
339d5789 34#endif
de941241
SG		 35#include <asm/io.h>
36#include <asm/arch/mmc_host_def.h>
3b68939f
RQ		 37#if !defined(CONFIG_SOC_KEYSTONE)
38#include <asm/gpio.h>
96e0e7b3 39#include <asm/arch/sys_proto.h>
3b68939f 40#endif
2a48b3a2
TR		 41#ifdef CONFIG_MMC_OMAP36XX_PINS
42#include <asm/arch/mux.h>
43#endif
a9d6a7e2
M		 44#include <dm.h>
45
46DECLARE_GLOBAL_DATA_PTR;
de941241 47
ab769f22
PA		 48/* simplify defines to OMAP_HSMMC_USE_GPIO */
49#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
50 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
51#define OMAP_HSMMC_USE_GPIO
52#else
53#undef OMAP_HSMMC_USE_GPIO
54#endif
55
25c719e2
GI		 56/* common definitions for all OMAPs */
57#define SYSCTL_SRC (1 << 25)
58#define SYSCTL_SRD (1 << 26)
59
cc22b0c0
NK		 60struct omap_hsmmc_data {
61 struct hsmmc *base_addr;
c4d660d4 62#if !CONFIG_IS_ENABLED(DM_MMC)
93bfd616 63 struct mmc_config cfg;
3d673ffc 64#endif
5baf543e 65 uint clock;
ab769f22 66#ifdef OMAP_HSMMC_USE_GPIO
c4d660d4 67#if CONFIG_IS_ENABLED(DM_MMC)
a9d6a7e2
M		 68 struct gpio_desc cd_gpio; /* Change Detect GPIO */
69 struct gpio_desc wp_gpio; /* Write Protect GPIO */
70 bool cd_inverted;
71#else
e874d5b0 72 int cd_gpio;
e3913f56 73 int wp_gpio;
ab769f22 74#endif
a9d6a7e2 75#endif
f0d53e88
KVA		 76 u8 controller_flags;
77#ifndef CONFIG_OMAP34XX
78 struct omap_hsmmc_adma_desc *adma_desc_table;
79 uint desc_slot;
80#endif
81};
82
83#ifndef CONFIG_OMAP34XX
84struct omap_hsmmc_adma_desc {
85 u8 attr;
86 u8 reserved;
87 u16 len;
88 u32 addr;
cc22b0c0
NK		 89};
90
f0d53e88
KVA		 91#define ADMA_MAX_LEN 63488
92
93/* Decriptor table defines */
94#define ADMA_DESC_ATTR_VALID BIT(0)
95#define ADMA_DESC_ATTR_END BIT(1)
96#define ADMA_DESC_ATTR_INT BIT(2)
97#define ADMA_DESC_ATTR_ACT1 BIT(4)
98#define ADMA_DESC_ATTR_ACT2 BIT(5)
99
100#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
101#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
102#endif
103
eb9a28f6
NM		 104/* If we fail after 1 second wait, something is really bad */
105#define MAX_RETRY_MS 1000
106
f0d53e88
KVA		 107/* DMA transfers can take a long time if a lot a data is transferred.
108 * The timeout must take in account the amount of data. Let's assume
109 * that the time will never exceed 333 ms per MB (in other word we assume
110 * that the bandwidth is always above 3MB/s).
111 */
112#define DMA_TIMEOUT_PER_MB 333
113#define OMAP_HSMMC_USE_ADMA BIT(2)
114
933efe64
S		 115static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
116static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
117 unsigned int siz);
5baf543e
JJH		 118static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
119static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
14fa2dd0 120
ae000e23
JJH		 121static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
122{
c4d660d4 123#if CONFIG_IS_ENABLED(DM_MMC)
ae000e23
JJH		 124 return dev_get_priv(mmc->dev);
125#else
126 return (struct omap_hsmmc_data *)mmc->priv;
127#endif
3d673ffc
JJH		 128}
129static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
130{
c4d660d4 131#if CONFIG_IS_ENABLED(DM_MMC)
3d673ffc
JJH		 132 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
133 return &plat->cfg;
134#else
135 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
136#endif
ae000e23
JJH		 137}
138
c4d660d4 139#if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
e874d5b0
NK		 140static int omap_mmc_setup_gpio_in(int gpio, const char *label)
141{
5915a2ad 142 int ret;
e874d5b0 143
5915a2ad
SG		 144#ifndef CONFIG_DM_GPIO
145 if (!gpio_is_valid(gpio))
e874d5b0 146 return -1;
5915a2ad
SG		 147#endif
148 ret = gpio_request(gpio, label);
149 if (ret)
150 return ret;
e874d5b0 151
5915a2ad
SG		 152 ret = gpio_direction_input(gpio);
153 if (ret)
154 return ret;
e874d5b0
NK		 155
156 return gpio;
157}
e874d5b0
NK		 158#endif
159
750121c3 160static unsigned char mmc_board_init(struct mmc *mmc)
de941241 161{
de941241 162#if defined(CONFIG_OMAP34XX)
3d673ffc 163 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
de941241
SG		 164 t2_t *t2_base = (t2_t *)T2_BASE;
165 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
b1e725f2 166 u32 pbias_lite;
6aca17c9
AF		 167#ifdef CONFIG_MMC_OMAP36XX_PINS
168 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
169#endif
de941241 170
b1e725f2
GI		 171 pbias_lite = readl(&t2_base->pbias_lite);
172 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
5bfdd1fc
AA		 173#ifdef CONFIG_TARGET_OMAP3_CAIRO
174 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
175 pbias_lite &= ~PBIASLITEVMODE0;
6aca17c9
AF		 176#endif
177#ifdef CONFIG_MMC_OMAP36XX_PINS
178 if (get_cpu_family() == CPU_OMAP36XX) {
179 /* Disable extended drain IO before changing PBIAS */
180 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
181 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
182 }
5bfdd1fc 183#endif
b1e725f2 184 writel(pbias_lite, &t2_base->pbias_lite);
aac5450e 185
b1e725f2 186 writel(pbias_lite | PBIASLITEPWRDNZ1 |
de941241
SG		 187 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
188 &t2_base->pbias_lite);
189
6aca17c9
AF		 190#ifdef CONFIG_MMC_OMAP36XX_PINS
191 if (get_cpu_family() == CPU_OMAP36XX)
192 /* Enable extended drain IO after changing PBIAS */
193 writel(wkup_ctrl |
194 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
195 OMAP34XX_CTRL_WKUP_CTRL);
196#endif
de941241
SG		 197 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
198 &t2_base->devconf0);
199
200 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
201 &t2_base->devconf1);
202
bbbc1ae9 203 /* Change from default of 52MHz to 26MHz if necessary */
3d673ffc 204 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
bbbc1ae9
JS		 205 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
206 &t2_base->ctl_prog_io1);
207
de941241
SG		 208 writel(readl(&prcm_base->fclken1_core) |
209 EN_MMC1 | EN_MMC2 | EN_MMC3,
210 &prcm_base->fclken1_core);
211
212 writel(readl(&prcm_base->iclken1_core) |
213 EN_MMC1 | EN_MMC2 | EN_MMC3,
214 &prcm_base->iclken1_core);
215#endif
216
b4b06006 217#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
14fa2dd0 218 /* PBIAS config needed for MMC1 only */
dc09127a 219 if (mmc_get_blk_desc(mmc)->devnum == 0)
b4b06006 220 vmmc_pbias_config(LDO_VOLT_3V0);
dd23e59d 221#endif
de941241
SG		 222
223 return 0;
224}
225
933efe64 226void mmc_init_stream(struct hsmmc *mmc_base)
de941241 227{
eb9a28f6 228 ulong start;
de941241
SG		 229
230 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
231
232 writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6
NM		 233 start = get_timer(0);
234 while (!(readl(&mmc_base->stat) & CC_MASK)) {
235 if (get_timer(0) - start > MAX_RETRY_MS) {
236 printf("%s: timedout waiting for cc!\n", __func__);
237 return;
238 }
239 }
de941241
SG		 240 writel(CC_MASK, &mmc_base->stat)
241 ;
242 writel(MMC_CMD0, &mmc_base->cmd)
243 ;
eb9a28f6
NM		 244 start = get_timer(0);
245 while (!(readl(&mmc_base->stat) & CC_MASK)) {
246 if (get_timer(0) - start > MAX_RETRY_MS) {
247 printf("%s: timedout waiting for cc2!\n", __func__);
248 return;
249 }
250 }
de941241
SG		 251 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
252}
253
ab769f22 254static int omap_hsmmc_init_setup(struct mmc *mmc)
de941241 255{
ae000e23 256 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
cc22b0c0 257 struct hsmmc *mmc_base;
de941241
SG		 258 unsigned int reg_val;
259 unsigned int dsor;
eb9a28f6 260 ulong start;
de941241 261
ae000e23 262 mmc_base = priv->base_addr;
14fa2dd0 263 mmc_board_init(mmc);
de941241
SG		 264
265 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
266 &mmc_base->sysconfig);
eb9a28f6
NM		 267 start = get_timer(0);
268 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
269 if (get_timer(0) - start > MAX_RETRY_MS) {
270 printf("%s: timedout waiting for cc2!\n", __func__);
915ffa52 271 return -ETIMEDOUT;
eb9a28f6
NM		 272 }
273 }
de941241 274 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6
NM		 275 start = get_timer(0);
276 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
277 if (get_timer(0) - start > MAX_RETRY_MS) {
278 printf("%s: timedout waiting for softresetall!\n",
279 __func__);
915ffa52 280 return -ETIMEDOUT;
eb9a28f6
NM		 281 }
282 }
f0d53e88
KVA		 283#ifndef CONFIG_OMAP34XX
284 reg_val = readl(&mmc_base->hl_hwinfo);
285 if (reg_val & MADMA_EN)
286 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
287#endif
de941241
SG		 288 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
289 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
290 &mmc_base->capa);
291
292 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
293
294 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
295 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
296 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
297
298 dsor = 240;
299 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
29171dcf 300 (ICE_STOP | DTO_15THDTO));
de941241
SG		 301 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
302 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
eb9a28f6
NM		 303 start = get_timer(0);
304 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
305 if (get_timer(0) - start > MAX_RETRY_MS) {
306 printf("%s: timedout waiting for ics!\n", __func__);
915ffa52 307 return -ETIMEDOUT;
eb9a28f6
NM		 308 }
309 }
de941241
SG		 310 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
311
312 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
313
314 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
f0d53e88
KVA		 315 IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
316 IE_CC, &mmc_base->ie);
de941241
SG		 317
318 mmc_init_stream(mmc_base);
319
320 return 0;
321}
322
25c719e2
GI		 323/*
324 * MMC controller internal finite state machine reset
325 *
326 * Used to reset command or data internal state machines, using respectively
327 * SRC or SRD bit of SYSCTL register
328 */
329static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
330{
331 ulong start;
332
333 mmc_reg_out(&mmc_base->sysctl, bit, bit);
334
61a6cc27
OT		 335 /*
336 * CMD(DAT) lines reset procedures are slightly different
337 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
338 * According to OMAP3 TRM:
339 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
340 * returns to 0x0.
341 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
342 * procedure steps must be as follows:
343 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
344 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
345 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
346 * 3. Wait until the SRC (SRD) bit returns to 0x0
347 * (reset procedure is completed).
348 */
349#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
dce55b93 350 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
61a6cc27
OT		 351 if (!(readl(&mmc_base->sysctl) & bit)) {
352 start = get_timer(0);
353 while (!(readl(&mmc_base->sysctl) & bit)) {
354 if (get_timer(0) - start > MAX_RETRY_MS)
355 return;
356 }
357 }
358#endif
25c719e2
GI		 359 start = get_timer(0);
360 while ((readl(&mmc_base->sysctl) & bit) != 0) {
361 if (get_timer(0) - start > MAX_RETRY_MS) {
362 printf("%s: timedout waiting for sysctl %x to clear\n",
363 __func__, bit);
364 return;
365 }
366 }
367}
f0d53e88
KVA		 368
369#ifndef CONFIG_OMAP34XX
370static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
371{
372 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
373 struct omap_hsmmc_adma_desc *desc;
374 u8 attr;
375
376 desc = &priv->adma_desc_table[priv->desc_slot];
377
378 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
379 if (!end)
380 priv->desc_slot++;
381 else
382 attr |= ADMA_DESC_ATTR_END;
383
384 desc->len = len;
385 desc->addr = (u32)buf;
386 desc->reserved = 0;
387 desc->attr = attr;
388}
389
390static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
391 struct mmc_data *data)
392{
393 uint total_len = data->blocksize * data->blocks;
394 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
395 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
396 int i = desc_count;
397 char *buf;
398
399 priv->desc_slot = 0;
400 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
401 memalign(ARCH_DMA_MINALIGN, desc_count *
402 sizeof(struct omap_hsmmc_adma_desc));
403
404 if (data->flags & MMC_DATA_READ)
405 buf = data->dest;
406 else
407 buf = (char *)data->src;
408
409 while (--i) {
410 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
411 buf += ADMA_MAX_LEN;
412 total_len -= ADMA_MAX_LEN;
413 }
414
415 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
416
417 flush_dcache_range((long)priv->adma_desc_table,
418 (long)priv->adma_desc_table +
419 ROUND(desc_count *
420 sizeof(struct omap_hsmmc_adma_desc),
421 ARCH_DMA_MINALIGN));
422}
423
424static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
425{
426 struct hsmmc *mmc_base;
427 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
428 u32 val;
429 char *buf;
430
431 mmc_base = priv->base_addr;
432 omap_hsmmc_prepare_adma_table(mmc, data);
433
434 if (data->flags & MMC_DATA_READ)
435 buf = data->dest;
436 else
437 buf = (char *)data->src;
438
439 val = readl(&mmc_base->hctl);
440 val |= DMA_SELECT;
441 writel(val, &mmc_base->hctl);
442
443 val = readl(&mmc_base->con);
444 val |= DMA_MASTER;
445 writel(val, &mmc_base->con);
446
447 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
448
449 flush_dcache_range((u32)buf,
450 (u32)buf +
451 ROUND(data->blocksize * data->blocks,
452 ARCH_DMA_MINALIGN));
453}
454
455static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
456{
457 struct hsmmc *mmc_base;
458 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
459 u32 val;
460
461 mmc_base = priv->base_addr;
462
463 val = readl(&mmc_base->con);
464 val &= ~DMA_MASTER;
465 writel(val, &mmc_base->con);
466
467 val = readl(&mmc_base->hctl);
468 val &= ~DMA_SELECT;
469 writel(val, &mmc_base->hctl);
470
471 kfree(priv->adma_desc_table);
472}
473#else
474#define omap_hsmmc_adma_desc
475#define omap_hsmmc_prepare_adma_table
476#define omap_hsmmc_prepare_data
477#define omap_hsmmc_dma_cleanup
478#endif
479
c4d660d4 480#if !CONFIG_IS_ENABLED(DM_MMC)
ab769f22 481static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
de941241
SG		 482 struct mmc_data *data)
483{
ae000e23 484 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
b5511d6c
JJH		 485#else
486static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
487 struct mmc_data *data)
488{
489 struct omap_hsmmc_data *priv = dev_get_priv(dev);
f0d53e88
KVA		 490#ifndef CONFIG_OMAP34XX
491 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
492 struct mmc *mmc = upriv->mmc;
493#endif
b5511d6c 494#endif
cc22b0c0 495 struct hsmmc *mmc_base;
de941241 496 unsigned int flags, mmc_stat;
eb9a28f6 497 ulong start;
de941241 498
ae000e23 499 mmc_base = priv->base_addr;
866bb984
KVA		 500
501 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
502 return 0;
503
eb9a28f6 504 start = get_timer(0);
a7778f8f 505 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
eb9a28f6 506 if (get_timer(0) - start > MAX_RETRY_MS) {
a7778f8f
TR		 507 printf("%s: timedout waiting on cmd inhibit to clear\n",
508 __func__);
915ffa52 509 return -ETIMEDOUT;
eb9a28f6
NM		 510 }
511 }
de941241 512 writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6
NM		 513 start = get_timer(0);
514 while (readl(&mmc_base->stat)) {
515 if (get_timer(0) - start > MAX_RETRY_MS) {
15ceb1de
GI		 516 printf("%s: timedout waiting for STAT (%x) to clear\n",
517 __func__, readl(&mmc_base->stat));
915ffa52 518 return -ETIMEDOUT;
eb9a28f6
NM		 519 }
520 }
de941241
SG		 521 /*
522 * CMDREG
523 * CMDIDX[13:8] : Command index
524 * DATAPRNT[5] : Data Present Select
525 * ENCMDIDX[4] : Command Index Check Enable
526 * ENCMDCRC[3] : Command CRC Check Enable
527 * RSPTYP[1:0]
528 * 00 = No Response
529 * 01 = Length 136
530 * 10 = Length 48
531 * 11 = Length 48 Check busy after response
532 */
533 /* Delay added before checking the status of frq change
534 * retry not supported by mmc.c(core file)
535 */
536 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
537 udelay(50000); /* wait 50 ms */
538
539 if (!(cmd->resp_type & MMC_RSP_PRESENT))
540 flags = 0;
541 else if (cmd->resp_type & MMC_RSP_136)
542 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
543 else if (cmd->resp_type & MMC_RSP_BUSY)
544 flags = RSP_TYPE_LGHT48B;
545 else
546 flags = RSP_TYPE_LGHT48;
547
548 /* enable default flags */
549 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
29171dcf
KVA		 550 MSBS_SGLEBLK);
551 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
de941241
SG		 552
553 if (cmd->resp_type & MMC_RSP_CRC)
554 flags |= CCCE_CHECK;
555 if (cmd->resp_type & MMC_RSP_OPCODE)
556 flags |= CICE_CHECK;
557
558 if (data) {
559 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
560 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
866bb984 561 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
de941241
SG		 562 data->blocksize = 512;
563 writel(data->blocksize | (data->blocks << 16),
564 &mmc_base->blk);
565 } else
566 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
567
568 if (data->flags & MMC_DATA_READ)
569 flags |= (DP_DATA | DDIR_READ);
570 else
571 flags |= (DP_DATA | DDIR_WRITE);
f0d53e88
KVA		 572
573#ifndef CONFIG_OMAP34XX
574 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
575 !mmc_is_tuning_cmd(cmd->cmdidx)) {
576 omap_hsmmc_prepare_data(mmc, data);
577 flags |= DE_ENABLE;
578 }
579#endif
de941241
SG		 580 }
581
582 writel(cmd->cmdarg, &mmc_base->arg);
152ba363 583 udelay(20); /* To fix "No status update" error on eMMC */
de941241
SG		 584 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
585
eb9a28f6 586 start = get_timer(0);
de941241
SG		 587 do {
588 mmc_stat = readl(&mmc_base->stat);
f0d53e88 589 if (get_timer(start) > MAX_RETRY_MS) {
eb9a28f6 590 printf("%s : timeout: No status update\n", __func__);
915ffa52 591 return -ETIMEDOUT;
eb9a28f6
NM		 592 }
593 } while (!mmc_stat);
de941241 594
25c719e2
GI		 595 if ((mmc_stat & IE_CTO) != 0) {
596 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
915ffa52 597 return -ETIMEDOUT;
25c719e2 598 } else if ((mmc_stat & ERRI_MASK) != 0)
de941241
SG		 599 return -1;
600
601 if (mmc_stat & CC_MASK) {
602 writel(CC_MASK, &mmc_base->stat);
603 if (cmd->resp_type & MMC_RSP_PRESENT) {
604 if (cmd->resp_type & MMC_RSP_136) {
605 /* response type 2 */
606 cmd->response[3] = readl(&mmc_base->rsp10);
607 cmd->response[2] = readl(&mmc_base->rsp32);
608 cmd->response[1] = readl(&mmc_base->rsp54);
609 cmd->response[0] = readl(&mmc_base->rsp76);
610 } else
611 /* response types 1, 1b, 3, 4, 5, 6 */
612 cmd->response[0] = readl(&mmc_base->rsp10);
613 }
614 }
615
f0d53e88
KVA		 616#ifndef CONFIG_OMAP34XX
617 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
618 !mmc_is_tuning_cmd(cmd->cmdidx)) {
619 u32 sz_mb, timeout;
620
621 if (mmc_stat & IE_ADMAE) {
622 omap_hsmmc_dma_cleanup(mmc);
623 return -EIO;
624 }
625
626 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
627 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
628 if (timeout < MAX_RETRY_MS)
629 timeout = MAX_RETRY_MS;
630
631 start = get_timer(0);
632 do {
633 mmc_stat = readl(&mmc_base->stat);
634 if (mmc_stat & TC_MASK) {
635 writel(readl(&mmc_base->stat) | TC_MASK,
636 &mmc_base->stat);
637 break;
638 }
639 if (get_timer(start) > timeout) {
640 printf("%s : DMA timeout: No status update\n",
641 __func__);
642 return -ETIMEDOUT;
643 }
644 } while (1);
645
646 omap_hsmmc_dma_cleanup(mmc);
647 return 0;
648 }
649#endif
650
de941241
SG		 651 if (data && (data->flags & MMC_DATA_READ)) {
652 mmc_read_data(mmc_base, data->dest,
653 data->blocksize * data->blocks);
654 } else if (data && (data->flags & MMC_DATA_WRITE)) {
655 mmc_write_data(mmc_base, data->src,
656 data->blocksize * data->blocks);
657 }
658 return 0;
659}
660
933efe64 661static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
de941241
SG		 662{
663 unsigned int *output_buf = (unsigned int *)buf;
664 unsigned int mmc_stat;
665 unsigned int count;
666
667 /*
668 * Start Polled Read
669 */
670 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
671 count /= 4;
672
673 while (size) {
eb9a28f6 674 ulong start = get_timer(0);
de941241
SG		 675 do {
676 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 677 if (get_timer(0) - start > MAX_RETRY_MS) {
678 printf("%s: timedout waiting for status!\n",
679 __func__);
915ffa52 680 return -ETIMEDOUT;
eb9a28f6 681 }
de941241
SG		 682 } while (mmc_stat == 0);
683
25c719e2
GI		 684 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
685 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
686
de941241
SG		 687 if ((mmc_stat & ERRI_MASK) != 0)
688 return 1;
689
690 if (mmc_stat & BRR_MASK) {
691 unsigned int k;
692
693 writel(readl(&mmc_base->stat) | BRR_MASK,
694 &mmc_base->stat);
695 for (k = 0; k < count; k++) {
696 *output_buf = readl(&mmc_base->data);
697 output_buf++;
698 }
699 size -= (count*4);
700 }
701
702 if (mmc_stat & BWR_MASK)
703 writel(readl(&mmc_base->stat) | BWR_MASK,
704 &mmc_base->stat);
705
706 if (mmc_stat & TC_MASK) {
707 writel(readl(&mmc_base->stat) | TC_MASK,
708 &mmc_base->stat);
709 break;
710 }
711 }
712 return 0;
713}
714
933efe64
S		 715static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
716 unsigned int size)
de941241
SG		 717{
718 unsigned int *input_buf = (unsigned int *)buf;
719 unsigned int mmc_stat;
720 unsigned int count;
721
722 /*
152ba363 723 * Start Polled Write
de941241
SG		 724 */
725 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
726 count /= 4;
727
728 while (size) {
eb9a28f6 729 ulong start = get_timer(0);
de941241
SG		 730 do {
731 mmc_stat = readl(&mmc_base->stat);
eb9a28f6
NM		 732 if (get_timer(0) - start > MAX_RETRY_MS) {
733 printf("%s: timedout waiting for status!\n",
734 __func__);
915ffa52 735 return -ETIMEDOUT;
eb9a28f6 736 }
de941241
SG		 737 } while (mmc_stat == 0);
738
25c719e2
GI		 739 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
740 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
741
de941241
SG		 742 if ((mmc_stat & ERRI_MASK) != 0)
743 return 1;
744
745 if (mmc_stat & BWR_MASK) {
746 unsigned int k;
747
748 writel(readl(&mmc_base->stat) | BWR_MASK,
749 &mmc_base->stat);
750 for (k = 0; k < count; k++) {
751 writel(*input_buf, &mmc_base->data);
752 input_buf++;
753 }
754 size -= (count*4);
755 }
756
757 if (mmc_stat & BRR_MASK)
758 writel(readl(&mmc_base->stat) | BRR_MASK,
759 &mmc_base->stat);
760
761 if (mmc_stat & TC_MASK) {
762 writel(readl(&mmc_base->stat) | TC_MASK,
763 &mmc_base->stat);
764 break;
765 }
766 }
767 return 0;
768}
769
5baf543e
JJH		 770static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
771{
772 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
773}
774
775static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
776{
777 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
778}
779
780static void omap_hsmmc_set_clock(struct mmc *mmc)
781{
782 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
783 struct hsmmc *mmc_base;
784 unsigned int dsor = 0;
785 ulong start;
786
787 mmc_base = priv->base_addr;
788 omap_hsmmc_stop_clock(mmc_base);
789
790 /* TODO: Is setting DTO required here? */
791 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
792 (ICE_STOP | DTO_15THDTO));
793
794 if (mmc->clock != 0) {
795 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
796 if (dsor > CLKD_MAX)
797 dsor = CLKD_MAX;
798 } else {
799 dsor = CLKD_MAX;
800 }
801
802 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
803 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
804
805 start = get_timer(0);
806 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
807 if (get_timer(0) - start > MAX_RETRY_MS) {
808 printf("%s: timedout waiting for ics!\n", __func__);
809 return;
810 }
811 }
812
813 priv->clock = mmc->clock;
814 omap_hsmmc_start_clock(mmc_base);
815}
816
c4d660d4 817#if !CONFIG_IS_ENABLED(DM_MMC)
07b0b9c0 818static int omap_hsmmc_set_ios(struct mmc *mmc)
de941241 819{
ae000e23 820 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
b5511d6c
JJH		 821#else
822static int omap_hsmmc_set_ios(struct udevice *dev)
823{
824 struct omap_hsmmc_data *priv = dev_get_priv(dev);
825 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
826 struct mmc *mmc = upriv->mmc;
827#endif
cc22b0c0 828 struct hsmmc *mmc_base;
de941241 829
ae000e23 830 mmc_base = priv->base_addr;
de941241
SG		 831 /* configue bus width */
832 switch (mmc->bus_width) {
833 case 8:
834 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
835 &mmc_base->con);
836 break;
837
838 case 4:
839 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
840 &mmc_base->con);
841 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
842 &mmc_base->hctl);
843 break;
844
845 case 1:
846 default:
847 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
848 &mmc_base->con);
849 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
850 &mmc_base->hctl);
851 break;
852 }
853
5baf543e
JJH		 854 if (priv->clock != mmc->clock)
855 omap_hsmmc_set_clock(mmc);
07b0b9c0
JC		 856
857 return 0;
de941241
SG		 858}
859
ab769f22 860#ifdef OMAP_HSMMC_USE_GPIO
c4d660d4 861#if CONFIG_IS_ENABLED(DM_MMC)
b5511d6c 862static int omap_hsmmc_getcd(struct udevice *dev)
a9d6a7e2 863{
b5511d6c 864 struct omap_hsmmc_data *priv = dev_get_priv(dev);
a9d6a7e2
M		 865 int value;
866
867 value = dm_gpio_get_value(&priv->cd_gpio);
868 /* if no CD return as 1 */
869 if (value < 0)
870 return 1;
871
872 if (priv->cd_inverted)
873 return !value;
874 return value;
875}
876
b5511d6c 877static int omap_hsmmc_getwp(struct udevice *dev)
a9d6a7e2 878{
b5511d6c 879 struct omap_hsmmc_data *priv = dev_get_priv(dev);
a9d6a7e2
M		 880 int value;
881
882 value = dm_gpio_get_value(&priv->wp_gpio);
883 /* if no WP return as 0 */
884 if (value < 0)
885 return 0;
886 return value;
887}
888#else
ab769f22
PA		 889static int omap_hsmmc_getcd(struct mmc *mmc)
890{
ae000e23 891 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
ab769f22
PA		 892 int cd_gpio;
893
894 /* if no CD return as 1 */
ae000e23 895 cd_gpio = priv->cd_gpio;
ab769f22
PA		 896 if (cd_gpio < 0)
897 return 1;
898
0b03a931
IG		 899 /* NOTE: assumes card detect signal is active-low */
900 return !gpio_get_value(cd_gpio);
ab769f22
PA		 901}
902
903static int omap_hsmmc_getwp(struct mmc *mmc)
904{
ae000e23 905 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
ab769f22
PA		 906 int wp_gpio;
907
908 /* if no WP return as 0 */
ae000e23 909 wp_gpio = priv->wp_gpio;
ab769f22
PA		 910 if (wp_gpio < 0)
911 return 0;
912
0b03a931 913 /* NOTE: assumes write protect signal is active-high */
ab769f22
PA		 914 return gpio_get_value(wp_gpio);
915}
916#endif
a9d6a7e2 917#endif
ab769f22 918
c4d660d4 919#if CONFIG_IS_ENABLED(DM_MMC)
b5511d6c
JJH		 920static const struct dm_mmc_ops omap_hsmmc_ops = {
921 .send_cmd = omap_hsmmc_send_cmd,
922 .set_ios = omap_hsmmc_set_ios,
923#ifdef OMAP_HSMMC_USE_GPIO
924 .get_cd = omap_hsmmc_getcd,
925 .get_wp = omap_hsmmc_getwp,
926#endif
927};
928#else
ab769f22
PA		 929static const struct mmc_ops omap_hsmmc_ops = {
930 .send_cmd = omap_hsmmc_send_cmd,
931 .set_ios = omap_hsmmc_set_ios,
932 .init = omap_hsmmc_init_setup,
933#ifdef OMAP_HSMMC_USE_GPIO
934 .getcd = omap_hsmmc_getcd,
935 .getwp = omap_hsmmc_getwp,
936#endif
937};
b5511d6c 938#endif
ab769f22 939
c4d660d4 940#if !CONFIG_IS_ENABLED(DM_MMC)
e3913f56
NK		 941int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
942 int wp_gpio)
de941241 943{
93bfd616 944 struct mmc *mmc;
ae000e23 945 struct omap_hsmmc_data *priv;
93bfd616
PA		 946 struct mmc_config *cfg;
947 uint host_caps_val;
948
ae000e23
JJH		 949 priv = malloc(sizeof(*priv));
950 if (priv == NULL)
93bfd616 951 return -1;
de941241 952
5a20397b 953 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
de941241
SG		 954
955 switch (dev_index) {
956 case 0:
ae000e23 957 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 958 break;
1037d585 959#ifdef OMAP_HSMMC2_BASE
de941241 960 case 1:
ae000e23 961 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
152ba363 962#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
3891a54f 963 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
3b68939f
RQ		 964 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
965 defined(CONFIG_HSMMC2_8BIT)
152ba363
LP		 966 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
967 host_caps_val |= MMC_MODE_8BIT;
968#endif
de941241 969 break;
1037d585
TR		 970#endif
971#ifdef OMAP_HSMMC3_BASE
de941241 972 case 2:
ae000e23 973 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
3891a54f 974#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
152ba363
LP		 975 /* Enable 8-bit interface for eMMC on DRA7XX */
976 host_caps_val |= MMC_MODE_8BIT;
977#endif
de941241 978 break;
1037d585 979#endif
de941241 980 default:
ae000e23 981 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241
SG		 982 return 1;
983 }
ab769f22
PA		 984#ifdef OMAP_HSMMC_USE_GPIO
985 /* on error gpio values are set to -1, which is what we want */
ae000e23
JJH		 986 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
987 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
ab769f22 988#endif
173ddc5b 989
ae000e23 990 cfg = &priv->cfg;
de941241 991
93bfd616
PA		 992 cfg->name = "OMAP SD/MMC";
993 cfg->ops = &omap_hsmmc_ops;
994
995 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
996 cfg->host_caps = host_caps_val & ~host_caps_mask;
997
998 cfg->f_min = 400000;
bbbc1ae9
JS		 999
1000 if (f_max != 0)
93bfd616 1001 cfg->f_max = f_max;
bbbc1ae9 1002 else {
93bfd616
PA		 1003 if (cfg->host_caps & MMC_MODE_HS) {
1004 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1005 cfg->f_max = 52000000;
bbbc1ae9 1006 else
93bfd616 1007 cfg->f_max = 26000000;
bbbc1ae9 1008 } else
93bfd616 1009 cfg->f_max = 20000000;
bbbc1ae9 1010 }
de941241 1011
93bfd616 1012 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
8feafcc4 1013
4ca9244d
JR		 1014#if defined(CONFIG_OMAP34XX)
1015 /*
1016 * Silicon revs 2.1 and older do not support multiblock transfers.
1017 */
1018 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
93bfd616 1019 cfg->b_max = 1;
4ca9244d 1020#endif
ae000e23 1021 mmc = mmc_create(cfg, priv);
93bfd616
PA		 1022 if (mmc == NULL)
1023 return -1;
de941241
SG		 1024
1025 return 0;
1026}
a9d6a7e2 1027#else
2558c049 1028#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2
M		 1029static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1030{
3d673ffc
JJH		 1031 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1032 struct mmc_config *cfg = &plat->cfg;
a9d6a7e2 1033 const void *fdt = gd->fdt_blob;
e160f7d4 1034 int node = dev_of_offset(dev);
a9d6a7e2
M		 1035 int val;
1036
a821c4af
SG		 1037 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1038 sizeof(struct hsmmc *),
741726ae 1039 MAP_NOCACHE);
a9d6a7e2
M		 1040
1041 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
1042 val = fdtdec_get_int(fdt, node, "bus-width", -1);
1043 if (val < 0) {
1044 printf("error: bus-width property missing\n");
1045 return -ENOENT;
1046 }
1047
1048 switch (val) {
1049 case 0x8:
1050 cfg->host_caps |= MMC_MODE_8BIT;
1051 case 0x4:
1052 cfg->host_caps |= MMC_MODE_4BIT;
1053 break;
1054 default:
1055 printf("error: invalid bus-width property\n");
1056 return -ENOENT;
1057 }
1058
1059 cfg->f_min = 400000;
1060 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
1061 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1062 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1063
4de2de51 1064#ifdef OMAP_HSMMC_USE_GPIO
2558c049 1065 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
4de2de51 1066#endif
a9d6a7e2
M		 1067
1068 return 0;
1069}
2558c049 1070#endif
a9d6a7e2 1071
17c9a1c1
JJH		 1072#ifdef CONFIG_BLK
1073
1074static int omap_hsmmc_bind(struct udevice *dev)
1075{
1076 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1077
1078 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1079}
1080#endif
a9d6a7e2
M		 1081static int omap_hsmmc_probe(struct udevice *dev)
1082{
3d673ffc 1083 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
a9d6a7e2
M		 1084 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1085 struct omap_hsmmc_data *priv = dev_get_priv(dev);
3d673ffc 1086 struct mmc_config *cfg = &plat->cfg;
a9d6a7e2
M		 1087 struct mmc *mmc;
1088
a9d6a7e2 1089 cfg->name = "OMAP SD/MMC";
2558c049
LV		 1090 priv->base_addr = plat->base_addr;
1091#ifdef OMAP_HSMMC_USE_GPIO
1092 priv->cd_inverted = plat->cd_inverted;
1093#endif
a9d6a7e2 1094
17c9a1c1
JJH		 1095#ifdef CONFIG_BLK
1096 mmc = &plat->mmc;
1097#else
a9d6a7e2
M		 1098 mmc = mmc_create(cfg, priv);
1099 if (mmc == NULL)
1100 return -1;
17c9a1c1 1101#endif
a9d6a7e2 1102
2558c049 1103#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
5cc6a245
M		 1104 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1105 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1106#endif
1107
cffe5d86 1108 mmc->dev = dev;
a9d6a7e2
M		 1109 upriv->mmc = mmc;
1110
b5511d6c 1111 return omap_hsmmc_init_setup(mmc);
a9d6a7e2
M		 1112}
1113
2558c049 1114#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a9d6a7e2 1115static const struct udevice_id omap_hsmmc_ids[] = {
741726ae
JJH		 1116 { .compatible = "ti,omap3-hsmmc" },
1117 { .compatible = "ti,omap4-hsmmc" },
1118 { .compatible = "ti,am33xx-hsmmc" },
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M		 1119 { }
1120};
2558c049 1121#endif
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M		 1122
1123U_BOOT_DRIVER(omap_hsmmc) = {
1124 .name = "omap_hsmmc",
1125 .id = UCLASS_MMC,
2558c049 1126#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
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M		 1127 .of_match = omap_hsmmc_ids,
1128 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
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LV		 1129 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1130#endif
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JJH		 1131#ifdef CONFIG_BLK
1132 .bind = omap_hsmmc_bind,
1133#endif
b5511d6c 1134 .ops = &omap_hsmmc_ops,
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M		 1135 .probe = omap_hsmmc_probe,
1136 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
cbcb1701 1137 .flags = DM_FLAG_PRE_RELOC,
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M		 1138};
1139#endif
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