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de941241 SG |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * Sukumar Ghorai <s-ghorai@ti.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation's version 2 of | |
12 | * the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <config.h> | |
26 | #include <common.h> | |
93bfd616 | 27 | #include <malloc.h> |
de941241 SG |
28 | #include <mmc.h> |
29 | #include <part.h> | |
30 | #include <i2c.h> | |
31 | #include <twl4030.h> | |
14fa2dd0 | 32 | #include <twl6030.h> |
cb199102 | 33 | #include <palmas.h> |
de941241 SG |
34 | #include <asm/io.h> |
35 | #include <asm/arch/mmc_host_def.h> | |
3b68939f RQ |
36 | #if !defined(CONFIG_SOC_KEYSTONE) |
37 | #include <asm/gpio.h> | |
96e0e7b3 | 38 | #include <asm/arch/sys_proto.h> |
3b68939f | 39 | #endif |
2a48b3a2 TR |
40 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
41 | #include <asm/arch/mux.h> | |
42 | #endif | |
a9d6a7e2 M |
43 | #include <dm.h> |
44 | ||
45 | DECLARE_GLOBAL_DATA_PTR; | |
de941241 | 46 | |
ab769f22 PA |
47 | /* simplify defines to OMAP_HSMMC_USE_GPIO */ |
48 | #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ | |
49 | (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) | |
50 | #define OMAP_HSMMC_USE_GPIO | |
51 | #else | |
52 | #undef OMAP_HSMMC_USE_GPIO | |
53 | #endif | |
54 | ||
25c719e2 GI |
55 | /* common definitions for all OMAPs */ |
56 | #define SYSCTL_SRC (1 << 25) | |
57 | #define SYSCTL_SRD (1 << 26) | |
58 | ||
46831c1a AF |
59 | struct omap2_mmc_platform_config { |
60 | u32 reg_offset; | |
61 | }; | |
62 | ||
cc22b0c0 NK |
63 | struct omap_hsmmc_data { |
64 | struct hsmmc *base_addr; | |
c4d660d4 | 65 | #if !CONFIG_IS_ENABLED(DM_MMC) |
93bfd616 | 66 | struct mmc_config cfg; |
3d673ffc | 67 | #endif |
ab769f22 | 68 | #ifdef OMAP_HSMMC_USE_GPIO |
c4d660d4 | 69 | #if CONFIG_IS_ENABLED(DM_MMC) |
a9d6a7e2 M |
70 | struct gpio_desc cd_gpio; /* Change Detect GPIO */ |
71 | struct gpio_desc wp_gpio; /* Write Protect GPIO */ | |
72 | bool cd_inverted; | |
73 | #else | |
e874d5b0 | 74 | int cd_gpio; |
e3913f56 | 75 | int wp_gpio; |
ab769f22 | 76 | #endif |
a9d6a7e2 | 77 | #endif |
cc22b0c0 NK |
78 | }; |
79 | ||
eb9a28f6 NM |
80 | /* If we fail after 1 second wait, something is really bad */ |
81 | #define MAX_RETRY_MS 1000 | |
82 | ||
933efe64 S |
83 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); |
84 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, | |
85 | unsigned int siz); | |
14fa2dd0 | 86 | |
ae000e23 JJH |
87 | static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) |
88 | { | |
c4d660d4 | 89 | #if CONFIG_IS_ENABLED(DM_MMC) |
ae000e23 JJH |
90 | return dev_get_priv(mmc->dev); |
91 | #else | |
92 | return (struct omap_hsmmc_data *)mmc->priv; | |
93 | #endif | |
3d673ffc JJH |
94 | } |
95 | static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc) | |
96 | { | |
c4d660d4 | 97 | #if CONFIG_IS_ENABLED(DM_MMC) |
3d673ffc JJH |
98 | struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev); |
99 | return &plat->cfg; | |
100 | #else | |
101 | return &((struct omap_hsmmc_data *)mmc->priv)->cfg; | |
102 | #endif | |
ae000e23 JJH |
103 | } |
104 | ||
c4d660d4 | 105 | #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC) |
e874d5b0 NK |
106 | static int omap_mmc_setup_gpio_in(int gpio, const char *label) |
107 | { | |
5915a2ad | 108 | int ret; |
e874d5b0 | 109 | |
5915a2ad SG |
110 | #ifndef CONFIG_DM_GPIO |
111 | if (!gpio_is_valid(gpio)) | |
e874d5b0 | 112 | return -1; |
5915a2ad SG |
113 | #endif |
114 | ret = gpio_request(gpio, label); | |
115 | if (ret) | |
116 | return ret; | |
e874d5b0 | 117 | |
5915a2ad SG |
118 | ret = gpio_direction_input(gpio); |
119 | if (ret) | |
120 | return ret; | |
e874d5b0 NK |
121 | |
122 | return gpio; | |
123 | } | |
e874d5b0 NK |
124 | #endif |
125 | ||
750121c3 | 126 | static unsigned char mmc_board_init(struct mmc *mmc) |
de941241 | 127 | { |
de941241 | 128 | #if defined(CONFIG_OMAP34XX) |
3d673ffc | 129 | struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); |
de941241 SG |
130 | t2_t *t2_base = (t2_t *)T2_BASE; |
131 | struct prcm *prcm_base = (struct prcm *)PRCM_BASE; | |
b1e725f2 | 132 | u32 pbias_lite; |
6aca17c9 AF |
133 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
134 | u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL); | |
135 | #endif | |
de941241 | 136 | |
b1e725f2 GI |
137 | pbias_lite = readl(&t2_base->pbias_lite); |
138 | pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0); | |
5bfdd1fc AA |
139 | #ifdef CONFIG_TARGET_OMAP3_CAIRO |
140 | /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */ | |
141 | pbias_lite &= ~PBIASLITEVMODE0; | |
6aca17c9 AF |
142 | #endif |
143 | #ifdef CONFIG_MMC_OMAP36XX_PINS | |
144 | if (get_cpu_family() == CPU_OMAP36XX) { | |
145 | /* Disable extended drain IO before changing PBIAS */ | |
146 | wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ; | |
147 | writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL); | |
148 | } | |
5bfdd1fc | 149 | #endif |
b1e725f2 | 150 | writel(pbias_lite, &t2_base->pbias_lite); |
aac5450e | 151 | |
b1e725f2 | 152 | writel(pbias_lite | PBIASLITEPWRDNZ1 | |
de941241 SG |
153 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, |
154 | &t2_base->pbias_lite); | |
155 | ||
6aca17c9 AF |
156 | #ifdef CONFIG_MMC_OMAP36XX_PINS |
157 | if (get_cpu_family() == CPU_OMAP36XX) | |
158 | /* Enable extended drain IO after changing PBIAS */ | |
159 | writel(wkup_ctrl | | |
160 | OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, | |
161 | OMAP34XX_CTRL_WKUP_CTRL); | |
162 | #endif | |
de941241 SG |
163 | writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, |
164 | &t2_base->devconf0); | |
165 | ||
166 | writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, | |
167 | &t2_base->devconf1); | |
168 | ||
bbbc1ae9 | 169 | /* Change from default of 52MHz to 26MHz if necessary */ |
3d673ffc | 170 | if (!(cfg->host_caps & MMC_MODE_HS_52MHz)) |
bbbc1ae9 JS |
171 | writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, |
172 | &t2_base->ctl_prog_io1); | |
173 | ||
de941241 SG |
174 | writel(readl(&prcm_base->fclken1_core) | |
175 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
176 | &prcm_base->fclken1_core); | |
177 | ||
178 | writel(readl(&prcm_base->iclken1_core) | | |
179 | EN_MMC1 | EN_MMC2 | EN_MMC3, | |
180 | &prcm_base->iclken1_core); | |
181 | #endif | |
182 | ||
b4b06006 | 183 | #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX) |
14fa2dd0 | 184 | /* PBIAS config needed for MMC1 only */ |
dc09127a | 185 | if (mmc_get_blk_desc(mmc)->devnum == 0) |
b4b06006 | 186 | vmmc_pbias_config(LDO_VOLT_3V0); |
dd23e59d | 187 | #endif |
de941241 SG |
188 | |
189 | return 0; | |
190 | } | |
191 | ||
933efe64 | 192 | void mmc_init_stream(struct hsmmc *mmc_base) |
de941241 | 193 | { |
eb9a28f6 | 194 | ulong start; |
de941241 SG |
195 | |
196 | writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); | |
197 | ||
198 | writel(MMC_CMD0, &mmc_base->cmd); | |
eb9a28f6 NM |
199 | start = get_timer(0); |
200 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
201 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
202 | printf("%s: timedout waiting for cc!\n", __func__); | |
203 | return; | |
204 | } | |
205 | } | |
de941241 SG |
206 | writel(CC_MASK, &mmc_base->stat) |
207 | ; | |
208 | writel(MMC_CMD0, &mmc_base->cmd) | |
209 | ; | |
eb9a28f6 NM |
210 | start = get_timer(0); |
211 | while (!(readl(&mmc_base->stat) & CC_MASK)) { | |
212 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
213 | printf("%s: timedout waiting for cc2!\n", __func__); | |
214 | return; | |
215 | } | |
216 | } | |
de941241 SG |
217 | writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); |
218 | } | |
219 | ||
ab769f22 | 220 | static int omap_hsmmc_init_setup(struct mmc *mmc) |
de941241 | 221 | { |
ae000e23 | 222 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
cc22b0c0 | 223 | struct hsmmc *mmc_base; |
de941241 SG |
224 | unsigned int reg_val; |
225 | unsigned int dsor; | |
eb9a28f6 | 226 | ulong start; |
de941241 | 227 | |
ae000e23 | 228 | mmc_base = priv->base_addr; |
14fa2dd0 | 229 | mmc_board_init(mmc); |
de941241 SG |
230 | |
231 | writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, | |
232 | &mmc_base->sysconfig); | |
eb9a28f6 NM |
233 | start = get_timer(0); |
234 | while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { | |
235 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
236 | printf("%s: timedout waiting for cc2!\n", __func__); | |
915ffa52 | 237 | return -ETIMEDOUT; |
eb9a28f6 NM |
238 | } |
239 | } | |
de941241 | 240 | writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); |
eb9a28f6 NM |
241 | start = get_timer(0); |
242 | while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { | |
243 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
244 | printf("%s: timedout waiting for softresetall!\n", | |
245 | __func__); | |
915ffa52 | 246 | return -ETIMEDOUT; |
eb9a28f6 NM |
247 | } |
248 | } | |
de941241 SG |
249 | writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); |
250 | writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, | |
251 | &mmc_base->capa); | |
252 | ||
253 | reg_val = readl(&mmc_base->con) & RESERVED_MASK; | |
254 | ||
255 | writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | | |
256 | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | | |
257 | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); | |
258 | ||
259 | dsor = 240; | |
260 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
261 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
262 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
263 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
eb9a28f6 NM |
264 | start = get_timer(0); |
265 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
266 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
267 | printf("%s: timedout waiting for ics!\n", __func__); | |
915ffa52 | 268 | return -ETIMEDOUT; |
eb9a28f6 NM |
269 | } |
270 | } | |
de941241 SG |
271 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
272 | ||
273 | writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); | |
274 | ||
275 | writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | | |
276 | IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, | |
277 | &mmc_base->ie); | |
278 | ||
279 | mmc_init_stream(mmc_base); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
25c719e2 GI |
284 | /* |
285 | * MMC controller internal finite state machine reset | |
286 | * | |
287 | * Used to reset command or data internal state machines, using respectively | |
288 | * SRC or SRD bit of SYSCTL register | |
289 | */ | |
290 | static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) | |
291 | { | |
292 | ulong start; | |
293 | ||
294 | mmc_reg_out(&mmc_base->sysctl, bit, bit); | |
295 | ||
61a6cc27 OT |
296 | /* |
297 | * CMD(DAT) lines reset procedures are slightly different | |
298 | * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). | |
299 | * According to OMAP3 TRM: | |
300 | * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it | |
301 | * returns to 0x0. | |
302 | * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset | |
303 | * procedure steps must be as follows: | |
304 | * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in | |
305 | * MMCHS_SYSCTL register (SD_SYSCTL for AM335x). | |
306 | * 2. Poll the SRC(SRD) bit until it is set to 0x1. | |
307 | * 3. Wait until the SRC (SRD) bit returns to 0x0 | |
308 | * (reset procedure is completed). | |
309 | */ | |
310 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ | |
dce55b93 | 311 | defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) |
61a6cc27 OT |
312 | if (!(readl(&mmc_base->sysctl) & bit)) { |
313 | start = get_timer(0); | |
314 | while (!(readl(&mmc_base->sysctl) & bit)) { | |
315 | if (get_timer(0) - start > MAX_RETRY_MS) | |
316 | return; | |
317 | } | |
318 | } | |
319 | #endif | |
25c719e2 GI |
320 | start = get_timer(0); |
321 | while ((readl(&mmc_base->sysctl) & bit) != 0) { | |
322 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
323 | printf("%s: timedout waiting for sysctl %x to clear\n", | |
324 | __func__, bit); | |
325 | return; | |
326 | } | |
327 | } | |
328 | } | |
c4d660d4 | 329 | #if !CONFIG_IS_ENABLED(DM_MMC) |
ab769f22 | 330 | static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
de941241 SG |
331 | struct mmc_data *data) |
332 | { | |
ae000e23 | 333 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
b5511d6c JJH |
334 | #else |
335 | static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, | |
336 | struct mmc_data *data) | |
337 | { | |
338 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
339 | #endif | |
cc22b0c0 | 340 | struct hsmmc *mmc_base; |
de941241 | 341 | unsigned int flags, mmc_stat; |
eb9a28f6 | 342 | ulong start; |
de941241 | 343 | |
ae000e23 | 344 | mmc_base = priv->base_addr; |
eb9a28f6 | 345 | start = get_timer(0); |
a7778f8f | 346 | while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { |
eb9a28f6 | 347 | if (get_timer(0) - start > MAX_RETRY_MS) { |
a7778f8f TR |
348 | printf("%s: timedout waiting on cmd inhibit to clear\n", |
349 | __func__); | |
915ffa52 | 350 | return -ETIMEDOUT; |
eb9a28f6 NM |
351 | } |
352 | } | |
de941241 | 353 | writel(0xFFFFFFFF, &mmc_base->stat); |
eb9a28f6 NM |
354 | start = get_timer(0); |
355 | while (readl(&mmc_base->stat)) { | |
356 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
15ceb1de GI |
357 | printf("%s: timedout waiting for STAT (%x) to clear\n", |
358 | __func__, readl(&mmc_base->stat)); | |
915ffa52 | 359 | return -ETIMEDOUT; |
eb9a28f6 NM |
360 | } |
361 | } | |
de941241 SG |
362 | /* |
363 | * CMDREG | |
364 | * CMDIDX[13:8] : Command index | |
365 | * DATAPRNT[5] : Data Present Select | |
366 | * ENCMDIDX[4] : Command Index Check Enable | |
367 | * ENCMDCRC[3] : Command CRC Check Enable | |
368 | * RSPTYP[1:0] | |
369 | * 00 = No Response | |
370 | * 01 = Length 136 | |
371 | * 10 = Length 48 | |
372 | * 11 = Length 48 Check busy after response | |
373 | */ | |
374 | /* Delay added before checking the status of frq change | |
375 | * retry not supported by mmc.c(core file) | |
376 | */ | |
377 | if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) | |
378 | udelay(50000); /* wait 50 ms */ | |
379 | ||
380 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) | |
381 | flags = 0; | |
382 | else if (cmd->resp_type & MMC_RSP_136) | |
383 | flags = RSP_TYPE_LGHT136 | CICE_NOCHECK; | |
384 | else if (cmd->resp_type & MMC_RSP_BUSY) | |
385 | flags = RSP_TYPE_LGHT48B; | |
386 | else | |
387 | flags = RSP_TYPE_LGHT48; | |
388 | ||
389 | /* enable default flags */ | |
390 | flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | | |
391 | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); | |
392 | ||
393 | if (cmd->resp_type & MMC_RSP_CRC) | |
394 | flags |= CCCE_CHECK; | |
395 | if (cmd->resp_type & MMC_RSP_OPCODE) | |
396 | flags |= CICE_CHECK; | |
397 | ||
398 | if (data) { | |
399 | if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || | |
400 | (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { | |
401 | flags |= (MSBS_MULTIBLK | BCE_ENABLE); | |
402 | data->blocksize = 512; | |
403 | writel(data->blocksize | (data->blocks << 16), | |
404 | &mmc_base->blk); | |
405 | } else | |
406 | writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk); | |
407 | ||
408 | if (data->flags & MMC_DATA_READ) | |
409 | flags |= (DP_DATA | DDIR_READ); | |
410 | else | |
411 | flags |= (DP_DATA | DDIR_WRITE); | |
412 | } | |
413 | ||
414 | writel(cmd->cmdarg, &mmc_base->arg); | |
152ba363 | 415 | udelay(20); /* To fix "No status update" error on eMMC */ |
de941241 SG |
416 | writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd); |
417 | ||
eb9a28f6 | 418 | start = get_timer(0); |
de941241 SG |
419 | do { |
420 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
421 | if (get_timer(0) - start > MAX_RETRY_MS) { |
422 | printf("%s : timeout: No status update\n", __func__); | |
915ffa52 | 423 | return -ETIMEDOUT; |
eb9a28f6 NM |
424 | } |
425 | } while (!mmc_stat); | |
de941241 | 426 | |
25c719e2 GI |
427 | if ((mmc_stat & IE_CTO) != 0) { |
428 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); | |
915ffa52 | 429 | return -ETIMEDOUT; |
25c719e2 | 430 | } else if ((mmc_stat & ERRI_MASK) != 0) |
de941241 SG |
431 | return -1; |
432 | ||
433 | if (mmc_stat & CC_MASK) { | |
434 | writel(CC_MASK, &mmc_base->stat); | |
435 | if (cmd->resp_type & MMC_RSP_PRESENT) { | |
436 | if (cmd->resp_type & MMC_RSP_136) { | |
437 | /* response type 2 */ | |
438 | cmd->response[3] = readl(&mmc_base->rsp10); | |
439 | cmd->response[2] = readl(&mmc_base->rsp32); | |
440 | cmd->response[1] = readl(&mmc_base->rsp54); | |
441 | cmd->response[0] = readl(&mmc_base->rsp76); | |
442 | } else | |
443 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
444 | cmd->response[0] = readl(&mmc_base->rsp10); | |
445 | } | |
446 | } | |
447 | ||
448 | if (data && (data->flags & MMC_DATA_READ)) { | |
449 | mmc_read_data(mmc_base, data->dest, | |
450 | data->blocksize * data->blocks); | |
451 | } else if (data && (data->flags & MMC_DATA_WRITE)) { | |
452 | mmc_write_data(mmc_base, data->src, | |
453 | data->blocksize * data->blocks); | |
454 | } | |
455 | return 0; | |
456 | } | |
457 | ||
933efe64 | 458 | static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) |
de941241 SG |
459 | { |
460 | unsigned int *output_buf = (unsigned int *)buf; | |
461 | unsigned int mmc_stat; | |
462 | unsigned int count; | |
463 | ||
464 | /* | |
465 | * Start Polled Read | |
466 | */ | |
467 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
468 | count /= 4; | |
469 | ||
470 | while (size) { | |
eb9a28f6 | 471 | ulong start = get_timer(0); |
de941241 SG |
472 | do { |
473 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
474 | if (get_timer(0) - start > MAX_RETRY_MS) { |
475 | printf("%s: timedout waiting for status!\n", | |
476 | __func__); | |
915ffa52 | 477 | return -ETIMEDOUT; |
eb9a28f6 | 478 | } |
de941241 SG |
479 | } while (mmc_stat == 0); |
480 | ||
25c719e2 GI |
481 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
482 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
483 | ||
de941241 SG |
484 | if ((mmc_stat & ERRI_MASK) != 0) |
485 | return 1; | |
486 | ||
487 | if (mmc_stat & BRR_MASK) { | |
488 | unsigned int k; | |
489 | ||
490 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
491 | &mmc_base->stat); | |
492 | for (k = 0; k < count; k++) { | |
493 | *output_buf = readl(&mmc_base->data); | |
494 | output_buf++; | |
495 | } | |
496 | size -= (count*4); | |
497 | } | |
498 | ||
499 | if (mmc_stat & BWR_MASK) | |
500 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
501 | &mmc_base->stat); | |
502 | ||
503 | if (mmc_stat & TC_MASK) { | |
504 | writel(readl(&mmc_base->stat) | TC_MASK, | |
505 | &mmc_base->stat); | |
506 | break; | |
507 | } | |
508 | } | |
509 | return 0; | |
510 | } | |
511 | ||
933efe64 S |
512 | static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, |
513 | unsigned int size) | |
de941241 SG |
514 | { |
515 | unsigned int *input_buf = (unsigned int *)buf; | |
516 | unsigned int mmc_stat; | |
517 | unsigned int count; | |
518 | ||
519 | /* | |
152ba363 | 520 | * Start Polled Write |
de941241 SG |
521 | */ |
522 | count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size; | |
523 | count /= 4; | |
524 | ||
525 | while (size) { | |
eb9a28f6 | 526 | ulong start = get_timer(0); |
de941241 SG |
527 | do { |
528 | mmc_stat = readl(&mmc_base->stat); | |
eb9a28f6 NM |
529 | if (get_timer(0) - start > MAX_RETRY_MS) { |
530 | printf("%s: timedout waiting for status!\n", | |
531 | __func__); | |
915ffa52 | 532 | return -ETIMEDOUT; |
eb9a28f6 | 533 | } |
de941241 SG |
534 | } while (mmc_stat == 0); |
535 | ||
25c719e2 GI |
536 | if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0) |
537 | mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); | |
538 | ||
de941241 SG |
539 | if ((mmc_stat & ERRI_MASK) != 0) |
540 | return 1; | |
541 | ||
542 | if (mmc_stat & BWR_MASK) { | |
543 | unsigned int k; | |
544 | ||
545 | writel(readl(&mmc_base->stat) | BWR_MASK, | |
546 | &mmc_base->stat); | |
547 | for (k = 0; k < count; k++) { | |
548 | writel(*input_buf, &mmc_base->data); | |
549 | input_buf++; | |
550 | } | |
551 | size -= (count*4); | |
552 | } | |
553 | ||
554 | if (mmc_stat & BRR_MASK) | |
555 | writel(readl(&mmc_base->stat) | BRR_MASK, | |
556 | &mmc_base->stat); | |
557 | ||
558 | if (mmc_stat & TC_MASK) { | |
559 | writel(readl(&mmc_base->stat) | TC_MASK, | |
560 | &mmc_base->stat); | |
561 | break; | |
562 | } | |
563 | } | |
564 | return 0; | |
565 | } | |
566 | ||
c4d660d4 | 567 | #if !CONFIG_IS_ENABLED(DM_MMC) |
07b0b9c0 | 568 | static int omap_hsmmc_set_ios(struct mmc *mmc) |
de941241 | 569 | { |
ae000e23 | 570 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
b5511d6c JJH |
571 | #else |
572 | static int omap_hsmmc_set_ios(struct udevice *dev) | |
573 | { | |
574 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
575 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); | |
576 | struct mmc *mmc = upriv->mmc; | |
577 | #endif | |
cc22b0c0 | 578 | struct hsmmc *mmc_base; |
de941241 | 579 | unsigned int dsor = 0; |
eb9a28f6 | 580 | ulong start; |
de941241 | 581 | |
ae000e23 | 582 | mmc_base = priv->base_addr; |
de941241 SG |
583 | /* configue bus width */ |
584 | switch (mmc->bus_width) { | |
585 | case 8: | |
586 | writel(readl(&mmc_base->con) | DTW_8_BITMODE, | |
587 | &mmc_base->con); | |
588 | break; | |
589 | ||
590 | case 4: | |
591 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
592 | &mmc_base->con); | |
593 | writel(readl(&mmc_base->hctl) | DTW_4_BITMODE, | |
594 | &mmc_base->hctl); | |
595 | break; | |
596 | ||
597 | case 1: | |
598 | default: | |
599 | writel(readl(&mmc_base->con) & ~DTW_8_BITMODE, | |
600 | &mmc_base->con); | |
601 | writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE, | |
602 | &mmc_base->hctl); | |
603 | break; | |
604 | } | |
605 | ||
606 | /* configure clock with 96Mhz system clock. | |
607 | */ | |
608 | if (mmc->clock != 0) { | |
609 | dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock); | |
610 | if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock) | |
611 | dsor++; | |
612 | } | |
613 | ||
614 | mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), | |
615 | (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); | |
616 | ||
617 | mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, | |
618 | (dsor << CLKD_OFFSET) | ICE_OSCILLATE); | |
619 | ||
eb9a28f6 NM |
620 | start = get_timer(0); |
621 | while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { | |
622 | if (get_timer(0) - start > MAX_RETRY_MS) { | |
623 | printf("%s: timedout waiting for ics!\n", __func__); | |
07b0b9c0 | 624 | return -ETIMEDOUT; |
eb9a28f6 NM |
625 | } |
626 | } | |
de941241 | 627 | writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); |
07b0b9c0 JC |
628 | |
629 | return 0; | |
de941241 SG |
630 | } |
631 | ||
ab769f22 | 632 | #ifdef OMAP_HSMMC_USE_GPIO |
c4d660d4 | 633 | #if CONFIG_IS_ENABLED(DM_MMC) |
b5511d6c | 634 | static int omap_hsmmc_getcd(struct udevice *dev) |
a9d6a7e2 | 635 | { |
b5511d6c | 636 | struct omap_hsmmc_data *priv = dev_get_priv(dev); |
a9d6a7e2 M |
637 | int value; |
638 | ||
639 | value = dm_gpio_get_value(&priv->cd_gpio); | |
640 | /* if no CD return as 1 */ | |
641 | if (value < 0) | |
642 | return 1; | |
643 | ||
644 | if (priv->cd_inverted) | |
645 | return !value; | |
646 | return value; | |
647 | } | |
648 | ||
b5511d6c | 649 | static int omap_hsmmc_getwp(struct udevice *dev) |
a9d6a7e2 | 650 | { |
b5511d6c | 651 | struct omap_hsmmc_data *priv = dev_get_priv(dev); |
a9d6a7e2 M |
652 | int value; |
653 | ||
654 | value = dm_gpio_get_value(&priv->wp_gpio); | |
655 | /* if no WP return as 0 */ | |
656 | if (value < 0) | |
657 | return 0; | |
658 | return value; | |
659 | } | |
660 | #else | |
ab769f22 PA |
661 | static int omap_hsmmc_getcd(struct mmc *mmc) |
662 | { | |
ae000e23 | 663 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
ab769f22 PA |
664 | int cd_gpio; |
665 | ||
666 | /* if no CD return as 1 */ | |
ae000e23 | 667 | cd_gpio = priv->cd_gpio; |
ab769f22 PA |
668 | if (cd_gpio < 0) |
669 | return 1; | |
670 | ||
0b03a931 IG |
671 | /* NOTE: assumes card detect signal is active-low */ |
672 | return !gpio_get_value(cd_gpio); | |
ab769f22 PA |
673 | } |
674 | ||
675 | static int omap_hsmmc_getwp(struct mmc *mmc) | |
676 | { | |
ae000e23 | 677 | struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); |
ab769f22 PA |
678 | int wp_gpio; |
679 | ||
680 | /* if no WP return as 0 */ | |
ae000e23 | 681 | wp_gpio = priv->wp_gpio; |
ab769f22 PA |
682 | if (wp_gpio < 0) |
683 | return 0; | |
684 | ||
0b03a931 | 685 | /* NOTE: assumes write protect signal is active-high */ |
ab769f22 PA |
686 | return gpio_get_value(wp_gpio); |
687 | } | |
688 | #endif | |
a9d6a7e2 | 689 | #endif |
ab769f22 | 690 | |
c4d660d4 | 691 | #if CONFIG_IS_ENABLED(DM_MMC) |
b5511d6c JJH |
692 | static const struct dm_mmc_ops omap_hsmmc_ops = { |
693 | .send_cmd = omap_hsmmc_send_cmd, | |
694 | .set_ios = omap_hsmmc_set_ios, | |
695 | #ifdef OMAP_HSMMC_USE_GPIO | |
696 | .get_cd = omap_hsmmc_getcd, | |
697 | .get_wp = omap_hsmmc_getwp, | |
698 | #endif | |
699 | }; | |
700 | #else | |
ab769f22 PA |
701 | static const struct mmc_ops omap_hsmmc_ops = { |
702 | .send_cmd = omap_hsmmc_send_cmd, | |
703 | .set_ios = omap_hsmmc_set_ios, | |
704 | .init = omap_hsmmc_init_setup, | |
705 | #ifdef OMAP_HSMMC_USE_GPIO | |
706 | .getcd = omap_hsmmc_getcd, | |
707 | .getwp = omap_hsmmc_getwp, | |
708 | #endif | |
709 | }; | |
b5511d6c | 710 | #endif |
ab769f22 | 711 | |
c4d660d4 | 712 | #if !CONFIG_IS_ENABLED(DM_MMC) |
e3913f56 NK |
713 | int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, |
714 | int wp_gpio) | |
de941241 | 715 | { |
93bfd616 | 716 | struct mmc *mmc; |
ae000e23 | 717 | struct omap_hsmmc_data *priv; |
93bfd616 PA |
718 | struct mmc_config *cfg; |
719 | uint host_caps_val; | |
720 | ||
ae000e23 JJH |
721 | priv = malloc(sizeof(*priv)); |
722 | if (priv == NULL) | |
93bfd616 | 723 | return -1; |
de941241 | 724 | |
5a20397b | 725 | host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS; |
de941241 SG |
726 | |
727 | switch (dev_index) { | |
728 | case 0: | |
ae000e23 | 729 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 | 730 | break; |
1037d585 | 731 | #ifdef OMAP_HSMMC2_BASE |
de941241 | 732 | case 1: |
ae000e23 | 733 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; |
152ba363 | 734 | #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ |
3891a54f | 735 | defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ |
3b68939f RQ |
736 | defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ |
737 | defined(CONFIG_HSMMC2_8BIT) | |
152ba363 LP |
738 | /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ |
739 | host_caps_val |= MMC_MODE_8BIT; | |
740 | #endif | |
de941241 | 741 | break; |
1037d585 TR |
742 | #endif |
743 | #ifdef OMAP_HSMMC3_BASE | |
de941241 | 744 | case 2: |
ae000e23 | 745 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE; |
3891a54f | 746 | #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT) |
152ba363 LP |
747 | /* Enable 8-bit interface for eMMC on DRA7XX */ |
748 | host_caps_val |= MMC_MODE_8BIT; | |
749 | #endif | |
de941241 | 750 | break; |
1037d585 | 751 | #endif |
de941241 | 752 | default: |
ae000e23 | 753 | priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; |
de941241 SG |
754 | return 1; |
755 | } | |
ab769f22 PA |
756 | #ifdef OMAP_HSMMC_USE_GPIO |
757 | /* on error gpio values are set to -1, which is what we want */ | |
ae000e23 JJH |
758 | priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); |
759 | priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); | |
ab769f22 | 760 | #endif |
173ddc5b | 761 | |
ae000e23 | 762 | cfg = &priv->cfg; |
de941241 | 763 | |
93bfd616 PA |
764 | cfg->name = "OMAP SD/MMC"; |
765 | cfg->ops = &omap_hsmmc_ops; | |
766 | ||
767 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
768 | cfg->host_caps = host_caps_val & ~host_caps_mask; | |
769 | ||
770 | cfg->f_min = 400000; | |
bbbc1ae9 JS |
771 | |
772 | if (f_max != 0) | |
93bfd616 | 773 | cfg->f_max = f_max; |
bbbc1ae9 | 774 | else { |
93bfd616 PA |
775 | if (cfg->host_caps & MMC_MODE_HS) { |
776 | if (cfg->host_caps & MMC_MODE_HS_52MHz) | |
777 | cfg->f_max = 52000000; | |
bbbc1ae9 | 778 | else |
93bfd616 | 779 | cfg->f_max = 26000000; |
bbbc1ae9 | 780 | } else |
93bfd616 | 781 | cfg->f_max = 20000000; |
bbbc1ae9 | 782 | } |
de941241 | 783 | |
93bfd616 | 784 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
8feafcc4 | 785 | |
4ca9244d JR |
786 | #if defined(CONFIG_OMAP34XX) |
787 | /* | |
788 | * Silicon revs 2.1 and older do not support multiblock transfers. | |
789 | */ | |
790 | if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) | |
93bfd616 | 791 | cfg->b_max = 1; |
4ca9244d | 792 | #endif |
ae000e23 | 793 | mmc = mmc_create(cfg, priv); |
93bfd616 PA |
794 | if (mmc == NULL) |
795 | return -1; | |
de941241 SG |
796 | |
797 | return 0; | |
798 | } | |
a9d6a7e2 | 799 | #else |
2558c049 | 800 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
a9d6a7e2 M |
801 | static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) |
802 | { | |
3d673ffc JJH |
803 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); |
804 | struct mmc_config *cfg = &plat->cfg; | |
46831c1a AF |
805 | struct omap2_mmc_platform_config *data = |
806 | (struct omap2_mmc_platform_config *)dev_get_driver_data(dev); | |
a9d6a7e2 | 807 | const void *fdt = gd->fdt_blob; |
e160f7d4 | 808 | int node = dev_of_offset(dev); |
a9d6a7e2 M |
809 | int val; |
810 | ||
a821c4af SG |
811 | plat->base_addr = map_physmem(devfdt_get_addr(dev), |
812 | sizeof(struct hsmmc *), | |
46831c1a | 813 | MAP_NOCACHE) + data->reg_offset; |
a9d6a7e2 M |
814 | |
815 | cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; | |
816 | val = fdtdec_get_int(fdt, node, "bus-width", -1); | |
817 | if (val < 0) { | |
818 | printf("error: bus-width property missing\n"); | |
819 | return -ENOENT; | |
820 | } | |
821 | ||
822 | switch (val) { | |
823 | case 0x8: | |
824 | cfg->host_caps |= MMC_MODE_8BIT; | |
825 | case 0x4: | |
826 | cfg->host_caps |= MMC_MODE_4BIT; | |
827 | break; | |
828 | default: | |
829 | printf("error: invalid bus-width property\n"); | |
830 | return -ENOENT; | |
831 | } | |
832 | ||
833 | cfg->f_min = 400000; | |
834 | cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000); | |
835 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
836 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; | |
837 | ||
4de2de51 | 838 | #ifdef OMAP_HSMMC_USE_GPIO |
2558c049 | 839 | plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); |
4de2de51 | 840 | #endif |
a9d6a7e2 M |
841 | |
842 | return 0; | |
843 | } | |
2558c049 | 844 | #endif |
a9d6a7e2 | 845 | |
17c9a1c1 JJH |
846 | #ifdef CONFIG_BLK |
847 | ||
848 | static int omap_hsmmc_bind(struct udevice *dev) | |
849 | { | |
850 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); | |
851 | ||
852 | return mmc_bind(dev, &plat->mmc, &plat->cfg); | |
853 | } | |
854 | #endif | |
a9d6a7e2 M |
855 | static int omap_hsmmc_probe(struct udevice *dev) |
856 | { | |
3d673ffc | 857 | struct omap_hsmmc_plat *plat = dev_get_platdata(dev); |
a9d6a7e2 M |
858 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
859 | struct omap_hsmmc_data *priv = dev_get_priv(dev); | |
3d673ffc | 860 | struct mmc_config *cfg = &plat->cfg; |
a9d6a7e2 M |
861 | struct mmc *mmc; |
862 | ||
a9d6a7e2 | 863 | cfg->name = "OMAP SD/MMC"; |
2558c049 LV |
864 | priv->base_addr = plat->base_addr; |
865 | #ifdef OMAP_HSMMC_USE_GPIO | |
866 | priv->cd_inverted = plat->cd_inverted; | |
867 | #endif | |
a9d6a7e2 | 868 | |
17c9a1c1 JJH |
869 | #ifdef CONFIG_BLK |
870 | mmc = &plat->mmc; | |
871 | #else | |
a9d6a7e2 M |
872 | mmc = mmc_create(cfg, priv); |
873 | if (mmc == NULL) | |
874 | return -1; | |
17c9a1c1 | 875 | #endif |
a9d6a7e2 | 876 | |
2558c049 | 877 | #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL) |
5cc6a245 M |
878 | gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); |
879 | gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); | |
880 | #endif | |
881 | ||
cffe5d86 | 882 | mmc->dev = dev; |
a9d6a7e2 M |
883 | upriv->mmc = mmc; |
884 | ||
b5511d6c | 885 | return omap_hsmmc_init_setup(mmc); |
a9d6a7e2 M |
886 | } |
887 | ||
2558c049 | 888 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
46831c1a AF |
889 | static const struct omap2_mmc_platform_config omap3_mmc_pdata = { |
890 | .reg_offset = 0, | |
891 | }; | |
892 | ||
893 | static const struct omap2_mmc_platform_config am33xx_mmc_pdata = { | |
894 | .reg_offset = 0x100, | |
895 | }; | |
896 | ||
897 | static const struct omap2_mmc_platform_config omap4_mmc_pdata = { | |
898 | .reg_offset = 0x100, | |
899 | }; | |
900 | ||
a9d6a7e2 | 901 | static const struct udevice_id omap_hsmmc_ids[] = { |
46831c1a AF |
902 | { |
903 | .compatible = "ti,omap3-hsmmc", | |
904 | .data = (ulong)&omap3_mmc_pdata | |
905 | }, | |
906 | { | |
907 | .compatible = "ti,omap4-hsmmc", | |
908 | .data = (ulong)&omap4_mmc_pdata | |
909 | }, | |
910 | { | |
911 | .compatible = "ti,am33xx-hsmmc", | |
912 | .data = (ulong)&am33xx_mmc_pdata | |
913 | }, | |
a9d6a7e2 M |
914 | { } |
915 | }; | |
2558c049 | 916 | #endif |
a9d6a7e2 M |
917 | |
918 | U_BOOT_DRIVER(omap_hsmmc) = { | |
919 | .name = "omap_hsmmc", | |
920 | .id = UCLASS_MMC, | |
2558c049 | 921 | #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) |
a9d6a7e2 M |
922 | .of_match = omap_hsmmc_ids, |
923 | .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata, | |
2558c049 LV |
924 | .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat), |
925 | #endif | |
17c9a1c1 JJH |
926 | #ifdef CONFIG_BLK |
927 | .bind = omap_hsmmc_bind, | |
928 | #endif | |
b5511d6c | 929 | .ops = &omap_hsmmc_ops, |
a9d6a7e2 M |
930 | .probe = omap_hsmmc_probe, |
931 | .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), | |
cbcb1701 | 932 | .flags = DM_FLAG_PRE_RELOC, |
a9d6a7e2 M |
933 | }; |
934 | #endif |