]> git.ipfire.org Git - thirdparty/kernel/stable.git/blame - arch/x86/kvm/x86.c
projects / thirdparty / kernel / stable.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: Introduce KVM_MEMORY_ENCRYPT_OP ioctl
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
9ed96e87
MT		 110unsigned int min_timer_period_us = 500;
111module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
112
630994b3
MT		 113static bool __read_mostly kvmclock_periodic_sync = true;
114module_param(kvmclock_periodic_sync, bool, S_IRUGO);
115
893590c7 116bool __read_mostly kvm_has_tsc_control;
92a1f12d 117EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 118u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 119EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 120u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
121EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
122u64 __read_mostly kvm_max_tsc_scaling_ratio;
123EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 124u64 __read_mostly kvm_default_tsc_scaling_ratio;
125EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 126
cc578287 127/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 128static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 129module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
130
d0659d94 131/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 132unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 133module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
134
52004014
FW		 135static bool __read_mostly vector_hashing = true;
136module_param(vector_hashing, bool, S_IRUGO);
137
18863bdd
AK		 138#define KVM_NR_SHARED_MSRS 16
139
140struct kvm_shared_msrs_global {
141 int nr;
2bf78fa7 142 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 143};
144
145struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
2bf78fa7
SY		 148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 152};
153
154static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 155static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 156
417bc304 157struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 168 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 173 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 181 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 182 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 183 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 184 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
185 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
186 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
187 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
188 { "mmu_flooded", VM_STAT(mmu_flooded) },
189 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 190 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 191 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 192 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 193 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 194 { "max_mmu_page_hash_collisions",
195 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 196 { NULL }
197};
198
2acf923e
DC		 199u64 __read_mostly host_xcr0;
200
b6785def 201static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 202
af585b92
GN		 203static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
204{
205 int i;
206 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
207 vcpu->arch.apf.gfns[i] = ~0;
208}
209
18863bdd
AK		 210static void kvm_on_user_return(struct user_return_notifier *urn)
211{
212 unsigned slot;
18863bdd
AK		 213 struct kvm_shared_msrs *locals
214 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 215 struct kvm_shared_msr_values *values;
1650b4eb
IA		 216 unsigned long flags;
217
218 /*
219 * Disabling irqs at this point since the following code could be
220 * interrupted and executed through kvm_arch_hardware_disable()
221 */
222 local_irq_save(flags);
223 if (locals->registered) {
224 locals->registered = false;
225 user_return_notifier_unregister(urn);
226 }
227 local_irq_restore(flags);
18863bdd 228 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 229 values = &locals->values[slot];
230 if (values->host != values->curr) {
231 wrmsrl(shared_msrs_global.msrs[slot], values->host);
232 values->curr = values->host;
18863bdd
AK		 233 }
234 }
18863bdd
AK		 235}
236
2bf78fa7 237static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 238{
18863bdd 239 u64 value;
013f6a5d
MT		 240 unsigned int cpu = smp_processor_id();
241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 242
2bf78fa7
SY		 243 /* only read, and nobody should modify it at this time,
244 * so don't need lock */
245 if (slot >= shared_msrs_global.nr) {
246 printk(KERN_ERR "kvm: invalid MSR slot!");
247 return;
248 }
249 rdmsrl_safe(msr, &value);
250 smsr->values[slot].host = value;
251 smsr->values[slot].curr = value;
252}
253
254void kvm_define_shared_msr(unsigned slot, u32 msr)
255{
0123be42 256 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 257 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 258 if (slot >= shared_msrs_global.nr)
259 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 260}
261EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
262
263static void kvm_shared_msr_cpu_online(void)
264{
265 unsigned i;
18863bdd
AK		 266
267 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 268 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 269}
270
8b3c3104 271int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 272{
013f6a5d
MT		 273 unsigned int cpu = smp_processor_id();
274 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 275 int err;
18863bdd 276
2bf78fa7 277 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 278 return 0;
2bf78fa7 279 smsr->values[slot].curr = value;
8b3c3104
AH		 280 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
281 if (err)
282 return 1;
283
18863bdd
AK		 284 if (!smsr->registered) {
285 smsr->urn.on_user_return = kvm_on_user_return;
286 user_return_notifier_register(&smsr->urn);
287 smsr->registered = true;
288 }
8b3c3104 289 return 0;
18863bdd
AK		 290}
291EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
292
13a34e06 293static void drop_user_return_notifiers(void)
3548bab5 294{
013f6a5d
MT		 295 unsigned int cpu = smp_processor_id();
296 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 297
298 if (smsr->registered)
299 kvm_on_user_return(&smsr->urn);
300}
301
6866b83e
CO		 302u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
303{
8a5a87d9 304 return vcpu->arch.apic_base;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_get_apic_base);
307
58cb628d
JK		 308int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
309{
310 u64 old_state = vcpu->arch.apic_base &
311 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
312 u64 new_state = msr_info->data &
313 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 314 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
315 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 316
d3802286
JM		 317 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
318 return 1;
58cb628d 319 if (!msr_info->host_initiated &&
d3802286 320 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 321 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
322 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
323 old_state == 0)))
324 return 1;
325
326 kvm_lapic_set_base(vcpu, msr_info->data);
327 return 0;
6866b83e
CO		 328}
329EXPORT_SYMBOL_GPL(kvm_set_apic_base);
330
2605fc21 331asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 332{
333 /* Fault while not rebooting. We want the trace. */
334 BUG();
335}
336EXPORT_SYMBOL_GPL(kvm_spurious_fault);
337
3fd28fce
ED		 338#define EXCPT_BENIGN 0
339#define EXCPT_CONTRIBUTORY 1
340#define EXCPT_PF 2
341
342static int exception_class(int vector)
343{
344 switch (vector) {
345 case PF_VECTOR:
346 return EXCPT_PF;
347 case DE_VECTOR:
348 case TS_VECTOR:
349 case NP_VECTOR:
350 case SS_VECTOR:
351 case GP_VECTOR:
352 return EXCPT_CONTRIBUTORY;
353 default:
354 break;
355 }
356 return EXCPT_BENIGN;
357}
358
d6e8c854
NA		 359#define EXCPT_FAULT 0
360#define EXCPT_TRAP 1
361#define EXCPT_ABORT 2
362#define EXCPT_INTERRUPT 3
363
364static int exception_type(int vector)
365{
366 unsigned int mask;
367
368 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
369 return EXCPT_INTERRUPT;
370
371 mask = 1 << vector;
372
373 /* #DB is trap, as instruction watchpoints are handled elsewhere */
374 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
375 return EXCPT_TRAP;
376
377 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
378 return EXCPT_ABORT;
379
380 /* Reserved exceptions will result in fault */
381 return EXCPT_FAULT;
382}
383
3fd28fce 384static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 385 unsigned nr, bool has_error, u32 error_code,
386 bool reinject)
3fd28fce
ED		 387{
388 u32 prev_nr;
389 int class1, class2;
390
3842d135
AK		 391 kvm_make_request(KVM_REQ_EVENT, vcpu);
392
664f8e26 393 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 394 queue:
3ffb2468
NA		 395 if (has_error && !is_protmode(vcpu))
396 has_error = false;
664f8e26
WL		 397 if (reinject) {
398 /*
399 * On vmentry, vcpu->arch.exception.pending is only
400 * true if an event injection was blocked by
401 * nested_run_pending. In that case, however,
402 * vcpu_enter_guest requests an immediate exit,
403 * and the guest shouldn't proceed far enough to
404 * need reinjection.
405 */
406 WARN_ON_ONCE(vcpu->arch.exception.pending);
407 vcpu->arch.exception.injected = true;
408 } else {
409 vcpu->arch.exception.pending = true;
410 vcpu->arch.exception.injected = false;
411 }
3fd28fce
ED		 412 vcpu->arch.exception.has_error_code = has_error;
413 vcpu->arch.exception.nr = nr;
414 vcpu->arch.exception.error_code = error_code;
415 return;
416 }
417
418 /* to check exception */
419 prev_nr = vcpu->arch.exception.nr;
420 if (prev_nr == DF_VECTOR) {
421 /* triple fault -> shutdown */
a8eeb04a 422 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 423 return;
424 }
425 class1 = exception_class(prev_nr);
426 class2 = exception_class(nr);
427 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
428 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 429 /*
430 * Generate double fault per SDM Table 5-5. Set
431 * exception.pending = true so that the double fault
432 * can trigger a nested vmexit.
433 */
3fd28fce 434 vcpu->arch.exception.pending = true;
664f8e26 435 vcpu->arch.exception.injected = false;
3fd28fce
ED		 436 vcpu->arch.exception.has_error_code = true;
437 vcpu->arch.exception.nr = DF_VECTOR;
438 vcpu->arch.exception.error_code = 0;
439 } else
440 /* replace previous exception with a new one in a hope
441 that instruction re-execution will regenerate lost
442 exception */
443 goto queue;
444}
445
298101da
AK		 446void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
447{
ce7ddec4 448 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 449}
450EXPORT_SYMBOL_GPL(kvm_queue_exception);
451
ce7ddec4
JR		 452void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
453{
454 kvm_multiple_exception(vcpu, nr, false, 0, true);
455}
456EXPORT_SYMBOL_GPL(kvm_requeue_exception);
457
6affcbed 458int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 459{
db8fcefa
AP		 460 if (err)
461 kvm_inject_gp(vcpu, 0);
462 else
6affcbed
KH		 463 return kvm_skip_emulated_instruction(vcpu);
464
465 return 1;
db8fcefa
AP		 466}
467EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 468
6389ee94 469void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 470{
471 ++vcpu->stat.pf_guest;
adfe20fb
WL		 472 vcpu->arch.exception.nested_apf =
473 is_guest_mode(vcpu) && fault->async_page_fault;
474 if (vcpu->arch.exception.nested_apf)
475 vcpu->arch.apf.nested_apf_token = fault->address;
476 else
477 vcpu->arch.cr2 = fault->address;
6389ee94 478 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 479}
27d6c865 480EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 481
ef54bcfe 482static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 483{
6389ee94
AK		 484 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
485 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 486 else
6389ee94 487 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 488
489 return fault->nested_page_fault;
d4f8cf66
JR		 490}
491
3419ffc8
SY		 492void kvm_inject_nmi(struct kvm_vcpu *vcpu)
493{
7460fb4a
AK		 494 atomic_inc(&vcpu->arch.nmi_queued);
495 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 496}
497EXPORT_SYMBOL_GPL(kvm_inject_nmi);
498
298101da
AK		 499void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
500{
ce7ddec4 501 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 502}
503EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
504
ce7ddec4
JR		 505void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
506{
507 kvm_multiple_exception(vcpu, nr, true, error_code, true);
508}
509EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
510
0a79b009
AK		 511/*
512 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
513 * a #GP and return false.
514 */
515bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 516{
0a79b009
AK		 517 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
518 return true;
519 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
520 return false;
298101da 521}
0a79b009 522EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 523
16f8a6f9
NA		 524bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
525{
526 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
527 return true;
528
529 kvm_queue_exception(vcpu, UD_VECTOR);
530 return false;
531}
532EXPORT_SYMBOL_GPL(kvm_require_dr);
533
ec92fe44
JR		 534/*
535 * This function will be used to read from the physical memory of the currently
54bf36aa 536 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 537 * can read from guest physical or from the guest's guest physical memory.
538 */
539int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
540 gfn_t ngfn, void *data, int offset, int len,
541 u32 access)
542{
54987b7a 543 struct x86_exception exception;
ec92fe44
JR		 544 gfn_t real_gfn;
545 gpa_t ngpa;
546
547 ngpa = gfn_to_gpa(ngfn);
54987b7a 548 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 549 if (real_gfn == UNMAPPED_GVA)
550 return -EFAULT;
551
552 real_gfn = gpa_to_gfn(real_gfn);
553
54bf36aa 554 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 555}
556EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
557
69b0049a 558static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 559 void *data, int offset, int len, u32 access)
560{
561 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
562 data, offset, len, access);
563}
564
a03490ed
CO		 565/*
566 * Load the pae pdptrs. Return true is they are all valid.
567 */
ff03a073 568int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 569{
570 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
571 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
572 int i;
573 int ret;
ff03a073 574 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 575
ff03a073
JR		 576 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
577 offset * sizeof(u64), sizeof(pdpte),
578 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 579 if (ret < 0) {
580 ret = 0;
581 goto out;
582 }
583 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 584 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 585 (pdpte[i] &
586 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 587 ret = 0;
588 goto out;
589 }
590 }
591 ret = 1;
592
ff03a073 593 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 594 __set_bit(VCPU_EXREG_PDPTR,
595 (unsigned long *)&vcpu->arch.regs_avail);
596 __set_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 598out:
a03490ed
CO		 599
600 return ret;
601}
cc4b6871 602EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 603
9ed38ffa 604bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 605{
ff03a073 606 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 607 bool changed = true;
3d06b8bf
JR		 608 int offset;
609 gfn_t gfn;
d835dfec
AK		 610 int r;
611
612 if (is_long_mode(vcpu) || !is_pae(vcpu))
613 return false;
614
6de4f3ad
AK		 615 if (!test_bit(VCPU_EXREG_PDPTR,
616 (unsigned long *)&vcpu->arch.regs_avail))
617 return true;
618
a512177e
PB		 619 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
620 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 621 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
622 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 623 if (r < 0)
624 goto out;
ff03a073 625 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 626out:
d835dfec
AK		 627
628 return changed;
629}
9ed38ffa 630EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 631
49a9b07e 632int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 633{
aad82703 634 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 635 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 636
f9a48e6a
AK		 637 cr0 |= X86_CR0_ET;
638
ab344828 639#ifdef CONFIG_X86_64
0f12244f
GN		 640 if (cr0 & 0xffffffff00000000UL)
641 return 1;
ab344828
GN		 642#endif
643
644 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 645
0f12244f
GN		 646 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
647 return 1;
a03490ed 648
0f12244f
GN		 649 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
650 return 1;
a03490ed
CO		 651
652 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
653#ifdef CONFIG_X86_64
f6801dff 654 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 655 int cs_db, cs_l;
656
0f12244f
GN		 657 if (!is_pae(vcpu))
658 return 1;
a03490ed 659 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 660 if (cs_l)
661 return 1;
a03490ed
CO		 662 } else
663#endif
ff03a073 664 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 665 kvm_read_cr3(vcpu)))
0f12244f 666 return 1;
a03490ed
CO		 667 }
668
ad756a16
MJ		 669 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
670 return 1;
671
a03490ed 672 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 673
d170c419 674 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 675 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 676 kvm_async_pf_hash_reset(vcpu);
677 }
e5f3f027 678
aad82703
SY		 679 if ((cr0 ^ old_cr0) & update_bits)
680 kvm_mmu_reset_context(vcpu);
b18d5431 681
879ae188
LE		 682 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
683 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
684 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 685 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
686
0f12244f
GN		 687 return 0;
688}
2d3ad1f4 689EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 690
2d3ad1f4 691void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 692{
49a9b07e 693 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 696
42bdf991
MT		 697static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
698{
699 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
700 !vcpu->guest_xcr0_loaded) {
701 /* kvm_set_xcr() also depends on this */
702 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
703 vcpu->guest_xcr0_loaded = 1;
704 }
705}
706
707static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
708{
709 if (vcpu->guest_xcr0_loaded) {
710 if (vcpu->arch.xcr0 != host_xcr0)
711 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
712 vcpu->guest_xcr0_loaded = 0;
713 }
714}
715
69b0049a 716static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 717{
56c103ec
LJ		 718 u64 xcr0 = xcr;
719 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 720 u64 valid_bits;
2acf923e
DC		 721
722 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
723 if (index != XCR_XFEATURE_ENABLED_MASK)
724 return 1;
d91cab78 725 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 726 return 1;
d91cab78 727 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 728 return 1;
46c34cb0
PB		 729
730 /*
731 * Do not allow the guest to set bits that we do not support
732 * saving. However, xcr0 bit 0 is always set, even if the
733 * emulated CPU does not support XSAVE (see fx_init).
734 */
d91cab78 735 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 736 if (xcr0 & ~valid_bits)
2acf923e 737 return 1;
46c34cb0 738
d91cab78
DH		 739 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
740 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 741 return 1;
742
d91cab78
DH		 743 if (xcr0 & XFEATURE_MASK_AVX512) {
744 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 745 return 1;
d91cab78 746 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 747 return 1;
748 }
2acf923e 749 vcpu->arch.xcr0 = xcr0;
56c103ec 750
d91cab78 751 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 752 kvm_update_cpuid(vcpu);
2acf923e
DC		 753 return 0;
754}
755
756int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
757{
764bcbc5
Z		 758 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
759 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 760 kvm_inject_gp(vcpu, 0);
761 return 1;
762 }
763 return 0;
764}
765EXPORT_SYMBOL_GPL(kvm_set_xcr);
766
a83b29c6 767int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 768{
fc78f519 769 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 770 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 771 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 772
0f12244f
GN		 773 if (cr4 & CR4_RESERVED_BITS)
774 return 1;
a03490ed 775
d6321d49 776 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 777 return 1;
778
d6321d49 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 780 return 1;
781
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 783 return 1;
784
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 786 return 1;
787
d6321d49 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 789 return 1;
790
fd8cb433 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 792 return 1;
793
a03490ed 794 if (is_long_mode(vcpu)) {
0f12244f
GN		 795 if (!(cr4 & X86_CR4_PAE))
796 return 1;
a2edf57f
AK		 797 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
798 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 799 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
800 kvm_read_cr3(vcpu)))
0f12244f
GN		 801 return 1;
802
ad756a16 803 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 804 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 805 return 1;
806
807 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
808 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
809 return 1;
810 }
811
5e1746d6 812 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 813 return 1;
a03490ed 814
ad756a16
MJ		 815 if (((cr4 ^ old_cr4) & pdptr_bits) ||
816 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 817 kvm_mmu_reset_context(vcpu);
0f12244f 818
b9baba86 819 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 820 kvm_update_cpuid(vcpu);
2acf923e 821
0f12244f
GN		 822 return 0;
823}
2d3ad1f4 824EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 825
2390218b 826int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 827{
ac146235 828#ifdef CONFIG_X86_64
9d88fca7 829 cr3 &= ~CR3_PCID_INVD;
ac146235 830#endif
9d88fca7 831
9f8fe504 832 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 833 kvm_mmu_sync_roots(vcpu);
77c3913b 834 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 835 return 0;
d835dfec
AK		 836 }
837
d1cd3ce9
YZ		 838 if (is_long_mode(vcpu) &&
839 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
840 return 1;
841 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 842 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 843 return 1;
a03490ed 844
0f12244f 845 vcpu->arch.cr3 = cr3;
aff48baa 846 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 847 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 848 return 0;
849}
2d3ad1f4 850EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 851
eea1cff9 852int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 853{
0f12244f
GN		 854 if (cr8 & CR8_RESERVED_BITS)
855 return 1;
35754c98 856 if (lapic_in_kernel(vcpu))
a03490ed
CO		 857 kvm_lapic_set_tpr(vcpu, cr8);
858 else
ad312c7c 859 vcpu->arch.cr8 = cr8;
0f12244f
GN		 860 return 0;
861}
2d3ad1f4 862EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 863
2d3ad1f4 864unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 865{
35754c98 866 if (lapic_in_kernel(vcpu))
a03490ed
CO		 867 return kvm_lapic_get_cr8(vcpu);
868 else
ad312c7c 869 return vcpu->arch.cr8;
a03490ed 870}
2d3ad1f4 871EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 872
ae561ede
NA		 873static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
874{
875 int i;
876
877 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
878 for (i = 0; i < KVM_NR_DB_REGS; i++)
879 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
880 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
881 }
882}
883
73aaf249
JK		 884static void kvm_update_dr6(struct kvm_vcpu *vcpu)
885{
886 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
887 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
888}
889
c8639010
JK		 890static void kvm_update_dr7(struct kvm_vcpu *vcpu)
891{
892 unsigned long dr7;
893
894 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
895 dr7 = vcpu->arch.guest_debug_dr7;
896 else
897 dr7 = vcpu->arch.dr7;
898 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 899 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
900 if (dr7 & DR7_BP_EN_MASK)
901 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 902}
903
6f43ed01
NA		 904static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
905{
906 u64 fixed = DR6_FIXED_1;
907
d6321d49 908 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 909 fixed |= DR6_RTM;
910 return fixed;
911}
912
338dbc97 913static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 914{
915 switch (dr) {
916 case 0 ... 3:
917 vcpu->arch.db[dr] = val;
918 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
919 vcpu->arch.eff_db[dr] = val;
920 break;
921 case 4:
020df079
GN		 922 /* fall through */
923 case 6:
338dbc97
GN		 924 if (val & 0xffffffff00000000ULL)
925 return -1; /* #GP */
6f43ed01 926 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 927 kvm_update_dr6(vcpu);
020df079
GN		 928 break;
929 case 5:
020df079
GN		 930 /* fall through */
931 default: /* 7 */
338dbc97
GN		 932 if (val & 0xffffffff00000000ULL)
933 return -1; /* #GP */
020df079 934 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 935 kvm_update_dr7(vcpu);
020df079
GN		 936 break;
937 }
938
939 return 0;
940}
338dbc97
GN		 941
942int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
943{
16f8a6f9 944 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 945 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 946 return 1;
947 }
948 return 0;
338dbc97 949}
020df079
GN		 950EXPORT_SYMBOL_GPL(kvm_set_dr);
951
16f8a6f9 952int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 953{
954 switch (dr) {
955 case 0 ... 3:
956 *val = vcpu->arch.db[dr];
957 break;
958 case 4:
020df079
GN		 959 /* fall through */
960 case 6:
73aaf249
JK		 961 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
962 *val = vcpu->arch.dr6;
963 else
964 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 965 break;
966 case 5:
020df079
GN		 967 /* fall through */
968 default: /* 7 */
969 *val = vcpu->arch.dr7;
970 break;
971 }
338dbc97
GN		 972 return 0;
973}
020df079
GN		 974EXPORT_SYMBOL_GPL(kvm_get_dr);
975
022cd0e8
AK		 976bool kvm_rdpmc(struct kvm_vcpu *vcpu)
977{
978 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
979 u64 data;
980 int err;
981
c6702c9d 982 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 983 if (err)
984 return err;
985 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
986 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
987 return err;
988}
989EXPORT_SYMBOL_GPL(kvm_rdpmc);
990
043405e1
CO		 991/*
992 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
993 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
994 *
995 * This list is modified at module load time to reflect the
e3267cbb 996 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 997 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
998 * may depend on host virtualization features rather than host cpu features.
043405e1 999 */
e3267cbb 1000
043405e1
CO		 1001static u32 msrs_to_save[] = {
1002 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1003 MSR_STAR,
043405e1
CO		 1004#ifdef CONFIG_X86_64
1005 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1006#endif
b3897a49 1007 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1008 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 1009};
1010
1011static unsigned num_msrs_to_save;
1012
62ef68bb
PB		 1013static u32 emulated_msrs[] = {
1014 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1015 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1016 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1017 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1018 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1019 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1020 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1021 HV_X64_MSR_RESET,
11c4b1ca 1022 HV_X64_MSR_VP_INDEX,
9eec50b8 1023 HV_X64_MSR_VP_RUNTIME,
5c919412 1024 HV_X64_MSR_SCONTROL,
1f4b34f8 1025 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1026 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1027 MSR_KVM_PV_EOI_EN,
1028
ba904635 1029 MSR_IA32_TSC_ADJUST,
a3e06bbe 1030 MSR_IA32_TSCDEADLINE,
043405e1 1031 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1032 MSR_IA32_MCG_STATUS,
1033 MSR_IA32_MCG_CTL,
c45dcc71 1034 MSR_IA32_MCG_EXT_CTL,
64d60670 1035 MSR_IA32_SMBASE,
db2336a8
KH		 1036 MSR_PLATFORM_INFO,
1037 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1038};
1039
62ef68bb
PB		 1040static unsigned num_emulated_msrs;
1041
384bb783 1042bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1043{
b69e8cae 1044 if (efer & efer_reserved_bits)
384bb783 1045 return false;
15c4a640 1046
1b4d56b8 1047 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1048 return false;
1b2fd70c 1049
1b4d56b8 1050 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1051 return false;
d8017474 1052
384bb783
JK		 1053 return true;
1054}
1055EXPORT_SYMBOL_GPL(kvm_valid_efer);
1056
1057static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1058{
1059 u64 old_efer = vcpu->arch.efer;
1060
1061 if (!kvm_valid_efer(vcpu, efer))
1062 return 1;
1063
1064 if (is_paging(vcpu)
1065 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1066 return 1;
1067
15c4a640 1068 efer &= ~EFER_LMA;
f6801dff 1069 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1070
a3d204e2
SY		 1071 kvm_x86_ops->set_efer(vcpu, efer);
1072
aad82703
SY		 1073 /* Update reserved bits */
1074 if ((efer ^ old_efer) & EFER_NX)
1075 kvm_mmu_reset_context(vcpu);
1076
b69e8cae 1077 return 0;
15c4a640
CO		 1078}
1079
f2b4b7dd
JR		 1080void kvm_enable_efer_bits(u64 mask)
1081{
1082 efer_reserved_bits &= ~mask;
1083}
1084EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1085
15c4a640
CO		 1086/*
1087 * Writes msr value into into the appropriate "register".
1088 * Returns 0 on success, non-0 otherwise.
1089 * Assumes vcpu_load() was already called.
1090 */
8fe8ab46 1091int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1092{
854e8bb1
NA		 1093 switch (msr->index) {
1094 case MSR_FS_BASE:
1095 case MSR_GS_BASE:
1096 case MSR_KERNEL_GS_BASE:
1097 case MSR_CSTAR:
1098 case MSR_LSTAR:
fd8cb433 1099 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1100 return 1;
1101 break;
1102 case MSR_IA32_SYSENTER_EIP:
1103 case MSR_IA32_SYSENTER_ESP:
1104 /*
1105 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1106 * non-canonical address is written on Intel but not on
1107 * AMD (which ignores the top 32-bits, because it does
1108 * not implement 64-bit SYSENTER).
1109 *
1110 * 64-bit code should hence be able to write a non-canonical
1111 * value on AMD. Making the address canonical ensures that
1112 * vmentry does not fail on Intel after writing a non-canonical
1113 * value, and that something deterministic happens if the guest
1114 * invokes 64-bit SYSENTER.
1115 */
fd8cb433 1116 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1117 }
8fe8ab46 1118 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1119}
854e8bb1 1120EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1121
313a3dc7
CO		 1122/*
1123 * Adapt set_msr() to msr_io()'s calling convention
1124 */
609e36d3
PB		 1125static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1126{
1127 struct msr_data msr;
1128 int r;
1129
1130 msr.index = index;
1131 msr.host_initiated = true;
1132 r = kvm_get_msr(vcpu, &msr);
1133 if (r)
1134 return r;
1135
1136 *data = msr.data;
1137 return 0;
1138}
1139
313a3dc7
CO		 1140static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1141{
8fe8ab46
WA		 1142 struct msr_data msr;
1143
1144 msr.data = *data;
1145 msr.index = index;
1146 msr.host_initiated = true;
1147 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1148}
1149
16e8d74d
MT		 1150#ifdef CONFIG_X86_64
1151struct pvclock_gtod_data {
1152 seqcount_t seq;
1153
1154 struct { /* extract of a clocksource struct */
1155 int vclock_mode;
a5a1d1c2
TG		 1156 u64 cycle_last;
1157 u64 mask;
16e8d74d
MT		 1158 u32 mult;
1159 u32 shift;
1160 } clock;
1161
cbcf2dd3
TG		 1162 u64 boot_ns;
1163 u64 nsec_base;
55dd00a7 1164 u64 wall_time_sec;
16e8d74d
MT		 1165};
1166
1167static struct pvclock_gtod_data pvclock_gtod_data;
1168
1169static void update_pvclock_gtod(struct timekeeper *tk)
1170{
1171 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1172 u64 boot_ns;
1173
876e7881 1174 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1175
1176 write_seqcount_begin(&vdata->seq);
1177
1178 /* copy pvclock gtod data */
876e7881
PZ		 1179 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1180 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1181 vdata->clock.mask = tk->tkr_mono.mask;
1182 vdata->clock.mult = tk->tkr_mono.mult;
1183 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1184
cbcf2dd3 1185 vdata->boot_ns = boot_ns;
876e7881 1186 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1187
55dd00a7
MT		 1188 vdata->wall_time_sec = tk->xtime_sec;
1189
16e8d74d
MT		 1190 write_seqcount_end(&vdata->seq);
1191}
1192#endif
1193
bab5bb39
NK		 1194void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1195{
1196 /*
1197 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1198 * vcpu_enter_guest. This function is only called from
1199 * the physical CPU that is running vcpu.
1200 */
1201 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1202}
16e8d74d 1203
18068523
GOC		 1204static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1205{
9ed3c444
AK		 1206 int version;
1207 int r;
50d0a0f9 1208 struct pvclock_wall_clock wc;
87aeb54f 1209 struct timespec64 boot;
18068523
GOC		 1210
1211 if (!wall_clock)
1212 return;
1213
9ed3c444
AK		 1214 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1215 if (r)
1216 return;
1217
1218 if (version & 1)
1219 ++version; /* first time write, random junk */
1220
1221 ++version;
18068523 1222
1dab1345
NK		 1223 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1224 return;
18068523 1225
50d0a0f9
GH		 1226 /*
1227 * The guest calculates current wall clock time by adding
34c238a1 1228 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1229 * wall clock specified here. guest system time equals host
1230 * system time for us, thus we must fill in host boot time here.
1231 */
87aeb54f 1232 getboottime64(&boot);
50d0a0f9 1233
4b648665 1234 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1235 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1236 boot = timespec64_sub(boot, ts);
4b648665 1237 }
87aeb54f 1238 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1239 wc.nsec = boot.tv_nsec;
1240 wc.version = version;
18068523
GOC		 1241
1242 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1243
1244 version++;
1245 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1246}
1247
50d0a0f9
GH		 1248static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1249{
b51012de
PB		 1250 do_shl32_div32(dividend, divisor);
1251 return dividend;
50d0a0f9
GH		 1252}
1253
3ae13faa 1254static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1255 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1256{
5f4e3f88 1257 uint64_t scaled64;
50d0a0f9
GH		 1258 int32_t shift = 0;
1259 uint64_t tps64;
1260 uint32_t tps32;
1261
3ae13faa
PB		 1262 tps64 = base_hz;
1263 scaled64 = scaled_hz;
50933623 1264 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1265 tps64 >>= 1;
1266 shift--;
1267 }
1268
1269 tps32 = (uint32_t)tps64;
50933623
JK		 1270 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1271 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1272 scaled64 >>= 1;
1273 else
1274 tps32 <<= 1;
50d0a0f9
GH		 1275 shift++;
1276 }
1277
5f4e3f88
ZA		 1278 *pshift = shift;
1279 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1280
3ae13faa
PB		 1281 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1282 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1283}
1284
d828199e 1285#ifdef CONFIG_X86_64
16e8d74d 1286static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1287#endif
16e8d74d 1288
c8076604 1289static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1290static unsigned long max_tsc_khz;
c8076604 1291
cc578287 1292static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1293{
cc578287
ZA		 1294 u64 v = (u64)khz * (1000000 + ppm);
1295 do_div(v, 1000000);
1296 return v;
1e993611
JR		 1297}
1298
381d585c
HZ		 1299static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1300{
1301 u64 ratio;
1302
1303 /* Guest TSC same frequency as host TSC? */
1304 if (!scale) {
1305 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1306 return 0;
1307 }
1308
1309 /* TSC scaling supported? */
1310 if (!kvm_has_tsc_control) {
1311 if (user_tsc_khz > tsc_khz) {
1312 vcpu->arch.tsc_catchup = 1;
1313 vcpu->arch.tsc_always_catchup = 1;
1314 return 0;
1315 } else {
1316 WARN(1, "user requested TSC rate below hardware speed\n");
1317 return -1;
1318 }
1319 }
1320
1321 /* TSC scaling required - calculate ratio */
1322 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1323 user_tsc_khz, tsc_khz);
1324
1325 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1326 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1327 user_tsc_khz);
1328 return -1;
1329 }
1330
1331 vcpu->arch.tsc_scaling_ratio = ratio;
1332 return 0;
1333}
1334
4941b8cb 1335static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1336{
cc578287
ZA		 1337 u32 thresh_lo, thresh_hi;
1338 int use_scaling = 0;
217fc9cf 1339
03ba32ca 1340 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1341 if (user_tsc_khz == 0) {
ad721883
HZ		 1342 /* set tsc_scaling_ratio to a safe value */
1343 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1344 return -1;
ad721883 1345 }
03ba32ca 1346
c285545f 1347 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1348 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1349 &vcpu->arch.virtual_tsc_shift,
1350 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1351 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1352
1353 /*
1354 * Compute the variation in TSC rate which is acceptable
1355 * within the range of tolerance and decide if the
1356 * rate being applied is within that bounds of the hardware
1357 * rate. If so, no scaling or compensation need be done.
1358 */
1359 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1360 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1361 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1362 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1363 use_scaling = 1;
1364 }
4941b8cb 1365 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1366}
1367
1368static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1369{
e26101b1 1370 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1371 vcpu->arch.virtual_tsc_mult,
1372 vcpu->arch.virtual_tsc_shift);
e26101b1 1373 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1374 return tsc;
1375}
1376
69b0049a 1377static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1378{
1379#ifdef CONFIG_X86_64
1380 bool vcpus_matched;
b48aa97e
MT		 1381 struct kvm_arch *ka = &vcpu->kvm->arch;
1382 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1383
1384 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1385 atomic_read(&vcpu->kvm->online_vcpus));
1386
7f187922
MT		 1387 /*
1388 * Once the masterclock is enabled, always perform request in
1389 * order to update it.
1390 *
1391 * In order to enable masterclock, the host clocksource must be TSC
1392 * and the vcpus need to have matched TSCs. When that happens,
1393 * perform request to enable masterclock.
1394 */
1395 if (ka->use_master_clock ||
1396 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1397 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1398
1399 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1400 atomic_read(&vcpu->kvm->online_vcpus),
1401 ka->use_master_clock, gtod->clock.vclock_mode);
1402#endif
1403}
1404
ba904635
WA		 1405static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1406{
3e3f5026 1407 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1408 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1409}
1410
35181e86
HZ		 1411/*
1412 * Multiply tsc by a fixed point number represented by ratio.
1413 *
1414 * The most significant 64-N bits (mult) of ratio represent the
1415 * integral part of the fixed point number; the remaining N bits
1416 * (frac) represent the fractional part, ie. ratio represents a fixed
1417 * point number (mult + frac * 2^(-N)).
1418 *
1419 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1420 */
1421static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1422{
1423 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1424}
1425
1426u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1427{
1428 u64 _tsc = tsc;
1429 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1430
1431 if (ratio != kvm_default_tsc_scaling_ratio)
1432 _tsc = __scale_tsc(ratio, tsc);
1433
1434 return _tsc;
1435}
1436EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1437
07c1419a
HZ		 1438static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1439{
1440 u64 tsc;
1441
1442 tsc = kvm_scale_tsc(vcpu, rdtsc());
1443
1444 return target_tsc - tsc;
1445}
1446
4ba76538
HZ		 1447u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1448{
ea26e4ec 1449 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1450}
1451EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1452
a545ab6a
LC		 1453static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1454{
1455 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1456 vcpu->arch.tsc_offset = offset;
1457}
1458
8fe8ab46 1459void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1460{
1461 struct kvm *kvm = vcpu->kvm;
f38e098f 1462 u64 offset, ns, elapsed;
99e3e30a 1463 unsigned long flags;
b48aa97e 1464 bool matched;
0d3da0d2 1465 bool already_matched;
8fe8ab46 1466 u64 data = msr->data;
c5e8ec8e 1467 bool synchronizing = false;
99e3e30a 1468
038f8c11 1469 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1470 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1471 ns = ktime_get_boot_ns();
f38e098f 1472 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1473
03ba32ca 1474 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1475 if (data == 0 && msr->host_initiated) {
1476 /*
1477 * detection of vcpu initialization -- need to sync
1478 * with other vCPUs. This particularly helps to keep
1479 * kvm_clock stable after CPU hotplug
1480 */
1481 synchronizing = true;
1482 } else {
1483 u64 tsc_exp = kvm->arch.last_tsc_write +
1484 nsec_to_cycles(vcpu, elapsed);
1485 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1486 /*
1487 * Special case: TSC write with a small delta (1 second)
1488 * of virtual cycle time against real time is
1489 * interpreted as an attempt to synchronize the CPU.
1490 */
1491 synchronizing = data < tsc_exp + tsc_hz &&
1492 data + tsc_hz > tsc_exp;
1493 }
c5e8ec8e 1494 }
f38e098f
ZA		 1495
1496 /*
5d3cb0f6
ZA		 1497 * For a reliable TSC, we can match TSC offsets, and for an unstable
1498 * TSC, we add elapsed time in this computation. We could let the
1499 * compensation code attempt to catch up if we fall behind, but
1500 * it's better to try to match offsets from the beginning.
1501 */
c5e8ec8e 1502 if (synchronizing &&
5d3cb0f6 1503 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1504 if (!check_tsc_unstable()) {
e26101b1 1505 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1506 pr_debug("kvm: matched tsc offset for %llu\n", data);
1507 } else {
857e4099 1508 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1509 data += delta;
07c1419a 1510 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1511 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1512 }
b48aa97e 1513 matched = true;
0d3da0d2 1514 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1515 } else {
1516 /*
1517 * We split periods of matched TSC writes into generations.
1518 * For each generation, we track the original measured
1519 * nanosecond time, offset, and write, so if TSCs are in
1520 * sync, we can match exact offset, and if not, we can match
4a969980 1521 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1522 *
1523 * These values are tracked in kvm->arch.cur_xxx variables.
1524 */
1525 kvm->arch.cur_tsc_generation++;
1526 kvm->arch.cur_tsc_nsec = ns;
1527 kvm->arch.cur_tsc_write = data;
1528 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1529 matched = false;
0d3da0d2 1530 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1531 kvm->arch.cur_tsc_generation, data);
f38e098f 1532 }
e26101b1
ZA		 1533
1534 /*
1535 * We also track th most recent recorded KHZ, write and time to
1536 * allow the matching interval to be extended at each write.
1537 */
f38e098f
ZA		 1538 kvm->arch.last_tsc_nsec = ns;
1539 kvm->arch.last_tsc_write = data;
5d3cb0f6 1540 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1541
b183aa58 1542 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1543
1544 /* Keep track of which generation this VCPU has synchronized to */
1545 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1546 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1547 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1548
d6321d49 1549 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1550 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1551
a545ab6a 1552 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1553 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1554
1555 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1556 if (!matched) {
b48aa97e 1557 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1558 } else if (!already_matched) {
1559 kvm->arch.nr_vcpus_matched_tsc++;
1560 }
b48aa97e
MT		 1561
1562 kvm_track_tsc_matching(vcpu);
1563 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1564}
e26101b1 1565
99e3e30a
ZA		 1566EXPORT_SYMBOL_GPL(kvm_write_tsc);
1567
58ea6767
HZ		 1568static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1569 s64 adjustment)
1570{
ea26e4ec 1571 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1572}
1573
1574static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1575{
1576 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1577 WARN_ON(adjustment < 0);
1578 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1579 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1580}
1581
d828199e
MT		 1582#ifdef CONFIG_X86_64
1583
a5a1d1c2 1584static u64 read_tsc(void)
d828199e 1585{
a5a1d1c2 1586 u64 ret = (u64)rdtsc_ordered();
03b9730b 1587 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1588
1589 if (likely(ret >= last))
1590 return ret;
1591
1592 /*
1593 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1594 * predictable (it's just a function of time and the likely is
d828199e
MT		 1595 * very likely) and there's a data dependence, so force GCC
1596 * to generate a branch instead. I don't barrier() because
1597 * we don't actually need a barrier, and if this function
1598 * ever gets inlined it will generate worse code.
1599 */
1600 asm volatile ("");
1601 return last;
1602}
1603
a5a1d1c2 1604static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1605{
1606 long v;
1607 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1608
1609 *cycle_now = read_tsc();
1610
1611 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1612 return v * gtod->clock.mult;
1613}
1614
a5a1d1c2 1615static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1616{
cbcf2dd3 1617 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1618 unsigned long seq;
d828199e 1619 int mode;
cbcf2dd3 1620 u64 ns;
d828199e 1621
d828199e
MT		 1622 do {
1623 seq = read_seqcount_begin(&gtod->seq);
1624 mode = gtod->clock.vclock_mode;
cbcf2dd3 1625 ns = gtod->nsec_base;
d828199e
MT		 1626 ns += vgettsc(cycle_now);
1627 ns >>= gtod->clock.shift;
cbcf2dd3 1628 ns += gtod->boot_ns;
d828199e 1629 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1630 *t = ns;
d828199e
MT		 1631
1632 return mode;
1633}
1634
55dd00a7
MT		 1635static int do_realtime(struct timespec *ts, u64 *cycle_now)
1636{
1637 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1638 unsigned long seq;
1639 int mode;
1640 u64 ns;
1641
1642 do {
1643 seq = read_seqcount_begin(&gtod->seq);
1644 mode = gtod->clock.vclock_mode;
1645 ts->tv_sec = gtod->wall_time_sec;
1646 ns = gtod->nsec_base;
1647 ns += vgettsc(cycle_now);
1648 ns >>= gtod->clock.shift;
1649 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1650
1651 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1652 ts->tv_nsec = ns;
1653
1654 return mode;
1655}
1656
d828199e 1657/* returns true if host is using tsc clocksource */
a5a1d1c2 1658static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1659{
d828199e
MT		 1660 /* checked again under seqlock below */
1661 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1662 return false;
1663
cbcf2dd3 1664 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1665}
55dd00a7
MT		 1666
1667/* returns true if host is using tsc clocksource */
1668static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1669 u64 *cycle_now)
1670{
1671 /* checked again under seqlock below */
1672 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1673 return false;
1674
1675 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1676}
d828199e
MT		 1677#endif
1678
1679/*
1680 *
b48aa97e
MT		 1681 * Assuming a stable TSC across physical CPUS, and a stable TSC
1682 * across virtual CPUs, the following condition is possible.
1683 * Each numbered line represents an event visible to both
d828199e
MT		 1684 * CPUs at the next numbered event.
1685 *
1686 * "timespecX" represents host monotonic time. "tscX" represents
1687 * RDTSC value.
1688 *
1689 * VCPU0 on CPU0 | VCPU1 on CPU1
1690 *
1691 * 1. read timespec0,tsc0
1692 * 2. | timespec1 = timespec0 + N
1693 * | tsc1 = tsc0 + M
1694 * 3. transition to guest | transition to guest
1695 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1696 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1697 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1698 *
1699 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1700 *
1701 * - ret0 < ret1
1702 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1703 * ...
1704 * - 0 < N - M => M < N
1705 *
1706 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1707 * always the case (the difference between two distinct xtime instances
1708 * might be smaller then the difference between corresponding TSC reads,
1709 * when updating guest vcpus pvclock areas).
1710 *
1711 * To avoid that problem, do not allow visibility of distinct
1712 * system_timestamp/tsc_timestamp values simultaneously: use a master
1713 * copy of host monotonic time values. Update that master copy
1714 * in lockstep.
1715 *
b48aa97e 1716 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1717 *
1718 */
1719
1720static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1721{
1722#ifdef CONFIG_X86_64
1723 struct kvm_arch *ka = &kvm->arch;
1724 int vclock_mode;
b48aa97e
MT		 1725 bool host_tsc_clocksource, vcpus_matched;
1726
1727 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1728 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1729
1730 /*
1731 * If the host uses TSC clock, then passthrough TSC as stable
1732 * to the guest.
1733 */
b48aa97e 1734 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1735 &ka->master_kernel_ns,
1736 &ka->master_cycle_now);
1737
16a96021 1738 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1739 && !ka->backwards_tsc_observed
54750f2c 1740 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1741
d828199e
MT		 1742 if (ka->use_master_clock)
1743 atomic_set(&kvm_guest_has_master_clock, 1);
1744
1745 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1746 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1747 vcpus_matched);
d828199e
MT		 1748#endif
1749}
1750
2860c4b1
PB		 1751void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1752{
1753 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1754}
1755
2e762ff7
MT		 1756static void kvm_gen_update_masterclock(struct kvm *kvm)
1757{
1758#ifdef CONFIG_X86_64
1759 int i;
1760 struct kvm_vcpu *vcpu;
1761 struct kvm_arch *ka = &kvm->arch;
1762
1763 spin_lock(&ka->pvclock_gtod_sync_lock);
1764 kvm_make_mclock_inprogress_request(kvm);
1765 /* no guest entries from this point */
1766 pvclock_update_vm_gtod_copy(kvm);
1767
1768 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1769 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1770
1771 /* guest entries allowed */
1772 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1773 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1774
1775 spin_unlock(&ka->pvclock_gtod_sync_lock);
1776#endif
1777}
1778
e891a32e 1779u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1780{
108b249c 1781 struct kvm_arch *ka = &kvm->arch;
8b953440 1782 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1783 u64 ret;
108b249c 1784
8b953440
PB		 1785 spin_lock(&ka->pvclock_gtod_sync_lock);
1786 if (!ka->use_master_clock) {
1787 spin_unlock(&ka->pvclock_gtod_sync_lock);
1788 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1789 }
1790
8b953440
PB		 1791 hv_clock.tsc_timestamp = ka->master_cycle_now;
1792 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1793 spin_unlock(&ka->pvclock_gtod_sync_lock);
1794
e2c2206a
WL		 1795 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1796 get_cpu();
1797
8b953440
PB		 1798 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1799 &hv_clock.tsc_shift,
1800 &hv_clock.tsc_to_system_mul);
e2c2206a
WL		 1801 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1802
1803 put_cpu();
1804
1805 return ret;
108b249c
PB		 1806}
1807
0d6dd2ff
PB		 1808static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1809{
1810 struct kvm_vcpu_arch *vcpu = &v->arch;
1811 struct pvclock_vcpu_time_info guest_hv_clock;
1812
4e335d9e 1813 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1814 &guest_hv_clock, sizeof(guest_hv_clock))))
1815 return;
1816
1817 /* This VCPU is paused, but it's legal for a guest to read another
1818 * VCPU's kvmclock, so we really have to follow the specification where
1819 * it says that version is odd if data is being modified, and even after
1820 * it is consistent.
1821 *
1822 * Version field updates must be kept separate. This is because
1823 * kvm_write_guest_cached might use a "rep movs" instruction, and
1824 * writes within a string instruction are weakly ordered. So there
1825 * are three writes overall.
1826 *
1827 * As a small optimization, only write the version field in the first
1828 * and third write. The vcpu->pv_time cache is still valid, because the
1829 * version field is the first in the struct.
1830 */
1831 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1832
1833 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1834 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1835 &vcpu->hv_clock,
1836 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1837
1838 smp_wmb();
1839
1840 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1841 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1842
1843 if (vcpu->pvclock_set_guest_stopped_request) {
1844 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1845 vcpu->pvclock_set_guest_stopped_request = false;
1846 }
1847
1848 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1849
4e335d9e
PB		 1850 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1851 &vcpu->hv_clock,
1852 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1853
1854 smp_wmb();
1855
1856 vcpu->hv_clock.version++;
4e335d9e
PB		 1857 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1858 &vcpu->hv_clock,
1859 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1860}
1861
34c238a1 1862static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1863{
78db6a50 1864 unsigned long flags, tgt_tsc_khz;
18068523 1865 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1866 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1867 s64 kernel_ns;
d828199e 1868 u64 tsc_timestamp, host_tsc;
51d59c6b 1869 u8 pvclock_flags;
d828199e
MT		 1870 bool use_master_clock;
1871
1872 kernel_ns = 0;
1873 host_tsc = 0;
18068523 1874
d828199e
MT		 1875 /*
1876 * If the host uses TSC clock, then passthrough TSC as stable
1877 * to the guest.
1878 */
1879 spin_lock(&ka->pvclock_gtod_sync_lock);
1880 use_master_clock = ka->use_master_clock;
1881 if (use_master_clock) {
1882 host_tsc = ka->master_cycle_now;
1883 kernel_ns = ka->master_kernel_ns;
1884 }
1885 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1886
1887 /* Keep irq disabled to prevent changes to the clock */
1888 local_irq_save(flags);
78db6a50
PB		 1889 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1890 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1891 local_irq_restore(flags);
1892 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1893 return 1;
1894 }
d828199e 1895 if (!use_master_clock) {
4ea1636b 1896 host_tsc = rdtsc();
108b249c 1897 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1898 }
1899
4ba76538 1900 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1901
c285545f
ZA		 1902 /*
1903 * We may have to catch up the TSC to match elapsed wall clock
1904 * time for two reasons, even if kvmclock is used.
1905 * 1) CPU could have been running below the maximum TSC rate
1906 * 2) Broken TSC compensation resets the base at each VCPU
1907 * entry to avoid unknown leaps of TSC even when running
1908 * again on the same CPU. This may cause apparent elapsed
1909 * time to disappear, and the guest to stand still or run
1910 * very slowly.
1911 */
1912 if (vcpu->tsc_catchup) {
1913 u64 tsc = compute_guest_tsc(v, kernel_ns);
1914 if (tsc > tsc_timestamp) {
f1e2b260 1915 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1916 tsc_timestamp = tsc;
1917 }
50d0a0f9
GH		 1918 }
1919
18068523
GOC		 1920 local_irq_restore(flags);
1921
0d6dd2ff 1922 /* With all the info we got, fill in the values */
18068523 1923
78db6a50
PB		 1924 if (kvm_has_tsc_control)
1925 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1926
1927 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1928 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1929 &vcpu->hv_clock.tsc_shift,
1930 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1931 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1932 }
1933
1d5f066e 1934 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1935 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1936 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1937
d828199e 1938 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1939 pvclock_flags = 0;
d828199e
MT		 1940 if (use_master_clock)
1941 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1942
78c0337a
MT		 1943 vcpu->hv_clock.flags = pvclock_flags;
1944
095cf55d
PB		 1945 if (vcpu->pv_time_enabled)
1946 kvm_setup_pvclock_page(v);
1947 if (v == kvm_get_vcpu(v->kvm, 0))
1948 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1949 return 0;
c8076604
GH		 1950}
1951
0061d53d
MT		 1952/*
1953 * kvmclock updates which are isolated to a given vcpu, such as
1954 * vcpu->cpu migration, should not allow system_timestamp from
1955 * the rest of the vcpus to remain static. Otherwise ntp frequency
1956 * correction applies to one vcpu's system_timestamp but not
1957 * the others.
1958 *
1959 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1960 * We need to rate-limit these requests though, as they can
1961 * considerably slow guests that have a large number of vcpus.
1962 * The time for a remote vcpu to update its kvmclock is bound
1963 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1964 */
1965
7e44e449
AJ		 1966#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1967
1968static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1969{
1970 int i;
7e44e449
AJ		 1971 struct delayed_work *dwork = to_delayed_work(work);
1972 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1973 kvmclock_update_work);
1974 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1975 struct kvm_vcpu *vcpu;
1976
1977 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1978 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1979 kvm_vcpu_kick(vcpu);
1980 }
1981}
1982
7e44e449
AJ		 1983static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1984{
1985 struct kvm *kvm = v->kvm;
1986
105b21bb 1987 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1988 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1989 KVMCLOCK_UPDATE_DELAY);
1990}
1991
332967a3
AJ		 1992#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1993
1994static void kvmclock_sync_fn(struct work_struct *work)
1995{
1996 struct delayed_work *dwork = to_delayed_work(work);
1997 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1998 kvmclock_sync_work);
1999 struct kvm *kvm = container_of(ka, struct kvm, arch);
2000
630994b3
MT		 2001 if (!kvmclock_periodic_sync)
2002 return;
2003
332967a3
AJ		 2004 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2005 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2006 KVMCLOCK_SYNC_PERIOD);
2007}
2008
9ffd986c 2009static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2010{
890ca9ae
HY		 2011 u64 mcg_cap = vcpu->arch.mcg_cap;
2012 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2013 u32 msr = msr_info->index;
2014 u64 data = msr_info->data;
890ca9ae 2015
15c4a640 2016 switch (msr) {
15c4a640 2017 case MSR_IA32_MCG_STATUS:
890ca9ae 2018 vcpu->arch.mcg_status = data;
15c4a640 2019 break;
c7ac679c 2020 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2021 if (!(mcg_cap & MCG_CTL_P))
2022 return 1;
2023 if (data != 0 && data != ~(u64)0)
2024 return -1;
2025 vcpu->arch.mcg_ctl = data;
2026 break;
2027 default:
2028 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2029 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2030 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2031 /* only 0 or all 1s can be written to IA32_MCi_CTL
2032 * some Linux kernels though clear bit 10 in bank 4 to
2033 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2034 * this to avoid an uncatched #GP in the guest
2035 */
890ca9ae 2036 if ((offset & 0x3) == 0 &&
114be429 2037 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2038 return -1;
9ffd986c
WL		 2039 if (!msr_info->host_initiated &&
2040 (offset & 0x3) == 1 && data != 0)
2041 return -1;
890ca9ae
HY		 2042 vcpu->arch.mce_banks[offset] = data;
2043 break;
2044 }
2045 return 1;
2046 }
2047 return 0;
2048}
2049
ffde22ac
ES		 2050static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2051{
2052 struct kvm *kvm = vcpu->kvm;
2053 int lm = is_long_mode(vcpu);
2054 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2055 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2056 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2057 : kvm->arch.xen_hvm_config.blob_size_32;
2058 u32 page_num = data & ~PAGE_MASK;
2059 u64 page_addr = data & PAGE_MASK;
2060 u8 *page;
2061 int r;
2062
2063 r = -E2BIG;
2064 if (page_num >= blob_size)
2065 goto out;
2066 r = -ENOMEM;
ff5c2c03
SL		 2067 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2068 if (IS_ERR(page)) {
2069 r = PTR_ERR(page);
ffde22ac 2070 goto out;
ff5c2c03 2071 }
54bf36aa 2072 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2073 goto out_free;
2074 r = 0;
2075out_free:
2076 kfree(page);
2077out:
2078 return r;
2079}
2080
344d9588
GN		 2081static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2082{
2083 gpa_t gpa = data & ~0x3f;
2084
52a5c155
WL		 2085 /* Bits 3:5 are reserved, Should be zero */
2086 if (data & 0x38)
344d9588
GN		 2087 return 1;
2088
2089 vcpu->arch.apf.msr_val = data;
2090
2091 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2092 kvm_clear_async_pf_completion_queue(vcpu);
2093 kvm_async_pf_hash_reset(vcpu);
2094 return 0;
2095 }
2096
4e335d9e 2097 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2098 sizeof(u32)))
344d9588
GN		 2099 return 1;
2100
6adba527 2101 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2102 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2103 kvm_async_pf_wakeup_all(vcpu);
2104 return 0;
2105}
2106
12f9a48f
GC		 2107static void kvmclock_reset(struct kvm_vcpu *vcpu)
2108{
0b79459b 2109 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2110}
2111
c9aaa895
GC		 2112static void record_steal_time(struct kvm_vcpu *vcpu)
2113{
2114 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2115 return;
2116
4e335d9e 2117 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2118 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2119 return;
2120
0b9f6c46
PX		 2121 vcpu->arch.st.steal.preempted = 0;
2122
35f3fae1
WL		 2123 if (vcpu->arch.st.steal.version & 1)
2124 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2125
2126 vcpu->arch.st.steal.version += 1;
2127
4e335d9e 2128 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2129 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2130
2131 smp_wmb();
2132
c54cdf14
LC		 2133 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2134 vcpu->arch.st.last_steal;
2135 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2136
4e335d9e 2137 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2138 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2139
2140 smp_wmb();
2141
2142 vcpu->arch.st.steal.version += 1;
c9aaa895 2143
4e335d9e 2144 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2145 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2146}
2147
8fe8ab46 2148int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2149{
5753785f 2150 bool pr = false;
8fe8ab46
WA		 2151 u32 msr = msr_info->index;
2152 u64 data = msr_info->data;
5753785f 2153
15c4a640 2154 switch (msr) {
2e32b719
BP		 2155 case MSR_AMD64_NB_CFG:
2156 case MSR_IA32_UCODE_REV:
2157 case MSR_IA32_UCODE_WRITE:
2158 case MSR_VM_HSAVE_PA:
2159 case MSR_AMD64_PATCH_LOADER:
2160 case MSR_AMD64_BU_CFG2:
405a353a 2161 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2162 break;
2163
15c4a640 2164 case MSR_EFER:
b69e8cae 2165 return set_efer(vcpu, data);
8f1589d9
AP		 2166 case MSR_K7_HWCR:
2167 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2168 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2169 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2170 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2171 if (data != 0) {
a737f256
CD		 2172 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2173 data);
8f1589d9
AP		 2174 return 1;
2175 }
15c4a640 2176 break;
f7c6d140
AP		 2177 case MSR_FAM10H_MMIO_CONF_BASE:
2178 if (data != 0) {
a737f256
CD		 2179 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2180 "0x%llx\n", data);
f7c6d140
AP		 2181 return 1;
2182 }
15c4a640 2183 break;
b5e2fec0
AG		 2184 case MSR_IA32_DEBUGCTLMSR:
2185 if (!data) {
2186 /* We support the non-activated case already */
2187 break;
2188 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2189 /* Values other than LBR and BTF are vendor-specific,
2190 thus reserved and should throw a #GP */
2191 return 1;
2192 }
a737f256
CD		 2193 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2194 __func__, data);
b5e2fec0 2195 break;
9ba075a6 2196 case 0x200 ... 0x2ff:
ff53604b 2197 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2198 case MSR_IA32_APICBASE:
58cb628d 2199 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2200 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2201 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2202 case MSR_IA32_TSCDEADLINE:
2203 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2204 break;
ba904635 2205 case MSR_IA32_TSC_ADJUST:
d6321d49 2206 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2207 if (!msr_info->host_initiated) {
d913b904 2208 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2209 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2210 }
2211 vcpu->arch.ia32_tsc_adjust_msr = data;
2212 }
2213 break;
15c4a640 2214 case MSR_IA32_MISC_ENABLE:
ad312c7c 2215 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2216 break;
64d60670
PB		 2217 case MSR_IA32_SMBASE:
2218 if (!msr_info->host_initiated)
2219 return 1;
2220 vcpu->arch.smbase = data;
2221 break;
11c6bffa 2222 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2223 case MSR_KVM_WALL_CLOCK:
2224 vcpu->kvm->arch.wall_clock = data;
2225 kvm_write_wall_clock(vcpu->kvm, data);
2226 break;
11c6bffa 2227 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2228 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2229 struct kvm_arch *ka = &vcpu->kvm->arch;
2230
12f9a48f 2231 kvmclock_reset(vcpu);
18068523 2232
54750f2c
MT		 2233 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2234 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2235
2236 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2237 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2238
2239 ka->boot_vcpu_runs_old_kvmclock = tmp;
2240 }
2241
18068523 2242 vcpu->arch.time = data;
0061d53d 2243 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2244
2245 /* we verify if the enable bit is set... */
2246 if (!(data & 1))
2247 break;
2248
4e335d9e 2249 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2250 &vcpu->arch.pv_time, data & ~1ULL,
2251 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2252 vcpu->arch.pv_time_enabled = false;
2253 else
2254 vcpu->arch.pv_time_enabled = true;
32cad84f 2255
18068523
GOC		 2256 break;
2257 }
344d9588
GN		 2258 case MSR_KVM_ASYNC_PF_EN:
2259 if (kvm_pv_enable_async_pf(vcpu, data))
2260 return 1;
2261 break;
c9aaa895
GC		 2262 case MSR_KVM_STEAL_TIME:
2263
2264 if (unlikely(!sched_info_on()))
2265 return 1;
2266
2267 if (data & KVM_STEAL_RESERVED_MASK)
2268 return 1;
2269
4e335d9e 2270 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2271 data & KVM_STEAL_VALID_BITS,
2272 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2273 return 1;
2274
2275 vcpu->arch.st.msr_val = data;
2276
2277 if (!(data & KVM_MSR_ENABLED))
2278 break;
2279
c9aaa895
GC		 2280 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2281
2282 break;
ae7a2a3f
MT		 2283 case MSR_KVM_PV_EOI_EN:
2284 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2285 return 1;
2286 break;
c9aaa895 2287
890ca9ae
HY		 2288 case MSR_IA32_MCG_CTL:
2289 case MSR_IA32_MCG_STATUS:
81760dcc 2290 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2291 return set_msr_mce(vcpu, msr_info);
71db6023 2292
6912ac32
WH		 2293 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2294 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2295 pr = true; /* fall through */
2296 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2297 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2298 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2299 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2300
2301 if (pr || data != 0)
a737f256
CD		 2302 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2303 "0x%x data 0x%llx\n", msr, data);
5753785f 2304 break;
84e0cefa
JS		 2305 case MSR_K7_CLK_CTL:
2306 /*
2307 * Ignore all writes to this no longer documented MSR.
2308 * Writes are only relevant for old K7 processors,
2309 * all pre-dating SVM, but a recommended workaround from
4a969980 2310 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2311 * affected processor models on the command line, hence
2312 * the need to ignore the workaround.
2313 */
2314 break;
55cd8e5a 2315 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2316 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2317 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2318 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2319 return kvm_hv_set_msr_common(vcpu, msr, data,
2320 msr_info->host_initiated);
91c9c3ed 2321 case MSR_IA32_BBL_CR_CTL3:
2322 /* Drop writes to this legacy MSR -- see rdmsr
2323 * counterpart for further detail.
2324 */
796f4687 2325 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2326 break;
2b036c6b 2327 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2328 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2329 return 1;
2330 vcpu->arch.osvw.length = data;
2331 break;
2332 case MSR_AMD64_OSVW_STATUS:
d6321d49 2333 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2334 return 1;
2335 vcpu->arch.osvw.status = data;
2336 break;
db2336a8
KH		 2337 case MSR_PLATFORM_INFO:
2338 if (!msr_info->host_initiated ||
2339 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2340 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2341 cpuid_fault_enabled(vcpu)))
2342 return 1;
2343 vcpu->arch.msr_platform_info = data;
2344 break;
2345 case MSR_MISC_FEATURES_ENABLES:
2346 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2347 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2348 !supports_cpuid_fault(vcpu)))
2349 return 1;
2350 vcpu->arch.msr_misc_features_enables = data;
2351 break;
15c4a640 2352 default:
ffde22ac
ES		 2353 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2354 return xen_hvm_config(vcpu, data);
c6702c9d 2355 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2356 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2357 if (!ignore_msrs) {
ae0f5499 2358 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2359 msr, data);
ed85c068
AP		 2360 return 1;
2361 } else {
796f4687 2362 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2363 msr, data);
ed85c068
AP		 2364 break;
2365 }
15c4a640
CO		 2366 }
2367 return 0;
2368}
2369EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2370
2371
2372/*
2373 * Reads an msr value (of 'msr_index') into 'pdata'.
2374 * Returns 0 on success, non-0 otherwise.
2375 * Assumes vcpu_load() was already called.
2376 */
609e36d3 2377int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2378{
609e36d3 2379 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2380}
ff651cb6 2381EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2382
890ca9ae 2383static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2384{
2385 u64 data;
890ca9ae
HY		 2386 u64 mcg_cap = vcpu->arch.mcg_cap;
2387 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2388
2389 switch (msr) {
15c4a640
CO		 2390 case MSR_IA32_P5_MC_ADDR:
2391 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2392 data = 0;
2393 break;
15c4a640 2394 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2395 data = vcpu->arch.mcg_cap;
2396 break;
c7ac679c 2397 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2398 if (!(mcg_cap & MCG_CTL_P))
2399 return 1;
2400 data = vcpu->arch.mcg_ctl;
2401 break;
2402 case MSR_IA32_MCG_STATUS:
2403 data = vcpu->arch.mcg_status;
2404 break;
2405 default:
2406 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2407 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2408 u32 offset = msr - MSR_IA32_MC0_CTL;
2409 data = vcpu->arch.mce_banks[offset];
2410 break;
2411 }
2412 return 1;
2413 }
2414 *pdata = data;
2415 return 0;
2416}
2417
609e36d3 2418int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2419{
609e36d3 2420 switch (msr_info->index) {
890ca9ae 2421 case MSR_IA32_PLATFORM_ID:
15c4a640 2422 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2423 case MSR_IA32_DEBUGCTLMSR:
2424 case MSR_IA32_LASTBRANCHFROMIP:
2425 case MSR_IA32_LASTBRANCHTOIP:
2426 case MSR_IA32_LASTINTFROMIP:
2427 case MSR_IA32_LASTINTTOIP:
60af2ecd 2428 case MSR_K8_SYSCFG:
3afb1121
PB		 2429 case MSR_K8_TSEG_ADDR:
2430 case MSR_K8_TSEG_MASK:
60af2ecd 2431 case MSR_K7_HWCR:
61a6bd67 2432 case MSR_VM_HSAVE_PA:
1fdbd48c 2433 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2434 case MSR_AMD64_NB_CFG:
f7c6d140 2435 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2436 case MSR_AMD64_BU_CFG2:
0c2df2a1 2437 case MSR_IA32_PERF_CTL:
405a353a 2438 case MSR_AMD64_DC_CFG:
609e36d3 2439 msr_info->data = 0;
15c4a640 2440 break;
6912ac32
WH		 2441 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2442 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2443 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2444 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2445 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2446 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2447 msr_info->data = 0;
5753785f 2448 break;
742bc670 2449 case MSR_IA32_UCODE_REV:
609e36d3 2450 msr_info->data = 0x100000000ULL;
742bc670 2451 break;
9ba075a6 2452 case MSR_MTRRcap:
9ba075a6 2453 case 0x200 ... 0x2ff:
ff53604b 2454 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2455 case 0xcd: /* fsb frequency */
609e36d3 2456 msr_info->data = 3;
15c4a640 2457 break;
7b914098
JS		 2458 /*
2459 * MSR_EBC_FREQUENCY_ID
2460 * Conservative value valid for even the basic CPU models.
2461 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2462 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2463 * and 266MHz for model 3, or 4. Set Core Clock
2464 * Frequency to System Bus Frequency Ratio to 1 (bits
2465 * 31:24) even though these are only valid for CPU
2466 * models > 2, however guests may end up dividing or
2467 * multiplying by zero otherwise.
2468 */
2469 case MSR_EBC_FREQUENCY_ID:
609e36d3 2470 msr_info->data = 1 << 24;
7b914098 2471 break;
15c4a640 2472 case MSR_IA32_APICBASE:
609e36d3 2473 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2474 break;
0105d1a5 2475 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2476 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2477 break;
a3e06bbe 2478 case MSR_IA32_TSCDEADLINE:
609e36d3 2479 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2480 break;
ba904635 2481 case MSR_IA32_TSC_ADJUST:
609e36d3 2482 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2483 break;
15c4a640 2484 case MSR_IA32_MISC_ENABLE:
609e36d3 2485 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2486 break;
64d60670
PB		 2487 case MSR_IA32_SMBASE:
2488 if (!msr_info->host_initiated)
2489 return 1;
2490 msr_info->data = vcpu->arch.smbase;
15c4a640 2491 break;
847f0ad8
AG		 2492 case MSR_IA32_PERF_STATUS:
2493 /* TSC increment by tick */
609e36d3 2494 msr_info->data = 1000ULL;
847f0ad8 2495 /* CPU multiplier */
b0996ae4 2496 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2497 break;
15c4a640 2498 case MSR_EFER:
609e36d3 2499 msr_info->data = vcpu->arch.efer;
15c4a640 2500 break;
18068523 2501 case MSR_KVM_WALL_CLOCK:
11c6bffa 2502 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2503 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2504 break;
2505 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2506 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2507 msr_info->data = vcpu->arch.time;
18068523 2508 break;
344d9588 2509 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2510 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2511 break;
c9aaa895 2512 case MSR_KVM_STEAL_TIME:
609e36d3 2513 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2514 break;
1d92128f 2515 case MSR_KVM_PV_EOI_EN:
609e36d3 2516 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2517 break;
890ca9ae
HY		 2518 case MSR_IA32_P5_MC_ADDR:
2519 case MSR_IA32_P5_MC_TYPE:
2520 case MSR_IA32_MCG_CAP:
2521 case MSR_IA32_MCG_CTL:
2522 case MSR_IA32_MCG_STATUS:
81760dcc 2523 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2524 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2525 case MSR_K7_CLK_CTL:
2526 /*
2527 * Provide expected ramp-up count for K7. All other
2528 * are set to zero, indicating minimum divisors for
2529 * every field.
2530 *
2531 * This prevents guest kernels on AMD host with CPU
2532 * type 6, model 8 and higher from exploding due to
2533 * the rdmsr failing.
2534 */
609e36d3 2535 msr_info->data = 0x20000000;
84e0cefa 2536 break;
55cd8e5a 2537 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2538 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2539 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2540 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2541 return kvm_hv_get_msr_common(vcpu,
2542 msr_info->index, &msr_info->data);
55cd8e5a 2543 break;
91c9c3ed 2544 case MSR_IA32_BBL_CR_CTL3:
2545 /* This legacy MSR exists but isn't fully documented in current
2546 * silicon. It is however accessed by winxp in very narrow
2547 * scenarios where it sets bit #19, itself documented as
2548 * a "reserved" bit. Best effort attempt to source coherent
2549 * read data here should the balance of the register be
2550 * interpreted by the guest:
2551 *
2552 * L2 cache control register 3: 64GB range, 256KB size,
2553 * enabled, latency 0x1, configured
2554 */
609e36d3 2555 msr_info->data = 0xbe702111;
91c9c3ed 2556 break;
2b036c6b 2557 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2558 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2559 return 1;
609e36d3 2560 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2561 break;
2562 case MSR_AMD64_OSVW_STATUS:
d6321d49 2563 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2564 return 1;
609e36d3 2565 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2566 break;
db2336a8
KH		 2567 case MSR_PLATFORM_INFO:
2568 msr_info->data = vcpu->arch.msr_platform_info;
2569 break;
2570 case MSR_MISC_FEATURES_ENABLES:
2571 msr_info->data = vcpu->arch.msr_misc_features_enables;
2572 break;
15c4a640 2573 default:
c6702c9d 2574 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2575 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2576 if (!ignore_msrs) {
ae0f5499
BD		 2577 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2578 msr_info->index);
ed85c068
AP		 2579 return 1;
2580 } else {
609e36d3
PB		 2581 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2582 msr_info->data = 0;
ed85c068
AP		 2583 }
2584 break;
15c4a640 2585 }
15c4a640
CO		 2586 return 0;
2587}
2588EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2589
313a3dc7
CO		 2590/*
2591 * Read or write a bunch of msrs. All parameters are kernel addresses.
2592 *
2593 * @return number of msrs set successfully.
2594 */
2595static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2596 struct kvm_msr_entry *entries,
2597 int (*do_msr)(struct kvm_vcpu *vcpu,
2598 unsigned index, u64 *data))
2599{
f656ce01 2600 int i, idx;
313a3dc7 2601
f656ce01 2602 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2603 for (i = 0; i < msrs->nmsrs; ++i)
2604 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2605 break;
f656ce01 2606 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2607
313a3dc7
CO		 2608 return i;
2609}
2610
2611/*
2612 * Read or write a bunch of msrs. Parameters are user addresses.
2613 *
2614 * @return number of msrs set successfully.
2615 */
2616static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2617 int (*do_msr)(struct kvm_vcpu *vcpu,
2618 unsigned index, u64 *data),
2619 int writeback)
2620{
2621 struct kvm_msrs msrs;
2622 struct kvm_msr_entry *entries;
2623 int r, n;
2624 unsigned size;
2625
2626 r = -EFAULT;
2627 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2628 goto out;
2629
2630 r = -E2BIG;
2631 if (msrs.nmsrs >= MAX_IO_MSRS)
2632 goto out;
2633
313a3dc7 2634 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2635 entries = memdup_user(user_msrs->entries, size);
2636 if (IS_ERR(entries)) {
2637 r = PTR_ERR(entries);
313a3dc7 2638 goto out;
ff5c2c03 2639 }
313a3dc7
CO		 2640
2641 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2642 if (r < 0)
2643 goto out_free;
2644
2645 r = -EFAULT;
2646 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2647 goto out_free;
2648
2649 r = n;
2650
2651out_free:
7a73c028 2652 kfree(entries);
313a3dc7
CO		 2653out:
2654 return r;
2655}
2656
784aa3d7 2657int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2658{
2659 int r;
2660
2661 switch (ext) {
2662 case KVM_CAP_IRQCHIP:
2663 case KVM_CAP_HLT:
2664 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2665 case KVM_CAP_SET_TSS_ADDR:
07716717 2666 case KVM_CAP_EXT_CPUID:
9c15bb1d 2667 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2668 case KVM_CAP_CLOCKSOURCE:
7837699f 2669 case KVM_CAP_PIT:
a28e4f5a 2670 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2671 case KVM_CAP_MP_STATE:
ed848624 2672 case KVM_CAP_SYNC_MMU:
a355c85c 2673 case KVM_CAP_USER_NMI:
52d939a0 2674 case KVM_CAP_REINJECT_CONTROL:
4925663a 2675 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2676 case KVM_CAP_IOEVENTFD:
f848a5a8 2677 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2678 case KVM_CAP_PIT2:
e9f42757 2679 case KVM_CAP_PIT_STATE2:
b927a3ce 2680 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2681 case KVM_CAP_XEN_HVM:
3cfc3092 2682 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2683 case KVM_CAP_HYPERV:
10388a07 2684 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2685 case KVM_CAP_HYPERV_SPIN:
5c919412 2686 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2687 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2688 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2689 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2690 case KVM_CAP_DEBUGREGS:
d2be1651 2691 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2692 case KVM_CAP_XSAVE:
344d9588 2693 case KVM_CAP_ASYNC_PF:
92a1f12d 2694 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2695 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2696 case KVM_CAP_READONLY_MEM:
5f66b620 2697 case KVM_CAP_HYPERV_TIME:
100943c5 2698 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2699 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2700 case KVM_CAP_ENABLE_CAP_VM:
2701 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2702 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2703 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2704 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2705 r = 1;
2706 break;
e3fd9a93
PB		 2707 case KVM_CAP_ADJUST_CLOCK:
2708 r = KVM_CLOCK_TSC_STABLE;
2709 break;
668fffa3
MT		 2710 case KVM_CAP_X86_GUEST_MWAIT:
2711 r = kvm_mwait_in_guest();
2712 break;
6d396b55
PB		 2713 case KVM_CAP_X86_SMM:
2714 /* SMBASE is usually relocated above 1M on modern chipsets,
2715 * and SMM handlers might indeed rely on 4G segment limits,
2716 * so do not report SMM to be available if real mode is
2717 * emulated via vm86 mode. Still, do not go to great lengths
2718 * to avoid userspace's usage of the feature, because it is a
2719 * fringe case that is not enabled except via specific settings
2720 * of the module parameters.
2721 */
2722 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2723 break;
774ead3a
AK		 2724 case KVM_CAP_VAPIC:
2725 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2726 break;
f725230a 2727 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2728 r = KVM_SOFT_MAX_VCPUS;
2729 break;
2730 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2731 r = KVM_MAX_VCPUS;
2732 break;
a988b910 2733 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2734 r = KVM_USER_MEM_SLOTS;
a988b910 2735 break;
a68a6a72
MT		 2736 case KVM_CAP_PV_MMU: /* obsolete */
2737 r = 0;
2f333bcb 2738 break;
890ca9ae
HY		 2739 case KVM_CAP_MCE:
2740 r = KVM_MAX_MCE_BANKS;
2741 break;
2d5b5a66 2742 case KVM_CAP_XCRS:
d366bf7e 2743 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2744 break;
92a1f12d
JR		 2745 case KVM_CAP_TSC_CONTROL:
2746 r = kvm_has_tsc_control;
2747 break;
37131313
RK		 2748 case KVM_CAP_X2APIC_API:
2749 r = KVM_X2APIC_API_VALID_FLAGS;
2750 break;
018d00d2
ZX		 2751 default:
2752 r = 0;
2753 break;
2754 }
2755 return r;
2756
2757}
2758
043405e1
CO		 2759long kvm_arch_dev_ioctl(struct file *filp,
2760 unsigned int ioctl, unsigned long arg)
2761{
2762 void __user *argp = (void __user *)arg;
2763 long r;
2764
2765 switch (ioctl) {
2766 case KVM_GET_MSR_INDEX_LIST: {
2767 struct kvm_msr_list __user *user_msr_list = argp;
2768 struct kvm_msr_list msr_list;
2769 unsigned n;
2770
2771 r = -EFAULT;
2772 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2773 goto out;
2774 n = msr_list.nmsrs;
62ef68bb 2775 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2776 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2777 goto out;
2778 r = -E2BIG;
e125e7b6 2779 if (n < msr_list.nmsrs)
043405e1
CO		 2780 goto out;
2781 r = -EFAULT;
2782 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2783 num_msrs_to_save * sizeof(u32)))
2784 goto out;
e125e7b6 2785 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2786 &emulated_msrs,
62ef68bb 2787 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2788 goto out;
2789 r = 0;
2790 break;
2791 }
9c15bb1d
BP		 2792 case KVM_GET_SUPPORTED_CPUID:
2793 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2794 struct kvm_cpuid2 __user *cpuid_arg = argp;
2795 struct kvm_cpuid2 cpuid;
2796
2797 r = -EFAULT;
2798 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2799 goto out;
9c15bb1d
BP		 2800
2801 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2802 ioctl);
674eea0f
AK		 2803 if (r)
2804 goto out;
2805
2806 r = -EFAULT;
2807 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2808 goto out;
2809 r = 0;
2810 break;
2811 }
890ca9ae 2812 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2813 r = -EFAULT;
c45dcc71
AR		 2814 if (copy_to_user(argp, &kvm_mce_cap_supported,
2815 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2816 goto out;
2817 r = 0;
2818 break;
2819 }
043405e1
CO		 2820 default:
2821 r = -EINVAL;
2822 }
2823out:
2824 return r;
2825}
2826
f5f48ee1
SY		 2827static void wbinvd_ipi(void *garbage)
2828{
2829 wbinvd();
2830}
2831
2832static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2833{
e0f0bbc5 2834 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2835}
2836
313a3dc7
CO		 2837void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2838{
f5f48ee1
SY		 2839 /* Address WBINVD may be executed by guest */
2840 if (need_emulate_wbinvd(vcpu)) {
2841 if (kvm_x86_ops->has_wbinvd_exit())
2842 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2843 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2844 smp_call_function_single(vcpu->cpu,
2845 wbinvd_ipi, NULL, 1);
2846 }
2847
313a3dc7 2848 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2849
0dd6a6ed
ZA		 2850 /* Apply any externally detected TSC adjustments (due to suspend) */
2851 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2852 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2853 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2854 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2855 }
8f6055cb 2856
48434c20 2857 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2858 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2859 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2860 if (tsc_delta < 0)
2861 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2862
c285545f 2863 if (check_tsc_unstable()) {
07c1419a 2864 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2865 vcpu->arch.last_guest_tsc);
a545ab6a 2866 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2867 vcpu->arch.tsc_catchup = 1;
c285545f 2868 }
a749e247
PB		 2869
2870 if (kvm_lapic_hv_timer_in_use(vcpu))
2871 kvm_lapic_restart_hv_timer(vcpu);
2872
d98d07ca
MT		 2873 /*
2874 * On a host with synchronized TSC, there is no need to update
2875 * kvmclock on vcpu->cpu migration
2876 */
2877 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2878 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2879 if (vcpu->cpu != cpu)
1bd2009e 2880 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2881 vcpu->cpu = cpu;
6b7d7e76 2882 }
c9aaa895 2883
c9aaa895 2884 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2885}
2886
0b9f6c46
PX		 2887static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2888{
2889 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2890 return;
2891
2892 vcpu->arch.st.steal.preempted = 1;
2893
4e335d9e 2894 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2895 &vcpu->arch.st.steal.preempted,
2896 offsetof(struct kvm_steal_time, preempted),
2897 sizeof(vcpu->arch.st.steal.preempted));
2898}
2899
313a3dc7
CO		 2900void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2901{
cc0d907c 2902 int idx;
de63ad4c
LM		 2903
2904 if (vcpu->preempted)
2905 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2906
931f261b
AA		 2907 /*
2908 * Disable page faults because we're in atomic context here.
2909 * kvm_write_guest_offset_cached() would call might_fault()
2910 * that relies on pagefault_disable() to tell if there's a
2911 * bug. NOTE: the write to guest memory may not go through if
2912 * during postcopy live migration or if there's heavy guest
2913 * paging.
2914 */
2915 pagefault_disable();
cc0d907c
AA		 2916 /*
2917 * kvm_memslots() will be called by
2918 * kvm_write_guest_offset_cached() so take the srcu lock.
2919 */
2920 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2921 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2922 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2923 pagefault_enable();
02daab21 2924 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2925 kvm_put_guest_fpu(vcpu);
4ea1636b 2926 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2927}
2928
313a3dc7
CO		 2929static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2930 struct kvm_lapic_state *s)
2931{
76dfafd5 2932 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2933 kvm_x86_ops->sync_pir_to_irr(vcpu);
2934
a92e2543 2935 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2936}
2937
2938static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2939 struct kvm_lapic_state *s)
2940{
a92e2543
RK		 2941 int r;
2942
2943 r = kvm_apic_set_state(vcpu, s);
2944 if (r)
2945 return r;
cb142eb7 2946 update_cr8_intercept(vcpu);
313a3dc7
CO		 2947
2948 return 0;
2949}
2950
127a457a
MG		 2951static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2952{
2953 return (!lapic_in_kernel(vcpu) ||
2954 kvm_apic_accept_pic_intr(vcpu));
2955}
2956
782d422b
MG		 2957/*
2958 * if userspace requested an interrupt window, check that the
2959 * interrupt window is open.
2960 *
2961 * No need to exit to userspace if we already have an interrupt queued.
2962 */
2963static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2964{
2965 return kvm_arch_interrupt_allowed(vcpu) &&
2966 !kvm_cpu_has_interrupt(vcpu) &&
2967 !kvm_event_needs_reinjection(vcpu) &&
2968 kvm_cpu_accept_dm_intr(vcpu);
2969}
2970
f77bc6a4
ZX		 2971static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2972 struct kvm_interrupt *irq)
2973{
02cdb50f 2974 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2975 return -EINVAL;
1c1a9ce9
SR		 2976
2977 if (!irqchip_in_kernel(vcpu->kvm)) {
2978 kvm_queue_interrupt(vcpu, irq->irq, false);
2979 kvm_make_request(KVM_REQ_EVENT, vcpu);
2980 return 0;
2981 }
2982
2983 /*
2984 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2985 * fail for in-kernel 8259.
2986 */
2987 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2988 return -ENXIO;
f77bc6a4 2989
1c1a9ce9
SR		 2990 if (vcpu->arch.pending_external_vector != -1)
2991 return -EEXIST;
f77bc6a4 2992
1c1a9ce9 2993 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2994 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2995 return 0;
2996}
2997
c4abb7c9
JK		 2998static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2999{
c4abb7c9 3000 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3001
3002 return 0;
3003}
3004
f077825a
PB		 3005static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3006{
64d60670
PB		 3007 kvm_make_request(KVM_REQ_SMI, vcpu);
3008
f077825a
PB		 3009 return 0;
3010}
3011
b209749f
AK		 3012static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3013 struct kvm_tpr_access_ctl *tac)
3014{
3015 if (tac->flags)
3016 return -EINVAL;
3017 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3018 return 0;
3019}
3020
890ca9ae
HY		 3021static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3022 u64 mcg_cap)
3023{
3024 int r;
3025 unsigned bank_num = mcg_cap & 0xff, bank;
3026
3027 r = -EINVAL;
a9e38c3e 3028 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3029 goto out;
c45dcc71 3030 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3031 goto out;
3032 r = 0;
3033 vcpu->arch.mcg_cap = mcg_cap;
3034 /* Init IA32_MCG_CTL to all 1s */
3035 if (mcg_cap & MCG_CTL_P)
3036 vcpu->arch.mcg_ctl = ~(u64)0;
3037 /* Init IA32_MCi_CTL to all 1s */
3038 for (bank = 0; bank < bank_num; bank++)
3039 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3040
3041 if (kvm_x86_ops->setup_mce)
3042 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3043out:
3044 return r;
3045}
3046
3047static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3048 struct kvm_x86_mce *mce)
3049{
3050 u64 mcg_cap = vcpu->arch.mcg_cap;
3051 unsigned bank_num = mcg_cap & 0xff;
3052 u64 *banks = vcpu->arch.mce_banks;
3053
3054 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3055 return -EINVAL;
3056 /*
3057 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3058 * reporting is disabled
3059 */
3060 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3061 vcpu->arch.mcg_ctl != ~(u64)0)
3062 return 0;
3063 banks += 4 * mce->bank;
3064 /*
3065 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3066 * reporting is disabled for the bank
3067 */
3068 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3069 return 0;
3070 if (mce->status & MCI_STATUS_UC) {
3071 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3072 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3073 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3074 return 0;
3075 }
3076 if (banks[1] & MCI_STATUS_VAL)
3077 mce->status |= MCI_STATUS_OVER;
3078 banks[2] = mce->addr;
3079 banks[3] = mce->misc;
3080 vcpu->arch.mcg_status = mce->mcg_status;
3081 banks[1] = mce->status;
3082 kvm_queue_exception(vcpu, MC_VECTOR);
3083 } else if (!(banks[1] & MCI_STATUS_VAL)
3084 || !(banks[1] & MCI_STATUS_UC)) {
3085 if (banks[1] & MCI_STATUS_VAL)
3086 mce->status |= MCI_STATUS_OVER;
3087 banks[2] = mce->addr;
3088 banks[3] = mce->misc;
3089 banks[1] = mce->status;
3090 } else
3091 banks[1] |= MCI_STATUS_OVER;
3092 return 0;
3093}
3094
3cfc3092
JK		 3095static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3096 struct kvm_vcpu_events *events)
3097{
7460fb4a 3098 process_nmi(vcpu);
664f8e26
WL		 3099 /*
3100 * FIXME: pass injected and pending separately. This is only
3101 * needed for nested virtualization, whose state cannot be
3102 * migrated yet. For now we can combine them.
3103 */
03b82a30 3104 events->exception.injected =
664f8e26
WL		 3105 (vcpu->arch.exception.pending ||
3106 vcpu->arch.exception.injected) &&
03b82a30 3107 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3108 events->exception.nr = vcpu->arch.exception.nr;
3109 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3110 events->exception.pad = 0;
3cfc3092
JK		 3111 events->exception.error_code = vcpu->arch.exception.error_code;
3112
03b82a30
JK		 3113 events->interrupt.injected =
3114 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3115 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3116 events->interrupt.soft = 0;
37ccdcbe 3117 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3118
3119 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3120 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3121 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3122 events->nmi.pad = 0;
3cfc3092 3123
66450a21 3124 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3125
f077825a
PB		 3126 events->smi.smm = is_smm(vcpu);
3127 events->smi.pending = vcpu->arch.smi_pending;
3128 events->smi.smm_inside_nmi =
3129 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3130 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3131
dab4b911 3132 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3133 | KVM_VCPUEVENT_VALID_SHADOW
3134 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3135 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3136}
3137
6ef4e07e
XG		 3138static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3139
3cfc3092
JK		 3140static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3141 struct kvm_vcpu_events *events)
3142{
dab4b911 3143 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3144 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3145 | KVM_VCPUEVENT_VALID_SHADOW
3146 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3147 return -EINVAL;
3148
78e546c8 3149 if (events->exception.injected &&
28d06353
JM		 3150 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3151 is_guest_mode(vcpu)))
78e546c8
PB		 3152 return -EINVAL;
3153
28bf2888
DH		 3154 /* INITs are latched while in SMM */
3155 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3156 (events->smi.smm || events->smi.pending) &&
3157 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3158 return -EINVAL;
3159
7460fb4a 3160 process_nmi(vcpu);
664f8e26 3161 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3162 vcpu->arch.exception.pending = events->exception.injected;
3163 vcpu->arch.exception.nr = events->exception.nr;
3164 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3165 vcpu->arch.exception.error_code = events->exception.error_code;
3166
3167 vcpu->arch.interrupt.pending = events->interrupt.injected;
3168 vcpu->arch.interrupt.nr = events->interrupt.nr;
3169 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3170 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3171 kvm_x86_ops->set_interrupt_shadow(vcpu,
3172 events->interrupt.shadow);
3cfc3092
JK		 3173
3174 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3175 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3176 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3177 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3178
66450a21 3179 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3180 lapic_in_kernel(vcpu))
66450a21 3181 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3182
f077825a 3183 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3184 u32 hflags = vcpu->arch.hflags;
f077825a 3185 if (events->smi.smm)
6ef4e07e 3186 hflags |= HF_SMM_MASK;
f077825a 3187 else
6ef4e07e
XG		 3188 hflags &= ~HF_SMM_MASK;
3189 kvm_set_hflags(vcpu, hflags);
3190
f077825a 3191 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3192
3193 if (events->smi.smm) {
3194 if (events->smi.smm_inside_nmi)
3195 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3196 else
f4ef1910
WL		 3197 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3198 if (lapic_in_kernel(vcpu)) {
3199 if (events->smi.latched_init)
3200 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3201 else
3202 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3203 }
f077825a
PB		 3204 }
3205 }
3206
3842d135
AK		 3207 kvm_make_request(KVM_REQ_EVENT, vcpu);
3208
3cfc3092
JK		 3209 return 0;
3210}
3211
a1efbe77
JK		 3212static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3213 struct kvm_debugregs *dbgregs)
3214{
73aaf249
JK		 3215 unsigned long val;
3216
a1efbe77 3217 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3218 kvm_get_dr(vcpu, 6, &val);
73aaf249 3219 dbgregs->dr6 = val;
a1efbe77
JK		 3220 dbgregs->dr7 = vcpu->arch.dr7;
3221 dbgregs->flags = 0;
97e69aa6 3222 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3223}
3224
3225static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3226 struct kvm_debugregs *dbgregs)
3227{
3228 if (dbgregs->flags)
3229 return -EINVAL;
3230
d14bdb55
PB		 3231 if (dbgregs->dr6 & ~0xffffffffull)
3232 return -EINVAL;
3233 if (dbgregs->dr7 & ~0xffffffffull)
3234 return -EINVAL;
3235
a1efbe77 3236 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3237 kvm_update_dr0123(vcpu);
a1efbe77 3238 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3239 kvm_update_dr6(vcpu);
a1efbe77 3240 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3241 kvm_update_dr7(vcpu);
a1efbe77 3242
a1efbe77
JK		 3243 return 0;
3244}
3245
df1daba7
PB		 3246#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3247
3248static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3249{
c47ada30 3250 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3251 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3252 u64 valid;
3253
3254 /*
3255 * Copy legacy XSAVE area, to avoid complications with CPUID
3256 * leaves 0 and 1 in the loop below.
3257 */
3258 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3259
3260 /* Set XSTATE_BV */
00c87e9a 3261 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3262 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3263
3264 /*
3265 * Copy each region from the possibly compacted offset to the
3266 * non-compacted offset.
3267 */
d91cab78 3268 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3269 while (valid) {
3270 u64 feature = valid & -valid;
3271 int index = fls64(feature) - 1;
3272 void *src = get_xsave_addr(xsave, feature);
3273
3274 if (src) {
3275 u32 size, offset, ecx, edx;
3276 cpuid_count(XSTATE_CPUID, index,
3277 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3278 if (feature == XFEATURE_MASK_PKRU)
3279 memcpy(dest + offset, &vcpu->arch.pkru,
3280 sizeof(vcpu->arch.pkru));
3281 else
3282 memcpy(dest + offset, src, size);
3283
df1daba7
PB		 3284 }
3285
3286 valid -= feature;
3287 }
3288}
3289
3290static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3291{
c47ada30 3292 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3293 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3294 u64 valid;
3295
3296 /*
3297 * Copy legacy XSAVE area, to avoid complications with CPUID
3298 * leaves 0 and 1 in the loop below.
3299 */
3300 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3301
3302 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3303 xsave->header.xfeatures = xstate_bv;
782511b0 3304 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3305 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3306
3307 /*
3308 * Copy each region from the non-compacted offset to the
3309 * possibly compacted offset.
3310 */
d91cab78 3311 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3312 while (valid) {
3313 u64 feature = valid & -valid;
3314 int index = fls64(feature) - 1;
3315 void *dest = get_xsave_addr(xsave, feature);
3316
3317 if (dest) {
3318 u32 size, offset, ecx, edx;
3319 cpuid_count(XSTATE_CPUID, index,
3320 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3321 if (feature == XFEATURE_MASK_PKRU)
3322 memcpy(&vcpu->arch.pkru, src + offset,
3323 sizeof(vcpu->arch.pkru));
3324 else
3325 memcpy(dest, src + offset, size);
ee4100da 3326 }
df1daba7
PB		 3327
3328 valid -= feature;
3329 }
3330}
3331
2d5b5a66
SY		 3332static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3333 struct kvm_xsave *guest_xsave)
3334{
d366bf7e 3335 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3336 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3337 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3338 } else {
2d5b5a66 3339 memcpy(guest_xsave->region,
7366ed77 3340 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3341 sizeof(struct fxregs_state));
2d5b5a66 3342 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3343 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3344 }
3345}
3346
a575813b
WL		 3347#define XSAVE_MXCSR_OFFSET 24
3348
2d5b5a66
SY		 3349static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3350 struct kvm_xsave *guest_xsave)
3351{
3352 u64 xstate_bv =
3353 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3354 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3355
d366bf7e 3356 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3357 /*
3358 * Here we allow setting states that are not present in
3359 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3360 * with old userspace.
3361 */
a575813b
WL		 3362 if (xstate_bv & ~kvm_supported_xcr0() ||
3363 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3364 return -EINVAL;
df1daba7 3365 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3366 } else {
a575813b
WL		 3367 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3368 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3369 return -EINVAL;
7366ed77 3370 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3371 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3372 }
3373 return 0;
3374}
3375
3376static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3377 struct kvm_xcrs *guest_xcrs)
3378{
d366bf7e 3379 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3380 guest_xcrs->nr_xcrs = 0;
3381 return;
3382 }
3383
3384 guest_xcrs->nr_xcrs = 1;
3385 guest_xcrs->flags = 0;
3386 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3387 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3388}
3389
3390static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3391 struct kvm_xcrs *guest_xcrs)
3392{
3393 int i, r = 0;
3394
d366bf7e 3395 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3396 return -EINVAL;
3397
3398 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3399 return -EINVAL;
3400
3401 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3402 /* Only support XCR0 currently */
c67a04cb 3403 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3404 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3405 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3406 break;
3407 }
3408 if (r)
3409 r = -EINVAL;
3410 return r;
3411}
3412
1c0b28c2
EM		 3413/*
3414 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3415 * stopped by the hypervisor. This function will be called from the host only.
3416 * EINVAL is returned when the host attempts to set the flag for a guest that
3417 * does not support pv clocks.
3418 */
3419static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3420{
0b79459b 3421 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3422 return -EINVAL;
51d59c6b 3423 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3424 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3425 return 0;
3426}
3427
5c919412
AS		 3428static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3429 struct kvm_enable_cap *cap)
3430{
3431 if (cap->flags)
3432 return -EINVAL;
3433
3434 switch (cap->cap) {
efc479e6
RK		 3435 case KVM_CAP_HYPERV_SYNIC2:
3436 if (cap->args[0])
3437 return -EINVAL;
5c919412 3438 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3439 if (!irqchip_in_kernel(vcpu->kvm))
3440 return -EINVAL;
efc479e6
RK		 3441 return kvm_hv_activate_synic(vcpu, cap->cap ==
3442 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3443 default:
3444 return -EINVAL;
3445 }
3446}
3447
313a3dc7
CO		 3448long kvm_arch_vcpu_ioctl(struct file *filp,
3449 unsigned int ioctl, unsigned long arg)
3450{
3451 struct kvm_vcpu *vcpu = filp->private_data;
3452 void __user *argp = (void __user *)arg;
3453 int r;
d1ac91d8
AK		 3454 union {
3455 struct kvm_lapic_state *lapic;
3456 struct kvm_xsave *xsave;
3457 struct kvm_xcrs *xcrs;
3458 void *buffer;
3459 } u;
3460
3461 u.buffer = NULL;
313a3dc7
CO		 3462 switch (ioctl) {
3463 case KVM_GET_LAPIC: {
2204ae3c 3464 r = -EINVAL;
bce87cce 3465 if (!lapic_in_kernel(vcpu))
2204ae3c 3466 goto out;
d1ac91d8 3467 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3468
b772ff36 3469 r = -ENOMEM;
d1ac91d8 3470 if (!u.lapic)
b772ff36 3471 goto out;
d1ac91d8 3472 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3473 if (r)
3474 goto out;
3475 r = -EFAULT;
d1ac91d8 3476 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3477 goto out;
3478 r = 0;
3479 break;
3480 }
3481 case KVM_SET_LAPIC: {
2204ae3c 3482 r = -EINVAL;
bce87cce 3483 if (!lapic_in_kernel(vcpu))
2204ae3c 3484 goto out;
ff5c2c03 3485 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3486 if (IS_ERR(u.lapic))
3487 return PTR_ERR(u.lapic);
ff5c2c03 3488
d1ac91d8 3489 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3490 break;
3491 }
f77bc6a4
ZX		 3492 case KVM_INTERRUPT: {
3493 struct kvm_interrupt irq;
3494
3495 r = -EFAULT;
3496 if (copy_from_user(&irq, argp, sizeof irq))
3497 goto out;
3498 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3499 break;
3500 }
c4abb7c9
JK		 3501 case KVM_NMI: {
3502 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3503 break;
3504 }
f077825a
PB		 3505 case KVM_SMI: {
3506 r = kvm_vcpu_ioctl_smi(vcpu);
3507 break;
3508 }
313a3dc7
CO		 3509 case KVM_SET_CPUID: {
3510 struct kvm_cpuid __user *cpuid_arg = argp;
3511 struct kvm_cpuid cpuid;
3512
3513 r = -EFAULT;
3514 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3515 goto out;
3516 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3517 break;
3518 }
07716717
DK		 3519 case KVM_SET_CPUID2: {
3520 struct kvm_cpuid2 __user *cpuid_arg = argp;
3521 struct kvm_cpuid2 cpuid;
3522
3523 r = -EFAULT;
3524 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3525 goto out;
3526 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3527 cpuid_arg->entries);
07716717
DK		 3528 break;
3529 }
3530 case KVM_GET_CPUID2: {
3531 struct kvm_cpuid2 __user *cpuid_arg = argp;
3532 struct kvm_cpuid2 cpuid;
3533
3534 r = -EFAULT;
3535 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3536 goto out;
3537 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3538 cpuid_arg->entries);
07716717
DK		 3539 if (r)
3540 goto out;
3541 r = -EFAULT;
3542 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3543 goto out;
3544 r = 0;
3545 break;
3546 }
313a3dc7 3547 case KVM_GET_MSRS:
609e36d3 3548 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3549 break;
3550 case KVM_SET_MSRS:
3551 r = msr_io(vcpu, argp, do_set_msr, 0);
3552 break;
b209749f
AK		 3553 case KVM_TPR_ACCESS_REPORTING: {
3554 struct kvm_tpr_access_ctl tac;
3555
3556 r = -EFAULT;
3557 if (copy_from_user(&tac, argp, sizeof tac))
3558 goto out;
3559 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3560 if (r)
3561 goto out;
3562 r = -EFAULT;
3563 if (copy_to_user(argp, &tac, sizeof tac))
3564 goto out;
3565 r = 0;
3566 break;
3567 };
b93463aa
AK		 3568 case KVM_SET_VAPIC_ADDR: {
3569 struct kvm_vapic_addr va;
7301d6ab 3570 int idx;
b93463aa
AK		 3571
3572 r = -EINVAL;
35754c98 3573 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3574 goto out;
3575 r = -EFAULT;
3576 if (copy_from_user(&va, argp, sizeof va))
3577 goto out;
7301d6ab 3578 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3579 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3580 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3581 break;
3582 }
890ca9ae
HY		 3583 case KVM_X86_SETUP_MCE: {
3584 u64 mcg_cap;
3585
3586 r = -EFAULT;
3587 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3588 goto out;
3589 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3590 break;
3591 }
3592 case KVM_X86_SET_MCE: {
3593 struct kvm_x86_mce mce;
3594
3595 r = -EFAULT;
3596 if (copy_from_user(&mce, argp, sizeof mce))
3597 goto out;
3598 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3599 break;
3600 }
3cfc3092
JK		 3601 case KVM_GET_VCPU_EVENTS: {
3602 struct kvm_vcpu_events events;
3603
3604 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3605
3606 r = -EFAULT;
3607 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3608 break;
3609 r = 0;
3610 break;
3611 }
3612 case KVM_SET_VCPU_EVENTS: {
3613 struct kvm_vcpu_events events;
3614
3615 r = -EFAULT;
3616 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3617 break;
3618
3619 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3620 break;
3621 }
a1efbe77
JK		 3622 case KVM_GET_DEBUGREGS: {
3623 struct kvm_debugregs dbgregs;
3624
3625 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3626
3627 r = -EFAULT;
3628 if (copy_to_user(argp, &dbgregs,
3629 sizeof(struct kvm_debugregs)))
3630 break;
3631 r = 0;
3632 break;
3633 }
3634 case KVM_SET_DEBUGREGS: {
3635 struct kvm_debugregs dbgregs;
3636
3637 r = -EFAULT;
3638 if (copy_from_user(&dbgregs, argp,
3639 sizeof(struct kvm_debugregs)))
3640 break;
3641
3642 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3643 break;
3644 }
2d5b5a66 3645 case KVM_GET_XSAVE: {
d1ac91d8 3646 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3647 r = -ENOMEM;
d1ac91d8 3648 if (!u.xsave)
2d5b5a66
SY		 3649 break;
3650
d1ac91d8 3651 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3652
3653 r = -EFAULT;
d1ac91d8 3654 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3655 break;
3656 r = 0;
3657 break;
3658 }
3659 case KVM_SET_XSAVE: {
ff5c2c03 3660 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3661 if (IS_ERR(u.xsave))
3662 return PTR_ERR(u.xsave);
2d5b5a66 3663
d1ac91d8 3664 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3665 break;
3666 }
3667 case KVM_GET_XCRS: {
d1ac91d8 3668 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3669 r = -ENOMEM;
d1ac91d8 3670 if (!u.xcrs)
2d5b5a66
SY		 3671 break;
3672
d1ac91d8 3673 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3674
3675 r = -EFAULT;
d1ac91d8 3676 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3677 sizeof(struct kvm_xcrs)))
3678 break;
3679 r = 0;
3680 break;
3681 }
3682 case KVM_SET_XCRS: {
ff5c2c03 3683 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3684 if (IS_ERR(u.xcrs))
3685 return PTR_ERR(u.xcrs);
2d5b5a66 3686
d1ac91d8 3687 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3688 break;
3689 }
92a1f12d
JR		 3690 case KVM_SET_TSC_KHZ: {
3691 u32 user_tsc_khz;
3692
3693 r = -EINVAL;
92a1f12d
JR		 3694 user_tsc_khz = (u32)arg;
3695
3696 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3697 goto out;
3698
cc578287
ZA		 3699 if (user_tsc_khz == 0)
3700 user_tsc_khz = tsc_khz;
3701
381d585c
HZ		 3702 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3703 r = 0;
92a1f12d 3704
92a1f12d
JR		 3705 goto out;
3706 }
3707 case KVM_GET_TSC_KHZ: {
cc578287 3708 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3709 goto out;
3710 }
1c0b28c2
EM		 3711 case KVM_KVMCLOCK_CTRL: {
3712 r = kvm_set_guest_paused(vcpu);
3713 goto out;
3714 }
5c919412
AS		 3715 case KVM_ENABLE_CAP: {
3716 struct kvm_enable_cap cap;
3717
3718 r = -EFAULT;
3719 if (copy_from_user(&cap, argp, sizeof(cap)))
3720 goto out;
3721 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3722 break;
3723 }
313a3dc7
CO		 3724 default:
3725 r = -EINVAL;
3726 }
3727out:
d1ac91d8 3728 kfree(u.buffer);
313a3dc7
CO		 3729 return r;
3730}
3731
5b1c1493
CO		 3732int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3733{
3734 return VM_FAULT_SIGBUS;
3735}
3736
1fe779f8
CO		 3737static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3738{
3739 int ret;
3740
3741 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3742 return -EINVAL;
1fe779f8
CO		 3743 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3744 return ret;
3745}
3746
b927a3ce
SY		 3747static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3748 u64 ident_addr)
3749{
3750 kvm->arch.ept_identity_map_addr = ident_addr;
3751 return 0;
3752}
3753
1fe779f8
CO		 3754static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3755 u32 kvm_nr_mmu_pages)
3756{
3757 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3758 return -EINVAL;
3759
79fac95e 3760 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3761
3762 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3763 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3764
79fac95e 3765 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3766 return 0;
3767}
3768
3769static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3770{
39de71ec 3771 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3772}
3773
1fe779f8
CO		 3774static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3775{
90bca052 3776 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3777 int r;
3778
3779 r = 0;
3780 switch (chip->chip_id) {
3781 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3782 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3783 sizeof(struct kvm_pic_state));
3784 break;
3785 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3786 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3787 sizeof(struct kvm_pic_state));
3788 break;
3789 case KVM_IRQCHIP_IOAPIC:
33392b49 3790 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3791 break;
3792 default:
3793 r = -EINVAL;
3794 break;
3795 }
3796 return r;
3797}
3798
3799static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3800{
90bca052 3801 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3802 int r;
3803
3804 r = 0;
3805 switch (chip->chip_id) {
3806 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3807 spin_lock(&pic->lock);
3808 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3809 sizeof(struct kvm_pic_state));
90bca052 3810 spin_unlock(&pic->lock);
1fe779f8
CO		 3811 break;
3812 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3813 spin_lock(&pic->lock);
3814 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3815 sizeof(struct kvm_pic_state));
90bca052 3816 spin_unlock(&pic->lock);
1fe779f8
CO		 3817 break;
3818 case KVM_IRQCHIP_IOAPIC:
33392b49 3819 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3820 break;
3821 default:
3822 r = -EINVAL;
3823 break;
3824 }
90bca052 3825 kvm_pic_update_irq(pic);
1fe779f8
CO		 3826 return r;
3827}
3828
e0f63cb9
SY		 3829static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3830{
34f3941c
RK		 3831 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3832
3833 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3834
3835 mutex_lock(&kps->lock);
3836 memcpy(ps, &kps->channels, sizeof(*ps));
3837 mutex_unlock(&kps->lock);
2da29bcc 3838 return 0;
e0f63cb9
SY		 3839}
3840
3841static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3842{
0185604c 3843 int i;
09edea72
RK		 3844 struct kvm_pit *pit = kvm->arch.vpit;
3845
3846 mutex_lock(&pit->pit_state.lock);
34f3941c 3847 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3848 for (i = 0; i < 3; i++)
09edea72
RK		 3849 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3850 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3851 return 0;
e9f42757
BK		 3852}
3853
3854static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3855{
e9f42757
BK		 3856 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3857 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3858 sizeof(ps->channels));
3859 ps->flags = kvm->arch.vpit->pit_state.flags;
3860 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3861 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3862 return 0;
e9f42757
BK		 3863}
3864
3865static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3866{
2da29bcc 3867 int start = 0;
0185604c 3868 int i;
e9f42757 3869 u32 prev_legacy, cur_legacy;
09edea72
RK		 3870 struct kvm_pit *pit = kvm->arch.vpit;
3871
3872 mutex_lock(&pit->pit_state.lock);
3873 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3874 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3875 if (!prev_legacy && cur_legacy)
3876 start = 1;
09edea72
RK		 3877 memcpy(&pit->pit_state.channels, &ps->channels,
3878 sizeof(pit->pit_state.channels));
3879 pit->pit_state.flags = ps->flags;
0185604c 3880 for (i = 0; i < 3; i++)
09edea72 3881 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3882 start && i == 0);
09edea72 3883 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3884 return 0;
e0f63cb9
SY		 3885}
3886
52d939a0
MT		 3887static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3888 struct kvm_reinject_control *control)
3889{
71474e2f
RK		 3890 struct kvm_pit *pit = kvm->arch.vpit;
3891
3892 if (!pit)
52d939a0 3893 return -ENXIO;
b39c90b6 3894
71474e2f
RK		 3895 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3896 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3897 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3898 */
3899 mutex_lock(&pit->pit_state.lock);
3900 kvm_pit_set_reinject(pit, control->pit_reinject);
3901 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3902
52d939a0
MT		 3903 return 0;
3904}
3905
95d4c16c 3906/**
60c34612
TY		 3907 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3908 * @kvm: kvm instance
3909 * @log: slot id and address to which we copy the log
95d4c16c 3910 *
e108ff2f
PB		 3911 * Steps 1-4 below provide general overview of dirty page logging. See
3912 * kvm_get_dirty_log_protect() function description for additional details.
3913 *
3914 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3915 * always flush the TLB (step 4) even if previous step failed and the dirty
3916 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3917 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3918 * writes will be marked dirty for next log read.
95d4c16c 3919 *
60c34612
TY		 3920 * 1. Take a snapshot of the bit and clear it if needed.
3921 * 2. Write protect the corresponding page.
e108ff2f
PB		 3922 * 3. Copy the snapshot to the userspace.
3923 * 4. Flush TLB's if needed.
5bb064dc 3924 */
60c34612 3925int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3926{
60c34612 3927 bool is_dirty = false;
e108ff2f 3928 int r;
5bb064dc 3929
79fac95e 3930 mutex_lock(&kvm->slots_lock);
5bb064dc 3931
88178fd4
KH		 3932 /*
3933 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3934 */
3935 if (kvm_x86_ops->flush_log_dirty)
3936 kvm_x86_ops->flush_log_dirty(kvm);
3937
e108ff2f 3938 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3939
3940 /*
3941 * All the TLBs can be flushed out of mmu lock, see the comments in
3942 * kvm_mmu_slot_remove_write_access().
3943 */
e108ff2f 3944 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3945 if (is_dirty)
3946 kvm_flush_remote_tlbs(kvm);
3947
79fac95e 3948 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3949 return r;
3950}
3951
aa2fbe6d
YZ		 3952int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3953 bool line_status)
23d43cf9
CD		 3954{
3955 if (!irqchip_in_kernel(kvm))
3956 return -ENXIO;
3957
3958 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3959 irq_event->irq, irq_event->level,
3960 line_status);
23d43cf9
CD		 3961 return 0;
3962}
3963
90de4a18
NA		 3964static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3965 struct kvm_enable_cap *cap)
3966{
3967 int r;
3968
3969 if (cap->flags)
3970 return -EINVAL;
3971
3972 switch (cap->cap) {
3973 case KVM_CAP_DISABLE_QUIRKS:
3974 kvm->arch.disabled_quirks = cap->args[0];
3975 r = 0;
3976 break;
49df6397
SR		 3977 case KVM_CAP_SPLIT_IRQCHIP: {
3978 mutex_lock(&kvm->lock);
b053b2ae
SR		 3979 r = -EINVAL;
3980 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3981 goto split_irqchip_unlock;
49df6397
SR		 3982 r = -EEXIST;
3983 if (irqchip_in_kernel(kvm))
3984 goto split_irqchip_unlock;
557abc40 3985 if (kvm->created_vcpus)
49df6397
SR		 3986 goto split_irqchip_unlock;
3987 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3988 if (r)
49df6397
SR		 3989 goto split_irqchip_unlock;
3990 /* Pairs with irqchip_in_kernel. */
3991 smp_wmb();
49776faf 3992 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3993 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3994 r = 0;
3995split_irqchip_unlock:
3996 mutex_unlock(&kvm->lock);
3997 break;
3998 }
37131313
RK		 3999 case KVM_CAP_X2APIC_API:
4000 r = -EINVAL;
4001 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4002 break;
4003
4004 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4005 kvm->arch.x2apic_format = true;
c519265f
RK		 4006 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4007 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4008
4009 r = 0;
4010 break;
90de4a18
NA		 4011 default:
4012 r = -EINVAL;
4013 break;
4014 }
4015 return r;
4016}
4017
1fe779f8
CO		 4018long kvm_arch_vm_ioctl(struct file *filp,
4019 unsigned int ioctl, unsigned long arg)
4020{
4021 struct kvm *kvm = filp->private_data;
4022 void __user *argp = (void __user *)arg;
367e1319 4023 int r = -ENOTTY;
f0d66275
DH		 4024 /*
4025 * This union makes it completely explicit to gcc-3.x
4026 * that these two variables' stack usage should be
4027 * combined, not added together.
4028 */
4029 union {
4030 struct kvm_pit_state ps;
e9f42757 4031 struct kvm_pit_state2 ps2;
c5ff41ce 4032 struct kvm_pit_config pit_config;
f0d66275 4033 } u;
1fe779f8
CO		 4034
4035 switch (ioctl) {
4036 case KVM_SET_TSS_ADDR:
4037 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4038 break;
b927a3ce
SY		 4039 case KVM_SET_IDENTITY_MAP_ADDR: {
4040 u64 ident_addr;
4041
1af1ac91
DH		 4042 mutex_lock(&kvm->lock);
4043 r = -EINVAL;
4044 if (kvm->created_vcpus)
4045 goto set_identity_unlock;
b927a3ce
SY		 4046 r = -EFAULT;
4047 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4048 goto set_identity_unlock;
b927a3ce 4049 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4050set_identity_unlock:
4051 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4052 break;
4053 }
1fe779f8
CO		 4054 case KVM_SET_NR_MMU_PAGES:
4055 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4056 break;
4057 case KVM_GET_NR_MMU_PAGES:
4058 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4059 break;
3ddea128 4060 case KVM_CREATE_IRQCHIP: {
3ddea128 4061 mutex_lock(&kvm->lock);
09941366 4062
3ddea128 4063 r = -EEXIST;
35e6eaa3 4064 if (irqchip_in_kernel(kvm))
3ddea128 4065 goto create_irqchip_unlock;
09941366 4066
3e515705 4067 r = -EINVAL;
557abc40 4068 if (kvm->created_vcpus)
3e515705 4069 goto create_irqchip_unlock;
09941366
RK		 4070
4071 r = kvm_pic_init(kvm);
4072 if (r)
3ddea128 4073 goto create_irqchip_unlock;
09941366
RK		 4074
4075 r = kvm_ioapic_init(kvm);
4076 if (r) {
09941366 4077 kvm_pic_destroy(kvm);
3ddea128 4078 goto create_irqchip_unlock;
09941366
RK		 4079 }
4080
399ec807
AK		 4081 r = kvm_setup_default_irq_routing(kvm);
4082 if (r) {
72bb2fcd 4083 kvm_ioapic_destroy(kvm);
09941366 4084 kvm_pic_destroy(kvm);
71ba994c 4085 goto create_irqchip_unlock;
399ec807 4086 }
49776faf 4087 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4088 smp_wmb();
49776faf 4089 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4090 create_irqchip_unlock:
4091 mutex_unlock(&kvm->lock);
1fe779f8 4092 break;
3ddea128 4093 }
7837699f 4094 case KVM_CREATE_PIT:
c5ff41ce
JK		 4095 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4096 goto create_pit;
4097 case KVM_CREATE_PIT2:
4098 r = -EFAULT;
4099 if (copy_from_user(&u.pit_config, argp,
4100 sizeof(struct kvm_pit_config)))
4101 goto out;
4102 create_pit:
250715a6 4103 mutex_lock(&kvm->lock);
269e05e4
AK		 4104 r = -EEXIST;
4105 if (kvm->arch.vpit)
4106 goto create_pit_unlock;
7837699f 4107 r = -ENOMEM;
c5ff41ce 4108 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4109 if (kvm->arch.vpit)
4110 r = 0;
269e05e4 4111 create_pit_unlock:
250715a6 4112 mutex_unlock(&kvm->lock);
7837699f 4113 break;
1fe779f8
CO		 4114 case KVM_GET_IRQCHIP: {
4115 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4116 struct kvm_irqchip *chip;
1fe779f8 4117
ff5c2c03
SL		 4118 chip = memdup_user(argp, sizeof(*chip));
4119 if (IS_ERR(chip)) {
4120 r = PTR_ERR(chip);
1fe779f8 4121 goto out;
ff5c2c03
SL		 4122 }
4123
1fe779f8 4124 r = -ENXIO;
826da321 4125 if (!irqchip_kernel(kvm))
f0d66275
DH		 4126 goto get_irqchip_out;
4127 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4128 if (r)
f0d66275 4129 goto get_irqchip_out;
1fe779f8 4130 r = -EFAULT;
f0d66275
DH		 4131 if (copy_to_user(argp, chip, sizeof *chip))
4132 goto get_irqchip_out;
1fe779f8 4133 r = 0;
f0d66275
DH		 4134 get_irqchip_out:
4135 kfree(chip);
1fe779f8
CO		 4136 break;
4137 }
4138 case KVM_SET_IRQCHIP: {
4139 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4140 struct kvm_irqchip *chip;
1fe779f8 4141
ff5c2c03
SL		 4142 chip = memdup_user(argp, sizeof(*chip));
4143 if (IS_ERR(chip)) {
4144 r = PTR_ERR(chip);
1fe779f8 4145 goto out;
ff5c2c03
SL		 4146 }
4147
1fe779f8 4148 r = -ENXIO;
826da321 4149 if (!irqchip_kernel(kvm))
f0d66275
DH		 4150 goto set_irqchip_out;
4151 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4152 if (r)
f0d66275 4153 goto set_irqchip_out;
1fe779f8 4154 r = 0;
f0d66275
DH		 4155 set_irqchip_out:
4156 kfree(chip);
1fe779f8
CO		 4157 break;
4158 }
e0f63cb9 4159 case KVM_GET_PIT: {
e0f63cb9 4160 r = -EFAULT;
f0d66275 4161 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4162 goto out;
4163 r = -ENXIO;
4164 if (!kvm->arch.vpit)
4165 goto out;
f0d66275 4166 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4167 if (r)
4168 goto out;
4169 r = -EFAULT;
f0d66275 4170 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4171 goto out;
4172 r = 0;
4173 break;
4174 }
4175 case KVM_SET_PIT: {
e0f63cb9 4176 r = -EFAULT;
f0d66275 4177 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4178 goto out;
4179 r = -ENXIO;
4180 if (!kvm->arch.vpit)
4181 goto out;
f0d66275 4182 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4183 break;
4184 }
e9f42757
BK		 4185 case KVM_GET_PIT2: {
4186 r = -ENXIO;
4187 if (!kvm->arch.vpit)
4188 goto out;
4189 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4190 if (r)
4191 goto out;
4192 r = -EFAULT;
4193 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4194 goto out;
4195 r = 0;
4196 break;
4197 }
4198 case KVM_SET_PIT2: {
4199 r = -EFAULT;
4200 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4201 goto out;
4202 r = -ENXIO;
4203 if (!kvm->arch.vpit)
4204 goto out;
4205 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4206 break;
4207 }
52d939a0
MT		 4208 case KVM_REINJECT_CONTROL: {
4209 struct kvm_reinject_control control;
4210 r = -EFAULT;
4211 if (copy_from_user(&control, argp, sizeof(control)))
4212 goto out;
4213 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4214 break;
4215 }
d71ba788
PB		 4216 case KVM_SET_BOOT_CPU_ID:
4217 r = 0;
4218 mutex_lock(&kvm->lock);
557abc40 4219 if (kvm->created_vcpus)
d71ba788
PB		 4220 r = -EBUSY;
4221 else
4222 kvm->arch.bsp_vcpu_id = arg;
4223 mutex_unlock(&kvm->lock);
4224 break;
ffde22ac
ES		 4225 case KVM_XEN_HVM_CONFIG: {
4226 r = -EFAULT;
4227 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4228 sizeof(struct kvm_xen_hvm_config)))
4229 goto out;
4230 r = -EINVAL;
4231 if (kvm->arch.xen_hvm_config.flags)
4232 goto out;
4233 r = 0;
4234 break;
4235 }
afbcf7ab 4236 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4237 struct kvm_clock_data user_ns;
4238 u64 now_ns;
afbcf7ab
GC		 4239
4240 r = -EFAULT;
4241 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4242 goto out;
4243
4244 r = -EINVAL;
4245 if (user_ns.flags)
4246 goto out;
4247
4248 r = 0;
0bc48bea
RK		 4249 /*
4250 * TODO: userspace has to take care of races with VCPU_RUN, so
4251 * kvm_gen_update_masterclock() can be cut down to locked
4252 * pvclock_update_vm_gtod_copy().
4253 */
4254 kvm_gen_update_masterclock(kvm);
e891a32e 4255 now_ns = get_kvmclock_ns(kvm);
108b249c 4256 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4257 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4258 break;
4259 }
4260 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4261 struct kvm_clock_data user_ns;
4262 u64 now_ns;
4263
e891a32e 4264 now_ns = get_kvmclock_ns(kvm);
108b249c 4265 user_ns.clock = now_ns;
e3fd9a93 4266 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4267 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4268
4269 r = -EFAULT;
4270 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4271 goto out;
4272 r = 0;
4273 break;
4274 }
90de4a18
NA		 4275 case KVM_ENABLE_CAP: {
4276 struct kvm_enable_cap cap;
afbcf7ab 4277
90de4a18
NA		 4278 r = -EFAULT;
4279 if (copy_from_user(&cap, argp, sizeof(cap)))
4280 goto out;
4281 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4282 break;
4283 }
5acc5c06
BS		 4284 case KVM_MEMORY_ENCRYPT_OP: {
4285 r = -ENOTTY;
4286 if (kvm_x86_ops->mem_enc_op)
4287 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4288 break;
4289 }
1fe779f8 4290 default:
ad6260da 4291 r = -ENOTTY;
1fe779f8
CO		 4292 }
4293out:
4294 return r;
4295}
4296
a16b043c 4297static void kvm_init_msr_list(void)
043405e1
CO		 4298{
4299 u32 dummy[2];
4300 unsigned i, j;
4301
62ef68bb 4302 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4303 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4304 continue;
93c4adc7
PB		 4305
4306 /*
4307 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4308 * to the guests in some cases.
93c4adc7
PB		 4309 */
4310 switch (msrs_to_save[i]) {
4311 case MSR_IA32_BNDCFGS:
4312 if (!kvm_x86_ops->mpx_supported())
4313 continue;
4314 break;
9dbe6cf9
PB		 4315 case MSR_TSC_AUX:
4316 if (!kvm_x86_ops->rdtscp_supported())
4317 continue;
4318 break;
93c4adc7
PB		 4319 default:
4320 break;
4321 }
4322
043405e1
CO		 4323 if (j < i)
4324 msrs_to_save[j] = msrs_to_save[i];
4325 j++;
4326 }
4327 num_msrs_to_save = j;
62ef68bb
PB		 4328
4329 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4330 switch (emulated_msrs[i]) {
6d396b55
PB		 4331 case MSR_IA32_SMBASE:
4332 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4333 continue;
4334 break;
62ef68bb
PB		 4335 default:
4336 break;
4337 }
4338
4339 if (j < i)
4340 emulated_msrs[j] = emulated_msrs[i];
4341 j++;
4342 }
4343 num_emulated_msrs = j;
043405e1
CO		 4344}
4345
bda9020e
MT		 4346static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4347 const void *v)
bbd9b64e 4348{
70252a10
AK		 4349 int handled = 0;
4350 int n;
4351
4352 do {
4353 n = min(len, 8);
bce87cce 4354 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4355 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4356 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4357 break;
4358 handled += n;
4359 addr += n;
4360 len -= n;
4361 v += n;
4362 } while (len);
bbd9b64e 4363
70252a10 4364 return handled;
bbd9b64e
CO		 4365}
4366
bda9020e 4367static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4368{
70252a10
AK		 4369 int handled = 0;
4370 int n;
4371
4372 do {
4373 n = min(len, 8);
bce87cce 4374 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4375 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4376 addr, n, v))
4377 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4378 break;
4379 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4380 handled += n;
4381 addr += n;
4382 len -= n;
4383 v += n;
4384 } while (len);
bbd9b64e 4385
70252a10 4386 return handled;
bbd9b64e
CO		 4387}
4388
2dafc6c2
GN		 4389static void kvm_set_segment(struct kvm_vcpu *vcpu,
4390 struct kvm_segment *var, int seg)
4391{
4392 kvm_x86_ops->set_segment(vcpu, var, seg);
4393}
4394
4395void kvm_get_segment(struct kvm_vcpu *vcpu,
4396 struct kvm_segment *var, int seg)
4397{
4398 kvm_x86_ops->get_segment(vcpu, var, seg);
4399}
4400
54987b7a
PB		 4401gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4402 struct x86_exception *exception)
02f59dc9
JR		 4403{
4404 gpa_t t_gpa;
02f59dc9
JR		 4405
4406 BUG_ON(!mmu_is_nested(vcpu));
4407
4408 /* NPT walks are always user-walks */
4409 access |= PFERR_USER_MASK;
54987b7a 4410 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4411
4412 return t_gpa;
4413}
4414
ab9ae313
AK		 4415gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4416 struct x86_exception *exception)
1871c602
GN		 4417{
4418 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4419 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4420}
4421
ab9ae313
AK		 4422 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4423 struct x86_exception *exception)
1871c602
GN		 4424{
4425 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4426 access |= PFERR_FETCH_MASK;
ab9ae313 4427 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4428}
4429
ab9ae313
AK		 4430gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4431 struct x86_exception *exception)
1871c602
GN		 4432{
4433 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4434 access |= PFERR_WRITE_MASK;
ab9ae313 4435 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4436}
4437
4438/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4439gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4440 struct x86_exception *exception)
1871c602 4441{
ab9ae313 4442 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4443}
4444
4445static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4446 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4447 struct x86_exception *exception)
bbd9b64e
CO		 4448{
4449 void *data = val;
10589a46 4450 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4451
4452 while (bytes) {
14dfe855 4453 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4454 exception);
bbd9b64e 4455 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4456 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4457 int ret;
4458
bcc55cba 4459 if (gpa == UNMAPPED_GVA)
ab9ae313 4460 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4461 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4462 offset, toread);
10589a46 4463 if (ret < 0) {
c3cd7ffa 4464 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4465 goto out;
4466 }
bbd9b64e 4467
77c2002e
IE		 4468 bytes -= toread;
4469 data += toread;
4470 addr += toread;
bbd9b64e 4471 }
10589a46 4472out:
10589a46 4473 return r;
bbd9b64e 4474}
77c2002e 4475
1871c602 4476/* used for instruction fetching */
0f65dd70
AK		 4477static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4478 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4479 struct x86_exception *exception)
1871c602 4480{
0f65dd70 4481 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4482 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4483 unsigned offset;
4484 int ret;
0f65dd70 4485
44583cba
PB		 4486 /* Inline kvm_read_guest_virt_helper for speed. */
4487 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4488 exception);
4489 if (unlikely(gpa == UNMAPPED_GVA))
4490 return X86EMUL_PROPAGATE_FAULT;
4491
4492 offset = addr & (PAGE_SIZE-1);
4493 if (WARN_ON(offset + bytes > PAGE_SIZE))
4494 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4495 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4496 offset, bytes);
44583cba
PB		 4497 if (unlikely(ret < 0))
4498 return X86EMUL_IO_NEEDED;
4499
4500 return X86EMUL_CONTINUE;
1871c602
GN		 4501}
4502
064aea77 4503int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4504 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4505 struct x86_exception *exception)
1871c602 4506{
0f65dd70 4507 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4508 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4509
1871c602 4510 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4511 exception);
1871c602 4512}
064aea77 4513EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4514
0f65dd70
AK		 4515static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4516 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4517 struct x86_exception *exception)
1871c602 4518{
0f65dd70 4519 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4520 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4521}
4522
7a036a6f
RK		 4523static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4524 unsigned long addr, void *val, unsigned int bytes)
4525{
4526 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4527 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4528
4529 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4530}
4531
6a4d7550 4532int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4533 gva_t addr, void *val,
2dafc6c2 4534 unsigned int bytes,
bcc55cba 4535 struct x86_exception *exception)
77c2002e 4536{
0f65dd70 4537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4538 void *data = val;
4539 int r = X86EMUL_CONTINUE;
4540
4541 while (bytes) {
14dfe855
JR		 4542 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4543 PFERR_WRITE_MASK,
ab9ae313 4544 exception);
77c2002e
IE		 4545 unsigned offset = addr & (PAGE_SIZE-1);
4546 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4547 int ret;
4548
bcc55cba 4549 if (gpa == UNMAPPED_GVA)
ab9ae313 4550 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4551 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4552 if (ret < 0) {
c3cd7ffa 4553 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4554 goto out;
4555 }
4556
4557 bytes -= towrite;
4558 data += towrite;
4559 addr += towrite;
4560 }
4561out:
4562 return r;
4563}
6a4d7550 4564EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4565
0f89b207
TL		 4566static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4567 gpa_t gpa, bool write)
4568{
4569 /* For APIC access vmexit */
4570 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4571 return 1;
4572
4573 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4574 trace_vcpu_match_mmio(gva, gpa, write, true);
4575 return 1;
4576 }
4577
4578 return 0;
4579}
4580
af7cc7d1
XG		 4581static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4582 gpa_t *gpa, struct x86_exception *exception,
4583 bool write)
4584{
97d64b78
AK		 4585 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4586 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4587
be94f6b7
HH		 4588 /*
4589 * currently PKRU is only applied to ept enabled guest so
4590 * there is no pkey in EPT page table for L1 guest or EPT
4591 * shadow page table for L2 guest.
4592 */
97d64b78 4593 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4594 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4595 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4596 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4597 (gva & (PAGE_SIZE - 1));
4f022648 4598 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4599 return 1;
4600 }
4601
af7cc7d1
XG		 4602 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4603
4604 if (*gpa == UNMAPPED_GVA)
4605 return -1;
4606
0f89b207 4607 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4608}
4609
3200f405 4610int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4611 const void *val, int bytes)
bbd9b64e
CO		 4612{
4613 int ret;
4614
54bf36aa 4615 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4616 if (ret < 0)
bbd9b64e 4617 return 0;
0eb05bf2 4618 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4619 return 1;
4620}
4621
77d197b2
XG		 4622struct read_write_emulator_ops {
4623 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4624 int bytes);
4625 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4626 void *val, int bytes);
4627 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4628 int bytes, void *val);
4629 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4630 void *val, int bytes);
4631 bool write;
4632};
4633
4634static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4635{
4636 if (vcpu->mmio_read_completed) {
77d197b2 4637 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4638 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4639 vcpu->mmio_read_completed = 0;
4640 return 1;
4641 }
4642
4643 return 0;
4644}
4645
4646static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4647 void *val, int bytes)
4648{
54bf36aa 4649 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4650}
4651
4652static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4653 void *val, int bytes)
4654{
4655 return emulator_write_phys(vcpu, gpa, val, bytes);
4656}
4657
4658static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4659{
4660 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4661 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4662}
4663
4664static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4665 void *val, int bytes)
4666{
4667 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4668 return X86EMUL_IO_NEEDED;
4669}
4670
4671static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4672 void *val, int bytes)
4673{
f78146b0
AK		 4674 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4675
87da7e66 4676 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4677 return X86EMUL_CONTINUE;
4678}
4679
0fbe9b0b 4680static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4681 .read_write_prepare = read_prepare,
4682 .read_write_emulate = read_emulate,
4683 .read_write_mmio = vcpu_mmio_read,
4684 .read_write_exit_mmio = read_exit_mmio,
4685};
4686
0fbe9b0b 4687static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4688 .read_write_emulate = write_emulate,
4689 .read_write_mmio = write_mmio,
4690 .read_write_exit_mmio = write_exit_mmio,
4691 .write = true,
4692};
4693
22388a3c
XG		 4694static int emulator_read_write_onepage(unsigned long addr, void *val,
4695 unsigned int bytes,
4696 struct x86_exception *exception,
4697 struct kvm_vcpu *vcpu,
0fbe9b0b 4698 const struct read_write_emulator_ops *ops)
bbd9b64e 4699{
af7cc7d1
XG		 4700 gpa_t gpa;
4701 int handled, ret;
22388a3c 4702 bool write = ops->write;
f78146b0 4703 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4704 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4705
4706 /*
4707 * If the exit was due to a NPF we may already have a GPA.
4708 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4709 * Note, this cannot be used on string operations since string
4710 * operation using rep will only have the initial GPA from the NPF
4711 * occurred.
4712 */
4713 if (vcpu->arch.gpa_available &&
4714 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4715 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4716 gpa = vcpu->arch.gpa_val;
4717 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4718 } else {
4719 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4720 if (ret < 0)
4721 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4722 }
10589a46 4723
618232e2 4724 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4725 return X86EMUL_CONTINUE;
4726
bbd9b64e
CO		 4727 /*
4728 * Is this MMIO handled locally?
4729 */
22388a3c 4730 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4731 if (handled == bytes)
bbd9b64e 4732 return X86EMUL_CONTINUE;
bbd9b64e 4733
70252a10
AK		 4734 gpa += handled;
4735 bytes -= handled;
4736 val += handled;
4737
87da7e66
XG		 4738 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4739 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4740 frag->gpa = gpa;
4741 frag->data = val;
4742 frag->len = bytes;
f78146b0 4743 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4744}
4745
52eb5a6d
XL		 4746static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4747 unsigned long addr,
22388a3c
XG		 4748 void *val, unsigned int bytes,
4749 struct x86_exception *exception,
0fbe9b0b 4750 const struct read_write_emulator_ops *ops)
bbd9b64e 4751{
0f65dd70 4752 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4753 gpa_t gpa;
4754 int rc;
4755
4756 if (ops->read_write_prepare &&
4757 ops->read_write_prepare(vcpu, val, bytes))
4758 return X86EMUL_CONTINUE;
4759
4760 vcpu->mmio_nr_fragments = 0;
0f65dd70 4761
bbd9b64e
CO		 4762 /* Crossing a page boundary? */
4763 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4764 int now;
bbd9b64e
CO		 4765
4766 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4767 rc = emulator_read_write_onepage(addr, val, now, exception,
4768 vcpu, ops);
4769
bbd9b64e
CO		 4770 if (rc != X86EMUL_CONTINUE)
4771 return rc;
4772 addr += now;
bac15531
NA		 4773 if (ctxt->mode != X86EMUL_MODE_PROT64)
4774 addr = (u32)addr;
bbd9b64e
CO		 4775 val += now;
4776 bytes -= now;
4777 }
22388a3c 4778
f78146b0
AK		 4779 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4780 vcpu, ops);
4781 if (rc != X86EMUL_CONTINUE)
4782 return rc;
4783
4784 if (!vcpu->mmio_nr_fragments)
4785 return rc;
4786
4787 gpa = vcpu->mmio_fragments[0].gpa;
4788
4789 vcpu->mmio_needed = 1;
4790 vcpu->mmio_cur_fragment = 0;
4791
87da7e66 4792 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4793 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4794 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4795 vcpu->run->mmio.phys_addr = gpa;
4796
4797 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4798}
4799
4800static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4801 unsigned long addr,
4802 void *val,
4803 unsigned int bytes,
4804 struct x86_exception *exception)
4805{
4806 return emulator_read_write(ctxt, addr, val, bytes,
4807 exception, &read_emultor);
4808}
4809
52eb5a6d 4810static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4811 unsigned long addr,
4812 const void *val,
4813 unsigned int bytes,
4814 struct x86_exception *exception)
4815{
4816 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4817 exception, &write_emultor);
bbd9b64e 4818}
bbd9b64e 4819
daea3e73
AK		 4820#define CMPXCHG_TYPE(t, ptr, old, new) \
4821 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4822
4823#ifdef CONFIG_X86_64
4824# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4825#else
4826# define CMPXCHG64(ptr, old, new) \
9749a6c0 4827 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4828#endif
4829
0f65dd70
AK		 4830static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4831 unsigned long addr,
bbd9b64e
CO		 4832 const void *old,
4833 const void *new,
4834 unsigned int bytes,
0f65dd70 4835 struct x86_exception *exception)
bbd9b64e 4836{
0f65dd70 4837 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4838 gpa_t gpa;
4839 struct page *page;
4840 char *kaddr;
4841 bool exchanged;
2bacc55c 4842
daea3e73
AK		 4843 /* guests cmpxchg8b have to be emulated atomically */
4844 if (bytes > 8 || (bytes & (bytes - 1)))
4845 goto emul_write;
10589a46 4846
daea3e73 4847 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4848
daea3e73
AK		 4849 if (gpa == UNMAPPED_GVA ||
4850 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4851 goto emul_write;
2bacc55c 4852
daea3e73
AK		 4853 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4854 goto emul_write;
72dc67a6 4855
54bf36aa 4856 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4857 if (is_error_page(page))
c19b8bd6 4858 goto emul_write;
72dc67a6 4859
8fd75e12 4860 kaddr = kmap_atomic(page);
daea3e73
AK		 4861 kaddr += offset_in_page(gpa);
4862 switch (bytes) {
4863 case 1:
4864 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4865 break;
4866 case 2:
4867 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4868 break;
4869 case 4:
4870 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4871 break;
4872 case 8:
4873 exchanged = CMPXCHG64(kaddr, old, new);
4874 break;
4875 default:
4876 BUG();
2bacc55c 4877 }
8fd75e12 4878 kunmap_atomic(kaddr);
daea3e73
AK		 4879 kvm_release_page_dirty(page);
4880
4881 if (!exchanged)
4882 return X86EMUL_CMPXCHG_FAILED;
4883
54bf36aa 4884 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4885 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4886
4887 return X86EMUL_CONTINUE;
4a5f48f6 4888
3200f405 4889emul_write:
daea3e73 4890 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4891
0f65dd70 4892 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4893}
4894
cf8f70bf
GN		 4895static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4896{
cbfc6c91 4897 int r = 0, i;
cf8f70bf 4898
cbfc6c91
WL		 4899 for (i = 0; i < vcpu->arch.pio.count; i++) {
4900 if (vcpu->arch.pio.in)
4901 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4902 vcpu->arch.pio.size, pd);
4903 else
4904 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4905 vcpu->arch.pio.port, vcpu->arch.pio.size,
4906 pd);
4907 if (r)
4908 break;
4909 pd += vcpu->arch.pio.size;
4910 }
cf8f70bf
GN		 4911 return r;
4912}
4913
6f6fbe98
XG		 4914static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4915 unsigned short port, void *val,
4916 unsigned int count, bool in)
cf8f70bf 4917{
cf8f70bf 4918 vcpu->arch.pio.port = port;
6f6fbe98 4919 vcpu->arch.pio.in = in;
7972995b 4920 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4921 vcpu->arch.pio.size = size;
4922
4923 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4924 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4925 return 1;
4926 }
4927
4928 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4929 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4930 vcpu->run->io.size = size;
4931 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4932 vcpu->run->io.count = count;
4933 vcpu->run->io.port = port;
4934
4935 return 0;
4936}
4937
6f6fbe98
XG		 4938static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4939 int size, unsigned short port, void *val,
4940 unsigned int count)
cf8f70bf 4941{
ca1d4a9e 4942 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4943 int ret;
ca1d4a9e 4944
6f6fbe98
XG		 4945 if (vcpu->arch.pio.count)
4946 goto data_avail;
cf8f70bf 4947
cbfc6c91
WL		 4948 memset(vcpu->arch.pio_data, 0, size * count);
4949
6f6fbe98
XG		 4950 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4951 if (ret) {
4952data_avail:
4953 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4954 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4955 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4956 return 1;
4957 }
4958
cf8f70bf
GN		 4959 return 0;
4960}
4961
6f6fbe98
XG		 4962static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4963 int size, unsigned short port,
4964 const void *val, unsigned int count)
4965{
4966 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4967
4968 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4969 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4970 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4971}
4972
bbd9b64e
CO		 4973static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4974{
4975 return kvm_x86_ops->get_segment_base(vcpu, seg);
4976}
4977
3cb16fe7 4978static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4979{
3cb16fe7 4980 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4981}
4982
ae6a2375 4983static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4984{
4985 if (!need_emulate_wbinvd(vcpu))
4986 return X86EMUL_CONTINUE;
4987
4988 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4989 int cpu = get_cpu();
4990
4991 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4992 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4993 wbinvd_ipi, NULL, 1);
2eec7343 4994 put_cpu();
f5f48ee1 4995 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4996 } else
4997 wbinvd();
f5f48ee1
SY		 4998 return X86EMUL_CONTINUE;
4999}
5cb56059
JS		 5000
5001int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5002{
6affcbed
KH		 5003 kvm_emulate_wbinvd_noskip(vcpu);
5004 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5005}
f5f48ee1
SY		 5006EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5007
5cb56059
JS		 5008
5009
bcaf5cc5
AK		 5010static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5011{
5cb56059 5012 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5013}
5014
52eb5a6d
XL		 5015static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5016 unsigned long *dest)
bbd9b64e 5017{
16f8a6f9 5018 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5019}
5020
52eb5a6d
XL		 5021static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5022 unsigned long value)
bbd9b64e 5023{
338dbc97 5024
717746e3 5025 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5026}
5027
52a46617 5028static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5029{
52a46617 5030 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5031}
5032
717746e3 5033static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5034{
717746e3 5035 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5036 unsigned long value;
5037
5038 switch (cr) {
5039 case 0:
5040 value = kvm_read_cr0(vcpu);
5041 break;
5042 case 2:
5043 value = vcpu->arch.cr2;
5044 break;
5045 case 3:
9f8fe504 5046 value = kvm_read_cr3(vcpu);
52a46617
GN		 5047 break;
5048 case 4:
5049 value = kvm_read_cr4(vcpu);
5050 break;
5051 case 8:
5052 value = kvm_get_cr8(vcpu);
5053 break;
5054 default:
a737f256 5055 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5056 return 0;
5057 }
5058
5059 return value;
5060}
5061
717746e3 5062static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5063{
717746e3 5064 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5065 int res = 0;
5066
52a46617
GN		 5067 switch (cr) {
5068 case 0:
49a9b07e 5069 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5070 break;
5071 case 2:
5072 vcpu->arch.cr2 = val;
5073 break;
5074 case 3:
2390218b 5075 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5076 break;
5077 case 4:
a83b29c6 5078 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5079 break;
5080 case 8:
eea1cff9 5081 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5082 break;
5083 default:
a737f256 5084 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5085 res = -1;
52a46617 5086 }
0f12244f
GN		 5087
5088 return res;
52a46617
GN		 5089}
5090
717746e3 5091static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5092{
717746e3 5093 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5094}
5095
4bff1e86 5096static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5097{
4bff1e86 5098 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5099}
5100
4bff1e86 5101static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5102{
4bff1e86 5103 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5104}
5105
1ac9d0cf
AK		 5106static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5107{
5108 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5109}
5110
5111static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5112{
5113 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5114}
5115
4bff1e86
AK		 5116static unsigned long emulator_get_cached_segment_base(
5117 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5118{
4bff1e86 5119 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5120}
5121
1aa36616
AK		 5122static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5123 struct desc_struct *desc, u32 *base3,
5124 int seg)
2dafc6c2
GN		 5125{
5126 struct kvm_segment var;
5127
4bff1e86 5128 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5129 *selector = var.selector;
2dafc6c2 5130
378a8b09
GN		 5131 if (var.unusable) {
5132 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5133 if (base3)
5134 *base3 = 0;
2dafc6c2 5135 return false;
378a8b09 5136 }
2dafc6c2
GN		 5137
5138 if (var.g)
5139 var.limit >>= 12;
5140 set_desc_limit(desc, var.limit);
5141 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5142#ifdef CONFIG_X86_64
5143 if (base3)
5144 *base3 = var.base >> 32;
5145#endif
2dafc6c2
GN		 5146 desc->type = var.type;
5147 desc->s = var.s;
5148 desc->dpl = var.dpl;
5149 desc->p = var.present;
5150 desc->avl = var.avl;
5151 desc->l = var.l;
5152 desc->d = var.db;
5153 desc->g = var.g;
5154
5155 return true;
5156}
5157
1aa36616
AK		 5158static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5159 struct desc_struct *desc, u32 base3,
5160 int seg)
2dafc6c2 5161{
4bff1e86 5162 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5163 struct kvm_segment var;
5164
1aa36616 5165 var.selector = selector;
2dafc6c2 5166 var.base = get_desc_base(desc);
5601d05b
GN		 5167#ifdef CONFIG_X86_64
5168 var.base |= ((u64)base3) << 32;
5169#endif
2dafc6c2
GN		 5170 var.limit = get_desc_limit(desc);
5171 if (desc->g)
5172 var.limit = (var.limit << 12) | 0xfff;
5173 var.type = desc->type;
2dafc6c2
GN		 5174 var.dpl = desc->dpl;
5175 var.db = desc->d;
5176 var.s = desc->s;
5177 var.l = desc->l;
5178 var.g = desc->g;
5179 var.avl = desc->avl;
5180 var.present = desc->p;
5181 var.unusable = !var.present;
5182 var.padding = 0;
5183
5184 kvm_set_segment(vcpu, &var, seg);
5185 return;
5186}
5187
717746e3
AK		 5188static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5189 u32 msr_index, u64 *pdata)
5190{
609e36d3
PB		 5191 struct msr_data msr;
5192 int r;
5193
5194 msr.index = msr_index;
5195 msr.host_initiated = false;
5196 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5197 if (r)
5198 return r;
5199
5200 *pdata = msr.data;
5201 return 0;
717746e3
AK		 5202}
5203
5204static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5205 u32 msr_index, u64 data)
5206{
8fe8ab46
WA		 5207 struct msr_data msr;
5208
5209 msr.data = data;
5210 msr.index = msr_index;
5211 msr.host_initiated = false;
5212 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5213}
5214
64d60670
PB		 5215static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5216{
5217 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5218
5219 return vcpu->arch.smbase;
5220}
5221
5222static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5223{
5224 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5225
5226 vcpu->arch.smbase = smbase;
5227}
5228
67f4d428
NA		 5229static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5230 u32 pmc)
5231{
c6702c9d 5232 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5233}
5234
222d21aa
AK		 5235static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5236 u32 pmc, u64 *pdata)
5237{
c6702c9d 5238 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5239}
5240
6c3287f7
AK		 5241static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5242{
5243 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5244}
5245
5037f6f3
AK		 5246static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5247{
5248 preempt_disable();
5197b808 5249 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5250}
5251
5252static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5253{
5254 preempt_enable();
5255}
5256
2953538e 5257static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5258 struct x86_instruction_info *info,
c4f035c6
AK		 5259 enum x86_intercept_stage stage)
5260{
2953538e 5261 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5262}
5263
e911eb3b
YZ		 5264static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5265 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5266{
e911eb3b 5267 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5268}
5269
dd856efa
AK		 5270static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5271{
5272 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5273}
5274
5275static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5276{
5277 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5278}
5279
801806d9
NA		 5280static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5281{
5282 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5283}
5284
6ed071f0
LP		 5285static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5286{
5287 return emul_to_vcpu(ctxt)->arch.hflags;
5288}
5289
5290static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5291{
5292 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5293}
5294
0234bf88
LP		 5295static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5296{
5297 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5298}
5299
0225fb50 5300static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5301 .read_gpr = emulator_read_gpr,
5302 .write_gpr = emulator_write_gpr,
1871c602 5303 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5304 .write_std = kvm_write_guest_virt_system,
7a036a6f 5305 .read_phys = kvm_read_guest_phys_system,
1871c602 5306 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5307 .read_emulated = emulator_read_emulated,
5308 .write_emulated = emulator_write_emulated,
5309 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5310 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5311 .pio_in_emulated = emulator_pio_in_emulated,
5312 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5313 .get_segment = emulator_get_segment,
5314 .set_segment = emulator_set_segment,
5951c442 5315 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5316 .get_gdt = emulator_get_gdt,
160ce1f1 5317 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5318 .set_gdt = emulator_set_gdt,
5319 .set_idt = emulator_set_idt,
52a46617
GN		 5320 .get_cr = emulator_get_cr,
5321 .set_cr = emulator_set_cr,
9c537244 5322 .cpl = emulator_get_cpl,
35aa5375
GN		 5323 .get_dr = emulator_get_dr,
5324 .set_dr = emulator_set_dr,
64d60670
PB		 5325 .get_smbase = emulator_get_smbase,
5326 .set_smbase = emulator_set_smbase,
717746e3
AK		 5327 .set_msr = emulator_set_msr,
5328 .get_msr = emulator_get_msr,
67f4d428 5329 .check_pmc = emulator_check_pmc,
222d21aa 5330 .read_pmc = emulator_read_pmc,
6c3287f7 5331 .halt = emulator_halt,
bcaf5cc5 5332 .wbinvd = emulator_wbinvd,
d6aa1000 5333 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5334 .get_fpu = emulator_get_fpu,
5335 .put_fpu = emulator_put_fpu,
c4f035c6 5336 .intercept = emulator_intercept,
bdb42f5a 5337 .get_cpuid = emulator_get_cpuid,
801806d9 5338 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5339 .get_hflags = emulator_get_hflags,
5340 .set_hflags = emulator_set_hflags,
0234bf88 5341 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5342};
5343
95cb2295
GN		 5344static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5345{
37ccdcbe 5346 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5347 /*
5348 * an sti; sti; sequence only disable interrupts for the first
5349 * instruction. So, if the last instruction, be it emulated or
5350 * not, left the system with the INT_STI flag enabled, it
5351 * means that the last instruction is an sti. We should not
5352 * leave the flag on in this case. The same goes for mov ss
5353 */
37ccdcbe
PB		 5354 if (int_shadow & mask)
5355 mask = 0;
6addfc42 5356 if (unlikely(int_shadow || mask)) {
95cb2295 5357 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5358 if (!mask)
5359 kvm_make_request(KVM_REQ_EVENT, vcpu);
5360 }
95cb2295
GN		 5361}
5362
ef54bcfe 5363static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5364{
5365 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5366 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5367 return kvm_propagate_fault(vcpu, &ctxt->exception);
5368
5369 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5370 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5371 ctxt->exception.error_code);
54b8486f 5372 else
da9cb575 5373 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5374 return false;
54b8486f
GN		 5375}
5376
8ec4722d
MG		 5377static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5378{
adf52235 5379 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5380 int cs_db, cs_l;
5381
8ec4722d
MG		 5382 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5383
adf52235 5384 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5385 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5386
adf52235
TY		 5387 ctxt->eip = kvm_rip_read(vcpu);
5388 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5389 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5390 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5391 cs_db ? X86EMUL_MODE_PROT32 :
5392 X86EMUL_MODE_PROT16;
a584539b 5393 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5394 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5395 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5396
dd856efa 5397 init_decode_cache(ctxt);
7ae441ea 5398 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5399}
5400
71f9833b 5401int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5402{
9d74191a 5403 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5404 int ret;
5405
5406 init_emulate_ctxt(vcpu);
5407
9dac77fa
AK		 5408 ctxt->op_bytes = 2;
5409 ctxt->ad_bytes = 2;
5410 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5411 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5412
5413 if (ret != X86EMUL_CONTINUE)
5414 return EMULATE_FAIL;
5415
9dac77fa 5416 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5417 kvm_rip_write(vcpu, ctxt->eip);
5418 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5419
5420 if (irq == NMI_VECTOR)
7460fb4a 5421 vcpu->arch.nmi_pending = 0;
63995653
MG		 5422 else
5423 vcpu->arch.interrupt.pending = false;
5424
5425 return EMULATE_DONE;
5426}
5427EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5428
6d77dbfc
GN		 5429static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5430{
fc3a9157
JR		 5431 int r = EMULATE_DONE;
5432
6d77dbfc
GN		 5433 ++vcpu->stat.insn_emulation_fail;
5434 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5435 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5436 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5437 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5438 vcpu->run->internal.ndata = 0;
5439 r = EMULATE_FAIL;
5440 }
6d77dbfc 5441 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5442
5443 return r;
6d77dbfc
GN		 5444}
5445
93c05d3e 5446static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5447 bool write_fault_to_shadow_pgtable,
5448 int emulation_type)
a6f177ef 5449{
95b3cf69 5450 gpa_t gpa = cr2;
ba049e93 5451 kvm_pfn_t pfn;
a6f177ef 5452
991eebf9
GN		 5453 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5454 return false;
5455
95b3cf69
XG		 5456 if (!vcpu->arch.mmu.direct_map) {
5457 /*
5458 * Write permission should be allowed since only
5459 * write access need to be emulated.
5460 */
5461 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5462
95b3cf69
XG		 5463 /*
5464 * If the mapping is invalid in guest, let cpu retry
5465 * it to generate fault.
5466 */
5467 if (gpa == UNMAPPED_GVA)
5468 return true;
5469 }
a6f177ef 5470
8e3d9d06
XG		 5471 /*
5472 * Do not retry the unhandleable instruction if it faults on the
5473 * readonly host memory, otherwise it will goto a infinite loop:
5474 * retry instruction -> write #PF -> emulation fail -> retry
5475 * instruction -> ...
5476 */
5477 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5478
5479 /*
5480 * If the instruction failed on the error pfn, it can not be fixed,
5481 * report the error to userspace.
5482 */
5483 if (is_error_noslot_pfn(pfn))
5484 return false;
5485
5486 kvm_release_pfn_clean(pfn);
5487
5488 /* The instructions are well-emulated on direct mmu. */
5489 if (vcpu->arch.mmu.direct_map) {
5490 unsigned int indirect_shadow_pages;
5491
5492 spin_lock(&vcpu->kvm->mmu_lock);
5493 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5494 spin_unlock(&vcpu->kvm->mmu_lock);
5495
5496 if (indirect_shadow_pages)
5497 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5498
a6f177ef 5499 return true;
8e3d9d06 5500 }
a6f177ef 5501
95b3cf69
XG		 5502 /*
5503 * if emulation was due to access to shadowed page table
5504 * and it failed try to unshadow page and re-enter the
5505 * guest to let CPU execute the instruction.
5506 */
5507 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5508
5509 /*
5510 * If the access faults on its page table, it can not
5511 * be fixed by unprotecting shadow page and it should
5512 * be reported to userspace.
5513 */
5514 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5515}
5516
1cb3f3ae
XG		 5517static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5518 unsigned long cr2, int emulation_type)
5519{
5520 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5521 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5522
5523 last_retry_eip = vcpu->arch.last_retry_eip;
5524 last_retry_addr = vcpu->arch.last_retry_addr;
5525
5526 /*
5527 * If the emulation is caused by #PF and it is non-page_table
5528 * writing instruction, it means the VM-EXIT is caused by shadow
5529 * page protected, we can zap the shadow page and retry this
5530 * instruction directly.
5531 *
5532 * Note: if the guest uses a non-page-table modifying instruction
5533 * on the PDE that points to the instruction, then we will unmap
5534 * the instruction and go to an infinite loop. So, we cache the
5535 * last retried eip and the last fault address, if we meet the eip
5536 * and the address again, we can break out of the potential infinite
5537 * loop.
5538 */
5539 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5540
5541 if (!(emulation_type & EMULTYPE_RETRY))
5542 return false;
5543
5544 if (x86_page_table_writing_insn(ctxt))
5545 return false;
5546
5547 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5548 return false;
5549
5550 vcpu->arch.last_retry_eip = ctxt->eip;
5551 vcpu->arch.last_retry_addr = cr2;
5552
5553 if (!vcpu->arch.mmu.direct_map)
5554 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5555
22368028 5556 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5557
5558 return true;
5559}
5560
716d51ab
GN		 5561static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5562static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5563
64d60670 5564static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5565{
64d60670 5566 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5567 /* This is a good place to trace that we are exiting SMM. */
5568 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5569
c43203ca
PB		 5570 /* Process a latched INIT or SMI, if any. */
5571 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5572 }
699023e2
PB		 5573
5574 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5575}
5576
5577static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5578{
5579 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5580
a584539b 5581 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5582
5583 if (changed & HF_SMM_MASK)
5584 kvm_smm_changed(vcpu);
a584539b
PB		 5585}
5586
4a1e10d5
PB		 5587static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5588 unsigned long *db)
5589{
5590 u32 dr6 = 0;
5591 int i;
5592 u32 enable, rwlen;
5593
5594 enable = dr7;
5595 rwlen = dr7 >> 16;
5596 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5597 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5598 dr6 |= (1 << i);
5599 return dr6;
5600}
5601
c8401dda 5602static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5603{
5604 struct kvm_run *kvm_run = vcpu->run;
5605
c8401dda
PB		 5606 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5607 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5608 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5609 kvm_run->debug.arch.exception = DB_VECTOR;
5610 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5611 *r = EMULATE_USER_EXIT;
5612 } else {
5613 /*
5614 * "Certain debug exceptions may clear bit 0-3. The
5615 * remaining contents of the DR6 register are never
5616 * cleared by the processor".
5617 */
5618 vcpu->arch.dr6 &= ~15;
5619 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5620 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5621 }
5622}
5623
6affcbed
KH		 5624int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5625{
5626 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5627 int r = EMULATE_DONE;
5628
5629 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5630
5631 /*
5632 * rflags is the old, "raw" value of the flags. The new value has
5633 * not been saved yet.
5634 *
5635 * This is correct even for TF set by the guest, because "the
5636 * processor will not generate this exception after the instruction
5637 * that sets the TF flag".
5638 */
5639 if (unlikely(rflags & X86_EFLAGS_TF))
5640 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5641 return r == EMULATE_DONE;
5642}
5643EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5644
4a1e10d5
PB		 5645static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5646{
4a1e10d5
PB		 5647 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5648 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5649 struct kvm_run *kvm_run = vcpu->run;
5650 unsigned long eip = kvm_get_linear_rip(vcpu);
5651 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5652 vcpu->arch.guest_debug_dr7,
5653 vcpu->arch.eff_db);
5654
5655 if (dr6 != 0) {
6f43ed01 5656 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5657 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5658 kvm_run->debug.arch.exception = DB_VECTOR;
5659 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5660 *r = EMULATE_USER_EXIT;
5661 return true;
5662 }
5663 }
5664
4161a569
NA		 5665 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5666 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5667 unsigned long eip = kvm_get_linear_rip(vcpu);
5668 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5669 vcpu->arch.dr7,
5670 vcpu->arch.db);
5671
5672 if (dr6 != 0) {
5673 vcpu->arch.dr6 &= ~15;
6f43ed01 5674 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5675 kvm_queue_exception(vcpu, DB_VECTOR);
5676 *r = EMULATE_DONE;
5677 return true;
5678 }
5679 }
5680
5681 return false;
5682}
5683
51d8b661
AP		 5684int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5685 unsigned long cr2,
dc25e89e
AP		 5686 int emulation_type,
5687 void *insn,
5688 int insn_len)
bbd9b64e 5689{
95cb2295 5690 int r;
9d74191a 5691 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5692 bool writeback = true;
93c05d3e 5693 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5694
93c05d3e
XG		 5695 /*
5696 * Clear write_fault_to_shadow_pgtable here to ensure it is
5697 * never reused.
5698 */
5699 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5700 kvm_clear_exception_queue(vcpu);
8d7d8102 5701
571008da 5702 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5703 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5704
5705 /*
5706 * We will reenter on the same instruction since
5707 * we do not set complete_userspace_io. This does not
5708 * handle watchpoints yet, those would be handled in
5709 * the emulate_ops.
5710 */
5711 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5712 return r;
5713
9d74191a
TY		 5714 ctxt->interruptibility = 0;
5715 ctxt->have_exception = false;
e0ad0b47 5716 ctxt->exception.vector = -1;
9d74191a 5717 ctxt->perm_ok = false;
bbd9b64e 5718
b51e974f 5719 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5720
9d74191a 5721 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5722
e46479f8 5723 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5724 ++vcpu->stat.insn_emulation;
1d2887e2 5725 if (r != EMULATION_OK) {
4005996e
AK		 5726 if (emulation_type & EMULTYPE_TRAP_UD)
5727 return EMULATE_FAIL;
991eebf9
GN		 5728 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5729 emulation_type))
bbd9b64e 5730 return EMULATE_DONE;
6d77dbfc
GN		 5731 if (emulation_type & EMULTYPE_SKIP)
5732 return EMULATE_FAIL;
5733 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5734 }
5735 }
5736
ba8afb6b 5737 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5738 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5739 if (ctxt->eflags & X86_EFLAGS_RF)
5740 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5741 return EMULATE_DONE;
5742 }
5743
1cb3f3ae
XG		 5744 if (retry_instruction(ctxt, cr2, emulation_type))
5745 return EMULATE_DONE;
5746
7ae441ea 5747 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5748 changes registers values during IO operation */
7ae441ea
GN		 5749 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5750 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5751 emulator_invalidate_register_cache(ctxt);
7ae441ea 5752 }
4d2179e1 5753
5cd21917 5754restart:
0f89b207
TL		 5755 /* Save the faulting GPA (cr2) in the address field */
5756 ctxt->exception.address = cr2;
5757
9d74191a 5758 r = x86_emulate_insn(ctxt);
bbd9b64e 5759
775fde86
JR		 5760 if (r == EMULATION_INTERCEPTED)
5761 return EMULATE_DONE;
5762
d2ddd1c4 5763 if (r == EMULATION_FAILED) {
991eebf9
GN		 5764 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5765 emulation_type))
c3cd7ffa
GN		 5766 return EMULATE_DONE;
5767
6d77dbfc 5768 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5769 }
5770
9d74191a 5771 if (ctxt->have_exception) {
d2ddd1c4 5772 r = EMULATE_DONE;
ef54bcfe
PB		 5773 if (inject_emulated_exception(vcpu))
5774 return r;
d2ddd1c4 5775 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5776 if (!vcpu->arch.pio.in) {
5777 /* FIXME: return into emulator if single-stepping. */
3457e419 5778 vcpu->arch.pio.count = 0;
0912c977 5779 } else {
7ae441ea 5780 writeback = false;
716d51ab
GN		 5781 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5782 }
ac0a48c3 5783 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5784 } else if (vcpu->mmio_needed) {
5785 if (!vcpu->mmio_is_write)
5786 writeback = false;
ac0a48c3 5787 r = EMULATE_USER_EXIT;
716d51ab 5788 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5789 } else if (r == EMULATION_RESTART)
5cd21917 5790 goto restart;
d2ddd1c4
GN		 5791 else
5792 r = EMULATE_DONE;
f850e2e6 5793
7ae441ea 5794 if (writeback) {
6addfc42 5795 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5796 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5797 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5798 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5799 if (r == EMULATE_DONE &&
5800 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5801 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5802 if (!ctxt->have_exception ||
5803 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5804 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5805
5806 /*
5807 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5808 * do nothing, and it will be requested again as soon as
5809 * the shadow expires. But we still need to check here,
5810 * because POPF has no interrupt shadow.
5811 */
5812 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5813 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5814 } else
5815 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5816
5817 return r;
de7d789a 5818}
51d8b661 5819EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5820
cf8f70bf 5821int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5822{
cf8f70bf 5823 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5824 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5825 size, port, &val, 1);
cf8f70bf 5826 /* do not return to emulator after return from userspace */
7972995b 5827 vcpu->arch.pio.count = 0;
de7d789a
CO		 5828 return ret;
5829}
cf8f70bf 5830EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5831
8370c3d0
TL		 5832static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5833{
5834 unsigned long val;
5835
5836 /* We should only ever be called with arch.pio.count equal to 1 */
5837 BUG_ON(vcpu->arch.pio.count != 1);
5838
5839 /* For size less than 4 we merge, else we zero extend */
5840 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5841 : 0;
5842
5843 /*
5844 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5845 * the copy and tracing
5846 */
5847 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5848 vcpu->arch.pio.port, &val, 1);
5849 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5850
5851 return 1;
5852}
5853
5854int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5855{
5856 unsigned long val;
5857 int ret;
5858
5859 /* For size less than 4 we merge, else we zero extend */
5860 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5861
5862 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5863 &val, 1);
5864 if (ret) {
5865 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5866 return ret;
5867 }
5868
5869 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5870
5871 return 0;
5872}
5873EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5874
251a5fd6 5875static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5876{
0a3aee0d 5877 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5878 return 0;
8cfdc000
ZA		 5879}
5880
5881static void tsc_khz_changed(void *data)
c8076604 5882{
8cfdc000
ZA		 5883 struct cpufreq_freqs *freq = data;
5884 unsigned long khz = 0;
5885
5886 if (data)
5887 khz = freq->new;
5888 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5889 khz = cpufreq_quick_get(raw_smp_processor_id());
5890 if (!khz)
5891 khz = tsc_khz;
0a3aee0d 5892 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5893}
5894
c8076604
GH		 5895static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5896 void *data)
5897{
5898 struct cpufreq_freqs *freq = data;
5899 struct kvm *kvm;
5900 struct kvm_vcpu *vcpu;
5901 int i, send_ipi = 0;
5902
8cfdc000
ZA		 5903 /*
5904 * We allow guests to temporarily run on slowing clocks,
5905 * provided we notify them after, or to run on accelerating
5906 * clocks, provided we notify them before. Thus time never
5907 * goes backwards.
5908 *
5909 * However, we have a problem. We can't atomically update
5910 * the frequency of a given CPU from this function; it is
5911 * merely a notifier, which can be called from any CPU.
5912 * Changing the TSC frequency at arbitrary points in time
5913 * requires a recomputation of local variables related to
5914 * the TSC for each VCPU. We must flag these local variables
5915 * to be updated and be sure the update takes place with the
5916 * new frequency before any guests proceed.
5917 *
5918 * Unfortunately, the combination of hotplug CPU and frequency
5919 * change creates an intractable locking scenario; the order
5920 * of when these callouts happen is undefined with respect to
5921 * CPU hotplug, and they can race with each other. As such,
5922 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5923 * undefined; you can actually have a CPU frequency change take
5924 * place in between the computation of X and the setting of the
5925 * variable. To protect against this problem, all updates of
5926 * the per_cpu tsc_khz variable are done in an interrupt
5927 * protected IPI, and all callers wishing to update the value
5928 * must wait for a synchronous IPI to complete (which is trivial
5929 * if the caller is on the CPU already). This establishes the
5930 * necessary total order on variable updates.
5931 *
5932 * Note that because a guest time update may take place
5933 * anytime after the setting of the VCPU's request bit, the
5934 * correct TSC value must be set before the request. However,
5935 * to ensure the update actually makes it to any guest which
5936 * starts running in hardware virtualization between the set
5937 * and the acquisition of the spinlock, we must also ping the
5938 * CPU after setting the request bit.
5939 *
5940 */
5941
c8076604
GH		 5942 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5943 return 0;
5944 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5945 return 0;
8cfdc000
ZA		 5946
5947 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5948
2f303b74 5949 spin_lock(&kvm_lock);
c8076604 5950 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5951 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5952 if (vcpu->cpu != freq->cpu)
5953 continue;
c285545f 5954 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5955 if (vcpu->cpu != smp_processor_id())
8cfdc000 5956 send_ipi = 1;
c8076604
GH		 5957 }
5958 }
2f303b74 5959 spin_unlock(&kvm_lock);
c8076604
GH		 5960
5961 if (freq->old < freq->new && send_ipi) {
5962 /*
5963 * We upscale the frequency. Must make the guest
5964 * doesn't see old kvmclock values while running with
5965 * the new frequency, otherwise we risk the guest sees
5966 * time go backwards.
5967 *
5968 * In case we update the frequency for another cpu
5969 * (which might be in guest context) send an interrupt
5970 * to kick the cpu out of guest context. Next time
5971 * guest context is entered kvmclock will be updated,
5972 * so the guest will not see stale values.
5973 */
8cfdc000 5974 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5975 }
5976 return 0;
5977}
5978
5979static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5980 .notifier_call = kvmclock_cpufreq_notifier
5981};
5982
251a5fd6 5983static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5984{
251a5fd6
SAS		 5985 tsc_khz_changed(NULL);
5986 return 0;
8cfdc000
ZA		 5987}
5988
b820cc0c
ZA		 5989static void kvm_timer_init(void)
5990{
c285545f 5991 max_tsc_khz = tsc_khz;
460dd42e 5992
b820cc0c 5993 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5994#ifdef CONFIG_CPU_FREQ
5995 struct cpufreq_policy policy;
758f588d
BP		 5996 int cpu;
5997
c285545f 5998 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5999 cpu = get_cpu();
6000 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6001 if (policy.cpuinfo.max_freq)
6002 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6003 put_cpu();
c285545f 6004#endif
b820cc0c
ZA		 6005 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6006 CPUFREQ_TRANSITION_NOTIFIER);
6007 }
c285545f 6008 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6009
73c1b41e 6010 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6011 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6012}
6013
ff9d07a0
ZY		 6014static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6015
f5132b01 6016int kvm_is_in_guest(void)
ff9d07a0 6017{
086c9855 6018 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6019}
6020
6021static int kvm_is_user_mode(void)
6022{
6023 int user_mode = 3;
dcf46b94 6024
086c9855
AS		 6025 if (__this_cpu_read(current_vcpu))
6026 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6027
ff9d07a0
ZY		 6028 return user_mode != 0;
6029}
6030
6031static unsigned long kvm_get_guest_ip(void)
6032{
6033 unsigned long ip = 0;
dcf46b94 6034
086c9855
AS		 6035 if (__this_cpu_read(current_vcpu))
6036 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6037
ff9d07a0
ZY		 6038 return ip;
6039}
6040
6041static struct perf_guest_info_callbacks kvm_guest_cbs = {
6042 .is_in_guest = kvm_is_in_guest,
6043 .is_user_mode = kvm_is_user_mode,
6044 .get_guest_ip = kvm_get_guest_ip,
6045};
6046
6047void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6048{
086c9855 6049 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6050}
6051EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6052
6053void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6054{
086c9855 6055 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6056}
6057EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6058
ce88decf
XG		 6059static void kvm_set_mmio_spte_mask(void)
6060{
6061 u64 mask;
6062 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6063
6064 /*
6065 * Set the reserved bits and the present bit of an paging-structure
6066 * entry to generate page fault with PFER.RSV = 1.
6067 */
885032b9 6068 /* Mask the reserved physical address bits. */
d1431483 6069 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6070
885032b9 6071 /* Set the present bit. */
ce88decf
XG		 6072 mask |= 1ull;
6073
6074#ifdef CONFIG_X86_64
6075 /*
6076 * If reserved bit is not supported, clear the present bit to disable
6077 * mmio page fault.
6078 */
6079 if (maxphyaddr == 52)
6080 mask &= ~1ull;
6081#endif
6082
dcdca5fe 6083 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6084}
6085
16e8d74d
MT		 6086#ifdef CONFIG_X86_64
6087static void pvclock_gtod_update_fn(struct work_struct *work)
6088{
d828199e
MT		 6089 struct kvm *kvm;
6090
6091 struct kvm_vcpu *vcpu;
6092 int i;
6093
2f303b74 6094 spin_lock(&kvm_lock);
d828199e
MT		 6095 list_for_each_entry(kvm, &vm_list, vm_list)
6096 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6097 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6098 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6099 spin_unlock(&kvm_lock);
16e8d74d
MT		 6100}
6101
6102static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6103
6104/*
6105 * Notification about pvclock gtod data update.
6106 */
6107static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6108 void *priv)
6109{
6110 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6111 struct timekeeper *tk = priv;
6112
6113 update_pvclock_gtod(tk);
6114
6115 /* disable master clock if host does not trust, or does not
6116 * use, TSC clocksource
6117 */
6118 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6119 atomic_read(&kvm_guest_has_master_clock) != 0)
6120 queue_work(system_long_wq, &pvclock_gtod_work);
6121
6122 return 0;
6123}
6124
6125static struct notifier_block pvclock_gtod_notifier = {
6126 .notifier_call = pvclock_gtod_notify,
6127};
6128#endif
6129
f8c16bba 6130int kvm_arch_init(void *opaque)
043405e1 6131{
b820cc0c 6132 int r;
6b61edf7 6133 struct kvm_x86_ops *ops = opaque;
f8c16bba 6134
f8c16bba
ZX		 6135 if (kvm_x86_ops) {
6136 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6137 r = -EEXIST;
6138 goto out;
f8c16bba
ZX		 6139 }
6140
6141 if (!ops->cpu_has_kvm_support()) {
6142 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6143 r = -EOPNOTSUPP;
6144 goto out;
f8c16bba
ZX		 6145 }
6146 if (ops->disabled_by_bios()) {
6147 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6148 r = -EOPNOTSUPP;
6149 goto out;
f8c16bba
ZX		 6150 }
6151
013f6a5d
MT		 6152 r = -ENOMEM;
6153 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6154 if (!shared_msrs) {
6155 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6156 goto out;
6157 }
6158
97db56ce
AK		 6159 r = kvm_mmu_module_init();
6160 if (r)
013f6a5d 6161 goto out_free_percpu;
97db56ce 6162
ce88decf 6163 kvm_set_mmio_spte_mask();
97db56ce 6164
f8c16bba 6165 kvm_x86_ops = ops;
920c8377 6166
7b52345e 6167 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6168 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6169 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6170 kvm_timer_init();
c8076604 6171
ff9d07a0
ZY		 6172 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6173
d366bf7e 6174 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6175 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6176
c5cc421b 6177 kvm_lapic_init();
16e8d74d
MT		 6178#ifdef CONFIG_X86_64
6179 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6180#endif
6181
f8c16bba 6182 return 0;
56c6d28a 6183
013f6a5d
MT		 6184out_free_percpu:
6185 free_percpu(shared_msrs);
56c6d28a 6186out:
56c6d28a 6187 return r;
043405e1 6188}
8776e519 6189
f8c16bba
ZX		 6190void kvm_arch_exit(void)
6191{
cef84c30 6192 kvm_lapic_exit();
ff9d07a0
ZY		 6193 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6194
888d256e
JK		 6195 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6196 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6197 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6198 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6199#ifdef CONFIG_X86_64
6200 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6201#endif
f8c16bba 6202 kvm_x86_ops = NULL;
56c6d28a 6203 kvm_mmu_module_exit();
013f6a5d 6204 free_percpu(shared_msrs);
56c6d28a 6205}
f8c16bba 6206
5cb56059 6207int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6208{
6209 ++vcpu->stat.halt_exits;
35754c98 6210 if (lapic_in_kernel(vcpu)) {
a4535290 6211 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6212 return 1;
6213 } else {
6214 vcpu->run->exit_reason = KVM_EXIT_HLT;
6215 return 0;
6216 }
6217}
5cb56059
JS		 6218EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6219
6220int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6221{
6affcbed
KH		 6222 int ret = kvm_skip_emulated_instruction(vcpu);
6223 /*
6224 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6225 * KVM_EXIT_DEBUG here.
6226 */
6227 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6228}
8776e519
HB		 6229EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6230
8ef81a9a 6231#ifdef CONFIG_X86_64
55dd00a7
MT		 6232static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6233 unsigned long clock_type)
6234{
6235 struct kvm_clock_pairing clock_pairing;
6236 struct timespec ts;
80fbd89c 6237 u64 cycle;
55dd00a7
MT		 6238 int ret;
6239
6240 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6241 return -KVM_EOPNOTSUPP;
6242
6243 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6244 return -KVM_EOPNOTSUPP;
6245
6246 clock_pairing.sec = ts.tv_sec;
6247 clock_pairing.nsec = ts.tv_nsec;
6248 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6249 clock_pairing.flags = 0;
6250
6251 ret = 0;
6252 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6253 sizeof(struct kvm_clock_pairing)))
6254 ret = -KVM_EFAULT;
6255
6256 return ret;
6257}
8ef81a9a 6258#endif
55dd00a7 6259
6aef266c
SV		 6260/*
6261 * kvm_pv_kick_cpu_op: Kick a vcpu.
6262 *
6263 * @apicid - apicid of vcpu to be kicked.
6264 */
6265static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6266{
24d2166b 6267 struct kvm_lapic_irq lapic_irq;
6aef266c 6268
24d2166b
R		 6269 lapic_irq.shorthand = 0;
6270 lapic_irq.dest_mode = 0;
ebd28fcb 6271 lapic_irq.level = 0;
24d2166b 6272 lapic_irq.dest_id = apicid;
93bbf0b8 6273 lapic_irq.msi_redir_hint = false;
6aef266c 6274
24d2166b 6275 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6276 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6277}
6278
d62caabb
AS		 6279void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6280{
6281 vcpu->arch.apicv_active = false;
6282 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6283}
6284
8776e519
HB		 6285int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6286{
6287 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6288 int op_64_bit, r;
8776e519 6289
6affcbed 6290 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6291
55cd8e5a
GN		 6292 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6293 return kvm_hv_hypercall(vcpu);
6294
5fdbf976
MT		 6295 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6296 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6297 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6298 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6299 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6300
229456fc 6301 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6302
a449c7aa
NA		 6303 op_64_bit = is_64_bit_mode(vcpu);
6304 if (!op_64_bit) {
8776e519
HB		 6305 nr &= 0xFFFFFFFF;
6306 a0 &= 0xFFFFFFFF;
6307 a1 &= 0xFFFFFFFF;
6308 a2 &= 0xFFFFFFFF;
6309 a3 &= 0xFFFFFFFF;
6310 }
6311
07708c4a
JK		 6312 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6313 ret = -KVM_EPERM;
6314 goto out;
6315 }
6316
8776e519 6317 switch (nr) {
b93463aa
AK		 6318 case KVM_HC_VAPIC_POLL_IRQ:
6319 ret = 0;
6320 break;
6aef266c
SV		 6321 case KVM_HC_KICK_CPU:
6322 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6323 ret = 0;
6324 break;
8ef81a9a 6325#ifdef CONFIG_X86_64
55dd00a7
MT		 6326 case KVM_HC_CLOCK_PAIRING:
6327 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6328 break;
8ef81a9a 6329#endif
8776e519
HB		 6330 default:
6331 ret = -KVM_ENOSYS;
6332 break;
6333 }
07708c4a 6334out:
a449c7aa
NA		 6335 if (!op_64_bit)
6336 ret = (u32)ret;
5fdbf976 6337 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6338 ++vcpu->stat.hypercalls;
2f333bcb 6339 return r;
8776e519
HB		 6340}
6341EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6342
b6785def 6343static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6344{
d6aa1000 6345 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6346 char instruction[3];
5fdbf976 6347 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6348
8776e519 6349 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6350
ce2e852e
DV		 6351 return emulator_write_emulated(ctxt, rip, instruction, 3,
6352 &ctxt->exception);
8776e519
HB		 6353}
6354
851ba692 6355static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6356{
782d422b
MG		 6357 return vcpu->run->request_interrupt_window &&
6358 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6359}
6360
851ba692 6361static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6362{
851ba692
AK		 6363 struct kvm_run *kvm_run = vcpu->run;
6364
91586a3b 6365 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6366 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6367 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6368 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6369 kvm_run->ready_for_interrupt_injection =
6370 pic_in_kernel(vcpu->kvm) ||
782d422b 6371 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6372}
6373
95ba8273
GN		 6374static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6375{
6376 int max_irr, tpr;
6377
6378 if (!kvm_x86_ops->update_cr8_intercept)
6379 return;
6380
bce87cce 6381 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6382 return;
6383
d62caabb
AS		 6384 if (vcpu->arch.apicv_active)
6385 return;
6386
8db3baa2
GN		 6387 if (!vcpu->arch.apic->vapic_addr)
6388 max_irr = kvm_lapic_find_highest_irr(vcpu);
6389 else
6390 max_irr = -1;
95ba8273
GN		 6391
6392 if (max_irr != -1)
6393 max_irr >>= 4;
6394
6395 tpr = kvm_lapic_get_cr8(vcpu);
6396
6397 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6398}
6399
b6b8a145 6400static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6401{
b6b8a145
JK		 6402 int r;
6403
95ba8273 6404 /* try to reinject previous events if any */
664f8e26
WL		 6405 if (vcpu->arch.exception.injected) {
6406 kvm_x86_ops->queue_exception(vcpu);
6407 return 0;
6408 }
6409
6410 /*
6411 * Exceptions must be injected immediately, or the exception
6412 * frame will have the address of the NMI or interrupt handler.
6413 */
6414 if (!vcpu->arch.exception.pending) {
6415 if (vcpu->arch.nmi_injected) {
6416 kvm_x86_ops->set_nmi(vcpu);
6417 return 0;
6418 }
6419
6420 if (vcpu->arch.interrupt.pending) {
6421 kvm_x86_ops->set_irq(vcpu);
6422 return 0;
6423 }
6424 }
6425
6426 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6427 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6428 if (r != 0)
6429 return r;
6430 }
6431
6432 /* try to inject new event if pending */
b59bb7bd 6433 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6434 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6435 vcpu->arch.exception.has_error_code,
6436 vcpu->arch.exception.error_code);
d6e8c854 6437
664f8e26
WL		 6438 vcpu->arch.exception.pending = false;
6439 vcpu->arch.exception.injected = true;
6440
d6e8c854
NA		 6441 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6442 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6443 X86_EFLAGS_RF);
6444
6bdf0662
NA		 6445 if (vcpu->arch.exception.nr == DB_VECTOR &&
6446 (vcpu->arch.dr7 & DR7_GD)) {
6447 vcpu->arch.dr7 &= ~DR7_GD;
6448 kvm_update_dr7(vcpu);
6449 }
6450
cfcd20e5 6451 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6452 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6453 vcpu->arch.smi_pending = false;
ee2cd4b7 6454 enter_smm(vcpu);
c43203ca 6455 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6456 --vcpu->arch.nmi_pending;
6457 vcpu->arch.nmi_injected = true;
6458 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6459 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6460 /*
6461 * Because interrupts can be injected asynchronously, we are
6462 * calling check_nested_events again here to avoid a race condition.
6463 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6464 * proposal and current concerns. Perhaps we should be setting
6465 * KVM_REQ_EVENT only on certain events and not unconditionally?
6466 */
6467 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6468 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6469 if (r != 0)
6470 return r;
6471 }
95ba8273 6472 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6473 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6474 false);
6475 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6476 }
6477 }
ee2cd4b7 6478
b6b8a145 6479 return 0;
95ba8273
GN		 6480}
6481
7460fb4a
AK		 6482static void process_nmi(struct kvm_vcpu *vcpu)
6483{
6484 unsigned limit = 2;
6485
6486 /*
6487 * x86 is limited to one NMI running, and one NMI pending after it.
6488 * If an NMI is already in progress, limit further NMIs to just one.
6489 * Otherwise, allow two (and we'll inject the first one immediately).
6490 */
6491 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6492 limit = 1;
6493
6494 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6495 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6496 kvm_make_request(KVM_REQ_EVENT, vcpu);
6497}
6498
ee2cd4b7 6499static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6500{
6501 u32 flags = 0;
6502 flags |= seg->g << 23;
6503 flags |= seg->db << 22;
6504 flags |= seg->l << 21;
6505 flags |= seg->avl << 20;
6506 flags |= seg->present << 15;
6507 flags |= seg->dpl << 13;
6508 flags |= seg->s << 12;
6509 flags |= seg->type << 8;
6510 return flags;
6511}
6512
ee2cd4b7 6513static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6514{
6515 struct kvm_segment seg;
6516 int offset;
6517
6518 kvm_get_segment(vcpu, &seg, n);
6519 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6520
6521 if (n < 3)
6522 offset = 0x7f84 + n * 12;
6523 else
6524 offset = 0x7f2c + (n - 3) * 12;
6525
6526 put_smstate(u32, buf, offset + 8, seg.base);
6527 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6528 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6529}
6530
efbb288a 6531#ifdef CONFIG_X86_64
ee2cd4b7 6532static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6533{
6534 struct kvm_segment seg;
6535 int offset;
6536 u16 flags;
6537
6538 kvm_get_segment(vcpu, &seg, n);
6539 offset = 0x7e00 + n * 16;
6540
ee2cd4b7 6541 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6542 put_smstate(u16, buf, offset, seg.selector);
6543 put_smstate(u16, buf, offset + 2, flags);
6544 put_smstate(u32, buf, offset + 4, seg.limit);
6545 put_smstate(u64, buf, offset + 8, seg.base);
6546}
efbb288a 6547#endif
660a5d51 6548
ee2cd4b7 6549static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6550{
6551 struct desc_ptr dt;
6552 struct kvm_segment seg;
6553 unsigned long val;
6554 int i;
6555
6556 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6557 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6558 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6559 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6560
6561 for (i = 0; i < 8; i++)
6562 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6563
6564 kvm_get_dr(vcpu, 6, &val);
6565 put_smstate(u32, buf, 0x7fcc, (u32)val);
6566 kvm_get_dr(vcpu, 7, &val);
6567 put_smstate(u32, buf, 0x7fc8, (u32)val);
6568
6569 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6570 put_smstate(u32, buf, 0x7fc4, seg.selector);
6571 put_smstate(u32, buf, 0x7f64, seg.base);
6572 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6573 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6574
6575 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6576 put_smstate(u32, buf, 0x7fc0, seg.selector);
6577 put_smstate(u32, buf, 0x7f80, seg.base);
6578 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6579 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6580
6581 kvm_x86_ops->get_gdt(vcpu, &dt);
6582 put_smstate(u32, buf, 0x7f74, dt.address);
6583 put_smstate(u32, buf, 0x7f70, dt.size);
6584
6585 kvm_x86_ops->get_idt(vcpu, &dt);
6586 put_smstate(u32, buf, 0x7f58, dt.address);
6587 put_smstate(u32, buf, 0x7f54, dt.size);
6588
6589 for (i = 0; i < 6; i++)
ee2cd4b7 6590 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6591
6592 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6593
6594 /* revision id */
6595 put_smstate(u32, buf, 0x7efc, 0x00020000);
6596 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6597}
6598
ee2cd4b7 6599static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6600{
6601#ifdef CONFIG_X86_64
6602 struct desc_ptr dt;
6603 struct kvm_segment seg;
6604 unsigned long val;
6605 int i;
6606
6607 for (i = 0; i < 16; i++)
6608 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6609
6610 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6611 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6612
6613 kvm_get_dr(vcpu, 6, &val);
6614 put_smstate(u64, buf, 0x7f68, val);
6615 kvm_get_dr(vcpu, 7, &val);
6616 put_smstate(u64, buf, 0x7f60, val);
6617
6618 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6619 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6620 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6621
6622 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6623
6624 /* revision id */
6625 put_smstate(u32, buf, 0x7efc, 0x00020064);
6626
6627 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6628
6629 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6630 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6631 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6632 put_smstate(u32, buf, 0x7e94, seg.limit);
6633 put_smstate(u64, buf, 0x7e98, seg.base);
6634
6635 kvm_x86_ops->get_idt(vcpu, &dt);
6636 put_smstate(u32, buf, 0x7e84, dt.size);
6637 put_smstate(u64, buf, 0x7e88, dt.address);
6638
6639 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6640 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6641 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6642 put_smstate(u32, buf, 0x7e74, seg.limit);
6643 put_smstate(u64, buf, 0x7e78, seg.base);
6644
6645 kvm_x86_ops->get_gdt(vcpu, &dt);
6646 put_smstate(u32, buf, 0x7e64, dt.size);
6647 put_smstate(u64, buf, 0x7e68, dt.address);
6648
6649 for (i = 0; i < 6; i++)
ee2cd4b7 6650 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6651#else
6652 WARN_ON_ONCE(1);
6653#endif
6654}
6655
ee2cd4b7 6656static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6657{
660a5d51 6658 struct kvm_segment cs, ds;
18c3626e 6659 struct desc_ptr dt;
660a5d51
PB		 6660 char buf[512];
6661 u32 cr0;
6662
660a5d51 6663 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6664 memset(buf, 0, 512);
d6321d49 6665 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6666 enter_smm_save_state_64(vcpu, buf);
660a5d51 6667 else
ee2cd4b7 6668 enter_smm_save_state_32(vcpu, buf);
660a5d51 6669
0234bf88
LP		 6670 /*
6671 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6672 * vCPU state (e.g. leave guest mode) after we've saved the state into
6673 * the SMM state-save area.
6674 */
6675 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6676
6677 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6678 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6679
6680 if (kvm_x86_ops->get_nmi_mask(vcpu))
6681 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6682 else
6683 kvm_x86_ops->set_nmi_mask(vcpu, true);
6684
6685 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6686 kvm_rip_write(vcpu, 0x8000);
6687
6688 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6689 kvm_x86_ops->set_cr0(vcpu, cr0);
6690 vcpu->arch.cr0 = cr0;
6691
6692 kvm_x86_ops->set_cr4(vcpu, 0);
6693
18c3626e
PB		 6694 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6695 dt.address = dt.size = 0;
6696 kvm_x86_ops->set_idt(vcpu, &dt);
6697
660a5d51
PB		 6698 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6699
6700 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6701 cs.base = vcpu->arch.smbase;
6702
6703 ds.selector = 0;
6704 ds.base = 0;
6705
6706 cs.limit = ds.limit = 0xffffffff;
6707 cs.type = ds.type = 0x3;
6708 cs.dpl = ds.dpl = 0;
6709 cs.db = ds.db = 0;
6710 cs.s = ds.s = 1;
6711 cs.l = ds.l = 0;
6712 cs.g = ds.g = 1;
6713 cs.avl = ds.avl = 0;
6714 cs.present = ds.present = 1;
6715 cs.unusable = ds.unusable = 0;
6716 cs.padding = ds.padding = 0;
6717
6718 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6719 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6720 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6721 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6722 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6723 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6724
d6321d49 6725 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6726 kvm_x86_ops->set_efer(vcpu, 0);
6727
6728 kvm_update_cpuid(vcpu);
6729 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6730}
6731
ee2cd4b7 6732static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6733{
6734 vcpu->arch.smi_pending = true;
6735 kvm_make_request(KVM_REQ_EVENT, vcpu);
6736}
6737
2860c4b1
PB		 6738void kvm_make_scan_ioapic_request(struct kvm *kvm)
6739{
6740 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6741}
6742
3d81bc7e 6743static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6744{
5c919412
AS		 6745 u64 eoi_exit_bitmap[4];
6746
3d81bc7e
YZ		 6747 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6748 return;
c7c9c56c 6749
6308630b 6750 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6751
b053b2ae 6752 if (irqchip_split(vcpu->kvm))
6308630b 6753 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6754 else {
76dfafd5 6755 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6756 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6757 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6758 }
5c919412
AS		 6759 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6760 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6761 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6762}
6763
a70656b6
RK		 6764static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6765{
6766 ++vcpu->stat.tlb_flush;
6767 kvm_x86_ops->tlb_flush(vcpu);
6768}
6769
4256f43f
TC		 6770void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6771{
c24ae0dc
TC		 6772 struct page *page = NULL;
6773
35754c98 6774 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6775 return;
6776
4256f43f
TC		 6777 if (!kvm_x86_ops->set_apic_access_page_addr)
6778 return;
6779
c24ae0dc 6780 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6781 if (is_error_page(page))
6782 return;
c24ae0dc
TC		 6783 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6784
6785 /*
6786 * Do not pin apic access page in memory, the MMU notifier
6787 * will call us again if it is migrated or swapped out.
6788 */
6789 put_page(page);
4256f43f
TC		 6790}
6791EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6792
9357d939 6793/*
362c698f 6794 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6795 * exiting to the userspace. Otherwise, the value will be returned to the
6796 * userspace.
6797 */
851ba692 6798static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6799{
6800 int r;
62a193ed
MG		 6801 bool req_int_win =
6802 dm_request_for_irq_injection(vcpu) &&
6803 kvm_cpu_accept_dm_intr(vcpu);
6804
730dca42 6805 bool req_immediate_exit = false;
b6c7a5dc 6806
2fa6e1e1 6807 if (kvm_request_pending(vcpu)) {
a8eeb04a 6808 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6809 kvm_mmu_unload(vcpu);
a8eeb04a 6810 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6811 __kvm_migrate_timers(vcpu);
d828199e
MT		 6812 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6813 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6814 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6815 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6816 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6817 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6818 if (unlikely(r))
6819 goto out;
6820 }
a8eeb04a 6821 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6822 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6823 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6824 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6825 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6826 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6827 r = 0;
6828 goto out;
6829 }
a8eeb04a 6830 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6831 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6832 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6833 r = 0;
6834 goto out;
6835 }
af585b92
GN		 6836 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6837 /* Page is swapped out. Do synthetic halt */
6838 vcpu->arch.apf.halted = true;
6839 r = 1;
6840 goto out;
6841 }
c9aaa895
GC		 6842 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6843 record_steal_time(vcpu);
64d60670
PB		 6844 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6845 process_smi(vcpu);
7460fb4a
AK		 6846 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6847 process_nmi(vcpu);
f5132b01 6848 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6849 kvm_pmu_handle_event(vcpu);
f5132b01 6850 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6851 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6852 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6853 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6854 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6855 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6856 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6857 vcpu->run->eoi.vector =
6858 vcpu->arch.pending_ioapic_eoi;
6859 r = 0;
6860 goto out;
6861 }
6862 }
3d81bc7e
YZ		 6863 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6864 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6865 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6866 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6867 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6868 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6869 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6870 r = 0;
6871 goto out;
6872 }
e516cebb
AS		 6873 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6874 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6875 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6876 r = 0;
6877 goto out;
6878 }
db397571
AS		 6879 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6880 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6881 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6882 r = 0;
6883 goto out;
6884 }
f3b138c5
AS		 6885
6886 /*
6887 * KVM_REQ_HV_STIMER has to be processed after
6888 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6889 * depend on the guest clock being up-to-date
6890 */
1f4b34f8
AS		 6891 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6892 kvm_hv_process_stimers(vcpu);
2f52d58c 6893 }
b93463aa 6894
b463a6f7 6895 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6896 ++vcpu->stat.req_event;
66450a21
JK		 6897 kvm_apic_accept_events(vcpu);
6898 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6899 r = 1;
6900 goto out;
6901 }
6902
b6b8a145
JK		 6903 if (inject_pending_event(vcpu, req_int_win) != 0)
6904 req_immediate_exit = true;
321c5658 6905 else {
cc3d967f 6906 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6907 *
cc3d967f
LP		 6908 * SMIs have three cases:
6909 * 1) They can be nested, and then there is nothing to
6910 * do here because RSM will cause a vmexit anyway.
6911 * 2) There is an ISA-specific reason why SMI cannot be
6912 * injected, and the moment when this changes can be
6913 * intercepted.
6914 * 3) Or the SMI can be pending because
6915 * inject_pending_event has completed the injection
6916 * of an IRQ or NMI from the previous vmexit, and
6917 * then we request an immediate exit to inject the
6918 * SMI.
c43203ca
PB		 6919 */
6920 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6921 if (!kvm_x86_ops->enable_smi_window(vcpu))
6922 req_immediate_exit = true;
321c5658
YS		 6923 if (vcpu->arch.nmi_pending)
6924 kvm_x86_ops->enable_nmi_window(vcpu);
6925 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6926 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6927 WARN_ON(vcpu->arch.exception.pending);
321c5658 6928 }
b463a6f7
AK		 6929
6930 if (kvm_lapic_enabled(vcpu)) {
6931 update_cr8_intercept(vcpu);
6932 kvm_lapic_sync_to_vapic(vcpu);
6933 }
6934 }
6935
d8368af8
AK		 6936 r = kvm_mmu_reload(vcpu);
6937 if (unlikely(r)) {
d905c069 6938 goto cancel_injection;
d8368af8
AK		 6939 }
6940
b6c7a5dc
HB		 6941 preempt_disable();
6942
6943 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6944 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6945
6946 /*
6947 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6948 * IPI are then delayed after guest entry, which ensures that they
6949 * result in virtual interrupt delivery.
6950 */
6951 local_irq_disable();
6b7e2d09
XG		 6952 vcpu->mode = IN_GUEST_MODE;
6953
01b71917
MT		 6954 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6955
0f127d12 6956 /*
b95234c8 6957 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6958 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6959 *
6960 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6961 * pairs with the memory barrier implicit in pi_test_and_set_on
6962 * (see vmx_deliver_posted_interrupt).
6963 *
6964 * 3) This also orders the write to mode from any reads to the page
6965 * tables done while the VCPU is running. Please see the comment
6966 * in kvm_flush_remote_tlbs.
6b7e2d09 6967 */
01b71917 6968 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6969
b95234c8
PB		 6970 /*
6971 * This handles the case where a posted interrupt was
6972 * notified with kvm_vcpu_kick.
6973 */
6974 if (kvm_lapic_enabled(vcpu)) {
6975 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6976 kvm_x86_ops->sync_pir_to_irr(vcpu);
6977 }
32f88400 6978
2fa6e1e1 6979 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6980 || need_resched() || signal_pending(current)) {
6b7e2d09 6981 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6982 smp_wmb();
6c142801
AK		 6983 local_irq_enable();
6984 preempt_enable();
01b71917 6985 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6986 r = 1;
d905c069 6987 goto cancel_injection;
6c142801
AK		 6988 }
6989
fc5b7f3b
DM		 6990 kvm_load_guest_xcr0(vcpu);
6991
c43203ca
PB		 6992 if (req_immediate_exit) {
6993 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6994 smp_send_reschedule(vcpu->cpu);
c43203ca 6995 }
d6185f20 6996
8b89fe1f
PB		 6997 trace_kvm_entry(vcpu->vcpu_id);
6998 wait_lapic_expire(vcpu);
6edaa530 6999 guest_enter_irqoff();
b6c7a5dc 7000
42dbaa5a 7001 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7002 set_debugreg(0, 7);
7003 set_debugreg(vcpu->arch.eff_db[0], 0);
7004 set_debugreg(vcpu->arch.eff_db[1], 1);
7005 set_debugreg(vcpu->arch.eff_db[2], 2);
7006 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7007 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7008 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7009 }
b6c7a5dc 7010
851ba692 7011 kvm_x86_ops->run(vcpu);
b6c7a5dc 7012
c77fb5fe
PB		 7013 /*
7014 * Do this here before restoring debug registers on the host. And
7015 * since we do this before handling the vmexit, a DR access vmexit
7016 * can (a) read the correct value of the debug registers, (b) set
7017 * KVM_DEBUGREG_WONT_EXIT again.
7018 */
7019 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7020 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7021 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7022 kvm_update_dr0123(vcpu);
7023 kvm_update_dr6(vcpu);
7024 kvm_update_dr7(vcpu);
7025 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7026 }
7027
24f1e32c
FW		 7028 /*
7029 * If the guest has used debug registers, at least dr7
7030 * will be disabled while returning to the host.
7031 * If we don't have active breakpoints in the host, we don't
7032 * care about the messed up debug address registers. But if
7033 * we have some of them active, restore the old state.
7034 */
59d8eb53 7035 if (hw_breakpoint_active())
24f1e32c 7036 hw_breakpoint_restore();
42dbaa5a 7037
4ba76538 7038 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7039
6b7e2d09 7040 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7041 smp_wmb();
a547c6db 7042
fc5b7f3b
DM		 7043 kvm_put_guest_xcr0(vcpu);
7044
a547c6db 7045 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7046
7047 ++vcpu->stat.exits;
7048
f2485b3e 7049 guest_exit_irqoff();
b6c7a5dc 7050
f2485b3e 7051 local_irq_enable();
b6c7a5dc
HB		 7052 preempt_enable();
7053
f656ce01 7054 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7055
b6c7a5dc
HB		 7056 /*
7057 * Profile KVM exit RIPs:
7058 */
7059 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7060 unsigned long rip = kvm_rip_read(vcpu);
7061 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7062 }
7063
cc578287
ZA		 7064 if (unlikely(vcpu->arch.tsc_always_catchup))
7065 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7066
5cfb1d5a
MT		 7067 if (vcpu->arch.apic_attention)
7068 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7069
618232e2 7070 vcpu->arch.gpa_available = false;
851ba692 7071 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7072 return r;
7073
7074cancel_injection:
7075 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7076 if (unlikely(vcpu->arch.apic_attention))
7077 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7078out:
7079 return r;
7080}
b6c7a5dc 7081
362c698f
PB		 7082static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7083{
bf9f6ac8
FW		 7084 if (!kvm_arch_vcpu_runnable(vcpu) &&
7085 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7086 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7087 kvm_vcpu_block(vcpu);
7088 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7089
7090 if (kvm_x86_ops->post_block)
7091 kvm_x86_ops->post_block(vcpu);
7092
9c8fd1ba
PB		 7093 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7094 return 1;
7095 }
362c698f
PB		 7096
7097 kvm_apic_accept_events(vcpu);
7098 switch(vcpu->arch.mp_state) {
7099 case KVM_MP_STATE_HALTED:
7100 vcpu->arch.pv.pv_unhalted = false;
7101 vcpu->arch.mp_state =
7102 KVM_MP_STATE_RUNNABLE;
7103 case KVM_MP_STATE_RUNNABLE:
7104 vcpu->arch.apf.halted = false;
7105 break;
7106 case KVM_MP_STATE_INIT_RECEIVED:
7107 break;
7108 default:
7109 return -EINTR;
7110 break;
7111 }
7112 return 1;
7113}
09cec754 7114
5d9bc648
PB		 7115static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7116{
0ad3bed6
PB		 7117 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7118 kvm_x86_ops->check_nested_events(vcpu, false);
7119
5d9bc648
PB		 7120 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7121 !vcpu->arch.apf.halted);
7122}
7123
362c698f 7124static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7125{
7126 int r;
f656ce01 7127 struct kvm *kvm = vcpu->kvm;
d7690175 7128
f656ce01 7129 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7130
362c698f 7131 for (;;) {
58f800d5 7132 if (kvm_vcpu_running(vcpu)) {
851ba692 7133 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7134 } else {
362c698f 7135 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7136 }
7137
09cec754
GN		 7138 if (r <= 0)
7139 break;
7140
72875d8a 7141 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7142 if (kvm_cpu_has_pending_timer(vcpu))
7143 kvm_inject_pending_timer_irqs(vcpu);
7144
782d422b
MG		 7145 if (dm_request_for_irq_injection(vcpu) &&
7146 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7147 r = 0;
7148 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7149 ++vcpu->stat.request_irq_exits;
362c698f 7150 break;
09cec754 7151 }
af585b92
GN		 7152
7153 kvm_check_async_pf_completion(vcpu);
7154
09cec754
GN		 7155 if (signal_pending(current)) {
7156 r = -EINTR;
851ba692 7157 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7158 ++vcpu->stat.signal_exits;
362c698f 7159 break;
09cec754
GN		 7160 }
7161 if (need_resched()) {
f656ce01 7162 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7163 cond_resched();
f656ce01 7164 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7165 }
b6c7a5dc
HB		 7166 }
7167
f656ce01 7168 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7169
7170 return r;
7171}
7172
716d51ab
GN		 7173static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7174{
7175 int r;
7176 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7177 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7178 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7179 if (r != EMULATE_DONE)
7180 return 0;
7181 return 1;
7182}
7183
7184static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7185{
7186 BUG_ON(!vcpu->arch.pio.count);
7187
7188 return complete_emulated_io(vcpu);
7189}
7190
f78146b0
AK		 7191/*
7192 * Implements the following, as a state machine:
7193 *
7194 * read:
7195 * for each fragment
87da7e66
XG		 7196 * for each mmio piece in the fragment
7197 * write gpa, len
7198 * exit
7199 * copy data
f78146b0
AK		 7200 * execute insn
7201 *
7202 * write:
7203 * for each fragment
87da7e66
XG		 7204 * for each mmio piece in the fragment
7205 * write gpa, len
7206 * copy data
7207 * exit
f78146b0 7208 */
716d51ab 7209static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7210{
7211 struct kvm_run *run = vcpu->run;
f78146b0 7212 struct kvm_mmio_fragment *frag;
87da7e66 7213 unsigned len;
5287f194 7214
716d51ab 7215 BUG_ON(!vcpu->mmio_needed);
5287f194 7216
716d51ab 7217 /* Complete previous fragment */
87da7e66
XG		 7218 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7219 len = min(8u, frag->len);
716d51ab 7220 if (!vcpu->mmio_is_write)
87da7e66
XG		 7221 memcpy(frag->data, run->mmio.data, len);
7222
7223 if (frag->len <= 8) {
7224 /* Switch to the next fragment. */
7225 frag++;
7226 vcpu->mmio_cur_fragment++;
7227 } else {
7228 /* Go forward to the next mmio piece. */
7229 frag->data += len;
7230 frag->gpa += len;
7231 frag->len -= len;
7232 }
7233
a08d3b3b 7234 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7235 vcpu->mmio_needed = 0;
0912c977
PB		 7236
7237 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7238 if (vcpu->mmio_is_write)
716d51ab
GN		 7239 return 1;
7240 vcpu->mmio_read_completed = 1;
7241 return complete_emulated_io(vcpu);
7242 }
87da7e66 7243
716d51ab
GN		 7244 run->exit_reason = KVM_EXIT_MMIO;
7245 run->mmio.phys_addr = frag->gpa;
7246 if (vcpu->mmio_is_write)
87da7e66
XG		 7247 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7248 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7249 run->mmio.is_write = vcpu->mmio_is_write;
7250 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7251 return 0;
5287f194
AK		 7252}
7253
716d51ab 7254
b6c7a5dc
HB		 7255int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7256{
c5bedc68 7257 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7258 int r;
7259 sigset_t sigsaved;
7260
2ce03d85 7261 fpu__initialize(fpu);
e5c30142 7262
ac9f6dc0
AK		 7263 if (vcpu->sigset_active)
7264 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7265
a4535290 7266 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7267 if (kvm_run->immediate_exit) {
7268 r = -EINTR;
7269 goto out;
7270 }
b6c7a5dc 7271 kvm_vcpu_block(vcpu);
66450a21 7272 kvm_apic_accept_events(vcpu);
72875d8a 7273 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7274 r = -EAGAIN;
a0595000
JS		 7275 if (signal_pending(current)) {
7276 r = -EINTR;
7277 vcpu->run->exit_reason = KVM_EXIT_INTR;
7278 ++vcpu->stat.signal_exits;
7279 }
ac9f6dc0 7280 goto out;
b6c7a5dc
HB		 7281 }
7282
b6c7a5dc 7283 /* re-sync apic's tpr */
35754c98 7284 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7285 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7286 r = -EINVAL;
7287 goto out;
7288 }
7289 }
b6c7a5dc 7290
716d51ab
GN		 7291 if (unlikely(vcpu->arch.complete_userspace_io)) {
7292 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7293 vcpu->arch.complete_userspace_io = NULL;
7294 r = cui(vcpu);
7295 if (r <= 0)
7296 goto out;
7297 } else
7298 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7299
460df4c1
PB		 7300 if (kvm_run->immediate_exit)
7301 r = -EINTR;
7302 else
7303 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7304
7305out:
f1d86e46 7306 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7307 if (vcpu->sigset_active)
7308 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7309
b6c7a5dc
HB		 7310 return r;
7311}
7312
7313int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7314{
7ae441ea
GN		 7315 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7316 /*
7317 * We are here if userspace calls get_regs() in the middle of
7318 * instruction emulation. Registers state needs to be copied
4a969980 7319 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7320 * that usually, but some bad designed PV devices (vmware
7321 * backdoor interface) need this to work
7322 */
dd856efa 7323 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7324 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7325 }
5fdbf976
MT		 7326 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7327 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7328 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7329 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7330 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7331 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7332 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7333 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7334#ifdef CONFIG_X86_64
5fdbf976
MT		 7335 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7336 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7337 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7338 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7339 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7340 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7341 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7342 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7343#endif
7344
5fdbf976 7345 regs->rip = kvm_rip_read(vcpu);
91586a3b 7346 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7347
b6c7a5dc
HB		 7348 return 0;
7349}
7350
7351int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7352{
7ae441ea
GN		 7353 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7354 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7355
5fdbf976
MT		 7356 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7357 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7358 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7359 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7360 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7361 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7362 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7363 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7364#ifdef CONFIG_X86_64
5fdbf976
MT		 7365 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7366 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7367 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7368 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7369 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7370 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7371 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7372 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7373#endif
7374
5fdbf976 7375 kvm_rip_write(vcpu, regs->rip);
91586a3b 7376 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7377
b4f14abd
JK		 7378 vcpu->arch.exception.pending = false;
7379
3842d135
AK		 7380 kvm_make_request(KVM_REQ_EVENT, vcpu);
7381
b6c7a5dc
HB		 7382 return 0;
7383}
7384
b6c7a5dc
HB		 7385void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7386{
7387 struct kvm_segment cs;
7388
3e6e0aab 7389 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7390 *db = cs.db;
7391 *l = cs.l;
7392}
7393EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7394
7395int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7396 struct kvm_sregs *sregs)
7397{
89a27f4d 7398 struct desc_ptr dt;
b6c7a5dc 7399
3e6e0aab
GT		 7400 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7401 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7402 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7403 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7404 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7405 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7406
3e6e0aab
GT		 7407 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7408 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7409
7410 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7411 sregs->idt.limit = dt.size;
7412 sregs->idt.base = dt.address;
b6c7a5dc 7413 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7414 sregs->gdt.limit = dt.size;
7415 sregs->gdt.base = dt.address;
b6c7a5dc 7416
4d4ec087 7417 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7418 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7419 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7420 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7421 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7422 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7423 sregs->apic_base = kvm_get_apic_base(vcpu);
7424
923c61bb 7425 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7426
36752c9b 7427 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7428 set_bit(vcpu->arch.interrupt.nr,
7429 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7430
b6c7a5dc
HB		 7431 return 0;
7432}
7433
62d9f0db
MT		 7434int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7435 struct kvm_mp_state *mp_state)
7436{
66450a21 7437 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7438 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7439 vcpu->arch.pv.pv_unhalted)
7440 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7441 else
7442 mp_state->mp_state = vcpu->arch.mp_state;
7443
62d9f0db
MT		 7444 return 0;
7445}
7446
7447int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7448 struct kvm_mp_state *mp_state)
7449{
bce87cce 7450 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7451 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7452 return -EINVAL;
7453
28bf2888
DH		 7454 /* INITs are latched while in SMM */
7455 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7456 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7457 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7458 return -EINVAL;
7459
66450a21
JK		 7460 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7461 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7462 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7463 } else
7464 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7465 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7466 return 0;
7467}
7468
7f3d35fd
KW		 7469int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7470 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7471{
9d74191a 7472 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7473 int ret;
e01c2426 7474
8ec4722d 7475 init_emulate_ctxt(vcpu);
c697518a 7476
7f3d35fd 7477 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7478 has_error_code, error_code);
c697518a 7479
c697518a 7480 if (ret)
19d04437 7481 return EMULATE_FAIL;
37817f29 7482
9d74191a
TY		 7483 kvm_rip_write(vcpu, ctxt->eip);
7484 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7485 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7486 return EMULATE_DONE;
37817f29
IE		 7487}
7488EXPORT_SYMBOL_GPL(kvm_task_switch);
7489
b6c7a5dc
HB		 7490int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7491 struct kvm_sregs *sregs)
7492{
58cb628d 7493 struct msr_data apic_base_msr;
b6c7a5dc 7494 int mmu_reset_needed = 0;
63f42e02 7495 int pending_vec, max_bits, idx;
89a27f4d 7496 struct desc_ptr dt;
b6c7a5dc 7497
d6321d49
RK		 7498 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7499 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7500 return -EINVAL;
7501
d3802286
JM		 7502 apic_base_msr.data = sregs->apic_base;
7503 apic_base_msr.host_initiated = true;
7504 if (kvm_set_apic_base(vcpu, &apic_base_msr))
6d1068b3
PM		 7505 return -EINVAL;
7506
89a27f4d
GN		 7507 dt.size = sregs->idt.limit;
7508 dt.address = sregs->idt.base;
b6c7a5dc 7509 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7510 dt.size = sregs->gdt.limit;
7511 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7512 kvm_x86_ops->set_gdt(vcpu, &dt);
7513
ad312c7c 7514 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7515 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7516 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7517 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7518
2d3ad1f4 7519 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7520
f6801dff 7521 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7522 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7523
4d4ec087 7524 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7525 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7526 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7527
fc78f519 7528 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7529 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7530 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7531 kvm_update_cpuid(vcpu);
63f42e02
XG		 7532
7533 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7534 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7535 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7536 mmu_reset_needed = 1;
7537 }
63f42e02 7538 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7539
7540 if (mmu_reset_needed)
7541 kvm_mmu_reset_context(vcpu);
7542
a50abc3b 7543 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7544 pending_vec = find_first_bit(
7545 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7546 if (pending_vec < max_bits) {
66fd3f7f 7547 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7548 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7549 }
7550
3e6e0aab
GT		 7551 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7552 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7553 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7554 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7555 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7556 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7557
3e6e0aab
GT		 7558 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7559 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7560
5f0269f5
ME		 7561 update_cr8_intercept(vcpu);
7562
9c3e4aab 7563 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7564 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7565 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7566 !is_protmode(vcpu))
9c3e4aab
MT		 7567 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7568
3842d135
AK		 7569 kvm_make_request(KVM_REQ_EVENT, vcpu);
7570
b6c7a5dc
HB		 7571 return 0;
7572}
7573
d0bfb940
JK		 7574int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7575 struct kvm_guest_debug *dbg)
b6c7a5dc 7576{
355be0b9 7577 unsigned long rflags;
ae675ef0 7578 int i, r;
b6c7a5dc 7579
4f926bf2
JK		 7580 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7581 r = -EBUSY;
7582 if (vcpu->arch.exception.pending)
2122ff5e 7583 goto out;
4f926bf2
JK		 7584 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7585 kvm_queue_exception(vcpu, DB_VECTOR);
7586 else
7587 kvm_queue_exception(vcpu, BP_VECTOR);
7588 }
7589
91586a3b
JK		 7590 /*
7591 * Read rflags as long as potentially injected trace flags are still
7592 * filtered out.
7593 */
7594 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7595
7596 vcpu->guest_debug = dbg->control;
7597 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7598 vcpu->guest_debug = 0;
7599
7600 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7601 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7602 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7603 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7604 } else {
7605 for (i = 0; i < KVM_NR_DB_REGS; i++)
7606 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7607 }
c8639010 7608 kvm_update_dr7(vcpu);
ae675ef0 7609
f92653ee
JK		 7610 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7611 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7612 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7613
91586a3b
JK		 7614 /*
7615 * Trigger an rflags update that will inject or remove the trace
7616 * flags.
7617 */
7618 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7619
a96036b8 7620 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7621
4f926bf2 7622 r = 0;
d0bfb940 7623
2122ff5e 7624out:
b6c7a5dc
HB		 7625
7626 return r;
7627}
7628
8b006791
ZX		 7629/*
7630 * Translate a guest virtual address to a guest physical address.
7631 */
7632int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7633 struct kvm_translation *tr)
7634{
7635 unsigned long vaddr = tr->linear_address;
7636 gpa_t gpa;
f656ce01 7637 int idx;
8b006791 7638
f656ce01 7639 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7640 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7641 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7642 tr->physical_address = gpa;
7643 tr->valid = gpa != UNMAPPED_GVA;
7644 tr->writeable = 1;
7645 tr->usermode = 0;
8b006791
ZX		 7646
7647 return 0;
7648}
7649
d0752060
HB		 7650int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7651{
c47ada30 7652 struct fxregs_state *fxsave =
7366ed77 7653 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7654
d0752060
HB		 7655 memcpy(fpu->fpr, fxsave->st_space, 128);
7656 fpu->fcw = fxsave->cwd;
7657 fpu->fsw = fxsave->swd;
7658 fpu->ftwx = fxsave->twd;
7659 fpu->last_opcode = fxsave->fop;
7660 fpu->last_ip = fxsave->rip;
7661 fpu->last_dp = fxsave->rdp;
7662 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7663
d0752060
HB		 7664 return 0;
7665}
7666
7667int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7668{
c47ada30 7669 struct fxregs_state *fxsave =
7366ed77 7670 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7671
d0752060
HB		 7672 memcpy(fxsave->st_space, fpu->fpr, 128);
7673 fxsave->cwd = fpu->fcw;
7674 fxsave->swd = fpu->fsw;
7675 fxsave->twd = fpu->ftwx;
7676 fxsave->fop = fpu->last_opcode;
7677 fxsave->rip = fpu->last_ip;
7678 fxsave->rdp = fpu->last_dp;
7679 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7680
d0752060
HB		 7681 return 0;
7682}
7683
0ee6a517 7684static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7685{
bf935b0b 7686 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7687 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7688 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7689 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7690
2acf923e
DC		 7691 /*
7692 * Ensure guest xcr0 is valid for loading
7693 */
d91cab78 7694 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7695
ad312c7c 7696 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7697}
d0752060
HB		 7698
7699void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7700{
2608d7a1 7701 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7702 return;
7703
2acf923e
DC		 7704 /*
7705 * Restore all possible states in the guest,
7706 * and assume host would use all available bits.
7707 * Guest xcr0 would be loaded later.
7708 */
d0752060 7709 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7710 __kernel_fpu_begin();
38cfd5e3
PB		 7711 /* PKRU is separately restored in kvm_x86_ops->run. */
7712 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7713 ~XFEATURE_MASK_PKRU);
0c04851c 7714 trace_kvm_fpu(1);
d0752060 7715}
d0752060
HB		 7716
7717void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7718{
3d42de25 7719 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7720 return;
7721
7722 vcpu->guest_fpu_loaded = 0;
4f836347 7723 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7724 __kernel_fpu_end();
f096ed85 7725 ++vcpu->stat.fpu_reload;
0c04851c 7726 trace_kvm_fpu(0);
d0752060 7727}
e9b11c17
ZX		 7728
7729void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7730{
bd768e14
IY		 7731 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7732
12f9a48f 7733 kvmclock_reset(vcpu);
7f1ea208 7734
e9b11c17 7735 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7736 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7737}
7738
7739struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7740 unsigned int id)
7741{
c447e76b
LL		 7742 struct kvm_vcpu *vcpu;
7743
6755bae8
ZA		 7744 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7745 printk_once(KERN_WARNING
7746 "kvm: SMP vm created on host with unstable TSC; "
7747 "guest TSC will not be reliable\n");
c447e76b
LL		 7748
7749 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7750
c447e76b 7751 return vcpu;
26e5215f 7752}
e9b11c17 7753
26e5215f
AK		 7754int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7755{
7756 int r;
e9b11c17 7757
19efffa2 7758 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7759 r = vcpu_load(vcpu);
7760 if (r)
7761 return r;
d28bc9dd 7762 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7763 kvm_mmu_setup(vcpu);
e9b11c17 7764 vcpu_put(vcpu);
26e5215f 7765 return r;
e9b11c17
ZX		 7766}
7767
31928aa5 7768void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7769{
8fe8ab46 7770 struct msr_data msr;
332967a3 7771 struct kvm *kvm = vcpu->kvm;
42897d86 7772
d3457c87
RK		 7773 kvm_hv_vcpu_postcreate(vcpu);
7774
31928aa5
DD		 7775 if (vcpu_load(vcpu))
7776 return;
8fe8ab46
WA		 7777 msr.data = 0x0;
7778 msr.index = MSR_IA32_TSC;
7779 msr.host_initiated = true;
7780 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7781 vcpu_put(vcpu);
7782
630994b3
MT		 7783 if (!kvmclock_periodic_sync)
7784 return;
7785
332967a3
AJ		 7786 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7787 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7788}
7789
d40ccc62 7790void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7791{
9fc77441 7792 int r;
344d9588
GN		 7793 vcpu->arch.apf.msr_val = 0;
7794
9fc77441
MT		 7795 r = vcpu_load(vcpu);
7796 BUG_ON(r);
e9b11c17
ZX		 7797 kvm_mmu_unload(vcpu);
7798 vcpu_put(vcpu);
7799
7800 kvm_x86_ops->vcpu_free(vcpu);
7801}
7802
d28bc9dd 7803void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7804{
e69fab5d
PB		 7805 vcpu->arch.hflags = 0;
7806
c43203ca 7807 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7808 atomic_set(&vcpu->arch.nmi_queued, 0);
7809 vcpu->arch.nmi_pending = 0;
448fa4a9 7810 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7811 kvm_clear_interrupt_queue(vcpu);
7812 kvm_clear_exception_queue(vcpu);
664f8e26 7813 vcpu->arch.exception.pending = false;
448fa4a9 7814
42dbaa5a 7815 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7816 kvm_update_dr0123(vcpu);
6f43ed01 7817 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7818 kvm_update_dr6(vcpu);
42dbaa5a 7819 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7820 kvm_update_dr7(vcpu);
42dbaa5a 7821
1119022c
NA		 7822 vcpu->arch.cr2 = 0;
7823
3842d135 7824 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7825 vcpu->arch.apf.msr_val = 0;
c9aaa895 7826 vcpu->arch.st.msr_val = 0;
3842d135 7827
12f9a48f
GC		 7828 kvmclock_reset(vcpu);
7829
af585b92
GN		 7830 kvm_clear_async_pf_completion_queue(vcpu);
7831 kvm_async_pf_hash_reset(vcpu);
7832 vcpu->arch.apf.halted = false;
3842d135 7833
a554d207
WL		 7834 if (kvm_mpx_supported()) {
7835 void *mpx_state_buffer;
7836
7837 /*
7838 * To avoid have the INIT path from kvm_apic_has_events() that be
7839 * called with loaded FPU and does not let userspace fix the state.
7840 */
7841 kvm_put_guest_fpu(vcpu);
7842 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7843 XFEATURE_MASK_BNDREGS);
7844 if (mpx_state_buffer)
7845 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7846 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7847 XFEATURE_MASK_BNDCSR);
7848 if (mpx_state_buffer)
7849 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
7850 }
7851
64d60670 7852 if (!init_event) {
d28bc9dd 7853 kvm_pmu_reset(vcpu);
64d60670 7854 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7855
7856 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7857 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7858
7859 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7860 }
f5132b01 7861
66f7b72e
JS		 7862 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7863 vcpu->arch.regs_avail = ~0;
7864 vcpu->arch.regs_dirty = ~0;
7865
a554d207
WL		 7866 vcpu->arch.ia32_xss = 0;
7867
d28bc9dd 7868 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7869}
7870
2b4a273b 7871void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7872{
7873 struct kvm_segment cs;
7874
7875 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7876 cs.selector = vector << 8;
7877 cs.base = vector << 12;
7878 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7879 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7880}
7881
13a34e06 7882int kvm_arch_hardware_enable(void)
e9b11c17 7883{
ca84d1a2
ZA		 7884 struct kvm *kvm;
7885 struct kvm_vcpu *vcpu;
7886 int i;
0dd6a6ed
ZA		 7887 int ret;
7888 u64 local_tsc;
7889 u64 max_tsc = 0;
7890 bool stable, backwards_tsc = false;
18863bdd
AK		 7891
7892 kvm_shared_msr_cpu_online();
13a34e06 7893 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7894 if (ret != 0)
7895 return ret;
7896
4ea1636b 7897 local_tsc = rdtsc();
0dd6a6ed
ZA		 7898 stable = !check_tsc_unstable();
7899 list_for_each_entry(kvm, &vm_list, vm_list) {
7900 kvm_for_each_vcpu(i, vcpu, kvm) {
7901 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7902 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7903 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7904 backwards_tsc = true;
7905 if (vcpu->arch.last_host_tsc > max_tsc)
7906 max_tsc = vcpu->arch.last_host_tsc;
7907 }
7908 }
7909 }
7910
7911 /*
7912 * Sometimes, even reliable TSCs go backwards. This happens on
7913 * platforms that reset TSC during suspend or hibernate actions, but
7914 * maintain synchronization. We must compensate. Fortunately, we can
7915 * detect that condition here, which happens early in CPU bringup,
7916 * before any KVM threads can be running. Unfortunately, we can't
7917 * bring the TSCs fully up to date with real time, as we aren't yet far
7918 * enough into CPU bringup that we know how much real time has actually
108b249c 7919 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7920 * variables that haven't been updated yet.
7921 *
7922 * So we simply find the maximum observed TSC above, then record the
7923 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7924 * the adjustment will be applied. Note that we accumulate
7925 * adjustments, in case multiple suspend cycles happen before some VCPU
7926 * gets a chance to run again. In the event that no KVM threads get a
7927 * chance to run, we will miss the entire elapsed period, as we'll have
7928 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7929 * loose cycle time. This isn't too big a deal, since the loss will be
7930 * uniform across all VCPUs (not to mention the scenario is extremely
7931 * unlikely). It is possible that a second hibernate recovery happens
7932 * much faster than a first, causing the observed TSC here to be
7933 * smaller; this would require additional padding adjustment, which is
7934 * why we set last_host_tsc to the local tsc observed here.
7935 *
7936 * N.B. - this code below runs only on platforms with reliable TSC,
7937 * as that is the only way backwards_tsc is set above. Also note
7938 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7939 * have the same delta_cyc adjustment applied if backwards_tsc
7940 * is detected. Note further, this adjustment is only done once,
7941 * as we reset last_host_tsc on all VCPUs to stop this from being
7942 * called multiple times (one for each physical CPU bringup).
7943 *
4a969980 7944 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7945 * will be compensated by the logic in vcpu_load, which sets the TSC to
7946 * catchup mode. This will catchup all VCPUs to real time, but cannot
7947 * guarantee that they stay in perfect synchronization.
7948 */
7949 if (backwards_tsc) {
7950 u64 delta_cyc = max_tsc - local_tsc;
7951 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7952 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7953 kvm_for_each_vcpu(i, vcpu, kvm) {
7954 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7955 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7956 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7957 }
7958
7959 /*
7960 * We have to disable TSC offset matching.. if you were
7961 * booting a VM while issuing an S4 host suspend....
7962 * you may have some problem. Solving this issue is
7963 * left as an exercise to the reader.
7964 */
7965 kvm->arch.last_tsc_nsec = 0;
7966 kvm->arch.last_tsc_write = 0;
7967 }
7968
7969 }
7970 return 0;
e9b11c17
ZX		 7971}
7972
13a34e06 7973void kvm_arch_hardware_disable(void)
e9b11c17 7974{
13a34e06
RK		 7975 kvm_x86_ops->hardware_disable();
7976 drop_user_return_notifiers();
e9b11c17
ZX		 7977}
7978
7979int kvm_arch_hardware_setup(void)
7980{
9e9c3fe4
NA		 7981 int r;
7982
7983 r = kvm_x86_ops->hardware_setup();
7984 if (r != 0)
7985 return r;
7986
35181e86
HZ		 7987 if (kvm_has_tsc_control) {
7988 /*
7989 * Make sure the user can only configure tsc_khz values that
7990 * fit into a signed integer.
7991 * A min value is not calculated needed because it will always
7992 * be 1 on all machines.
7993 */
7994 u64 max = min(0x7fffffffULL,
7995 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7996 kvm_max_guest_tsc_khz = max;
7997
ad721883 7998 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7999 }
ad721883 8000
9e9c3fe4
NA		 8001 kvm_init_msr_list();
8002 return 0;
e9b11c17
ZX		 8003}
8004
8005void kvm_arch_hardware_unsetup(void)
8006{
8007 kvm_x86_ops->hardware_unsetup();
8008}
8009
8010void kvm_arch_check_processor_compat(void *rtn)
8011{
8012 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8013}
8014
8015bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8016{
8017 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8018}
8019EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8020
8021bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8022{
8023 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8024}
8025
54e9818f 8026struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8027EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8028
e9b11c17
ZX		 8029int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8030{
8031 struct page *page;
e9b11c17
ZX		 8032 int r;
8033
b2a05fef 8034 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8035 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8036 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8037 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8038 else
a4535290 8039 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8040
8041 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8042 if (!page) {
8043 r = -ENOMEM;
8044 goto fail;
8045 }
ad312c7c 8046 vcpu->arch.pio_data = page_address(page);
e9b11c17 8047
cc578287 8048 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8049
e9b11c17
ZX		 8050 r = kvm_mmu_create(vcpu);
8051 if (r < 0)
8052 goto fail_free_pio_data;
8053
26de7988 8054 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8055 r = kvm_create_lapic(vcpu);
8056 if (r < 0)
8057 goto fail_mmu_destroy;
54e9818f
GN		 8058 } else
8059 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8060
890ca9ae
HY		 8061 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8062 GFP_KERNEL);
8063 if (!vcpu->arch.mce_banks) {
8064 r = -ENOMEM;
443c39bc 8065 goto fail_free_lapic;
890ca9ae
HY		 8066 }
8067 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8068
f1797359
WY		 8069 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8070 r = -ENOMEM;
f5f48ee1 8071 goto fail_free_mce_banks;
f1797359 8072 }
f5f48ee1 8073
0ee6a517 8074 fx_init(vcpu);
66f7b72e 8075
4344ee98 8076 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8077
5a4f55cd
EK		 8078 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8079
74545705
RK		 8080 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8081
af585b92 8082 kvm_async_pf_hash_reset(vcpu);
f5132b01 8083 kvm_pmu_init(vcpu);
af585b92 8084
1c1a9ce9 8085 vcpu->arch.pending_external_vector = -1;
de63ad4c 8086 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8087
5c919412
AS		 8088 kvm_hv_vcpu_init(vcpu);
8089
e9b11c17 8090 return 0;
0ee6a517 8091
f5f48ee1
SY		 8092fail_free_mce_banks:
8093 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8094fail_free_lapic:
8095 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8096fail_mmu_destroy:
8097 kvm_mmu_destroy(vcpu);
8098fail_free_pio_data:
ad312c7c 8099 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8100fail:
8101 return r;
8102}
8103
8104void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8105{
f656ce01
MT		 8106 int idx;
8107
1f4b34f8 8108 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8109 kvm_pmu_destroy(vcpu);
36cb93fd 8110 kfree(vcpu->arch.mce_banks);
e9b11c17 8111 kvm_free_lapic(vcpu);
f656ce01 8112 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8113 kvm_mmu_destroy(vcpu);
f656ce01 8114 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8115 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8116 if (!lapic_in_kernel(vcpu))
54e9818f 8117 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8118}
d19a9cd2 8119
e790d9ef
RK		 8120void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8121{
ae97a3b8 8122 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8123}
8124
e08b9637 8125int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8126{
e08b9637
CO		 8127 if (type)
8128 return -EINVAL;
8129
6ef768fa 8130 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8131 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8132 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8133 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8134 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8135
5550af4d
SY		 8136 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8137 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8138 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8139 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8140 &kvm->arch.irq_sources_bitmap);
5550af4d 8141
038f8c11 8142 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8143 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8144 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8145 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8146
108b249c 8147 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8148 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8149
7e44e449 8150 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8151 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8152
0eb05bf2 8153 kvm_page_track_init(kvm);
13d268ca 8154 kvm_mmu_init_vm(kvm);
0eb05bf2 8155
03543133
SS		 8156 if (kvm_x86_ops->vm_init)
8157 return kvm_x86_ops->vm_init(kvm);
8158
d89f5eff 8159 return 0;
d19a9cd2
ZX		 8160}
8161
8162static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8163{
9fc77441
MT		 8164 int r;
8165 r = vcpu_load(vcpu);
8166 BUG_ON(r);
d19a9cd2
ZX		 8167 kvm_mmu_unload(vcpu);
8168 vcpu_put(vcpu);
8169}
8170
8171static void kvm_free_vcpus(struct kvm *kvm)
8172{
8173 unsigned int i;
988a2cae 8174 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8175
8176 /*
8177 * Unpin any mmu pages first.
8178 */
af585b92
GN		 8179 kvm_for_each_vcpu(i, vcpu, kvm) {
8180 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8181 kvm_unload_vcpu_mmu(vcpu);
af585b92 8182 }
988a2cae
GN		 8183 kvm_for_each_vcpu(i, vcpu, kvm)
8184 kvm_arch_vcpu_free(vcpu);
8185
8186 mutex_lock(&kvm->lock);
8187 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8188 kvm->vcpus[i] = NULL;
d19a9cd2 8189
988a2cae
GN		 8190 atomic_set(&kvm->online_vcpus, 0);
8191 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8192}
8193
ad8ba2cd
SY		 8194void kvm_arch_sync_events(struct kvm *kvm)
8195{
332967a3 8196 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8197 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8198 kvm_free_pit(kvm);
ad8ba2cd
SY		 8199}
8200
1d8007bd 8201int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8202{
8203 int i, r;
25188b99 8204 unsigned long hva;
f0d648bd
PB		 8205 struct kvm_memslots *slots = kvm_memslots(kvm);
8206 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8207
8208 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8209 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8210 return -EINVAL;
9da0e4d5 8211
f0d648bd
PB		 8212 slot = id_to_memslot(slots, id);
8213 if (size) {
b21629da 8214 if (slot->npages)
f0d648bd
PB		 8215 return -EEXIST;
8216
8217 /*
8218 * MAP_SHARED to prevent internal slot pages from being moved
8219 * by fork()/COW.
8220 */
8221 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8222 MAP_SHARED | MAP_ANONYMOUS, 0);
8223 if (IS_ERR((void *)hva))
8224 return PTR_ERR((void *)hva);
8225 } else {
8226 if (!slot->npages)
8227 return 0;
8228
8229 hva = 0;
8230 }
8231
8232 old = *slot;
9da0e4d5 8233 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8234 struct kvm_userspace_memory_region m;
9da0e4d5 8235
1d8007bd
PB		 8236 m.slot = id | (i << 16);
8237 m.flags = 0;
8238 m.guest_phys_addr = gpa;
f0d648bd 8239 m.userspace_addr = hva;
1d8007bd 8240 m.memory_size = size;
9da0e4d5
PB		 8241 r = __kvm_set_memory_region(kvm, &m);
8242 if (r < 0)
8243 return r;
8244 }
8245
f0d648bd
PB		 8246 if (!size) {
8247 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8248 WARN_ON(r < 0);
8249 }
8250
9da0e4d5
PB		 8251 return 0;
8252}
8253EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8254
1d8007bd 8255int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8256{
8257 int r;
8258
8259 mutex_lock(&kvm->slots_lock);
1d8007bd 8260 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8261 mutex_unlock(&kvm->slots_lock);
8262
8263 return r;
8264}
8265EXPORT_SYMBOL_GPL(x86_set_memory_region);
8266
d19a9cd2
ZX		 8267void kvm_arch_destroy_vm(struct kvm *kvm)
8268{
27469d29
AH		 8269 if (current->mm == kvm->mm) {
8270 /*
8271 * Free memory regions allocated on behalf of userspace,
8272 * unless the the memory map has changed due to process exit
8273 * or fd copying.
8274 */
1d8007bd
PB		 8275 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8276 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8277 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8278 }
03543133
SS		 8279 if (kvm_x86_ops->vm_destroy)
8280 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8281 kvm_pic_destroy(kvm);
8282 kvm_ioapic_destroy(kvm);
d19a9cd2 8283 kvm_free_vcpus(kvm);
af1bae54 8284 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8285 kvm_mmu_uninit_vm(kvm);
2beb6dad 8286 kvm_page_track_cleanup(kvm);
d19a9cd2 8287}
0de10343 8288
5587027c 8289void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8290 struct kvm_memory_slot *dont)
8291{
8292 int i;
8293
d89cc617
TY		 8294 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8295 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8296 kvfree(free->arch.rmap[i]);
d89cc617 8297 free->arch.rmap[i] = NULL;
77d11309 8298 }
d89cc617
TY		 8299 if (i == 0)
8300 continue;
8301
8302 if (!dont || free->arch.lpage_info[i - 1] !=
8303 dont->arch.lpage_info[i - 1]) {
548ef284 8304 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8305 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8306 }
8307 }
21ebbeda
XG		 8308
8309 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8310}
8311
5587027c
AK		 8312int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8313 unsigned long npages)
db3fe4eb
TY		 8314{
8315 int i;
8316
d89cc617 8317 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8318 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8319 unsigned long ugfn;
8320 int lpages;
d89cc617 8321 int level = i + 1;
db3fe4eb
TY		 8322
8323 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8324 slot->base_gfn, level) + 1;
8325
d89cc617 8326 slot->arch.rmap[i] =
a7c3e901 8327 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8328 if (!slot->arch.rmap[i])
77d11309 8329 goto out_free;
d89cc617
TY		 8330 if (i == 0)
8331 continue;
77d11309 8332
a7c3e901 8333 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8334 if (!linfo)
db3fe4eb
TY		 8335 goto out_free;
8336
92f94f1e
XG		 8337 slot->arch.lpage_info[i - 1] = linfo;
8338
db3fe4eb 8339 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8340 linfo[0].disallow_lpage = 1;
db3fe4eb 8341 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8342 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8343 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8344 /*
8345 * If the gfn and userspace address are not aligned wrt each
8346 * other, or if explicitly asked to, disable large page
8347 * support for this slot
8348 */
8349 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8350 !kvm_largepages_enabled()) {
8351 unsigned long j;
8352
8353 for (j = 0; j < lpages; ++j)
92f94f1e 8354 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8355 }
8356 }
8357
21ebbeda
XG		 8358 if (kvm_page_track_create_memslot(slot, npages))
8359 goto out_free;
8360
db3fe4eb
TY		 8361 return 0;
8362
8363out_free:
d89cc617 8364 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8365 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8366 slot->arch.rmap[i] = NULL;
8367 if (i == 0)
8368 continue;
8369
548ef284 8370 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8371 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8372 }
8373 return -ENOMEM;
8374}
8375
15f46015 8376void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8377{
e6dff7d1
TY		 8378 /*
8379 * memslots->generation has been incremented.
8380 * mmio generation may have reached its maximum value.
8381 */
54bf36aa 8382 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8383}
8384
f7784b8e
MT		 8385int kvm_arch_prepare_memory_region(struct kvm *kvm,
8386 struct kvm_memory_slot *memslot,
09170a49 8387 const struct kvm_userspace_memory_region *mem,
7b6195a9 8388 enum kvm_mr_change change)
0de10343 8389{
f7784b8e
MT		 8390 return 0;
8391}
8392
88178fd4
KH		 8393static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8394 struct kvm_memory_slot *new)
8395{
8396 /* Still write protect RO slot */
8397 if (new->flags & KVM_MEM_READONLY) {
8398 kvm_mmu_slot_remove_write_access(kvm, new);
8399 return;
8400 }
8401
8402 /*
8403 * Call kvm_x86_ops dirty logging hooks when they are valid.
8404 *
8405 * kvm_x86_ops->slot_disable_log_dirty is called when:
8406 *
8407 * - KVM_MR_CREATE with dirty logging is disabled
8408 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8409 *
8410 * The reason is, in case of PML, we need to set D-bit for any slots
8411 * with dirty logging disabled in order to eliminate unnecessary GPA
8412 * logging in PML buffer (and potential PML buffer full VMEXT). This
8413 * guarantees leaving PML enabled during guest's lifetime won't have
8414 * any additonal overhead from PML when guest is running with dirty
8415 * logging disabled for memory slots.
8416 *
8417 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8418 * to dirty logging mode.
8419 *
8420 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8421 *
8422 * In case of write protect:
8423 *
8424 * Write protect all pages for dirty logging.
8425 *
8426 * All the sptes including the large sptes which point to this
8427 * slot are set to readonly. We can not create any new large
8428 * spte on this slot until the end of the logging.
8429 *
8430 * See the comments in fast_page_fault().
8431 */
8432 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8433 if (kvm_x86_ops->slot_enable_log_dirty)
8434 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8435 else
8436 kvm_mmu_slot_remove_write_access(kvm, new);
8437 } else {
8438 if (kvm_x86_ops->slot_disable_log_dirty)
8439 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8440 }
8441}
8442
f7784b8e 8443void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8444 const struct kvm_userspace_memory_region *mem,
8482644a 8445 const struct kvm_memory_slot *old,
f36f3f28 8446 const struct kvm_memory_slot *new,
8482644a 8447 enum kvm_mr_change change)
f7784b8e 8448{
8482644a 8449 int nr_mmu_pages = 0;
f7784b8e 8450
48c0e4e9
XG		 8451 if (!kvm->arch.n_requested_mmu_pages)
8452 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8453
48c0e4e9 8454 if (nr_mmu_pages)
0de10343 8455 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8456
3ea3b7fa
WL		 8457 /*
8458 * Dirty logging tracks sptes in 4k granularity, meaning that large
8459 * sptes have to be split. If live migration is successful, the guest
8460 * in the source machine will be destroyed and large sptes will be
8461 * created in the destination. However, if the guest continues to run
8462 * in the source machine (for example if live migration fails), small
8463 * sptes will remain around and cause bad performance.
8464 *
8465 * Scan sptes if dirty logging has been stopped, dropping those
8466 * which can be collapsed into a single large-page spte. Later
8467 * page faults will create the large-page sptes.
8468 */
8469 if ((change != KVM_MR_DELETE) &&
8470 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8471 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8472 kvm_mmu_zap_collapsible_sptes(kvm, new);
8473
c972f3b1 8474 /*
88178fd4 8475 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8476 *
88178fd4
KH		 8477 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8478 * been zapped so no dirty logging staff is needed for old slot. For
8479 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8480 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8481 *
8482 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8483 */
88178fd4 8484 if (change != KVM_MR_DELETE)
f36f3f28 8485 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8486}
1d737c8a 8487
2df72e9b 8488void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8489{
6ca18b69 8490 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8491}
8492
2df72e9b
MT		 8493void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8494 struct kvm_memory_slot *slot)
8495{
ae7cd873 8496 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8497}
8498
5d9bc648
PB		 8499static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8500{
8501 if (!list_empty_careful(&vcpu->async_pf.done))
8502 return true;
8503
8504 if (kvm_apic_has_events(vcpu))
8505 return true;
8506
8507 if (vcpu->arch.pv.pv_unhalted)
8508 return true;
8509
a5f01f8e
WL		 8510 if (vcpu->arch.exception.pending)
8511 return true;
8512
47a66eed
Z		 8513 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8514 (vcpu->arch.nmi_pending &&
8515 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8516 return true;
8517
47a66eed
Z		 8518 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8519 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8520 return true;
8521
5d9bc648
PB		 8522 if (kvm_arch_interrupt_allowed(vcpu) &&
8523 kvm_cpu_has_interrupt(vcpu))
8524 return true;
8525
1f4b34f8
AS		 8526 if (kvm_hv_has_stimer_pending(vcpu))
8527 return true;
8528
5d9bc648
PB		 8529 return false;
8530}
8531
1d737c8a
ZX		 8532int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8533{
5d9bc648 8534 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8535}
5736199a 8536
199b5763
LM		 8537bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8538{
de63ad4c 8539 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8540}
8541
b6d33834 8542int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8543{
b6d33834 8544 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8545}
78646121
GN		 8546
8547int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8548{
8549 return kvm_x86_ops->interrupt_allowed(vcpu);
8550}
229456fc 8551
82b32774 8552unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8553{
82b32774
NA		 8554 if (is_64_bit_mode(vcpu))
8555 return kvm_rip_read(vcpu);
8556 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8557 kvm_rip_read(vcpu));
8558}
8559EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8560
82b32774
NA		 8561bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8562{
8563 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8564}
8565EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8566
94fe45da
JK		 8567unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8568{
8569 unsigned long rflags;
8570
8571 rflags = kvm_x86_ops->get_rflags(vcpu);
8572 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8573 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8574 return rflags;
8575}
8576EXPORT_SYMBOL_GPL(kvm_get_rflags);
8577
6addfc42 8578static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8579{
8580 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8581 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8582 rflags |= X86_EFLAGS_TF;
94fe45da 8583 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8584}
8585
8586void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8587{
8588 __kvm_set_rflags(vcpu, rflags);
3842d135 8589 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8590}
8591EXPORT_SYMBOL_GPL(kvm_set_rflags);
8592
56028d08
GN		 8593void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8594{
8595 int r;
8596
fb67e14f 8597 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8598 work->wakeup_all)
56028d08
GN		 8599 return;
8600
8601 r = kvm_mmu_reload(vcpu);
8602 if (unlikely(r))
8603 return;
8604
fb67e14f
XG		 8605 if (!vcpu->arch.mmu.direct_map &&
8606 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8607 return;
8608
56028d08
GN		 8609 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8610}
8611
af585b92
GN		 8612static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8613{
8614 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8615}
8616
8617static inline u32 kvm_async_pf_next_probe(u32 key)
8618{
8619 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8620}
8621
8622static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8623{
8624 u32 key = kvm_async_pf_hash_fn(gfn);
8625
8626 while (vcpu->arch.apf.gfns[key] != ~0)
8627 key = kvm_async_pf_next_probe(key);
8628
8629 vcpu->arch.apf.gfns[key] = gfn;
8630}
8631
8632static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8633{
8634 int i;
8635 u32 key = kvm_async_pf_hash_fn(gfn);
8636
8637 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8638 (vcpu->arch.apf.gfns[key] != gfn &&
8639 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8640 key = kvm_async_pf_next_probe(key);
8641
8642 return key;
8643}
8644
8645bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8646{
8647 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8648}
8649
8650static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8651{
8652 u32 i, j, k;
8653
8654 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8655 while (true) {
8656 vcpu->arch.apf.gfns[i] = ~0;
8657 do {
8658 j = kvm_async_pf_next_probe(j);
8659 if (vcpu->arch.apf.gfns[j] == ~0)
8660 return;
8661 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8662 /*
8663 * k lies cyclically in ]i,j]
8664 * | i.k.j |
8665 * |....j i.k.| or |.k..j i...|
8666 */
8667 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8668 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8669 i = j;
8670 }
8671}
8672
7c90705b
GN		 8673static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8674{
4e335d9e
PB		 8675
8676 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8677 sizeof(val));
7c90705b
GN		 8678}
8679
9a6e7c39
WL		 8680static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8681{
8682
8683 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8684 sizeof(u32));
8685}
8686
af585b92
GN		 8687void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8688 struct kvm_async_pf *work)
8689{
6389ee94
AK		 8690 struct x86_exception fault;
8691
7c90705b 8692 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8693 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8694
8695 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8696 (vcpu->arch.apf.send_user_only &&
8697 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8698 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8699 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8700 fault.vector = PF_VECTOR;
8701 fault.error_code_valid = true;
8702 fault.error_code = 0;
8703 fault.nested_page_fault = false;
8704 fault.address = work->arch.token;
adfe20fb 8705 fault.async_page_fault = true;
6389ee94 8706 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8707 }
af585b92
GN		 8708}
8709
8710void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8711 struct kvm_async_pf *work)
8712{
6389ee94 8713 struct x86_exception fault;
9a6e7c39 8714 u32 val;
6389ee94 8715
f2e10669 8716 if (work->wakeup_all)
7c90705b
GN		 8717 work->arch.token = ~0; /* broadcast wakeup */
8718 else
8719 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8720 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8721
9a6e7c39
WL		 8722 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8723 !apf_get_user(vcpu, &val)) {
8724 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8725 vcpu->arch.exception.pending &&
8726 vcpu->arch.exception.nr == PF_VECTOR &&
8727 !apf_put_user(vcpu, 0)) {
8728 vcpu->arch.exception.injected = false;
8729 vcpu->arch.exception.pending = false;
8730 vcpu->arch.exception.nr = 0;
8731 vcpu->arch.exception.has_error_code = false;
8732 vcpu->arch.exception.error_code = 0;
8733 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8734 fault.vector = PF_VECTOR;
8735 fault.error_code_valid = true;
8736 fault.error_code = 0;
8737 fault.nested_page_fault = false;
8738 fault.address = work->arch.token;
8739 fault.async_page_fault = true;
8740 kvm_inject_page_fault(vcpu, &fault);
8741 }
7c90705b 8742 }
e6d53e3b 8743 vcpu->arch.apf.halted = false;
a4fa1635 8744 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8745}
8746
8747bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8748{
8749 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8750 return true;
8751 else
9bc1f09f 8752 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8753}
8754
5544eb9b
PB		 8755void kvm_arch_start_assignment(struct kvm *kvm)
8756{
8757 atomic_inc(&kvm->arch.assigned_device_count);
8758}
8759EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8760
8761void kvm_arch_end_assignment(struct kvm *kvm)
8762{
8763 atomic_dec(&kvm->arch.assigned_device_count);
8764}
8765EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8766
8767bool kvm_arch_has_assigned_device(struct kvm *kvm)
8768{
8769 return atomic_read(&kvm->arch.assigned_device_count);
8770}
8771EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8772
e0f0bbc5
AW		 8773void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8774{
8775 atomic_inc(&kvm->arch.noncoherent_dma_count);
8776}
8777EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8778
8779void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8780{
8781 atomic_dec(&kvm->arch.noncoherent_dma_count);
8782}
8783EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8784
8785bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8786{
8787 return atomic_read(&kvm->arch.noncoherent_dma_count);
8788}
8789EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8790
14717e20
AW		 8791bool kvm_arch_has_irq_bypass(void)
8792{
8793 return kvm_x86_ops->update_pi_irte != NULL;
8794}
8795
87276880
FW		 8796int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8797 struct irq_bypass_producer *prod)
8798{
8799 struct kvm_kernel_irqfd *irqfd =
8800 container_of(cons, struct kvm_kernel_irqfd, consumer);
8801
14717e20 8802 irqfd->producer = prod;
87276880 8803
14717e20
AW		 8804 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8805 prod->irq, irqfd->gsi, 1);
87276880
FW		 8806}
8807
8808void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8809 struct irq_bypass_producer *prod)
8810{
8811 int ret;
8812 struct kvm_kernel_irqfd *irqfd =
8813 container_of(cons, struct kvm_kernel_irqfd, consumer);
8814
87276880
FW		 8815 WARN_ON(irqfd->producer != prod);
8816 irqfd->producer = NULL;
8817
8818 /*
8819 * When producer of consumer is unregistered, we change back to
8820 * remapped mode, so we can re-use the current implementation
bb3541f1 8821 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8822 * int this case doesn't want to receive the interrupts.
8823 */
8824 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8825 if (ret)
8826 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8827 " fails: %d\n", irqfd->consumer.token, ret);
8828}
8829
8830int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8831 uint32_t guest_irq, bool set)
8832{
8833 if (!kvm_x86_ops->update_pi_irte)
8834 return -EINVAL;
8835
8836 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8837}
8838
52004014
FW		 8839bool kvm_vector_hashing_enabled(void)
8840{
8841 return vector_hashing;
8842}
8843EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8844
229456fc 8845EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8846EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8847EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8848EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8849EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8850EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8851EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8854EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8855EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8856EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8857EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8858EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8859EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8860EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8861EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8862EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8863EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git