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KVM: VMX: Fix vmx->nested freeing when no SMI handler
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
fab0aa3b
EM		 110static bool __read_mostly report_ignored_msrs = true;
111module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
9ed96e87
MT		 113unsigned int min_timer_period_us = 500;
114module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
630994b3
MT		 116static bool __read_mostly kvmclock_periodic_sync = true;
117module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
893590c7 119bool __read_mostly kvm_has_tsc_control;
92a1f12d 120EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 121u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 123u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125u64 __read_mostly kvm_max_tsc_scaling_ratio;
126EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 127u64 __read_mostly kvm_default_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 129
cc578287 130/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 131static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 132module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
d0659d94 134/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 135unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 136module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
52004014
FW		 138static bool __read_mostly vector_hashing = true;
139module_param(vector_hashing, bool, S_IRUGO);
140
18863bdd
AK		 141#define KVM_NR_SHARED_MSRS 16
142
143struct kvm_shared_msrs_global {
144 int nr;
2bf78fa7 145 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 146};
147
148struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
2bf78fa7
SY		 151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 155};
156
157static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 158static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 159
417bc304 160struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 171 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 176 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 184 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 185 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 186 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 187 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
188 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
189 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
190 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
191 { "mmu_flooded", VM_STAT(mmu_flooded) },
192 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 193 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 194 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 195 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 196 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 197 { "max_mmu_page_hash_collisions",
198 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 199 { NULL }
200};
201
2acf923e
DC		 202u64 __read_mostly host_xcr0;
203
b6785def 204static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 205
af585b92
GN		 206static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
207{
208 int i;
209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
210 vcpu->arch.apf.gfns[i] = ~0;
211}
212
18863bdd
AK		 213static void kvm_on_user_return(struct user_return_notifier *urn)
214{
215 unsigned slot;
18863bdd
AK		 216 struct kvm_shared_msrs *locals
217 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 218 struct kvm_shared_msr_values *values;
1650b4eb
IA		 219 unsigned long flags;
220
221 /*
222 * Disabling irqs at this point since the following code could be
223 * interrupted and executed through kvm_arch_hardware_disable()
224 */
225 local_irq_save(flags);
226 if (locals->registered) {
227 locals->registered = false;
228 user_return_notifier_unregister(urn);
229 }
230 local_irq_restore(flags);
18863bdd 231 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 232 values = &locals->values[slot];
233 if (values->host != values->curr) {
234 wrmsrl(shared_msrs_global.msrs[slot], values->host);
235 values->curr = values->host;
18863bdd
AK		 236 }
237 }
18863bdd
AK		 238}
239
2bf78fa7 240static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 241{
18863bdd 242 u64 value;
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 245
2bf78fa7
SY		 246 /* only read, and nobody should modify it at this time,
247 * so don't need lock */
248 if (slot >= shared_msrs_global.nr) {
249 printk(KERN_ERR "kvm: invalid MSR slot!");
250 return;
251 }
252 rdmsrl_safe(msr, &value);
253 smsr->values[slot].host = value;
254 smsr->values[slot].curr = value;
255}
256
257void kvm_define_shared_msr(unsigned slot, u32 msr)
258{
0123be42 259 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 260 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 261 if (slot >= shared_msrs_global.nr)
262 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 263}
264EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
265
266static void kvm_shared_msr_cpu_online(void)
267{
268 unsigned i;
18863bdd
AK		 269
270 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 271 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 272}
273
8b3c3104 274int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 275{
013f6a5d
MT		 276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 278 int err;
18863bdd 279
2bf78fa7 280 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 281 return 0;
2bf78fa7 282 smsr->values[slot].curr = value;
8b3c3104
AH		 283 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
284 if (err)
285 return 1;
286
18863bdd
AK		 287 if (!smsr->registered) {
288 smsr->urn.on_user_return = kvm_on_user_return;
289 user_return_notifier_register(&smsr->urn);
290 smsr->registered = true;
291 }
8b3c3104 292 return 0;
18863bdd
AK		 293}
294EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
295
13a34e06 296static void drop_user_return_notifiers(void)
3548bab5 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 300
301 if (smsr->registered)
302 kvm_on_user_return(&smsr->urn);
303}
304
6866b83e
CO		 305u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
306{
8a5a87d9 307 return vcpu->arch.apic_base;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_get_apic_base);
310
58cb628d
JK		 311int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
312{
313 u64 old_state = vcpu->arch.apic_base &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 new_state = msr_info->data &
316 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 317 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
318 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 319
d3802286
JM		 320 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
321 return 1;
58cb628d 322 if (!msr_info->host_initiated &&
d3802286 323 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 324 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
325 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
326 old_state == 0)))
327 return 1;
328
329 kvm_lapic_set_base(vcpu, msr_info->data);
330 return 0;
6866b83e
CO		 331}
332EXPORT_SYMBOL_GPL(kvm_set_apic_base);
333
2605fc21 334asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 335{
336 /* Fault while not rebooting. We want the trace. */
337 BUG();
338}
339EXPORT_SYMBOL_GPL(kvm_spurious_fault);
340
3fd28fce
ED		 341#define EXCPT_BENIGN 0
342#define EXCPT_CONTRIBUTORY 1
343#define EXCPT_PF 2
344
345static int exception_class(int vector)
346{
347 switch (vector) {
348 case PF_VECTOR:
349 return EXCPT_PF;
350 case DE_VECTOR:
351 case TS_VECTOR:
352 case NP_VECTOR:
353 case SS_VECTOR:
354 case GP_VECTOR:
355 return EXCPT_CONTRIBUTORY;
356 default:
357 break;
358 }
359 return EXCPT_BENIGN;
360}
361
d6e8c854
NA		 362#define EXCPT_FAULT 0
363#define EXCPT_TRAP 1
364#define EXCPT_ABORT 2
365#define EXCPT_INTERRUPT 3
366
367static int exception_type(int vector)
368{
369 unsigned int mask;
370
371 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
372 return EXCPT_INTERRUPT;
373
374 mask = 1 << vector;
375
376 /* #DB is trap, as instruction watchpoints are handled elsewhere */
377 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
378 return EXCPT_TRAP;
379
380 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
381 return EXCPT_ABORT;
382
383 /* Reserved exceptions will result in fault */
384 return EXCPT_FAULT;
385}
386
3fd28fce 387static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 388 unsigned nr, bool has_error, u32 error_code,
389 bool reinject)
3fd28fce
ED		 390{
391 u32 prev_nr;
392 int class1, class2;
393
3842d135
AK		 394 kvm_make_request(KVM_REQ_EVENT, vcpu);
395
664f8e26 396 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 397 queue:
3ffb2468
NA		 398 if (has_error && !is_protmode(vcpu))
399 has_error = false;
664f8e26
WL		 400 if (reinject) {
401 /*
402 * On vmentry, vcpu->arch.exception.pending is only
403 * true if an event injection was blocked by
404 * nested_run_pending. In that case, however,
405 * vcpu_enter_guest requests an immediate exit,
406 * and the guest shouldn't proceed far enough to
407 * need reinjection.
408 */
409 WARN_ON_ONCE(vcpu->arch.exception.pending);
410 vcpu->arch.exception.injected = true;
411 } else {
412 vcpu->arch.exception.pending = true;
413 vcpu->arch.exception.injected = false;
414 }
3fd28fce
ED		 415 vcpu->arch.exception.has_error_code = has_error;
416 vcpu->arch.exception.nr = nr;
417 vcpu->arch.exception.error_code = error_code;
418 return;
419 }
420
421 /* to check exception */
422 prev_nr = vcpu->arch.exception.nr;
423 if (prev_nr == DF_VECTOR) {
424 /* triple fault -> shutdown */
a8eeb04a 425 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 426 return;
427 }
428 class1 = exception_class(prev_nr);
429 class2 = exception_class(nr);
430 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
431 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 432 /*
433 * Generate double fault per SDM Table 5-5. Set
434 * exception.pending = true so that the double fault
435 * can trigger a nested vmexit.
436 */
3fd28fce 437 vcpu->arch.exception.pending = true;
664f8e26 438 vcpu->arch.exception.injected = false;
3fd28fce
ED		 439 vcpu->arch.exception.has_error_code = true;
440 vcpu->arch.exception.nr = DF_VECTOR;
441 vcpu->arch.exception.error_code = 0;
442 } else
443 /* replace previous exception with a new one in a hope
444 that instruction re-execution will regenerate lost
445 exception */
446 goto queue;
447}
448
298101da
AK		 449void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
450{
ce7ddec4 451 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 452}
453EXPORT_SYMBOL_GPL(kvm_queue_exception);
454
ce7ddec4
JR		 455void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
456{
457 kvm_multiple_exception(vcpu, nr, false, 0, true);
458}
459EXPORT_SYMBOL_GPL(kvm_requeue_exception);
460
6affcbed 461int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 462{
db8fcefa
AP		 463 if (err)
464 kvm_inject_gp(vcpu, 0);
465 else
6affcbed
KH		 466 return kvm_skip_emulated_instruction(vcpu);
467
468 return 1;
db8fcefa
AP		 469}
470EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 471
6389ee94 472void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 473{
474 ++vcpu->stat.pf_guest;
adfe20fb
WL		 475 vcpu->arch.exception.nested_apf =
476 is_guest_mode(vcpu) && fault->async_page_fault;
477 if (vcpu->arch.exception.nested_apf)
478 vcpu->arch.apf.nested_apf_token = fault->address;
479 else
480 vcpu->arch.cr2 = fault->address;
6389ee94 481 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 482}
27d6c865 483EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 484
ef54bcfe 485static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 486{
6389ee94
AK		 487 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
488 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 489 else
6389ee94 490 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 491
492 return fault->nested_page_fault;
d4f8cf66
JR		 493}
494
3419ffc8
SY		 495void kvm_inject_nmi(struct kvm_vcpu *vcpu)
496{
7460fb4a
AK		 497 atomic_inc(&vcpu->arch.nmi_queued);
498 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 499}
500EXPORT_SYMBOL_GPL(kvm_inject_nmi);
501
298101da
AK		 502void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
503{
ce7ddec4 504 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 505}
506EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
507
ce7ddec4
JR		 508void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
509{
510 kvm_multiple_exception(vcpu, nr, true, error_code, true);
511}
512EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
513
0a79b009
AK		 514/*
515 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
516 * a #GP and return false.
517 */
518bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 519{
0a79b009
AK		 520 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
521 return true;
522 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
523 return false;
298101da 524}
0a79b009 525EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 526
16f8a6f9
NA		 527bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
528{
529 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
530 return true;
531
532 kvm_queue_exception(vcpu, UD_VECTOR);
533 return false;
534}
535EXPORT_SYMBOL_GPL(kvm_require_dr);
536
ec92fe44
JR		 537/*
538 * This function will be used to read from the physical memory of the currently
54bf36aa 539 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 540 * can read from guest physical or from the guest's guest physical memory.
541 */
542int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
543 gfn_t ngfn, void *data, int offset, int len,
544 u32 access)
545{
54987b7a 546 struct x86_exception exception;
ec92fe44
JR		 547 gfn_t real_gfn;
548 gpa_t ngpa;
549
550 ngpa = gfn_to_gpa(ngfn);
54987b7a 551 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 552 if (real_gfn == UNMAPPED_GVA)
553 return -EFAULT;
554
555 real_gfn = gpa_to_gfn(real_gfn);
556
54bf36aa 557 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 558}
559EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
560
69b0049a 561static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 562 void *data, int offset, int len, u32 access)
563{
564 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
565 data, offset, len, access);
566}
567
a03490ed
CO		 568/*
569 * Load the pae pdptrs. Return true is they are all valid.
570 */
ff03a073 571int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 572{
573 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
574 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
575 int i;
576 int ret;
ff03a073 577 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 578
ff03a073
JR		 579 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
580 offset * sizeof(u64), sizeof(pdpte),
581 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 582 if (ret < 0) {
583 ret = 0;
584 goto out;
585 }
586 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 587 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 588 (pdpte[i] &
589 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 590 ret = 0;
591 goto out;
592 }
593 }
594 ret = 1;
595
ff03a073 596 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 597 __set_bit(VCPU_EXREG_PDPTR,
598 (unsigned long *)&vcpu->arch.regs_avail);
599 __set_bit(VCPU_EXREG_PDPTR,
600 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 601out:
a03490ed
CO		 602
603 return ret;
604}
cc4b6871 605EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 606
9ed38ffa 607bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 608{
ff03a073 609 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 610 bool changed = true;
3d06b8bf
JR		 611 int offset;
612 gfn_t gfn;
d835dfec
AK		 613 int r;
614
615 if (is_long_mode(vcpu) || !is_pae(vcpu))
616 return false;
617
6de4f3ad
AK		 618 if (!test_bit(VCPU_EXREG_PDPTR,
619 (unsigned long *)&vcpu->arch.regs_avail))
620 return true;
621
a512177e
PB		 622 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
623 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 624 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
625 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 626 if (r < 0)
627 goto out;
ff03a073 628 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 629out:
d835dfec
AK		 630
631 return changed;
632}
9ed38ffa 633EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 634
49a9b07e 635int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 636{
aad82703 637 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 638 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 639
f9a48e6a
AK		 640 cr0 |= X86_CR0_ET;
641
ab344828 642#ifdef CONFIG_X86_64
0f12244f
GN		 643 if (cr0 & 0xffffffff00000000UL)
644 return 1;
ab344828
GN		 645#endif
646
647 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 648
0f12244f
GN		 649 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
650 return 1;
a03490ed 651
0f12244f
GN		 652 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
653 return 1;
a03490ed
CO		 654
655 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
656#ifdef CONFIG_X86_64
f6801dff 657 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 658 int cs_db, cs_l;
659
0f12244f
GN		 660 if (!is_pae(vcpu))
661 return 1;
a03490ed 662 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 663 if (cs_l)
664 return 1;
a03490ed
CO		 665 } else
666#endif
ff03a073 667 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 668 kvm_read_cr3(vcpu)))
0f12244f 669 return 1;
a03490ed
CO		 670 }
671
ad756a16
MJ		 672 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
673 return 1;
674
a03490ed 675 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 676
d170c419 677 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 678 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 679 kvm_async_pf_hash_reset(vcpu);
680 }
e5f3f027 681
aad82703
SY		 682 if ((cr0 ^ old_cr0) & update_bits)
683 kvm_mmu_reset_context(vcpu);
b18d5431 684
879ae188
LE		 685 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
686 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
687 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 688 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
689
0f12244f
GN		 690 return 0;
691}
2d3ad1f4 692EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 693
2d3ad1f4 694void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 695{
49a9b07e 696 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 697}
2d3ad1f4 698EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 699
42bdf991
MT		 700static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
701{
702 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
703 !vcpu->guest_xcr0_loaded) {
704 /* kvm_set_xcr() also depends on this */
705 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
706 vcpu->guest_xcr0_loaded = 1;
707 }
708}
709
710static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
711{
712 if (vcpu->guest_xcr0_loaded) {
713 if (vcpu->arch.xcr0 != host_xcr0)
714 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
715 vcpu->guest_xcr0_loaded = 0;
716 }
717}
718
69b0049a 719static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 720{
56c103ec
LJ		 721 u64 xcr0 = xcr;
722 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 723 u64 valid_bits;
2acf923e
DC		 724
725 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
726 if (index != XCR_XFEATURE_ENABLED_MASK)
727 return 1;
d91cab78 728 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 729 return 1;
d91cab78 730 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 731 return 1;
46c34cb0
PB		 732
733 /*
734 * Do not allow the guest to set bits that we do not support
735 * saving. However, xcr0 bit 0 is always set, even if the
736 * emulated CPU does not support XSAVE (see fx_init).
737 */
d91cab78 738 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 739 if (xcr0 & ~valid_bits)
2acf923e 740 return 1;
46c34cb0 741
d91cab78
DH		 742 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
743 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 744 return 1;
745
d91cab78
DH		 746 if (xcr0 & XFEATURE_MASK_AVX512) {
747 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 748 return 1;
d91cab78 749 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 750 return 1;
751 }
2acf923e 752 vcpu->arch.xcr0 = xcr0;
56c103ec 753
d91cab78 754 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 755 kvm_update_cpuid(vcpu);
2acf923e
DC		 756 return 0;
757}
758
759int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
760{
764bcbc5
Z		 761 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
762 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 763 kvm_inject_gp(vcpu, 0);
764 return 1;
765 }
766 return 0;
767}
768EXPORT_SYMBOL_GPL(kvm_set_xcr);
769
a83b29c6 770int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 771{
fc78f519 772 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 773 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 774 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 775
0f12244f
GN		 776 if (cr4 & CR4_RESERVED_BITS)
777 return 1;
a03490ed 778
d6321d49 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 780 return 1;
781
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 783 return 1;
784
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 786 return 1;
787
d6321d49 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 789 return 1;
790
d6321d49 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 792 return 1;
793
fd8cb433 794 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 795 return 1;
796
a03490ed 797 if (is_long_mode(vcpu)) {
0f12244f
GN		 798 if (!(cr4 & X86_CR4_PAE))
799 return 1;
a2edf57f
AK		 800 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
801 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 802 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
803 kvm_read_cr3(vcpu)))
0f12244f
GN		 804 return 1;
805
ad756a16 806 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 807 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 808 return 1;
809
810 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
811 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
812 return 1;
813 }
814
5e1746d6 815 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 816 return 1;
a03490ed 817
ad756a16
MJ		 818 if (((cr4 ^ old_cr4) & pdptr_bits) ||
819 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 820 kvm_mmu_reset_context(vcpu);
0f12244f 821
b9baba86 822 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 823 kvm_update_cpuid(vcpu);
2acf923e 824
0f12244f
GN		 825 return 0;
826}
2d3ad1f4 827EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 828
2390218b 829int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 830{
ac146235 831#ifdef CONFIG_X86_64
9d88fca7 832 cr3 &= ~CR3_PCID_INVD;
ac146235 833#endif
9d88fca7 834
9f8fe504 835 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 836 kvm_mmu_sync_roots(vcpu);
77c3913b 837 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 838 return 0;
d835dfec
AK		 839 }
840
d1cd3ce9
YZ		 841 if (is_long_mode(vcpu) &&
842 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
843 return 1;
844 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 845 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 846 return 1;
a03490ed 847
0f12244f 848 vcpu->arch.cr3 = cr3;
aff48baa 849 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 850 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 851 return 0;
852}
2d3ad1f4 853EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 854
eea1cff9 855int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 856{
0f12244f
GN		 857 if (cr8 & CR8_RESERVED_BITS)
858 return 1;
35754c98 859 if (lapic_in_kernel(vcpu))
a03490ed
CO		 860 kvm_lapic_set_tpr(vcpu, cr8);
861 else
ad312c7c 862 vcpu->arch.cr8 = cr8;
0f12244f
GN		 863 return 0;
864}
2d3ad1f4 865EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 866
2d3ad1f4 867unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 868{
35754c98 869 if (lapic_in_kernel(vcpu))
a03490ed
CO		 870 return kvm_lapic_get_cr8(vcpu);
871 else
ad312c7c 872 return vcpu->arch.cr8;
a03490ed 873}
2d3ad1f4 874EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 875
ae561ede
NA		 876static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
877{
878 int i;
879
880 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
881 for (i = 0; i < KVM_NR_DB_REGS; i++)
882 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
883 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
884 }
885}
886
73aaf249
JK		 887static void kvm_update_dr6(struct kvm_vcpu *vcpu)
888{
889 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
890 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
891}
892
c8639010
JK		 893static void kvm_update_dr7(struct kvm_vcpu *vcpu)
894{
895 unsigned long dr7;
896
897 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
898 dr7 = vcpu->arch.guest_debug_dr7;
899 else
900 dr7 = vcpu->arch.dr7;
901 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 902 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
903 if (dr7 & DR7_BP_EN_MASK)
904 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 905}
906
6f43ed01
NA		 907static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
908{
909 u64 fixed = DR6_FIXED_1;
910
d6321d49 911 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 912 fixed |= DR6_RTM;
913 return fixed;
914}
915
338dbc97 916static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 917{
918 switch (dr) {
919 case 0 ... 3:
920 vcpu->arch.db[dr] = val;
921 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
922 vcpu->arch.eff_db[dr] = val;
923 break;
924 case 4:
020df079
GN		 925 /* fall through */
926 case 6:
338dbc97
GN		 927 if (val & 0xffffffff00000000ULL)
928 return -1; /* #GP */
6f43ed01 929 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 930 kvm_update_dr6(vcpu);
020df079
GN		 931 break;
932 case 5:
020df079
GN		 933 /* fall through */
934 default: /* 7 */
338dbc97
GN		 935 if (val & 0xffffffff00000000ULL)
936 return -1; /* #GP */
020df079 937 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 938 kvm_update_dr7(vcpu);
020df079
GN		 939 break;
940 }
941
942 return 0;
943}
338dbc97
GN		 944
945int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
946{
16f8a6f9 947 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 948 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 949 return 1;
950 }
951 return 0;
338dbc97 952}
020df079
GN		 953EXPORT_SYMBOL_GPL(kvm_set_dr);
954
16f8a6f9 955int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 956{
957 switch (dr) {
958 case 0 ... 3:
959 *val = vcpu->arch.db[dr];
960 break;
961 case 4:
020df079
GN		 962 /* fall through */
963 case 6:
73aaf249
JK		 964 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
965 *val = vcpu->arch.dr6;
966 else
967 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 968 break;
969 case 5:
020df079
GN		 970 /* fall through */
971 default: /* 7 */
972 *val = vcpu->arch.dr7;
973 break;
974 }
338dbc97
GN		 975 return 0;
976}
020df079
GN		 977EXPORT_SYMBOL_GPL(kvm_get_dr);
978
022cd0e8
AK		 979bool kvm_rdpmc(struct kvm_vcpu *vcpu)
980{
981 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
982 u64 data;
983 int err;
984
c6702c9d 985 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 986 if (err)
987 return err;
988 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
989 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
990 return err;
991}
992EXPORT_SYMBOL_GPL(kvm_rdpmc);
993
043405e1
CO		 994/*
995 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
996 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
997 *
998 * This list is modified at module load time to reflect the
e3267cbb 999 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1000 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1001 * may depend on host virtualization features rather than host cpu features.
043405e1 1002 */
e3267cbb 1003
043405e1
CO		 1004static u32 msrs_to_save[] = {
1005 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1006 MSR_STAR,
043405e1
CO		 1007#ifdef CONFIG_X86_64
1008 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1009#endif
b3897a49 1010 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1011 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 1012};
1013
1014static unsigned num_msrs_to_save;
1015
62ef68bb
PB		 1016static u32 emulated_msrs[] = {
1017 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1018 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1019 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1020 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1021 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1022 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1023 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1024 HV_X64_MSR_RESET,
11c4b1ca 1025 HV_X64_MSR_VP_INDEX,
9eec50b8 1026 HV_X64_MSR_VP_RUNTIME,
5c919412 1027 HV_X64_MSR_SCONTROL,
1f4b34f8 1028 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1029 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1030 MSR_KVM_PV_EOI_EN,
1031
ba904635 1032 MSR_IA32_TSC_ADJUST,
a3e06bbe 1033 MSR_IA32_TSCDEADLINE,
043405e1 1034 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1035 MSR_IA32_MCG_STATUS,
1036 MSR_IA32_MCG_CTL,
c45dcc71 1037 MSR_IA32_MCG_EXT_CTL,
64d60670 1038 MSR_IA32_SMBASE,
db2336a8
KH		 1039 MSR_PLATFORM_INFO,
1040 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1041};
1042
62ef68bb
PB		 1043static unsigned num_emulated_msrs;
1044
384bb783 1045bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1046{
b69e8cae 1047 if (efer & efer_reserved_bits)
384bb783 1048 return false;
15c4a640 1049
1b4d56b8 1050 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1051 return false;
1b2fd70c 1052
1b4d56b8 1053 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1054 return false;
d8017474 1055
384bb783
JK		 1056 return true;
1057}
1058EXPORT_SYMBOL_GPL(kvm_valid_efer);
1059
1060static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1061{
1062 u64 old_efer = vcpu->arch.efer;
1063
1064 if (!kvm_valid_efer(vcpu, efer))
1065 return 1;
1066
1067 if (is_paging(vcpu)
1068 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1069 return 1;
1070
15c4a640 1071 efer &= ~EFER_LMA;
f6801dff 1072 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1073
a3d204e2
SY		 1074 kvm_x86_ops->set_efer(vcpu, efer);
1075
aad82703
SY		 1076 /* Update reserved bits */
1077 if ((efer ^ old_efer) & EFER_NX)
1078 kvm_mmu_reset_context(vcpu);
1079
b69e8cae 1080 return 0;
15c4a640
CO		 1081}
1082
f2b4b7dd
JR		 1083void kvm_enable_efer_bits(u64 mask)
1084{
1085 efer_reserved_bits &= ~mask;
1086}
1087EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1088
15c4a640
CO		 1089/*
1090 * Writes msr value into into the appropriate "register".
1091 * Returns 0 on success, non-0 otherwise.
1092 * Assumes vcpu_load() was already called.
1093 */
8fe8ab46 1094int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1095{
854e8bb1
NA		 1096 switch (msr->index) {
1097 case MSR_FS_BASE:
1098 case MSR_GS_BASE:
1099 case MSR_KERNEL_GS_BASE:
1100 case MSR_CSTAR:
1101 case MSR_LSTAR:
fd8cb433 1102 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1103 return 1;
1104 break;
1105 case MSR_IA32_SYSENTER_EIP:
1106 case MSR_IA32_SYSENTER_ESP:
1107 /*
1108 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1109 * non-canonical address is written on Intel but not on
1110 * AMD (which ignores the top 32-bits, because it does
1111 * not implement 64-bit SYSENTER).
1112 *
1113 * 64-bit code should hence be able to write a non-canonical
1114 * value on AMD. Making the address canonical ensures that
1115 * vmentry does not fail on Intel after writing a non-canonical
1116 * value, and that something deterministic happens if the guest
1117 * invokes 64-bit SYSENTER.
1118 */
fd8cb433 1119 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1120 }
8fe8ab46 1121 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1122}
854e8bb1 1123EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1124
313a3dc7
CO		 1125/*
1126 * Adapt set_msr() to msr_io()'s calling convention
1127 */
609e36d3
PB		 1128static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1129{
1130 struct msr_data msr;
1131 int r;
1132
1133 msr.index = index;
1134 msr.host_initiated = true;
1135 r = kvm_get_msr(vcpu, &msr);
1136 if (r)
1137 return r;
1138
1139 *data = msr.data;
1140 return 0;
1141}
1142
313a3dc7
CO		 1143static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1144{
8fe8ab46
WA		 1145 struct msr_data msr;
1146
1147 msr.data = *data;
1148 msr.index = index;
1149 msr.host_initiated = true;
1150 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1151}
1152
16e8d74d
MT		 1153#ifdef CONFIG_X86_64
1154struct pvclock_gtod_data {
1155 seqcount_t seq;
1156
1157 struct { /* extract of a clocksource struct */
1158 int vclock_mode;
a5a1d1c2
TG		 1159 u64 cycle_last;
1160 u64 mask;
16e8d74d
MT		 1161 u32 mult;
1162 u32 shift;
1163 } clock;
1164
cbcf2dd3
TG		 1165 u64 boot_ns;
1166 u64 nsec_base;
55dd00a7 1167 u64 wall_time_sec;
16e8d74d
MT		 1168};
1169
1170static struct pvclock_gtod_data pvclock_gtod_data;
1171
1172static void update_pvclock_gtod(struct timekeeper *tk)
1173{
1174 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1175 u64 boot_ns;
1176
876e7881 1177 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1178
1179 write_seqcount_begin(&vdata->seq);
1180
1181 /* copy pvclock gtod data */
876e7881
PZ		 1182 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1183 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1184 vdata->clock.mask = tk->tkr_mono.mask;
1185 vdata->clock.mult = tk->tkr_mono.mult;
1186 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1187
cbcf2dd3 1188 vdata->boot_ns = boot_ns;
876e7881 1189 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1190
55dd00a7
MT		 1191 vdata->wall_time_sec = tk->xtime_sec;
1192
16e8d74d
MT		 1193 write_seqcount_end(&vdata->seq);
1194}
1195#endif
1196
bab5bb39
NK		 1197void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1198{
1199 /*
1200 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1201 * vcpu_enter_guest. This function is only called from
1202 * the physical CPU that is running vcpu.
1203 */
1204 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1205}
16e8d74d 1206
18068523
GOC		 1207static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1208{
9ed3c444
AK		 1209 int version;
1210 int r;
50d0a0f9 1211 struct pvclock_wall_clock wc;
87aeb54f 1212 struct timespec64 boot;
18068523
GOC		 1213
1214 if (!wall_clock)
1215 return;
1216
9ed3c444
AK		 1217 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1218 if (r)
1219 return;
1220
1221 if (version & 1)
1222 ++version; /* first time write, random junk */
1223
1224 ++version;
18068523 1225
1dab1345
NK		 1226 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1227 return;
18068523 1228
50d0a0f9
GH		 1229 /*
1230 * The guest calculates current wall clock time by adding
34c238a1 1231 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1232 * wall clock specified here. guest system time equals host
1233 * system time for us, thus we must fill in host boot time here.
1234 */
87aeb54f 1235 getboottime64(&boot);
50d0a0f9 1236
4b648665 1237 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1238 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1239 boot = timespec64_sub(boot, ts);
4b648665 1240 }
87aeb54f 1241 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1242 wc.nsec = boot.tv_nsec;
1243 wc.version = version;
18068523
GOC		 1244
1245 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1246
1247 version++;
1248 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1249}
1250
50d0a0f9
GH		 1251static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1252{
b51012de
PB		 1253 do_shl32_div32(dividend, divisor);
1254 return dividend;
50d0a0f9
GH		 1255}
1256
3ae13faa 1257static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1258 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1259{
5f4e3f88 1260 uint64_t scaled64;
50d0a0f9
GH		 1261 int32_t shift = 0;
1262 uint64_t tps64;
1263 uint32_t tps32;
1264
3ae13faa
PB		 1265 tps64 = base_hz;
1266 scaled64 = scaled_hz;
50933623 1267 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1268 tps64 >>= 1;
1269 shift--;
1270 }
1271
1272 tps32 = (uint32_t)tps64;
50933623
JK		 1273 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1274 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1275 scaled64 >>= 1;
1276 else
1277 tps32 <<= 1;
50d0a0f9
GH		 1278 shift++;
1279 }
1280
5f4e3f88
ZA		 1281 *pshift = shift;
1282 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1283
3ae13faa
PB		 1284 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1285 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1286}
1287
d828199e 1288#ifdef CONFIG_X86_64
16e8d74d 1289static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1290#endif
16e8d74d 1291
c8076604 1292static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1293static unsigned long max_tsc_khz;
c8076604 1294
cc578287 1295static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1296{
cc578287
ZA		 1297 u64 v = (u64)khz * (1000000 + ppm);
1298 do_div(v, 1000000);
1299 return v;
1e993611
JR		 1300}
1301
381d585c
HZ		 1302static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1303{
1304 u64 ratio;
1305
1306 /* Guest TSC same frequency as host TSC? */
1307 if (!scale) {
1308 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1309 return 0;
1310 }
1311
1312 /* TSC scaling supported? */
1313 if (!kvm_has_tsc_control) {
1314 if (user_tsc_khz > tsc_khz) {
1315 vcpu->arch.tsc_catchup = 1;
1316 vcpu->arch.tsc_always_catchup = 1;
1317 return 0;
1318 } else {
1319 WARN(1, "user requested TSC rate below hardware speed\n");
1320 return -1;
1321 }
1322 }
1323
1324 /* TSC scaling required - calculate ratio */
1325 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1326 user_tsc_khz, tsc_khz);
1327
1328 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1329 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1330 user_tsc_khz);
1331 return -1;
1332 }
1333
1334 vcpu->arch.tsc_scaling_ratio = ratio;
1335 return 0;
1336}
1337
4941b8cb 1338static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1339{
cc578287
ZA		 1340 u32 thresh_lo, thresh_hi;
1341 int use_scaling = 0;
217fc9cf 1342
03ba32ca 1343 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1344 if (user_tsc_khz == 0) {
ad721883
HZ		 1345 /* set tsc_scaling_ratio to a safe value */
1346 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1347 return -1;
ad721883 1348 }
03ba32ca 1349
c285545f 1350 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1351 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1352 &vcpu->arch.virtual_tsc_shift,
1353 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1354 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1355
1356 /*
1357 * Compute the variation in TSC rate which is acceptable
1358 * within the range of tolerance and decide if the
1359 * rate being applied is within that bounds of the hardware
1360 * rate. If so, no scaling or compensation need be done.
1361 */
1362 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1363 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1364 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1365 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1366 use_scaling = 1;
1367 }
4941b8cb 1368 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1369}
1370
1371static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1372{
e26101b1 1373 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1374 vcpu->arch.virtual_tsc_mult,
1375 vcpu->arch.virtual_tsc_shift);
e26101b1 1376 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1377 return tsc;
1378}
1379
69b0049a 1380static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1381{
1382#ifdef CONFIG_X86_64
1383 bool vcpus_matched;
b48aa97e
MT		 1384 struct kvm_arch *ka = &vcpu->kvm->arch;
1385 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1386
1387 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1388 atomic_read(&vcpu->kvm->online_vcpus));
1389
7f187922
MT		 1390 /*
1391 * Once the masterclock is enabled, always perform request in
1392 * order to update it.
1393 *
1394 * In order to enable masterclock, the host clocksource must be TSC
1395 * and the vcpus need to have matched TSCs. When that happens,
1396 * perform request to enable masterclock.
1397 */
1398 if (ka->use_master_clock ||
1399 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1400 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1401
1402 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1403 atomic_read(&vcpu->kvm->online_vcpus),
1404 ka->use_master_clock, gtod->clock.vclock_mode);
1405#endif
1406}
1407
ba904635
WA		 1408static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1409{
3e3f5026 1410 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1411 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1412}
1413
35181e86
HZ		 1414/*
1415 * Multiply tsc by a fixed point number represented by ratio.
1416 *
1417 * The most significant 64-N bits (mult) of ratio represent the
1418 * integral part of the fixed point number; the remaining N bits
1419 * (frac) represent the fractional part, ie. ratio represents a fixed
1420 * point number (mult + frac * 2^(-N)).
1421 *
1422 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1423 */
1424static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1425{
1426 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1427}
1428
1429u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1430{
1431 u64 _tsc = tsc;
1432 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1433
1434 if (ratio != kvm_default_tsc_scaling_ratio)
1435 _tsc = __scale_tsc(ratio, tsc);
1436
1437 return _tsc;
1438}
1439EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1440
07c1419a
HZ		 1441static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1442{
1443 u64 tsc;
1444
1445 tsc = kvm_scale_tsc(vcpu, rdtsc());
1446
1447 return target_tsc - tsc;
1448}
1449
4ba76538
HZ		 1450u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1451{
ea26e4ec 1452 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1453}
1454EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1455
a545ab6a
LC		 1456static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1457{
1458 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1459 vcpu->arch.tsc_offset = offset;
1460}
1461
8fe8ab46 1462void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1463{
1464 struct kvm *kvm = vcpu->kvm;
f38e098f 1465 u64 offset, ns, elapsed;
99e3e30a 1466 unsigned long flags;
b48aa97e 1467 bool matched;
0d3da0d2 1468 bool already_matched;
8fe8ab46 1469 u64 data = msr->data;
c5e8ec8e 1470 bool synchronizing = false;
99e3e30a 1471
038f8c11 1472 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1473 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1474 ns = ktime_get_boot_ns();
f38e098f 1475 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1476
03ba32ca 1477 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1478 if (data == 0 && msr->host_initiated) {
1479 /*
1480 * detection of vcpu initialization -- need to sync
1481 * with other vCPUs. This particularly helps to keep
1482 * kvm_clock stable after CPU hotplug
1483 */
1484 synchronizing = true;
1485 } else {
1486 u64 tsc_exp = kvm->arch.last_tsc_write +
1487 nsec_to_cycles(vcpu, elapsed);
1488 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1489 /*
1490 * Special case: TSC write with a small delta (1 second)
1491 * of virtual cycle time against real time is
1492 * interpreted as an attempt to synchronize the CPU.
1493 */
1494 synchronizing = data < tsc_exp + tsc_hz &&
1495 data + tsc_hz > tsc_exp;
1496 }
c5e8ec8e 1497 }
f38e098f
ZA		 1498
1499 /*
5d3cb0f6
ZA		 1500 * For a reliable TSC, we can match TSC offsets, and for an unstable
1501 * TSC, we add elapsed time in this computation. We could let the
1502 * compensation code attempt to catch up if we fall behind, but
1503 * it's better to try to match offsets from the beginning.
1504 */
c5e8ec8e 1505 if (synchronizing &&
5d3cb0f6 1506 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1507 if (!check_tsc_unstable()) {
e26101b1 1508 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1509 pr_debug("kvm: matched tsc offset for %llu\n", data);
1510 } else {
857e4099 1511 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1512 data += delta;
07c1419a 1513 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1514 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1515 }
b48aa97e 1516 matched = true;
0d3da0d2 1517 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1518 } else {
1519 /*
1520 * We split periods of matched TSC writes into generations.
1521 * For each generation, we track the original measured
1522 * nanosecond time, offset, and write, so if TSCs are in
1523 * sync, we can match exact offset, and if not, we can match
4a969980 1524 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1525 *
1526 * These values are tracked in kvm->arch.cur_xxx variables.
1527 */
1528 kvm->arch.cur_tsc_generation++;
1529 kvm->arch.cur_tsc_nsec = ns;
1530 kvm->arch.cur_tsc_write = data;
1531 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1532 matched = false;
0d3da0d2 1533 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1534 kvm->arch.cur_tsc_generation, data);
f38e098f 1535 }
e26101b1
ZA		 1536
1537 /*
1538 * We also track th most recent recorded KHZ, write and time to
1539 * allow the matching interval to be extended at each write.
1540 */
f38e098f
ZA		 1541 kvm->arch.last_tsc_nsec = ns;
1542 kvm->arch.last_tsc_write = data;
5d3cb0f6 1543 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1544
b183aa58 1545 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1546
1547 /* Keep track of which generation this VCPU has synchronized to */
1548 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1549 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1550 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1551
d6321d49 1552 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1553 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1554
a545ab6a 1555 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1556 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1557
1558 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1559 if (!matched) {
b48aa97e 1560 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1561 } else if (!already_matched) {
1562 kvm->arch.nr_vcpus_matched_tsc++;
1563 }
b48aa97e
MT		 1564
1565 kvm_track_tsc_matching(vcpu);
1566 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1567}
e26101b1 1568
99e3e30a
ZA		 1569EXPORT_SYMBOL_GPL(kvm_write_tsc);
1570
58ea6767
HZ		 1571static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1572 s64 adjustment)
1573{
ea26e4ec 1574 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1575}
1576
1577static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1578{
1579 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1580 WARN_ON(adjustment < 0);
1581 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1582 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1583}
1584
d828199e
MT		 1585#ifdef CONFIG_X86_64
1586
a5a1d1c2 1587static u64 read_tsc(void)
d828199e 1588{
a5a1d1c2 1589 u64 ret = (u64)rdtsc_ordered();
03b9730b 1590 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1591
1592 if (likely(ret >= last))
1593 return ret;
1594
1595 /*
1596 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1597 * predictable (it's just a function of time and the likely is
d828199e
MT		 1598 * very likely) and there's a data dependence, so force GCC
1599 * to generate a branch instead. I don't barrier() because
1600 * we don't actually need a barrier, and if this function
1601 * ever gets inlined it will generate worse code.
1602 */
1603 asm volatile ("");
1604 return last;
1605}
1606
a5a1d1c2 1607static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1608{
1609 long v;
1610 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1611
1612 *cycle_now = read_tsc();
1613
1614 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1615 return v * gtod->clock.mult;
1616}
1617
a5a1d1c2 1618static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1619{
cbcf2dd3 1620 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1621 unsigned long seq;
d828199e 1622 int mode;
cbcf2dd3 1623 u64 ns;
d828199e 1624
d828199e
MT		 1625 do {
1626 seq = read_seqcount_begin(&gtod->seq);
1627 mode = gtod->clock.vclock_mode;
cbcf2dd3 1628 ns = gtod->nsec_base;
d828199e
MT		 1629 ns += vgettsc(cycle_now);
1630 ns >>= gtod->clock.shift;
cbcf2dd3 1631 ns += gtod->boot_ns;
d828199e 1632 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1633 *t = ns;
d828199e
MT		 1634
1635 return mode;
1636}
1637
55dd00a7
MT		 1638static int do_realtime(struct timespec *ts, u64 *cycle_now)
1639{
1640 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1641 unsigned long seq;
1642 int mode;
1643 u64 ns;
1644
1645 do {
1646 seq = read_seqcount_begin(&gtod->seq);
1647 mode = gtod->clock.vclock_mode;
1648 ts->tv_sec = gtod->wall_time_sec;
1649 ns = gtod->nsec_base;
1650 ns += vgettsc(cycle_now);
1651 ns >>= gtod->clock.shift;
1652 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1653
1654 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1655 ts->tv_nsec = ns;
1656
1657 return mode;
1658}
1659
d828199e 1660/* returns true if host is using tsc clocksource */
a5a1d1c2 1661static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1662{
d828199e
MT		 1663 /* checked again under seqlock below */
1664 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1665 return false;
1666
cbcf2dd3 1667 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1668}
55dd00a7
MT		 1669
1670/* returns true if host is using tsc clocksource */
1671static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1672 u64 *cycle_now)
1673{
1674 /* checked again under seqlock below */
1675 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1676 return false;
1677
1678 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1679}
d828199e
MT		 1680#endif
1681
1682/*
1683 *
b48aa97e
MT		 1684 * Assuming a stable TSC across physical CPUS, and a stable TSC
1685 * across virtual CPUs, the following condition is possible.
1686 * Each numbered line represents an event visible to both
d828199e
MT		 1687 * CPUs at the next numbered event.
1688 *
1689 * "timespecX" represents host monotonic time. "tscX" represents
1690 * RDTSC value.
1691 *
1692 * VCPU0 on CPU0 | VCPU1 on CPU1
1693 *
1694 * 1. read timespec0,tsc0
1695 * 2. | timespec1 = timespec0 + N
1696 * | tsc1 = tsc0 + M
1697 * 3. transition to guest | transition to guest
1698 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1699 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1700 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1701 *
1702 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1703 *
1704 * - ret0 < ret1
1705 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1706 * ...
1707 * - 0 < N - M => M < N
1708 *
1709 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1710 * always the case (the difference between two distinct xtime instances
1711 * might be smaller then the difference between corresponding TSC reads,
1712 * when updating guest vcpus pvclock areas).
1713 *
1714 * To avoid that problem, do not allow visibility of distinct
1715 * system_timestamp/tsc_timestamp values simultaneously: use a master
1716 * copy of host monotonic time values. Update that master copy
1717 * in lockstep.
1718 *
b48aa97e 1719 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1720 *
1721 */
1722
1723static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1724{
1725#ifdef CONFIG_X86_64
1726 struct kvm_arch *ka = &kvm->arch;
1727 int vclock_mode;
b48aa97e
MT		 1728 bool host_tsc_clocksource, vcpus_matched;
1729
1730 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1731 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1732
1733 /*
1734 * If the host uses TSC clock, then passthrough TSC as stable
1735 * to the guest.
1736 */
b48aa97e 1737 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1738 &ka->master_kernel_ns,
1739 &ka->master_cycle_now);
1740
16a96021 1741 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1742 && !ka->backwards_tsc_observed
54750f2c 1743 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1744
d828199e
MT		 1745 if (ka->use_master_clock)
1746 atomic_set(&kvm_guest_has_master_clock, 1);
1747
1748 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1749 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1750 vcpus_matched);
d828199e
MT		 1751#endif
1752}
1753
2860c4b1
PB		 1754void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1755{
1756 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1757}
1758
2e762ff7
MT		 1759static void kvm_gen_update_masterclock(struct kvm *kvm)
1760{
1761#ifdef CONFIG_X86_64
1762 int i;
1763 struct kvm_vcpu *vcpu;
1764 struct kvm_arch *ka = &kvm->arch;
1765
1766 spin_lock(&ka->pvclock_gtod_sync_lock);
1767 kvm_make_mclock_inprogress_request(kvm);
1768 /* no guest entries from this point */
1769 pvclock_update_vm_gtod_copy(kvm);
1770
1771 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1772 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1773
1774 /* guest entries allowed */
1775 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1776 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1777
1778 spin_unlock(&ka->pvclock_gtod_sync_lock);
1779#endif
1780}
1781
e891a32e 1782u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1783{
108b249c 1784 struct kvm_arch *ka = &kvm->arch;
8b953440 1785 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1786 u64 ret;
108b249c 1787
8b953440
PB		 1788 spin_lock(&ka->pvclock_gtod_sync_lock);
1789 if (!ka->use_master_clock) {
1790 spin_unlock(&ka->pvclock_gtod_sync_lock);
1791 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1792 }
1793
8b953440
PB		 1794 hv_clock.tsc_timestamp = ka->master_cycle_now;
1795 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1796 spin_unlock(&ka->pvclock_gtod_sync_lock);
1797
e2c2206a
WL		 1798 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1799 get_cpu();
1800
e70b57a6
WL		 1801 if (__this_cpu_read(cpu_tsc_khz)) {
1802 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1803 &hv_clock.tsc_shift,
1804 &hv_clock.tsc_to_system_mul);
1805 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1806 } else
1807 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1808
1809 put_cpu();
1810
1811 return ret;
108b249c
PB		 1812}
1813
0d6dd2ff
PB		 1814static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1815{
1816 struct kvm_vcpu_arch *vcpu = &v->arch;
1817 struct pvclock_vcpu_time_info guest_hv_clock;
1818
4e335d9e 1819 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1820 &guest_hv_clock, sizeof(guest_hv_clock))))
1821 return;
1822
1823 /* This VCPU is paused, but it's legal for a guest to read another
1824 * VCPU's kvmclock, so we really have to follow the specification where
1825 * it says that version is odd if data is being modified, and even after
1826 * it is consistent.
1827 *
1828 * Version field updates must be kept separate. This is because
1829 * kvm_write_guest_cached might use a "rep movs" instruction, and
1830 * writes within a string instruction are weakly ordered. So there
1831 * are three writes overall.
1832 *
1833 * As a small optimization, only write the version field in the first
1834 * and third write. The vcpu->pv_time cache is still valid, because the
1835 * version field is the first in the struct.
1836 */
1837 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1838
51c4b8bb
LA		 1839 if (guest_hv_clock.version & 1)
1840 ++guest_hv_clock.version; /* first time write, random junk */
1841
0d6dd2ff 1842 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1843 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1844 &vcpu->hv_clock,
1845 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1846
1847 smp_wmb();
1848
1849 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1850 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1851
1852 if (vcpu->pvclock_set_guest_stopped_request) {
1853 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1854 vcpu->pvclock_set_guest_stopped_request = false;
1855 }
1856
1857 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1858
4e335d9e
PB		 1859 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1860 &vcpu->hv_clock,
1861 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1862
1863 smp_wmb();
1864
1865 vcpu->hv_clock.version++;
4e335d9e
PB		 1866 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1867 &vcpu->hv_clock,
1868 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1869}
1870
34c238a1 1871static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1872{
78db6a50 1873 unsigned long flags, tgt_tsc_khz;
18068523 1874 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1875 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1876 s64 kernel_ns;
d828199e 1877 u64 tsc_timestamp, host_tsc;
51d59c6b 1878 u8 pvclock_flags;
d828199e
MT		 1879 bool use_master_clock;
1880
1881 kernel_ns = 0;
1882 host_tsc = 0;
18068523 1883
d828199e
MT		 1884 /*
1885 * If the host uses TSC clock, then passthrough TSC as stable
1886 * to the guest.
1887 */
1888 spin_lock(&ka->pvclock_gtod_sync_lock);
1889 use_master_clock = ka->use_master_clock;
1890 if (use_master_clock) {
1891 host_tsc = ka->master_cycle_now;
1892 kernel_ns = ka->master_kernel_ns;
1893 }
1894 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1895
1896 /* Keep irq disabled to prevent changes to the clock */
1897 local_irq_save(flags);
78db6a50
PB		 1898 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1899 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1900 local_irq_restore(flags);
1901 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1902 return 1;
1903 }
d828199e 1904 if (!use_master_clock) {
4ea1636b 1905 host_tsc = rdtsc();
108b249c 1906 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1907 }
1908
4ba76538 1909 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1910
c285545f
ZA		 1911 /*
1912 * We may have to catch up the TSC to match elapsed wall clock
1913 * time for two reasons, even if kvmclock is used.
1914 * 1) CPU could have been running below the maximum TSC rate
1915 * 2) Broken TSC compensation resets the base at each VCPU
1916 * entry to avoid unknown leaps of TSC even when running
1917 * again on the same CPU. This may cause apparent elapsed
1918 * time to disappear, and the guest to stand still or run
1919 * very slowly.
1920 */
1921 if (vcpu->tsc_catchup) {
1922 u64 tsc = compute_guest_tsc(v, kernel_ns);
1923 if (tsc > tsc_timestamp) {
f1e2b260 1924 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1925 tsc_timestamp = tsc;
1926 }
50d0a0f9
GH		 1927 }
1928
18068523
GOC		 1929 local_irq_restore(flags);
1930
0d6dd2ff 1931 /* With all the info we got, fill in the values */
18068523 1932
78db6a50
PB		 1933 if (kvm_has_tsc_control)
1934 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1935
1936 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1937 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1938 &vcpu->hv_clock.tsc_shift,
1939 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1940 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1941 }
1942
1d5f066e 1943 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1944 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1945 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1946
d828199e 1947 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1948 pvclock_flags = 0;
d828199e
MT		 1949 if (use_master_clock)
1950 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1951
78c0337a
MT		 1952 vcpu->hv_clock.flags = pvclock_flags;
1953
095cf55d
PB		 1954 if (vcpu->pv_time_enabled)
1955 kvm_setup_pvclock_page(v);
1956 if (v == kvm_get_vcpu(v->kvm, 0))
1957 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1958 return 0;
c8076604
GH		 1959}
1960
0061d53d
MT		 1961/*
1962 * kvmclock updates which are isolated to a given vcpu, such as
1963 * vcpu->cpu migration, should not allow system_timestamp from
1964 * the rest of the vcpus to remain static. Otherwise ntp frequency
1965 * correction applies to one vcpu's system_timestamp but not
1966 * the others.
1967 *
1968 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1969 * We need to rate-limit these requests though, as they can
1970 * considerably slow guests that have a large number of vcpus.
1971 * The time for a remote vcpu to update its kvmclock is bound
1972 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1973 */
1974
7e44e449
AJ		 1975#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1976
1977static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1978{
1979 int i;
7e44e449
AJ		 1980 struct delayed_work *dwork = to_delayed_work(work);
1981 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1982 kvmclock_update_work);
1983 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1984 struct kvm_vcpu *vcpu;
1985
1986 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1987 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1988 kvm_vcpu_kick(vcpu);
1989 }
1990}
1991
7e44e449
AJ		 1992static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1993{
1994 struct kvm *kvm = v->kvm;
1995
105b21bb 1996 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1997 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1998 KVMCLOCK_UPDATE_DELAY);
1999}
2000
332967a3
AJ		 2001#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2002
2003static void kvmclock_sync_fn(struct work_struct *work)
2004{
2005 struct delayed_work *dwork = to_delayed_work(work);
2006 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2007 kvmclock_sync_work);
2008 struct kvm *kvm = container_of(ka, struct kvm, arch);
2009
630994b3
MT		 2010 if (!kvmclock_periodic_sync)
2011 return;
2012
332967a3
AJ		 2013 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2014 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2015 KVMCLOCK_SYNC_PERIOD);
2016}
2017
9ffd986c 2018static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2019{
890ca9ae
HY		 2020 u64 mcg_cap = vcpu->arch.mcg_cap;
2021 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2022 u32 msr = msr_info->index;
2023 u64 data = msr_info->data;
890ca9ae 2024
15c4a640 2025 switch (msr) {
15c4a640 2026 case MSR_IA32_MCG_STATUS:
890ca9ae 2027 vcpu->arch.mcg_status = data;
15c4a640 2028 break;
c7ac679c 2029 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2030 if (!(mcg_cap & MCG_CTL_P))
2031 return 1;
2032 if (data != 0 && data != ~(u64)0)
2033 return -1;
2034 vcpu->arch.mcg_ctl = data;
2035 break;
2036 default:
2037 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2038 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2039 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2040 /* only 0 or all 1s can be written to IA32_MCi_CTL
2041 * some Linux kernels though clear bit 10 in bank 4 to
2042 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2043 * this to avoid an uncatched #GP in the guest
2044 */
890ca9ae 2045 if ((offset & 0x3) == 0 &&
114be429 2046 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2047 return -1;
9ffd986c
WL		 2048 if (!msr_info->host_initiated &&
2049 (offset & 0x3) == 1 && data != 0)
2050 return -1;
890ca9ae
HY		 2051 vcpu->arch.mce_banks[offset] = data;
2052 break;
2053 }
2054 return 1;
2055 }
2056 return 0;
2057}
2058
ffde22ac
ES		 2059static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2060{
2061 struct kvm *kvm = vcpu->kvm;
2062 int lm = is_long_mode(vcpu);
2063 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2064 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2065 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2066 : kvm->arch.xen_hvm_config.blob_size_32;
2067 u32 page_num = data & ~PAGE_MASK;
2068 u64 page_addr = data & PAGE_MASK;
2069 u8 *page;
2070 int r;
2071
2072 r = -E2BIG;
2073 if (page_num >= blob_size)
2074 goto out;
2075 r = -ENOMEM;
ff5c2c03
SL		 2076 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2077 if (IS_ERR(page)) {
2078 r = PTR_ERR(page);
ffde22ac 2079 goto out;
ff5c2c03 2080 }
54bf36aa 2081 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2082 goto out_free;
2083 r = 0;
2084out_free:
2085 kfree(page);
2086out:
2087 return r;
2088}
2089
344d9588
GN		 2090static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2091{
2092 gpa_t gpa = data & ~0x3f;
2093
52a5c155
WL		 2094 /* Bits 3:5 are reserved, Should be zero */
2095 if (data & 0x38)
344d9588
GN		 2096 return 1;
2097
2098 vcpu->arch.apf.msr_val = data;
2099
2100 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2101 kvm_clear_async_pf_completion_queue(vcpu);
2102 kvm_async_pf_hash_reset(vcpu);
2103 return 0;
2104 }
2105
4e335d9e 2106 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2107 sizeof(u32)))
344d9588
GN		 2108 return 1;
2109
6adba527 2110 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2111 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2112 kvm_async_pf_wakeup_all(vcpu);
2113 return 0;
2114}
2115
12f9a48f
GC		 2116static void kvmclock_reset(struct kvm_vcpu *vcpu)
2117{
0b79459b 2118 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2119}
2120
c9aaa895
GC		 2121static void record_steal_time(struct kvm_vcpu *vcpu)
2122{
2123 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2124 return;
2125
4e335d9e 2126 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2127 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2128 return;
2129
0b9f6c46
PX		 2130 vcpu->arch.st.steal.preempted = 0;
2131
35f3fae1
WL		 2132 if (vcpu->arch.st.steal.version & 1)
2133 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2134
2135 vcpu->arch.st.steal.version += 1;
2136
4e335d9e 2137 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2138 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2139
2140 smp_wmb();
2141
c54cdf14
LC		 2142 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2143 vcpu->arch.st.last_steal;
2144 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2145
4e335d9e 2146 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2147 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2148
2149 smp_wmb();
2150
2151 vcpu->arch.st.steal.version += 1;
c9aaa895 2152
4e335d9e 2153 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2154 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2155}
2156
8fe8ab46 2157int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2158{
5753785f 2159 bool pr = false;
8fe8ab46
WA		 2160 u32 msr = msr_info->index;
2161 u64 data = msr_info->data;
5753785f 2162
15c4a640 2163 switch (msr) {
2e32b719
BP		 2164 case MSR_AMD64_NB_CFG:
2165 case MSR_IA32_UCODE_REV:
2166 case MSR_IA32_UCODE_WRITE:
2167 case MSR_VM_HSAVE_PA:
2168 case MSR_AMD64_PATCH_LOADER:
2169 case MSR_AMD64_BU_CFG2:
405a353a 2170 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2171 break;
2172
15c4a640 2173 case MSR_EFER:
b69e8cae 2174 return set_efer(vcpu, data);
8f1589d9
AP		 2175 case MSR_K7_HWCR:
2176 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2177 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2178 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2179 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2180 if (data != 0) {
a737f256
CD		 2181 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2182 data);
8f1589d9
AP		 2183 return 1;
2184 }
15c4a640 2185 break;
f7c6d140
AP		 2186 case MSR_FAM10H_MMIO_CONF_BASE:
2187 if (data != 0) {
a737f256
CD		 2188 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2189 "0x%llx\n", data);
f7c6d140
AP		 2190 return 1;
2191 }
15c4a640 2192 break;
b5e2fec0
AG		 2193 case MSR_IA32_DEBUGCTLMSR:
2194 if (!data) {
2195 /* We support the non-activated case already */
2196 break;
2197 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2198 /* Values other than LBR and BTF are vendor-specific,
2199 thus reserved and should throw a #GP */
2200 return 1;
2201 }
a737f256
CD		 2202 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2203 __func__, data);
b5e2fec0 2204 break;
9ba075a6 2205 case 0x200 ... 0x2ff:
ff53604b 2206 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2207 case MSR_IA32_APICBASE:
58cb628d 2208 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2209 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2210 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2211 case MSR_IA32_TSCDEADLINE:
2212 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2213 break;
ba904635 2214 case MSR_IA32_TSC_ADJUST:
d6321d49 2215 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2216 if (!msr_info->host_initiated) {
d913b904 2217 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2218 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2219 }
2220 vcpu->arch.ia32_tsc_adjust_msr = data;
2221 }
2222 break;
15c4a640 2223 case MSR_IA32_MISC_ENABLE:
ad312c7c 2224 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2225 break;
64d60670
PB		 2226 case MSR_IA32_SMBASE:
2227 if (!msr_info->host_initiated)
2228 return 1;
2229 vcpu->arch.smbase = data;
2230 break;
11c6bffa 2231 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2232 case MSR_KVM_WALL_CLOCK:
2233 vcpu->kvm->arch.wall_clock = data;
2234 kvm_write_wall_clock(vcpu->kvm, data);
2235 break;
11c6bffa 2236 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2237 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2238 struct kvm_arch *ka = &vcpu->kvm->arch;
2239
12f9a48f 2240 kvmclock_reset(vcpu);
18068523 2241
54750f2c
MT		 2242 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2243 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2244
2245 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2246 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2247
2248 ka->boot_vcpu_runs_old_kvmclock = tmp;
2249 }
2250
18068523 2251 vcpu->arch.time = data;
0061d53d 2252 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2253
2254 /* we verify if the enable bit is set... */
2255 if (!(data & 1))
2256 break;
2257
4e335d9e 2258 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2259 &vcpu->arch.pv_time, data & ~1ULL,
2260 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2261 vcpu->arch.pv_time_enabled = false;
2262 else
2263 vcpu->arch.pv_time_enabled = true;
32cad84f 2264
18068523
GOC		 2265 break;
2266 }
344d9588
GN		 2267 case MSR_KVM_ASYNC_PF_EN:
2268 if (kvm_pv_enable_async_pf(vcpu, data))
2269 return 1;
2270 break;
c9aaa895
GC		 2271 case MSR_KVM_STEAL_TIME:
2272
2273 if (unlikely(!sched_info_on()))
2274 return 1;
2275
2276 if (data & KVM_STEAL_RESERVED_MASK)
2277 return 1;
2278
4e335d9e 2279 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2280 data & KVM_STEAL_VALID_BITS,
2281 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2282 return 1;
2283
2284 vcpu->arch.st.msr_val = data;
2285
2286 if (!(data & KVM_MSR_ENABLED))
2287 break;
2288
c9aaa895
GC		 2289 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2290
2291 break;
ae7a2a3f
MT		 2292 case MSR_KVM_PV_EOI_EN:
2293 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2294 return 1;
2295 break;
c9aaa895 2296
890ca9ae
HY		 2297 case MSR_IA32_MCG_CTL:
2298 case MSR_IA32_MCG_STATUS:
81760dcc 2299 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2300 return set_msr_mce(vcpu, msr_info);
71db6023 2301
6912ac32
WH		 2302 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2303 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2304 pr = true; /* fall through */
2305 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2306 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2307 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2308 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2309
2310 if (pr || data != 0)
a737f256
CD		 2311 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2312 "0x%x data 0x%llx\n", msr, data);
5753785f 2313 break;
84e0cefa
JS		 2314 case MSR_K7_CLK_CTL:
2315 /*
2316 * Ignore all writes to this no longer documented MSR.
2317 * Writes are only relevant for old K7 processors,
2318 * all pre-dating SVM, but a recommended workaround from
4a969980 2319 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2320 * affected processor models on the command line, hence
2321 * the need to ignore the workaround.
2322 */
2323 break;
55cd8e5a 2324 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2325 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2326 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2327 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2328 return kvm_hv_set_msr_common(vcpu, msr, data,
2329 msr_info->host_initiated);
91c9c3ed 2330 case MSR_IA32_BBL_CR_CTL3:
2331 /* Drop writes to this legacy MSR -- see rdmsr
2332 * counterpart for further detail.
2333 */
fab0aa3b
EM		 2334 if (report_ignored_msrs)
2335 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2336 msr, data);
91c9c3ed 2337 break;
2b036c6b 2338 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2339 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2340 return 1;
2341 vcpu->arch.osvw.length = data;
2342 break;
2343 case MSR_AMD64_OSVW_STATUS:
d6321d49 2344 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2345 return 1;
2346 vcpu->arch.osvw.status = data;
2347 break;
db2336a8
KH		 2348 case MSR_PLATFORM_INFO:
2349 if (!msr_info->host_initiated ||
2350 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2351 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2352 cpuid_fault_enabled(vcpu)))
2353 return 1;
2354 vcpu->arch.msr_platform_info = data;
2355 break;
2356 case MSR_MISC_FEATURES_ENABLES:
2357 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2358 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2359 !supports_cpuid_fault(vcpu)))
2360 return 1;
2361 vcpu->arch.msr_misc_features_enables = data;
2362 break;
15c4a640 2363 default:
ffde22ac
ES		 2364 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2365 return xen_hvm_config(vcpu, data);
c6702c9d 2366 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2367 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2368 if (!ignore_msrs) {
ae0f5499 2369 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2370 msr, data);
ed85c068
AP		 2371 return 1;
2372 } else {
fab0aa3b
EM		 2373 if (report_ignored_msrs)
2374 vcpu_unimpl(vcpu,
2375 "ignored wrmsr: 0x%x data 0x%llx\n",
2376 msr, data);
ed85c068
AP		 2377 break;
2378 }
15c4a640
CO		 2379 }
2380 return 0;
2381}
2382EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2383
2384
2385/*
2386 * Reads an msr value (of 'msr_index') into 'pdata'.
2387 * Returns 0 on success, non-0 otherwise.
2388 * Assumes vcpu_load() was already called.
2389 */
609e36d3 2390int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2391{
609e36d3 2392 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2393}
ff651cb6 2394EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2395
890ca9ae 2396static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2397{
2398 u64 data;
890ca9ae
HY		 2399 u64 mcg_cap = vcpu->arch.mcg_cap;
2400 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2401
2402 switch (msr) {
15c4a640
CO		 2403 case MSR_IA32_P5_MC_ADDR:
2404 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2405 data = 0;
2406 break;
15c4a640 2407 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2408 data = vcpu->arch.mcg_cap;
2409 break;
c7ac679c 2410 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2411 if (!(mcg_cap & MCG_CTL_P))
2412 return 1;
2413 data = vcpu->arch.mcg_ctl;
2414 break;
2415 case MSR_IA32_MCG_STATUS:
2416 data = vcpu->arch.mcg_status;
2417 break;
2418 default:
2419 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2420 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2421 u32 offset = msr - MSR_IA32_MC0_CTL;
2422 data = vcpu->arch.mce_banks[offset];
2423 break;
2424 }
2425 return 1;
2426 }
2427 *pdata = data;
2428 return 0;
2429}
2430
609e36d3 2431int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2432{
609e36d3 2433 switch (msr_info->index) {
890ca9ae 2434 case MSR_IA32_PLATFORM_ID:
15c4a640 2435 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2436 case MSR_IA32_DEBUGCTLMSR:
2437 case MSR_IA32_LASTBRANCHFROMIP:
2438 case MSR_IA32_LASTBRANCHTOIP:
2439 case MSR_IA32_LASTINTFROMIP:
2440 case MSR_IA32_LASTINTTOIP:
60af2ecd 2441 case MSR_K8_SYSCFG:
3afb1121
PB		 2442 case MSR_K8_TSEG_ADDR:
2443 case MSR_K8_TSEG_MASK:
60af2ecd 2444 case MSR_K7_HWCR:
61a6bd67 2445 case MSR_VM_HSAVE_PA:
1fdbd48c 2446 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2447 case MSR_AMD64_NB_CFG:
f7c6d140 2448 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2449 case MSR_AMD64_BU_CFG2:
0c2df2a1 2450 case MSR_IA32_PERF_CTL:
405a353a 2451 case MSR_AMD64_DC_CFG:
609e36d3 2452 msr_info->data = 0;
15c4a640 2453 break;
6912ac32
WH		 2454 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2455 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2456 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2457 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2458 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2459 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2460 msr_info->data = 0;
5753785f 2461 break;
742bc670 2462 case MSR_IA32_UCODE_REV:
609e36d3 2463 msr_info->data = 0x100000000ULL;
742bc670 2464 break;
9ba075a6 2465 case MSR_MTRRcap:
9ba075a6 2466 case 0x200 ... 0x2ff:
ff53604b 2467 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2468 case 0xcd: /* fsb frequency */
609e36d3 2469 msr_info->data = 3;
15c4a640 2470 break;
7b914098
JS		 2471 /*
2472 * MSR_EBC_FREQUENCY_ID
2473 * Conservative value valid for even the basic CPU models.
2474 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2475 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2476 * and 266MHz for model 3, or 4. Set Core Clock
2477 * Frequency to System Bus Frequency Ratio to 1 (bits
2478 * 31:24) even though these are only valid for CPU
2479 * models > 2, however guests may end up dividing or
2480 * multiplying by zero otherwise.
2481 */
2482 case MSR_EBC_FREQUENCY_ID:
609e36d3 2483 msr_info->data = 1 << 24;
7b914098 2484 break;
15c4a640 2485 case MSR_IA32_APICBASE:
609e36d3 2486 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2487 break;
0105d1a5 2488 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2489 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2490 break;
a3e06bbe 2491 case MSR_IA32_TSCDEADLINE:
609e36d3 2492 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2493 break;
ba904635 2494 case MSR_IA32_TSC_ADJUST:
609e36d3 2495 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2496 break;
15c4a640 2497 case MSR_IA32_MISC_ENABLE:
609e36d3 2498 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2499 break;
64d60670
PB		 2500 case MSR_IA32_SMBASE:
2501 if (!msr_info->host_initiated)
2502 return 1;
2503 msr_info->data = vcpu->arch.smbase;
15c4a640 2504 break;
847f0ad8
AG		 2505 case MSR_IA32_PERF_STATUS:
2506 /* TSC increment by tick */
609e36d3 2507 msr_info->data = 1000ULL;
847f0ad8 2508 /* CPU multiplier */
b0996ae4 2509 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2510 break;
15c4a640 2511 case MSR_EFER:
609e36d3 2512 msr_info->data = vcpu->arch.efer;
15c4a640 2513 break;
18068523 2514 case MSR_KVM_WALL_CLOCK:
11c6bffa 2515 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2516 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2517 break;
2518 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2519 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2520 msr_info->data = vcpu->arch.time;
18068523 2521 break;
344d9588 2522 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2523 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2524 break;
c9aaa895 2525 case MSR_KVM_STEAL_TIME:
609e36d3 2526 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2527 break;
1d92128f 2528 case MSR_KVM_PV_EOI_EN:
609e36d3 2529 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2530 break;
890ca9ae
HY		 2531 case MSR_IA32_P5_MC_ADDR:
2532 case MSR_IA32_P5_MC_TYPE:
2533 case MSR_IA32_MCG_CAP:
2534 case MSR_IA32_MCG_CTL:
2535 case MSR_IA32_MCG_STATUS:
81760dcc 2536 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2537 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2538 case MSR_K7_CLK_CTL:
2539 /*
2540 * Provide expected ramp-up count for K7. All other
2541 * are set to zero, indicating minimum divisors for
2542 * every field.
2543 *
2544 * This prevents guest kernels on AMD host with CPU
2545 * type 6, model 8 and higher from exploding due to
2546 * the rdmsr failing.
2547 */
609e36d3 2548 msr_info->data = 0x20000000;
84e0cefa 2549 break;
55cd8e5a 2550 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2551 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2552 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2553 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2554 return kvm_hv_get_msr_common(vcpu,
2555 msr_info->index, &msr_info->data);
55cd8e5a 2556 break;
91c9c3ed 2557 case MSR_IA32_BBL_CR_CTL3:
2558 /* This legacy MSR exists but isn't fully documented in current
2559 * silicon. It is however accessed by winxp in very narrow
2560 * scenarios where it sets bit #19, itself documented as
2561 * a "reserved" bit. Best effort attempt to source coherent
2562 * read data here should the balance of the register be
2563 * interpreted by the guest:
2564 *
2565 * L2 cache control register 3: 64GB range, 256KB size,
2566 * enabled, latency 0x1, configured
2567 */
609e36d3 2568 msr_info->data = 0xbe702111;
91c9c3ed 2569 break;
2b036c6b 2570 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2571 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2572 return 1;
609e36d3 2573 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2574 break;
2575 case MSR_AMD64_OSVW_STATUS:
d6321d49 2576 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2577 return 1;
609e36d3 2578 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2579 break;
db2336a8
KH		 2580 case MSR_PLATFORM_INFO:
2581 msr_info->data = vcpu->arch.msr_platform_info;
2582 break;
2583 case MSR_MISC_FEATURES_ENABLES:
2584 msr_info->data = vcpu->arch.msr_misc_features_enables;
2585 break;
15c4a640 2586 default:
c6702c9d 2587 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2588 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2589 if (!ignore_msrs) {
ae0f5499
BD		 2590 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2591 msr_info->index);
ed85c068
AP		 2592 return 1;
2593 } else {
fab0aa3b
EM		 2594 if (report_ignored_msrs)
2595 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2596 msr_info->index);
609e36d3 2597 msr_info->data = 0;
ed85c068
AP		 2598 }
2599 break;
15c4a640 2600 }
15c4a640
CO		 2601 return 0;
2602}
2603EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2604
313a3dc7
CO		 2605/*
2606 * Read or write a bunch of msrs. All parameters are kernel addresses.
2607 *
2608 * @return number of msrs set successfully.
2609 */
2610static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2611 struct kvm_msr_entry *entries,
2612 int (*do_msr)(struct kvm_vcpu *vcpu,
2613 unsigned index, u64 *data))
2614{
f656ce01 2615 int i, idx;
313a3dc7 2616
f656ce01 2617 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2618 for (i = 0; i < msrs->nmsrs; ++i)
2619 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2620 break;
f656ce01 2621 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2622
313a3dc7
CO		 2623 return i;
2624}
2625
2626/*
2627 * Read or write a bunch of msrs. Parameters are user addresses.
2628 *
2629 * @return number of msrs set successfully.
2630 */
2631static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2632 int (*do_msr)(struct kvm_vcpu *vcpu,
2633 unsigned index, u64 *data),
2634 int writeback)
2635{
2636 struct kvm_msrs msrs;
2637 struct kvm_msr_entry *entries;
2638 int r, n;
2639 unsigned size;
2640
2641 r = -EFAULT;
2642 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2643 goto out;
2644
2645 r = -E2BIG;
2646 if (msrs.nmsrs >= MAX_IO_MSRS)
2647 goto out;
2648
313a3dc7 2649 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2650 entries = memdup_user(user_msrs->entries, size);
2651 if (IS_ERR(entries)) {
2652 r = PTR_ERR(entries);
313a3dc7 2653 goto out;
ff5c2c03 2654 }
313a3dc7
CO		 2655
2656 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2657 if (r < 0)
2658 goto out_free;
2659
2660 r = -EFAULT;
2661 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2662 goto out_free;
2663
2664 r = n;
2665
2666out_free:
7a73c028 2667 kfree(entries);
313a3dc7
CO		 2668out:
2669 return r;
2670}
2671
784aa3d7 2672int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2673{
2674 int r;
2675
2676 switch (ext) {
2677 case KVM_CAP_IRQCHIP:
2678 case KVM_CAP_HLT:
2679 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2680 case KVM_CAP_SET_TSS_ADDR:
07716717 2681 case KVM_CAP_EXT_CPUID:
9c15bb1d 2682 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2683 case KVM_CAP_CLOCKSOURCE:
7837699f 2684 case KVM_CAP_PIT:
a28e4f5a 2685 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2686 case KVM_CAP_MP_STATE:
ed848624 2687 case KVM_CAP_SYNC_MMU:
a355c85c 2688 case KVM_CAP_USER_NMI:
52d939a0 2689 case KVM_CAP_REINJECT_CONTROL:
4925663a 2690 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2691 case KVM_CAP_IOEVENTFD:
f848a5a8 2692 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2693 case KVM_CAP_PIT2:
e9f42757 2694 case KVM_CAP_PIT_STATE2:
b927a3ce 2695 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2696 case KVM_CAP_XEN_HVM:
3cfc3092 2697 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2698 case KVM_CAP_HYPERV:
10388a07 2699 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2700 case KVM_CAP_HYPERV_SPIN:
5c919412 2701 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2702 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2703 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2704 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2705 case KVM_CAP_DEBUGREGS:
d2be1651 2706 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2707 case KVM_CAP_XSAVE:
344d9588 2708 case KVM_CAP_ASYNC_PF:
92a1f12d 2709 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2710 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2711 case KVM_CAP_READONLY_MEM:
5f66b620 2712 case KVM_CAP_HYPERV_TIME:
100943c5 2713 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2714 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2715 case KVM_CAP_ENABLE_CAP_VM:
2716 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2717 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2718 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2719 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2720 r = 1;
2721 break;
e3fd9a93
PB		 2722 case KVM_CAP_ADJUST_CLOCK:
2723 r = KVM_CLOCK_TSC_STABLE;
2724 break;
668fffa3
MT		 2725 case KVM_CAP_X86_GUEST_MWAIT:
2726 r = kvm_mwait_in_guest();
2727 break;
6d396b55
PB		 2728 case KVM_CAP_X86_SMM:
2729 /* SMBASE is usually relocated above 1M on modern chipsets,
2730 * and SMM handlers might indeed rely on 4G segment limits,
2731 * so do not report SMM to be available if real mode is
2732 * emulated via vm86 mode. Still, do not go to great lengths
2733 * to avoid userspace's usage of the feature, because it is a
2734 * fringe case that is not enabled except via specific settings
2735 * of the module parameters.
2736 */
2737 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2738 break;
774ead3a
AK		 2739 case KVM_CAP_VAPIC:
2740 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2741 break;
f725230a 2742 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2743 r = KVM_SOFT_MAX_VCPUS;
2744 break;
2745 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2746 r = KVM_MAX_VCPUS;
2747 break;
a988b910 2748 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2749 r = KVM_USER_MEM_SLOTS;
a988b910 2750 break;
a68a6a72
MT		 2751 case KVM_CAP_PV_MMU: /* obsolete */
2752 r = 0;
2f333bcb 2753 break;
890ca9ae
HY		 2754 case KVM_CAP_MCE:
2755 r = KVM_MAX_MCE_BANKS;
2756 break;
2d5b5a66 2757 case KVM_CAP_XCRS:
d366bf7e 2758 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2759 break;
92a1f12d
JR		 2760 case KVM_CAP_TSC_CONTROL:
2761 r = kvm_has_tsc_control;
2762 break;
37131313
RK		 2763 case KVM_CAP_X2APIC_API:
2764 r = KVM_X2APIC_API_VALID_FLAGS;
2765 break;
018d00d2
ZX		 2766 default:
2767 r = 0;
2768 break;
2769 }
2770 return r;
2771
2772}
2773
043405e1
CO		 2774long kvm_arch_dev_ioctl(struct file *filp,
2775 unsigned int ioctl, unsigned long arg)
2776{
2777 void __user *argp = (void __user *)arg;
2778 long r;
2779
2780 switch (ioctl) {
2781 case KVM_GET_MSR_INDEX_LIST: {
2782 struct kvm_msr_list __user *user_msr_list = argp;
2783 struct kvm_msr_list msr_list;
2784 unsigned n;
2785
2786 r = -EFAULT;
2787 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2788 goto out;
2789 n = msr_list.nmsrs;
62ef68bb 2790 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2791 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2792 goto out;
2793 r = -E2BIG;
e125e7b6 2794 if (n < msr_list.nmsrs)
043405e1
CO		 2795 goto out;
2796 r = -EFAULT;
2797 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2798 num_msrs_to_save * sizeof(u32)))
2799 goto out;
e125e7b6 2800 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2801 &emulated_msrs,
62ef68bb 2802 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2803 goto out;
2804 r = 0;
2805 break;
2806 }
9c15bb1d
BP		 2807 case KVM_GET_SUPPORTED_CPUID:
2808 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2809 struct kvm_cpuid2 __user *cpuid_arg = argp;
2810 struct kvm_cpuid2 cpuid;
2811
2812 r = -EFAULT;
2813 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2814 goto out;
9c15bb1d
BP		 2815
2816 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2817 ioctl);
674eea0f
AK		 2818 if (r)
2819 goto out;
2820
2821 r = -EFAULT;
2822 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2823 goto out;
2824 r = 0;
2825 break;
2826 }
890ca9ae 2827 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2828 r = -EFAULT;
c45dcc71
AR		 2829 if (copy_to_user(argp, &kvm_mce_cap_supported,
2830 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2831 goto out;
2832 r = 0;
2833 break;
2834 }
043405e1
CO		 2835 default:
2836 r = -EINVAL;
2837 }
2838out:
2839 return r;
2840}
2841
f5f48ee1
SY		 2842static void wbinvd_ipi(void *garbage)
2843{
2844 wbinvd();
2845}
2846
2847static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2848{
e0f0bbc5 2849 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2850}
2851
313a3dc7
CO		 2852void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2853{
f5f48ee1
SY		 2854 /* Address WBINVD may be executed by guest */
2855 if (need_emulate_wbinvd(vcpu)) {
2856 if (kvm_x86_ops->has_wbinvd_exit())
2857 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2858 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2859 smp_call_function_single(vcpu->cpu,
2860 wbinvd_ipi, NULL, 1);
2861 }
2862
313a3dc7 2863 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2864
0dd6a6ed
ZA		 2865 /* Apply any externally detected TSC adjustments (due to suspend) */
2866 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2867 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2868 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2869 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2870 }
8f6055cb 2871
48434c20 2872 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2873 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2874 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2875 if (tsc_delta < 0)
2876 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2877
c285545f 2878 if (check_tsc_unstable()) {
07c1419a 2879 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2880 vcpu->arch.last_guest_tsc);
a545ab6a 2881 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2882 vcpu->arch.tsc_catchup = 1;
c285545f 2883 }
a749e247
PB		 2884
2885 if (kvm_lapic_hv_timer_in_use(vcpu))
2886 kvm_lapic_restart_hv_timer(vcpu);
2887
d98d07ca
MT		 2888 /*
2889 * On a host with synchronized TSC, there is no need to update
2890 * kvmclock on vcpu->cpu migration
2891 */
2892 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2893 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2894 if (vcpu->cpu != cpu)
1bd2009e 2895 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2896 vcpu->cpu = cpu;
6b7d7e76 2897 }
c9aaa895 2898
c9aaa895 2899 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2900}
2901
0b9f6c46
PX		 2902static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2903{
2904 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2905 return;
2906
2907 vcpu->arch.st.steal.preempted = 1;
2908
4e335d9e 2909 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2910 &vcpu->arch.st.steal.preempted,
2911 offsetof(struct kvm_steal_time, preempted),
2912 sizeof(vcpu->arch.st.steal.preempted));
2913}
2914
313a3dc7
CO		 2915void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2916{
cc0d907c 2917 int idx;
de63ad4c
LM		 2918
2919 if (vcpu->preempted)
2920 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2921
931f261b
AA		 2922 /*
2923 * Disable page faults because we're in atomic context here.
2924 * kvm_write_guest_offset_cached() would call might_fault()
2925 * that relies on pagefault_disable() to tell if there's a
2926 * bug. NOTE: the write to guest memory may not go through if
2927 * during postcopy live migration or if there's heavy guest
2928 * paging.
2929 */
2930 pagefault_disable();
cc0d907c
AA		 2931 /*
2932 * kvm_memslots() will be called by
2933 * kvm_write_guest_offset_cached() so take the srcu lock.
2934 */
2935 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2936 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2937 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2938 pagefault_enable();
02daab21 2939 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2940 kvm_put_guest_fpu(vcpu);
4ea1636b 2941 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2942}
2943
313a3dc7
CO		 2944static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2945 struct kvm_lapic_state *s)
2946{
76dfafd5 2947 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2948 kvm_x86_ops->sync_pir_to_irr(vcpu);
2949
a92e2543 2950 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2951}
2952
2953static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2954 struct kvm_lapic_state *s)
2955{
a92e2543
RK		 2956 int r;
2957
2958 r = kvm_apic_set_state(vcpu, s);
2959 if (r)
2960 return r;
cb142eb7 2961 update_cr8_intercept(vcpu);
313a3dc7
CO		 2962
2963 return 0;
2964}
2965
127a457a
MG		 2966static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2967{
2968 return (!lapic_in_kernel(vcpu) ||
2969 kvm_apic_accept_pic_intr(vcpu));
2970}
2971
782d422b
MG		 2972/*
2973 * if userspace requested an interrupt window, check that the
2974 * interrupt window is open.
2975 *
2976 * No need to exit to userspace if we already have an interrupt queued.
2977 */
2978static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2979{
2980 return kvm_arch_interrupt_allowed(vcpu) &&
2981 !kvm_cpu_has_interrupt(vcpu) &&
2982 !kvm_event_needs_reinjection(vcpu) &&
2983 kvm_cpu_accept_dm_intr(vcpu);
2984}
2985
f77bc6a4
ZX		 2986static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2987 struct kvm_interrupt *irq)
2988{
02cdb50f 2989 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2990 return -EINVAL;
1c1a9ce9
SR		 2991
2992 if (!irqchip_in_kernel(vcpu->kvm)) {
2993 kvm_queue_interrupt(vcpu, irq->irq, false);
2994 kvm_make_request(KVM_REQ_EVENT, vcpu);
2995 return 0;
2996 }
2997
2998 /*
2999 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3000 * fail for in-kernel 8259.
3001 */
3002 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3003 return -ENXIO;
f77bc6a4 3004
1c1a9ce9
SR		 3005 if (vcpu->arch.pending_external_vector != -1)
3006 return -EEXIST;
f77bc6a4 3007
1c1a9ce9 3008 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3009 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3010 return 0;
3011}
3012
c4abb7c9
JK		 3013static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3014{
c4abb7c9 3015 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3016
3017 return 0;
3018}
3019
f077825a
PB		 3020static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3021{
64d60670
PB		 3022 kvm_make_request(KVM_REQ_SMI, vcpu);
3023
f077825a
PB		 3024 return 0;
3025}
3026
b209749f
AK		 3027static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3028 struct kvm_tpr_access_ctl *tac)
3029{
3030 if (tac->flags)
3031 return -EINVAL;
3032 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3033 return 0;
3034}
3035
890ca9ae
HY		 3036static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3037 u64 mcg_cap)
3038{
3039 int r;
3040 unsigned bank_num = mcg_cap & 0xff, bank;
3041
3042 r = -EINVAL;
a9e38c3e 3043 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3044 goto out;
c45dcc71 3045 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3046 goto out;
3047 r = 0;
3048 vcpu->arch.mcg_cap = mcg_cap;
3049 /* Init IA32_MCG_CTL to all 1s */
3050 if (mcg_cap & MCG_CTL_P)
3051 vcpu->arch.mcg_ctl = ~(u64)0;
3052 /* Init IA32_MCi_CTL to all 1s */
3053 for (bank = 0; bank < bank_num; bank++)
3054 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3055
3056 if (kvm_x86_ops->setup_mce)
3057 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3058out:
3059 return r;
3060}
3061
3062static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3063 struct kvm_x86_mce *mce)
3064{
3065 u64 mcg_cap = vcpu->arch.mcg_cap;
3066 unsigned bank_num = mcg_cap & 0xff;
3067 u64 *banks = vcpu->arch.mce_banks;
3068
3069 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3070 return -EINVAL;
3071 /*
3072 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3073 * reporting is disabled
3074 */
3075 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3076 vcpu->arch.mcg_ctl != ~(u64)0)
3077 return 0;
3078 banks += 4 * mce->bank;
3079 /*
3080 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3081 * reporting is disabled for the bank
3082 */
3083 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3084 return 0;
3085 if (mce->status & MCI_STATUS_UC) {
3086 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3087 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3088 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3089 return 0;
3090 }
3091 if (banks[1] & MCI_STATUS_VAL)
3092 mce->status |= MCI_STATUS_OVER;
3093 banks[2] = mce->addr;
3094 banks[3] = mce->misc;
3095 vcpu->arch.mcg_status = mce->mcg_status;
3096 banks[1] = mce->status;
3097 kvm_queue_exception(vcpu, MC_VECTOR);
3098 } else if (!(banks[1] & MCI_STATUS_VAL)
3099 || !(banks[1] & MCI_STATUS_UC)) {
3100 if (banks[1] & MCI_STATUS_VAL)
3101 mce->status |= MCI_STATUS_OVER;
3102 banks[2] = mce->addr;
3103 banks[3] = mce->misc;
3104 banks[1] = mce->status;
3105 } else
3106 banks[1] |= MCI_STATUS_OVER;
3107 return 0;
3108}
3109
3cfc3092
JK		 3110static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3111 struct kvm_vcpu_events *events)
3112{
7460fb4a 3113 process_nmi(vcpu);
664f8e26
WL		 3114 /*
3115 * FIXME: pass injected and pending separately. This is only
3116 * needed for nested virtualization, whose state cannot be
3117 * migrated yet. For now we can combine them.
3118 */
03b82a30 3119 events->exception.injected =
664f8e26
WL		 3120 (vcpu->arch.exception.pending ||
3121 vcpu->arch.exception.injected) &&
03b82a30 3122 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3123 events->exception.nr = vcpu->arch.exception.nr;
3124 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3125 events->exception.pad = 0;
3cfc3092
JK		 3126 events->exception.error_code = vcpu->arch.exception.error_code;
3127
03b82a30
JK		 3128 events->interrupt.injected =
3129 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3130 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3131 events->interrupt.soft = 0;
37ccdcbe 3132 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3133
3134 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3135 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3136 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3137 events->nmi.pad = 0;
3cfc3092 3138
66450a21 3139 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3140
f077825a
PB		 3141 events->smi.smm = is_smm(vcpu);
3142 events->smi.pending = vcpu->arch.smi_pending;
3143 events->smi.smm_inside_nmi =
3144 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3145 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3146
dab4b911 3147 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3148 | KVM_VCPUEVENT_VALID_SHADOW
3149 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3150 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3151}
3152
6ef4e07e
XG		 3153static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3154
3cfc3092
JK		 3155static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3156 struct kvm_vcpu_events *events)
3157{
dab4b911 3158 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3159 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3160 | KVM_VCPUEVENT_VALID_SHADOW
3161 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3162 return -EINVAL;
3163
78e546c8 3164 if (events->exception.injected &&
28d06353
JM		 3165 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3166 is_guest_mode(vcpu)))
78e546c8
PB		 3167 return -EINVAL;
3168
28bf2888
DH		 3169 /* INITs are latched while in SMM */
3170 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3171 (events->smi.smm || events->smi.pending) &&
3172 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3173 return -EINVAL;
3174
7460fb4a 3175 process_nmi(vcpu);
664f8e26 3176 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3177 vcpu->arch.exception.pending = events->exception.injected;
3178 vcpu->arch.exception.nr = events->exception.nr;
3179 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3180 vcpu->arch.exception.error_code = events->exception.error_code;
3181
3182 vcpu->arch.interrupt.pending = events->interrupt.injected;
3183 vcpu->arch.interrupt.nr = events->interrupt.nr;
3184 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3185 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3186 kvm_x86_ops->set_interrupt_shadow(vcpu,
3187 events->interrupt.shadow);
3cfc3092
JK		 3188
3189 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3190 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3191 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3192 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3193
66450a21 3194 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3195 lapic_in_kernel(vcpu))
66450a21 3196 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3197
f077825a 3198 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3199 u32 hflags = vcpu->arch.hflags;
f077825a 3200 if (events->smi.smm)
6ef4e07e 3201 hflags |= HF_SMM_MASK;
f077825a 3202 else
6ef4e07e
XG		 3203 hflags &= ~HF_SMM_MASK;
3204 kvm_set_hflags(vcpu, hflags);
3205
f077825a 3206 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3207
3208 if (events->smi.smm) {
3209 if (events->smi.smm_inside_nmi)
3210 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3211 else
f4ef1910
WL		 3212 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3213 if (lapic_in_kernel(vcpu)) {
3214 if (events->smi.latched_init)
3215 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3216 else
3217 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3218 }
f077825a
PB		 3219 }
3220 }
3221
3842d135
AK		 3222 kvm_make_request(KVM_REQ_EVENT, vcpu);
3223
3cfc3092
JK		 3224 return 0;
3225}
3226
a1efbe77
JK		 3227static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3228 struct kvm_debugregs *dbgregs)
3229{
73aaf249
JK		 3230 unsigned long val;
3231
a1efbe77 3232 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3233 kvm_get_dr(vcpu, 6, &val);
73aaf249 3234 dbgregs->dr6 = val;
a1efbe77
JK		 3235 dbgregs->dr7 = vcpu->arch.dr7;
3236 dbgregs->flags = 0;
97e69aa6 3237 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3238}
3239
3240static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3241 struct kvm_debugregs *dbgregs)
3242{
3243 if (dbgregs->flags)
3244 return -EINVAL;
3245
d14bdb55
PB		 3246 if (dbgregs->dr6 & ~0xffffffffull)
3247 return -EINVAL;
3248 if (dbgregs->dr7 & ~0xffffffffull)
3249 return -EINVAL;
3250
a1efbe77 3251 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3252 kvm_update_dr0123(vcpu);
a1efbe77 3253 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3254 kvm_update_dr6(vcpu);
a1efbe77 3255 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3256 kvm_update_dr7(vcpu);
a1efbe77 3257
a1efbe77
JK		 3258 return 0;
3259}
3260
df1daba7
PB		 3261#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3262
3263static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3264{
c47ada30 3265 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3266 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3267 u64 valid;
3268
3269 /*
3270 * Copy legacy XSAVE area, to avoid complications with CPUID
3271 * leaves 0 and 1 in the loop below.
3272 */
3273 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3274
3275 /* Set XSTATE_BV */
00c87e9a 3276 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3277 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3278
3279 /*
3280 * Copy each region from the possibly compacted offset to the
3281 * non-compacted offset.
3282 */
d91cab78 3283 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3284 while (valid) {
3285 u64 feature = valid & -valid;
3286 int index = fls64(feature) - 1;
3287 void *src = get_xsave_addr(xsave, feature);
3288
3289 if (src) {
3290 u32 size, offset, ecx, edx;
3291 cpuid_count(XSTATE_CPUID, index,
3292 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3293 if (feature == XFEATURE_MASK_PKRU)
3294 memcpy(dest + offset, &vcpu->arch.pkru,
3295 sizeof(vcpu->arch.pkru));
3296 else
3297 memcpy(dest + offset, src, size);
3298
df1daba7
PB		 3299 }
3300
3301 valid -= feature;
3302 }
3303}
3304
3305static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3306{
c47ada30 3307 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3308 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3309 u64 valid;
3310
3311 /*
3312 * Copy legacy XSAVE area, to avoid complications with CPUID
3313 * leaves 0 and 1 in the loop below.
3314 */
3315 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3316
3317 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3318 xsave->header.xfeatures = xstate_bv;
782511b0 3319 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3320 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3321
3322 /*
3323 * Copy each region from the non-compacted offset to the
3324 * possibly compacted offset.
3325 */
d91cab78 3326 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3327 while (valid) {
3328 u64 feature = valid & -valid;
3329 int index = fls64(feature) - 1;
3330 void *dest = get_xsave_addr(xsave, feature);
3331
3332 if (dest) {
3333 u32 size, offset, ecx, edx;
3334 cpuid_count(XSTATE_CPUID, index,
3335 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3336 if (feature == XFEATURE_MASK_PKRU)
3337 memcpy(&vcpu->arch.pkru, src + offset,
3338 sizeof(vcpu->arch.pkru));
3339 else
3340 memcpy(dest, src + offset, size);
ee4100da 3341 }
df1daba7
PB		 3342
3343 valid -= feature;
3344 }
3345}
3346
2d5b5a66
SY		 3347static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3348 struct kvm_xsave *guest_xsave)
3349{
d366bf7e 3350 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3351 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3352 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3353 } else {
2d5b5a66 3354 memcpy(guest_xsave->region,
7366ed77 3355 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3356 sizeof(struct fxregs_state));
2d5b5a66 3357 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3358 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3359 }
3360}
3361
a575813b
WL		 3362#define XSAVE_MXCSR_OFFSET 24
3363
2d5b5a66
SY		 3364static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3365 struct kvm_xsave *guest_xsave)
3366{
3367 u64 xstate_bv =
3368 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3369 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3370
d366bf7e 3371 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3372 /*
3373 * Here we allow setting states that are not present in
3374 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3375 * with old userspace.
3376 */
a575813b
WL		 3377 if (xstate_bv & ~kvm_supported_xcr0() ||
3378 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3379 return -EINVAL;
df1daba7 3380 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3381 } else {
a575813b
WL		 3382 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3383 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3384 return -EINVAL;
7366ed77 3385 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3386 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3387 }
3388 return 0;
3389}
3390
3391static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3392 struct kvm_xcrs *guest_xcrs)
3393{
d366bf7e 3394 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3395 guest_xcrs->nr_xcrs = 0;
3396 return;
3397 }
3398
3399 guest_xcrs->nr_xcrs = 1;
3400 guest_xcrs->flags = 0;
3401 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3402 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3403}
3404
3405static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3406 struct kvm_xcrs *guest_xcrs)
3407{
3408 int i, r = 0;
3409
d366bf7e 3410 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3411 return -EINVAL;
3412
3413 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3414 return -EINVAL;
3415
3416 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3417 /* Only support XCR0 currently */
c67a04cb 3418 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3419 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3420 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3421 break;
3422 }
3423 if (r)
3424 r = -EINVAL;
3425 return r;
3426}
3427
1c0b28c2
EM		 3428/*
3429 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3430 * stopped by the hypervisor. This function will be called from the host only.
3431 * EINVAL is returned when the host attempts to set the flag for a guest that
3432 * does not support pv clocks.
3433 */
3434static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3435{
0b79459b 3436 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3437 return -EINVAL;
51d59c6b 3438 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3439 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3440 return 0;
3441}
3442
5c919412
AS		 3443static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3444 struct kvm_enable_cap *cap)
3445{
3446 if (cap->flags)
3447 return -EINVAL;
3448
3449 switch (cap->cap) {
efc479e6
RK		 3450 case KVM_CAP_HYPERV_SYNIC2:
3451 if (cap->args[0])
3452 return -EINVAL;
5c919412 3453 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3454 if (!irqchip_in_kernel(vcpu->kvm))
3455 return -EINVAL;
efc479e6
RK		 3456 return kvm_hv_activate_synic(vcpu, cap->cap ==
3457 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3458 default:
3459 return -EINVAL;
3460 }
3461}
3462
313a3dc7
CO		 3463long kvm_arch_vcpu_ioctl(struct file *filp,
3464 unsigned int ioctl, unsigned long arg)
3465{
3466 struct kvm_vcpu *vcpu = filp->private_data;
3467 void __user *argp = (void __user *)arg;
3468 int r;
d1ac91d8
AK		 3469 union {
3470 struct kvm_lapic_state *lapic;
3471 struct kvm_xsave *xsave;
3472 struct kvm_xcrs *xcrs;
3473 void *buffer;
3474 } u;
3475
3476 u.buffer = NULL;
313a3dc7
CO		 3477 switch (ioctl) {
3478 case KVM_GET_LAPIC: {
2204ae3c 3479 r = -EINVAL;
bce87cce 3480 if (!lapic_in_kernel(vcpu))
2204ae3c 3481 goto out;
d1ac91d8 3482 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3483
b772ff36 3484 r = -ENOMEM;
d1ac91d8 3485 if (!u.lapic)
b772ff36 3486 goto out;
d1ac91d8 3487 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3488 if (r)
3489 goto out;
3490 r = -EFAULT;
d1ac91d8 3491 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3492 goto out;
3493 r = 0;
3494 break;
3495 }
3496 case KVM_SET_LAPIC: {
2204ae3c 3497 r = -EINVAL;
bce87cce 3498 if (!lapic_in_kernel(vcpu))
2204ae3c 3499 goto out;
ff5c2c03 3500 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3501 if (IS_ERR(u.lapic))
3502 return PTR_ERR(u.lapic);
ff5c2c03 3503
d1ac91d8 3504 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3505 break;
3506 }
f77bc6a4
ZX		 3507 case KVM_INTERRUPT: {
3508 struct kvm_interrupt irq;
3509
3510 r = -EFAULT;
3511 if (copy_from_user(&irq, argp, sizeof irq))
3512 goto out;
3513 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3514 break;
3515 }
c4abb7c9
JK		 3516 case KVM_NMI: {
3517 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3518 break;
3519 }
f077825a
PB		 3520 case KVM_SMI: {
3521 r = kvm_vcpu_ioctl_smi(vcpu);
3522 break;
3523 }
313a3dc7
CO		 3524 case KVM_SET_CPUID: {
3525 struct kvm_cpuid __user *cpuid_arg = argp;
3526 struct kvm_cpuid cpuid;
3527
3528 r = -EFAULT;
3529 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3530 goto out;
3531 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3532 break;
3533 }
07716717
DK		 3534 case KVM_SET_CPUID2: {
3535 struct kvm_cpuid2 __user *cpuid_arg = argp;
3536 struct kvm_cpuid2 cpuid;
3537
3538 r = -EFAULT;
3539 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3540 goto out;
3541 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3542 cpuid_arg->entries);
07716717
DK		 3543 break;
3544 }
3545 case KVM_GET_CPUID2: {
3546 struct kvm_cpuid2 __user *cpuid_arg = argp;
3547 struct kvm_cpuid2 cpuid;
3548
3549 r = -EFAULT;
3550 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3551 goto out;
3552 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3553 cpuid_arg->entries);
07716717
DK		 3554 if (r)
3555 goto out;
3556 r = -EFAULT;
3557 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3558 goto out;
3559 r = 0;
3560 break;
3561 }
313a3dc7 3562 case KVM_GET_MSRS:
609e36d3 3563 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3564 break;
3565 case KVM_SET_MSRS:
3566 r = msr_io(vcpu, argp, do_set_msr, 0);
3567 break;
b209749f
AK		 3568 case KVM_TPR_ACCESS_REPORTING: {
3569 struct kvm_tpr_access_ctl tac;
3570
3571 r = -EFAULT;
3572 if (copy_from_user(&tac, argp, sizeof tac))
3573 goto out;
3574 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3575 if (r)
3576 goto out;
3577 r = -EFAULT;
3578 if (copy_to_user(argp, &tac, sizeof tac))
3579 goto out;
3580 r = 0;
3581 break;
3582 };
b93463aa
AK		 3583 case KVM_SET_VAPIC_ADDR: {
3584 struct kvm_vapic_addr va;
7301d6ab 3585 int idx;
b93463aa
AK		 3586
3587 r = -EINVAL;
35754c98 3588 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3589 goto out;
3590 r = -EFAULT;
3591 if (copy_from_user(&va, argp, sizeof va))
3592 goto out;
7301d6ab 3593 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3594 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3595 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3596 break;
3597 }
890ca9ae
HY		 3598 case KVM_X86_SETUP_MCE: {
3599 u64 mcg_cap;
3600
3601 r = -EFAULT;
3602 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3603 goto out;
3604 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3605 break;
3606 }
3607 case KVM_X86_SET_MCE: {
3608 struct kvm_x86_mce mce;
3609
3610 r = -EFAULT;
3611 if (copy_from_user(&mce, argp, sizeof mce))
3612 goto out;
3613 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3614 break;
3615 }
3cfc3092
JK		 3616 case KVM_GET_VCPU_EVENTS: {
3617 struct kvm_vcpu_events events;
3618
3619 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3620
3621 r = -EFAULT;
3622 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3623 break;
3624 r = 0;
3625 break;
3626 }
3627 case KVM_SET_VCPU_EVENTS: {
3628 struct kvm_vcpu_events events;
3629
3630 r = -EFAULT;
3631 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3632 break;
3633
3634 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3635 break;
3636 }
a1efbe77
JK		 3637 case KVM_GET_DEBUGREGS: {
3638 struct kvm_debugregs dbgregs;
3639
3640 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3641
3642 r = -EFAULT;
3643 if (copy_to_user(argp, &dbgregs,
3644 sizeof(struct kvm_debugregs)))
3645 break;
3646 r = 0;
3647 break;
3648 }
3649 case KVM_SET_DEBUGREGS: {
3650 struct kvm_debugregs dbgregs;
3651
3652 r = -EFAULT;
3653 if (copy_from_user(&dbgregs, argp,
3654 sizeof(struct kvm_debugregs)))
3655 break;
3656
3657 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3658 break;
3659 }
2d5b5a66 3660 case KVM_GET_XSAVE: {
d1ac91d8 3661 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3662 r = -ENOMEM;
d1ac91d8 3663 if (!u.xsave)
2d5b5a66
SY		 3664 break;
3665
d1ac91d8 3666 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3667
3668 r = -EFAULT;
d1ac91d8 3669 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3670 break;
3671 r = 0;
3672 break;
3673 }
3674 case KVM_SET_XSAVE: {
ff5c2c03 3675 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3676 if (IS_ERR(u.xsave))
3677 return PTR_ERR(u.xsave);
2d5b5a66 3678
d1ac91d8 3679 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3680 break;
3681 }
3682 case KVM_GET_XCRS: {
d1ac91d8 3683 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3684 r = -ENOMEM;
d1ac91d8 3685 if (!u.xcrs)
2d5b5a66
SY		 3686 break;
3687
d1ac91d8 3688 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3689
3690 r = -EFAULT;
d1ac91d8 3691 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3692 sizeof(struct kvm_xcrs)))
3693 break;
3694 r = 0;
3695 break;
3696 }
3697 case KVM_SET_XCRS: {
ff5c2c03 3698 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3699 if (IS_ERR(u.xcrs))
3700 return PTR_ERR(u.xcrs);
2d5b5a66 3701
d1ac91d8 3702 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3703 break;
3704 }
92a1f12d
JR		 3705 case KVM_SET_TSC_KHZ: {
3706 u32 user_tsc_khz;
3707
3708 r = -EINVAL;
92a1f12d
JR		 3709 user_tsc_khz = (u32)arg;
3710
3711 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3712 goto out;
3713
cc578287
ZA		 3714 if (user_tsc_khz == 0)
3715 user_tsc_khz = tsc_khz;
3716
381d585c
HZ		 3717 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3718 r = 0;
92a1f12d 3719
92a1f12d
JR		 3720 goto out;
3721 }
3722 case KVM_GET_TSC_KHZ: {
cc578287 3723 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3724 goto out;
3725 }
1c0b28c2
EM		 3726 case KVM_KVMCLOCK_CTRL: {
3727 r = kvm_set_guest_paused(vcpu);
3728 goto out;
3729 }
5c919412
AS		 3730 case KVM_ENABLE_CAP: {
3731 struct kvm_enable_cap cap;
3732
3733 r = -EFAULT;
3734 if (copy_from_user(&cap, argp, sizeof(cap)))
3735 goto out;
3736 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3737 break;
3738 }
313a3dc7
CO		 3739 default:
3740 r = -EINVAL;
3741 }
3742out:
d1ac91d8 3743 kfree(u.buffer);
313a3dc7
CO		 3744 return r;
3745}
3746
5b1c1493
CO		 3747int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3748{
3749 return VM_FAULT_SIGBUS;
3750}
3751
1fe779f8
CO		 3752static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3753{
3754 int ret;
3755
3756 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3757 return -EINVAL;
1fe779f8
CO		 3758 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3759 return ret;
3760}
3761
b927a3ce
SY		 3762static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3763 u64 ident_addr)
3764{
3765 kvm->arch.ept_identity_map_addr = ident_addr;
3766 return 0;
3767}
3768
1fe779f8
CO		 3769static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3770 u32 kvm_nr_mmu_pages)
3771{
3772 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3773 return -EINVAL;
3774
79fac95e 3775 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3776
3777 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3778 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3779
79fac95e 3780 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3781 return 0;
3782}
3783
3784static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3785{
39de71ec 3786 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3787}
3788
1fe779f8
CO		 3789static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3790{
90bca052 3791 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3792 int r;
3793
3794 r = 0;
3795 switch (chip->chip_id) {
3796 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3797 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3798 sizeof(struct kvm_pic_state));
3799 break;
3800 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3801 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3802 sizeof(struct kvm_pic_state));
3803 break;
3804 case KVM_IRQCHIP_IOAPIC:
33392b49 3805 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3806 break;
3807 default:
3808 r = -EINVAL;
3809 break;
3810 }
3811 return r;
3812}
3813
3814static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3815{
90bca052 3816 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3817 int r;
3818
3819 r = 0;
3820 switch (chip->chip_id) {
3821 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3822 spin_lock(&pic->lock);
3823 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3824 sizeof(struct kvm_pic_state));
90bca052 3825 spin_unlock(&pic->lock);
1fe779f8
CO		 3826 break;
3827 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3828 spin_lock(&pic->lock);
3829 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3830 sizeof(struct kvm_pic_state));
90bca052 3831 spin_unlock(&pic->lock);
1fe779f8
CO		 3832 break;
3833 case KVM_IRQCHIP_IOAPIC:
33392b49 3834 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3835 break;
3836 default:
3837 r = -EINVAL;
3838 break;
3839 }
90bca052 3840 kvm_pic_update_irq(pic);
1fe779f8
CO		 3841 return r;
3842}
3843
e0f63cb9
SY		 3844static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3845{
34f3941c
RK		 3846 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3847
3848 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3849
3850 mutex_lock(&kps->lock);
3851 memcpy(ps, &kps->channels, sizeof(*ps));
3852 mutex_unlock(&kps->lock);
2da29bcc 3853 return 0;
e0f63cb9
SY		 3854}
3855
3856static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3857{
0185604c 3858 int i;
09edea72
RK		 3859 struct kvm_pit *pit = kvm->arch.vpit;
3860
3861 mutex_lock(&pit->pit_state.lock);
34f3941c 3862 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3863 for (i = 0; i < 3; i++)
09edea72
RK		 3864 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3865 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3866 return 0;
e9f42757
BK		 3867}
3868
3869static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3870{
e9f42757
BK		 3871 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3872 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3873 sizeof(ps->channels));
3874 ps->flags = kvm->arch.vpit->pit_state.flags;
3875 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3876 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3877 return 0;
e9f42757
BK		 3878}
3879
3880static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3881{
2da29bcc 3882 int start = 0;
0185604c 3883 int i;
e9f42757 3884 u32 prev_legacy, cur_legacy;
09edea72
RK		 3885 struct kvm_pit *pit = kvm->arch.vpit;
3886
3887 mutex_lock(&pit->pit_state.lock);
3888 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3889 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3890 if (!prev_legacy && cur_legacy)
3891 start = 1;
09edea72
RK		 3892 memcpy(&pit->pit_state.channels, &ps->channels,
3893 sizeof(pit->pit_state.channels));
3894 pit->pit_state.flags = ps->flags;
0185604c 3895 for (i = 0; i < 3; i++)
09edea72 3896 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3897 start && i == 0);
09edea72 3898 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3899 return 0;
e0f63cb9
SY		 3900}
3901
52d939a0
MT		 3902static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3903 struct kvm_reinject_control *control)
3904{
71474e2f
RK		 3905 struct kvm_pit *pit = kvm->arch.vpit;
3906
3907 if (!pit)
52d939a0 3908 return -ENXIO;
b39c90b6 3909
71474e2f
RK		 3910 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3911 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3912 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3913 */
3914 mutex_lock(&pit->pit_state.lock);
3915 kvm_pit_set_reinject(pit, control->pit_reinject);
3916 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3917
52d939a0
MT		 3918 return 0;
3919}
3920
95d4c16c 3921/**
60c34612
TY		 3922 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3923 * @kvm: kvm instance
3924 * @log: slot id and address to which we copy the log
95d4c16c 3925 *
e108ff2f
PB		 3926 * Steps 1-4 below provide general overview of dirty page logging. See
3927 * kvm_get_dirty_log_protect() function description for additional details.
3928 *
3929 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3930 * always flush the TLB (step 4) even if previous step failed and the dirty
3931 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3932 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3933 * writes will be marked dirty for next log read.
95d4c16c 3934 *
60c34612
TY		 3935 * 1. Take a snapshot of the bit and clear it if needed.
3936 * 2. Write protect the corresponding page.
e108ff2f
PB		 3937 * 3. Copy the snapshot to the userspace.
3938 * 4. Flush TLB's if needed.
5bb064dc 3939 */
60c34612 3940int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3941{
60c34612 3942 bool is_dirty = false;
e108ff2f 3943 int r;
5bb064dc 3944
79fac95e 3945 mutex_lock(&kvm->slots_lock);
5bb064dc 3946
88178fd4
KH		 3947 /*
3948 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3949 */
3950 if (kvm_x86_ops->flush_log_dirty)
3951 kvm_x86_ops->flush_log_dirty(kvm);
3952
e108ff2f 3953 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3954
3955 /*
3956 * All the TLBs can be flushed out of mmu lock, see the comments in
3957 * kvm_mmu_slot_remove_write_access().
3958 */
e108ff2f 3959 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3960 if (is_dirty)
3961 kvm_flush_remote_tlbs(kvm);
3962
79fac95e 3963 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3964 return r;
3965}
3966
aa2fbe6d
YZ		 3967int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3968 bool line_status)
23d43cf9
CD		 3969{
3970 if (!irqchip_in_kernel(kvm))
3971 return -ENXIO;
3972
3973 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3974 irq_event->irq, irq_event->level,
3975 line_status);
23d43cf9
CD		 3976 return 0;
3977}
3978
90de4a18
NA		 3979static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3980 struct kvm_enable_cap *cap)
3981{
3982 int r;
3983
3984 if (cap->flags)
3985 return -EINVAL;
3986
3987 switch (cap->cap) {
3988 case KVM_CAP_DISABLE_QUIRKS:
3989 kvm->arch.disabled_quirks = cap->args[0];
3990 r = 0;
3991 break;
49df6397
SR		 3992 case KVM_CAP_SPLIT_IRQCHIP: {
3993 mutex_lock(&kvm->lock);
b053b2ae
SR		 3994 r = -EINVAL;
3995 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3996 goto split_irqchip_unlock;
49df6397
SR		 3997 r = -EEXIST;
3998 if (irqchip_in_kernel(kvm))
3999 goto split_irqchip_unlock;
557abc40 4000 if (kvm->created_vcpus)
49df6397
SR		 4001 goto split_irqchip_unlock;
4002 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4003 if (r)
49df6397
SR		 4004 goto split_irqchip_unlock;
4005 /* Pairs with irqchip_in_kernel. */
4006 smp_wmb();
49776faf 4007 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4008 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4009 r = 0;
4010split_irqchip_unlock:
4011 mutex_unlock(&kvm->lock);
4012 break;
4013 }
37131313
RK		 4014 case KVM_CAP_X2APIC_API:
4015 r = -EINVAL;
4016 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4017 break;
4018
4019 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4020 kvm->arch.x2apic_format = true;
c519265f
RK		 4021 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4022 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4023
4024 r = 0;
4025 break;
90de4a18
NA		 4026 default:
4027 r = -EINVAL;
4028 break;
4029 }
4030 return r;
4031}
4032
1fe779f8
CO		 4033long kvm_arch_vm_ioctl(struct file *filp,
4034 unsigned int ioctl, unsigned long arg)
4035{
4036 struct kvm *kvm = filp->private_data;
4037 void __user *argp = (void __user *)arg;
367e1319 4038 int r = -ENOTTY;
f0d66275
DH		 4039 /*
4040 * This union makes it completely explicit to gcc-3.x
4041 * that these two variables' stack usage should be
4042 * combined, not added together.
4043 */
4044 union {
4045 struct kvm_pit_state ps;
e9f42757 4046 struct kvm_pit_state2 ps2;
c5ff41ce 4047 struct kvm_pit_config pit_config;
f0d66275 4048 } u;
1fe779f8
CO		 4049
4050 switch (ioctl) {
4051 case KVM_SET_TSS_ADDR:
4052 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4053 break;
b927a3ce
SY		 4054 case KVM_SET_IDENTITY_MAP_ADDR: {
4055 u64 ident_addr;
4056
1af1ac91
DH		 4057 mutex_lock(&kvm->lock);
4058 r = -EINVAL;
4059 if (kvm->created_vcpus)
4060 goto set_identity_unlock;
b927a3ce
SY		 4061 r = -EFAULT;
4062 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4063 goto set_identity_unlock;
b927a3ce 4064 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4065set_identity_unlock:
4066 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4067 break;
4068 }
1fe779f8
CO		 4069 case KVM_SET_NR_MMU_PAGES:
4070 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4071 break;
4072 case KVM_GET_NR_MMU_PAGES:
4073 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4074 break;
3ddea128 4075 case KVM_CREATE_IRQCHIP: {
3ddea128 4076 mutex_lock(&kvm->lock);
09941366 4077
3ddea128 4078 r = -EEXIST;
35e6eaa3 4079 if (irqchip_in_kernel(kvm))
3ddea128 4080 goto create_irqchip_unlock;
09941366 4081
3e515705 4082 r = -EINVAL;
557abc40 4083 if (kvm->created_vcpus)
3e515705 4084 goto create_irqchip_unlock;
09941366
RK		 4085
4086 r = kvm_pic_init(kvm);
4087 if (r)
3ddea128 4088 goto create_irqchip_unlock;
09941366
RK		 4089
4090 r = kvm_ioapic_init(kvm);
4091 if (r) {
09941366 4092 kvm_pic_destroy(kvm);
3ddea128 4093 goto create_irqchip_unlock;
09941366
RK		 4094 }
4095
399ec807
AK		 4096 r = kvm_setup_default_irq_routing(kvm);
4097 if (r) {
72bb2fcd 4098 kvm_ioapic_destroy(kvm);
09941366 4099 kvm_pic_destroy(kvm);
71ba994c 4100 goto create_irqchip_unlock;
399ec807 4101 }
49776faf 4102 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4103 smp_wmb();
49776faf 4104 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4105 create_irqchip_unlock:
4106 mutex_unlock(&kvm->lock);
1fe779f8 4107 break;
3ddea128 4108 }
7837699f 4109 case KVM_CREATE_PIT:
c5ff41ce
JK		 4110 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4111 goto create_pit;
4112 case KVM_CREATE_PIT2:
4113 r = -EFAULT;
4114 if (copy_from_user(&u.pit_config, argp,
4115 sizeof(struct kvm_pit_config)))
4116 goto out;
4117 create_pit:
250715a6 4118 mutex_lock(&kvm->lock);
269e05e4
AK		 4119 r = -EEXIST;
4120 if (kvm->arch.vpit)
4121 goto create_pit_unlock;
7837699f 4122 r = -ENOMEM;
c5ff41ce 4123 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4124 if (kvm->arch.vpit)
4125 r = 0;
269e05e4 4126 create_pit_unlock:
250715a6 4127 mutex_unlock(&kvm->lock);
7837699f 4128 break;
1fe779f8
CO		 4129 case KVM_GET_IRQCHIP: {
4130 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4131 struct kvm_irqchip *chip;
1fe779f8 4132
ff5c2c03
SL		 4133 chip = memdup_user(argp, sizeof(*chip));
4134 if (IS_ERR(chip)) {
4135 r = PTR_ERR(chip);
1fe779f8 4136 goto out;
ff5c2c03
SL		 4137 }
4138
1fe779f8 4139 r = -ENXIO;
826da321 4140 if (!irqchip_kernel(kvm))
f0d66275
DH		 4141 goto get_irqchip_out;
4142 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4143 if (r)
f0d66275 4144 goto get_irqchip_out;
1fe779f8 4145 r = -EFAULT;
f0d66275
DH		 4146 if (copy_to_user(argp, chip, sizeof *chip))
4147 goto get_irqchip_out;
1fe779f8 4148 r = 0;
f0d66275
DH		 4149 get_irqchip_out:
4150 kfree(chip);
1fe779f8
CO		 4151 break;
4152 }
4153 case KVM_SET_IRQCHIP: {
4154 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4155 struct kvm_irqchip *chip;
1fe779f8 4156
ff5c2c03
SL		 4157 chip = memdup_user(argp, sizeof(*chip));
4158 if (IS_ERR(chip)) {
4159 r = PTR_ERR(chip);
1fe779f8 4160 goto out;
ff5c2c03
SL		 4161 }
4162
1fe779f8 4163 r = -ENXIO;
826da321 4164 if (!irqchip_kernel(kvm))
f0d66275
DH		 4165 goto set_irqchip_out;
4166 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4167 if (r)
f0d66275 4168 goto set_irqchip_out;
1fe779f8 4169 r = 0;
f0d66275
DH		 4170 set_irqchip_out:
4171 kfree(chip);
1fe779f8
CO		 4172 break;
4173 }
e0f63cb9 4174 case KVM_GET_PIT: {
e0f63cb9 4175 r = -EFAULT;
f0d66275 4176 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4177 goto out;
4178 r = -ENXIO;
4179 if (!kvm->arch.vpit)
4180 goto out;
f0d66275 4181 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4182 if (r)
4183 goto out;
4184 r = -EFAULT;
f0d66275 4185 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4186 goto out;
4187 r = 0;
4188 break;
4189 }
4190 case KVM_SET_PIT: {
e0f63cb9 4191 r = -EFAULT;
f0d66275 4192 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4193 goto out;
4194 r = -ENXIO;
4195 if (!kvm->arch.vpit)
4196 goto out;
f0d66275 4197 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4198 break;
4199 }
e9f42757
BK		 4200 case KVM_GET_PIT2: {
4201 r = -ENXIO;
4202 if (!kvm->arch.vpit)
4203 goto out;
4204 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4205 if (r)
4206 goto out;
4207 r = -EFAULT;
4208 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4209 goto out;
4210 r = 0;
4211 break;
4212 }
4213 case KVM_SET_PIT2: {
4214 r = -EFAULT;
4215 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4216 goto out;
4217 r = -ENXIO;
4218 if (!kvm->arch.vpit)
4219 goto out;
4220 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4221 break;
4222 }
52d939a0
MT		 4223 case KVM_REINJECT_CONTROL: {
4224 struct kvm_reinject_control control;
4225 r = -EFAULT;
4226 if (copy_from_user(&control, argp, sizeof(control)))
4227 goto out;
4228 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4229 break;
4230 }
d71ba788
PB		 4231 case KVM_SET_BOOT_CPU_ID:
4232 r = 0;
4233 mutex_lock(&kvm->lock);
557abc40 4234 if (kvm->created_vcpus)
d71ba788
PB		 4235 r = -EBUSY;
4236 else
4237 kvm->arch.bsp_vcpu_id = arg;
4238 mutex_unlock(&kvm->lock);
4239 break;
ffde22ac
ES		 4240 case KVM_XEN_HVM_CONFIG: {
4241 r = -EFAULT;
4242 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4243 sizeof(struct kvm_xen_hvm_config)))
4244 goto out;
4245 r = -EINVAL;
4246 if (kvm->arch.xen_hvm_config.flags)
4247 goto out;
4248 r = 0;
4249 break;
4250 }
afbcf7ab 4251 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4252 struct kvm_clock_data user_ns;
4253 u64 now_ns;
afbcf7ab
GC		 4254
4255 r = -EFAULT;
4256 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4257 goto out;
4258
4259 r = -EINVAL;
4260 if (user_ns.flags)
4261 goto out;
4262
4263 r = 0;
0bc48bea
RK		 4264 /*
4265 * TODO: userspace has to take care of races with VCPU_RUN, so
4266 * kvm_gen_update_masterclock() can be cut down to locked
4267 * pvclock_update_vm_gtod_copy().
4268 */
4269 kvm_gen_update_masterclock(kvm);
e891a32e 4270 now_ns = get_kvmclock_ns(kvm);
108b249c 4271 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4272 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4273 break;
4274 }
4275 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4276 struct kvm_clock_data user_ns;
4277 u64 now_ns;
4278
e891a32e 4279 now_ns = get_kvmclock_ns(kvm);
108b249c 4280 user_ns.clock = now_ns;
e3fd9a93 4281 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4282 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4283
4284 r = -EFAULT;
4285 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4286 goto out;
4287 r = 0;
4288 break;
4289 }
90de4a18
NA		 4290 case KVM_ENABLE_CAP: {
4291 struct kvm_enable_cap cap;
afbcf7ab 4292
90de4a18
NA		 4293 r = -EFAULT;
4294 if (copy_from_user(&cap, argp, sizeof(cap)))
4295 goto out;
4296 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4297 break;
4298 }
1fe779f8 4299 default:
ad6260da 4300 r = -ENOTTY;
1fe779f8
CO		 4301 }
4302out:
4303 return r;
4304}
4305
a16b043c 4306static void kvm_init_msr_list(void)
043405e1
CO		 4307{
4308 u32 dummy[2];
4309 unsigned i, j;
4310
62ef68bb 4311 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4312 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4313 continue;
93c4adc7
PB		 4314
4315 /*
4316 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4317 * to the guests in some cases.
93c4adc7
PB		 4318 */
4319 switch (msrs_to_save[i]) {
4320 case MSR_IA32_BNDCFGS:
4321 if (!kvm_x86_ops->mpx_supported())
4322 continue;
4323 break;
9dbe6cf9
PB		 4324 case MSR_TSC_AUX:
4325 if (!kvm_x86_ops->rdtscp_supported())
4326 continue;
4327 break;
93c4adc7
PB		 4328 default:
4329 break;
4330 }
4331
043405e1
CO		 4332 if (j < i)
4333 msrs_to_save[j] = msrs_to_save[i];
4334 j++;
4335 }
4336 num_msrs_to_save = j;
62ef68bb
PB		 4337
4338 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4339 switch (emulated_msrs[i]) {
6d396b55
PB		 4340 case MSR_IA32_SMBASE:
4341 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4342 continue;
4343 break;
62ef68bb
PB		 4344 default:
4345 break;
4346 }
4347
4348 if (j < i)
4349 emulated_msrs[j] = emulated_msrs[i];
4350 j++;
4351 }
4352 num_emulated_msrs = j;
043405e1
CO		 4353}
4354
bda9020e
MT		 4355static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4356 const void *v)
bbd9b64e 4357{
70252a10
AK		 4358 int handled = 0;
4359 int n;
4360
4361 do {
4362 n = min(len, 8);
bce87cce 4363 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4364 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4365 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4366 break;
4367 handled += n;
4368 addr += n;
4369 len -= n;
4370 v += n;
4371 } while (len);
bbd9b64e 4372
70252a10 4373 return handled;
bbd9b64e
CO		 4374}
4375
bda9020e 4376static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4377{
70252a10
AK		 4378 int handled = 0;
4379 int n;
4380
4381 do {
4382 n = min(len, 8);
bce87cce 4383 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4384 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4385 addr, n, v))
4386 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4387 break;
4388 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4389 handled += n;
4390 addr += n;
4391 len -= n;
4392 v += n;
4393 } while (len);
bbd9b64e 4394
70252a10 4395 return handled;
bbd9b64e
CO		 4396}
4397
2dafc6c2
GN		 4398static void kvm_set_segment(struct kvm_vcpu *vcpu,
4399 struct kvm_segment *var, int seg)
4400{
4401 kvm_x86_ops->set_segment(vcpu, var, seg);
4402}
4403
4404void kvm_get_segment(struct kvm_vcpu *vcpu,
4405 struct kvm_segment *var, int seg)
4406{
4407 kvm_x86_ops->get_segment(vcpu, var, seg);
4408}
4409
54987b7a
PB		 4410gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4411 struct x86_exception *exception)
02f59dc9
JR		 4412{
4413 gpa_t t_gpa;
02f59dc9
JR		 4414
4415 BUG_ON(!mmu_is_nested(vcpu));
4416
4417 /* NPT walks are always user-walks */
4418 access |= PFERR_USER_MASK;
54987b7a 4419 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4420
4421 return t_gpa;
4422}
4423
ab9ae313
AK		 4424gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4425 struct x86_exception *exception)
1871c602
GN		 4426{
4427 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4428 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4429}
4430
ab9ae313
AK		 4431 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4432 struct x86_exception *exception)
1871c602
GN		 4433{
4434 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4435 access |= PFERR_FETCH_MASK;
ab9ae313 4436 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4437}
4438
ab9ae313
AK		 4439gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4440 struct x86_exception *exception)
1871c602
GN		 4441{
4442 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4443 access |= PFERR_WRITE_MASK;
ab9ae313 4444 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4445}
4446
4447/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4448gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4449 struct x86_exception *exception)
1871c602 4450{
ab9ae313 4451 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4452}
4453
4454static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4455 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4456 struct x86_exception *exception)
bbd9b64e
CO		 4457{
4458 void *data = val;
10589a46 4459 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4460
4461 while (bytes) {
14dfe855 4462 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4463 exception);
bbd9b64e 4464 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4465 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4466 int ret;
4467
bcc55cba 4468 if (gpa == UNMAPPED_GVA)
ab9ae313 4469 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4470 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4471 offset, toread);
10589a46 4472 if (ret < 0) {
c3cd7ffa 4473 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4474 goto out;
4475 }
bbd9b64e 4476
77c2002e
IE		 4477 bytes -= toread;
4478 data += toread;
4479 addr += toread;
bbd9b64e 4480 }
10589a46 4481out:
10589a46 4482 return r;
bbd9b64e 4483}
77c2002e 4484
1871c602 4485/* used for instruction fetching */
0f65dd70
AK		 4486static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4487 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4488 struct x86_exception *exception)
1871c602 4489{
0f65dd70 4490 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4491 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4492 unsigned offset;
4493 int ret;
0f65dd70 4494
44583cba
PB		 4495 /* Inline kvm_read_guest_virt_helper for speed. */
4496 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4497 exception);
4498 if (unlikely(gpa == UNMAPPED_GVA))
4499 return X86EMUL_PROPAGATE_FAULT;
4500
4501 offset = addr & (PAGE_SIZE-1);
4502 if (WARN_ON(offset + bytes > PAGE_SIZE))
4503 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4504 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4505 offset, bytes);
44583cba
PB		 4506 if (unlikely(ret < 0))
4507 return X86EMUL_IO_NEEDED;
4508
4509 return X86EMUL_CONTINUE;
1871c602
GN		 4510}
4511
064aea77 4512int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4513 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4514 struct x86_exception *exception)
1871c602 4515{
0f65dd70 4516 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4517 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4518
1871c602 4519 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4520 exception);
1871c602 4521}
064aea77 4522EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4523
0f65dd70
AK		 4524static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4525 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4526 struct x86_exception *exception)
1871c602 4527{
0f65dd70 4528 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4529 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4530}
4531
7a036a6f
RK		 4532static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4533 unsigned long addr, void *val, unsigned int bytes)
4534{
4535 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4536 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4537
4538 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4539}
4540
6a4d7550 4541int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4542 gva_t addr, void *val,
2dafc6c2 4543 unsigned int bytes,
bcc55cba 4544 struct x86_exception *exception)
77c2002e 4545{
0f65dd70 4546 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4547 void *data = val;
4548 int r = X86EMUL_CONTINUE;
4549
4550 while (bytes) {
14dfe855
JR		 4551 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4552 PFERR_WRITE_MASK,
ab9ae313 4553 exception);
77c2002e
IE		 4554 unsigned offset = addr & (PAGE_SIZE-1);
4555 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4556 int ret;
4557
bcc55cba 4558 if (gpa == UNMAPPED_GVA)
ab9ae313 4559 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4560 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4561 if (ret < 0) {
c3cd7ffa 4562 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4563 goto out;
4564 }
4565
4566 bytes -= towrite;
4567 data += towrite;
4568 addr += towrite;
4569 }
4570out:
4571 return r;
4572}
6a4d7550 4573EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4574
0f89b207
TL		 4575static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4576 gpa_t gpa, bool write)
4577{
4578 /* For APIC access vmexit */
4579 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4580 return 1;
4581
4582 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4583 trace_vcpu_match_mmio(gva, gpa, write, true);
4584 return 1;
4585 }
4586
4587 return 0;
4588}
4589
af7cc7d1
XG		 4590static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4591 gpa_t *gpa, struct x86_exception *exception,
4592 bool write)
4593{
97d64b78
AK		 4594 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4595 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4596
be94f6b7
HH		 4597 /*
4598 * currently PKRU is only applied to ept enabled guest so
4599 * there is no pkey in EPT page table for L1 guest or EPT
4600 * shadow page table for L2 guest.
4601 */
97d64b78 4602 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4603 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4604 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4605 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4606 (gva & (PAGE_SIZE - 1));
4f022648 4607 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4608 return 1;
4609 }
4610
af7cc7d1
XG		 4611 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4612
4613 if (*gpa == UNMAPPED_GVA)
4614 return -1;
4615
0f89b207 4616 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4617}
4618
3200f405 4619int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4620 const void *val, int bytes)
bbd9b64e
CO		 4621{
4622 int ret;
4623
54bf36aa 4624 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4625 if (ret < 0)
bbd9b64e 4626 return 0;
0eb05bf2 4627 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4628 return 1;
4629}
4630
77d197b2
XG		 4631struct read_write_emulator_ops {
4632 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4633 int bytes);
4634 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4635 void *val, int bytes);
4636 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4637 int bytes, void *val);
4638 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4639 void *val, int bytes);
4640 bool write;
4641};
4642
4643static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4644{
4645 if (vcpu->mmio_read_completed) {
77d197b2 4646 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4647 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4648 vcpu->mmio_read_completed = 0;
4649 return 1;
4650 }
4651
4652 return 0;
4653}
4654
4655static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4656 void *val, int bytes)
4657{
54bf36aa 4658 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4659}
4660
4661static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4662 void *val, int bytes)
4663{
4664 return emulator_write_phys(vcpu, gpa, val, bytes);
4665}
4666
4667static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4668{
4669 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4670 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4671}
4672
4673static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4674 void *val, int bytes)
4675{
4676 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4677 return X86EMUL_IO_NEEDED;
4678}
4679
4680static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4681 void *val, int bytes)
4682{
f78146b0
AK		 4683 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4684
87da7e66 4685 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4686 return X86EMUL_CONTINUE;
4687}
4688
0fbe9b0b 4689static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4690 .read_write_prepare = read_prepare,
4691 .read_write_emulate = read_emulate,
4692 .read_write_mmio = vcpu_mmio_read,
4693 .read_write_exit_mmio = read_exit_mmio,
4694};
4695
0fbe9b0b 4696static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4697 .read_write_emulate = write_emulate,
4698 .read_write_mmio = write_mmio,
4699 .read_write_exit_mmio = write_exit_mmio,
4700 .write = true,
4701};
4702
22388a3c
XG		 4703static int emulator_read_write_onepage(unsigned long addr, void *val,
4704 unsigned int bytes,
4705 struct x86_exception *exception,
4706 struct kvm_vcpu *vcpu,
0fbe9b0b 4707 const struct read_write_emulator_ops *ops)
bbd9b64e 4708{
af7cc7d1
XG		 4709 gpa_t gpa;
4710 int handled, ret;
22388a3c 4711 bool write = ops->write;
f78146b0 4712 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4713 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4714
4715 /*
4716 * If the exit was due to a NPF we may already have a GPA.
4717 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4718 * Note, this cannot be used on string operations since string
4719 * operation using rep will only have the initial GPA from the NPF
4720 * occurred.
4721 */
4722 if (vcpu->arch.gpa_available &&
4723 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4724 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4725 gpa = vcpu->arch.gpa_val;
4726 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4727 } else {
4728 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4729 if (ret < 0)
4730 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4731 }
10589a46 4732
618232e2 4733 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4734 return X86EMUL_CONTINUE;
4735
bbd9b64e
CO		 4736 /*
4737 * Is this MMIO handled locally?
4738 */
22388a3c 4739 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4740 if (handled == bytes)
bbd9b64e 4741 return X86EMUL_CONTINUE;
bbd9b64e 4742
70252a10
AK		 4743 gpa += handled;
4744 bytes -= handled;
4745 val += handled;
4746
87da7e66
XG		 4747 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4748 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4749 frag->gpa = gpa;
4750 frag->data = val;
4751 frag->len = bytes;
f78146b0 4752 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4753}
4754
52eb5a6d
XL		 4755static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4756 unsigned long addr,
22388a3c
XG		 4757 void *val, unsigned int bytes,
4758 struct x86_exception *exception,
0fbe9b0b 4759 const struct read_write_emulator_ops *ops)
bbd9b64e 4760{
0f65dd70 4761 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4762 gpa_t gpa;
4763 int rc;
4764
4765 if (ops->read_write_prepare &&
4766 ops->read_write_prepare(vcpu, val, bytes))
4767 return X86EMUL_CONTINUE;
4768
4769 vcpu->mmio_nr_fragments = 0;
0f65dd70 4770
bbd9b64e
CO		 4771 /* Crossing a page boundary? */
4772 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4773 int now;
bbd9b64e
CO		 4774
4775 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4776 rc = emulator_read_write_onepage(addr, val, now, exception,
4777 vcpu, ops);
4778
bbd9b64e
CO		 4779 if (rc != X86EMUL_CONTINUE)
4780 return rc;
4781 addr += now;
bac15531
NA		 4782 if (ctxt->mode != X86EMUL_MODE_PROT64)
4783 addr = (u32)addr;
bbd9b64e
CO		 4784 val += now;
4785 bytes -= now;
4786 }
22388a3c 4787
f78146b0
AK		 4788 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4789 vcpu, ops);
4790 if (rc != X86EMUL_CONTINUE)
4791 return rc;
4792
4793 if (!vcpu->mmio_nr_fragments)
4794 return rc;
4795
4796 gpa = vcpu->mmio_fragments[0].gpa;
4797
4798 vcpu->mmio_needed = 1;
4799 vcpu->mmio_cur_fragment = 0;
4800
87da7e66 4801 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4802 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4803 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4804 vcpu->run->mmio.phys_addr = gpa;
4805
4806 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4807}
4808
4809static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4810 unsigned long addr,
4811 void *val,
4812 unsigned int bytes,
4813 struct x86_exception *exception)
4814{
4815 return emulator_read_write(ctxt, addr, val, bytes,
4816 exception, &read_emultor);
4817}
4818
52eb5a6d 4819static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4820 unsigned long addr,
4821 const void *val,
4822 unsigned int bytes,
4823 struct x86_exception *exception)
4824{
4825 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4826 exception, &write_emultor);
bbd9b64e 4827}
bbd9b64e 4828
daea3e73
AK		 4829#define CMPXCHG_TYPE(t, ptr, old, new) \
4830 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4831
4832#ifdef CONFIG_X86_64
4833# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4834#else
4835# define CMPXCHG64(ptr, old, new) \
9749a6c0 4836 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4837#endif
4838
0f65dd70
AK		 4839static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4840 unsigned long addr,
bbd9b64e
CO		 4841 const void *old,
4842 const void *new,
4843 unsigned int bytes,
0f65dd70 4844 struct x86_exception *exception)
bbd9b64e 4845{
0f65dd70 4846 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4847 gpa_t gpa;
4848 struct page *page;
4849 char *kaddr;
4850 bool exchanged;
2bacc55c 4851
daea3e73
AK		 4852 /* guests cmpxchg8b have to be emulated atomically */
4853 if (bytes > 8 || (bytes & (bytes - 1)))
4854 goto emul_write;
10589a46 4855
daea3e73 4856 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4857
daea3e73
AK		 4858 if (gpa == UNMAPPED_GVA ||
4859 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4860 goto emul_write;
2bacc55c 4861
daea3e73
AK		 4862 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4863 goto emul_write;
72dc67a6 4864
54bf36aa 4865 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4866 if (is_error_page(page))
c19b8bd6 4867 goto emul_write;
72dc67a6 4868
8fd75e12 4869 kaddr = kmap_atomic(page);
daea3e73
AK		 4870 kaddr += offset_in_page(gpa);
4871 switch (bytes) {
4872 case 1:
4873 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4874 break;
4875 case 2:
4876 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4877 break;
4878 case 4:
4879 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4880 break;
4881 case 8:
4882 exchanged = CMPXCHG64(kaddr, old, new);
4883 break;
4884 default:
4885 BUG();
2bacc55c 4886 }
8fd75e12 4887 kunmap_atomic(kaddr);
daea3e73
AK		 4888 kvm_release_page_dirty(page);
4889
4890 if (!exchanged)
4891 return X86EMUL_CMPXCHG_FAILED;
4892
54bf36aa 4893 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4894 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4895
4896 return X86EMUL_CONTINUE;
4a5f48f6 4897
3200f405 4898emul_write:
daea3e73 4899 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4900
0f65dd70 4901 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4902}
4903
cf8f70bf
GN		 4904static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4905{
cbfc6c91 4906 int r = 0, i;
cf8f70bf 4907
cbfc6c91
WL		 4908 for (i = 0; i < vcpu->arch.pio.count; i++) {
4909 if (vcpu->arch.pio.in)
4910 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4911 vcpu->arch.pio.size, pd);
4912 else
4913 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4914 vcpu->arch.pio.port, vcpu->arch.pio.size,
4915 pd);
4916 if (r)
4917 break;
4918 pd += vcpu->arch.pio.size;
4919 }
cf8f70bf
GN		 4920 return r;
4921}
4922
6f6fbe98
XG		 4923static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4924 unsigned short port, void *val,
4925 unsigned int count, bool in)
cf8f70bf 4926{
cf8f70bf 4927 vcpu->arch.pio.port = port;
6f6fbe98 4928 vcpu->arch.pio.in = in;
7972995b 4929 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4930 vcpu->arch.pio.size = size;
4931
4932 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4933 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4934 return 1;
4935 }
4936
4937 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4938 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4939 vcpu->run->io.size = size;
4940 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4941 vcpu->run->io.count = count;
4942 vcpu->run->io.port = port;
4943
4944 return 0;
4945}
4946
6f6fbe98
XG		 4947static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4948 int size, unsigned short port, void *val,
4949 unsigned int count)
cf8f70bf 4950{
ca1d4a9e 4951 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4952 int ret;
ca1d4a9e 4953
6f6fbe98
XG		 4954 if (vcpu->arch.pio.count)
4955 goto data_avail;
cf8f70bf 4956
cbfc6c91
WL		 4957 memset(vcpu->arch.pio_data, 0, size * count);
4958
6f6fbe98
XG		 4959 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4960 if (ret) {
4961data_avail:
4962 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4963 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4964 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4965 return 1;
4966 }
4967
cf8f70bf
GN		 4968 return 0;
4969}
4970
6f6fbe98
XG		 4971static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4972 int size, unsigned short port,
4973 const void *val, unsigned int count)
4974{
4975 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4976
4977 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4978 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4979 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4980}
4981
bbd9b64e
CO		 4982static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4983{
4984 return kvm_x86_ops->get_segment_base(vcpu, seg);
4985}
4986
3cb16fe7 4987static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4988{
3cb16fe7 4989 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4990}
4991
ae6a2375 4992static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4993{
4994 if (!need_emulate_wbinvd(vcpu))
4995 return X86EMUL_CONTINUE;
4996
4997 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4998 int cpu = get_cpu();
4999
5000 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5001 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5002 wbinvd_ipi, NULL, 1);
2eec7343 5003 put_cpu();
f5f48ee1 5004 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5005 } else
5006 wbinvd();
f5f48ee1
SY		 5007 return X86EMUL_CONTINUE;
5008}
5cb56059
JS		 5009
5010int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5011{
6affcbed
KH		 5012 kvm_emulate_wbinvd_noskip(vcpu);
5013 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5014}
f5f48ee1
SY		 5015EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5016
5cb56059
JS		 5017
5018
bcaf5cc5
AK		 5019static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5020{
5cb56059 5021 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5022}
5023
52eb5a6d
XL		 5024static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5025 unsigned long *dest)
bbd9b64e 5026{
16f8a6f9 5027 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5028}
5029
52eb5a6d
XL		 5030static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5031 unsigned long value)
bbd9b64e 5032{
338dbc97 5033
717746e3 5034 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5035}
5036
52a46617 5037static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5038{
52a46617 5039 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5040}
5041
717746e3 5042static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5043{
717746e3 5044 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5045 unsigned long value;
5046
5047 switch (cr) {
5048 case 0:
5049 value = kvm_read_cr0(vcpu);
5050 break;
5051 case 2:
5052 value = vcpu->arch.cr2;
5053 break;
5054 case 3:
9f8fe504 5055 value = kvm_read_cr3(vcpu);
52a46617
GN		 5056 break;
5057 case 4:
5058 value = kvm_read_cr4(vcpu);
5059 break;
5060 case 8:
5061 value = kvm_get_cr8(vcpu);
5062 break;
5063 default:
a737f256 5064 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5065 return 0;
5066 }
5067
5068 return value;
5069}
5070
717746e3 5071static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5072{
717746e3 5073 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5074 int res = 0;
5075
52a46617
GN		 5076 switch (cr) {
5077 case 0:
49a9b07e 5078 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5079 break;
5080 case 2:
5081 vcpu->arch.cr2 = val;
5082 break;
5083 case 3:
2390218b 5084 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5085 break;
5086 case 4:
a83b29c6 5087 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5088 break;
5089 case 8:
eea1cff9 5090 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5091 break;
5092 default:
a737f256 5093 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5094 res = -1;
52a46617 5095 }
0f12244f
GN		 5096
5097 return res;
52a46617
GN		 5098}
5099
717746e3 5100static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5101{
717746e3 5102 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5103}
5104
4bff1e86 5105static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5106{
4bff1e86 5107 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5108}
5109
4bff1e86 5110static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5111{
4bff1e86 5112 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5113}
5114
1ac9d0cf
AK		 5115static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5116{
5117 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5118}
5119
5120static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5121{
5122 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5123}
5124
4bff1e86
AK		 5125static unsigned long emulator_get_cached_segment_base(
5126 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5127{
4bff1e86 5128 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5129}
5130
1aa36616
AK		 5131static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5132 struct desc_struct *desc, u32 *base3,
5133 int seg)
2dafc6c2
GN		 5134{
5135 struct kvm_segment var;
5136
4bff1e86 5137 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5138 *selector = var.selector;
2dafc6c2 5139
378a8b09
GN		 5140 if (var.unusable) {
5141 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5142 if (base3)
5143 *base3 = 0;
2dafc6c2 5144 return false;
378a8b09 5145 }
2dafc6c2
GN		 5146
5147 if (var.g)
5148 var.limit >>= 12;
5149 set_desc_limit(desc, var.limit);
5150 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5151#ifdef CONFIG_X86_64
5152 if (base3)
5153 *base3 = var.base >> 32;
5154#endif
2dafc6c2
GN		 5155 desc->type = var.type;
5156 desc->s = var.s;
5157 desc->dpl = var.dpl;
5158 desc->p = var.present;
5159 desc->avl = var.avl;
5160 desc->l = var.l;
5161 desc->d = var.db;
5162 desc->g = var.g;
5163
5164 return true;
5165}
5166
1aa36616
AK		 5167static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5168 struct desc_struct *desc, u32 base3,
5169 int seg)
2dafc6c2 5170{
4bff1e86 5171 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5172 struct kvm_segment var;
5173
1aa36616 5174 var.selector = selector;
2dafc6c2 5175 var.base = get_desc_base(desc);
5601d05b
GN		 5176#ifdef CONFIG_X86_64
5177 var.base |= ((u64)base3) << 32;
5178#endif
2dafc6c2
GN		 5179 var.limit = get_desc_limit(desc);
5180 if (desc->g)
5181 var.limit = (var.limit << 12) | 0xfff;
5182 var.type = desc->type;
2dafc6c2
GN		 5183 var.dpl = desc->dpl;
5184 var.db = desc->d;
5185 var.s = desc->s;
5186 var.l = desc->l;
5187 var.g = desc->g;
5188 var.avl = desc->avl;
5189 var.present = desc->p;
5190 var.unusable = !var.present;
5191 var.padding = 0;
5192
5193 kvm_set_segment(vcpu, &var, seg);
5194 return;
5195}
5196
717746e3
AK		 5197static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5198 u32 msr_index, u64 *pdata)
5199{
609e36d3
PB		 5200 struct msr_data msr;
5201 int r;
5202
5203 msr.index = msr_index;
5204 msr.host_initiated = false;
5205 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5206 if (r)
5207 return r;
5208
5209 *pdata = msr.data;
5210 return 0;
717746e3
AK		 5211}
5212
5213static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5214 u32 msr_index, u64 data)
5215{
8fe8ab46
WA		 5216 struct msr_data msr;
5217
5218 msr.data = data;
5219 msr.index = msr_index;
5220 msr.host_initiated = false;
5221 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5222}
5223
64d60670
PB		 5224static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5225{
5226 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5227
5228 return vcpu->arch.smbase;
5229}
5230
5231static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5232{
5233 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5234
5235 vcpu->arch.smbase = smbase;
5236}
5237
67f4d428
NA		 5238static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5239 u32 pmc)
5240{
c6702c9d 5241 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5242}
5243
222d21aa
AK		 5244static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5245 u32 pmc, u64 *pdata)
5246{
c6702c9d 5247 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5248}
5249
6c3287f7
AK		 5250static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5251{
5252 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5253}
5254
5037f6f3
AK		 5255static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5256{
5257 preempt_disable();
5197b808 5258 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5259}
5260
5261static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5262{
5263 preempt_enable();
5264}
5265
2953538e 5266static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5267 struct x86_instruction_info *info,
c4f035c6
AK		 5268 enum x86_intercept_stage stage)
5269{
2953538e 5270 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5271}
5272
e911eb3b
YZ		 5273static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5274 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5275{
e911eb3b 5276 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5277}
5278
dd856efa
AK		 5279static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5280{
5281 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5282}
5283
5284static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5285{
5286 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5287}
5288
801806d9
NA		 5289static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5290{
5291 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5292}
5293
6ed071f0
LP		 5294static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5295{
5296 return emul_to_vcpu(ctxt)->arch.hflags;
5297}
5298
5299static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5300{
5301 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5302}
5303
0234bf88
LP		 5304static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5305{
5306 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5307}
5308
0225fb50 5309static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5310 .read_gpr = emulator_read_gpr,
5311 .write_gpr = emulator_write_gpr,
1871c602 5312 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5313 .write_std = kvm_write_guest_virt_system,
7a036a6f 5314 .read_phys = kvm_read_guest_phys_system,
1871c602 5315 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5316 .read_emulated = emulator_read_emulated,
5317 .write_emulated = emulator_write_emulated,
5318 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5319 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5320 .pio_in_emulated = emulator_pio_in_emulated,
5321 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5322 .get_segment = emulator_get_segment,
5323 .set_segment = emulator_set_segment,
5951c442 5324 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5325 .get_gdt = emulator_get_gdt,
160ce1f1 5326 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5327 .set_gdt = emulator_set_gdt,
5328 .set_idt = emulator_set_idt,
52a46617
GN		 5329 .get_cr = emulator_get_cr,
5330 .set_cr = emulator_set_cr,
9c537244 5331 .cpl = emulator_get_cpl,
35aa5375
GN		 5332 .get_dr = emulator_get_dr,
5333 .set_dr = emulator_set_dr,
64d60670
PB		 5334 .get_smbase = emulator_get_smbase,
5335 .set_smbase = emulator_set_smbase,
717746e3
AK		 5336 .set_msr = emulator_set_msr,
5337 .get_msr = emulator_get_msr,
67f4d428 5338 .check_pmc = emulator_check_pmc,
222d21aa 5339 .read_pmc = emulator_read_pmc,
6c3287f7 5340 .halt = emulator_halt,
bcaf5cc5 5341 .wbinvd = emulator_wbinvd,
d6aa1000 5342 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5343 .get_fpu = emulator_get_fpu,
5344 .put_fpu = emulator_put_fpu,
c4f035c6 5345 .intercept = emulator_intercept,
bdb42f5a 5346 .get_cpuid = emulator_get_cpuid,
801806d9 5347 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5348 .get_hflags = emulator_get_hflags,
5349 .set_hflags = emulator_set_hflags,
0234bf88 5350 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5351};
5352
95cb2295
GN		 5353static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5354{
37ccdcbe 5355 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5356 /*
5357 * an sti; sti; sequence only disable interrupts for the first
5358 * instruction. So, if the last instruction, be it emulated or
5359 * not, left the system with the INT_STI flag enabled, it
5360 * means that the last instruction is an sti. We should not
5361 * leave the flag on in this case. The same goes for mov ss
5362 */
37ccdcbe
PB		 5363 if (int_shadow & mask)
5364 mask = 0;
6addfc42 5365 if (unlikely(int_shadow || mask)) {
95cb2295 5366 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5367 if (!mask)
5368 kvm_make_request(KVM_REQ_EVENT, vcpu);
5369 }
95cb2295
GN		 5370}
5371
ef54bcfe 5372static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5373{
5374 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5375 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5376 return kvm_propagate_fault(vcpu, &ctxt->exception);
5377
5378 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5379 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5380 ctxt->exception.error_code);
54b8486f 5381 else
da9cb575 5382 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5383 return false;
54b8486f
GN		 5384}
5385
8ec4722d
MG		 5386static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5387{
adf52235 5388 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5389 int cs_db, cs_l;
5390
8ec4722d
MG		 5391 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5392
adf52235 5393 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5394 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5395
adf52235
TY		 5396 ctxt->eip = kvm_rip_read(vcpu);
5397 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5398 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5399 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5400 cs_db ? X86EMUL_MODE_PROT32 :
5401 X86EMUL_MODE_PROT16;
a584539b 5402 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5403 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5404 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5405
dd856efa 5406 init_decode_cache(ctxt);
7ae441ea 5407 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5408}
5409
71f9833b 5410int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5411{
9d74191a 5412 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5413 int ret;
5414
5415 init_emulate_ctxt(vcpu);
5416
9dac77fa
AK		 5417 ctxt->op_bytes = 2;
5418 ctxt->ad_bytes = 2;
5419 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5420 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5421
5422 if (ret != X86EMUL_CONTINUE)
5423 return EMULATE_FAIL;
5424
9dac77fa 5425 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5426 kvm_rip_write(vcpu, ctxt->eip);
5427 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5428
5429 if (irq == NMI_VECTOR)
7460fb4a 5430 vcpu->arch.nmi_pending = 0;
63995653
MG		 5431 else
5432 vcpu->arch.interrupt.pending = false;
5433
5434 return EMULATE_DONE;
5435}
5436EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5437
6d77dbfc
GN		 5438static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5439{
fc3a9157
JR		 5440 int r = EMULATE_DONE;
5441
6d77dbfc
GN		 5442 ++vcpu->stat.insn_emulation_fail;
5443 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5444 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5445 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5446 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5447 vcpu->run->internal.ndata = 0;
1f4dcb3b 5448 r = EMULATE_USER_EXIT;
fc3a9157 5449 }
6d77dbfc 5450 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5451
5452 return r;
6d77dbfc
GN		 5453}
5454
93c05d3e 5455static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5456 bool write_fault_to_shadow_pgtable,
5457 int emulation_type)
a6f177ef 5458{
95b3cf69 5459 gpa_t gpa = cr2;
ba049e93 5460 kvm_pfn_t pfn;
a6f177ef 5461
991eebf9
GN		 5462 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5463 return false;
5464
95b3cf69
XG		 5465 if (!vcpu->arch.mmu.direct_map) {
5466 /*
5467 * Write permission should be allowed since only
5468 * write access need to be emulated.
5469 */
5470 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5471
95b3cf69
XG		 5472 /*
5473 * If the mapping is invalid in guest, let cpu retry
5474 * it to generate fault.
5475 */
5476 if (gpa == UNMAPPED_GVA)
5477 return true;
5478 }
a6f177ef 5479
8e3d9d06
XG		 5480 /*
5481 * Do not retry the unhandleable instruction if it faults on the
5482 * readonly host memory, otherwise it will goto a infinite loop:
5483 * retry instruction -> write #PF -> emulation fail -> retry
5484 * instruction -> ...
5485 */
5486 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5487
5488 /*
5489 * If the instruction failed on the error pfn, it can not be fixed,
5490 * report the error to userspace.
5491 */
5492 if (is_error_noslot_pfn(pfn))
5493 return false;
5494
5495 kvm_release_pfn_clean(pfn);
5496
5497 /* The instructions are well-emulated on direct mmu. */
5498 if (vcpu->arch.mmu.direct_map) {
5499 unsigned int indirect_shadow_pages;
5500
5501 spin_lock(&vcpu->kvm->mmu_lock);
5502 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5503 spin_unlock(&vcpu->kvm->mmu_lock);
5504
5505 if (indirect_shadow_pages)
5506 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5507
a6f177ef 5508 return true;
8e3d9d06 5509 }
a6f177ef 5510
95b3cf69
XG		 5511 /*
5512 * if emulation was due to access to shadowed page table
5513 * and it failed try to unshadow page and re-enter the
5514 * guest to let CPU execute the instruction.
5515 */
5516 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5517
5518 /*
5519 * If the access faults on its page table, it can not
5520 * be fixed by unprotecting shadow page and it should
5521 * be reported to userspace.
5522 */
5523 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5524}
5525
1cb3f3ae
XG		 5526static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5527 unsigned long cr2, int emulation_type)
5528{
5529 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5530 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5531
5532 last_retry_eip = vcpu->arch.last_retry_eip;
5533 last_retry_addr = vcpu->arch.last_retry_addr;
5534
5535 /*
5536 * If the emulation is caused by #PF and it is non-page_table
5537 * writing instruction, it means the VM-EXIT is caused by shadow
5538 * page protected, we can zap the shadow page and retry this
5539 * instruction directly.
5540 *
5541 * Note: if the guest uses a non-page-table modifying instruction
5542 * on the PDE that points to the instruction, then we will unmap
5543 * the instruction and go to an infinite loop. So, we cache the
5544 * last retried eip and the last fault address, if we meet the eip
5545 * and the address again, we can break out of the potential infinite
5546 * loop.
5547 */
5548 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5549
5550 if (!(emulation_type & EMULTYPE_RETRY))
5551 return false;
5552
5553 if (x86_page_table_writing_insn(ctxt))
5554 return false;
5555
5556 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5557 return false;
5558
5559 vcpu->arch.last_retry_eip = ctxt->eip;
5560 vcpu->arch.last_retry_addr = cr2;
5561
5562 if (!vcpu->arch.mmu.direct_map)
5563 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5564
22368028 5565 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5566
5567 return true;
5568}
5569
716d51ab
GN		 5570static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5571static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5572
64d60670 5573static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5574{
64d60670 5575 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5576 /* This is a good place to trace that we are exiting SMM. */
5577 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5578
c43203ca
PB		 5579 /* Process a latched INIT or SMI, if any. */
5580 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5581 }
699023e2
PB		 5582
5583 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5584}
5585
5586static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5587{
5588 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5589
a584539b 5590 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5591
5592 if (changed & HF_SMM_MASK)
5593 kvm_smm_changed(vcpu);
a584539b
PB		 5594}
5595
4a1e10d5
PB		 5596static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5597 unsigned long *db)
5598{
5599 u32 dr6 = 0;
5600 int i;
5601 u32 enable, rwlen;
5602
5603 enable = dr7;
5604 rwlen = dr7 >> 16;
5605 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5606 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5607 dr6 |= (1 << i);
5608 return dr6;
5609}
5610
c8401dda 5611static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5612{
5613 struct kvm_run *kvm_run = vcpu->run;
5614
c8401dda
PB		 5615 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5616 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5617 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5618 kvm_run->debug.arch.exception = DB_VECTOR;
5619 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5620 *r = EMULATE_USER_EXIT;
5621 } else {
5622 /*
5623 * "Certain debug exceptions may clear bit 0-3. The
5624 * remaining contents of the DR6 register are never
5625 * cleared by the processor".
5626 */
5627 vcpu->arch.dr6 &= ~15;
5628 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5629 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5630 }
5631}
5632
6affcbed
KH		 5633int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5634{
5635 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5636 int r = EMULATE_DONE;
5637
5638 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5639
5640 /*
5641 * rflags is the old, "raw" value of the flags. The new value has
5642 * not been saved yet.
5643 *
5644 * This is correct even for TF set by the guest, because "the
5645 * processor will not generate this exception after the instruction
5646 * that sets the TF flag".
5647 */
5648 if (unlikely(rflags & X86_EFLAGS_TF))
5649 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5650 return r == EMULATE_DONE;
5651}
5652EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5653
4a1e10d5
PB		 5654static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5655{
4a1e10d5
PB		 5656 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5657 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5658 struct kvm_run *kvm_run = vcpu->run;
5659 unsigned long eip = kvm_get_linear_rip(vcpu);
5660 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5661 vcpu->arch.guest_debug_dr7,
5662 vcpu->arch.eff_db);
5663
5664 if (dr6 != 0) {
6f43ed01 5665 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5666 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5667 kvm_run->debug.arch.exception = DB_VECTOR;
5668 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5669 *r = EMULATE_USER_EXIT;
5670 return true;
5671 }
5672 }
5673
4161a569
NA		 5674 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5675 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5676 unsigned long eip = kvm_get_linear_rip(vcpu);
5677 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5678 vcpu->arch.dr7,
5679 vcpu->arch.db);
5680
5681 if (dr6 != 0) {
5682 vcpu->arch.dr6 &= ~15;
6f43ed01 5683 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5684 kvm_queue_exception(vcpu, DB_VECTOR);
5685 *r = EMULATE_DONE;
5686 return true;
5687 }
5688 }
5689
5690 return false;
5691}
5692
51d8b661
AP		 5693int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5694 unsigned long cr2,
dc25e89e
AP		 5695 int emulation_type,
5696 void *insn,
5697 int insn_len)
bbd9b64e 5698{
95cb2295 5699 int r;
9d74191a 5700 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5701 bool writeback = true;
93c05d3e 5702 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5703
93c05d3e
XG		 5704 /*
5705 * Clear write_fault_to_shadow_pgtable here to ensure it is
5706 * never reused.
5707 */
5708 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5709 kvm_clear_exception_queue(vcpu);
8d7d8102 5710
571008da 5711 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5712 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5713
5714 /*
5715 * We will reenter on the same instruction since
5716 * we do not set complete_userspace_io. This does not
5717 * handle watchpoints yet, those would be handled in
5718 * the emulate_ops.
5719 */
5720 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5721 return r;
5722
9d74191a
TY		 5723 ctxt->interruptibility = 0;
5724 ctxt->have_exception = false;
e0ad0b47 5725 ctxt->exception.vector = -1;
9d74191a 5726 ctxt->perm_ok = false;
bbd9b64e 5727
b51e974f 5728 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5729
9d74191a 5730 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5731
e46479f8 5732 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5733 ++vcpu->stat.insn_emulation;
1d2887e2 5734 if (r != EMULATION_OK) {
4005996e
AK		 5735 if (emulation_type & EMULTYPE_TRAP_UD)
5736 return EMULATE_FAIL;
991eebf9
GN		 5737 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5738 emulation_type))
bbd9b64e 5739 return EMULATE_DONE;
6ea6e843
PB		 5740 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5741 return EMULATE_DONE;
6d77dbfc
GN		 5742 if (emulation_type & EMULTYPE_SKIP)
5743 return EMULATE_FAIL;
5744 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5745 }
5746 }
5747
ba8afb6b 5748 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5749 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5750 if (ctxt->eflags & X86_EFLAGS_RF)
5751 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5752 return EMULATE_DONE;
5753 }
5754
1cb3f3ae
XG		 5755 if (retry_instruction(ctxt, cr2, emulation_type))
5756 return EMULATE_DONE;
5757
7ae441ea 5758 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5759 changes registers values during IO operation */
7ae441ea
GN		 5760 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5761 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5762 emulator_invalidate_register_cache(ctxt);
7ae441ea 5763 }
4d2179e1 5764
5cd21917 5765restart:
0f89b207
TL		 5766 /* Save the faulting GPA (cr2) in the address field */
5767 ctxt->exception.address = cr2;
5768
9d74191a 5769 r = x86_emulate_insn(ctxt);
bbd9b64e 5770
775fde86
JR		 5771 if (r == EMULATION_INTERCEPTED)
5772 return EMULATE_DONE;
5773
d2ddd1c4 5774 if (r == EMULATION_FAILED) {
991eebf9
GN		 5775 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5776 emulation_type))
c3cd7ffa
GN		 5777 return EMULATE_DONE;
5778
6d77dbfc 5779 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5780 }
5781
9d74191a 5782 if (ctxt->have_exception) {
d2ddd1c4 5783 r = EMULATE_DONE;
ef54bcfe
PB		 5784 if (inject_emulated_exception(vcpu))
5785 return r;
d2ddd1c4 5786 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5787 if (!vcpu->arch.pio.in) {
5788 /* FIXME: return into emulator if single-stepping. */
3457e419 5789 vcpu->arch.pio.count = 0;
0912c977 5790 } else {
7ae441ea 5791 writeback = false;
716d51ab
GN		 5792 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5793 }
ac0a48c3 5794 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5795 } else if (vcpu->mmio_needed) {
5796 if (!vcpu->mmio_is_write)
5797 writeback = false;
ac0a48c3 5798 r = EMULATE_USER_EXIT;
716d51ab 5799 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5800 } else if (r == EMULATION_RESTART)
5cd21917 5801 goto restart;
d2ddd1c4
GN		 5802 else
5803 r = EMULATE_DONE;
f850e2e6 5804
7ae441ea 5805 if (writeback) {
6addfc42 5806 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5807 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5808 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5809 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5810 if (r == EMULATE_DONE &&
5811 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5812 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5813 if (!ctxt->have_exception ||
5814 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5815 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5816
5817 /*
5818 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5819 * do nothing, and it will be requested again as soon as
5820 * the shadow expires. But we still need to check here,
5821 * because POPF has no interrupt shadow.
5822 */
5823 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5824 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5825 } else
5826 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5827
5828 return r;
de7d789a 5829}
51d8b661 5830EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5831
cf8f70bf 5832int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5833{
cf8f70bf 5834 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5835 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5836 size, port, &val, 1);
cf8f70bf 5837 /* do not return to emulator after return from userspace */
7972995b 5838 vcpu->arch.pio.count = 0;
de7d789a
CO		 5839 return ret;
5840}
cf8f70bf 5841EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5842
8370c3d0
TL		 5843static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5844{
5845 unsigned long val;
5846
5847 /* We should only ever be called with arch.pio.count equal to 1 */
5848 BUG_ON(vcpu->arch.pio.count != 1);
5849
5850 /* For size less than 4 we merge, else we zero extend */
5851 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5852 : 0;
5853
5854 /*
5855 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5856 * the copy and tracing
5857 */
5858 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5859 vcpu->arch.pio.port, &val, 1);
5860 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5861
5862 return 1;
5863}
5864
5865int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5866{
5867 unsigned long val;
5868 int ret;
5869
5870 /* For size less than 4 we merge, else we zero extend */
5871 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5872
5873 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5874 &val, 1);
5875 if (ret) {
5876 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5877 return ret;
5878 }
5879
5880 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5881
5882 return 0;
5883}
5884EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5885
251a5fd6 5886static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5887{
0a3aee0d 5888 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5889 return 0;
8cfdc000
ZA		 5890}
5891
5892static void tsc_khz_changed(void *data)
c8076604 5893{
8cfdc000
ZA		 5894 struct cpufreq_freqs *freq = data;
5895 unsigned long khz = 0;
5896
5897 if (data)
5898 khz = freq->new;
5899 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5900 khz = cpufreq_quick_get(raw_smp_processor_id());
5901 if (!khz)
5902 khz = tsc_khz;
0a3aee0d 5903 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5904}
5905
c8076604
GH		 5906static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5907 void *data)
5908{
5909 struct cpufreq_freqs *freq = data;
5910 struct kvm *kvm;
5911 struct kvm_vcpu *vcpu;
5912 int i, send_ipi = 0;
5913
8cfdc000
ZA		 5914 /*
5915 * We allow guests to temporarily run on slowing clocks,
5916 * provided we notify them after, or to run on accelerating
5917 * clocks, provided we notify them before. Thus time never
5918 * goes backwards.
5919 *
5920 * However, we have a problem. We can't atomically update
5921 * the frequency of a given CPU from this function; it is
5922 * merely a notifier, which can be called from any CPU.
5923 * Changing the TSC frequency at arbitrary points in time
5924 * requires a recomputation of local variables related to
5925 * the TSC for each VCPU. We must flag these local variables
5926 * to be updated and be sure the update takes place with the
5927 * new frequency before any guests proceed.
5928 *
5929 * Unfortunately, the combination of hotplug CPU and frequency
5930 * change creates an intractable locking scenario; the order
5931 * of when these callouts happen is undefined with respect to
5932 * CPU hotplug, and they can race with each other. As such,
5933 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5934 * undefined; you can actually have a CPU frequency change take
5935 * place in between the computation of X and the setting of the
5936 * variable. To protect against this problem, all updates of
5937 * the per_cpu tsc_khz variable are done in an interrupt
5938 * protected IPI, and all callers wishing to update the value
5939 * must wait for a synchronous IPI to complete (which is trivial
5940 * if the caller is on the CPU already). This establishes the
5941 * necessary total order on variable updates.
5942 *
5943 * Note that because a guest time update may take place
5944 * anytime after the setting of the VCPU's request bit, the
5945 * correct TSC value must be set before the request. However,
5946 * to ensure the update actually makes it to any guest which
5947 * starts running in hardware virtualization between the set
5948 * and the acquisition of the spinlock, we must also ping the
5949 * CPU after setting the request bit.
5950 *
5951 */
5952
c8076604
GH		 5953 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5954 return 0;
5955 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5956 return 0;
8cfdc000
ZA		 5957
5958 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5959
2f303b74 5960 spin_lock(&kvm_lock);
c8076604 5961 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5962 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5963 if (vcpu->cpu != freq->cpu)
5964 continue;
c285545f 5965 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5966 if (vcpu->cpu != smp_processor_id())
8cfdc000 5967 send_ipi = 1;
c8076604
GH		 5968 }
5969 }
2f303b74 5970 spin_unlock(&kvm_lock);
c8076604
GH		 5971
5972 if (freq->old < freq->new && send_ipi) {
5973 /*
5974 * We upscale the frequency. Must make the guest
5975 * doesn't see old kvmclock values while running with
5976 * the new frequency, otherwise we risk the guest sees
5977 * time go backwards.
5978 *
5979 * In case we update the frequency for another cpu
5980 * (which might be in guest context) send an interrupt
5981 * to kick the cpu out of guest context. Next time
5982 * guest context is entered kvmclock will be updated,
5983 * so the guest will not see stale values.
5984 */
8cfdc000 5985 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5986 }
5987 return 0;
5988}
5989
5990static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5991 .notifier_call = kvmclock_cpufreq_notifier
5992};
5993
251a5fd6 5994static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5995{
251a5fd6
SAS		 5996 tsc_khz_changed(NULL);
5997 return 0;
8cfdc000
ZA		 5998}
5999
b820cc0c
ZA		 6000static void kvm_timer_init(void)
6001{
c285545f 6002 max_tsc_khz = tsc_khz;
460dd42e 6003
b820cc0c 6004 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6005#ifdef CONFIG_CPU_FREQ
6006 struct cpufreq_policy policy;
758f588d
BP		 6007 int cpu;
6008
c285545f 6009 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6010 cpu = get_cpu();
6011 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6012 if (policy.cpuinfo.max_freq)
6013 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6014 put_cpu();
c285545f 6015#endif
b820cc0c
ZA		 6016 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6017 CPUFREQ_TRANSITION_NOTIFIER);
6018 }
c285545f 6019 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6020
73c1b41e 6021 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6022 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6023}
6024
ff9d07a0
ZY		 6025static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6026
f5132b01 6027int kvm_is_in_guest(void)
ff9d07a0 6028{
086c9855 6029 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6030}
6031
6032static int kvm_is_user_mode(void)
6033{
6034 int user_mode = 3;
dcf46b94 6035
086c9855
AS		 6036 if (__this_cpu_read(current_vcpu))
6037 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6038
ff9d07a0
ZY		 6039 return user_mode != 0;
6040}
6041
6042static unsigned long kvm_get_guest_ip(void)
6043{
6044 unsigned long ip = 0;
dcf46b94 6045
086c9855
AS		 6046 if (__this_cpu_read(current_vcpu))
6047 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6048
ff9d07a0
ZY		 6049 return ip;
6050}
6051
6052static struct perf_guest_info_callbacks kvm_guest_cbs = {
6053 .is_in_guest = kvm_is_in_guest,
6054 .is_user_mode = kvm_is_user_mode,
6055 .get_guest_ip = kvm_get_guest_ip,
6056};
6057
6058void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6059{
086c9855 6060 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6061}
6062EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6063
6064void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6065{
086c9855 6066 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6067}
6068EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6069
ce88decf
XG		 6070static void kvm_set_mmio_spte_mask(void)
6071{
6072 u64 mask;
6073 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6074
6075 /*
6076 * Set the reserved bits and the present bit of an paging-structure
6077 * entry to generate page fault with PFER.RSV = 1.
6078 */
885032b9 6079 /* Mask the reserved physical address bits. */
d1431483 6080 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6081
885032b9 6082 /* Set the present bit. */
ce88decf
XG		 6083 mask |= 1ull;
6084
6085#ifdef CONFIG_X86_64
6086 /*
6087 * If reserved bit is not supported, clear the present bit to disable
6088 * mmio page fault.
6089 */
6090 if (maxphyaddr == 52)
6091 mask &= ~1ull;
6092#endif
6093
dcdca5fe 6094 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6095}
6096
16e8d74d
MT		 6097#ifdef CONFIG_X86_64
6098static void pvclock_gtod_update_fn(struct work_struct *work)
6099{
d828199e
MT		 6100 struct kvm *kvm;
6101
6102 struct kvm_vcpu *vcpu;
6103 int i;
6104
2f303b74 6105 spin_lock(&kvm_lock);
d828199e
MT		 6106 list_for_each_entry(kvm, &vm_list, vm_list)
6107 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6108 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6109 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6110 spin_unlock(&kvm_lock);
16e8d74d
MT		 6111}
6112
6113static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6114
6115/*
6116 * Notification about pvclock gtod data update.
6117 */
6118static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6119 void *priv)
6120{
6121 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6122 struct timekeeper *tk = priv;
6123
6124 update_pvclock_gtod(tk);
6125
6126 /* disable master clock if host does not trust, or does not
6127 * use, TSC clocksource
6128 */
6129 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6130 atomic_read(&kvm_guest_has_master_clock) != 0)
6131 queue_work(system_long_wq, &pvclock_gtod_work);
6132
6133 return 0;
6134}
6135
6136static struct notifier_block pvclock_gtod_notifier = {
6137 .notifier_call = pvclock_gtod_notify,
6138};
6139#endif
6140
f8c16bba 6141int kvm_arch_init(void *opaque)
043405e1 6142{
b820cc0c 6143 int r;
6b61edf7 6144 struct kvm_x86_ops *ops = opaque;
f8c16bba 6145
f8c16bba
ZX		 6146 if (kvm_x86_ops) {
6147 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6148 r = -EEXIST;
6149 goto out;
f8c16bba
ZX		 6150 }
6151
6152 if (!ops->cpu_has_kvm_support()) {
6153 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6154 r = -EOPNOTSUPP;
6155 goto out;
f8c16bba
ZX		 6156 }
6157 if (ops->disabled_by_bios()) {
6158 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6159 r = -EOPNOTSUPP;
6160 goto out;
f8c16bba
ZX		 6161 }
6162
013f6a5d
MT		 6163 r = -ENOMEM;
6164 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6165 if (!shared_msrs) {
6166 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6167 goto out;
6168 }
6169
97db56ce
AK		 6170 r = kvm_mmu_module_init();
6171 if (r)
013f6a5d 6172 goto out_free_percpu;
97db56ce 6173
ce88decf 6174 kvm_set_mmio_spte_mask();
97db56ce 6175
f8c16bba 6176 kvm_x86_ops = ops;
920c8377 6177
7b52345e 6178 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6179 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6180 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6181 kvm_timer_init();
c8076604 6182
ff9d07a0
ZY		 6183 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6184
d366bf7e 6185 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6186 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6187
c5cc421b 6188 kvm_lapic_init();
16e8d74d
MT		 6189#ifdef CONFIG_X86_64
6190 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6191#endif
6192
f8c16bba 6193 return 0;
56c6d28a 6194
013f6a5d
MT		 6195out_free_percpu:
6196 free_percpu(shared_msrs);
56c6d28a 6197out:
56c6d28a 6198 return r;
043405e1 6199}
8776e519 6200
f8c16bba
ZX		 6201void kvm_arch_exit(void)
6202{
cef84c30 6203 kvm_lapic_exit();
ff9d07a0
ZY		 6204 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6205
888d256e
JK		 6206 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6207 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6208 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6209 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6210#ifdef CONFIG_X86_64
6211 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6212#endif
f8c16bba 6213 kvm_x86_ops = NULL;
56c6d28a 6214 kvm_mmu_module_exit();
013f6a5d 6215 free_percpu(shared_msrs);
56c6d28a 6216}
f8c16bba 6217
5cb56059 6218int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6219{
6220 ++vcpu->stat.halt_exits;
35754c98 6221 if (lapic_in_kernel(vcpu)) {
a4535290 6222 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6223 return 1;
6224 } else {
6225 vcpu->run->exit_reason = KVM_EXIT_HLT;
6226 return 0;
6227 }
6228}
5cb56059
JS		 6229EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6230
6231int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6232{
6affcbed
KH		 6233 int ret = kvm_skip_emulated_instruction(vcpu);
6234 /*
6235 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6236 * KVM_EXIT_DEBUG here.
6237 */
6238 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6239}
8776e519
HB		 6240EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6241
8ef81a9a 6242#ifdef CONFIG_X86_64
55dd00a7
MT		 6243static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6244 unsigned long clock_type)
6245{
6246 struct kvm_clock_pairing clock_pairing;
6247 struct timespec ts;
80fbd89c 6248 u64 cycle;
55dd00a7
MT		 6249 int ret;
6250
6251 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6252 return -KVM_EOPNOTSUPP;
6253
6254 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6255 return -KVM_EOPNOTSUPP;
6256
6257 clock_pairing.sec = ts.tv_sec;
6258 clock_pairing.nsec = ts.tv_nsec;
6259 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6260 clock_pairing.flags = 0;
6261
6262 ret = 0;
6263 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6264 sizeof(struct kvm_clock_pairing)))
6265 ret = -KVM_EFAULT;
6266
6267 return ret;
6268}
8ef81a9a 6269#endif
55dd00a7 6270
6aef266c
SV		 6271/*
6272 * kvm_pv_kick_cpu_op: Kick a vcpu.
6273 *
6274 * @apicid - apicid of vcpu to be kicked.
6275 */
6276static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6277{
24d2166b 6278 struct kvm_lapic_irq lapic_irq;
6aef266c 6279
24d2166b
R		 6280 lapic_irq.shorthand = 0;
6281 lapic_irq.dest_mode = 0;
ebd28fcb 6282 lapic_irq.level = 0;
24d2166b 6283 lapic_irq.dest_id = apicid;
93bbf0b8 6284 lapic_irq.msi_redir_hint = false;
6aef266c 6285
24d2166b 6286 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6287 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6288}
6289
d62caabb
AS		 6290void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6291{
6292 vcpu->arch.apicv_active = false;
6293 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6294}
6295
8776e519
HB		 6296int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6297{
6298 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6299 int op_64_bit, r;
8776e519 6300
6affcbed 6301 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6302
55cd8e5a
GN		 6303 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6304 return kvm_hv_hypercall(vcpu);
6305
5fdbf976
MT		 6306 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6307 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6308 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6309 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6310 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6311
229456fc 6312 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6313
a449c7aa
NA		 6314 op_64_bit = is_64_bit_mode(vcpu);
6315 if (!op_64_bit) {
8776e519
HB		 6316 nr &= 0xFFFFFFFF;
6317 a0 &= 0xFFFFFFFF;
6318 a1 &= 0xFFFFFFFF;
6319 a2 &= 0xFFFFFFFF;
6320 a3 &= 0xFFFFFFFF;
6321 }
6322
07708c4a
JK		 6323 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6324 ret = -KVM_EPERM;
6325 goto out;
6326 }
6327
8776e519 6328 switch (nr) {
b93463aa
AK		 6329 case KVM_HC_VAPIC_POLL_IRQ:
6330 ret = 0;
6331 break;
6aef266c
SV		 6332 case KVM_HC_KICK_CPU:
6333 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6334 ret = 0;
6335 break;
8ef81a9a 6336#ifdef CONFIG_X86_64
55dd00a7
MT		 6337 case KVM_HC_CLOCK_PAIRING:
6338 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6339 break;
8ef81a9a 6340#endif
8776e519
HB		 6341 default:
6342 ret = -KVM_ENOSYS;
6343 break;
6344 }
07708c4a 6345out:
a449c7aa
NA		 6346 if (!op_64_bit)
6347 ret = (u32)ret;
5fdbf976 6348 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6349 ++vcpu->stat.hypercalls;
2f333bcb 6350 return r;
8776e519
HB		 6351}
6352EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6353
b6785def 6354static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6355{
d6aa1000 6356 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6357 char instruction[3];
5fdbf976 6358 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6359
8776e519 6360 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6361
ce2e852e
DV		 6362 return emulator_write_emulated(ctxt, rip, instruction, 3,
6363 &ctxt->exception);
8776e519
HB		 6364}
6365
851ba692 6366static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6367{
782d422b
MG		 6368 return vcpu->run->request_interrupt_window &&
6369 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6370}
6371
851ba692 6372static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6373{
851ba692
AK		 6374 struct kvm_run *kvm_run = vcpu->run;
6375
91586a3b 6376 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6377 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6378 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6379 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6380 kvm_run->ready_for_interrupt_injection =
6381 pic_in_kernel(vcpu->kvm) ||
782d422b 6382 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6383}
6384
95ba8273
GN		 6385static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6386{
6387 int max_irr, tpr;
6388
6389 if (!kvm_x86_ops->update_cr8_intercept)
6390 return;
6391
bce87cce 6392 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6393 return;
6394
d62caabb
AS		 6395 if (vcpu->arch.apicv_active)
6396 return;
6397
8db3baa2
GN		 6398 if (!vcpu->arch.apic->vapic_addr)
6399 max_irr = kvm_lapic_find_highest_irr(vcpu);
6400 else
6401 max_irr = -1;
95ba8273
GN		 6402
6403 if (max_irr != -1)
6404 max_irr >>= 4;
6405
6406 tpr = kvm_lapic_get_cr8(vcpu);
6407
6408 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6409}
6410
b6b8a145 6411static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6412{
b6b8a145
JK		 6413 int r;
6414
95ba8273 6415 /* try to reinject previous events if any */
664f8e26
WL		 6416 if (vcpu->arch.exception.injected) {
6417 kvm_x86_ops->queue_exception(vcpu);
6418 return 0;
6419 }
6420
6421 /*
6422 * Exceptions must be injected immediately, or the exception
6423 * frame will have the address of the NMI or interrupt handler.
6424 */
6425 if (!vcpu->arch.exception.pending) {
6426 if (vcpu->arch.nmi_injected) {
6427 kvm_x86_ops->set_nmi(vcpu);
6428 return 0;
6429 }
6430
6431 if (vcpu->arch.interrupt.pending) {
6432 kvm_x86_ops->set_irq(vcpu);
6433 return 0;
6434 }
6435 }
6436
6437 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6438 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6439 if (r != 0)
6440 return r;
6441 }
6442
6443 /* try to inject new event if pending */
b59bb7bd 6444 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6445 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6446 vcpu->arch.exception.has_error_code,
6447 vcpu->arch.exception.error_code);
d6e8c854 6448
664f8e26
WL		 6449 vcpu->arch.exception.pending = false;
6450 vcpu->arch.exception.injected = true;
6451
d6e8c854
NA		 6452 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6453 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6454 X86_EFLAGS_RF);
6455
6bdf0662
NA		 6456 if (vcpu->arch.exception.nr == DB_VECTOR &&
6457 (vcpu->arch.dr7 & DR7_GD)) {
6458 vcpu->arch.dr7 &= ~DR7_GD;
6459 kvm_update_dr7(vcpu);
6460 }
6461
cfcd20e5 6462 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6463 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6464 vcpu->arch.smi_pending = false;
ee2cd4b7 6465 enter_smm(vcpu);
c43203ca 6466 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6467 --vcpu->arch.nmi_pending;
6468 vcpu->arch.nmi_injected = true;
6469 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6470 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6471 /*
6472 * Because interrupts can be injected asynchronously, we are
6473 * calling check_nested_events again here to avoid a race condition.
6474 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6475 * proposal and current concerns. Perhaps we should be setting
6476 * KVM_REQ_EVENT only on certain events and not unconditionally?
6477 */
6478 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6479 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6480 if (r != 0)
6481 return r;
6482 }
95ba8273 6483 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6484 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6485 false);
6486 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6487 }
6488 }
ee2cd4b7 6489
b6b8a145 6490 return 0;
95ba8273
GN		 6491}
6492
7460fb4a
AK		 6493static void process_nmi(struct kvm_vcpu *vcpu)
6494{
6495 unsigned limit = 2;
6496
6497 /*
6498 * x86 is limited to one NMI running, and one NMI pending after it.
6499 * If an NMI is already in progress, limit further NMIs to just one.
6500 * Otherwise, allow two (and we'll inject the first one immediately).
6501 */
6502 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6503 limit = 1;
6504
6505 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6506 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6507 kvm_make_request(KVM_REQ_EVENT, vcpu);
6508}
6509
ee2cd4b7 6510static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6511{
6512 u32 flags = 0;
6513 flags |= seg->g << 23;
6514 flags |= seg->db << 22;
6515 flags |= seg->l << 21;
6516 flags |= seg->avl << 20;
6517 flags |= seg->present << 15;
6518 flags |= seg->dpl << 13;
6519 flags |= seg->s << 12;
6520 flags |= seg->type << 8;
6521 return flags;
6522}
6523
ee2cd4b7 6524static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6525{
6526 struct kvm_segment seg;
6527 int offset;
6528
6529 kvm_get_segment(vcpu, &seg, n);
6530 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6531
6532 if (n < 3)
6533 offset = 0x7f84 + n * 12;
6534 else
6535 offset = 0x7f2c + (n - 3) * 12;
6536
6537 put_smstate(u32, buf, offset + 8, seg.base);
6538 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6539 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6540}
6541
efbb288a 6542#ifdef CONFIG_X86_64
ee2cd4b7 6543static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6544{
6545 struct kvm_segment seg;
6546 int offset;
6547 u16 flags;
6548
6549 kvm_get_segment(vcpu, &seg, n);
6550 offset = 0x7e00 + n * 16;
6551
ee2cd4b7 6552 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6553 put_smstate(u16, buf, offset, seg.selector);
6554 put_smstate(u16, buf, offset + 2, flags);
6555 put_smstate(u32, buf, offset + 4, seg.limit);
6556 put_smstate(u64, buf, offset + 8, seg.base);
6557}
efbb288a 6558#endif
660a5d51 6559
ee2cd4b7 6560static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6561{
6562 struct desc_ptr dt;
6563 struct kvm_segment seg;
6564 unsigned long val;
6565 int i;
6566
6567 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6568 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6569 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6570 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6571
6572 for (i = 0; i < 8; i++)
6573 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6574
6575 kvm_get_dr(vcpu, 6, &val);
6576 put_smstate(u32, buf, 0x7fcc, (u32)val);
6577 kvm_get_dr(vcpu, 7, &val);
6578 put_smstate(u32, buf, 0x7fc8, (u32)val);
6579
6580 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6581 put_smstate(u32, buf, 0x7fc4, seg.selector);
6582 put_smstate(u32, buf, 0x7f64, seg.base);
6583 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6584 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6585
6586 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6587 put_smstate(u32, buf, 0x7fc0, seg.selector);
6588 put_smstate(u32, buf, 0x7f80, seg.base);
6589 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6590 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6591
6592 kvm_x86_ops->get_gdt(vcpu, &dt);
6593 put_smstate(u32, buf, 0x7f74, dt.address);
6594 put_smstate(u32, buf, 0x7f70, dt.size);
6595
6596 kvm_x86_ops->get_idt(vcpu, &dt);
6597 put_smstate(u32, buf, 0x7f58, dt.address);
6598 put_smstate(u32, buf, 0x7f54, dt.size);
6599
6600 for (i = 0; i < 6; i++)
ee2cd4b7 6601 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6602
6603 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6604
6605 /* revision id */
6606 put_smstate(u32, buf, 0x7efc, 0x00020000);
6607 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6608}
6609
ee2cd4b7 6610static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6611{
6612#ifdef CONFIG_X86_64
6613 struct desc_ptr dt;
6614 struct kvm_segment seg;
6615 unsigned long val;
6616 int i;
6617
6618 for (i = 0; i < 16; i++)
6619 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6620
6621 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6622 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6623
6624 kvm_get_dr(vcpu, 6, &val);
6625 put_smstate(u64, buf, 0x7f68, val);
6626 kvm_get_dr(vcpu, 7, &val);
6627 put_smstate(u64, buf, 0x7f60, val);
6628
6629 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6630 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6631 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6632
6633 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6634
6635 /* revision id */
6636 put_smstate(u32, buf, 0x7efc, 0x00020064);
6637
6638 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6639
6640 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6641 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6642 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6643 put_smstate(u32, buf, 0x7e94, seg.limit);
6644 put_smstate(u64, buf, 0x7e98, seg.base);
6645
6646 kvm_x86_ops->get_idt(vcpu, &dt);
6647 put_smstate(u32, buf, 0x7e84, dt.size);
6648 put_smstate(u64, buf, 0x7e88, dt.address);
6649
6650 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6651 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6652 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6653 put_smstate(u32, buf, 0x7e74, seg.limit);
6654 put_smstate(u64, buf, 0x7e78, seg.base);
6655
6656 kvm_x86_ops->get_gdt(vcpu, &dt);
6657 put_smstate(u32, buf, 0x7e64, dt.size);
6658 put_smstate(u64, buf, 0x7e68, dt.address);
6659
6660 for (i = 0; i < 6; i++)
ee2cd4b7 6661 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6662#else
6663 WARN_ON_ONCE(1);
6664#endif
6665}
6666
ee2cd4b7 6667static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6668{
660a5d51 6669 struct kvm_segment cs, ds;
18c3626e 6670 struct desc_ptr dt;
660a5d51
PB		 6671 char buf[512];
6672 u32 cr0;
6673
660a5d51 6674 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6675 memset(buf, 0, 512);
d6321d49 6676 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6677 enter_smm_save_state_64(vcpu, buf);
660a5d51 6678 else
ee2cd4b7 6679 enter_smm_save_state_32(vcpu, buf);
660a5d51 6680
0234bf88
LP		 6681 /*
6682 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6683 * vCPU state (e.g. leave guest mode) after we've saved the state into
6684 * the SMM state-save area.
6685 */
6686 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6687
6688 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6689 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6690
6691 if (kvm_x86_ops->get_nmi_mask(vcpu))
6692 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6693 else
6694 kvm_x86_ops->set_nmi_mask(vcpu, true);
6695
6696 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6697 kvm_rip_write(vcpu, 0x8000);
6698
6699 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6700 kvm_x86_ops->set_cr0(vcpu, cr0);
6701 vcpu->arch.cr0 = cr0;
6702
6703 kvm_x86_ops->set_cr4(vcpu, 0);
6704
18c3626e
PB		 6705 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6706 dt.address = dt.size = 0;
6707 kvm_x86_ops->set_idt(vcpu, &dt);
6708
660a5d51
PB		 6709 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6710
6711 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6712 cs.base = vcpu->arch.smbase;
6713
6714 ds.selector = 0;
6715 ds.base = 0;
6716
6717 cs.limit = ds.limit = 0xffffffff;
6718 cs.type = ds.type = 0x3;
6719 cs.dpl = ds.dpl = 0;
6720 cs.db = ds.db = 0;
6721 cs.s = ds.s = 1;
6722 cs.l = ds.l = 0;
6723 cs.g = ds.g = 1;
6724 cs.avl = ds.avl = 0;
6725 cs.present = ds.present = 1;
6726 cs.unusable = ds.unusable = 0;
6727 cs.padding = ds.padding = 0;
6728
6729 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6730 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6731 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6732 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6733 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6734 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6735
d6321d49 6736 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6737 kvm_x86_ops->set_efer(vcpu, 0);
6738
6739 kvm_update_cpuid(vcpu);
6740 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6741}
6742
ee2cd4b7 6743static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6744{
6745 vcpu->arch.smi_pending = true;
6746 kvm_make_request(KVM_REQ_EVENT, vcpu);
6747}
6748
2860c4b1
PB		 6749void kvm_make_scan_ioapic_request(struct kvm *kvm)
6750{
6751 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6752}
6753
3d81bc7e 6754static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6755{
5c919412
AS		 6756 u64 eoi_exit_bitmap[4];
6757
3d81bc7e
YZ		 6758 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6759 return;
c7c9c56c 6760
6308630b 6761 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6762
b053b2ae 6763 if (irqchip_split(vcpu->kvm))
6308630b 6764 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6765 else {
76dfafd5 6766 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6767 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6768 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6769 }
5c919412
AS		 6770 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6771 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6772 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6773}
6774
a70656b6
RK		 6775static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6776{
6777 ++vcpu->stat.tlb_flush;
6778 kvm_x86_ops->tlb_flush(vcpu);
6779}
6780
4256f43f
TC		 6781void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6782{
c24ae0dc
TC		 6783 struct page *page = NULL;
6784
35754c98 6785 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6786 return;
6787
4256f43f
TC		 6788 if (!kvm_x86_ops->set_apic_access_page_addr)
6789 return;
6790
c24ae0dc 6791 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6792 if (is_error_page(page))
6793 return;
c24ae0dc
TC		 6794 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6795
6796 /*
6797 * Do not pin apic access page in memory, the MMU notifier
6798 * will call us again if it is migrated or swapped out.
6799 */
6800 put_page(page);
4256f43f
TC		 6801}
6802EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6803
9357d939 6804/*
362c698f 6805 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6806 * exiting to the userspace. Otherwise, the value will be returned to the
6807 * userspace.
6808 */
851ba692 6809static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6810{
6811 int r;
62a193ed
MG		 6812 bool req_int_win =
6813 dm_request_for_irq_injection(vcpu) &&
6814 kvm_cpu_accept_dm_intr(vcpu);
6815
730dca42 6816 bool req_immediate_exit = false;
b6c7a5dc 6817
2fa6e1e1 6818 if (kvm_request_pending(vcpu)) {
a8eeb04a 6819 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6820 kvm_mmu_unload(vcpu);
a8eeb04a 6821 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6822 __kvm_migrate_timers(vcpu);
d828199e
MT		 6823 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6824 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6825 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6826 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6827 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6828 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6829 if (unlikely(r))
6830 goto out;
6831 }
a8eeb04a 6832 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6833 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6834 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6835 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6836 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6837 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6838 r = 0;
6839 goto out;
6840 }
a8eeb04a 6841 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6842 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6843 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6844 r = 0;
6845 goto out;
6846 }
af585b92
GN		 6847 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6848 /* Page is swapped out. Do synthetic halt */
6849 vcpu->arch.apf.halted = true;
6850 r = 1;
6851 goto out;
6852 }
c9aaa895
GC		 6853 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6854 record_steal_time(vcpu);
64d60670
PB		 6855 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6856 process_smi(vcpu);
7460fb4a
AK		 6857 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6858 process_nmi(vcpu);
f5132b01 6859 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6860 kvm_pmu_handle_event(vcpu);
f5132b01 6861 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6862 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6863 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6864 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6865 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6866 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6867 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6868 vcpu->run->eoi.vector =
6869 vcpu->arch.pending_ioapic_eoi;
6870 r = 0;
6871 goto out;
6872 }
6873 }
3d81bc7e
YZ		 6874 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6875 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6876 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6877 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6878 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6879 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6880 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6881 r = 0;
6882 goto out;
6883 }
e516cebb
AS		 6884 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6885 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6886 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6887 r = 0;
6888 goto out;
6889 }
db397571
AS		 6890 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6891 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6892 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6893 r = 0;
6894 goto out;
6895 }
f3b138c5
AS		 6896
6897 /*
6898 * KVM_REQ_HV_STIMER has to be processed after
6899 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6900 * depend on the guest clock being up-to-date
6901 */
1f4b34f8
AS		 6902 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6903 kvm_hv_process_stimers(vcpu);
2f52d58c 6904 }
b93463aa 6905
b463a6f7 6906 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6907 ++vcpu->stat.req_event;
66450a21
JK		 6908 kvm_apic_accept_events(vcpu);
6909 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6910 r = 1;
6911 goto out;
6912 }
6913
b6b8a145
JK		 6914 if (inject_pending_event(vcpu, req_int_win) != 0)
6915 req_immediate_exit = true;
321c5658 6916 else {
cc3d967f 6917 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6918 *
cc3d967f
LP		 6919 * SMIs have three cases:
6920 * 1) They can be nested, and then there is nothing to
6921 * do here because RSM will cause a vmexit anyway.
6922 * 2) There is an ISA-specific reason why SMI cannot be
6923 * injected, and the moment when this changes can be
6924 * intercepted.
6925 * 3) Or the SMI can be pending because
6926 * inject_pending_event has completed the injection
6927 * of an IRQ or NMI from the previous vmexit, and
6928 * then we request an immediate exit to inject the
6929 * SMI.
c43203ca
PB		 6930 */
6931 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6932 if (!kvm_x86_ops->enable_smi_window(vcpu))
6933 req_immediate_exit = true;
321c5658
YS		 6934 if (vcpu->arch.nmi_pending)
6935 kvm_x86_ops->enable_nmi_window(vcpu);
6936 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6937 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6938 WARN_ON(vcpu->arch.exception.pending);
321c5658 6939 }
b463a6f7
AK		 6940
6941 if (kvm_lapic_enabled(vcpu)) {
6942 update_cr8_intercept(vcpu);
6943 kvm_lapic_sync_to_vapic(vcpu);
6944 }
6945 }
6946
d8368af8
AK		 6947 r = kvm_mmu_reload(vcpu);
6948 if (unlikely(r)) {
d905c069 6949 goto cancel_injection;
d8368af8
AK		 6950 }
6951
b6c7a5dc
HB		 6952 preempt_disable();
6953
6954 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6955 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6956
6957 /*
6958 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6959 * IPI are then delayed after guest entry, which ensures that they
6960 * result in virtual interrupt delivery.
6961 */
6962 local_irq_disable();
6b7e2d09
XG		 6963 vcpu->mode = IN_GUEST_MODE;
6964
01b71917
MT		 6965 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6966
0f127d12 6967 /*
b95234c8 6968 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6969 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6970 *
6971 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6972 * pairs with the memory barrier implicit in pi_test_and_set_on
6973 * (see vmx_deliver_posted_interrupt).
6974 *
6975 * 3) This also orders the write to mode from any reads to the page
6976 * tables done while the VCPU is running. Please see the comment
6977 * in kvm_flush_remote_tlbs.
6b7e2d09 6978 */
01b71917 6979 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6980
b95234c8
PB		 6981 /*
6982 * This handles the case where a posted interrupt was
6983 * notified with kvm_vcpu_kick.
6984 */
6985 if (kvm_lapic_enabled(vcpu)) {
6986 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6987 kvm_x86_ops->sync_pir_to_irr(vcpu);
6988 }
32f88400 6989
2fa6e1e1 6990 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6991 || need_resched() || signal_pending(current)) {
6b7e2d09 6992 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6993 smp_wmb();
6c142801
AK		 6994 local_irq_enable();
6995 preempt_enable();
01b71917 6996 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6997 r = 1;
d905c069 6998 goto cancel_injection;
6c142801
AK		 6999 }
7000
fc5b7f3b
DM		 7001 kvm_load_guest_xcr0(vcpu);
7002
c43203ca
PB		 7003 if (req_immediate_exit) {
7004 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7005 smp_send_reschedule(vcpu->cpu);
c43203ca 7006 }
d6185f20 7007
8b89fe1f
PB		 7008 trace_kvm_entry(vcpu->vcpu_id);
7009 wait_lapic_expire(vcpu);
6edaa530 7010 guest_enter_irqoff();
b6c7a5dc 7011
42dbaa5a 7012 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7013 set_debugreg(0, 7);
7014 set_debugreg(vcpu->arch.eff_db[0], 0);
7015 set_debugreg(vcpu->arch.eff_db[1], 1);
7016 set_debugreg(vcpu->arch.eff_db[2], 2);
7017 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7018 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7019 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7020 }
b6c7a5dc 7021
851ba692 7022 kvm_x86_ops->run(vcpu);
b6c7a5dc 7023
c77fb5fe
PB		 7024 /*
7025 * Do this here before restoring debug registers on the host. And
7026 * since we do this before handling the vmexit, a DR access vmexit
7027 * can (a) read the correct value of the debug registers, (b) set
7028 * KVM_DEBUGREG_WONT_EXIT again.
7029 */
7030 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7031 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7032 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7033 kvm_update_dr0123(vcpu);
7034 kvm_update_dr6(vcpu);
7035 kvm_update_dr7(vcpu);
7036 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7037 }
7038
24f1e32c
FW		 7039 /*
7040 * If the guest has used debug registers, at least dr7
7041 * will be disabled while returning to the host.
7042 * If we don't have active breakpoints in the host, we don't
7043 * care about the messed up debug address registers. But if
7044 * we have some of them active, restore the old state.
7045 */
59d8eb53 7046 if (hw_breakpoint_active())
24f1e32c 7047 hw_breakpoint_restore();
42dbaa5a 7048
4ba76538 7049 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7050
6b7e2d09 7051 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7052 smp_wmb();
a547c6db 7053
fc5b7f3b
DM		 7054 kvm_put_guest_xcr0(vcpu);
7055
a547c6db 7056 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7057
7058 ++vcpu->stat.exits;
7059
f2485b3e 7060 guest_exit_irqoff();
b6c7a5dc 7061
f2485b3e 7062 local_irq_enable();
b6c7a5dc
HB		 7063 preempt_enable();
7064
f656ce01 7065 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7066
b6c7a5dc
HB		 7067 /*
7068 * Profile KVM exit RIPs:
7069 */
7070 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7071 unsigned long rip = kvm_rip_read(vcpu);
7072 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7073 }
7074
cc578287
ZA		 7075 if (unlikely(vcpu->arch.tsc_always_catchup))
7076 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7077
5cfb1d5a
MT		 7078 if (vcpu->arch.apic_attention)
7079 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7080
618232e2 7081 vcpu->arch.gpa_available = false;
851ba692 7082 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7083 return r;
7084
7085cancel_injection:
7086 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7087 if (unlikely(vcpu->arch.apic_attention))
7088 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7089out:
7090 return r;
7091}
b6c7a5dc 7092
362c698f
PB		 7093static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7094{
bf9f6ac8
FW		 7095 if (!kvm_arch_vcpu_runnable(vcpu) &&
7096 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7097 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7098 kvm_vcpu_block(vcpu);
7099 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7100
7101 if (kvm_x86_ops->post_block)
7102 kvm_x86_ops->post_block(vcpu);
7103
9c8fd1ba
PB		 7104 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7105 return 1;
7106 }
362c698f
PB		 7107
7108 kvm_apic_accept_events(vcpu);
7109 switch(vcpu->arch.mp_state) {
7110 case KVM_MP_STATE_HALTED:
7111 vcpu->arch.pv.pv_unhalted = false;
7112 vcpu->arch.mp_state =
7113 KVM_MP_STATE_RUNNABLE;
7114 case KVM_MP_STATE_RUNNABLE:
7115 vcpu->arch.apf.halted = false;
7116 break;
7117 case KVM_MP_STATE_INIT_RECEIVED:
7118 break;
7119 default:
7120 return -EINTR;
7121 break;
7122 }
7123 return 1;
7124}
09cec754 7125
5d9bc648
PB		 7126static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7127{
0ad3bed6
PB		 7128 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7129 kvm_x86_ops->check_nested_events(vcpu, false);
7130
5d9bc648
PB		 7131 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7132 !vcpu->arch.apf.halted);
7133}
7134
362c698f 7135static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7136{
7137 int r;
f656ce01 7138 struct kvm *kvm = vcpu->kvm;
d7690175 7139
f656ce01 7140 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7141
362c698f 7142 for (;;) {
58f800d5 7143 if (kvm_vcpu_running(vcpu)) {
851ba692 7144 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7145 } else {
362c698f 7146 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7147 }
7148
09cec754
GN		 7149 if (r <= 0)
7150 break;
7151
72875d8a 7152 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7153 if (kvm_cpu_has_pending_timer(vcpu))
7154 kvm_inject_pending_timer_irqs(vcpu);
7155
782d422b
MG		 7156 if (dm_request_for_irq_injection(vcpu) &&
7157 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7158 r = 0;
7159 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7160 ++vcpu->stat.request_irq_exits;
362c698f 7161 break;
09cec754 7162 }
af585b92
GN		 7163
7164 kvm_check_async_pf_completion(vcpu);
7165
09cec754
GN		 7166 if (signal_pending(current)) {
7167 r = -EINTR;
851ba692 7168 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7169 ++vcpu->stat.signal_exits;
362c698f 7170 break;
09cec754
GN		 7171 }
7172 if (need_resched()) {
f656ce01 7173 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7174 cond_resched();
f656ce01 7175 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7176 }
b6c7a5dc
HB		 7177 }
7178
f656ce01 7179 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7180
7181 return r;
7182}
7183
716d51ab
GN		 7184static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7185{
7186 int r;
7187 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7188 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7189 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7190 if (r != EMULATE_DONE)
7191 return 0;
7192 return 1;
7193}
7194
7195static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7196{
7197 BUG_ON(!vcpu->arch.pio.count);
7198
7199 return complete_emulated_io(vcpu);
7200}
7201
f78146b0
AK		 7202/*
7203 * Implements the following, as a state machine:
7204 *
7205 * read:
7206 * for each fragment
87da7e66
XG		 7207 * for each mmio piece in the fragment
7208 * write gpa, len
7209 * exit
7210 * copy data
f78146b0
AK		 7211 * execute insn
7212 *
7213 * write:
7214 * for each fragment
87da7e66
XG		 7215 * for each mmio piece in the fragment
7216 * write gpa, len
7217 * copy data
7218 * exit
f78146b0 7219 */
716d51ab 7220static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7221{
7222 struct kvm_run *run = vcpu->run;
f78146b0 7223 struct kvm_mmio_fragment *frag;
87da7e66 7224 unsigned len;
5287f194 7225
716d51ab 7226 BUG_ON(!vcpu->mmio_needed);
5287f194 7227
716d51ab 7228 /* Complete previous fragment */
87da7e66
XG		 7229 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7230 len = min(8u, frag->len);
716d51ab 7231 if (!vcpu->mmio_is_write)
87da7e66
XG		 7232 memcpy(frag->data, run->mmio.data, len);
7233
7234 if (frag->len <= 8) {
7235 /* Switch to the next fragment. */
7236 frag++;
7237 vcpu->mmio_cur_fragment++;
7238 } else {
7239 /* Go forward to the next mmio piece. */
7240 frag->data += len;
7241 frag->gpa += len;
7242 frag->len -= len;
7243 }
7244
a08d3b3b 7245 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7246 vcpu->mmio_needed = 0;
0912c977
PB		 7247
7248 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7249 if (vcpu->mmio_is_write)
716d51ab
GN		 7250 return 1;
7251 vcpu->mmio_read_completed = 1;
7252 return complete_emulated_io(vcpu);
7253 }
87da7e66 7254
716d51ab
GN		 7255 run->exit_reason = KVM_EXIT_MMIO;
7256 run->mmio.phys_addr = frag->gpa;
7257 if (vcpu->mmio_is_write)
87da7e66
XG		 7258 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7259 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7260 run->mmio.is_write = vcpu->mmio_is_write;
7261 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7262 return 0;
5287f194
AK		 7263}
7264
716d51ab 7265
b6c7a5dc
HB		 7266int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7267{
c5bedc68 7268 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7269 int r;
7270 sigset_t sigsaved;
7271
2ce03d85 7272 fpu__initialize(fpu);
e5c30142 7273
ac9f6dc0
AK		 7274 if (vcpu->sigset_active)
7275 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7276
a4535290 7277 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7278 if (kvm_run->immediate_exit) {
7279 r = -EINTR;
7280 goto out;
7281 }
b6c7a5dc 7282 kvm_vcpu_block(vcpu);
66450a21 7283 kvm_apic_accept_events(vcpu);
72875d8a 7284 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7285 r = -EAGAIN;
a0595000
JS		 7286 if (signal_pending(current)) {
7287 r = -EINTR;
7288 vcpu->run->exit_reason = KVM_EXIT_INTR;
7289 ++vcpu->stat.signal_exits;
7290 }
ac9f6dc0 7291 goto out;
b6c7a5dc
HB		 7292 }
7293
b6c7a5dc 7294 /* re-sync apic's tpr */
35754c98 7295 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7296 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7297 r = -EINVAL;
7298 goto out;
7299 }
7300 }
b6c7a5dc 7301
716d51ab
GN		 7302 if (unlikely(vcpu->arch.complete_userspace_io)) {
7303 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7304 vcpu->arch.complete_userspace_io = NULL;
7305 r = cui(vcpu);
7306 if (r <= 0)
7307 goto out;
7308 } else
7309 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7310
460df4c1
PB		 7311 if (kvm_run->immediate_exit)
7312 r = -EINTR;
7313 else
7314 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7315
7316out:
f1d86e46 7317 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7318 if (vcpu->sigset_active)
7319 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7320
b6c7a5dc
HB		 7321 return r;
7322}
7323
7324int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7325{
7ae441ea
GN		 7326 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7327 /*
7328 * We are here if userspace calls get_regs() in the middle of
7329 * instruction emulation. Registers state needs to be copied
4a969980 7330 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7331 * that usually, but some bad designed PV devices (vmware
7332 * backdoor interface) need this to work
7333 */
dd856efa 7334 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7335 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7336 }
5fdbf976
MT		 7337 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7338 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7339 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7340 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7341 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7342 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7343 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7344 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7345#ifdef CONFIG_X86_64
5fdbf976
MT		 7346 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7347 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7348 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7349 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7350 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7351 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7352 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7353 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7354#endif
7355
5fdbf976 7356 regs->rip = kvm_rip_read(vcpu);
91586a3b 7357 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7358
b6c7a5dc
HB		 7359 return 0;
7360}
7361
7362int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7363{
7ae441ea
GN		 7364 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7365 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7366
5fdbf976
MT		 7367 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7368 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7369 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7370 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7371 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7372 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7373 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7374 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7375#ifdef CONFIG_X86_64
5fdbf976
MT		 7376 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7377 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7378 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7379 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7380 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7381 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7382 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7383 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7384#endif
7385
5fdbf976 7386 kvm_rip_write(vcpu, regs->rip);
91586a3b 7387 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7388
b4f14abd
JK		 7389 vcpu->arch.exception.pending = false;
7390
3842d135
AK		 7391 kvm_make_request(KVM_REQ_EVENT, vcpu);
7392
b6c7a5dc
HB		 7393 return 0;
7394}
7395
b6c7a5dc
HB		 7396void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7397{
7398 struct kvm_segment cs;
7399
3e6e0aab 7400 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7401 *db = cs.db;
7402 *l = cs.l;
7403}
7404EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7405
7406int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7407 struct kvm_sregs *sregs)
7408{
89a27f4d 7409 struct desc_ptr dt;
b6c7a5dc 7410
3e6e0aab
GT		 7411 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7412 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7413 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7414 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7415 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7416 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7417
3e6e0aab
GT		 7418 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7419 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7420
7421 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7422 sregs->idt.limit = dt.size;
7423 sregs->idt.base = dt.address;
b6c7a5dc 7424 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7425 sregs->gdt.limit = dt.size;
7426 sregs->gdt.base = dt.address;
b6c7a5dc 7427
4d4ec087 7428 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7429 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7430 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7431 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7432 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7433 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7434 sregs->apic_base = kvm_get_apic_base(vcpu);
7435
923c61bb 7436 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7437
36752c9b 7438 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7439 set_bit(vcpu->arch.interrupt.nr,
7440 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7441
b6c7a5dc
HB		 7442 return 0;
7443}
7444
62d9f0db
MT		 7445int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7446 struct kvm_mp_state *mp_state)
7447{
66450a21 7448 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7449 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7450 vcpu->arch.pv.pv_unhalted)
7451 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7452 else
7453 mp_state->mp_state = vcpu->arch.mp_state;
7454
62d9f0db
MT		 7455 return 0;
7456}
7457
7458int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7459 struct kvm_mp_state *mp_state)
7460{
bce87cce 7461 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7462 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7463 return -EINVAL;
7464
28bf2888
DH		 7465 /* INITs are latched while in SMM */
7466 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7467 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7468 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7469 return -EINVAL;
7470
66450a21
JK		 7471 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7472 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7473 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7474 } else
7475 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7476 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7477 return 0;
7478}
7479
7f3d35fd
KW		 7480int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7481 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7482{
9d74191a 7483 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7484 int ret;
e01c2426 7485
8ec4722d 7486 init_emulate_ctxt(vcpu);
c697518a 7487
7f3d35fd 7488 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7489 has_error_code, error_code);
c697518a 7490
c697518a 7491 if (ret)
19d04437 7492 return EMULATE_FAIL;
37817f29 7493
9d74191a
TY		 7494 kvm_rip_write(vcpu, ctxt->eip);
7495 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7496 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7497 return EMULATE_DONE;
37817f29
IE		 7498}
7499EXPORT_SYMBOL_GPL(kvm_task_switch);
7500
b6c7a5dc
HB		 7501int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7502 struct kvm_sregs *sregs)
7503{
58cb628d 7504 struct msr_data apic_base_msr;
b6c7a5dc 7505 int mmu_reset_needed = 0;
63f42e02 7506 int pending_vec, max_bits, idx;
89a27f4d 7507 struct desc_ptr dt;
b6c7a5dc 7508
d6321d49
RK		 7509 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7510 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7511 return -EINVAL;
7512
d3802286
JM		 7513 apic_base_msr.data = sregs->apic_base;
7514 apic_base_msr.host_initiated = true;
7515 if (kvm_set_apic_base(vcpu, &apic_base_msr))
6d1068b3
PM		 7516 return -EINVAL;
7517
89a27f4d
GN		 7518 dt.size = sregs->idt.limit;
7519 dt.address = sregs->idt.base;
b6c7a5dc 7520 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7521 dt.size = sregs->gdt.limit;
7522 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7523 kvm_x86_ops->set_gdt(vcpu, &dt);
7524
ad312c7c 7525 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7526 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7527 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7528 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7529
2d3ad1f4 7530 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7531
f6801dff 7532 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7533 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7534
4d4ec087 7535 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7536 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7537 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7538
fc78f519 7539 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7540 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7541 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7542 kvm_update_cpuid(vcpu);
63f42e02
XG		 7543
7544 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7545 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7546 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7547 mmu_reset_needed = 1;
7548 }
63f42e02 7549 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7550
7551 if (mmu_reset_needed)
7552 kvm_mmu_reset_context(vcpu);
7553
a50abc3b 7554 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7555 pending_vec = find_first_bit(
7556 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7557 if (pending_vec < max_bits) {
66fd3f7f 7558 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7559 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7560 }
7561
3e6e0aab
GT		 7562 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7563 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7564 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7565 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7566 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7567 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7568
3e6e0aab
GT		 7569 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7570 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7571
5f0269f5
ME		 7572 update_cr8_intercept(vcpu);
7573
9c3e4aab 7574 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7575 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7576 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7577 !is_protmode(vcpu))
9c3e4aab
MT		 7578 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7579
3842d135
AK		 7580 kvm_make_request(KVM_REQ_EVENT, vcpu);
7581
b6c7a5dc
HB		 7582 return 0;
7583}
7584
d0bfb940
JK		 7585int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7586 struct kvm_guest_debug *dbg)
b6c7a5dc 7587{
355be0b9 7588 unsigned long rflags;
ae675ef0 7589 int i, r;
b6c7a5dc 7590
4f926bf2
JK		 7591 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7592 r = -EBUSY;
7593 if (vcpu->arch.exception.pending)
2122ff5e 7594 goto out;
4f926bf2
JK		 7595 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7596 kvm_queue_exception(vcpu, DB_VECTOR);
7597 else
7598 kvm_queue_exception(vcpu, BP_VECTOR);
7599 }
7600
91586a3b
JK		 7601 /*
7602 * Read rflags as long as potentially injected trace flags are still
7603 * filtered out.
7604 */
7605 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7606
7607 vcpu->guest_debug = dbg->control;
7608 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7609 vcpu->guest_debug = 0;
7610
7611 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7612 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7613 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7614 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7615 } else {
7616 for (i = 0; i < KVM_NR_DB_REGS; i++)
7617 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7618 }
c8639010 7619 kvm_update_dr7(vcpu);
ae675ef0 7620
f92653ee
JK		 7621 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7622 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7623 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7624
91586a3b
JK		 7625 /*
7626 * Trigger an rflags update that will inject or remove the trace
7627 * flags.
7628 */
7629 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7630
a96036b8 7631 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7632
4f926bf2 7633 r = 0;
d0bfb940 7634
2122ff5e 7635out:
b6c7a5dc
HB		 7636
7637 return r;
7638}
7639
8b006791
ZX		 7640/*
7641 * Translate a guest virtual address to a guest physical address.
7642 */
7643int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7644 struct kvm_translation *tr)
7645{
7646 unsigned long vaddr = tr->linear_address;
7647 gpa_t gpa;
f656ce01 7648 int idx;
8b006791 7649
f656ce01 7650 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7651 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7652 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7653 tr->physical_address = gpa;
7654 tr->valid = gpa != UNMAPPED_GVA;
7655 tr->writeable = 1;
7656 tr->usermode = 0;
8b006791
ZX		 7657
7658 return 0;
7659}
7660
d0752060
HB		 7661int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7662{
c47ada30 7663 struct fxregs_state *fxsave =
7366ed77 7664 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7665
d0752060
HB		 7666 memcpy(fpu->fpr, fxsave->st_space, 128);
7667 fpu->fcw = fxsave->cwd;
7668 fpu->fsw = fxsave->swd;
7669 fpu->ftwx = fxsave->twd;
7670 fpu->last_opcode = fxsave->fop;
7671 fpu->last_ip = fxsave->rip;
7672 fpu->last_dp = fxsave->rdp;
7673 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7674
d0752060
HB		 7675 return 0;
7676}
7677
7678int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7679{
c47ada30 7680 struct fxregs_state *fxsave =
7366ed77 7681 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7682
d0752060
HB		 7683 memcpy(fxsave->st_space, fpu->fpr, 128);
7684 fxsave->cwd = fpu->fcw;
7685 fxsave->swd = fpu->fsw;
7686 fxsave->twd = fpu->ftwx;
7687 fxsave->fop = fpu->last_opcode;
7688 fxsave->rip = fpu->last_ip;
7689 fxsave->rdp = fpu->last_dp;
7690 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7691
d0752060
HB		 7692 return 0;
7693}
7694
0ee6a517 7695static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7696{
bf935b0b 7697 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7698 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7699 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7700 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7701
2acf923e
DC		 7702 /*
7703 * Ensure guest xcr0 is valid for loading
7704 */
d91cab78 7705 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7706
ad312c7c 7707 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7708}
d0752060
HB		 7709
7710void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7711{
2608d7a1 7712 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7713 return;
7714
2acf923e
DC		 7715 /*
7716 * Restore all possible states in the guest,
7717 * and assume host would use all available bits.
7718 * Guest xcr0 would be loaded later.
7719 */
d0752060 7720 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7721 __kernel_fpu_begin();
38cfd5e3
PB		 7722 /* PKRU is separately restored in kvm_x86_ops->run. */
7723 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7724 ~XFEATURE_MASK_PKRU);
0c04851c 7725 trace_kvm_fpu(1);
d0752060 7726}
d0752060
HB		 7727
7728void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7729{
3d42de25 7730 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7731 return;
7732
7733 vcpu->guest_fpu_loaded = 0;
4f836347 7734 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7735 __kernel_fpu_end();
f096ed85 7736 ++vcpu->stat.fpu_reload;
0c04851c 7737 trace_kvm_fpu(0);
d0752060 7738}
e9b11c17
ZX		 7739
7740void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7741{
bd768e14
IY		 7742 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7743
12f9a48f 7744 kvmclock_reset(vcpu);
7f1ea208 7745
e9b11c17 7746 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7747 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7748}
7749
7750struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7751 unsigned int id)
7752{
c447e76b
LL		 7753 struct kvm_vcpu *vcpu;
7754
6755bae8
ZA		 7755 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7756 printk_once(KERN_WARNING
7757 "kvm: SMP vm created on host with unstable TSC; "
7758 "guest TSC will not be reliable\n");
c447e76b
LL		 7759
7760 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7761
c447e76b 7762 return vcpu;
26e5215f 7763}
e9b11c17 7764
26e5215f
AK		 7765int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7766{
7767 int r;
e9b11c17 7768
19efffa2 7769 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7770 r = vcpu_load(vcpu);
7771 if (r)
7772 return r;
d28bc9dd 7773 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7774 kvm_mmu_setup(vcpu);
e9b11c17 7775 vcpu_put(vcpu);
26e5215f 7776 return r;
e9b11c17
ZX		 7777}
7778
31928aa5 7779void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7780{
8fe8ab46 7781 struct msr_data msr;
332967a3 7782 struct kvm *kvm = vcpu->kvm;
42897d86 7783
d3457c87
RK		 7784 kvm_hv_vcpu_postcreate(vcpu);
7785
31928aa5
DD		 7786 if (vcpu_load(vcpu))
7787 return;
8fe8ab46
WA		 7788 msr.data = 0x0;
7789 msr.index = MSR_IA32_TSC;
7790 msr.host_initiated = true;
7791 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7792 vcpu_put(vcpu);
7793
630994b3
MT		 7794 if (!kvmclock_periodic_sync)
7795 return;
7796
332967a3
AJ		 7797 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7798 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7799}
7800
d40ccc62 7801void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7802{
9fc77441 7803 int r;
344d9588
GN		 7804 vcpu->arch.apf.msr_val = 0;
7805
9fc77441
MT		 7806 r = vcpu_load(vcpu);
7807 BUG_ON(r);
e9b11c17
ZX		 7808 kvm_mmu_unload(vcpu);
7809 vcpu_put(vcpu);
7810
7811 kvm_x86_ops->vcpu_free(vcpu);
7812}
7813
d28bc9dd 7814void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7815{
e69fab5d
PB		 7816 vcpu->arch.hflags = 0;
7817
c43203ca 7818 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7819 atomic_set(&vcpu->arch.nmi_queued, 0);
7820 vcpu->arch.nmi_pending = 0;
448fa4a9 7821 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7822 kvm_clear_interrupt_queue(vcpu);
7823 kvm_clear_exception_queue(vcpu);
664f8e26 7824 vcpu->arch.exception.pending = false;
448fa4a9 7825
42dbaa5a 7826 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7827 kvm_update_dr0123(vcpu);
6f43ed01 7828 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7829 kvm_update_dr6(vcpu);
42dbaa5a 7830 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7831 kvm_update_dr7(vcpu);
42dbaa5a 7832
1119022c
NA		 7833 vcpu->arch.cr2 = 0;
7834
3842d135 7835 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7836 vcpu->arch.apf.msr_val = 0;
c9aaa895 7837 vcpu->arch.st.msr_val = 0;
3842d135 7838
12f9a48f
GC		 7839 kvmclock_reset(vcpu);
7840
af585b92
GN		 7841 kvm_clear_async_pf_completion_queue(vcpu);
7842 kvm_async_pf_hash_reset(vcpu);
7843 vcpu->arch.apf.halted = false;
3842d135 7844
a554d207
WL		 7845 if (kvm_mpx_supported()) {
7846 void *mpx_state_buffer;
7847
7848 /*
7849 * To avoid have the INIT path from kvm_apic_has_events() that be
7850 * called with loaded FPU and does not let userspace fix the state.
7851 */
7852 kvm_put_guest_fpu(vcpu);
7853 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7854 XFEATURE_MASK_BNDREGS);
7855 if (mpx_state_buffer)
7856 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7857 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7858 XFEATURE_MASK_BNDCSR);
7859 if (mpx_state_buffer)
7860 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
7861 }
7862
64d60670 7863 if (!init_event) {
d28bc9dd 7864 kvm_pmu_reset(vcpu);
64d60670 7865 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7866
7867 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7868 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7869
7870 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7871 }
f5132b01 7872
66f7b72e
JS		 7873 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7874 vcpu->arch.regs_avail = ~0;
7875 vcpu->arch.regs_dirty = ~0;
7876
a554d207
WL		 7877 vcpu->arch.ia32_xss = 0;
7878
d28bc9dd 7879 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7880}
7881
2b4a273b 7882void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7883{
7884 struct kvm_segment cs;
7885
7886 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7887 cs.selector = vector << 8;
7888 cs.base = vector << 12;
7889 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7890 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7891}
7892
13a34e06 7893int kvm_arch_hardware_enable(void)
e9b11c17 7894{
ca84d1a2
ZA		 7895 struct kvm *kvm;
7896 struct kvm_vcpu *vcpu;
7897 int i;
0dd6a6ed
ZA		 7898 int ret;
7899 u64 local_tsc;
7900 u64 max_tsc = 0;
7901 bool stable, backwards_tsc = false;
18863bdd
AK		 7902
7903 kvm_shared_msr_cpu_online();
13a34e06 7904 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7905 if (ret != 0)
7906 return ret;
7907
4ea1636b 7908 local_tsc = rdtsc();
0dd6a6ed
ZA		 7909 stable = !check_tsc_unstable();
7910 list_for_each_entry(kvm, &vm_list, vm_list) {
7911 kvm_for_each_vcpu(i, vcpu, kvm) {
7912 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7913 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7914 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7915 backwards_tsc = true;
7916 if (vcpu->arch.last_host_tsc > max_tsc)
7917 max_tsc = vcpu->arch.last_host_tsc;
7918 }
7919 }
7920 }
7921
7922 /*
7923 * Sometimes, even reliable TSCs go backwards. This happens on
7924 * platforms that reset TSC during suspend or hibernate actions, but
7925 * maintain synchronization. We must compensate. Fortunately, we can
7926 * detect that condition here, which happens early in CPU bringup,
7927 * before any KVM threads can be running. Unfortunately, we can't
7928 * bring the TSCs fully up to date with real time, as we aren't yet far
7929 * enough into CPU bringup that we know how much real time has actually
108b249c 7930 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7931 * variables that haven't been updated yet.
7932 *
7933 * So we simply find the maximum observed TSC above, then record the
7934 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7935 * the adjustment will be applied. Note that we accumulate
7936 * adjustments, in case multiple suspend cycles happen before some VCPU
7937 * gets a chance to run again. In the event that no KVM threads get a
7938 * chance to run, we will miss the entire elapsed period, as we'll have
7939 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7940 * loose cycle time. This isn't too big a deal, since the loss will be
7941 * uniform across all VCPUs (not to mention the scenario is extremely
7942 * unlikely). It is possible that a second hibernate recovery happens
7943 * much faster than a first, causing the observed TSC here to be
7944 * smaller; this would require additional padding adjustment, which is
7945 * why we set last_host_tsc to the local tsc observed here.
7946 *
7947 * N.B. - this code below runs only on platforms with reliable TSC,
7948 * as that is the only way backwards_tsc is set above. Also note
7949 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7950 * have the same delta_cyc adjustment applied if backwards_tsc
7951 * is detected. Note further, this adjustment is only done once,
7952 * as we reset last_host_tsc on all VCPUs to stop this from being
7953 * called multiple times (one for each physical CPU bringup).
7954 *
4a969980 7955 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7956 * will be compensated by the logic in vcpu_load, which sets the TSC to
7957 * catchup mode. This will catchup all VCPUs to real time, but cannot
7958 * guarantee that they stay in perfect synchronization.
7959 */
7960 if (backwards_tsc) {
7961 u64 delta_cyc = max_tsc - local_tsc;
7962 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7963 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7964 kvm_for_each_vcpu(i, vcpu, kvm) {
7965 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7966 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7967 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7968 }
7969
7970 /*
7971 * We have to disable TSC offset matching.. if you were
7972 * booting a VM while issuing an S4 host suspend....
7973 * you may have some problem. Solving this issue is
7974 * left as an exercise to the reader.
7975 */
7976 kvm->arch.last_tsc_nsec = 0;
7977 kvm->arch.last_tsc_write = 0;
7978 }
7979
7980 }
7981 return 0;
e9b11c17
ZX		 7982}
7983
13a34e06 7984void kvm_arch_hardware_disable(void)
e9b11c17 7985{
13a34e06
RK		 7986 kvm_x86_ops->hardware_disable();
7987 drop_user_return_notifiers();
e9b11c17
ZX		 7988}
7989
7990int kvm_arch_hardware_setup(void)
7991{
9e9c3fe4
NA		 7992 int r;
7993
7994 r = kvm_x86_ops->hardware_setup();
7995 if (r != 0)
7996 return r;
7997
35181e86
HZ		 7998 if (kvm_has_tsc_control) {
7999 /*
8000 * Make sure the user can only configure tsc_khz values that
8001 * fit into a signed integer.
8002 * A min value is not calculated needed because it will always
8003 * be 1 on all machines.
8004 */
8005 u64 max = min(0x7fffffffULL,
8006 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8007 kvm_max_guest_tsc_khz = max;
8008
ad721883 8009 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8010 }
ad721883 8011
9e9c3fe4
NA		 8012 kvm_init_msr_list();
8013 return 0;
e9b11c17
ZX		 8014}
8015
8016void kvm_arch_hardware_unsetup(void)
8017{
8018 kvm_x86_ops->hardware_unsetup();
8019}
8020
8021void kvm_arch_check_processor_compat(void *rtn)
8022{
8023 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8024}
8025
8026bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8027{
8028 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8029}
8030EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8031
8032bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8033{
8034 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8035}
8036
54e9818f 8037struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8038EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8039
e9b11c17
ZX		 8040int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8041{
8042 struct page *page;
e9b11c17
ZX		 8043 int r;
8044
b2a05fef 8045 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8046 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8047 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8048 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8049 else
a4535290 8050 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8051
8052 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8053 if (!page) {
8054 r = -ENOMEM;
8055 goto fail;
8056 }
ad312c7c 8057 vcpu->arch.pio_data = page_address(page);
e9b11c17 8058
cc578287 8059 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8060
e9b11c17
ZX		 8061 r = kvm_mmu_create(vcpu);
8062 if (r < 0)
8063 goto fail_free_pio_data;
8064
26de7988 8065 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8066 r = kvm_create_lapic(vcpu);
8067 if (r < 0)
8068 goto fail_mmu_destroy;
54e9818f
GN		 8069 } else
8070 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8071
890ca9ae
HY		 8072 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8073 GFP_KERNEL);
8074 if (!vcpu->arch.mce_banks) {
8075 r = -ENOMEM;
443c39bc 8076 goto fail_free_lapic;
890ca9ae
HY		 8077 }
8078 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8079
f1797359
WY		 8080 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8081 r = -ENOMEM;
f5f48ee1 8082 goto fail_free_mce_banks;
f1797359 8083 }
f5f48ee1 8084
0ee6a517 8085 fx_init(vcpu);
66f7b72e 8086
4344ee98 8087 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8088
5a4f55cd
EK		 8089 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8090
74545705
RK		 8091 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8092
af585b92 8093 kvm_async_pf_hash_reset(vcpu);
f5132b01 8094 kvm_pmu_init(vcpu);
af585b92 8095
1c1a9ce9 8096 vcpu->arch.pending_external_vector = -1;
de63ad4c 8097 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8098
5c919412
AS		 8099 kvm_hv_vcpu_init(vcpu);
8100
e9b11c17 8101 return 0;
0ee6a517 8102
f5f48ee1
SY		 8103fail_free_mce_banks:
8104 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8105fail_free_lapic:
8106 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8107fail_mmu_destroy:
8108 kvm_mmu_destroy(vcpu);
8109fail_free_pio_data:
ad312c7c 8110 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8111fail:
8112 return r;
8113}
8114
8115void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8116{
f656ce01
MT		 8117 int idx;
8118
1f4b34f8 8119 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8120 kvm_pmu_destroy(vcpu);
36cb93fd 8121 kfree(vcpu->arch.mce_banks);
e9b11c17 8122 kvm_free_lapic(vcpu);
f656ce01 8123 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8124 kvm_mmu_destroy(vcpu);
f656ce01 8125 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8126 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8127 if (!lapic_in_kernel(vcpu))
54e9818f 8128 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8129}
d19a9cd2 8130
e790d9ef
RK		 8131void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8132{
ae97a3b8 8133 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8134}
8135
e08b9637 8136int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8137{
e08b9637
CO		 8138 if (type)
8139 return -EINVAL;
8140
6ef768fa 8141 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8142 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8143 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8144 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8145 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8146
5550af4d
SY		 8147 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8148 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8149 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8150 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8151 &kvm->arch.irq_sources_bitmap);
5550af4d 8152
038f8c11 8153 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8154 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8155 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8156 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8157
108b249c 8158 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8159 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8160
7e44e449 8161 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8162 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8163
0eb05bf2 8164 kvm_page_track_init(kvm);
13d268ca 8165 kvm_mmu_init_vm(kvm);
0eb05bf2 8166
03543133
SS		 8167 if (kvm_x86_ops->vm_init)
8168 return kvm_x86_ops->vm_init(kvm);
8169
d89f5eff 8170 return 0;
d19a9cd2
ZX		 8171}
8172
8173static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8174{
9fc77441
MT		 8175 int r;
8176 r = vcpu_load(vcpu);
8177 BUG_ON(r);
d19a9cd2
ZX		 8178 kvm_mmu_unload(vcpu);
8179 vcpu_put(vcpu);
8180}
8181
8182static void kvm_free_vcpus(struct kvm *kvm)
8183{
8184 unsigned int i;
988a2cae 8185 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8186
8187 /*
8188 * Unpin any mmu pages first.
8189 */
af585b92
GN		 8190 kvm_for_each_vcpu(i, vcpu, kvm) {
8191 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8192 kvm_unload_vcpu_mmu(vcpu);
af585b92 8193 }
988a2cae
GN		 8194 kvm_for_each_vcpu(i, vcpu, kvm)
8195 kvm_arch_vcpu_free(vcpu);
8196
8197 mutex_lock(&kvm->lock);
8198 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8199 kvm->vcpus[i] = NULL;
d19a9cd2 8200
988a2cae
GN		 8201 atomic_set(&kvm->online_vcpus, 0);
8202 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8203}
8204
ad8ba2cd
SY		 8205void kvm_arch_sync_events(struct kvm *kvm)
8206{
332967a3 8207 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8208 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8209 kvm_free_pit(kvm);
ad8ba2cd
SY		 8210}
8211
1d8007bd 8212int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8213{
8214 int i, r;
25188b99 8215 unsigned long hva;
f0d648bd
PB		 8216 struct kvm_memslots *slots = kvm_memslots(kvm);
8217 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8218
8219 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8220 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8221 return -EINVAL;
9da0e4d5 8222
f0d648bd
PB		 8223 slot = id_to_memslot(slots, id);
8224 if (size) {
b21629da 8225 if (slot->npages)
f0d648bd
PB		 8226 return -EEXIST;
8227
8228 /*
8229 * MAP_SHARED to prevent internal slot pages from being moved
8230 * by fork()/COW.
8231 */
8232 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8233 MAP_SHARED | MAP_ANONYMOUS, 0);
8234 if (IS_ERR((void *)hva))
8235 return PTR_ERR((void *)hva);
8236 } else {
8237 if (!slot->npages)
8238 return 0;
8239
8240 hva = 0;
8241 }
8242
8243 old = *slot;
9da0e4d5 8244 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8245 struct kvm_userspace_memory_region m;
9da0e4d5 8246
1d8007bd
PB		 8247 m.slot = id | (i << 16);
8248 m.flags = 0;
8249 m.guest_phys_addr = gpa;
f0d648bd 8250 m.userspace_addr = hva;
1d8007bd 8251 m.memory_size = size;
9da0e4d5
PB		 8252 r = __kvm_set_memory_region(kvm, &m);
8253 if (r < 0)
8254 return r;
8255 }
8256
f0d648bd
PB		 8257 if (!size) {
8258 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8259 WARN_ON(r < 0);
8260 }
8261
9da0e4d5
PB		 8262 return 0;
8263}
8264EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8265
1d8007bd 8266int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8267{
8268 int r;
8269
8270 mutex_lock(&kvm->slots_lock);
1d8007bd 8271 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8272 mutex_unlock(&kvm->slots_lock);
8273
8274 return r;
8275}
8276EXPORT_SYMBOL_GPL(x86_set_memory_region);
8277
d19a9cd2
ZX		 8278void kvm_arch_destroy_vm(struct kvm *kvm)
8279{
27469d29
AH		 8280 if (current->mm == kvm->mm) {
8281 /*
8282 * Free memory regions allocated on behalf of userspace,
8283 * unless the the memory map has changed due to process exit
8284 * or fd copying.
8285 */
1d8007bd
PB		 8286 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8287 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8288 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8289 }
03543133
SS		 8290 if (kvm_x86_ops->vm_destroy)
8291 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8292 kvm_pic_destroy(kvm);
8293 kvm_ioapic_destroy(kvm);
d19a9cd2 8294 kvm_free_vcpus(kvm);
af1bae54 8295 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8296 kvm_mmu_uninit_vm(kvm);
2beb6dad 8297 kvm_page_track_cleanup(kvm);
d19a9cd2 8298}
0de10343 8299
5587027c 8300void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8301 struct kvm_memory_slot *dont)
8302{
8303 int i;
8304
d89cc617
TY		 8305 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8306 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8307 kvfree(free->arch.rmap[i]);
d89cc617 8308 free->arch.rmap[i] = NULL;
77d11309 8309 }
d89cc617
TY		 8310 if (i == 0)
8311 continue;
8312
8313 if (!dont || free->arch.lpage_info[i - 1] !=
8314 dont->arch.lpage_info[i - 1]) {
548ef284 8315 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8316 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8317 }
8318 }
21ebbeda
XG		 8319
8320 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8321}
8322
5587027c
AK		 8323int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8324 unsigned long npages)
db3fe4eb
TY		 8325{
8326 int i;
8327
d89cc617 8328 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8329 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8330 unsigned long ugfn;
8331 int lpages;
d89cc617 8332 int level = i + 1;
db3fe4eb
TY		 8333
8334 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8335 slot->base_gfn, level) + 1;
8336
d89cc617 8337 slot->arch.rmap[i] =
a7c3e901 8338 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8339 if (!slot->arch.rmap[i])
77d11309 8340 goto out_free;
d89cc617
TY		 8341 if (i == 0)
8342 continue;
77d11309 8343
a7c3e901 8344 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8345 if (!linfo)
db3fe4eb
TY		 8346 goto out_free;
8347
92f94f1e
XG		 8348 slot->arch.lpage_info[i - 1] = linfo;
8349
db3fe4eb 8350 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8351 linfo[0].disallow_lpage = 1;
db3fe4eb 8352 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8353 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8354 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8355 /*
8356 * If the gfn and userspace address are not aligned wrt each
8357 * other, or if explicitly asked to, disable large page
8358 * support for this slot
8359 */
8360 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8361 !kvm_largepages_enabled()) {
8362 unsigned long j;
8363
8364 for (j = 0; j < lpages; ++j)
92f94f1e 8365 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8366 }
8367 }
8368
21ebbeda
XG		 8369 if (kvm_page_track_create_memslot(slot, npages))
8370 goto out_free;
8371
db3fe4eb
TY		 8372 return 0;
8373
8374out_free:
d89cc617 8375 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8376 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8377 slot->arch.rmap[i] = NULL;
8378 if (i == 0)
8379 continue;
8380
548ef284 8381 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8382 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8383 }
8384 return -ENOMEM;
8385}
8386
15f46015 8387void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8388{
e6dff7d1
TY		 8389 /*
8390 * memslots->generation has been incremented.
8391 * mmio generation may have reached its maximum value.
8392 */
54bf36aa 8393 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8394}
8395
f7784b8e
MT		 8396int kvm_arch_prepare_memory_region(struct kvm *kvm,
8397 struct kvm_memory_slot *memslot,
09170a49 8398 const struct kvm_userspace_memory_region *mem,
7b6195a9 8399 enum kvm_mr_change change)
0de10343 8400{
f7784b8e
MT		 8401 return 0;
8402}
8403
88178fd4
KH		 8404static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8405 struct kvm_memory_slot *new)
8406{
8407 /* Still write protect RO slot */
8408 if (new->flags & KVM_MEM_READONLY) {
8409 kvm_mmu_slot_remove_write_access(kvm, new);
8410 return;
8411 }
8412
8413 /*
8414 * Call kvm_x86_ops dirty logging hooks when they are valid.
8415 *
8416 * kvm_x86_ops->slot_disable_log_dirty is called when:
8417 *
8418 * - KVM_MR_CREATE with dirty logging is disabled
8419 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8420 *
8421 * The reason is, in case of PML, we need to set D-bit for any slots
8422 * with dirty logging disabled in order to eliminate unnecessary GPA
8423 * logging in PML buffer (and potential PML buffer full VMEXT). This
8424 * guarantees leaving PML enabled during guest's lifetime won't have
8425 * any additonal overhead from PML when guest is running with dirty
8426 * logging disabled for memory slots.
8427 *
8428 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8429 * to dirty logging mode.
8430 *
8431 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8432 *
8433 * In case of write protect:
8434 *
8435 * Write protect all pages for dirty logging.
8436 *
8437 * All the sptes including the large sptes which point to this
8438 * slot are set to readonly. We can not create any new large
8439 * spte on this slot until the end of the logging.
8440 *
8441 * See the comments in fast_page_fault().
8442 */
8443 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8444 if (kvm_x86_ops->slot_enable_log_dirty)
8445 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8446 else
8447 kvm_mmu_slot_remove_write_access(kvm, new);
8448 } else {
8449 if (kvm_x86_ops->slot_disable_log_dirty)
8450 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8451 }
8452}
8453
f7784b8e 8454void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8455 const struct kvm_userspace_memory_region *mem,
8482644a 8456 const struct kvm_memory_slot *old,
f36f3f28 8457 const struct kvm_memory_slot *new,
8482644a 8458 enum kvm_mr_change change)
f7784b8e 8459{
8482644a 8460 int nr_mmu_pages = 0;
f7784b8e 8461
48c0e4e9
XG		 8462 if (!kvm->arch.n_requested_mmu_pages)
8463 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8464
48c0e4e9 8465 if (nr_mmu_pages)
0de10343 8466 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8467
3ea3b7fa
WL		 8468 /*
8469 * Dirty logging tracks sptes in 4k granularity, meaning that large
8470 * sptes have to be split. If live migration is successful, the guest
8471 * in the source machine will be destroyed and large sptes will be
8472 * created in the destination. However, if the guest continues to run
8473 * in the source machine (for example if live migration fails), small
8474 * sptes will remain around and cause bad performance.
8475 *
8476 * Scan sptes if dirty logging has been stopped, dropping those
8477 * which can be collapsed into a single large-page spte. Later
8478 * page faults will create the large-page sptes.
8479 */
8480 if ((change != KVM_MR_DELETE) &&
8481 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8482 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8483 kvm_mmu_zap_collapsible_sptes(kvm, new);
8484
c972f3b1 8485 /*
88178fd4 8486 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8487 *
88178fd4
KH		 8488 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8489 * been zapped so no dirty logging staff is needed for old slot. For
8490 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8491 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8492 *
8493 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8494 */
88178fd4 8495 if (change != KVM_MR_DELETE)
f36f3f28 8496 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8497}
1d737c8a 8498
2df72e9b 8499void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8500{
6ca18b69 8501 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8502}
8503
2df72e9b
MT		 8504void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8505 struct kvm_memory_slot *slot)
8506{
ae7cd873 8507 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8508}
8509
5d9bc648
PB		 8510static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8511{
8512 if (!list_empty_careful(&vcpu->async_pf.done))
8513 return true;
8514
8515 if (kvm_apic_has_events(vcpu))
8516 return true;
8517
8518 if (vcpu->arch.pv.pv_unhalted)
8519 return true;
8520
a5f01f8e
WL		 8521 if (vcpu->arch.exception.pending)
8522 return true;
8523
47a66eed
Z		 8524 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8525 (vcpu->arch.nmi_pending &&
8526 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8527 return true;
8528
47a66eed
Z		 8529 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8530 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8531 return true;
8532
5d9bc648
PB		 8533 if (kvm_arch_interrupt_allowed(vcpu) &&
8534 kvm_cpu_has_interrupt(vcpu))
8535 return true;
8536
1f4b34f8
AS		 8537 if (kvm_hv_has_stimer_pending(vcpu))
8538 return true;
8539
5d9bc648
PB		 8540 return false;
8541}
8542
1d737c8a
ZX		 8543int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8544{
5d9bc648 8545 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8546}
5736199a 8547
199b5763
LM		 8548bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8549{
de63ad4c 8550 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8551}
8552
b6d33834 8553int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8554{
b6d33834 8555 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8556}
78646121
GN		 8557
8558int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8559{
8560 return kvm_x86_ops->interrupt_allowed(vcpu);
8561}
229456fc 8562
82b32774 8563unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8564{
82b32774
NA		 8565 if (is_64_bit_mode(vcpu))
8566 return kvm_rip_read(vcpu);
8567 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8568 kvm_rip_read(vcpu));
8569}
8570EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8571
82b32774
NA		 8572bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8573{
8574 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8575}
8576EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8577
94fe45da
JK		 8578unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8579{
8580 unsigned long rflags;
8581
8582 rflags = kvm_x86_ops->get_rflags(vcpu);
8583 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8584 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8585 return rflags;
8586}
8587EXPORT_SYMBOL_GPL(kvm_get_rflags);
8588
6addfc42 8589static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8590{
8591 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8592 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8593 rflags |= X86_EFLAGS_TF;
94fe45da 8594 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8595}
8596
8597void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8598{
8599 __kvm_set_rflags(vcpu, rflags);
3842d135 8600 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8601}
8602EXPORT_SYMBOL_GPL(kvm_set_rflags);
8603
56028d08
GN		 8604void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8605{
8606 int r;
8607
fb67e14f 8608 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8609 work->wakeup_all)
56028d08
GN		 8610 return;
8611
8612 r = kvm_mmu_reload(vcpu);
8613 if (unlikely(r))
8614 return;
8615
fb67e14f
XG		 8616 if (!vcpu->arch.mmu.direct_map &&
8617 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8618 return;
8619
56028d08
GN		 8620 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8621}
8622
af585b92
GN		 8623static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8624{
8625 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8626}
8627
8628static inline u32 kvm_async_pf_next_probe(u32 key)
8629{
8630 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8631}
8632
8633static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8634{
8635 u32 key = kvm_async_pf_hash_fn(gfn);
8636
8637 while (vcpu->arch.apf.gfns[key] != ~0)
8638 key = kvm_async_pf_next_probe(key);
8639
8640 vcpu->arch.apf.gfns[key] = gfn;
8641}
8642
8643static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8644{
8645 int i;
8646 u32 key = kvm_async_pf_hash_fn(gfn);
8647
8648 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8649 (vcpu->arch.apf.gfns[key] != gfn &&
8650 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8651 key = kvm_async_pf_next_probe(key);
8652
8653 return key;
8654}
8655
8656bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8657{
8658 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8659}
8660
8661static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8662{
8663 u32 i, j, k;
8664
8665 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8666 while (true) {
8667 vcpu->arch.apf.gfns[i] = ~0;
8668 do {
8669 j = kvm_async_pf_next_probe(j);
8670 if (vcpu->arch.apf.gfns[j] == ~0)
8671 return;
8672 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8673 /*
8674 * k lies cyclically in ]i,j]
8675 * | i.k.j |
8676 * |....j i.k.| or |.k..j i...|
8677 */
8678 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8679 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8680 i = j;
8681 }
8682}
8683
7c90705b
GN		 8684static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8685{
4e335d9e
PB		 8686
8687 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8688 sizeof(val));
7c90705b
GN		 8689}
8690
9a6e7c39
WL		 8691static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8692{
8693
8694 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8695 sizeof(u32));
8696}
8697
af585b92
GN		 8698void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8699 struct kvm_async_pf *work)
8700{
6389ee94
AK		 8701 struct x86_exception fault;
8702
7c90705b 8703 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8704 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8705
8706 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8707 (vcpu->arch.apf.send_user_only &&
8708 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8709 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8710 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8711 fault.vector = PF_VECTOR;
8712 fault.error_code_valid = true;
8713 fault.error_code = 0;
8714 fault.nested_page_fault = false;
8715 fault.address = work->arch.token;
adfe20fb 8716 fault.async_page_fault = true;
6389ee94 8717 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8718 }
af585b92
GN		 8719}
8720
8721void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8722 struct kvm_async_pf *work)
8723{
6389ee94 8724 struct x86_exception fault;
9a6e7c39 8725 u32 val;
6389ee94 8726
f2e10669 8727 if (work->wakeup_all)
7c90705b
GN		 8728 work->arch.token = ~0; /* broadcast wakeup */
8729 else
8730 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8731 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8732
9a6e7c39
WL		 8733 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8734 !apf_get_user(vcpu, &val)) {
8735 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8736 vcpu->arch.exception.pending &&
8737 vcpu->arch.exception.nr == PF_VECTOR &&
8738 !apf_put_user(vcpu, 0)) {
8739 vcpu->arch.exception.injected = false;
8740 vcpu->arch.exception.pending = false;
8741 vcpu->arch.exception.nr = 0;
8742 vcpu->arch.exception.has_error_code = false;
8743 vcpu->arch.exception.error_code = 0;
8744 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8745 fault.vector = PF_VECTOR;
8746 fault.error_code_valid = true;
8747 fault.error_code = 0;
8748 fault.nested_page_fault = false;
8749 fault.address = work->arch.token;
8750 fault.async_page_fault = true;
8751 kvm_inject_page_fault(vcpu, &fault);
8752 }
7c90705b 8753 }
e6d53e3b 8754 vcpu->arch.apf.halted = false;
a4fa1635 8755 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8756}
8757
8758bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8759{
8760 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8761 return true;
8762 else
9bc1f09f 8763 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8764}
8765
5544eb9b
PB		 8766void kvm_arch_start_assignment(struct kvm *kvm)
8767{
8768 atomic_inc(&kvm->arch.assigned_device_count);
8769}
8770EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8771
8772void kvm_arch_end_assignment(struct kvm *kvm)
8773{
8774 atomic_dec(&kvm->arch.assigned_device_count);
8775}
8776EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8777
8778bool kvm_arch_has_assigned_device(struct kvm *kvm)
8779{
8780 return atomic_read(&kvm->arch.assigned_device_count);
8781}
8782EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8783
e0f0bbc5
AW		 8784void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8785{
8786 atomic_inc(&kvm->arch.noncoherent_dma_count);
8787}
8788EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8789
8790void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8791{
8792 atomic_dec(&kvm->arch.noncoherent_dma_count);
8793}
8794EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8795
8796bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8797{
8798 return atomic_read(&kvm->arch.noncoherent_dma_count);
8799}
8800EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8801
14717e20
AW		 8802bool kvm_arch_has_irq_bypass(void)
8803{
8804 return kvm_x86_ops->update_pi_irte != NULL;
8805}
8806
87276880
FW		 8807int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8808 struct irq_bypass_producer *prod)
8809{
8810 struct kvm_kernel_irqfd *irqfd =
8811 container_of(cons, struct kvm_kernel_irqfd, consumer);
8812
14717e20 8813 irqfd->producer = prod;
87276880 8814
14717e20
AW		 8815 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8816 prod->irq, irqfd->gsi, 1);
87276880
FW		 8817}
8818
8819void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8820 struct irq_bypass_producer *prod)
8821{
8822 int ret;
8823 struct kvm_kernel_irqfd *irqfd =
8824 container_of(cons, struct kvm_kernel_irqfd, consumer);
8825
87276880
FW		 8826 WARN_ON(irqfd->producer != prod);
8827 irqfd->producer = NULL;
8828
8829 /*
8830 * When producer of consumer is unregistered, we change back to
8831 * remapped mode, so we can re-use the current implementation
bb3541f1 8832 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8833 * int this case doesn't want to receive the interrupts.
8834 */
8835 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8836 if (ret)
8837 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8838 " fails: %d\n", irqfd->consumer.token, ret);
8839}
8840
8841int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8842 uint32_t guest_irq, bool set)
8843{
8844 if (!kvm_x86_ops->update_pi_irte)
8845 return -EINVAL;
8846
8847 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8848}
8849
52004014
FW		 8850bool kvm_vector_hashing_enabled(void)
8851{
8852 return vector_hashing;
8853}
8854EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8855
229456fc 8856EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8857EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8858EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8859EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8860EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8861EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8862EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8863EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8864EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8865EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8866EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8867EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8868EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8869EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8870EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8871EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8872EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8873EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8874EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git