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4b27d27c
L		 12020-04-02 Lili Cui <lili.cui@intel.com>
2
3 * i386-dis.c (prefix_table): New instructions serialize.
4 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
5 CPU_ANY_SERIALIZE_FLAGS.
6 (cpu_flags): Add CpuSERIALIZE.
7 * i386-opc.h (enum): Add CpuSERIALIZE.
8 (i386_cpu_flags): Add cpuserialize.
9 * i386-opc.tbl: Add SERIALIZE insns.
10 * i386-init.h: Regenerate.
11 * i386-tbl.h: Likewise.
12
832a5807
AM		 132020-03-26 Alan Modra <amodra@gmail.com>
14
15 * disassemble.h (opcodes_assert): Declare.
16 (OPCODES_ASSERT): Define.
17 * disassemble.c: Don't include assert.h. Include opintl.h.
18 (opcodes_assert): New function.
19 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
20 (bfd_h8_disassemble): Reduce size of data array. Correctly
21 calculate maxlen. Omit insn decoding when insn length exceeds
22 maxlen. Exit from nibble loop when looking for E, before
23 accessing next data byte. Move processing of E outside loop.
24 Replace tests of maxlen in loop with assertions.
25
4c4addbe
AM		 262020-03-26 Alan Modra <amodra@gmail.com>
27
28 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
29
a18cd0ca
AM		 302020-03-25 Alan Modra <amodra@gmail.com>
31
32 * z80-dis.c (suffix): Init mybuf.
33
57cb32b3
AM		 342020-03-22 Alan Modra <amodra@gmail.com>
35
36 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
37 successflly read from section.
38
beea5cc1
AM		 392020-03-22 Alan Modra <amodra@gmail.com>
40
41 * arc-dis.c (find_format): Use ISO C string concatenation rather
42 than line continuation within a string. Don't access needs_limm
43 before testing opcode != NULL.
44
03704c77
AM		 452020-03-22 Alan Modra <amodra@gmail.com>
46
47 * ns32k-dis.c (print_insn_arg): Update comment.
48 (print_insn_ns32k): Reduce size of index_offset array, and
49 initialize, passing -1 to print_insn_arg for args that are not
50 an index. Don't exit arg loop early. Abort on bad arg number.
51
d1023b5d
AM		 522020-03-22 Alan Modra <amodra@gmail.com>
53
54 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
55 * s12z-opc.c: Formatting.
56 (operands_f): Return an int.
57 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
58 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
59 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
60 (exg_sex_discrim): Likewise.
61 (create_immediate_operand, create_bitfield_operand),
62 (create_register_operand_with_size, create_register_all_operand),
63 (create_register_all16_operand, create_simple_memory_operand),
64 (create_memory_operand, create_memory_auto_operand): Don't
65 segfault on malloc failure.
66 (z_ext24_decode): Return an int status, negative on fail, zero
67 on success.
68 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
69 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
70 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
71 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
72 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
73 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
74 (loop_primitive_decode, shift_decode, psh_pul_decode),
75 (bit_field_decode): Similarly.
76 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
77 to return value, update callers.
78 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
79 Don't segfault on NULL operand.
80 (decode_operation): Return OP_INVALID on first fail.
81 (decode_s12z): Check all reads, returning -1 on fail.
82
340f3ac8
AM		 832020-03-20 Alan Modra <amodra@gmail.com>
84
85 * metag-dis.c (print_insn_metag): Don't ignore status from
86 read_memory_func.
87
fe90ae8a
AM		 882020-03-20 Alan Modra <amodra@gmail.com>
89
90 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
91 Initialize parts of buffer not written when handling a possible
92 2-byte insn at end of section. Don't attempt decoding of such
93 an insn by the 4-byte machinery.
94
833d919c
AM		 952020-03-20 Alan Modra <amodra@gmail.com>
96
97 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
98 partially filled buffer. Prevent lookup of 4-byte insns when
99 only VLE 2-byte insns are possible due to section size. Print
100 ".word" rather than ".long" for 2-byte leftovers.
101
327ef784
NC		 1022020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
103
104 PR 25641
105 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
106
1673df32
JB		 1072020-03-13 Jan Beulich <jbeulich@suse.com>
108
109 * i386-dis.c (X86_64_0D): Rename to ...
110 (X86_64_0E): ... this.
111
384f3689
L		 1122020-03-09 H.J. Lu <hongjiu.lu@intel.com>
113
114 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
115 * Makefile.in: Regenerated.
116
865e2027
JB		 1172020-03-09 Jan Beulich <jbeulich@suse.com>
118
119 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
120 3-operand pseudos.
121 * i386-tbl.h: Re-generate.
122
2f13234b
JB		 1232020-03-09 Jan Beulich <jbeulich@suse.com>
124
125 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
126 vprot*, vpsha*, and vpshl*.
127 * i386-tbl.h: Re-generate.
128
3fabc179
JB		 1292020-03-09 Jan Beulich <jbeulich@suse.com>
130
131 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
132 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
133 * i386-tbl.h: Re-generate.
134
3677e4c1
JB		 1352020-03-09 Jan Beulich <jbeulich@suse.com>
136
137 * i386-gen.c (set_bitfield): Ignore zero-length field names.
138 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
139 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
140 * i386-tbl.h: Re-generate.
141
4c4898e8
JB		 1422020-03-09 Jan Beulich <jbeulich@suse.com>
143
144 * i386-gen.c (struct template_arg, struct template_instance,
145 struct template_param, struct template, templates,
146 parse_template, expand_templates): New.
147 (process_i386_opcodes): Various local variables moved to
148 expand_templates. Call parse_template and expand_templates.
149 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
150 * i386-tbl.h: Re-generate.
151
bc49bfd8
JB		 1522020-03-06 Jan Beulich <jbeulich@suse.com>
153
154 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
155 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
156 register and memory source templates. Replace VexW= by VexW*
157 where applicable.
158 * i386-tbl.h: Re-generate.
159
4873e243
JB		 1602020-03-06 Jan Beulich <jbeulich@suse.com>
161
162 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
163 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
164 * i386-tbl.h: Re-generate.
165
672a349b
JB		 1662020-03-06 Jan Beulich <jbeulich@suse.com>
167
168 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
169 * i386-tbl.h: Re-generate.
170
4ed21b58
JB		 1712020-03-06 Jan Beulich <jbeulich@suse.com>
172
173 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
174 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
175 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
176 VexW0 on SSE2AVX variants.
177 (vmovq): Drop NoRex64 from XMM/XMM variants.
178 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
179 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
180 applicable use VexW0.
181 * i386-tbl.h: Re-generate.
182
643bb870
JB		 1832020-03-06 Jan Beulich <jbeulich@suse.com>
184
185 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
186 * i386-opc.h (Rex64): Delete.
187 (struct i386_opcode_modifier): Remove rex64 field.
188 * i386-opc.tbl (crc32): Drop Rex64.
189 Replace Rex64 with Size64 everywhere else.
190 * i386-tbl.h: Re-generate.
191
a23b33b3
JB		 1922020-03-06 Jan Beulich <jbeulich@suse.com>
193
194 * i386-dis.c (OP_E_memory): Exclude recording of used address
195 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
196 addressed memory operands for MPX insns.
197
a0497384
JB		 1982020-03-06 Jan Beulich <jbeulich@suse.com>
199
200 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
201 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
202 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
203 (ptwrite): Split into non-64-bit and 64-bit forms.
204 * i386-tbl.h: Re-generate.
205
b630c145
JB		 2062020-03-06 Jan Beulich <jbeulich@suse.com>
207
208 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
209 template.
210 * i386-tbl.h: Re-generate.
211
a847e322
JB		 2122020-03-04 Jan Beulich <jbeulich@suse.com>
213
214 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
215 (prefix_table): Move vmmcall here. Add vmgexit.
216 (rm_table): Replace vmmcall entry by prefix_table[] escape.
217 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
218 (cpu_flags): Add CpuSEV_ES entry.
219 * i386-opc.h (CpuSEV_ES): New.
220 (union i386_cpu_flags): Add cpusev_es field.
221 * i386-opc.tbl (vmgexit): New.
222 * i386-init.h, i386-tbl.h: Re-generate.
223
3cd7f3e3
L		 2242020-03-03 H.J. Lu <hongjiu.lu@intel.com>
225
226 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
227 with MnemonicSize.
228 * i386-opc.h (IGNORESIZE): New.
229 (DEFAULTSIZE): Likewise.
230 (IgnoreSize): Removed.
231 (DefaultSize): Likewise.
232 (MnemonicSize): New.
233 (i386_opcode_modifier): Replace ignoresize/defaultsize with
234 mnemonicsize.
235 * i386-opc.tbl (IgnoreSize): New.
236 (DefaultSize): Likewise.
237 * i386-tbl.h: Regenerated.
238
b8ba1385
SB		 2392020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
240
241 PR 25627
242 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
243 instructions.
244
10d97a0f
L		 2452020-03-03 H.J. Lu <hongjiu.lu@intel.com>
246
247 PR gas/25622
248 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
249 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
250 * i386-tbl.h: Regenerated.
251
dc1e8a47
AM		 2522020-02-26 Alan Modra <amodra@gmail.com>
253
254 * aarch64-asm.c: Indent labels correctly.
255 * aarch64-dis.c: Likewise.
256 * aarch64-gen.c: Likewise.
257 * aarch64-opc.c: Likewise.
258 * alpha-dis.c: Likewise.
259 * i386-dis.c: Likewise.
260 * nds32-asm.c: Likewise.
261 * nfp-dis.c: Likewise.
262 * visium-dis.c: Likewise.
263
265b4673
CZ		 2642020-02-25 Claudiu Zissulescu <claziss@gmail.com>
265
266 * arc-regs.h (int_vector_base): Make it available for all ARC
267 CPUs.
268
bd0cf5a6
NC		 2692020-02-20 Nelson Chu <nelson.chu@sifive.com>
270
271 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
272 changed.
273
fa164239
JW		 2742020-02-19 Nelson Chu <nelson.chu@sifive.com>
275
276 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
277 c.mv/c.li if rs1 is zero.
278
272a84b1
L		 2792020-02-17 H.J. Lu <hongjiu.lu@intel.com>
280
281 * i386-gen.c (cpu_flag_init): Replace CpuABM with
282 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
283 CPU_POPCNT_FLAGS.
284 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
285 * i386-opc.h (CpuABM): Removed.
286 (CpuPOPCNT): New.
287 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
288 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
289 popcnt. Remove CpuABM from lzcnt.
290 * i386-init.h: Regenerated.
291 * i386-tbl.h: Likewise.
292
1f730c46
JB		 2932020-02-17 Jan Beulich <jbeulich@suse.com>
294
295 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
296 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
297 VexW1 instead of open-coding them.
298 * i386-tbl.h: Re-generate.
299
c8f8eebc
JB		 3002020-02-17 Jan Beulich <jbeulich@suse.com>
301
302 * i386-opc.tbl (AddrPrefixOpReg): Define.
303 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
304 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
305 templates. Drop NoRex64.
306 * i386-tbl.h: Re-generate.
307
b9915cbc
JB		 3082020-02-17 Jan Beulich <jbeulich@suse.com>
309
310 PR gas/6518
311 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
312 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
313 into Intel syntax instance (with Unpsecified) and AT&T one
314 (without).
315 (vcvtneps2bf16): Likewise, along with folding the two so far
316 separate ones.
317 * i386-tbl.h: Re-generate.
318
ce504911
L		 3192020-02-16 H.J. Lu <hongjiu.lu@intel.com>
320
321 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
322 CPU_ANY_SSE4A_FLAGS.
323
dabec65d
AM		 3242020-02-17 Alan Modra <amodra@gmail.com>
325
326 * i386-gen.c (cpu_flag_init): Correct last change.
327
af5c13b0
L		 3282020-02-16 H.J. Lu <hongjiu.lu@intel.com>
329
330 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
331 CPU_ANY_SSE4_FLAGS.
332
6867aac0
L		 3332020-02-14 H.J. Lu <hongjiu.lu@intel.com>
334
335 * i386-opc.tbl (movsx): Remove Intel syntax comments.
336 (movzx): Likewise.
337
65fca059
JB		 3382020-02-14 Jan Beulich <jbeulich@suse.com>
339
340 PR gas/25438
341 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
342 destination for Cpu64-only variant.
343 (movzx): Fold patterns.
344 * i386-tbl.h: Re-generate.
345
7deea9aa
JB		 3462020-02-13 Jan Beulich <jbeulich@suse.com>
347
348 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
349 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
350 CPU_ANY_SSE4_FLAGS entry.
351 * i386-init.h: Re-generate.
352
6c0946d0
JB		 3532020-02-12 Jan Beulich <jbeulich@suse.com>
354
355 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
356 with Unspecified, making the present one AT&T syntax only.
357 * i386-tbl.h: Re-generate.
358
ddb56fe6
JB		 3592020-02-12 Jan Beulich <jbeulich@suse.com>
360
361 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
362 * i386-tbl.h: Re-generate.
363
5990e377
JB		 3642020-02-12 Jan Beulich <jbeulich@suse.com>
365
366 PR gas/24546
367 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
368 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
369 Amd64 and Intel64 templates.
370 (call, jmp): Likewise for far indirect variants. Dro
371 Unspecified.
372 * i386-tbl.h: Re-generate.
373
50128d0c
JB		 3742020-02-11 Jan Beulich <jbeulich@suse.com>
375
376 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
377 * i386-opc.h (ShortForm): Delete.
378 (struct i386_opcode_modifier): Remove shortform field.
379 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
380 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
381 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
382 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
383 Drop ShortForm.
384 * i386-tbl.h: Re-generate.
385
1e05b5c4
JB		 3862020-02-11 Jan Beulich <jbeulich@suse.com>
387
388 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
389 fucompi): Drop ShortForm from operand-less templates.
390 * i386-tbl.h: Re-generate.
391
2f5dd314
AM		 3922020-02-11 Alan Modra <amodra@gmail.com>
393
394 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
395 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
396 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
397 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
398 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
399
5aae9ae9
MM		 4002020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
401
402 * arm-dis.c (print_insn_cde): Define 'V' parse character.
403 (cde_opcodes): Add VCX* instructions.
404
4934a27c
MM		 4052020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
406 Matthew Malcomson <matthew.malcomson@arm.com>
407
408 * arm-dis.c (struct cdeopcode32): New.
409 (CDE_OPCODE): New macro.
410 (cde_opcodes): New disassembly table.
411 (regnames): New option to table.
412 (cde_coprocs): New global variable.
413 (print_insn_cde): New
414 (print_insn_thumb32): Use print_insn_cde.
415 (parse_arm_disassembler_options): Parse coprocN args.
416
4b5aaf5f
L		 4172020-02-10 H.J. Lu <hongjiu.lu@intel.com>
418
419 PR gas/25516
420 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
421 with ISA64.
422 * i386-opc.h (AMD64): Removed.
423 (Intel64): Likewose.
424 (AMD64): New.
425 (INTEL64): Likewise.
426 (INTEL64ONLY): Likewise.
427 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
428 * i386-opc.tbl (Amd64): New.
429 (Intel64): Likewise.
430 (Intel64Only): Likewise.
431 Replace AMD64 with Amd64. Update sysenter/sysenter with
432 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
433 * i386-tbl.h: Regenerated.
434
9fc0b501
SB		 4352020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
436
437 PR 25469
438 * z80-dis.c: Add support for GBZ80 opcodes.
439
c5d7be0c
AM		 4402020-02-04 Alan Modra <amodra@gmail.com>
441
442 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
443
44e4546f
AM		 4442020-02-03 Alan Modra <amodra@gmail.com>
445
446 * m32c-ibld.c: Regenerate.
447
b2b1453a
AM		 4482020-02-01 Alan Modra <amodra@gmail.com>
449
450 * frv-ibld.c: Regenerate.
451
4102be5c
JB		 4522020-01-31 Jan Beulich <jbeulich@suse.com>
453
454 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
455 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
456 (OP_E_memory): Replace xmm_mdq_mode case label by
457 vex_scalar_w_dq_mode one.
458 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
459
825bd36c
JB		 4602020-01-31 Jan Beulich <jbeulich@suse.com>
461
462 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
463 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
464 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
465 (intel_operand_size): Drop vex_w_dq_mode case label.
466
c3036ed0
RS		 4672020-01-31 Richard Sandiford <richard.sandiford@arm.com>
468
469 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
470 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
471
0c115f84
AM		 4722020-01-30 Alan Modra <amodra@gmail.com>
473
474 * m32c-ibld.c: Regenerate.
475
bd434cc4
JM		 4762020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
477
478 * bpf-opc.c: Regenerate.
479
aeab2b26
JB		 4802020-01-30 Jan Beulich <jbeulich@suse.com>
481
482 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
483 (dis386): Use them to replace C2/C3 table entries.
484 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
485 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
486 ones. Use Size64 instead of DefaultSize on Intel64 ones.
487 * i386-tbl.h: Re-generate.
488
62b3f548
JB		 4892020-01-30 Jan Beulich <jbeulich@suse.com>
490
491 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
492 forms.
493 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
494 DefaultSize.
495 * i386-tbl.h: Re-generate.
496
1bd8ae10
AM		 4972020-01-30 Alan Modra <amodra@gmail.com>
498
499 * tic4x-dis.c (tic4x_dp): Make unsigned.
500
bc31405e
L		 5012020-01-27 H.J. Lu <hongjiu.lu@intel.com>
502 Jan Beulich <jbeulich@suse.com>
503
504 PR binutils/25445
505 * i386-dis.c (MOVSXD_Fixup): New function.
506 (movsxd_mode): New enum.
507 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
508 (intel_operand_size): Handle movsxd_mode.
509 (OP_E_register): Likewise.
510 (OP_G): Likewise.
511 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
512 register on movsxd. Add movsxd with 16-bit destination register
513 for AMD64 and Intel64 ISAs.
514 * i386-tbl.h: Regenerated.
515
7568c93b
TC		 5162020-01-27 Tamar Christina <tamar.christina@arm.com>
517
518 PR 25403
519 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
520 * aarch64-asm-2.c: Regenerate
521 * aarch64-dis-2.c: Likewise.
522 * aarch64-opc-2.c: Likewise.
523
c006a730
JB		 5242020-01-21 Jan Beulich <jbeulich@suse.com>
525
526 * i386-opc.tbl (sysret): Drop DefaultSize.
527 * i386-tbl.h: Re-generate.
528
c906a69a
JB		 5292020-01-21 Jan Beulich <jbeulich@suse.com>
530
531 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
532 Dword.
533 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
534 * i386-tbl.h: Re-generate.
535
26916852
NC		 5362020-01-20 Nick Clifton <nickc@redhat.com>
537
538 * po/de.po: Updated German translation.
539 * po/pt_BR.po: Updated Brazilian Portuguese translation.
540 * po/uk.po: Updated Ukranian translation.
541
4d6cbb64
AM		 5422020-01-20 Alan Modra <amodra@gmail.com>
543
544 * hppa-dis.c (fput_const): Remove useless cast.
545
2bddb71a
AM		 5462020-01-20 Alan Modra <amodra@gmail.com>
547
548 * arm-dis.c (print_insn_arm): Wrap 'T' value.
549
1b1bb2c6
NC		 5502020-01-18 Nick Clifton <nickc@redhat.com>
551
552 * configure: Regenerate.
553 * po/opcodes.pot: Regenerate.
554
ae774686
NC		 5552020-01-18 Nick Clifton <nickc@redhat.com>
556
557 Binutils 2.34 branch created.
558
07f1f3aa
CB		 5592020-01-17 Christian Biesinger <cbiesinger@google.com>
560
561 * opintl.h: Fix spelling error (seperate).
562
42e04b36
L		 5632020-01-17 H.J. Lu <hongjiu.lu@intel.com>
564
565 * i386-opc.tbl: Add {vex} pseudo prefix.
566 * i386-tbl.h: Regenerated.
567
2da2eaf4
AV		 5682020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
569
570 PR 25376
571 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
572 (neon_opcodes): Likewise.
573 (select_arm_features): Make sure we enable MVE bits when selecting
574 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
575 any architecture.
576
d0849eed
JB		 5772020-01-16 Jan Beulich <jbeulich@suse.com>
578
579 * i386-opc.tbl: Drop stale comment from XOP section.
580
9cf70a44
JB		 5812020-01-16 Jan Beulich <jbeulich@suse.com>
582
583 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
584 (extractps): Add VexWIG to SSE2AVX forms.
585 * i386-tbl.h: Re-generate.
586
4814632e
JB		 5872020-01-16 Jan Beulich <jbeulich@suse.com>
588
589 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
590 Size64 from and use VexW1 on SSE2AVX forms.
591 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
592 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
593 * i386-tbl.h: Re-generate.
594
aad09917
AM		 5952020-01-15 Alan Modra <amodra@gmail.com>
596
597 * tic4x-dis.c (tic4x_version): Make unsigned long.
598 (optab, optab_special, registernames): New file scope vars.
599 (tic4x_print_register): Set up registernames rather than
600 malloc'd registertable.
601 (tic4x_disassemble): Delete optable and optable_special. Use
602 optab and optab_special instead. Throw away old optab,
603 optab_special and registernames when info->mach changes.
604
7a6bf3be
SB		 6052020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
606
607 PR 25377
608 * z80-dis.c (suffix): Use .db instruction to generate double
609 prefix.
610
ca1eaac0
AM		 6112020-01-14 Alan Modra <amodra@gmail.com>
612
613 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
614 values to unsigned before shifting.
615
1d67fe3b
TT		 6162020-01-13 Thomas Troeger <tstroege@gmx.de>
617
618 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
619 flow instructions.
620 (print_insn_thumb16, print_insn_thumb32): Likewise.
621 (print_insn): Initialize the insn info.
622 * i386-dis.c (print_insn): Initialize the insn info fields, and
623 detect jumps.
624
5e4f7e05
CZ		 6252012-01-13 Claudiu Zissulescu <claziss@gmail.com>
626
627 * arc-opc.c (C_NE): Make it required.
628
b9fe6b8a
CZ		 6292012-01-13 Claudiu Zissulescu <claziss@gmail.com>
630
631 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
632 reserved register name.
633
90dee485
AM		 6342020-01-13 Alan Modra <amodra@gmail.com>
635
636 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
637 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
638
febda64f
AM		 6392020-01-13 Alan Modra <amodra@gmail.com>
640
641 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
642 result of wasm_read_leb128 in a uint64_t and check that bits
643 are not lost when copying to other locals. Use uint32_t for
644 most locals. Use PRId64 when printing int64_t.
645
df08b588
AM		 6462020-01-13 Alan Modra <amodra@gmail.com>
647
648 * score-dis.c: Formatting.
649 * score7-dis.c: Formatting.
650
b2c759ce
AM		 6512020-01-13 Alan Modra <amodra@gmail.com>
652
653 * score-dis.c (print_insn_score48): Use unsigned variables for
654 unsigned values. Don't left shift negative values.
655 (print_insn_score32): Likewise.
656 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
657
5496abe1
AM		 6582020-01-13 Alan Modra <amodra@gmail.com>
659
660 * tic4x-dis.c (tic4x_print_register): Remove dead code.
661
202e762b
AM		 6622020-01-13 Alan Modra <amodra@gmail.com>
663
664 * fr30-ibld.c: Regenerate.
665
7ef412cf
AM		 6662020-01-13 Alan Modra <amodra@gmail.com>
667
668 * xgate-dis.c (print_insn): Don't left shift signed value.
669 (ripBits): Formatting, use 1u.
670
7f578b95
AM		 6712020-01-10 Alan Modra <amodra@gmail.com>
672
673 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
674 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
675
441af85b
AM		 6762020-01-10 Alan Modra <amodra@gmail.com>
677
678 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
679 and XRREG value earlier to avoid a shift with negative exponent.
680 * m10200-dis.c (disassemble): Similarly.
681
bce58db4
NC		 6822020-01-09 Nick Clifton <nickc@redhat.com>
683
684 PR 25224
685 * z80-dis.c (ld_ii_ii): Use correct cast.
686
40c75bc8
SB		 6872020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
688
689 PR 25224
690 * z80-dis.c (ld_ii_ii): Use character constant when checking
691 opcode byte value.
692
d835a58b
JB		 6932020-01-09 Jan Beulich <jbeulich@suse.com>
694
695 * i386-dis.c (SEP_Fixup): New.
696 (SEP): Define.
697 (dis386_twobyte): Use it for sysenter/sysexit.
698 (enum x86_64_isa): Change amd64 enumerator to value 1.
699 (OP_J): Compare isa64 against intel64 instead of amd64.
700 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
701 forms.
702 * i386-tbl.h: Re-generate.
703
030a2e78
AM		 7042020-01-08 Alan Modra <amodra@gmail.com>
705
706 * z8k-dis.c: Include libiberty.h
707 (instr_data_s): Make max_fetched unsigned.
708 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
709 Don't exceed byte_info bounds.
710 (output_instr): Make num_bytes unsigned.
711 (unpack_instr): Likewise for nibl_count and loop.
712 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
713 idx unsigned.
714 * z8k-opc.h: Regenerate.
715
bb82aefe
SV		 7162020-01-07 Shahab Vahedi <shahab@synopsys.com>
717
718 * arc-tbl.h (llock): Use 'LLOCK' as class.
719 (llockd): Likewise.
720 (scond): Use 'SCOND' as class.
721 (scondd): Likewise.
722 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
723 (scondd): Likewise.
724
cc6aa1a6
AM		 7252020-01-06 Alan Modra <amodra@gmail.com>
726
727 * m32c-ibld.c: Regenerate.
728
660e62b1
AM		 7292020-01-06 Alan Modra <amodra@gmail.com>
730
731 PR 25344
732 * z80-dis.c (suffix): Don't use a local struct buffer copy.
733 Peek at next byte to prevent recursion on repeated prefix bytes.
734 Ensure uninitialised "mybuf" is not accessed.
735 (print_insn_z80): Don't zero n_fetch and n_used here,..
736 (print_insn_z80_buf): ..do it here instead.
737
c9ae58fe
AM		 7382020-01-04 Alan Modra <amodra@gmail.com>
739
740 * m32r-ibld.c: Regenerate.
741
5f57d4ec
AM		 7422020-01-04 Alan Modra <amodra@gmail.com>
743
744 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
745
2c5c1196
AM		 7462020-01-04 Alan Modra <amodra@gmail.com>
747
748 * crx-dis.c (match_opcode): Avoid shift left of signed value.
749
2e98c6c5
AM		 7502020-01-04 Alan Modra <amodra@gmail.com>
751
752 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
753
567dfba2
JB		 7542020-01-03 Jan Beulich <jbeulich@suse.com>
755
5437a02a
JB		 756 * aarch64-tbl.h (aarch64_opcode_table): Use
757 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
758
7592020-01-03 Jan Beulich <jbeulich@suse.com>
760
761 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 762 forms of SUDOT and USDOT.
763
8c45011a
JB		 7642020-01-03 Jan Beulich <jbeulich@suse.com>
765
5437a02a 766 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 767 uzip{1,2}.
768 * opcodes/aarch64-dis-2.c: Re-generate.
769
f4950f76
JB		 7702020-01-03 Jan Beulich <jbeulich@suse.com>
771
5437a02a 772 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 773 FMMLA encoding.
774 * opcodes/aarch64-dis-2.c: Re-generate.
775
6655dba2
SB		 7762020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
777
778 * z80-dis.c: Add support for eZ80 and Z80 instructions.
779
b14ce8bf
AM		 7802020-01-01 Alan Modra <amodra@gmail.com>
781
782 Update year range in copyright notice of all files.
783
0b114740 784For older changes see ChangeLog-2019
3499769a 785\f
0b114740 786Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 787
788Copying and distribution of this file, with or without modification,
789are permitted in any medium without royalty provided the copyright
790notice and this notice are preserved.
791
792Local Variables:
793mode: change-log
794left-margin: 8
795fill-column: 74
796version-control: never
797End:
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