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2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
07892c0b
CD		 12002-03-19 Chris G. Demetriou <cgd@broadcom.com>
2
3 * cp1.c (fpu_format_name): New function to replace...
4 (DOFMT): This. Delete, and update all callers.
5 (fpu_rounding_mode_name): New function to replace...
6 (RMMODE): This. Delete, and update all callers.
7
487f79b7
CD		 82002-03-19 Chris G. Demetriou <cgd@broadcom.com>
9
10 * interp.c: Move FPU support routines from here to...
11 * cp1.c: Here. New file.
12 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
13 (cp1.o): New target.
14
1e799e28
CD		 152002-03-12 Chris Demetriou <cgd@broadcom.com>
16
17 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
18 * mips.igen (mips32, mips64): New models, add to all instructions
19 and functions as appropriate.
20 (loadstore_ea, check_u64): New variant for model mips64.
21 (check_fmt_p): New variant for models mipsV and mips64, remove
22 mipsV model marking fro other variant.
23 (SLL) Rename to...
24 (SLLa) this.
25 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
26 for mips32 and mips64.
27 (DCLO, DCLZ): New instructions for mips64.
28
82f728db
CD		 292002-03-07 Chris Demetriou <cgd@broadcom.com>
30
31 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
32 immediate or code as a hex value with the "%#lx" format.
33 (ANDI): Likewise, and fix printed instruction name.
34
b96e7ef1
CD		 352002-03-05 Chris Demetriou <cgd@broadcom.com>
36
37 * sim-main.h (UndefinedResult, Unpredictable): New macros
38 which currently do nothing.
39
d35d4f70
CD		 402002-03-05 Chris Demetriou <cgd@broadcom.com>
41
42 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
43 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
44 (status_CU3): New definitions.
45
46 * sim-main.h (ExceptionCause): Add new values for MIPS32
47 and MIPS64: MDMX, MCheck, CacheErr. Update comments
48 for DebugBreakPoint and NMIReset to note their status in
49 MIPS32 and MIPS64.
50 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
51 (SignalExceptionCacheErr): New exception macros.
52
3ad6f714
CD		 532002-03-05 Chris Demetriou <cgd@broadcom.com>
54
55 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
56 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
57 is always enabled.
58 (SignalExceptionCoProcessorUnusable): Take as argument the
59 unusable coprocessor number.
60
86b77b47
CD		 612002-03-05 Chris Demetriou <cgd@broadcom.com>
62
63 * mips.igen: Fix formatting of all SignalException calls.
64
97a88e93 652002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 66
67 * sim-main.h (SIGNEXTEND): Remove.
68
97a88e93 692002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 70
71 * mips.igen: Remove gencode comment from top of file, fix
72 spelling in another comment.
73
97a88e93 742002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 75
76 * mips.igen (check_fmt, check_fmt_p): New functions to check
77 whether specific floating point formats are usable.
78 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
79 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
80 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
81 Use the new functions.
82 (do_c_cond_fmt): Remove format checks...
83 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
84
97a88e93 852002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 86
87 * mips.igen: Fix formatting of check_fpu calls.
88
41774c9d
CD		 892002-03-03 Chris Demetriou <cgd@broadcom.com>
90
91 * mips.igen (FLOOR.L.fmt): Store correct destination register.
92
4a0bd876
CD		 932002-03-03 Chris Demetriou <cgd@broadcom.com>
94
95 * mips.igen: Remove whitespace at end of lines.
96
09297648
CD		 972002-03-02 Chris Demetriou <cgd@broadcom.com>
98
99 * mips.igen (loadstore_ea): New function to do effective
100 address calculations.
101 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
102 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
103 CACHE): Use loadstore_ea to do effective address computations.
104
043b7057
CD		 1052002-03-02 Chris Demetriou <cgd@broadcom.com>
106
107 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
108 * mips.igen (LL, CxC1, MxC1): Likewise.
109
c1e8ada4
CD		 1102002-03-02 Chris Demetriou <cgd@broadcom.com>
111
112 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
113 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
114 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
115 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
116 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
117 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
118 Don't split opcode fields by hand, use the opcode field values
119 provided by igen.
120
3e1dca16
CD		 1212002-03-01 Chris Demetriou <cgd@broadcom.com>
122
123 * mips.igen (do_divu): Fix spacing.
124
125 * mips.igen (do_dsllv): Move to be right before DSLLV,
126 to match the rest of the do_<shift> functions.
127
fff8d27d
CD		 1282002-03-01 Chris Demetriou <cgd@broadcom.com>
129
130 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
131 DSRL32, do_dsrlv): Trace inputs and results.
132
0d3e762b
CD		 1332002-03-01 Chris Demetriou <cgd@broadcom.com>
134
135 * mips.igen (CACHE): Provide instruction-printing string.
136
137 * interp.c (signal_exception): Comment tokens after #endif.
138
eb5fcf93
CD		 1392002-02-28 Chris Demetriou <cgd@broadcom.com>
140
141 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
142 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
143 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
144 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
145 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
146 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
147 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
148 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
149
bb22bd7d
CD		 1502002-02-28 Chris Demetriou <cgd@broadcom.com>
151
152 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
153 instruction-printing string.
154 (LWU): Use '64' as the filter flag.
155
91a177cf
CD		 1562002-02-28 Chris Demetriou <cgd@broadcom.com>
157
158 * mips.igen (SDXC1): Fix instruction-printing string.
159
387f484a
CD		 1602002-02-28 Chris Demetriou <cgd@broadcom.com>
161
162 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
163 filter flags "32,f".
164
3d81f391
CD		 1652002-02-27 Chris Demetriou <cgd@broadcom.com>
166
167 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
168 as the filter flag.
169
af5107af
CD		 1702002-02-27 Chris Demetriou <cgd@broadcom.com>
171
172 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
173 add a comma) so that it more closely match the MIPS ISA
174 documentation opcode partitioning.
175 (PREF): Put useful names on opcode fields, and include
176 instruction-printing string.
177
ca971540
CD		 1782002-02-27 Chris Demetriou <cgd@broadcom.com>
179
180 * mips.igen (check_u64): New function which in the future will
181 check whether 64-bit instructions are usable and signal an
182 exception if not. Currently a no-op.
183 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
184 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
185 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
186 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
187
188 * mips.igen (check_fpu): New function which in the future will
189 check whether FPU instructions are usable and signal an exception
190 if not. Currently a no-op.
191 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
192 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
193 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
194 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
195 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
196 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
197 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
198 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
199
1c47a468
CD		 2002002-02-27 Chris Demetriou <cgd@broadcom.com>
201
202 * mips.igen (do_load_left, do_load_right): Move to be immediately
203 following do_load.
204 (do_store_left, do_store_right): Move to be immediately following
205 do_store.
206
603a98e7
CD		 2072002-02-27 Chris Demetriou <cgd@broadcom.com>
208
209 * mips.igen (mipsV): New model name. Also, add it to
210 all instructions and functions where it is appropriate.
211
c5d00cc7
CD		 2122002-02-18 Chris Demetriou <cgd@broadcom.com>
213
214 * mips.igen: For all functions and instructions, list model
215 names that support that instruction one per line.
216
074e9cb8
CD		 2172002-02-11 Chris Demetriou <cgd@broadcom.com>
218
219 * mips.igen: Add some additional comments about supported
220 models, and about which instructions go where.
221 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
222 order as is used in the rest of the file.
223
9805e229
CD		 2242002-02-11 Chris Demetriou <cgd@broadcom.com>
225
226 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
227 indicating that ALU32_END or ALU64_END are there to check
228 for overflow.
229 (DADD): Likewise, but also remove previous comment about
230 overflow checking.
231
f701dad2
CD		 2322002-02-10 Chris Demetriou <cgd@broadcom.com>
233
234 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
235 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
236 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
237 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
238 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
239 fields (i.e., add and move commas) so that they more closely
240 match the MIPS ISA documentation opcode partitioning.
241
2422002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 243
244 * mips.igen (ADDI): Print immediate value.
245 (BREAK): Print code.
246 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
247 (SLL): Print "nop" specially, and don't run the code
248 that does the shift for the "nop" case.
249
9e52972e
FF		 2502001-11-17 Fred Fish <fnf@redhat.com>
251
252 * sim-main.h (float_operation): Move enum declaration outside
253 of _sim_cpu struct declaration.
254
c0efbca4
JB		 2552001-04-12 Jim Blandy <jimb@redhat.com>
256
257 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
258 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
259 set of the FCSR.
260 * sim-main.h (COCIDX): Remove definition; this isn't supported by
261 PENDING_FILL, and you can get the intended effect gracefully by
262 calling PENDING_SCHED directly.
263
fb891446
BE		 2642001-02-23 Ben Elliston <bje@redhat.com>
265
266 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
267 already defined elsewhere.
268
8030f857
BE		 2692001-02-19 Ben Elliston <bje@redhat.com>
270
271 * sim-main.h (sim_monitor): Return an int.
272 * interp.c (sim_monitor): Add return values.
273 (signal_exception): Handle error conditions from sim_monitor.
274
56b48a7a
CD		 2752001-02-08 Ben Elliston <bje@redhat.com>
276
277 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
278 (store_memory): Likewise, pass cia to sim_core_write*.
279
d3ee60d9
FCE		 2802000-10-19 Frank Ch. Eigler <fche@redhat.com>
281
282 On advice from Chris G. Demetriou <cgd@sibyte.com>:
283 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
284
071da002
AC		 285Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
286
287 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
288 * Makefile.in: Don't delete *.igen when cleaning directory.
289
a28c02cd
AC		 290Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
291
292 * m16.igen (break): Call SignalException not sim_engine_halt.
293
80ee11fa
AC		 294Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
295
296 From Jason Eckhardt:
297 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
298
673388c0
AC		 299Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
300
301 * mips.igen (MxC1, DMxC1): Fix printf formatting.
302
4c0deff4
NC		 3032000-05-24 Michael Hayes <mhayes@cygnus.com>
304
305 * mips.igen (do_dmultx): Fix typo.
306
eb2d80b4
AC		 307Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
308
309 * configure: Regenerated to track ../common/aclocal.m4 changes.
310
dd37a34b
AC		 311Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
312
313 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
314
4c0deff4
NC		 3152000-04-12 Frank Ch. Eigler <fche@redhat.com>
316
317 * sim-main.h (GPR_CLEAR): Define macro.
318
e30db738
AC		 319Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
320
321 * interp.c (decode_coproc): Output long using %lx and not %s.
322
cb7450ea
FCE		 3232000-03-21 Frank Ch. Eigler <fche@redhat.com>
324
325 * interp.c (sim_open): Sort & extend dummy memory regions for
326 --board=jmr3904 for eCos.
327
a3027dd7
FCE		 3282000-03-02 Frank Ch. Eigler <fche@redhat.com>
329
330 * configure: Regenerated.
331
332Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
333
334 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
335 calls, conditional on the simulator being in verbose mode.
336
dfcd3bfb
JM		 337Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
338
339 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
340 cache don't get ReservedInstruction traps.
341
c2d11a7d
JM		 3421999-11-29 Mark Salter <msalter@cygnus.com>
343
344 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
345 to clear status bits in sdisr register. This is how the hardware works.
346
347 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
348 being used by cygmon.
349
4ce44c66
JM		 3501999-11-11 Andrew Haley <aph@cygnus.com>
351
352 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
353 instructions.
354
cff3e48b
JM		 355Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
356
357 * mips.igen (MULT): Correct previous mis-applied patch.
358
d4f3574e
SS		 359Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
360
361 * mips.igen (delayslot32): Handle sequence like
362 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
363 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
364 (MULT): Actually pass the third register...
365
3661999-09-03 Mark Salter <msalter@cygnus.com>
367
368 * interp.c (sim_open): Added more memory aliases for additional
369 hardware being touched by cygmon on jmr3904 board.
370
371Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
372
373 * configure: Regenerated to track ../common/aclocal.m4 changes.
374
a0b3c4fd
JM		 375Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
376
377 * interp.c (sim_store_register): Handle case where client - GDB -
378 specifies that a 4 byte register is 8 bytes in size.
379 (sim_fetch_register): Ditto.
380
adf40b2e
JM		 3811999-07-14 Frank Ch. Eigler <fche@cygnus.com>
382
383 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
384 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
385 (idt_monitor_base): Base address for IDT monitor traps.
386 (pmon_monitor_base): Ditto for PMON.
387 (lsipmon_monitor_base): Ditto for LSI PMON.
388 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
389 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
390 (sim_firmware_command): New function.
391 (mips_option_handler): Call it for OPTION_FIRMWARE.
392 (sim_open): Allocate memory for idt_monitor region. If "--board"
393 option was given, add no monitor by default. Add BREAK hooks only if
394 monitors are also there.
395
43e526b9
JM		 396Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
397
398 * interp.c (sim_monitor): Flush output before reading input.
399
400Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
401
402 * tconfig.in (SIM_HANDLES_LMA): Always define.
403
404Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
405
406 From Mark Salter <msalter@cygnus.com>:
407 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
408 (sim_open): Add setup for BSP board.
409
9846de1b
JM		 410Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
411
412 * mips.igen (MULT, MULTU): Add syntax for two operand version.
413 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
414 them as unimplemented.
415
cd0fc7c3
SS		 4161999-05-08 Felix Lee <flee@cygnus.com>
417
418 * configure: Regenerated to track ../common/aclocal.m4 changes.
419
7a292a7a
SS		 4201999-04-21 Frank Ch. Eigler <fche@cygnus.com>
421
422 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
423
424Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
425
426 * configure.in: Any mips64vr5*-*-* target should have
427 -DTARGET_ENABLE_FR=1.
428 (default_endian): Any mips64vr*el-*-* target should default to
429 LITTLE_ENDIAN.
430 * configure: Re-generate.
431
4321999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
433
434 * mips.igen (ldl): Extend from _16_, not 32.
435
436Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
437
438 * interp.c (sim_store_register): Force registers written to by GDB
439 into an un-interpreted state.
440
c906108c
SS		 4411999-02-05 Frank Ch. Eigler <fche@cygnus.com>
442
443 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
444 CPU, start periodic background I/O polls.
445 (tx3904sio_poll): New function: periodic I/O poller.
446
4471998-12-30 Frank Ch. Eigler <fche@cygnus.com>
448
449 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
450
451Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
452
453 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
454 case statement.
455
4561998-12-29 Frank Ch. Eigler <fche@cygnus.com>
457
458 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
459 (load_word): Call SIM_CORE_SIGNAL hook on error.
460 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
461 starting. For exception dispatching, pass PC instead of NULL_CIA.
462 (decode_coproc): Use COP0_BADVADDR to store faulting address.
463 * sim-main.h (COP0_BADVADDR): Define.
464 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
465 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
466 (_sim_cpu): Add exc_* fields to store register value snapshots.
467 * mips.igen (*): Replace memory-related SignalException* calls
468 with references to SIM_CORE_SIGNAL hook.
469
470 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
471 fix.
472 * sim-main.c (*): Minor warning cleanups.
473
4741998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
475
476 * m16.igen (DADDIU5): Correct type-o.
477
478Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
479
480 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
481 variables.
482
483Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
484
485 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
486 to include path.
487 (interp.o): Add dependency on itable.h
488 (oengine.c, gencode): Delete remaining references.
489 (BUILT_SRC_FROM_GEN): Clean up.
490
4911998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
492
493 * vr4run.c: New.
494 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
495 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
496 tmp-run-hack) : New.
497 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
498 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
499 Drop the "64" qualifier to get the HACK generator working.
500 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
501 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
502 qualifier to get the hack generator working.
503 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
504 (DSLL): Use do_dsll.
505 (DSLLV): Use do_dsllv.
506 (DSRA): Use do_dsra.
507 (DSRL): Use do_dsrl.
508 (DSRLV): Use do_dsrlv.
509 (BC1): Move *vr4100 to get the HACK generator working.
510 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
511 get the HACK generator working.
512 (MACC) Rename to get the HACK generator working.
513 (DMACC,MACCS,DMACCS): Add the 64.
514
5151998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
516
517 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
518 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
519
5201998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
521
522 * mips/interp.c (DEBUG): Cleanups.
523
5241998-12-10 Frank Ch. Eigler <fche@cygnus.com>
525
526 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
527 (tx3904sio_tickle): fflush after a stdout character output.
528
5291998-12-03 Frank Ch. Eigler <fche@cygnus.com>
530
531 * interp.c (sim_close): Uninstall modules.
532
533Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
534
535 * sim-main.h, interp.c (sim_monitor): Change to global
536 function.
537
538Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
539
540 * configure.in (vr4100): Only include vr4100 instructions in
541 simulator.
542 * configure: Re-generate.
543 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
544
545Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
546
547 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
548 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
549 true alternative.
550
551 * configure.in (sim_default_gen, sim_use_gen): Replace with
552 sim_gen.
553 (--enable-sim-igen): Delete config option. Always using IGEN.
554 * configure: Re-generate.
555
556 * Makefile.in (gencode): Kill, kill, kill.
557 * gencode.c: Ditto.
558
559Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
560
561 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
562 bit mips16 igen simulator.
563 * configure: Re-generate.
564
565 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
566 as part of vr4100 ISA.
567 * vr.igen: Mark all instructions as 64 bit only.
568
569Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
570
571 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
572 Pacify GCC.
573
574Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
575
576 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
577 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
578 * configure: Re-generate.
579
580 * m16.igen (BREAK): Define breakpoint instruction.
581 (JALX32): Mark instruction as mips16 and not r3900.
582 * mips.igen (C.cond.fmt): Fix typo in instruction format.
583
584 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
585
586Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
587
588 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
589 insn as a debug breakpoint.
590
591 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
592 pending.slot_size.
593 (PENDING_SCHED): Clean up trace statement.
594 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
595 (PENDING_FILL): Delay write by only one cycle.
596 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
597
598 * sim-main.c (pending_tick): Clean up trace statements. Add trace
599 of pending writes.
600 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
601 32 & 64.
602 (pending_tick): Move incrementing of index to FOR statement.
603 (pending_tick): Only update PENDING_OUT after a write has occured.
604
605 * configure.in: Add explicit mips-lsi-* target. Use gencode to
606 build simulator.
607 * configure: Re-generate.
608
609 * interp.c (sim_engine_run OLD): Delete explicit call to
610 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
611
612Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
613
614 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
615 interrupt level number to match changed SignalExceptionInterrupt
616 macro.
617
618Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
619
620 * interp.c: #include "itable.h" if WITH_IGEN.
621 (get_insn_name): New function.
622 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
623 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
624
625Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
626
627 * configure: Rebuilt to inhale new common/aclocal.m4.
628
629Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
630
631 * dv-tx3904sio.c: Include sim-assert.h.
632
633Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
634
635 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
636 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
637 Reorganize target-specific sim-hardware checks.
638 * configure: rebuilt.
639 * interp.c (sim_open): For tx39 target boards, set
640 OPERATING_ENVIRONMENT, add tx3904sio devices.
641 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
642 ROM executables. Install dv-sockser into sim-modules list.
643
644 * dv-tx3904irc.c: Compiler warning clean-up.
645 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
646 frequent hw-trace messages.
647
648Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
649
650 * vr.igen (MulAcc): Identify as a vr4100 specific function.
651
652Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
653
654 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
655
656 * vr.igen: New file.
657 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
658 * mips.igen: Define vr4100 model. Include vr.igen.
659Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
660
661 * mips.igen (check_mf_hilo): Correct check.
662
663Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
664
665 * sim-main.h (interrupt_event): Add prototype.
666
667 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
668 register_ptr, register_value.
669 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
670
671 * sim-main.h (tracefh): Make extern.
672
673Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
674
675 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
676 Reduce unnecessarily high timer event frequency.
677 * dv-tx3904cpu.c: Ditto for interrupt event.
678
679Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
680
681 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
682 to allay warnings.
683 (interrupt_event): Made non-static.
684
685 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
686 interchange of configuration values for external vs. internal
687 clock dividers.
688
689Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
690
691 * mips.igen (BREAK): Moved code to here for
692 simulator-reserved break instructions.
693 * gencode.c (build_instruction): Ditto.
694 * interp.c (signal_exception): Code moved from here. Non-
695 reserved instructions now use exception vector, rather
696 than halting sim.
697 * sim-main.h: Moved magic constants to here.
698
699Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
700
701 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
702 register upon non-zero interrupt event level, clear upon zero
703 event value.
704 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
705 by passing zero event value.
706 (*_io_{read,write}_buffer): Endianness fixes.
707 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
708 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
709
710 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
711 serial I/O and timer module at base address 0xFFFF0000.
712
713Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
714
715 * mips.igen (SWC1) : Correct the handling of ReverseEndian
716 and BigEndianCPU.
717
718Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
719
720 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
721 parts.
722 * configure: Update.
723
724Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
725
726 * dv-tx3904tmr.c: New file - implements tx3904 timer.
727 * dv-tx3904{irc,cpu}.c: Mild reformatting.
728 * configure.in: Include tx3904tmr in hw_device list.
729 * configure: Rebuilt.
730 * interp.c (sim_open): Instantiate three timer instances.
731 Fix address typo of tx3904irc instance.
732
733Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
734
735 * interp.c (signal_exception): SystemCall exception now uses
736 the exception vector.
737
738Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
739
740 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
741 to allay warnings.
742
743Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
744
745 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
746
747Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
748
749 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
750
751 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
752 sim-main.h. Declare a struct hw_descriptor instead of struct
753 hw_device_descriptor.
754
755Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
756
757 * mips.igen (do_store_left, do_load_left): Compute nr of left and
758 right bits and then re-align left hand bytes to correct byte
759 lanes. Fix incorrect computation in do_store_left when loading
760 bytes from second word.
761
762Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
763
764 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
765 * interp.c (sim_open): Only create a device tree when HW is
766 enabled.
767
768 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
769 * interp.c (signal_exception): Ditto.
770
771Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
772
773 * gencode.c: Mark BEGEZALL as LIKELY.
774
775Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
776
777 * sim-main.h (ALU32_END): Sign extend 32 bit results.
778 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
779
780Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
781
782 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
783 modules. Recognize TX39 target with "mips*tx39" pattern.
784 * configure: Rebuilt.
785 * sim-main.h (*): Added many macros defining bits in
786 TX39 control registers.
787 (SignalInterrupt): Send actual PC instead of NULL.
788 (SignalNMIReset): New exception type.
789 * interp.c (board): New variable for future use to identify
790 a particular board being simulated.
791 (mips_option_handler,mips_options): Added "--board" option.
792 (interrupt_event): Send actual PC.
793 (sim_open): Make memory layout conditional on board setting.
794 (signal_exception): Initial implementation of hardware interrupt
795 handling. Accept another break instruction variant for simulator
796 exit.
797 (decode_coproc): Implement RFE instruction for TX39.
798 (mips.igen): Decode RFE instruction as such.
799 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
800 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
801 bbegin to implement memory map.
802 * dv-tx3904cpu.c: New file.
803 * dv-tx3904irc.c: New file.
804
805Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
806
807 * mips.igen (check_mt_hilo): Create a separate r3900 version.
808
809Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
810
811 * tx.igen (madd,maddu): Replace calls to check_op_hilo
812 with calls to check_div_hilo.
813
814Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
815
816 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
817 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
818 Add special r3900 version of do_mult_hilo.
819 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
820 with calls to check_mult_hilo.
821 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
822 with calls to check_div_hilo.
823
824Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
825
826 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
827 Document a replacement.
828
829Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
830
831 * interp.c (sim_monitor): Make mon_printf work.
832
833Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
834
835 * sim-main.h (INSN_NAME): New arg `cpu'.
836
837Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
838
839 * configure: Regenerated to track ../common/aclocal.m4 changes.
840
841Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
842
843 * configure: Regenerated to track ../common/aclocal.m4 changes.
844 * config.in: Ditto.
845
846Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
847
848 * acconfig.h: New file.
849 * configure.in: Reverted change of Apr 24; use sinclude again.
850
851Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
852
853 * configure: Regenerated to track ../common/aclocal.m4 changes.
854 * config.in: Ditto.
855
856Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
857
858 * configure.in: Don't call sinclude.
859
860Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
861
862 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
863
864Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
865
866 * mips.igen (ERET): Implement.
867
868 * interp.c (decode_coproc): Return sign-extended EPC.
869
870 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
871
872 * interp.c (signal_exception): Do not ignore Trap.
873 (signal_exception): On TRAP, restart at exception address.
874 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
875 (signal_exception): Update.
876 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
877 so that TRAP instructions are caught.
878
879Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
880
881 * sim-main.h (struct hilo_access, struct hilo_history): Define,
882 contains HI/LO access history.
883 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
884 (HIACCESS, LOACCESS): Delete, replace with
885 (HIHISTORY, LOHISTORY): New macros.
886 (CHECKHILO): Delete all, moved to mips.igen
887
888 * gencode.c (build_instruction): Do not generate checks for
889 correct HI/LO register usage.
890
891 * interp.c (old_engine_run): Delete checks for correct HI/LO
892 register usage.
893
894 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
895 check_mf_cycles): New functions.
896 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
897 do_divu, domultx, do_mult, do_multu): Use.
898
899 * tx.igen ("madd", "maddu"): Use.
900
901Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
902
903 * mips.igen (DSRAV): Use function do_dsrav.
904 (SRAV): Use new function do_srav.
905
906 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
907 (B): Sign extend 11 bit immediate.
908 (EXT-B*): Shift 16 bit immediate left by 1.
909 (ADDIU*): Don't sign extend immediate value.
910
911Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
912
913 * m16run.c (sim_engine_run): Restore CIA after handling an event.
914
915 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
916 functions.
917
918 * mips.igen (delayslot32, nullify_next_insn): New functions.
919 (m16.igen): Always include.
920 (do_*): Add more tracing.
921
922 * m16.igen (delayslot16): Add NIA argument, could be called by a
923 32 bit MIPS16 instruction.
924
925 * interp.c (ifetch16): Move function from here.
926 * sim-main.c (ifetch16): To here.
927
928 * sim-main.c (ifetch16, ifetch32): Update to match current
929 implementations of LH, LW.
930 (signal_exception): Don't print out incorrect hex value of illegal
931 instruction.
932
933Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
934
935 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
936 instruction.
937
938 * m16.igen: Implement MIPS16 instructions.
939
940 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
941 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
942 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
943 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
944 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
945 bodies of corresponding code from 32 bit insn to these. Also used
946 by MIPS16 versions of functions.
947
948 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
949 (IMEM16): Drop NR argument from macro.
950
951Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
952
953 * Makefile.in (SIM_OBJS): Add sim-main.o.
954
955 * sim-main.h (address_translation, load_memory, store_memory,
956 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
957 as INLINE_SIM_MAIN.
958 (pr_addr, pr_uword64): Declare.
959 (sim-main.c): Include when H_REVEALS_MODULE_P.
960
961 * interp.c (address_translation, load_memory, store_memory,
962 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
963 from here.
964 * sim-main.c: To here. Fix compilation problems.
965
966 * configure.in: Enable inlining.
967 * configure: Re-config.
968
969Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
970
971 * configure: Regenerated to track ../common/aclocal.m4 changes.
972
973Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
974
975 * mips.igen: Include tx.igen.
976 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
977 * tx.igen: New file, contains MADD and MADDU.
978
979 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
980 the hardwired constant `7'.
981 (store_memory): Ditto.
982 (LOADDRMASK): Move definition to sim-main.h.
983
984 mips.igen (MTC0): Enable for r3900.
985 (ADDU): Add trace.
986
987 mips.igen (do_load_byte): Delete.
988 (do_load, do_store, do_load_left, do_load_write, do_store_left,
989 do_store_right): New functions.
990 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
991
992 configure.in: Let the tx39 use igen again.
993 configure: Update.
994
995Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
996
997 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
998 not an address sized quantity. Return zero for cache sizes.
999
1000Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1001
1002 * mips.igen (r3900): r3900 does not support 64 bit integer
1003 operations.
1004
1005Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1006
1007 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1008 than igen one.
1009 * configure : Rebuild.
1010
1011Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1012
1013 * configure: Regenerated to track ../common/aclocal.m4 changes.
1014
1015Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1016
1017 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1018
1019Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1020
1021 * configure: Regenerated to track ../common/aclocal.m4 changes.
1022 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1023
1024Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1025
1026 * configure: Regenerated to track ../common/aclocal.m4 changes.
1027
1028Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1029
1030 * interp.c (Max, Min): Comment out functions. Not yet used.
1031
1032Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1033
1034 * configure: Regenerated to track ../common/aclocal.m4 changes.
1035
1036Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1037
1038 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1039 configurable settings for stand-alone simulator.
1040
1041 * configure.in: Added X11 search, just in case.
1042
1043 * configure: Regenerated.
1044
1045Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1046
1047 * interp.c (sim_write, sim_read, load_memory, store_memory):
1048 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1049
1050Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1051
1052 * sim-main.h (GETFCC): Return an unsigned value.
1053
1054Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1055
1056 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1057 (DADD): Result destination is RD not RT.
1058
1059Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1060
1061 * sim-main.h (HIACCESS, LOACCESS): Always define.
1062
1063 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1064
1065 * interp.c (sim_info): Delete.
1066
1067Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1068
1069 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1070 (mips_option_handler): New argument `cpu'.
1071 (sim_open): Update call to sim_add_option_table.
1072
1073Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1074
1075 * mips.igen (CxC1): Add tracing.
1076
1077Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1078
1079 * sim-main.h (Max, Min): Declare.
1080
1081 * interp.c (Max, Min): New functions.
1082
1083 * mips.igen (BC1): Add tracing.
1084
1085Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1086
1087 * interp.c Added memory map for stack in vr4100
1088
1089Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1090
1091 * interp.c (load_memory): Add missing "break"'s.
1092
1093Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1094
1095 * interp.c (sim_store_register, sim_fetch_register): Pass in
1096 length parameter. Return -1.
1097
1098Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1099
1100 * interp.c: Added hardware init hook, fixed warnings.
1101
1102Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1103
1104 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1105
1106Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1107
1108 * interp.c (ifetch16): New function.
1109
1110 * sim-main.h (IMEM32): Rename IMEM.
1111 (IMEM16_IMMED): Define.
1112 (IMEM16): Define.
1113 (DELAY_SLOT): Update.
1114
1115 * m16run.c (sim_engine_run): New file.
1116
1117 * m16.igen: All instructions except LB.
1118 (LB): Call do_load_byte.
1119 * mips.igen (do_load_byte): New function.
1120 (LB): Call do_load_byte.
1121
1122 * mips.igen: Move spec for insn bit size and high bit from here.
1123 * Makefile.in (tmp-igen, tmp-m16): To here.
1124
1125 * m16.dc: New file, decode mips16 instructions.
1126
1127 * Makefile.in (SIM_NO_ALL): Define.
1128 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1129
1130Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1131
1132 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1133 point unit to 32 bit registers.
1134 * configure: Re-generate.
1135
1136Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1137
1138 * configure.in (sim_use_gen): Make IGEN the default simulator
1139 generator for generic 32 and 64 bit mips targets.
1140 * configure: Re-generate.
1141
1142Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1143
1144 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1145 bitsize.
1146
1147 * interp.c (sim_fetch_register, sim_store_register): Read/write
1148 FGR from correct location.
1149 (sim_open): Set size of FGR's according to
1150 WITH_TARGET_FLOATING_POINT_BITSIZE.
1151
1152 * sim-main.h (FGR): Store floating point registers in a separate
1153 array.
1154
1155Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1156
1157 * configure: Regenerated to track ../common/aclocal.m4 changes.
1158
1159Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1160
1161 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1162
1163 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1164
1165 * interp.c (pending_tick): New function. Deliver pending writes.
1166
1167 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1168 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1169 it can handle mixed sized quantites and single bits.
1170
1171Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1172
1173 * interp.c (oengine.h): Do not include when building with IGEN.
1174 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1175 (sim_info): Ditto for PROCESSOR_64BIT.
1176 (sim_monitor): Replace ut_reg with unsigned_word.
1177 (*): Ditto for t_reg.
1178 (LOADDRMASK): Define.
1179 (sim_open): Remove defunct check that host FP is IEEE compliant,
1180 using software to emulate floating point.
1181 (value_fpr, ...): Always compile, was conditional on HASFPU.
1182
1183Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1184
1185 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1186 size.
1187
1188 * interp.c (SD, CPU): Define.
1189 (mips_option_handler): Set flags in each CPU.
1190 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1191 (sim_close): Do not clear STATE, deleted anyway.
1192 (sim_write, sim_read): Assume CPU zero's vm should be used for
1193 data transfers.
1194 (sim_create_inferior): Set the PC for all processors.
1195 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1196 argument.
1197 (mips16_entry): Pass correct nr of args to store_word, load_word.
1198 (ColdReset): Cold reset all cpu's.
1199 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1200 (sim_monitor, load_memory, store_memory, signal_exception): Use
1201 `CPU' instead of STATE_CPU.
1202
1203
1204 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1205 SD or CPU_.
1206
1207 * sim-main.h (signal_exception): Add sim_cpu arg.
1208 (SignalException*): Pass both SD and CPU to signal_exception.
1209 * interp.c (signal_exception): Update.
1210
1211 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1212 Ditto
1213 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1214 address_translation): Ditto
1215 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1216
1217Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1218
1219 * configure: Regenerated to track ../common/aclocal.m4 changes.
1220
1221Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1222
1223 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1224
1225 * mips.igen (model): Map processor names onto BFD name.
1226
1227 * sim-main.h (CPU_CIA): Delete.
1228 (SET_CIA, GET_CIA): Define
1229
1230Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1231
1232 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1233 regiser.
1234
1235 * configure.in (default_endian): Configure a big-endian simulator
1236 by default.
1237 * configure: Re-generate.
1238
1239Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1240
1241 * configure: Regenerated to track ../common/aclocal.m4 changes.
1242
1243Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1244
1245 * interp.c (sim_monitor): Handle Densan monitor outbyte
1246 and inbyte functions.
1247
12481997-12-29 Felix Lee <flee@cygnus.com>
1249
1250 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1251
1252Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1253
1254 * Makefile.in (tmp-igen): Arrange for $zero to always be
1255 reset to zero after every instruction.
1256
1257Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1258
1259 * configure: Regenerated to track ../common/aclocal.m4 changes.
1260 * config.in: Ditto.
1261
1262Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1263
1264 * mips.igen (MSUB): Fix to work like MADD.
1265 * gencode.c (MSUB): Similarly.
1266
1267Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1268
1269 * configure: Regenerated to track ../common/aclocal.m4 changes.
1270
1271Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1272
1273 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1274
1275Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1276
1277 * sim-main.h (sim-fpu.h): Include.
1278
1279 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1280 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1281 using host independant sim_fpu module.
1282
1283Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1284
1285 * interp.c (signal_exception): Report internal errors with SIGABRT
1286 not SIGQUIT.
1287
1288 * sim-main.h (C0_CONFIG): New register.
1289 (signal.h): No longer include.
1290
1291 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1292
1293Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1294
1295 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1296
1297Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1298
1299 * mips.igen: Tag vr5000 instructions.
1300 (ANDI): Was missing mipsIV model, fix assembler syntax.
1301 (do_c_cond_fmt): New function.
1302 (C.cond.fmt): Handle mips I-III which do not support CC field
1303 separatly.
1304 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1305 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1306 in IV3.2 spec.
1307 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1308 vr5000 which saves LO in a GPR separatly.
1309
1310 * configure.in (enable-sim-igen): For vr5000, select vr5000
1311 specific instructions.
1312 * configure: Re-generate.
1313
1314Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1315
1316 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1317
1318 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1319 fmt_uninterpreted_64 bit cases to switch. Convert to
1320 fmt_formatted,
1321
1322 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1323
1324 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1325 as specified in IV3.2 spec.
1326 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1327
1328Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1329
1330 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1331 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1332 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1333 PENDING_FILL versions of instructions. Simplify.
1334 (X): New function.
1335 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1336 instructions.
1337 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1338 a signed value.
1339 (MTHI, MFHI): Disable code checking HI-LO.
1340
1341 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1342 global.
1343 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1344
1345Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1346
1347 * gencode.c (build_mips16_operands): Replace IPC with cia.
1348
1349 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1350 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1351 IPC to `cia'.
1352 (UndefinedResult): Replace function with macro/function
1353 combination.
1354 (sim_engine_run): Don't save PC in IPC.
1355
1356 * sim-main.h (IPC): Delete.
1357
1358
1359 * interp.c (signal_exception, store_word, load_word,
1360 address_translation, load_memory, store_memory, cache_op,
1361 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1362 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1363 current instruction address - cia - argument.
1364 (sim_read, sim_write): Call address_translation directly.
1365 (sim_engine_run): Rename variable vaddr to cia.
1366 (signal_exception): Pass cia to sim_monitor
1367
1368 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1369 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1370 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1371
1372 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1373 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1374 SIM_ASSERT.
1375
1376 * interp.c (signal_exception): Pass restart address to
1377 sim_engine_restart.
1378
1379 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1380 idecode.o): Add dependency.
1381
1382 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1383 Delete definitions
1384 (DELAY_SLOT): Update NIA not PC with branch address.
1385 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1386
1387 * mips.igen: Use CIA not PC in branch calculations.
1388 (illegal): Call SignalException.
1389 (BEQ, ADDIU): Fix assembler.
1390
1391Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1392
1393 * m16.igen (JALX): Was missing.
1394
1395 * configure.in (enable-sim-igen): New configuration option.
1396 * configure: Re-generate.
1397
1398 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1399
1400 * interp.c (load_memory, store_memory): Delete parameter RAW.
1401 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1402 bypassing {load,store}_memory.
1403
1404 * sim-main.h (ByteSwapMem): Delete definition.
1405
1406 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1407
1408 * interp.c (sim_do_command, sim_commands): Delete mips specific
1409 commands. Handled by module sim-options.
1410
1411 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1412 (WITH_MODULO_MEMORY): Define.
1413
1414 * interp.c (sim_info): Delete code printing memory size.
1415
1416 * interp.c (mips_size): Nee sim_size, delete function.
1417 (power2): Delete.
1418 (monitor, monitor_base, monitor_size): Delete global variables.
1419 (sim_open, sim_close): Delete code creating monitor and other
1420 memory regions. Use sim-memopts module, via sim_do_commandf, to
1421 manage memory regions.
1422 (load_memory, store_memory): Use sim-core for memory model.
1423
1424 * interp.c (address_translation): Delete all memory map code
1425 except line forcing 32 bit addresses.
1426
1427Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1428
1429 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1430 trace options.
1431
1432 * interp.c (logfh, logfile): Delete globals.
1433 (sim_open, sim_close): Delete code opening & closing log file.
1434 (mips_option_handler): Delete -l and -n options.
1435 (OPTION mips_options): Ditto.
1436
1437 * interp.c (OPTION mips_options): Rename option trace to dinero.
1438 (mips_option_handler): Update.
1439
1440Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1441
1442 * interp.c (fetch_str): New function.
1443 (sim_monitor): Rewrite using sim_read & sim_write.
1444 (sim_open): Check magic number.
1445 (sim_open): Write monitor vectors into memory using sim_write.
1446 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1447 (sim_read, sim_write): Simplify - transfer data one byte at a
1448 time.
1449 (load_memory, store_memory): Clarify meaning of parameter RAW.
1450
1451 * sim-main.h (isHOST): Defete definition.
1452 (isTARGET): Mark as depreciated.
1453 (address_translation): Delete parameter HOST.
1454
1455 * interp.c (address_translation): Delete parameter HOST.
1456
1457Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1458
1459 * mips.igen:
1460
1461 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1462 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1463
1464Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1465
1466 * mips.igen: Add model filter field to records.
1467
1468Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1469
1470 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1471
1472 interp.c (sim_engine_run): Do not compile function sim_engine_run
1473 when WITH_IGEN == 1.
1474
1475 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1476 target architecture.
1477
1478 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1479 igen. Replace with configuration variables sim_igen_flags /
1480 sim_m16_flags.
1481
1482 * m16.igen: New file. Copy mips16 insns here.
1483 * mips.igen: From here.
1484
1485Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1486
1487 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1488 to top.
1489 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1490
1491Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1492
1493 * gencode.c (build_instruction): Follow sim_write's lead in using
1494 BigEndianMem instead of !ByteSwapMem.
1495
1496Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1497
1498 * configure.in (sim_gen): Dependent on target, select type of
1499 generator. Always select old style generator.
1500
1501 configure: Re-generate.
1502
1503 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1504 targets.
1505 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1506 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1507 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1508 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1509 SIM_@sim_gen@_*, set by autoconf.
1510
1511Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1514
1515 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1516 CURRENT_FLOATING_POINT instead.
1517
1518 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1519 (address_translation): Raise exception InstructionFetch when
1520 translation fails and isINSTRUCTION.
1521
1522 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1523 sim_engine_run): Change type of of vaddr and paddr to
1524 address_word.
1525 (address_translation, prefetch, load_memory, store_memory,
1526 cache_op): Change type of vAddr and pAddr to address_word.
1527
1528 * gencode.c (build_instruction): Change type of vaddr and paddr to
1529 address_word.
1530
1531Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1532
1533 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1534 macro to obtain result of ALU op.
1535
1536Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1537
1538 * interp.c (sim_info): Call profile_print.
1539
1540Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1541
1542 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1543
1544 * sim-main.h (WITH_PROFILE): Do not define, defined in
1545 common/sim-config.h. Use sim-profile module.
1546 (simPROFILE): Delete defintion.
1547
1548 * interp.c (PROFILE): Delete definition.
1549 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1550 (sim_close): Delete code writing profile histogram.
1551 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1552 Delete.
1553 (sim_engine_run): Delete code profiling the PC.
1554
1555Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1556
1557 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1558
1559 * interp.c (sim_monitor): Make register pointers of type
1560 unsigned_word*.
1561
1562 * sim-main.h: Make registers of type unsigned_word not
1563 signed_word.
1564
1565Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1566
1567 * interp.c (sync_operation): Rename from SyncOperation, make
1568 global, add SD argument.
1569 (prefetch): Rename from Prefetch, make global, add SD argument.
1570 (decode_coproc): Make global.
1571
1572 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1573
1574 * gencode.c (build_instruction): Generate DecodeCoproc not
1575 decode_coproc calls.
1576
1577 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1578 (SizeFGR): Move to sim-main.h
1579 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1580 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1581 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1582 sim-main.h.
1583 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1584 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1585 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1586 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1587 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1588 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1589
1590 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1591 exception.
1592 (sim-alu.h): Include.
1593 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1594 (sim_cia): Typedef to instruction_address.
1595
1596Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1597
1598 * Makefile.in (interp.o): Rename generated file engine.c to
1599 oengine.c.
1600
1601 * interp.c: Update.
1602
1603Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1604
1605 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1606
1607Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1608
1609 * gencode.c (build_instruction): For "FPSQRT", output correct
1610 number of arguments to Recip.
1611
1612Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1613
1614 * Makefile.in (interp.o): Depends on sim-main.h
1615
1616 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1617
1618 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1619 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1620 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1621 STATE, DSSTATE): Define
1622 (GPR, FGRIDX, ..): Define.
1623
1624 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1625 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1626 (GPR, FGRIDX, ...): Delete macros.
1627
1628 * interp.c: Update names to match defines from sim-main.h
1629
1630Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1631
1632 * interp.c (sim_monitor): Add SD argument.
1633 (sim_warning): Delete. Replace calls with calls to
1634 sim_io_eprintf.
1635 (sim_error): Delete. Replace calls with sim_io_error.
1636 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1637 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1638 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1639 argument.
1640 (mips_size): Rename from sim_size. Add SD argument.
1641
1642 * interp.c (simulator): Delete global variable.
1643 (callback): Delete global variable.
1644 (mips_option_handler, sim_open, sim_write, sim_read,
1645 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1646 sim_size,sim_monitor): Use sim_io_* not callback->*.
1647 (sim_open): ZALLOC simulator struct.
1648 (PROFILE): Do not define.
1649
1650Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1651
1652 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1653 support.h with corresponding code.
1654
1655 * sim-main.h (word64, uword64), support.h: Move definition to
1656 sim-main.h.
1657 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1658
1659 * support.h: Delete
1660 * Makefile.in: Update dependencies
1661 * interp.c: Do not include.
1662
1663Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1664
1665 * interp.c (address_translation, load_memory, store_memory,
1666 cache_op): Rename to from AddressTranslation et.al., make global,
1667 add SD argument
1668
1669 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1670 CacheOp): Define.
1671
1672 * interp.c (SignalException): Rename to signal_exception, make
1673 global.
1674
1675 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1676
1677 * sim-main.h (SignalException, SignalExceptionInterrupt,
1678 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1679 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1680 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1681 Define.
1682
1683 * interp.c, support.h: Use.
1684
1685Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1686
1687 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1688 to value_fpr / store_fpr. Add SD argument.
1689 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1690 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1691
1692 * sim-main.h (ValueFPR, StoreFPR): Define.
1693
1694Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1695
1696 * interp.c (sim_engine_run): Check consistency between configure
1697 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1698 and HASFPU.
1699
1700 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1701 (mips_fpu): Configure WITH_FLOATING_POINT.
1702 (mips_endian): Configure WITH_TARGET_ENDIAN.
1703 * configure: Update.
1704
1705Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1706
1707 * configure: Regenerated to track ../common/aclocal.m4 changes.
1708
1709Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1710
1711 * configure: Regenerated.
1712
1713Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1714
1715 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1716
1717Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1718
1719 * gencode.c (print_igen_insn_models): Assume certain architectures
1720 include all mips* instructions.
1721 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1722 instruction.
1723
1724 * Makefile.in (tmp.igen): Add target. Generate igen input from
1725 gencode file.
1726
1727 * gencode.c (FEATURE_IGEN): Define.
1728 (main): Add --igen option. Generate output in igen format.
1729 (process_instructions): Format output according to igen option.
1730 (print_igen_insn_format): New function.
1731 (print_igen_insn_models): New function.
1732 (process_instructions): Only issue warnings and ignore
1733 instructions when no FEATURE_IGEN.
1734
1735Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1736
1737 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1738 MIPS targets.
1739
1740Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1741
1742 * configure: Regenerated to track ../common/aclocal.m4 changes.
1743
1744Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1745
1746 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1747 SIM_RESERVED_BITS): Delete, moved to common.
1748 (SIM_EXTRA_CFLAGS): Update.
1749
1750Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1751
1752 * configure.in: Configure non-strict memory alignment.
1753 * configure: Regenerated to track ../common/aclocal.m4 changes.
1754
1755Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1756
1757 * configure: Regenerated to track ../common/aclocal.m4 changes.
1758
1759Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1760
1761 * gencode.c (SDBBP,DERET): Added (3900) insns.
1762 (RFE): Turn on for 3900.
1763 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1764 (dsstate): Made global.
1765 (SUBTARGET_R3900): Added.
1766 (CANCELDELAYSLOT): New.
1767 (SignalException): Ignore SystemCall rather than ignore and
1768 terminate. Add DebugBreakPoint handling.
1769 (decode_coproc): New insns RFE, DERET; and new registers Debug
1770 and DEPC protected by SUBTARGET_R3900.
1771 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1772 bits explicitly.
1773 * Makefile.in,configure.in: Add mips subtarget option.
1774 * configure: Update.
1775
1776Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1777
1778 * gencode.c: Add r3900 (tx39).
1779
1780
1781Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1782
1783 * gencode.c (build_instruction): Don't need to subtract 4 for
1784 JALR, just 2.
1785
1786Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1787
1788 * interp.c: Correct some HASFPU problems.
1789
1790Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1791
1792 * configure: Regenerated to track ../common/aclocal.m4 changes.
1793
1794Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1795
1796 * interp.c (mips_options): Fix samples option short form, should
1797 be `x'.
1798
1799Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1800
1801 * interp.c (sim_info): Enable info code. Was just returning.
1802
1803Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1804
1805 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1806 MFC0.
1807
1808Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1809
1810 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1811 constants.
1812 (build_instruction): Ditto for LL.
1813
1814Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1815
1816 * configure: Regenerated to track ../common/aclocal.m4 changes.
1817
1818Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1819
1820 * configure: Regenerated to track ../common/aclocal.m4 changes.
1821 * config.in: Ditto.
1822
1823Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1824
1825 * interp.c (sim_open): Add call to sim_analyze_program, update
1826 call to sim_config.
1827
1828Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1829
1830 * interp.c (sim_kill): Delete.
1831 (sim_create_inferior): Add ABFD argument. Set PC from same.
1832 (sim_load): Move code initializing trap handlers from here.
1833 (sim_open): To here.
1834 (sim_load): Delete, use sim-hload.c.
1835
1836 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1837
1838Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1839
1840 * configure: Regenerated to track ../common/aclocal.m4 changes.
1841 * config.in: Ditto.
1842
1843Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1844
1845 * interp.c (sim_open): Add ABFD argument.
1846 (sim_load): Move call to sim_config from here.
1847 (sim_open): To here. Check return status.
1848
1849Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1850
1851 * gencode.c (build_instruction): Two arg MADD should
1852 not assign result to $0.
1853
1854Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1855
1856 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1857 * sim/mips/configure.in: Regenerate.
1858
1859Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1860
1861 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1862 signed8, unsigned8 et.al. types.
1863
1864 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1865 hosts when selecting subreg.
1866
1867Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1868
1869 * interp.c (sim_engine_run): Reset the ZERO register to zero
1870 regardless of FEATURE_WARN_ZERO.
1871 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1872
1873Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1874
1875 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1876 (SignalException): For BreakPoints ignore any mode bits and just
1877 save the PC.
1878 (SignalException): Always set the CAUSE register.
1879
1880Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1881
1882 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1883 exception has been taken.
1884
1885 * interp.c: Implement the ERET and mt/f sr instructions.
1886
1887Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1888
1889 * interp.c (SignalException): Don't bother restarting an
1890 interrupt.
1891
1892Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1893
1894 * interp.c (SignalException): Really take an interrupt.
1895 (interrupt_event): Only deliver interrupts when enabled.
1896
1897Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1898
1899 * interp.c (sim_info): Only print info when verbose.
1900 (sim_info) Use sim_io_printf for output.
1901
1902Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1903
1904 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1905 mips architectures.
1906
1907Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1908
1909 * interp.c (sim_do_command): Check for common commands if a
1910 simulator specific command fails.
1911
1912Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1913
1914 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1915 and simBE when DEBUG is defined.
1916
1917Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1918
1919 * interp.c (interrupt_event): New function. Pass exception event
1920 onto exception handler.
1921
1922 * configure.in: Check for stdlib.h.
1923 * configure: Regenerate.
1924
1925 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1926 variable declaration.
1927 (build_instruction): Initialize memval1.
1928 (build_instruction): Add UNUSED attribute to byte, bigend,
1929 reverse.
1930 (build_operands): Ditto.
1931
1932 * interp.c: Fix GCC warnings.
1933 (sim_get_quit_code): Delete.
1934
1935 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1936 * Makefile.in: Ditto.
1937 * configure: Re-generate.
1938
1939 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1940
1941Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1942
1943 * interp.c (mips_option_handler): New function parse argumes using
1944 sim-options.
1945 (myname): Replace with STATE_MY_NAME.
1946 (sim_open): Delete check for host endianness - performed by
1947 sim_config.
1948 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1949 (sim_open): Move much of the initialization from here.
1950 (sim_load): To here. After the image has been loaded and
1951 endianness set.
1952 (sim_open): Move ColdReset from here.
1953 (sim_create_inferior): To here.
1954 (sim_open): Make FP check less dependant on host endianness.
1955
1956 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1957 run.
1958 * interp.c (sim_set_callbacks): Delete.
1959
1960 * interp.c (membank, membank_base, membank_size): Replace with
1961 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1962 (sim_open): Remove call to callback->init. gdb/run do this.
1963
1964 * interp.c: Update
1965
1966 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1967
1968 * interp.c (big_endian_p): Delete, replaced by
1969 current_target_byte_order.
1970
1971Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1972
1973 * interp.c (host_read_long, host_read_word, host_swap_word,
1974 host_swap_long): Delete. Using common sim-endian.
1975 (sim_fetch_register, sim_store_register): Use H2T.
1976 (pipeline_ticks): Delete. Handled by sim-events.
1977 (sim_info): Update.
1978 (sim_engine_run): Update.
1979
1980Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1981
1982 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1983 reason from here.
1984 (SignalException): To here. Signal using sim_engine_halt.
1985 (sim_stop_reason): Delete, moved to common.
1986
1987Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1988
1989 * interp.c (sim_open): Add callback argument.
1990 (sim_set_callbacks): Delete SIM_DESC argument.
1991 (sim_size): Ditto.
1992
1993Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1994
1995 * Makefile.in (SIM_OBJS): Add common modules.
1996
1997 * interp.c (sim_set_callbacks): Also set SD callback.
1998 (set_endianness, xfer_*, swap_*): Delete.
1999 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2000 Change to functions using sim-endian macros.
2001 (control_c, sim_stop): Delete, use common version.
2002 (simulate): Convert into.
2003 (sim_engine_run): This function.
2004 (sim_resume): Delete.
2005
2006 * interp.c (simulation): New variable - the simulator object.
2007 (sim_kind): Delete global - merged into simulation.
2008 (sim_load): Cleanup. Move PC assignment from here.
2009 (sim_create_inferior): To here.
2010
2011 * sim-main.h: New file.
2012 * interp.c (sim-main.h): Include.
2013
2014Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2015
2016 * configure: Regenerated to track ../common/aclocal.m4 changes.
2017
2018Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2019
2020 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2021
2022Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2023
2024 * gencode.c (build_instruction): DIV instructions: check
2025 for division by zero and integer overflow before using
2026 host's division operation.
2027
2028Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2029
2030 * Makefile.in (SIM_OBJS): Add sim-load.o.
2031 * interp.c: #include bfd.h.
2032 (target_byte_order): Delete.
2033 (sim_kind, myname, big_endian_p): New static locals.
2034 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2035 after argument parsing. Recognize -E arg, set endianness accordingly.
2036 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2037 load file into simulator. Set PC from bfd.
2038 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2039 (set_endianness): Use big_endian_p instead of target_byte_order.
2040
2041Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2042
2043 * interp.c (sim_size): Delete prototype - conflicts with
2044 definition in remote-sim.h. Correct definition.
2045
2046Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2047
2048 * configure: Regenerated to track ../common/aclocal.m4 changes.
2049 * config.in: Ditto.
2050
2051Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2052
2053 * interp.c (sim_open): New arg `kind'.
2054
2055 * configure: Regenerated to track ../common/aclocal.m4 changes.
2056
2057Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2058
2059 * configure: Regenerated to track ../common/aclocal.m4 changes.
2060
2061Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2062
2063 * interp.c (sim_open): Set optind to 0 before calling getopt.
2064
2065Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2066
2067 * configure: Regenerated to track ../common/aclocal.m4 changes.
2068
2069Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2070
2071 * interp.c : Replace uses of pr_addr with pr_uword64
2072 where the bit length is always 64 independent of SIM_ADDR.
2073 (pr_uword64) : added.
2074
2075Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2076
2077 * configure: Re-generate.
2078
2079Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2080
2081 * configure: Regenerate to track ../common/aclocal.m4 changes.
2082
2083Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2084
2085 * interp.c (sim_open): New SIM_DESC result. Argument is now
2086 in argv form.
2087 (other sim_*): New SIM_DESC argument.
2088
2089Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2090
2091 * interp.c: Fix printing of addresses for non-64-bit targets.
2092 (pr_addr): Add function to print address based on size.
2093
2094Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2095
2096 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2097
2098Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2099
2100 * gencode.c (build_mips16_operands): Correct computation of base
2101 address for extended PC relative instruction.
2102
2103Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2104
2105 * interp.c (mips16_entry): Add support for floating point cases.
2106 (SignalException): Pass floating point cases to mips16_entry.
2107 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2108 registers.
2109 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2110 or fmt_word.
2111 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2112 and then set the state to fmt_uninterpreted.
2113 (COP_SW): Temporarily set the state to fmt_word while calling
2114 ValueFPR.
2115
2116Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2117
2118 * gencode.c (build_instruction): The high order may be set in the
2119 comparison flags at any ISA level, not just ISA 4.
2120
2121Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2122
2123 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2124 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2125 * configure.in: sinclude ../common/aclocal.m4.
2126 * configure: Regenerated.
2127
2128Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2129
2130 * configure: Rebuild after change to aclocal.m4.
2131
2132Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2133
2134 * configure configure.in Makefile.in: Update to new configure
2135 scheme which is more compatible with WinGDB builds.
2136 * configure.in: Improve comment on how to run autoconf.
2137 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2138 * Makefile.in: Use autoconf substitution to install common
2139 makefile fragment.
2140
2141Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2142
2143 * gencode.c (build_instruction): Use BigEndianCPU instead of
2144 ByteSwapMem.
2145
2146Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2147
2148 * interp.c (sim_monitor): Make output to stdout visible in
2149 wingdb's I/O log window.
2150
2151Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2152
2153 * support.h: Undo previous change to SIGTRAP
2154 and SIGQUIT values.
2155
2156Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2157
2158 * interp.c (store_word, load_word): New static functions.
2159 (mips16_entry): New static function.
2160 (SignalException): Look for mips16 entry and exit instructions.
2161 (simulate): Use the correct index when setting fpr_state after
2162 doing a pending move.
2163
2164Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2165
2166 * interp.c: Fix byte-swapping code throughout to work on
2167 both little- and big-endian hosts.
2168
2169Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2170
2171 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2172 with gdb/config/i386/xm-windows.h.
2173
2174Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2175
2176 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2177 that messes up arithmetic shifts.
2178
2179Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2180
2181 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2182 SIGTRAP and SIGQUIT for _WIN32.
2183
2184Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2185
2186 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2187 force a 64 bit multiplication.
2188 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2189 destination register is 0, since that is the default mips16 nop
2190 instruction.
2191
2192Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2193
2194 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2195 (build_endian_shift): Don't check proc64.
2196 (build_instruction): Always set memval to uword64. Cast op2 to
2197 uword64 when shifting it left in memory instructions. Always use
2198 the same code for stores--don't special case proc64.
2199
2200 * gencode.c (build_mips16_operands): Fix base PC value for PC
2201 relative operands.
2202 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2203 jal instruction.
2204 * interp.c (simJALDELAYSLOT): Define.
2205 (JALDELAYSLOT): Define.
2206 (INDELAYSLOT, INJALDELAYSLOT): Define.
2207 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2208
2209Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2210
2211 * interp.c (sim_open): add flush_cache as a PMON routine
2212 (sim_monitor): handle flush_cache by ignoring it
2213
2214Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2215
2216 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2217 BigEndianMem.
2218 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2219 (BigEndianMem): Rename to ByteSwapMem and change sense.
2220 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2221 BigEndianMem references to !ByteSwapMem.
2222 (set_endianness): New function, with prototype.
2223 (sim_open): Call set_endianness.
2224 (sim_info): Use simBE instead of BigEndianMem.
2225 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2226 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2227 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2228 ifdefs, keeping the prototype declaration.
2229 (swap_word): Rewrite correctly.
2230 (ColdReset): Delete references to CONFIG. Delete endianness related
2231 code; moved to set_endianness.
2232
2233Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2234
2235 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2236 * interp.c (CHECKHILO): Define away.
2237 (simSIGINT): New macro.
2238 (membank_size): Increase from 1MB to 2MB.
2239 (control_c): New function.
2240 (sim_resume): Rename parameter signal to signal_number. Add local
2241 variable prev. Call signal before and after simulate.
2242 (sim_stop_reason): Add simSIGINT support.
2243 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2244 functions always.
2245 (sim_warning): Delete call to SignalException. Do call printf_filtered
2246 if logfh is NULL.
2247 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2248 a call to sim_warning.
2249
2250Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2251
2252 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2253 16 bit instructions.
2254
2255Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2256
2257 Add support for mips16 (16 bit MIPS implementation):
2258 * gencode.c (inst_type): Add mips16 instruction encoding types.
2259 (GETDATASIZEINSN): Define.
2260 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2261 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2262 mtlo.
2263 (MIPS16_DECODE): New table, for mips16 instructions.
2264 (bitmap_val): New static function.
2265 (struct mips16_op): Define.
2266 (mips16_op_table): New table, for mips16 operands.
2267 (build_mips16_operands): New static function.
2268 (process_instructions): If PC is odd, decode a mips16
2269 instruction. Break out instruction handling into new
2270 build_instruction function.
2271 (build_instruction): New static function, broken out of
2272 process_instructions. Check modifiers rather than flags for SHIFT
2273 bit count and m[ft]{hi,lo} direction.
2274 (usage): Pass program name to fprintf.
2275 (main): Remove unused variable this_option_optind. Change
2276 ``*loptarg++'' to ``loptarg++''.
2277 (my_strtoul): Parenthesize && within ||.
2278 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2279 (simulate): If PC is odd, fetch a 16 bit instruction, and
2280 increment PC by 2 rather than 4.
2281 * configure.in: Add case for mips16*-*-*.
2282 * configure: Rebuild.
2283
2284Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2285
2286 * interp.c: Allow -t to enable tracing in standalone simulator.
2287 Fix garbage output in trace file and error messages.
2288
2289Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2290
2291 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2292 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2293 * configure.in: Simplify using macros in ../common/aclocal.m4.
2294 * configure: Regenerated.
2295 * tconfig.in: New file.
2296
2297Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2298
2299 * interp.c: Fix bugs in 64-bit port.
2300 Use ansi function declarations for msvc compiler.
2301 Initialize and test file pointer in trace code.
2302 Prevent duplicate definition of LAST_EMED_REGNUM.
2303
2304Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2305
2306 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2307
2308Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2309
2310 * interp.c (SignalException): Check for explicit terminating
2311 breakpoint value.
2312 * gencode.c: Pass instruction value through SignalException()
2313 calls for Trap, Breakpoint and Syscall.
2314
2315Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2316
2317 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2318 only used on those hosts that provide it.
2319 * configure.in: Add sqrt() to list of functions to be checked for.
2320 * config.in: Re-generated.
2321 * configure: Re-generated.
2322
2323Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2324
2325 * gencode.c (process_instructions): Call build_endian_shift when
2326 expanding STORE RIGHT, to fix swr.
2327 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2328 clear the high bits.
2329 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2330 Fix float to int conversions to produce signed values.
2331
2332Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2333
2334 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2335 (process_instructions): Correct handling of nor instruction.
2336 Correct shift count for 32 bit shift instructions. Correct sign
2337 extension for arithmetic shifts to not shift the number of bits in
2338 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2339 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2340 Fix madd.
2341 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2342 It's OK to have a mult follow a mult. What's not OK is to have a
2343 mult follow an mfhi.
2344 (Convert): Comment out incorrect rounding code.
2345
2346Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2347
2348 * interp.c (sim_monitor): Improved monitor printf
2349 simulation. Tidied up simulator warnings, and added "--log" option
2350 for directing warning message output.
2351 * gencode.c: Use sim_warning() rather than WARNING macro.
2352
2353Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2354
2355 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2356 getopt1.o, rather than on gencode.c. Link objects together.
2357 Don't link against -liberty.
2358 (gencode.o, getopt.o, getopt1.o): New targets.
2359 * gencode.c: Include <ctype.h> and "ansidecl.h".
2360 (AND): Undefine after including "ansidecl.h".
2361 (ULONG_MAX): Define if not defined.
2362 (OP_*): Don't define macros; now defined in opcode/mips.h.
2363 (main): Call my_strtoul rather than strtoul.
2364 (my_strtoul): New static function.
2365
2366Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2367
2368 * gencode.c (process_instructions): Generate word64 and uword64
2369 instead of `long long' and `unsigned long long' data types.
2370 * interp.c: #include sysdep.h to get signals, and define default
2371 for SIGBUS.
2372 * (Convert): Work around for Visual-C++ compiler bug with type
2373 conversion.
2374 * support.h: Make things compile under Visual-C++ by using
2375 __int64 instead of `long long'. Change many refs to long long
2376 into word64/uword64 typedefs.
2377
2378Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2379
2380 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2381 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2382 (docdir): Removed.
2383 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2384 (AC_PROG_INSTALL): Added.
2385 (AC_PROG_CC): Moved to before configure.host call.
2386 * configure: Rebuilt.
2387
2388Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2389
2390 * configure.in: Define @SIMCONF@ depending on mips target.
2391 * configure: Rebuild.
2392 * Makefile.in (run): Add @SIMCONF@ to control simulator
2393 construction.
2394 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2395 * interp.c: Remove some debugging, provide more detailed error
2396 messages, update memory accesses to use LOADDRMASK.
2397
2398Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2399
2400 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2401 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2402 stamp-h.
2403 * configure: Rebuild.
2404 * config.in: New file, generated by autoheader.
2405 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2406 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2407 HAVE_ANINT and HAVE_AINT, as appropriate.
2408 * Makefile.in (run): Use @LIBS@ rather than -lm.
2409 (interp.o): Depend upon config.h.
2410 (Makefile): Just rebuild Makefile.
2411 (clean): Remove stamp-h.
2412 (mostlyclean): Make the same as clean, not as distclean.
2413 (config.h, stamp-h): New targets.
2414
2415Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2416
2417 * interp.c (ColdReset): Fix boolean test. Make all simulator
2418 globals static.
2419
2420Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2421
2422 * interp.c (xfer_direct_word, xfer_direct_long,
2423 swap_direct_word, swap_direct_long, xfer_big_word,
2424 xfer_big_long, xfer_little_word, xfer_little_long,
2425 swap_word,swap_long): Added.
2426 * interp.c (ColdReset): Provide function indirection to
2427 host<->simulated_target transfer routines.
2428 * interp.c (sim_store_register, sim_fetch_register): Updated to
2429 make use of indirected transfer routines.
2430
2431Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2432
2433 * gencode.c (process_instructions): Ensure FP ABS instruction
2434 recognised.
2435 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2436 system call support.
2437
2438Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2439
2440 * interp.c (sim_do_command): Complain if callback structure not
2441 initialised.
2442
2443Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2444
2445 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2446 support for Sun hosts.
2447 * Makefile.in (gencode): Ensure the host compiler and libraries
2448 used for cross-hosted build.
2449
2450Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2451
2452 * interp.c, gencode.c: Some more (TODO) tidying.
2453
2454Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2455
2456 * gencode.c, interp.c: Replaced explicit long long references with
2457 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2458 * support.h (SET64LO, SET64HI): Macros added.
2459
2460Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2461
2462 * configure: Regenerate with autoconf 2.7.
2463
2464Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2465
2466 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2467 * support.h: Remove superfluous "1" from #if.
2468 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2469
2470Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2471
2472 * interp.c (StoreFPR): Control UndefinedResult() call on
2473 WARN_RESULT manifest.
2474
2475Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2476
2477 * gencode.c: Tidied instruction decoding, and added FP instruction
2478 support.
2479
2480 * interp.c: Added dineroIII, and BSD profiling support. Also
2481 run-time FP handling.
2482
2483Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2484
2485 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2486 gencode.c, interp.c, support.h: created.
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