]> git.ipfire.org Git - thirdparty/kernel/stable.git/blame - arch/x86/kvm/x86.c
projects / thirdparty / kernel / stable.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: Move vcpu_load to arch-specific kvm_arch_vcpu_ioctl_get_mpstate
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
fab0aa3b
EM		 110static bool __read_mostly report_ignored_msrs = true;
111module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
9ed96e87
MT		 113unsigned int min_timer_period_us = 500;
114module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
630994b3
MT		 116static bool __read_mostly kvmclock_periodic_sync = true;
117module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
893590c7 119bool __read_mostly kvm_has_tsc_control;
92a1f12d 120EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 121u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 123u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125u64 __read_mostly kvm_max_tsc_scaling_ratio;
126EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 127u64 __read_mostly kvm_default_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 129
cc578287 130/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 131static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 132module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
d0659d94 134/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 135unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 136module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
52004014
FW		 138static bool __read_mostly vector_hashing = true;
139module_param(vector_hashing, bool, S_IRUGO);
140
18863bdd
AK		 141#define KVM_NR_SHARED_MSRS 16
142
143struct kvm_shared_msrs_global {
144 int nr;
2bf78fa7 145 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 146};
147
148struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
2bf78fa7
SY		 151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 155};
156
157static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 158static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 159
417bc304 160struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 171 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 176 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 184 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 185 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 186 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 187 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
188 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
189 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
190 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
191 { "mmu_flooded", VM_STAT(mmu_flooded) },
192 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 193 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 194 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 195 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 196 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 197 { "max_mmu_page_hash_collisions",
198 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 199 { NULL }
200};
201
2acf923e
DC		 202u64 __read_mostly host_xcr0;
203
b6785def 204static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 205
af585b92
GN		 206static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
207{
208 int i;
209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
210 vcpu->arch.apf.gfns[i] = ~0;
211}
212
18863bdd
AK		 213static void kvm_on_user_return(struct user_return_notifier *urn)
214{
215 unsigned slot;
18863bdd
AK		 216 struct kvm_shared_msrs *locals
217 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 218 struct kvm_shared_msr_values *values;
1650b4eb
IA		 219 unsigned long flags;
220
221 /*
222 * Disabling irqs at this point since the following code could be
223 * interrupted and executed through kvm_arch_hardware_disable()
224 */
225 local_irq_save(flags);
226 if (locals->registered) {
227 locals->registered = false;
228 user_return_notifier_unregister(urn);
229 }
230 local_irq_restore(flags);
18863bdd 231 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 232 values = &locals->values[slot];
233 if (values->host != values->curr) {
234 wrmsrl(shared_msrs_global.msrs[slot], values->host);
235 values->curr = values->host;
18863bdd
AK		 236 }
237 }
18863bdd
AK		 238}
239
2bf78fa7 240static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 241{
18863bdd 242 u64 value;
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 245
2bf78fa7
SY		 246 /* only read, and nobody should modify it at this time,
247 * so don't need lock */
248 if (slot >= shared_msrs_global.nr) {
249 printk(KERN_ERR "kvm: invalid MSR slot!");
250 return;
251 }
252 rdmsrl_safe(msr, &value);
253 smsr->values[slot].host = value;
254 smsr->values[slot].curr = value;
255}
256
257void kvm_define_shared_msr(unsigned slot, u32 msr)
258{
0123be42 259 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 260 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 261 if (slot >= shared_msrs_global.nr)
262 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 263}
264EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
265
266static void kvm_shared_msr_cpu_online(void)
267{
268 unsigned i;
18863bdd
AK		 269
270 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 271 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 272}
273
8b3c3104 274int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 275{
013f6a5d
MT		 276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 278 int err;
18863bdd 279
2bf78fa7 280 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 281 return 0;
2bf78fa7 282 smsr->values[slot].curr = value;
8b3c3104
AH		 283 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
284 if (err)
285 return 1;
286
18863bdd
AK		 287 if (!smsr->registered) {
288 smsr->urn.on_user_return = kvm_on_user_return;
289 user_return_notifier_register(&smsr->urn);
290 smsr->registered = true;
291 }
8b3c3104 292 return 0;
18863bdd
AK		 293}
294EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
295
13a34e06 296static void drop_user_return_notifiers(void)
3548bab5 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 300
301 if (smsr->registered)
302 kvm_on_user_return(&smsr->urn);
303}
304
6866b83e
CO		 305u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
306{
8a5a87d9 307 return vcpu->arch.apic_base;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_get_apic_base);
310
58cb628d
JK		 311int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
312{
313 u64 old_state = vcpu->arch.apic_base &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 new_state = msr_info->data &
316 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 317 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
318 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 319
d3802286
JM		 320 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
321 return 1;
58cb628d 322 if (!msr_info->host_initiated &&
d3802286 323 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 324 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
325 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
326 old_state == 0)))
327 return 1;
328
329 kvm_lapic_set_base(vcpu, msr_info->data);
330 return 0;
6866b83e
CO		 331}
332EXPORT_SYMBOL_GPL(kvm_set_apic_base);
333
2605fc21 334asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 335{
336 /* Fault while not rebooting. We want the trace. */
337 BUG();
338}
339EXPORT_SYMBOL_GPL(kvm_spurious_fault);
340
3fd28fce
ED		 341#define EXCPT_BENIGN 0
342#define EXCPT_CONTRIBUTORY 1
343#define EXCPT_PF 2
344
345static int exception_class(int vector)
346{
347 switch (vector) {
348 case PF_VECTOR:
349 return EXCPT_PF;
350 case DE_VECTOR:
351 case TS_VECTOR:
352 case NP_VECTOR:
353 case SS_VECTOR:
354 case GP_VECTOR:
355 return EXCPT_CONTRIBUTORY;
356 default:
357 break;
358 }
359 return EXCPT_BENIGN;
360}
361
d6e8c854
NA		 362#define EXCPT_FAULT 0
363#define EXCPT_TRAP 1
364#define EXCPT_ABORT 2
365#define EXCPT_INTERRUPT 3
366
367static int exception_type(int vector)
368{
369 unsigned int mask;
370
371 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
372 return EXCPT_INTERRUPT;
373
374 mask = 1 << vector;
375
376 /* #DB is trap, as instruction watchpoints are handled elsewhere */
377 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
378 return EXCPT_TRAP;
379
380 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
381 return EXCPT_ABORT;
382
383 /* Reserved exceptions will result in fault */
384 return EXCPT_FAULT;
385}
386
3fd28fce 387static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 388 unsigned nr, bool has_error, u32 error_code,
389 bool reinject)
3fd28fce
ED		 390{
391 u32 prev_nr;
392 int class1, class2;
393
3842d135
AK		 394 kvm_make_request(KVM_REQ_EVENT, vcpu);
395
664f8e26 396 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 397 queue:
3ffb2468
NA		 398 if (has_error && !is_protmode(vcpu))
399 has_error = false;
664f8e26
WL		 400 if (reinject) {
401 /*
402 * On vmentry, vcpu->arch.exception.pending is only
403 * true if an event injection was blocked by
404 * nested_run_pending. In that case, however,
405 * vcpu_enter_guest requests an immediate exit,
406 * and the guest shouldn't proceed far enough to
407 * need reinjection.
408 */
409 WARN_ON_ONCE(vcpu->arch.exception.pending);
410 vcpu->arch.exception.injected = true;
411 } else {
412 vcpu->arch.exception.pending = true;
413 vcpu->arch.exception.injected = false;
414 }
3fd28fce
ED		 415 vcpu->arch.exception.has_error_code = has_error;
416 vcpu->arch.exception.nr = nr;
417 vcpu->arch.exception.error_code = error_code;
418 return;
419 }
420
421 /* to check exception */
422 prev_nr = vcpu->arch.exception.nr;
423 if (prev_nr == DF_VECTOR) {
424 /* triple fault -> shutdown */
a8eeb04a 425 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 426 return;
427 }
428 class1 = exception_class(prev_nr);
429 class2 = exception_class(nr);
430 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
431 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 432 /*
433 * Generate double fault per SDM Table 5-5. Set
434 * exception.pending = true so that the double fault
435 * can trigger a nested vmexit.
436 */
3fd28fce 437 vcpu->arch.exception.pending = true;
664f8e26 438 vcpu->arch.exception.injected = false;
3fd28fce
ED		 439 vcpu->arch.exception.has_error_code = true;
440 vcpu->arch.exception.nr = DF_VECTOR;
441 vcpu->arch.exception.error_code = 0;
442 } else
443 /* replace previous exception with a new one in a hope
444 that instruction re-execution will regenerate lost
445 exception */
446 goto queue;
447}
448
298101da
AK		 449void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
450{
ce7ddec4 451 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 452}
453EXPORT_SYMBOL_GPL(kvm_queue_exception);
454
ce7ddec4
JR		 455void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
456{
457 kvm_multiple_exception(vcpu, nr, false, 0, true);
458}
459EXPORT_SYMBOL_GPL(kvm_requeue_exception);
460
6affcbed 461int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 462{
db8fcefa
AP		 463 if (err)
464 kvm_inject_gp(vcpu, 0);
465 else
6affcbed
KH		 466 return kvm_skip_emulated_instruction(vcpu);
467
468 return 1;
db8fcefa
AP		 469}
470EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 471
6389ee94 472void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 473{
474 ++vcpu->stat.pf_guest;
adfe20fb
WL		 475 vcpu->arch.exception.nested_apf =
476 is_guest_mode(vcpu) && fault->async_page_fault;
477 if (vcpu->arch.exception.nested_apf)
478 vcpu->arch.apf.nested_apf_token = fault->address;
479 else
480 vcpu->arch.cr2 = fault->address;
6389ee94 481 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 482}
27d6c865 483EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 484
ef54bcfe 485static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 486{
6389ee94
AK		 487 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
488 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 489 else
6389ee94 490 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 491
492 return fault->nested_page_fault;
d4f8cf66
JR		 493}
494
3419ffc8
SY		 495void kvm_inject_nmi(struct kvm_vcpu *vcpu)
496{
7460fb4a
AK		 497 atomic_inc(&vcpu->arch.nmi_queued);
498 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 499}
500EXPORT_SYMBOL_GPL(kvm_inject_nmi);
501
298101da
AK		 502void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
503{
ce7ddec4 504 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 505}
506EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
507
ce7ddec4
JR		 508void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
509{
510 kvm_multiple_exception(vcpu, nr, true, error_code, true);
511}
512EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
513
0a79b009
AK		 514/*
515 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
516 * a #GP and return false.
517 */
518bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 519{
0a79b009
AK		 520 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
521 return true;
522 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
523 return false;
298101da 524}
0a79b009 525EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 526
16f8a6f9
NA		 527bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
528{
529 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
530 return true;
531
532 kvm_queue_exception(vcpu, UD_VECTOR);
533 return false;
534}
535EXPORT_SYMBOL_GPL(kvm_require_dr);
536
ec92fe44
JR		 537/*
538 * This function will be used to read from the physical memory of the currently
54bf36aa 539 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 540 * can read from guest physical or from the guest's guest physical memory.
541 */
542int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
543 gfn_t ngfn, void *data, int offset, int len,
544 u32 access)
545{
54987b7a 546 struct x86_exception exception;
ec92fe44
JR		 547 gfn_t real_gfn;
548 gpa_t ngpa;
549
550 ngpa = gfn_to_gpa(ngfn);
54987b7a 551 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 552 if (real_gfn == UNMAPPED_GVA)
553 return -EFAULT;
554
555 real_gfn = gpa_to_gfn(real_gfn);
556
54bf36aa 557 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 558}
559EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
560
69b0049a 561static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 562 void *data, int offset, int len, u32 access)
563{
564 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
565 data, offset, len, access);
566}
567
a03490ed
CO		 568/*
569 * Load the pae pdptrs. Return true is they are all valid.
570 */
ff03a073 571int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 572{
573 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
574 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
575 int i;
576 int ret;
ff03a073 577 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 578
ff03a073
JR		 579 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
580 offset * sizeof(u64), sizeof(pdpte),
581 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 582 if (ret < 0) {
583 ret = 0;
584 goto out;
585 }
586 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 587 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 588 (pdpte[i] &
589 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 590 ret = 0;
591 goto out;
592 }
593 }
594 ret = 1;
595
ff03a073 596 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 597 __set_bit(VCPU_EXREG_PDPTR,
598 (unsigned long *)&vcpu->arch.regs_avail);
599 __set_bit(VCPU_EXREG_PDPTR,
600 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 601out:
a03490ed
CO		 602
603 return ret;
604}
cc4b6871 605EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 606
9ed38ffa 607bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 608{
ff03a073 609 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 610 bool changed = true;
3d06b8bf
JR		 611 int offset;
612 gfn_t gfn;
d835dfec
AK		 613 int r;
614
615 if (is_long_mode(vcpu) || !is_pae(vcpu))
616 return false;
617
6de4f3ad
AK		 618 if (!test_bit(VCPU_EXREG_PDPTR,
619 (unsigned long *)&vcpu->arch.regs_avail))
620 return true;
621
a512177e
PB		 622 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
623 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 624 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
625 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 626 if (r < 0)
627 goto out;
ff03a073 628 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 629out:
d835dfec
AK		 630
631 return changed;
632}
9ed38ffa 633EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 634
49a9b07e 635int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 636{
aad82703 637 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 638 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 639
f9a48e6a
AK		 640 cr0 |= X86_CR0_ET;
641
ab344828 642#ifdef CONFIG_X86_64
0f12244f
GN		 643 if (cr0 & 0xffffffff00000000UL)
644 return 1;
ab344828
GN		 645#endif
646
647 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 648
0f12244f
GN		 649 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
650 return 1;
a03490ed 651
0f12244f
GN		 652 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
653 return 1;
a03490ed
CO		 654
655 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
656#ifdef CONFIG_X86_64
f6801dff 657 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 658 int cs_db, cs_l;
659
0f12244f
GN		 660 if (!is_pae(vcpu))
661 return 1;
a03490ed 662 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 663 if (cs_l)
664 return 1;
a03490ed
CO		 665 } else
666#endif
ff03a073 667 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 668 kvm_read_cr3(vcpu)))
0f12244f 669 return 1;
a03490ed
CO		 670 }
671
ad756a16
MJ		 672 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
673 return 1;
674
a03490ed 675 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 676
d170c419 677 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 678 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 679 kvm_async_pf_hash_reset(vcpu);
680 }
e5f3f027 681
aad82703
SY		 682 if ((cr0 ^ old_cr0) & update_bits)
683 kvm_mmu_reset_context(vcpu);
b18d5431 684
879ae188
LE		 685 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
686 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
687 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 688 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
689
0f12244f
GN		 690 return 0;
691}
2d3ad1f4 692EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 693
2d3ad1f4 694void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 695{
49a9b07e 696 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 697}
2d3ad1f4 698EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 699
42bdf991
MT		 700static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
701{
702 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
703 !vcpu->guest_xcr0_loaded) {
704 /* kvm_set_xcr() also depends on this */
705 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
706 vcpu->guest_xcr0_loaded = 1;
707 }
708}
709
710static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
711{
712 if (vcpu->guest_xcr0_loaded) {
713 if (vcpu->arch.xcr0 != host_xcr0)
714 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
715 vcpu->guest_xcr0_loaded = 0;
716 }
717}
718
69b0049a 719static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 720{
56c103ec
LJ		 721 u64 xcr0 = xcr;
722 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 723 u64 valid_bits;
2acf923e
DC		 724
725 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
726 if (index != XCR_XFEATURE_ENABLED_MASK)
727 return 1;
d91cab78 728 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 729 return 1;
d91cab78 730 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 731 return 1;
46c34cb0
PB		 732
733 /*
734 * Do not allow the guest to set bits that we do not support
735 * saving. However, xcr0 bit 0 is always set, even if the
736 * emulated CPU does not support XSAVE (see fx_init).
737 */
d91cab78 738 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 739 if (xcr0 & ~valid_bits)
2acf923e 740 return 1;
46c34cb0 741
d91cab78
DH		 742 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
743 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 744 return 1;
745
d91cab78
DH		 746 if (xcr0 & XFEATURE_MASK_AVX512) {
747 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 748 return 1;
d91cab78 749 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 750 return 1;
751 }
2acf923e 752 vcpu->arch.xcr0 = xcr0;
56c103ec 753
d91cab78 754 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 755 kvm_update_cpuid(vcpu);
2acf923e
DC		 756 return 0;
757}
758
759int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
760{
764bcbc5
Z		 761 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
762 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 763 kvm_inject_gp(vcpu, 0);
764 return 1;
765 }
766 return 0;
767}
768EXPORT_SYMBOL_GPL(kvm_set_xcr);
769
a83b29c6 770int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 771{
fc78f519 772 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 773 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 774 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 775
0f12244f
GN		 776 if (cr4 & CR4_RESERVED_BITS)
777 return 1;
a03490ed 778
d6321d49 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 780 return 1;
781
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 783 return 1;
784
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 786 return 1;
787
d6321d49 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 789 return 1;
790
d6321d49 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 792 return 1;
793
fd8cb433 794 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 795 return 1;
796
ae3e61e1
PB		 797 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
798 return 1;
799
a03490ed 800 if (is_long_mode(vcpu)) {
0f12244f
GN		 801 if (!(cr4 & X86_CR4_PAE))
802 return 1;
a2edf57f
AK		 803 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
804 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 805 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
806 kvm_read_cr3(vcpu)))
0f12244f
GN		 807 return 1;
808
ad756a16 809 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 810 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 811 return 1;
812
813 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
814 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
815 return 1;
816 }
817
5e1746d6 818 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 819 return 1;
a03490ed 820
ad756a16
MJ		 821 if (((cr4 ^ old_cr4) & pdptr_bits) ||
822 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 823 kvm_mmu_reset_context(vcpu);
0f12244f 824
b9baba86 825 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 826 kvm_update_cpuid(vcpu);
2acf923e 827
0f12244f
GN		 828 return 0;
829}
2d3ad1f4 830EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 831
2390218b 832int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 833{
ac146235 834#ifdef CONFIG_X86_64
9d88fca7 835 cr3 &= ~CR3_PCID_INVD;
ac146235 836#endif
9d88fca7 837
9f8fe504 838 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 839 kvm_mmu_sync_roots(vcpu);
77c3913b 840 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 841 return 0;
d835dfec
AK		 842 }
843
d1cd3ce9
YZ		 844 if (is_long_mode(vcpu) &&
845 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
846 return 1;
847 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 848 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 849 return 1;
a03490ed 850
0f12244f 851 vcpu->arch.cr3 = cr3;
aff48baa 852 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 853 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 854 return 0;
855}
2d3ad1f4 856EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 857
eea1cff9 858int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 859{
0f12244f
GN		 860 if (cr8 & CR8_RESERVED_BITS)
861 return 1;
35754c98 862 if (lapic_in_kernel(vcpu))
a03490ed
CO		 863 kvm_lapic_set_tpr(vcpu, cr8);
864 else
ad312c7c 865 vcpu->arch.cr8 = cr8;
0f12244f
GN		 866 return 0;
867}
2d3ad1f4 868EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 869
2d3ad1f4 870unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 871{
35754c98 872 if (lapic_in_kernel(vcpu))
a03490ed
CO		 873 return kvm_lapic_get_cr8(vcpu);
874 else
ad312c7c 875 return vcpu->arch.cr8;
a03490ed 876}
2d3ad1f4 877EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 878
ae561ede
NA		 879static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
880{
881 int i;
882
883 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
884 for (i = 0; i < KVM_NR_DB_REGS; i++)
885 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
886 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
887 }
888}
889
73aaf249
JK		 890static void kvm_update_dr6(struct kvm_vcpu *vcpu)
891{
892 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
893 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
894}
895
c8639010
JK		 896static void kvm_update_dr7(struct kvm_vcpu *vcpu)
897{
898 unsigned long dr7;
899
900 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
901 dr7 = vcpu->arch.guest_debug_dr7;
902 else
903 dr7 = vcpu->arch.dr7;
904 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 905 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
906 if (dr7 & DR7_BP_EN_MASK)
907 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 908}
909
6f43ed01
NA		 910static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
911{
912 u64 fixed = DR6_FIXED_1;
913
d6321d49 914 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 915 fixed |= DR6_RTM;
916 return fixed;
917}
918
338dbc97 919static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 920{
921 switch (dr) {
922 case 0 ... 3:
923 vcpu->arch.db[dr] = val;
924 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
925 vcpu->arch.eff_db[dr] = val;
926 break;
927 case 4:
020df079
GN		 928 /* fall through */
929 case 6:
338dbc97
GN		 930 if (val & 0xffffffff00000000ULL)
931 return -1; /* #GP */
6f43ed01 932 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 933 kvm_update_dr6(vcpu);
020df079
GN		 934 break;
935 case 5:
020df079
GN		 936 /* fall through */
937 default: /* 7 */
338dbc97
GN		 938 if (val & 0xffffffff00000000ULL)
939 return -1; /* #GP */
020df079 940 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 941 kvm_update_dr7(vcpu);
020df079
GN		 942 break;
943 }
944
945 return 0;
946}
338dbc97
GN		 947
948int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
949{
16f8a6f9 950 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 951 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 952 return 1;
953 }
954 return 0;
338dbc97 955}
020df079
GN		 956EXPORT_SYMBOL_GPL(kvm_set_dr);
957
16f8a6f9 958int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 959{
960 switch (dr) {
961 case 0 ... 3:
962 *val = vcpu->arch.db[dr];
963 break;
964 case 4:
020df079
GN		 965 /* fall through */
966 case 6:
73aaf249
JK		 967 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
968 *val = vcpu->arch.dr6;
969 else
970 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 971 break;
972 case 5:
020df079
GN		 973 /* fall through */
974 default: /* 7 */
975 *val = vcpu->arch.dr7;
976 break;
977 }
338dbc97
GN		 978 return 0;
979}
020df079
GN		 980EXPORT_SYMBOL_GPL(kvm_get_dr);
981
022cd0e8
AK		 982bool kvm_rdpmc(struct kvm_vcpu *vcpu)
983{
984 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
985 u64 data;
986 int err;
987
c6702c9d 988 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 989 if (err)
990 return err;
991 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
992 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
993 return err;
994}
995EXPORT_SYMBOL_GPL(kvm_rdpmc);
996
043405e1
CO		 997/*
998 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
999 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1000 *
1001 * This list is modified at module load time to reflect the
e3267cbb 1002 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1003 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1004 * may depend on host virtualization features rather than host cpu features.
043405e1 1005 */
e3267cbb 1006
043405e1
CO		 1007static u32 msrs_to_save[] = {
1008 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1009 MSR_STAR,
043405e1
CO		 1010#ifdef CONFIG_X86_64
1011 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1012#endif
b3897a49 1013 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1014 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 1015};
1016
1017static unsigned num_msrs_to_save;
1018
62ef68bb
PB		 1019static u32 emulated_msrs[] = {
1020 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1021 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1022 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1023 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1024 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1025 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1026 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1027 HV_X64_MSR_RESET,
11c4b1ca 1028 HV_X64_MSR_VP_INDEX,
9eec50b8 1029 HV_X64_MSR_VP_RUNTIME,
5c919412 1030 HV_X64_MSR_SCONTROL,
1f4b34f8 1031 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1032 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1033 MSR_KVM_PV_EOI_EN,
1034
ba904635 1035 MSR_IA32_TSC_ADJUST,
a3e06bbe 1036 MSR_IA32_TSCDEADLINE,
043405e1 1037 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1038 MSR_IA32_MCG_STATUS,
1039 MSR_IA32_MCG_CTL,
c45dcc71 1040 MSR_IA32_MCG_EXT_CTL,
64d60670 1041 MSR_IA32_SMBASE,
52797bf9 1042 MSR_SMI_COUNT,
db2336a8
KH		 1043 MSR_PLATFORM_INFO,
1044 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1045};
1046
62ef68bb
PB		 1047static unsigned num_emulated_msrs;
1048
384bb783 1049bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1050{
b69e8cae 1051 if (efer & efer_reserved_bits)
384bb783 1052 return false;
15c4a640 1053
1b4d56b8 1054 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1055 return false;
1b2fd70c 1056
1b4d56b8 1057 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1058 return false;
d8017474 1059
384bb783
JK		 1060 return true;
1061}
1062EXPORT_SYMBOL_GPL(kvm_valid_efer);
1063
1064static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1065{
1066 u64 old_efer = vcpu->arch.efer;
1067
1068 if (!kvm_valid_efer(vcpu, efer))
1069 return 1;
1070
1071 if (is_paging(vcpu)
1072 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1073 return 1;
1074
15c4a640 1075 efer &= ~EFER_LMA;
f6801dff 1076 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1077
a3d204e2
SY		 1078 kvm_x86_ops->set_efer(vcpu, efer);
1079
aad82703
SY		 1080 /* Update reserved bits */
1081 if ((efer ^ old_efer) & EFER_NX)
1082 kvm_mmu_reset_context(vcpu);
1083
b69e8cae 1084 return 0;
15c4a640
CO		 1085}
1086
f2b4b7dd
JR		 1087void kvm_enable_efer_bits(u64 mask)
1088{
1089 efer_reserved_bits &= ~mask;
1090}
1091EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1092
15c4a640
CO		 1093/*
1094 * Writes msr value into into the appropriate "register".
1095 * Returns 0 on success, non-0 otherwise.
1096 * Assumes vcpu_load() was already called.
1097 */
8fe8ab46 1098int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1099{
854e8bb1
NA		 1100 switch (msr->index) {
1101 case MSR_FS_BASE:
1102 case MSR_GS_BASE:
1103 case MSR_KERNEL_GS_BASE:
1104 case MSR_CSTAR:
1105 case MSR_LSTAR:
fd8cb433 1106 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1107 return 1;
1108 break;
1109 case MSR_IA32_SYSENTER_EIP:
1110 case MSR_IA32_SYSENTER_ESP:
1111 /*
1112 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1113 * non-canonical address is written on Intel but not on
1114 * AMD (which ignores the top 32-bits, because it does
1115 * not implement 64-bit SYSENTER).
1116 *
1117 * 64-bit code should hence be able to write a non-canonical
1118 * value on AMD. Making the address canonical ensures that
1119 * vmentry does not fail on Intel after writing a non-canonical
1120 * value, and that something deterministic happens if the guest
1121 * invokes 64-bit SYSENTER.
1122 */
fd8cb433 1123 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1124 }
8fe8ab46 1125 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1126}
854e8bb1 1127EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1128
313a3dc7
CO		 1129/*
1130 * Adapt set_msr() to msr_io()'s calling convention
1131 */
609e36d3
PB		 1132static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1133{
1134 struct msr_data msr;
1135 int r;
1136
1137 msr.index = index;
1138 msr.host_initiated = true;
1139 r = kvm_get_msr(vcpu, &msr);
1140 if (r)
1141 return r;
1142
1143 *data = msr.data;
1144 return 0;
1145}
1146
313a3dc7
CO		 1147static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1148{
8fe8ab46
WA		 1149 struct msr_data msr;
1150
1151 msr.data = *data;
1152 msr.index = index;
1153 msr.host_initiated = true;
1154 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1155}
1156
16e8d74d
MT		 1157#ifdef CONFIG_X86_64
1158struct pvclock_gtod_data {
1159 seqcount_t seq;
1160
1161 struct { /* extract of a clocksource struct */
1162 int vclock_mode;
a5a1d1c2
TG		 1163 u64 cycle_last;
1164 u64 mask;
16e8d74d
MT		 1165 u32 mult;
1166 u32 shift;
1167 } clock;
1168
cbcf2dd3
TG		 1169 u64 boot_ns;
1170 u64 nsec_base;
55dd00a7 1171 u64 wall_time_sec;
16e8d74d
MT		 1172};
1173
1174static struct pvclock_gtod_data pvclock_gtod_data;
1175
1176static void update_pvclock_gtod(struct timekeeper *tk)
1177{
1178 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1179 u64 boot_ns;
1180
876e7881 1181 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1182
1183 write_seqcount_begin(&vdata->seq);
1184
1185 /* copy pvclock gtod data */
876e7881
PZ		 1186 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1187 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1188 vdata->clock.mask = tk->tkr_mono.mask;
1189 vdata->clock.mult = tk->tkr_mono.mult;
1190 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1191
cbcf2dd3 1192 vdata->boot_ns = boot_ns;
876e7881 1193 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1194
55dd00a7
MT		 1195 vdata->wall_time_sec = tk->xtime_sec;
1196
16e8d74d
MT		 1197 write_seqcount_end(&vdata->seq);
1198}
1199#endif
1200
bab5bb39
NK		 1201void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1202{
1203 /*
1204 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1205 * vcpu_enter_guest. This function is only called from
1206 * the physical CPU that is running vcpu.
1207 */
1208 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1209}
16e8d74d 1210
18068523
GOC		 1211static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1212{
9ed3c444
AK		 1213 int version;
1214 int r;
50d0a0f9 1215 struct pvclock_wall_clock wc;
87aeb54f 1216 struct timespec64 boot;
18068523
GOC		 1217
1218 if (!wall_clock)
1219 return;
1220
9ed3c444
AK		 1221 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1222 if (r)
1223 return;
1224
1225 if (version & 1)
1226 ++version; /* first time write, random junk */
1227
1228 ++version;
18068523 1229
1dab1345
NK		 1230 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1231 return;
18068523 1232
50d0a0f9
GH		 1233 /*
1234 * The guest calculates current wall clock time by adding
34c238a1 1235 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1236 * wall clock specified here. guest system time equals host
1237 * system time for us, thus we must fill in host boot time here.
1238 */
87aeb54f 1239 getboottime64(&boot);
50d0a0f9 1240
4b648665 1241 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1242 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1243 boot = timespec64_sub(boot, ts);
4b648665 1244 }
87aeb54f 1245 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1246 wc.nsec = boot.tv_nsec;
1247 wc.version = version;
18068523
GOC		 1248
1249 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1250
1251 version++;
1252 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1253}
1254
50d0a0f9
GH		 1255static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1256{
b51012de
PB		 1257 do_shl32_div32(dividend, divisor);
1258 return dividend;
50d0a0f9
GH		 1259}
1260
3ae13faa 1261static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1262 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1263{
5f4e3f88 1264 uint64_t scaled64;
50d0a0f9
GH		 1265 int32_t shift = 0;
1266 uint64_t tps64;
1267 uint32_t tps32;
1268
3ae13faa
PB		 1269 tps64 = base_hz;
1270 scaled64 = scaled_hz;
50933623 1271 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1272 tps64 >>= 1;
1273 shift--;
1274 }
1275
1276 tps32 = (uint32_t)tps64;
50933623
JK		 1277 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1278 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1279 scaled64 >>= 1;
1280 else
1281 tps32 <<= 1;
50d0a0f9
GH		 1282 shift++;
1283 }
1284
5f4e3f88
ZA		 1285 *pshift = shift;
1286 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1287
3ae13faa
PB		 1288 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1289 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1290}
1291
d828199e 1292#ifdef CONFIG_X86_64
16e8d74d 1293static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1294#endif
16e8d74d 1295
c8076604 1296static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1297static unsigned long max_tsc_khz;
c8076604 1298
cc578287 1299static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1300{
cc578287
ZA		 1301 u64 v = (u64)khz * (1000000 + ppm);
1302 do_div(v, 1000000);
1303 return v;
1e993611
JR		 1304}
1305
381d585c
HZ		 1306static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1307{
1308 u64 ratio;
1309
1310 /* Guest TSC same frequency as host TSC? */
1311 if (!scale) {
1312 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1313 return 0;
1314 }
1315
1316 /* TSC scaling supported? */
1317 if (!kvm_has_tsc_control) {
1318 if (user_tsc_khz > tsc_khz) {
1319 vcpu->arch.tsc_catchup = 1;
1320 vcpu->arch.tsc_always_catchup = 1;
1321 return 0;
1322 } else {
1323 WARN(1, "user requested TSC rate below hardware speed\n");
1324 return -1;
1325 }
1326 }
1327
1328 /* TSC scaling required - calculate ratio */
1329 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1330 user_tsc_khz, tsc_khz);
1331
1332 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1333 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1334 user_tsc_khz);
1335 return -1;
1336 }
1337
1338 vcpu->arch.tsc_scaling_ratio = ratio;
1339 return 0;
1340}
1341
4941b8cb 1342static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1343{
cc578287
ZA		 1344 u32 thresh_lo, thresh_hi;
1345 int use_scaling = 0;
217fc9cf 1346
03ba32ca 1347 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1348 if (user_tsc_khz == 0) {
ad721883
HZ		 1349 /* set tsc_scaling_ratio to a safe value */
1350 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1351 return -1;
ad721883 1352 }
03ba32ca 1353
c285545f 1354 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1355 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1356 &vcpu->arch.virtual_tsc_shift,
1357 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1358 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1359
1360 /*
1361 * Compute the variation in TSC rate which is acceptable
1362 * within the range of tolerance and decide if the
1363 * rate being applied is within that bounds of the hardware
1364 * rate. If so, no scaling or compensation need be done.
1365 */
1366 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1367 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1368 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1369 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1370 use_scaling = 1;
1371 }
4941b8cb 1372 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1373}
1374
1375static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1376{
e26101b1 1377 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1378 vcpu->arch.virtual_tsc_mult,
1379 vcpu->arch.virtual_tsc_shift);
e26101b1 1380 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1381 return tsc;
1382}
1383
69b0049a 1384static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1385{
1386#ifdef CONFIG_X86_64
1387 bool vcpus_matched;
b48aa97e
MT		 1388 struct kvm_arch *ka = &vcpu->kvm->arch;
1389 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1390
1391 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1392 atomic_read(&vcpu->kvm->online_vcpus));
1393
7f187922
MT		 1394 /*
1395 * Once the masterclock is enabled, always perform request in
1396 * order to update it.
1397 *
1398 * In order to enable masterclock, the host clocksource must be TSC
1399 * and the vcpus need to have matched TSCs. When that happens,
1400 * perform request to enable masterclock.
1401 */
1402 if (ka->use_master_clock ||
1403 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1404 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1405
1406 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1407 atomic_read(&vcpu->kvm->online_vcpus),
1408 ka->use_master_clock, gtod->clock.vclock_mode);
1409#endif
1410}
1411
ba904635
WA		 1412static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1413{
3e3f5026 1414 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1415 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1416}
1417
35181e86
HZ		 1418/*
1419 * Multiply tsc by a fixed point number represented by ratio.
1420 *
1421 * The most significant 64-N bits (mult) of ratio represent the
1422 * integral part of the fixed point number; the remaining N bits
1423 * (frac) represent the fractional part, ie. ratio represents a fixed
1424 * point number (mult + frac * 2^(-N)).
1425 *
1426 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1427 */
1428static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1429{
1430 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1431}
1432
1433u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1434{
1435 u64 _tsc = tsc;
1436 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1437
1438 if (ratio != kvm_default_tsc_scaling_ratio)
1439 _tsc = __scale_tsc(ratio, tsc);
1440
1441 return _tsc;
1442}
1443EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1444
07c1419a
HZ		 1445static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1446{
1447 u64 tsc;
1448
1449 tsc = kvm_scale_tsc(vcpu, rdtsc());
1450
1451 return target_tsc - tsc;
1452}
1453
4ba76538
HZ		 1454u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1455{
ea26e4ec 1456 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1457}
1458EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1459
a545ab6a
LC		 1460static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1461{
1462 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1463 vcpu->arch.tsc_offset = offset;
1464}
1465
8fe8ab46 1466void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1467{
1468 struct kvm *kvm = vcpu->kvm;
f38e098f 1469 u64 offset, ns, elapsed;
99e3e30a 1470 unsigned long flags;
b48aa97e 1471 bool matched;
0d3da0d2 1472 bool already_matched;
8fe8ab46 1473 u64 data = msr->data;
c5e8ec8e 1474 bool synchronizing = false;
99e3e30a 1475
038f8c11 1476 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1477 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1478 ns = ktime_get_boot_ns();
f38e098f 1479 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1480
03ba32ca 1481 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1482 if (data == 0 && msr->host_initiated) {
1483 /*
1484 * detection of vcpu initialization -- need to sync
1485 * with other vCPUs. This particularly helps to keep
1486 * kvm_clock stable after CPU hotplug
1487 */
1488 synchronizing = true;
1489 } else {
1490 u64 tsc_exp = kvm->arch.last_tsc_write +
1491 nsec_to_cycles(vcpu, elapsed);
1492 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1493 /*
1494 * Special case: TSC write with a small delta (1 second)
1495 * of virtual cycle time against real time is
1496 * interpreted as an attempt to synchronize the CPU.
1497 */
1498 synchronizing = data < tsc_exp + tsc_hz &&
1499 data + tsc_hz > tsc_exp;
1500 }
c5e8ec8e 1501 }
f38e098f
ZA		 1502
1503 /*
5d3cb0f6
ZA		 1504 * For a reliable TSC, we can match TSC offsets, and for an unstable
1505 * TSC, we add elapsed time in this computation. We could let the
1506 * compensation code attempt to catch up if we fall behind, but
1507 * it's better to try to match offsets from the beginning.
1508 */
c5e8ec8e 1509 if (synchronizing &&
5d3cb0f6 1510 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1511 if (!check_tsc_unstable()) {
e26101b1 1512 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1513 pr_debug("kvm: matched tsc offset for %llu\n", data);
1514 } else {
857e4099 1515 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1516 data += delta;
07c1419a 1517 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1518 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1519 }
b48aa97e 1520 matched = true;
0d3da0d2 1521 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1522 } else {
1523 /*
1524 * We split periods of matched TSC writes into generations.
1525 * For each generation, we track the original measured
1526 * nanosecond time, offset, and write, so if TSCs are in
1527 * sync, we can match exact offset, and if not, we can match
4a969980 1528 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1529 *
1530 * These values are tracked in kvm->arch.cur_xxx variables.
1531 */
1532 kvm->arch.cur_tsc_generation++;
1533 kvm->arch.cur_tsc_nsec = ns;
1534 kvm->arch.cur_tsc_write = data;
1535 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1536 matched = false;
0d3da0d2 1537 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1538 kvm->arch.cur_tsc_generation, data);
f38e098f 1539 }
e26101b1
ZA		 1540
1541 /*
1542 * We also track th most recent recorded KHZ, write and time to
1543 * allow the matching interval to be extended at each write.
1544 */
f38e098f
ZA		 1545 kvm->arch.last_tsc_nsec = ns;
1546 kvm->arch.last_tsc_write = data;
5d3cb0f6 1547 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1548
b183aa58 1549 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1550
1551 /* Keep track of which generation this VCPU has synchronized to */
1552 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1553 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1554 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1555
d6321d49 1556 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1557 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1558
a545ab6a 1559 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1560 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1561
1562 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1563 if (!matched) {
b48aa97e 1564 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1565 } else if (!already_matched) {
1566 kvm->arch.nr_vcpus_matched_tsc++;
1567 }
b48aa97e
MT		 1568
1569 kvm_track_tsc_matching(vcpu);
1570 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1571}
e26101b1 1572
99e3e30a
ZA		 1573EXPORT_SYMBOL_GPL(kvm_write_tsc);
1574
58ea6767
HZ		 1575static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1576 s64 adjustment)
1577{
ea26e4ec 1578 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1579}
1580
1581static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1582{
1583 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1584 WARN_ON(adjustment < 0);
1585 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1586 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1587}
1588
d828199e
MT		 1589#ifdef CONFIG_X86_64
1590
a5a1d1c2 1591static u64 read_tsc(void)
d828199e 1592{
a5a1d1c2 1593 u64 ret = (u64)rdtsc_ordered();
03b9730b 1594 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1595
1596 if (likely(ret >= last))
1597 return ret;
1598
1599 /*
1600 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1601 * predictable (it's just a function of time and the likely is
d828199e
MT		 1602 * very likely) and there's a data dependence, so force GCC
1603 * to generate a branch instead. I don't barrier() because
1604 * we don't actually need a barrier, and if this function
1605 * ever gets inlined it will generate worse code.
1606 */
1607 asm volatile ("");
1608 return last;
1609}
1610
a5a1d1c2 1611static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1612{
1613 long v;
1614 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1615
1616 *cycle_now = read_tsc();
1617
1618 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1619 return v * gtod->clock.mult;
1620}
1621
a5a1d1c2 1622static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1623{
cbcf2dd3 1624 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1625 unsigned long seq;
d828199e 1626 int mode;
cbcf2dd3 1627 u64 ns;
d828199e 1628
d828199e
MT		 1629 do {
1630 seq = read_seqcount_begin(&gtod->seq);
1631 mode = gtod->clock.vclock_mode;
cbcf2dd3 1632 ns = gtod->nsec_base;
d828199e
MT		 1633 ns += vgettsc(cycle_now);
1634 ns >>= gtod->clock.shift;
cbcf2dd3 1635 ns += gtod->boot_ns;
d828199e 1636 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1637 *t = ns;
d828199e
MT		 1638
1639 return mode;
1640}
1641
55dd00a7
MT		 1642static int do_realtime(struct timespec *ts, u64 *cycle_now)
1643{
1644 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1645 unsigned long seq;
1646 int mode;
1647 u64 ns;
1648
1649 do {
1650 seq = read_seqcount_begin(&gtod->seq);
1651 mode = gtod->clock.vclock_mode;
1652 ts->tv_sec = gtod->wall_time_sec;
1653 ns = gtod->nsec_base;
1654 ns += vgettsc(cycle_now);
1655 ns >>= gtod->clock.shift;
1656 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1657
1658 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1659 ts->tv_nsec = ns;
1660
1661 return mode;
1662}
1663
d828199e 1664/* returns true if host is using tsc clocksource */
a5a1d1c2 1665static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1666{
d828199e
MT		 1667 /* checked again under seqlock below */
1668 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1669 return false;
1670
cbcf2dd3 1671 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1672}
55dd00a7
MT		 1673
1674/* returns true if host is using tsc clocksource */
1675static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1676 u64 *cycle_now)
1677{
1678 /* checked again under seqlock below */
1679 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1680 return false;
1681
1682 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1683}
d828199e
MT		 1684#endif
1685
1686/*
1687 *
b48aa97e
MT		 1688 * Assuming a stable TSC across physical CPUS, and a stable TSC
1689 * across virtual CPUs, the following condition is possible.
1690 * Each numbered line represents an event visible to both
d828199e
MT		 1691 * CPUs at the next numbered event.
1692 *
1693 * "timespecX" represents host monotonic time. "tscX" represents
1694 * RDTSC value.
1695 *
1696 * VCPU0 on CPU0 | VCPU1 on CPU1
1697 *
1698 * 1. read timespec0,tsc0
1699 * 2. | timespec1 = timespec0 + N
1700 * | tsc1 = tsc0 + M
1701 * 3. transition to guest | transition to guest
1702 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1703 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1704 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1705 *
1706 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1707 *
1708 * - ret0 < ret1
1709 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1710 * ...
1711 * - 0 < N - M => M < N
1712 *
1713 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1714 * always the case (the difference between two distinct xtime instances
1715 * might be smaller then the difference between corresponding TSC reads,
1716 * when updating guest vcpus pvclock areas).
1717 *
1718 * To avoid that problem, do not allow visibility of distinct
1719 * system_timestamp/tsc_timestamp values simultaneously: use a master
1720 * copy of host monotonic time values. Update that master copy
1721 * in lockstep.
1722 *
b48aa97e 1723 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1724 *
1725 */
1726
1727static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1728{
1729#ifdef CONFIG_X86_64
1730 struct kvm_arch *ka = &kvm->arch;
1731 int vclock_mode;
b48aa97e
MT		 1732 bool host_tsc_clocksource, vcpus_matched;
1733
1734 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1735 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1736
1737 /*
1738 * If the host uses TSC clock, then passthrough TSC as stable
1739 * to the guest.
1740 */
b48aa97e 1741 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1742 &ka->master_kernel_ns,
1743 &ka->master_cycle_now);
1744
16a96021 1745 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1746 && !ka->backwards_tsc_observed
54750f2c 1747 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1748
d828199e
MT		 1749 if (ka->use_master_clock)
1750 atomic_set(&kvm_guest_has_master_clock, 1);
1751
1752 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1753 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1754 vcpus_matched);
d828199e
MT		 1755#endif
1756}
1757
2860c4b1
PB		 1758void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1759{
1760 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1761}
1762
2e762ff7
MT		 1763static void kvm_gen_update_masterclock(struct kvm *kvm)
1764{
1765#ifdef CONFIG_X86_64
1766 int i;
1767 struct kvm_vcpu *vcpu;
1768 struct kvm_arch *ka = &kvm->arch;
1769
1770 spin_lock(&ka->pvclock_gtod_sync_lock);
1771 kvm_make_mclock_inprogress_request(kvm);
1772 /* no guest entries from this point */
1773 pvclock_update_vm_gtod_copy(kvm);
1774
1775 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1776 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1777
1778 /* guest entries allowed */
1779 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1780 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1781
1782 spin_unlock(&ka->pvclock_gtod_sync_lock);
1783#endif
1784}
1785
e891a32e 1786u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1787{
108b249c 1788 struct kvm_arch *ka = &kvm->arch;
8b953440 1789 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1790 u64 ret;
108b249c 1791
8b953440
PB		 1792 spin_lock(&ka->pvclock_gtod_sync_lock);
1793 if (!ka->use_master_clock) {
1794 spin_unlock(&ka->pvclock_gtod_sync_lock);
1795 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1796 }
1797
8b953440
PB		 1798 hv_clock.tsc_timestamp = ka->master_cycle_now;
1799 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1800 spin_unlock(&ka->pvclock_gtod_sync_lock);
1801
e2c2206a
WL		 1802 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1803 get_cpu();
1804
e70b57a6
WL		 1805 if (__this_cpu_read(cpu_tsc_khz)) {
1806 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1807 &hv_clock.tsc_shift,
1808 &hv_clock.tsc_to_system_mul);
1809 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1810 } else
1811 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1812
1813 put_cpu();
1814
1815 return ret;
108b249c
PB		 1816}
1817
0d6dd2ff
PB		 1818static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1819{
1820 struct kvm_vcpu_arch *vcpu = &v->arch;
1821 struct pvclock_vcpu_time_info guest_hv_clock;
1822
4e335d9e 1823 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1824 &guest_hv_clock, sizeof(guest_hv_clock))))
1825 return;
1826
1827 /* This VCPU is paused, but it's legal for a guest to read another
1828 * VCPU's kvmclock, so we really have to follow the specification where
1829 * it says that version is odd if data is being modified, and even after
1830 * it is consistent.
1831 *
1832 * Version field updates must be kept separate. This is because
1833 * kvm_write_guest_cached might use a "rep movs" instruction, and
1834 * writes within a string instruction are weakly ordered. So there
1835 * are three writes overall.
1836 *
1837 * As a small optimization, only write the version field in the first
1838 * and third write. The vcpu->pv_time cache is still valid, because the
1839 * version field is the first in the struct.
1840 */
1841 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1842
51c4b8bb
LA		 1843 if (guest_hv_clock.version & 1)
1844 ++guest_hv_clock.version; /* first time write, random junk */
1845
0d6dd2ff 1846 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1847 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1848 &vcpu->hv_clock,
1849 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1850
1851 smp_wmb();
1852
1853 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1854 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1855
1856 if (vcpu->pvclock_set_guest_stopped_request) {
1857 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1858 vcpu->pvclock_set_guest_stopped_request = false;
1859 }
1860
1861 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1862
4e335d9e
PB		 1863 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1864 &vcpu->hv_clock,
1865 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1866
1867 smp_wmb();
1868
1869 vcpu->hv_clock.version++;
4e335d9e
PB		 1870 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1871 &vcpu->hv_clock,
1872 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1873}
1874
34c238a1 1875static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1876{
78db6a50 1877 unsigned long flags, tgt_tsc_khz;
18068523 1878 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1879 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1880 s64 kernel_ns;
d828199e 1881 u64 tsc_timestamp, host_tsc;
51d59c6b 1882 u8 pvclock_flags;
d828199e
MT		 1883 bool use_master_clock;
1884
1885 kernel_ns = 0;
1886 host_tsc = 0;
18068523 1887
d828199e
MT		 1888 /*
1889 * If the host uses TSC clock, then passthrough TSC as stable
1890 * to the guest.
1891 */
1892 spin_lock(&ka->pvclock_gtod_sync_lock);
1893 use_master_clock = ka->use_master_clock;
1894 if (use_master_clock) {
1895 host_tsc = ka->master_cycle_now;
1896 kernel_ns = ka->master_kernel_ns;
1897 }
1898 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1899
1900 /* Keep irq disabled to prevent changes to the clock */
1901 local_irq_save(flags);
78db6a50
PB		 1902 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1903 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1904 local_irq_restore(flags);
1905 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1906 return 1;
1907 }
d828199e 1908 if (!use_master_clock) {
4ea1636b 1909 host_tsc = rdtsc();
108b249c 1910 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1911 }
1912
4ba76538 1913 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1914
c285545f
ZA		 1915 /*
1916 * We may have to catch up the TSC to match elapsed wall clock
1917 * time for two reasons, even if kvmclock is used.
1918 * 1) CPU could have been running below the maximum TSC rate
1919 * 2) Broken TSC compensation resets the base at each VCPU
1920 * entry to avoid unknown leaps of TSC even when running
1921 * again on the same CPU. This may cause apparent elapsed
1922 * time to disappear, and the guest to stand still or run
1923 * very slowly.
1924 */
1925 if (vcpu->tsc_catchup) {
1926 u64 tsc = compute_guest_tsc(v, kernel_ns);
1927 if (tsc > tsc_timestamp) {
f1e2b260 1928 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1929 tsc_timestamp = tsc;
1930 }
50d0a0f9
GH		 1931 }
1932
18068523
GOC		 1933 local_irq_restore(flags);
1934
0d6dd2ff 1935 /* With all the info we got, fill in the values */
18068523 1936
78db6a50
PB		 1937 if (kvm_has_tsc_control)
1938 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1939
1940 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1941 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1942 &vcpu->hv_clock.tsc_shift,
1943 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1944 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1945 }
1946
1d5f066e 1947 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1948 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1949 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1950
d828199e 1951 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1952 pvclock_flags = 0;
d828199e
MT		 1953 if (use_master_clock)
1954 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1955
78c0337a
MT		 1956 vcpu->hv_clock.flags = pvclock_flags;
1957
095cf55d
PB		 1958 if (vcpu->pv_time_enabled)
1959 kvm_setup_pvclock_page(v);
1960 if (v == kvm_get_vcpu(v->kvm, 0))
1961 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1962 return 0;
c8076604
GH		 1963}
1964
0061d53d
MT		 1965/*
1966 * kvmclock updates which are isolated to a given vcpu, such as
1967 * vcpu->cpu migration, should not allow system_timestamp from
1968 * the rest of the vcpus to remain static. Otherwise ntp frequency
1969 * correction applies to one vcpu's system_timestamp but not
1970 * the others.
1971 *
1972 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1973 * We need to rate-limit these requests though, as they can
1974 * considerably slow guests that have a large number of vcpus.
1975 * The time for a remote vcpu to update its kvmclock is bound
1976 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1977 */
1978
7e44e449
AJ		 1979#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1980
1981static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1982{
1983 int i;
7e44e449
AJ		 1984 struct delayed_work *dwork = to_delayed_work(work);
1985 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1986 kvmclock_update_work);
1987 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1988 struct kvm_vcpu *vcpu;
1989
1990 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1991 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1992 kvm_vcpu_kick(vcpu);
1993 }
1994}
1995
7e44e449
AJ		 1996static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1997{
1998 struct kvm *kvm = v->kvm;
1999
105b21bb 2000 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2001 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2002 KVMCLOCK_UPDATE_DELAY);
2003}
2004
332967a3
AJ		 2005#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2006
2007static void kvmclock_sync_fn(struct work_struct *work)
2008{
2009 struct delayed_work *dwork = to_delayed_work(work);
2010 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2011 kvmclock_sync_work);
2012 struct kvm *kvm = container_of(ka, struct kvm, arch);
2013
630994b3
MT		 2014 if (!kvmclock_periodic_sync)
2015 return;
2016
332967a3
AJ		 2017 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2018 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2019 KVMCLOCK_SYNC_PERIOD);
2020}
2021
9ffd986c 2022static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2023{
890ca9ae
HY		 2024 u64 mcg_cap = vcpu->arch.mcg_cap;
2025 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2026 u32 msr = msr_info->index;
2027 u64 data = msr_info->data;
890ca9ae 2028
15c4a640 2029 switch (msr) {
15c4a640 2030 case MSR_IA32_MCG_STATUS:
890ca9ae 2031 vcpu->arch.mcg_status = data;
15c4a640 2032 break;
c7ac679c 2033 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2034 if (!(mcg_cap & MCG_CTL_P))
2035 return 1;
2036 if (data != 0 && data != ~(u64)0)
2037 return -1;
2038 vcpu->arch.mcg_ctl = data;
2039 break;
2040 default:
2041 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2042 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2043 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2044 /* only 0 or all 1s can be written to IA32_MCi_CTL
2045 * some Linux kernels though clear bit 10 in bank 4 to
2046 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2047 * this to avoid an uncatched #GP in the guest
2048 */
890ca9ae 2049 if ((offset & 0x3) == 0 &&
114be429 2050 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2051 return -1;
9ffd986c
WL		 2052 if (!msr_info->host_initiated &&
2053 (offset & 0x3) == 1 && data != 0)
2054 return -1;
890ca9ae
HY		 2055 vcpu->arch.mce_banks[offset] = data;
2056 break;
2057 }
2058 return 1;
2059 }
2060 return 0;
2061}
2062
ffde22ac
ES		 2063static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2064{
2065 struct kvm *kvm = vcpu->kvm;
2066 int lm = is_long_mode(vcpu);
2067 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2068 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2069 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2070 : kvm->arch.xen_hvm_config.blob_size_32;
2071 u32 page_num = data & ~PAGE_MASK;
2072 u64 page_addr = data & PAGE_MASK;
2073 u8 *page;
2074 int r;
2075
2076 r = -E2BIG;
2077 if (page_num >= blob_size)
2078 goto out;
2079 r = -ENOMEM;
ff5c2c03
SL		 2080 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2081 if (IS_ERR(page)) {
2082 r = PTR_ERR(page);
ffde22ac 2083 goto out;
ff5c2c03 2084 }
54bf36aa 2085 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2086 goto out_free;
2087 r = 0;
2088out_free:
2089 kfree(page);
2090out:
2091 return r;
2092}
2093
344d9588
GN		 2094static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2095{
2096 gpa_t gpa = data & ~0x3f;
2097
52a5c155
WL		 2098 /* Bits 3:5 are reserved, Should be zero */
2099 if (data & 0x38)
344d9588
GN		 2100 return 1;
2101
2102 vcpu->arch.apf.msr_val = data;
2103
2104 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2105 kvm_clear_async_pf_completion_queue(vcpu);
2106 kvm_async_pf_hash_reset(vcpu);
2107 return 0;
2108 }
2109
4e335d9e 2110 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2111 sizeof(u32)))
344d9588
GN		 2112 return 1;
2113
6adba527 2114 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2115 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2116 kvm_async_pf_wakeup_all(vcpu);
2117 return 0;
2118}
2119
12f9a48f
GC		 2120static void kvmclock_reset(struct kvm_vcpu *vcpu)
2121{
0b79459b 2122 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2123}
2124
c9aaa895
GC		 2125static void record_steal_time(struct kvm_vcpu *vcpu)
2126{
2127 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2128 return;
2129
4e335d9e 2130 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2131 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2132 return;
2133
0b9f6c46
PX		 2134 vcpu->arch.st.steal.preempted = 0;
2135
35f3fae1
WL		 2136 if (vcpu->arch.st.steal.version & 1)
2137 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2138
2139 vcpu->arch.st.steal.version += 1;
2140
4e335d9e 2141 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2142 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2143
2144 smp_wmb();
2145
c54cdf14
LC		 2146 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2147 vcpu->arch.st.last_steal;
2148 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2149
4e335d9e 2150 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2151 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2152
2153 smp_wmb();
2154
2155 vcpu->arch.st.steal.version += 1;
c9aaa895 2156
4e335d9e 2157 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2158 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2159}
2160
8fe8ab46 2161int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2162{
5753785f 2163 bool pr = false;
8fe8ab46
WA		 2164 u32 msr = msr_info->index;
2165 u64 data = msr_info->data;
5753785f 2166
15c4a640 2167 switch (msr) {
2e32b719
BP		 2168 case MSR_AMD64_NB_CFG:
2169 case MSR_IA32_UCODE_REV:
2170 case MSR_IA32_UCODE_WRITE:
2171 case MSR_VM_HSAVE_PA:
2172 case MSR_AMD64_PATCH_LOADER:
2173 case MSR_AMD64_BU_CFG2:
405a353a 2174 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2175 break;
2176
15c4a640 2177 case MSR_EFER:
b69e8cae 2178 return set_efer(vcpu, data);
8f1589d9
AP		 2179 case MSR_K7_HWCR:
2180 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2181 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2182 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2183 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2184 if (data != 0) {
a737f256
CD		 2185 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2186 data);
8f1589d9
AP		 2187 return 1;
2188 }
15c4a640 2189 break;
f7c6d140
AP		 2190 case MSR_FAM10H_MMIO_CONF_BASE:
2191 if (data != 0) {
a737f256
CD		 2192 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2193 "0x%llx\n", data);
f7c6d140
AP		 2194 return 1;
2195 }
15c4a640 2196 break;
b5e2fec0
AG		 2197 case MSR_IA32_DEBUGCTLMSR:
2198 if (!data) {
2199 /* We support the non-activated case already */
2200 break;
2201 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2202 /* Values other than LBR and BTF are vendor-specific,
2203 thus reserved and should throw a #GP */
2204 return 1;
2205 }
a737f256
CD		 2206 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2207 __func__, data);
b5e2fec0 2208 break;
9ba075a6 2209 case 0x200 ... 0x2ff:
ff53604b 2210 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2211 case MSR_IA32_APICBASE:
58cb628d 2212 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2213 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2214 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2215 case MSR_IA32_TSCDEADLINE:
2216 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2217 break;
ba904635 2218 case MSR_IA32_TSC_ADJUST:
d6321d49 2219 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2220 if (!msr_info->host_initiated) {
d913b904 2221 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2222 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2223 }
2224 vcpu->arch.ia32_tsc_adjust_msr = data;
2225 }
2226 break;
15c4a640 2227 case MSR_IA32_MISC_ENABLE:
ad312c7c 2228 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2229 break;
64d60670
PB		 2230 case MSR_IA32_SMBASE:
2231 if (!msr_info->host_initiated)
2232 return 1;
2233 vcpu->arch.smbase = data;
2234 break;
52797bf9
LA		 2235 case MSR_SMI_COUNT:
2236 if (!msr_info->host_initiated)
2237 return 1;
2238 vcpu->arch.smi_count = data;
2239 break;
11c6bffa 2240 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2241 case MSR_KVM_WALL_CLOCK:
2242 vcpu->kvm->arch.wall_clock = data;
2243 kvm_write_wall_clock(vcpu->kvm, data);
2244 break;
11c6bffa 2245 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2246 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2247 struct kvm_arch *ka = &vcpu->kvm->arch;
2248
12f9a48f 2249 kvmclock_reset(vcpu);
18068523 2250
54750f2c
MT		 2251 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2252 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2253
2254 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2255 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2256
2257 ka->boot_vcpu_runs_old_kvmclock = tmp;
2258 }
2259
18068523 2260 vcpu->arch.time = data;
0061d53d 2261 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2262
2263 /* we verify if the enable bit is set... */
2264 if (!(data & 1))
2265 break;
2266
4e335d9e 2267 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2268 &vcpu->arch.pv_time, data & ~1ULL,
2269 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2270 vcpu->arch.pv_time_enabled = false;
2271 else
2272 vcpu->arch.pv_time_enabled = true;
32cad84f 2273
18068523
GOC		 2274 break;
2275 }
344d9588
GN		 2276 case MSR_KVM_ASYNC_PF_EN:
2277 if (kvm_pv_enable_async_pf(vcpu, data))
2278 return 1;
2279 break;
c9aaa895
GC		 2280 case MSR_KVM_STEAL_TIME:
2281
2282 if (unlikely(!sched_info_on()))
2283 return 1;
2284
2285 if (data & KVM_STEAL_RESERVED_MASK)
2286 return 1;
2287
4e335d9e 2288 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2289 data & KVM_STEAL_VALID_BITS,
2290 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2291 return 1;
2292
2293 vcpu->arch.st.msr_val = data;
2294
2295 if (!(data & KVM_MSR_ENABLED))
2296 break;
2297
c9aaa895
GC		 2298 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2299
2300 break;
ae7a2a3f
MT		 2301 case MSR_KVM_PV_EOI_EN:
2302 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2303 return 1;
2304 break;
c9aaa895 2305
890ca9ae
HY		 2306 case MSR_IA32_MCG_CTL:
2307 case MSR_IA32_MCG_STATUS:
81760dcc 2308 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2309 return set_msr_mce(vcpu, msr_info);
71db6023 2310
6912ac32
WH		 2311 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2312 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2313 pr = true; /* fall through */
2314 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2315 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2316 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2317 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2318
2319 if (pr || data != 0)
a737f256
CD		 2320 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2321 "0x%x data 0x%llx\n", msr, data);
5753785f 2322 break;
84e0cefa
JS		 2323 case MSR_K7_CLK_CTL:
2324 /*
2325 * Ignore all writes to this no longer documented MSR.
2326 * Writes are only relevant for old K7 processors,
2327 * all pre-dating SVM, but a recommended workaround from
4a969980 2328 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2329 * affected processor models on the command line, hence
2330 * the need to ignore the workaround.
2331 */
2332 break;
55cd8e5a 2333 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2334 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2335 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2336 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2337 return kvm_hv_set_msr_common(vcpu, msr, data,
2338 msr_info->host_initiated);
91c9c3ed 2339 case MSR_IA32_BBL_CR_CTL3:
2340 /* Drop writes to this legacy MSR -- see rdmsr
2341 * counterpart for further detail.
2342 */
fab0aa3b
EM		 2343 if (report_ignored_msrs)
2344 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2345 msr, data);
91c9c3ed 2346 break;
2b036c6b 2347 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2348 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2349 return 1;
2350 vcpu->arch.osvw.length = data;
2351 break;
2352 case MSR_AMD64_OSVW_STATUS:
d6321d49 2353 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2354 return 1;
2355 vcpu->arch.osvw.status = data;
2356 break;
db2336a8
KH		 2357 case MSR_PLATFORM_INFO:
2358 if (!msr_info->host_initiated ||
2359 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2360 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2361 cpuid_fault_enabled(vcpu)))
2362 return 1;
2363 vcpu->arch.msr_platform_info = data;
2364 break;
2365 case MSR_MISC_FEATURES_ENABLES:
2366 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2367 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2368 !supports_cpuid_fault(vcpu)))
2369 return 1;
2370 vcpu->arch.msr_misc_features_enables = data;
2371 break;
15c4a640 2372 default:
ffde22ac
ES		 2373 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2374 return xen_hvm_config(vcpu, data);
c6702c9d 2375 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2376 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2377 if (!ignore_msrs) {
ae0f5499 2378 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2379 msr, data);
ed85c068
AP		 2380 return 1;
2381 } else {
fab0aa3b
EM		 2382 if (report_ignored_msrs)
2383 vcpu_unimpl(vcpu,
2384 "ignored wrmsr: 0x%x data 0x%llx\n",
2385 msr, data);
ed85c068
AP		 2386 break;
2387 }
15c4a640
CO		 2388 }
2389 return 0;
2390}
2391EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2392
2393
2394/*
2395 * Reads an msr value (of 'msr_index') into 'pdata'.
2396 * Returns 0 on success, non-0 otherwise.
2397 * Assumes vcpu_load() was already called.
2398 */
609e36d3 2399int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2400{
609e36d3 2401 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2402}
ff651cb6 2403EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2404
890ca9ae 2405static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2406{
2407 u64 data;
890ca9ae
HY		 2408 u64 mcg_cap = vcpu->arch.mcg_cap;
2409 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2410
2411 switch (msr) {
15c4a640
CO		 2412 case MSR_IA32_P5_MC_ADDR:
2413 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2414 data = 0;
2415 break;
15c4a640 2416 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2417 data = vcpu->arch.mcg_cap;
2418 break;
c7ac679c 2419 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2420 if (!(mcg_cap & MCG_CTL_P))
2421 return 1;
2422 data = vcpu->arch.mcg_ctl;
2423 break;
2424 case MSR_IA32_MCG_STATUS:
2425 data = vcpu->arch.mcg_status;
2426 break;
2427 default:
2428 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2429 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2430 u32 offset = msr - MSR_IA32_MC0_CTL;
2431 data = vcpu->arch.mce_banks[offset];
2432 break;
2433 }
2434 return 1;
2435 }
2436 *pdata = data;
2437 return 0;
2438}
2439
609e36d3 2440int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2441{
609e36d3 2442 switch (msr_info->index) {
890ca9ae 2443 case MSR_IA32_PLATFORM_ID:
15c4a640 2444 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2445 case MSR_IA32_DEBUGCTLMSR:
2446 case MSR_IA32_LASTBRANCHFROMIP:
2447 case MSR_IA32_LASTBRANCHTOIP:
2448 case MSR_IA32_LASTINTFROMIP:
2449 case MSR_IA32_LASTINTTOIP:
60af2ecd 2450 case MSR_K8_SYSCFG:
3afb1121
PB		 2451 case MSR_K8_TSEG_ADDR:
2452 case MSR_K8_TSEG_MASK:
60af2ecd 2453 case MSR_K7_HWCR:
61a6bd67 2454 case MSR_VM_HSAVE_PA:
1fdbd48c 2455 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2456 case MSR_AMD64_NB_CFG:
f7c6d140 2457 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2458 case MSR_AMD64_BU_CFG2:
0c2df2a1 2459 case MSR_IA32_PERF_CTL:
405a353a 2460 case MSR_AMD64_DC_CFG:
609e36d3 2461 msr_info->data = 0;
15c4a640 2462 break;
6912ac32
WH		 2463 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2464 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2465 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2466 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2467 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2468 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2469 msr_info->data = 0;
5753785f 2470 break;
742bc670 2471 case MSR_IA32_UCODE_REV:
609e36d3 2472 msr_info->data = 0x100000000ULL;
742bc670 2473 break;
9ba075a6 2474 case MSR_MTRRcap:
9ba075a6 2475 case 0x200 ... 0x2ff:
ff53604b 2476 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2477 case 0xcd: /* fsb frequency */
609e36d3 2478 msr_info->data = 3;
15c4a640 2479 break;
7b914098
JS		 2480 /*
2481 * MSR_EBC_FREQUENCY_ID
2482 * Conservative value valid for even the basic CPU models.
2483 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2484 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2485 * and 266MHz for model 3, or 4. Set Core Clock
2486 * Frequency to System Bus Frequency Ratio to 1 (bits
2487 * 31:24) even though these are only valid for CPU
2488 * models > 2, however guests may end up dividing or
2489 * multiplying by zero otherwise.
2490 */
2491 case MSR_EBC_FREQUENCY_ID:
609e36d3 2492 msr_info->data = 1 << 24;
7b914098 2493 break;
15c4a640 2494 case MSR_IA32_APICBASE:
609e36d3 2495 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2496 break;
0105d1a5 2497 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2498 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2499 break;
a3e06bbe 2500 case MSR_IA32_TSCDEADLINE:
609e36d3 2501 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2502 break;
ba904635 2503 case MSR_IA32_TSC_ADJUST:
609e36d3 2504 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2505 break;
15c4a640 2506 case MSR_IA32_MISC_ENABLE:
609e36d3 2507 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2508 break;
64d60670
PB		 2509 case MSR_IA32_SMBASE:
2510 if (!msr_info->host_initiated)
2511 return 1;
2512 msr_info->data = vcpu->arch.smbase;
15c4a640 2513 break;
52797bf9
LA		 2514 case MSR_SMI_COUNT:
2515 msr_info->data = vcpu->arch.smi_count;
2516 break;
847f0ad8
AG		 2517 case MSR_IA32_PERF_STATUS:
2518 /* TSC increment by tick */
609e36d3 2519 msr_info->data = 1000ULL;
847f0ad8 2520 /* CPU multiplier */
b0996ae4 2521 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2522 break;
15c4a640 2523 case MSR_EFER:
609e36d3 2524 msr_info->data = vcpu->arch.efer;
15c4a640 2525 break;
18068523 2526 case MSR_KVM_WALL_CLOCK:
11c6bffa 2527 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2528 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2529 break;
2530 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2531 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2532 msr_info->data = vcpu->arch.time;
18068523 2533 break;
344d9588 2534 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2535 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2536 break;
c9aaa895 2537 case MSR_KVM_STEAL_TIME:
609e36d3 2538 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2539 break;
1d92128f 2540 case MSR_KVM_PV_EOI_EN:
609e36d3 2541 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2542 break;
890ca9ae
HY		 2543 case MSR_IA32_P5_MC_ADDR:
2544 case MSR_IA32_P5_MC_TYPE:
2545 case MSR_IA32_MCG_CAP:
2546 case MSR_IA32_MCG_CTL:
2547 case MSR_IA32_MCG_STATUS:
81760dcc 2548 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2549 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2550 case MSR_K7_CLK_CTL:
2551 /*
2552 * Provide expected ramp-up count for K7. All other
2553 * are set to zero, indicating minimum divisors for
2554 * every field.
2555 *
2556 * This prevents guest kernels on AMD host with CPU
2557 * type 6, model 8 and higher from exploding due to
2558 * the rdmsr failing.
2559 */
609e36d3 2560 msr_info->data = 0x20000000;
84e0cefa 2561 break;
55cd8e5a 2562 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2563 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2564 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2565 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2566 return kvm_hv_get_msr_common(vcpu,
2567 msr_info->index, &msr_info->data);
55cd8e5a 2568 break;
91c9c3ed 2569 case MSR_IA32_BBL_CR_CTL3:
2570 /* This legacy MSR exists but isn't fully documented in current
2571 * silicon. It is however accessed by winxp in very narrow
2572 * scenarios where it sets bit #19, itself documented as
2573 * a "reserved" bit. Best effort attempt to source coherent
2574 * read data here should the balance of the register be
2575 * interpreted by the guest:
2576 *
2577 * L2 cache control register 3: 64GB range, 256KB size,
2578 * enabled, latency 0x1, configured
2579 */
609e36d3 2580 msr_info->data = 0xbe702111;
91c9c3ed 2581 break;
2b036c6b 2582 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2583 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2584 return 1;
609e36d3 2585 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2586 break;
2587 case MSR_AMD64_OSVW_STATUS:
d6321d49 2588 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2589 return 1;
609e36d3 2590 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2591 break;
db2336a8
KH		 2592 case MSR_PLATFORM_INFO:
2593 msr_info->data = vcpu->arch.msr_platform_info;
2594 break;
2595 case MSR_MISC_FEATURES_ENABLES:
2596 msr_info->data = vcpu->arch.msr_misc_features_enables;
2597 break;
15c4a640 2598 default:
c6702c9d 2599 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2600 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2601 if (!ignore_msrs) {
ae0f5499
BD		 2602 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2603 msr_info->index);
ed85c068
AP		 2604 return 1;
2605 } else {
fab0aa3b
EM		 2606 if (report_ignored_msrs)
2607 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2608 msr_info->index);
609e36d3 2609 msr_info->data = 0;
ed85c068
AP		 2610 }
2611 break;
15c4a640 2612 }
15c4a640
CO		 2613 return 0;
2614}
2615EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2616
313a3dc7
CO		 2617/*
2618 * Read or write a bunch of msrs. All parameters are kernel addresses.
2619 *
2620 * @return number of msrs set successfully.
2621 */
2622static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2623 struct kvm_msr_entry *entries,
2624 int (*do_msr)(struct kvm_vcpu *vcpu,
2625 unsigned index, u64 *data))
2626{
f656ce01 2627 int i, idx;
313a3dc7 2628
f656ce01 2629 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2630 for (i = 0; i < msrs->nmsrs; ++i)
2631 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2632 break;
f656ce01 2633 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2634
313a3dc7
CO		 2635 return i;
2636}
2637
2638/*
2639 * Read or write a bunch of msrs. Parameters are user addresses.
2640 *
2641 * @return number of msrs set successfully.
2642 */
2643static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2644 int (*do_msr)(struct kvm_vcpu *vcpu,
2645 unsigned index, u64 *data),
2646 int writeback)
2647{
2648 struct kvm_msrs msrs;
2649 struct kvm_msr_entry *entries;
2650 int r, n;
2651 unsigned size;
2652
2653 r = -EFAULT;
2654 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2655 goto out;
2656
2657 r = -E2BIG;
2658 if (msrs.nmsrs >= MAX_IO_MSRS)
2659 goto out;
2660
313a3dc7 2661 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2662 entries = memdup_user(user_msrs->entries, size);
2663 if (IS_ERR(entries)) {
2664 r = PTR_ERR(entries);
313a3dc7 2665 goto out;
ff5c2c03 2666 }
313a3dc7
CO		 2667
2668 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2669 if (r < 0)
2670 goto out_free;
2671
2672 r = -EFAULT;
2673 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2674 goto out_free;
2675
2676 r = n;
2677
2678out_free:
7a73c028 2679 kfree(entries);
313a3dc7
CO		 2680out:
2681 return r;
2682}
2683
784aa3d7 2684int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2685{
2686 int r;
2687
2688 switch (ext) {
2689 case KVM_CAP_IRQCHIP:
2690 case KVM_CAP_HLT:
2691 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2692 case KVM_CAP_SET_TSS_ADDR:
07716717 2693 case KVM_CAP_EXT_CPUID:
9c15bb1d 2694 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2695 case KVM_CAP_CLOCKSOURCE:
7837699f 2696 case KVM_CAP_PIT:
a28e4f5a 2697 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2698 case KVM_CAP_MP_STATE:
ed848624 2699 case KVM_CAP_SYNC_MMU:
a355c85c 2700 case KVM_CAP_USER_NMI:
52d939a0 2701 case KVM_CAP_REINJECT_CONTROL:
4925663a 2702 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2703 case KVM_CAP_IOEVENTFD:
f848a5a8 2704 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2705 case KVM_CAP_PIT2:
e9f42757 2706 case KVM_CAP_PIT_STATE2:
b927a3ce 2707 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2708 case KVM_CAP_XEN_HVM:
3cfc3092 2709 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2710 case KVM_CAP_HYPERV:
10388a07 2711 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2712 case KVM_CAP_HYPERV_SPIN:
5c919412 2713 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2714 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2715 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2716 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2717 case KVM_CAP_DEBUGREGS:
d2be1651 2718 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2719 case KVM_CAP_XSAVE:
344d9588 2720 case KVM_CAP_ASYNC_PF:
92a1f12d 2721 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2722 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2723 case KVM_CAP_READONLY_MEM:
5f66b620 2724 case KVM_CAP_HYPERV_TIME:
100943c5 2725 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2726 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2727 case KVM_CAP_ENABLE_CAP_VM:
2728 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2729 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2730 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2731 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2732 r = 1;
2733 break;
e3fd9a93
PB		 2734 case KVM_CAP_ADJUST_CLOCK:
2735 r = KVM_CLOCK_TSC_STABLE;
2736 break;
668fffa3
MT		 2737 case KVM_CAP_X86_GUEST_MWAIT:
2738 r = kvm_mwait_in_guest();
2739 break;
6d396b55
PB		 2740 case KVM_CAP_X86_SMM:
2741 /* SMBASE is usually relocated above 1M on modern chipsets,
2742 * and SMM handlers might indeed rely on 4G segment limits,
2743 * so do not report SMM to be available if real mode is
2744 * emulated via vm86 mode. Still, do not go to great lengths
2745 * to avoid userspace's usage of the feature, because it is a
2746 * fringe case that is not enabled except via specific settings
2747 * of the module parameters.
2748 */
2749 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2750 break;
774ead3a
AK		 2751 case KVM_CAP_VAPIC:
2752 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2753 break;
f725230a 2754 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2755 r = KVM_SOFT_MAX_VCPUS;
2756 break;
2757 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2758 r = KVM_MAX_VCPUS;
2759 break;
a988b910 2760 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2761 r = KVM_USER_MEM_SLOTS;
a988b910 2762 break;
a68a6a72
MT		 2763 case KVM_CAP_PV_MMU: /* obsolete */
2764 r = 0;
2f333bcb 2765 break;
890ca9ae
HY		 2766 case KVM_CAP_MCE:
2767 r = KVM_MAX_MCE_BANKS;
2768 break;
2d5b5a66 2769 case KVM_CAP_XCRS:
d366bf7e 2770 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2771 break;
92a1f12d
JR		 2772 case KVM_CAP_TSC_CONTROL:
2773 r = kvm_has_tsc_control;
2774 break;
37131313
RK		 2775 case KVM_CAP_X2APIC_API:
2776 r = KVM_X2APIC_API_VALID_FLAGS;
2777 break;
018d00d2
ZX		 2778 default:
2779 r = 0;
2780 break;
2781 }
2782 return r;
2783
2784}
2785
043405e1
CO		 2786long kvm_arch_dev_ioctl(struct file *filp,
2787 unsigned int ioctl, unsigned long arg)
2788{
2789 void __user *argp = (void __user *)arg;
2790 long r;
2791
2792 switch (ioctl) {
2793 case KVM_GET_MSR_INDEX_LIST: {
2794 struct kvm_msr_list __user *user_msr_list = argp;
2795 struct kvm_msr_list msr_list;
2796 unsigned n;
2797
2798 r = -EFAULT;
2799 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2800 goto out;
2801 n = msr_list.nmsrs;
62ef68bb 2802 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2803 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2804 goto out;
2805 r = -E2BIG;
e125e7b6 2806 if (n < msr_list.nmsrs)
043405e1
CO		 2807 goto out;
2808 r = -EFAULT;
2809 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2810 num_msrs_to_save * sizeof(u32)))
2811 goto out;
e125e7b6 2812 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2813 &emulated_msrs,
62ef68bb 2814 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2815 goto out;
2816 r = 0;
2817 break;
2818 }
9c15bb1d
BP		 2819 case KVM_GET_SUPPORTED_CPUID:
2820 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2821 struct kvm_cpuid2 __user *cpuid_arg = argp;
2822 struct kvm_cpuid2 cpuid;
2823
2824 r = -EFAULT;
2825 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2826 goto out;
9c15bb1d
BP		 2827
2828 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2829 ioctl);
674eea0f
AK		 2830 if (r)
2831 goto out;
2832
2833 r = -EFAULT;
2834 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2835 goto out;
2836 r = 0;
2837 break;
2838 }
890ca9ae 2839 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2840 r = -EFAULT;
c45dcc71
AR		 2841 if (copy_to_user(argp, &kvm_mce_cap_supported,
2842 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2843 goto out;
2844 r = 0;
2845 break;
2846 }
043405e1
CO		 2847 default:
2848 r = -EINVAL;
2849 }
2850out:
2851 return r;
2852}
2853
f5f48ee1
SY		 2854static void wbinvd_ipi(void *garbage)
2855{
2856 wbinvd();
2857}
2858
2859static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2860{
e0f0bbc5 2861 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2862}
2863
313a3dc7
CO		 2864void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2865{
f5f48ee1
SY		 2866 /* Address WBINVD may be executed by guest */
2867 if (need_emulate_wbinvd(vcpu)) {
2868 if (kvm_x86_ops->has_wbinvd_exit())
2869 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2870 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2871 smp_call_function_single(vcpu->cpu,
2872 wbinvd_ipi, NULL, 1);
2873 }
2874
313a3dc7 2875 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2876
0dd6a6ed
ZA		 2877 /* Apply any externally detected TSC adjustments (due to suspend) */
2878 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2879 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2880 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2881 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2882 }
8f6055cb 2883
48434c20 2884 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2885 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2886 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2887 if (tsc_delta < 0)
2888 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2889
c285545f 2890 if (check_tsc_unstable()) {
07c1419a 2891 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2892 vcpu->arch.last_guest_tsc);
a545ab6a 2893 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2894 vcpu->arch.tsc_catchup = 1;
c285545f 2895 }
a749e247
PB		 2896
2897 if (kvm_lapic_hv_timer_in_use(vcpu))
2898 kvm_lapic_restart_hv_timer(vcpu);
2899
d98d07ca
MT		 2900 /*
2901 * On a host with synchronized TSC, there is no need to update
2902 * kvmclock on vcpu->cpu migration
2903 */
2904 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2905 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2906 if (vcpu->cpu != cpu)
1bd2009e 2907 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2908 vcpu->cpu = cpu;
6b7d7e76 2909 }
c9aaa895 2910
c9aaa895 2911 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2912}
2913
0b9f6c46
PX		 2914static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2915{
2916 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2917 return;
2918
2919 vcpu->arch.st.steal.preempted = 1;
2920
4e335d9e 2921 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2922 &vcpu->arch.st.steal.preempted,
2923 offsetof(struct kvm_steal_time, preempted),
2924 sizeof(vcpu->arch.st.steal.preempted));
2925}
2926
313a3dc7
CO		 2927void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2928{
cc0d907c 2929 int idx;
de63ad4c
LM		 2930
2931 if (vcpu->preempted)
2932 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2933
931f261b
AA		 2934 /*
2935 * Disable page faults because we're in atomic context here.
2936 * kvm_write_guest_offset_cached() would call might_fault()
2937 * that relies on pagefault_disable() to tell if there's a
2938 * bug. NOTE: the write to guest memory may not go through if
2939 * during postcopy live migration or if there's heavy guest
2940 * paging.
2941 */
2942 pagefault_disable();
cc0d907c
AA		 2943 /*
2944 * kvm_memslots() will be called by
2945 * kvm_write_guest_offset_cached() so take the srcu lock.
2946 */
2947 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2948 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2949 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2950 pagefault_enable();
02daab21 2951 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 2952 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2953}
2954
313a3dc7
CO		 2955static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2956 struct kvm_lapic_state *s)
2957{
76dfafd5 2958 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2959 kvm_x86_ops->sync_pir_to_irr(vcpu);
2960
a92e2543 2961 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2962}
2963
2964static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2965 struct kvm_lapic_state *s)
2966{
a92e2543
RK		 2967 int r;
2968
2969 r = kvm_apic_set_state(vcpu, s);
2970 if (r)
2971 return r;
cb142eb7 2972 update_cr8_intercept(vcpu);
313a3dc7
CO		 2973
2974 return 0;
2975}
2976
127a457a
MG		 2977static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2978{
2979 return (!lapic_in_kernel(vcpu) ||
2980 kvm_apic_accept_pic_intr(vcpu));
2981}
2982
782d422b
MG		 2983/*
2984 * if userspace requested an interrupt window, check that the
2985 * interrupt window is open.
2986 *
2987 * No need to exit to userspace if we already have an interrupt queued.
2988 */
2989static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2990{
2991 return kvm_arch_interrupt_allowed(vcpu) &&
2992 !kvm_cpu_has_interrupt(vcpu) &&
2993 !kvm_event_needs_reinjection(vcpu) &&
2994 kvm_cpu_accept_dm_intr(vcpu);
2995}
2996
f77bc6a4
ZX		 2997static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2998 struct kvm_interrupt *irq)
2999{
02cdb50f 3000 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3001 return -EINVAL;
1c1a9ce9
SR		 3002
3003 if (!irqchip_in_kernel(vcpu->kvm)) {
3004 kvm_queue_interrupt(vcpu, irq->irq, false);
3005 kvm_make_request(KVM_REQ_EVENT, vcpu);
3006 return 0;
3007 }
3008
3009 /*
3010 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3011 * fail for in-kernel 8259.
3012 */
3013 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3014 return -ENXIO;
f77bc6a4 3015
1c1a9ce9
SR		 3016 if (vcpu->arch.pending_external_vector != -1)
3017 return -EEXIST;
f77bc6a4 3018
1c1a9ce9 3019 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3020 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3021 return 0;
3022}
3023
c4abb7c9
JK		 3024static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3025{
c4abb7c9 3026 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3027
3028 return 0;
3029}
3030
f077825a
PB		 3031static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3032{
64d60670
PB		 3033 kvm_make_request(KVM_REQ_SMI, vcpu);
3034
f077825a
PB		 3035 return 0;
3036}
3037
b209749f
AK		 3038static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3039 struct kvm_tpr_access_ctl *tac)
3040{
3041 if (tac->flags)
3042 return -EINVAL;
3043 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3044 return 0;
3045}
3046
890ca9ae
HY		 3047static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3048 u64 mcg_cap)
3049{
3050 int r;
3051 unsigned bank_num = mcg_cap & 0xff, bank;
3052
3053 r = -EINVAL;
a9e38c3e 3054 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3055 goto out;
c45dcc71 3056 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3057 goto out;
3058 r = 0;
3059 vcpu->arch.mcg_cap = mcg_cap;
3060 /* Init IA32_MCG_CTL to all 1s */
3061 if (mcg_cap & MCG_CTL_P)
3062 vcpu->arch.mcg_ctl = ~(u64)0;
3063 /* Init IA32_MCi_CTL to all 1s */
3064 for (bank = 0; bank < bank_num; bank++)
3065 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3066
3067 if (kvm_x86_ops->setup_mce)
3068 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3069out:
3070 return r;
3071}
3072
3073static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3074 struct kvm_x86_mce *mce)
3075{
3076 u64 mcg_cap = vcpu->arch.mcg_cap;
3077 unsigned bank_num = mcg_cap & 0xff;
3078 u64 *banks = vcpu->arch.mce_banks;
3079
3080 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3081 return -EINVAL;
3082 /*
3083 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3084 * reporting is disabled
3085 */
3086 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3087 vcpu->arch.mcg_ctl != ~(u64)0)
3088 return 0;
3089 banks += 4 * mce->bank;
3090 /*
3091 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3092 * reporting is disabled for the bank
3093 */
3094 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3095 return 0;
3096 if (mce->status & MCI_STATUS_UC) {
3097 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3098 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3099 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3100 return 0;
3101 }
3102 if (banks[1] & MCI_STATUS_VAL)
3103 mce->status |= MCI_STATUS_OVER;
3104 banks[2] = mce->addr;
3105 banks[3] = mce->misc;
3106 vcpu->arch.mcg_status = mce->mcg_status;
3107 banks[1] = mce->status;
3108 kvm_queue_exception(vcpu, MC_VECTOR);
3109 } else if (!(banks[1] & MCI_STATUS_VAL)
3110 || !(banks[1] & MCI_STATUS_UC)) {
3111 if (banks[1] & MCI_STATUS_VAL)
3112 mce->status |= MCI_STATUS_OVER;
3113 banks[2] = mce->addr;
3114 banks[3] = mce->misc;
3115 banks[1] = mce->status;
3116 } else
3117 banks[1] |= MCI_STATUS_OVER;
3118 return 0;
3119}
3120
3cfc3092
JK		 3121static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3122 struct kvm_vcpu_events *events)
3123{
7460fb4a 3124 process_nmi(vcpu);
664f8e26
WL		 3125 /*
3126 * FIXME: pass injected and pending separately. This is only
3127 * needed for nested virtualization, whose state cannot be
3128 * migrated yet. For now we can combine them.
3129 */
03b82a30 3130 events->exception.injected =
664f8e26
WL		 3131 (vcpu->arch.exception.pending ||
3132 vcpu->arch.exception.injected) &&
03b82a30 3133 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3134 events->exception.nr = vcpu->arch.exception.nr;
3135 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3136 events->exception.pad = 0;
3cfc3092
JK		 3137 events->exception.error_code = vcpu->arch.exception.error_code;
3138
03b82a30
JK		 3139 events->interrupt.injected =
3140 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3141 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3142 events->interrupt.soft = 0;
37ccdcbe 3143 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3144
3145 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3146 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3147 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3148 events->nmi.pad = 0;
3cfc3092 3149
66450a21 3150 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3151
f077825a
PB		 3152 events->smi.smm = is_smm(vcpu);
3153 events->smi.pending = vcpu->arch.smi_pending;
3154 events->smi.smm_inside_nmi =
3155 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3156 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3157
dab4b911 3158 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3159 | KVM_VCPUEVENT_VALID_SHADOW
3160 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3161 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3162}
3163
6ef4e07e
XG		 3164static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3165
3cfc3092
JK		 3166static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3167 struct kvm_vcpu_events *events)
3168{
dab4b911 3169 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3170 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3171 | KVM_VCPUEVENT_VALID_SHADOW
3172 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3173 return -EINVAL;
3174
78e546c8 3175 if (events->exception.injected &&
28d06353
JM		 3176 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3177 is_guest_mode(vcpu)))
78e546c8
PB		 3178 return -EINVAL;
3179
28bf2888
DH		 3180 /* INITs are latched while in SMM */
3181 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3182 (events->smi.smm || events->smi.pending) &&
3183 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3184 return -EINVAL;
3185
7460fb4a 3186 process_nmi(vcpu);
664f8e26 3187 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3188 vcpu->arch.exception.pending = events->exception.injected;
3189 vcpu->arch.exception.nr = events->exception.nr;
3190 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3191 vcpu->arch.exception.error_code = events->exception.error_code;
3192
3193 vcpu->arch.interrupt.pending = events->interrupt.injected;
3194 vcpu->arch.interrupt.nr = events->interrupt.nr;
3195 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3196 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3197 kvm_x86_ops->set_interrupt_shadow(vcpu,
3198 events->interrupt.shadow);
3cfc3092
JK		 3199
3200 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3201 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3202 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3203 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3204
66450a21 3205 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3206 lapic_in_kernel(vcpu))
66450a21 3207 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3208
f077825a 3209 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3210 u32 hflags = vcpu->arch.hflags;
f077825a 3211 if (events->smi.smm)
6ef4e07e 3212 hflags |= HF_SMM_MASK;
f077825a 3213 else
6ef4e07e
XG		 3214 hflags &= ~HF_SMM_MASK;
3215 kvm_set_hflags(vcpu, hflags);
3216
f077825a 3217 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3218
3219 if (events->smi.smm) {
3220 if (events->smi.smm_inside_nmi)
3221 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3222 else
f4ef1910
WL		 3223 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3224 if (lapic_in_kernel(vcpu)) {
3225 if (events->smi.latched_init)
3226 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3227 else
3228 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3229 }
f077825a
PB		 3230 }
3231 }
3232
3842d135
AK		 3233 kvm_make_request(KVM_REQ_EVENT, vcpu);
3234
3cfc3092
JK		 3235 return 0;
3236}
3237
a1efbe77
JK		 3238static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3239 struct kvm_debugregs *dbgregs)
3240{
73aaf249
JK		 3241 unsigned long val;
3242
a1efbe77 3243 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3244 kvm_get_dr(vcpu, 6, &val);
73aaf249 3245 dbgregs->dr6 = val;
a1efbe77
JK		 3246 dbgregs->dr7 = vcpu->arch.dr7;
3247 dbgregs->flags = 0;
97e69aa6 3248 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3249}
3250
3251static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3252 struct kvm_debugregs *dbgregs)
3253{
3254 if (dbgregs->flags)
3255 return -EINVAL;
3256
d14bdb55
PB		 3257 if (dbgregs->dr6 & ~0xffffffffull)
3258 return -EINVAL;
3259 if (dbgregs->dr7 & ~0xffffffffull)
3260 return -EINVAL;
3261
a1efbe77 3262 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3263 kvm_update_dr0123(vcpu);
a1efbe77 3264 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3265 kvm_update_dr6(vcpu);
a1efbe77 3266 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3267 kvm_update_dr7(vcpu);
a1efbe77 3268
a1efbe77
JK		 3269 return 0;
3270}
3271
df1daba7
PB		 3272#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3273
3274static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3275{
c47ada30 3276 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3277 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3278 u64 valid;
3279
3280 /*
3281 * Copy legacy XSAVE area, to avoid complications with CPUID
3282 * leaves 0 and 1 in the loop below.
3283 */
3284 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3285
3286 /* Set XSTATE_BV */
00c87e9a 3287 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3288 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3289
3290 /*
3291 * Copy each region from the possibly compacted offset to the
3292 * non-compacted offset.
3293 */
d91cab78 3294 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3295 while (valid) {
3296 u64 feature = valid & -valid;
3297 int index = fls64(feature) - 1;
3298 void *src = get_xsave_addr(xsave, feature);
3299
3300 if (src) {
3301 u32 size, offset, ecx, edx;
3302 cpuid_count(XSTATE_CPUID, index,
3303 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3304 if (feature == XFEATURE_MASK_PKRU)
3305 memcpy(dest + offset, &vcpu->arch.pkru,
3306 sizeof(vcpu->arch.pkru));
3307 else
3308 memcpy(dest + offset, src, size);
3309
df1daba7
PB		 3310 }
3311
3312 valid -= feature;
3313 }
3314}
3315
3316static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3317{
c47ada30 3318 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3319 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3320 u64 valid;
3321
3322 /*
3323 * Copy legacy XSAVE area, to avoid complications with CPUID
3324 * leaves 0 and 1 in the loop below.
3325 */
3326 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3327
3328 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3329 xsave->header.xfeatures = xstate_bv;
782511b0 3330 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3331 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3332
3333 /*
3334 * Copy each region from the non-compacted offset to the
3335 * possibly compacted offset.
3336 */
d91cab78 3337 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3338 while (valid) {
3339 u64 feature = valid & -valid;
3340 int index = fls64(feature) - 1;
3341 void *dest = get_xsave_addr(xsave, feature);
3342
3343 if (dest) {
3344 u32 size, offset, ecx, edx;
3345 cpuid_count(XSTATE_CPUID, index,
3346 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3347 if (feature == XFEATURE_MASK_PKRU)
3348 memcpy(&vcpu->arch.pkru, src + offset,
3349 sizeof(vcpu->arch.pkru));
3350 else
3351 memcpy(dest, src + offset, size);
ee4100da 3352 }
df1daba7
PB		 3353
3354 valid -= feature;
3355 }
3356}
3357
2d5b5a66
SY		 3358static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3359 struct kvm_xsave *guest_xsave)
3360{
d366bf7e 3361 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3362 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3363 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3364 } else {
2d5b5a66 3365 memcpy(guest_xsave->region,
7366ed77 3366 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3367 sizeof(struct fxregs_state));
2d5b5a66 3368 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3369 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3370 }
3371}
3372
a575813b
WL		 3373#define XSAVE_MXCSR_OFFSET 24
3374
2d5b5a66
SY		 3375static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3376 struct kvm_xsave *guest_xsave)
3377{
3378 u64 xstate_bv =
3379 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3380 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3381
d366bf7e 3382 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3383 /*
3384 * Here we allow setting states that are not present in
3385 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3386 * with old userspace.
3387 */
a575813b
WL		 3388 if (xstate_bv & ~kvm_supported_xcr0() ||
3389 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3390 return -EINVAL;
df1daba7 3391 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3392 } else {
a575813b
WL		 3393 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3394 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3395 return -EINVAL;
7366ed77 3396 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3397 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3398 }
3399 return 0;
3400}
3401
3402static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3403 struct kvm_xcrs *guest_xcrs)
3404{
d366bf7e 3405 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3406 guest_xcrs->nr_xcrs = 0;
3407 return;
3408 }
3409
3410 guest_xcrs->nr_xcrs = 1;
3411 guest_xcrs->flags = 0;
3412 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3413 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3414}
3415
3416static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3417 struct kvm_xcrs *guest_xcrs)
3418{
3419 int i, r = 0;
3420
d366bf7e 3421 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3422 return -EINVAL;
3423
3424 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3425 return -EINVAL;
3426
3427 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3428 /* Only support XCR0 currently */
c67a04cb 3429 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3430 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3431 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3432 break;
3433 }
3434 if (r)
3435 r = -EINVAL;
3436 return r;
3437}
3438
1c0b28c2
EM		 3439/*
3440 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3441 * stopped by the hypervisor. This function will be called from the host only.
3442 * EINVAL is returned when the host attempts to set the flag for a guest that
3443 * does not support pv clocks.
3444 */
3445static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3446{
0b79459b 3447 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3448 return -EINVAL;
51d59c6b 3449 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3450 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3451 return 0;
3452}
3453
5c919412
AS		 3454static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3455 struct kvm_enable_cap *cap)
3456{
3457 if (cap->flags)
3458 return -EINVAL;
3459
3460 switch (cap->cap) {
efc479e6
RK		 3461 case KVM_CAP_HYPERV_SYNIC2:
3462 if (cap->args[0])
3463 return -EINVAL;
5c919412 3464 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3465 if (!irqchip_in_kernel(vcpu->kvm))
3466 return -EINVAL;
efc479e6
RK		 3467 return kvm_hv_activate_synic(vcpu, cap->cap ==
3468 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3469 default:
3470 return -EINVAL;
3471 }
3472}
3473
313a3dc7
CO		 3474long kvm_arch_vcpu_ioctl(struct file *filp,
3475 unsigned int ioctl, unsigned long arg)
3476{
3477 struct kvm_vcpu *vcpu = filp->private_data;
3478 void __user *argp = (void __user *)arg;
3479 int r;
d1ac91d8
AK		 3480 union {
3481 struct kvm_lapic_state *lapic;
3482 struct kvm_xsave *xsave;
3483 struct kvm_xcrs *xcrs;
3484 void *buffer;
3485 } u;
3486
3487 u.buffer = NULL;
313a3dc7
CO		 3488 switch (ioctl) {
3489 case KVM_GET_LAPIC: {
2204ae3c 3490 r = -EINVAL;
bce87cce 3491 if (!lapic_in_kernel(vcpu))
2204ae3c 3492 goto out;
d1ac91d8 3493 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3494
b772ff36 3495 r = -ENOMEM;
d1ac91d8 3496 if (!u.lapic)
b772ff36 3497 goto out;
d1ac91d8 3498 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3499 if (r)
3500 goto out;
3501 r = -EFAULT;
d1ac91d8 3502 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3503 goto out;
3504 r = 0;
3505 break;
3506 }
3507 case KVM_SET_LAPIC: {
2204ae3c 3508 r = -EINVAL;
bce87cce 3509 if (!lapic_in_kernel(vcpu))
2204ae3c 3510 goto out;
ff5c2c03 3511 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3512 if (IS_ERR(u.lapic))
3513 return PTR_ERR(u.lapic);
ff5c2c03 3514
d1ac91d8 3515 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3516 break;
3517 }
f77bc6a4
ZX		 3518 case KVM_INTERRUPT: {
3519 struct kvm_interrupt irq;
3520
3521 r = -EFAULT;
3522 if (copy_from_user(&irq, argp, sizeof irq))
3523 goto out;
3524 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3525 break;
3526 }
c4abb7c9
JK		 3527 case KVM_NMI: {
3528 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3529 break;
3530 }
f077825a
PB		 3531 case KVM_SMI: {
3532 r = kvm_vcpu_ioctl_smi(vcpu);
3533 break;
3534 }
313a3dc7
CO		 3535 case KVM_SET_CPUID: {
3536 struct kvm_cpuid __user *cpuid_arg = argp;
3537 struct kvm_cpuid cpuid;
3538
3539 r = -EFAULT;
3540 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3541 goto out;
3542 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3543 break;
3544 }
07716717
DK		 3545 case KVM_SET_CPUID2: {
3546 struct kvm_cpuid2 __user *cpuid_arg = argp;
3547 struct kvm_cpuid2 cpuid;
3548
3549 r = -EFAULT;
3550 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3551 goto out;
3552 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3553 cpuid_arg->entries);
07716717
DK		 3554 break;
3555 }
3556 case KVM_GET_CPUID2: {
3557 struct kvm_cpuid2 __user *cpuid_arg = argp;
3558 struct kvm_cpuid2 cpuid;
3559
3560 r = -EFAULT;
3561 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3562 goto out;
3563 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3564 cpuid_arg->entries);
07716717
DK		 3565 if (r)
3566 goto out;
3567 r = -EFAULT;
3568 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3569 goto out;
3570 r = 0;
3571 break;
3572 }
313a3dc7 3573 case KVM_GET_MSRS:
609e36d3 3574 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3575 break;
3576 case KVM_SET_MSRS:
3577 r = msr_io(vcpu, argp, do_set_msr, 0);
3578 break;
b209749f
AK		 3579 case KVM_TPR_ACCESS_REPORTING: {
3580 struct kvm_tpr_access_ctl tac;
3581
3582 r = -EFAULT;
3583 if (copy_from_user(&tac, argp, sizeof tac))
3584 goto out;
3585 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3586 if (r)
3587 goto out;
3588 r = -EFAULT;
3589 if (copy_to_user(argp, &tac, sizeof tac))
3590 goto out;
3591 r = 0;
3592 break;
3593 };
b93463aa
AK		 3594 case KVM_SET_VAPIC_ADDR: {
3595 struct kvm_vapic_addr va;
7301d6ab 3596 int idx;
b93463aa
AK		 3597
3598 r = -EINVAL;
35754c98 3599 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3600 goto out;
3601 r = -EFAULT;
3602 if (copy_from_user(&va, argp, sizeof va))
3603 goto out;
7301d6ab 3604 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3605 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3606 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3607 break;
3608 }
890ca9ae
HY		 3609 case KVM_X86_SETUP_MCE: {
3610 u64 mcg_cap;
3611
3612 r = -EFAULT;
3613 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3614 goto out;
3615 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3616 break;
3617 }
3618 case KVM_X86_SET_MCE: {
3619 struct kvm_x86_mce mce;
3620
3621 r = -EFAULT;
3622 if (copy_from_user(&mce, argp, sizeof mce))
3623 goto out;
3624 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3625 break;
3626 }
3cfc3092
JK		 3627 case KVM_GET_VCPU_EVENTS: {
3628 struct kvm_vcpu_events events;
3629
3630 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3631
3632 r = -EFAULT;
3633 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3634 break;
3635 r = 0;
3636 break;
3637 }
3638 case KVM_SET_VCPU_EVENTS: {
3639 struct kvm_vcpu_events events;
3640
3641 r = -EFAULT;
3642 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3643 break;
3644
3645 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3646 break;
3647 }
a1efbe77
JK		 3648 case KVM_GET_DEBUGREGS: {
3649 struct kvm_debugregs dbgregs;
3650
3651 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3652
3653 r = -EFAULT;
3654 if (copy_to_user(argp, &dbgregs,
3655 sizeof(struct kvm_debugregs)))
3656 break;
3657 r = 0;
3658 break;
3659 }
3660 case KVM_SET_DEBUGREGS: {
3661 struct kvm_debugregs dbgregs;
3662
3663 r = -EFAULT;
3664 if (copy_from_user(&dbgregs, argp,
3665 sizeof(struct kvm_debugregs)))
3666 break;
3667
3668 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3669 break;
3670 }
2d5b5a66 3671 case KVM_GET_XSAVE: {
d1ac91d8 3672 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3673 r = -ENOMEM;
d1ac91d8 3674 if (!u.xsave)
2d5b5a66
SY		 3675 break;
3676
d1ac91d8 3677 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3678
3679 r = -EFAULT;
d1ac91d8 3680 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3681 break;
3682 r = 0;
3683 break;
3684 }
3685 case KVM_SET_XSAVE: {
ff5c2c03 3686 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3687 if (IS_ERR(u.xsave))
3688 return PTR_ERR(u.xsave);
2d5b5a66 3689
d1ac91d8 3690 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3691 break;
3692 }
3693 case KVM_GET_XCRS: {
d1ac91d8 3694 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3695 r = -ENOMEM;
d1ac91d8 3696 if (!u.xcrs)
2d5b5a66
SY		 3697 break;
3698
d1ac91d8 3699 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3700
3701 r = -EFAULT;
d1ac91d8 3702 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3703 sizeof(struct kvm_xcrs)))
3704 break;
3705 r = 0;
3706 break;
3707 }
3708 case KVM_SET_XCRS: {
ff5c2c03 3709 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3710 if (IS_ERR(u.xcrs))
3711 return PTR_ERR(u.xcrs);
2d5b5a66 3712
d1ac91d8 3713 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3714 break;
3715 }
92a1f12d
JR		 3716 case KVM_SET_TSC_KHZ: {
3717 u32 user_tsc_khz;
3718
3719 r = -EINVAL;
92a1f12d
JR		 3720 user_tsc_khz = (u32)arg;
3721
3722 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3723 goto out;
3724
cc578287
ZA		 3725 if (user_tsc_khz == 0)
3726 user_tsc_khz = tsc_khz;
3727
381d585c
HZ		 3728 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3729 r = 0;
92a1f12d 3730
92a1f12d
JR		 3731 goto out;
3732 }
3733 case KVM_GET_TSC_KHZ: {
cc578287 3734 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3735 goto out;
3736 }
1c0b28c2
EM		 3737 case KVM_KVMCLOCK_CTRL: {
3738 r = kvm_set_guest_paused(vcpu);
3739 goto out;
3740 }
5c919412
AS		 3741 case KVM_ENABLE_CAP: {
3742 struct kvm_enable_cap cap;
3743
3744 r = -EFAULT;
3745 if (copy_from_user(&cap, argp, sizeof(cap)))
3746 goto out;
3747 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3748 break;
3749 }
313a3dc7
CO		 3750 default:
3751 r = -EINVAL;
3752 }
3753out:
d1ac91d8 3754 kfree(u.buffer);
313a3dc7
CO		 3755 return r;
3756}
3757
5b1c1493
CO		 3758int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3759{
3760 return VM_FAULT_SIGBUS;
3761}
3762
1fe779f8
CO		 3763static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3764{
3765 int ret;
3766
3767 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3768 return -EINVAL;
1fe779f8
CO		 3769 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3770 return ret;
3771}
3772
b927a3ce
SY		 3773static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3774 u64 ident_addr)
3775{
3776 kvm->arch.ept_identity_map_addr = ident_addr;
3777 return 0;
3778}
3779
1fe779f8
CO		 3780static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3781 u32 kvm_nr_mmu_pages)
3782{
3783 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3784 return -EINVAL;
3785
79fac95e 3786 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3787
3788 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3789 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3790
79fac95e 3791 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3792 return 0;
3793}
3794
3795static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3796{
39de71ec 3797 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3798}
3799
1fe779f8
CO		 3800static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3801{
90bca052 3802 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3803 int r;
3804
3805 r = 0;
3806 switch (chip->chip_id) {
3807 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3808 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3809 sizeof(struct kvm_pic_state));
3810 break;
3811 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3812 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3813 sizeof(struct kvm_pic_state));
3814 break;
3815 case KVM_IRQCHIP_IOAPIC:
33392b49 3816 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3817 break;
3818 default:
3819 r = -EINVAL;
3820 break;
3821 }
3822 return r;
3823}
3824
3825static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3826{
90bca052 3827 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3828 int r;
3829
3830 r = 0;
3831 switch (chip->chip_id) {
3832 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3833 spin_lock(&pic->lock);
3834 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3835 sizeof(struct kvm_pic_state));
90bca052 3836 spin_unlock(&pic->lock);
1fe779f8
CO		 3837 break;
3838 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3839 spin_lock(&pic->lock);
3840 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3841 sizeof(struct kvm_pic_state));
90bca052 3842 spin_unlock(&pic->lock);
1fe779f8
CO		 3843 break;
3844 case KVM_IRQCHIP_IOAPIC:
33392b49 3845 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3846 break;
3847 default:
3848 r = -EINVAL;
3849 break;
3850 }
90bca052 3851 kvm_pic_update_irq(pic);
1fe779f8
CO		 3852 return r;
3853}
3854
e0f63cb9
SY		 3855static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3856{
34f3941c
RK		 3857 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3858
3859 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3860
3861 mutex_lock(&kps->lock);
3862 memcpy(ps, &kps->channels, sizeof(*ps));
3863 mutex_unlock(&kps->lock);
2da29bcc 3864 return 0;
e0f63cb9
SY		 3865}
3866
3867static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3868{
0185604c 3869 int i;
09edea72
RK		 3870 struct kvm_pit *pit = kvm->arch.vpit;
3871
3872 mutex_lock(&pit->pit_state.lock);
34f3941c 3873 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3874 for (i = 0; i < 3; i++)
09edea72
RK		 3875 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3876 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3877 return 0;
e9f42757
BK		 3878}
3879
3880static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3881{
e9f42757
BK		 3882 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3883 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3884 sizeof(ps->channels));
3885 ps->flags = kvm->arch.vpit->pit_state.flags;
3886 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3887 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3888 return 0;
e9f42757
BK		 3889}
3890
3891static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3892{
2da29bcc 3893 int start = 0;
0185604c 3894 int i;
e9f42757 3895 u32 prev_legacy, cur_legacy;
09edea72
RK		 3896 struct kvm_pit *pit = kvm->arch.vpit;
3897
3898 mutex_lock(&pit->pit_state.lock);
3899 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3900 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3901 if (!prev_legacy && cur_legacy)
3902 start = 1;
09edea72
RK		 3903 memcpy(&pit->pit_state.channels, &ps->channels,
3904 sizeof(pit->pit_state.channels));
3905 pit->pit_state.flags = ps->flags;
0185604c 3906 for (i = 0; i < 3; i++)
09edea72 3907 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3908 start && i == 0);
09edea72 3909 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3910 return 0;
e0f63cb9
SY		 3911}
3912
52d939a0
MT		 3913static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3914 struct kvm_reinject_control *control)
3915{
71474e2f
RK		 3916 struct kvm_pit *pit = kvm->arch.vpit;
3917
3918 if (!pit)
52d939a0 3919 return -ENXIO;
b39c90b6 3920
71474e2f
RK		 3921 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3922 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3923 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3924 */
3925 mutex_lock(&pit->pit_state.lock);
3926 kvm_pit_set_reinject(pit, control->pit_reinject);
3927 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3928
52d939a0
MT		 3929 return 0;
3930}
3931
95d4c16c 3932/**
60c34612
TY		 3933 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3934 * @kvm: kvm instance
3935 * @log: slot id and address to which we copy the log
95d4c16c 3936 *
e108ff2f
PB		 3937 * Steps 1-4 below provide general overview of dirty page logging. See
3938 * kvm_get_dirty_log_protect() function description for additional details.
3939 *
3940 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3941 * always flush the TLB (step 4) even if previous step failed and the dirty
3942 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3943 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3944 * writes will be marked dirty for next log read.
95d4c16c 3945 *
60c34612
TY		 3946 * 1. Take a snapshot of the bit and clear it if needed.
3947 * 2. Write protect the corresponding page.
e108ff2f
PB		 3948 * 3. Copy the snapshot to the userspace.
3949 * 4. Flush TLB's if needed.
5bb064dc 3950 */
60c34612 3951int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3952{
60c34612 3953 bool is_dirty = false;
e108ff2f 3954 int r;
5bb064dc 3955
79fac95e 3956 mutex_lock(&kvm->slots_lock);
5bb064dc 3957
88178fd4
KH		 3958 /*
3959 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3960 */
3961 if (kvm_x86_ops->flush_log_dirty)
3962 kvm_x86_ops->flush_log_dirty(kvm);
3963
e108ff2f 3964 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3965
3966 /*
3967 * All the TLBs can be flushed out of mmu lock, see the comments in
3968 * kvm_mmu_slot_remove_write_access().
3969 */
e108ff2f 3970 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3971 if (is_dirty)
3972 kvm_flush_remote_tlbs(kvm);
3973
79fac95e 3974 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3975 return r;
3976}
3977
aa2fbe6d
YZ		 3978int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3979 bool line_status)
23d43cf9
CD		 3980{
3981 if (!irqchip_in_kernel(kvm))
3982 return -ENXIO;
3983
3984 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3985 irq_event->irq, irq_event->level,
3986 line_status);
23d43cf9
CD		 3987 return 0;
3988}
3989
90de4a18
NA		 3990static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3991 struct kvm_enable_cap *cap)
3992{
3993 int r;
3994
3995 if (cap->flags)
3996 return -EINVAL;
3997
3998 switch (cap->cap) {
3999 case KVM_CAP_DISABLE_QUIRKS:
4000 kvm->arch.disabled_quirks = cap->args[0];
4001 r = 0;
4002 break;
49df6397
SR		 4003 case KVM_CAP_SPLIT_IRQCHIP: {
4004 mutex_lock(&kvm->lock);
b053b2ae
SR		 4005 r = -EINVAL;
4006 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4007 goto split_irqchip_unlock;
49df6397
SR		 4008 r = -EEXIST;
4009 if (irqchip_in_kernel(kvm))
4010 goto split_irqchip_unlock;
557abc40 4011 if (kvm->created_vcpus)
49df6397
SR		 4012 goto split_irqchip_unlock;
4013 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4014 if (r)
49df6397
SR		 4015 goto split_irqchip_unlock;
4016 /* Pairs with irqchip_in_kernel. */
4017 smp_wmb();
49776faf 4018 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4019 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4020 r = 0;
4021split_irqchip_unlock:
4022 mutex_unlock(&kvm->lock);
4023 break;
4024 }
37131313
RK		 4025 case KVM_CAP_X2APIC_API:
4026 r = -EINVAL;
4027 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4028 break;
4029
4030 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4031 kvm->arch.x2apic_format = true;
c519265f
RK		 4032 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4033 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4034
4035 r = 0;
4036 break;
90de4a18
NA		 4037 default:
4038 r = -EINVAL;
4039 break;
4040 }
4041 return r;
4042}
4043
1fe779f8
CO		 4044long kvm_arch_vm_ioctl(struct file *filp,
4045 unsigned int ioctl, unsigned long arg)
4046{
4047 struct kvm *kvm = filp->private_data;
4048 void __user *argp = (void __user *)arg;
367e1319 4049 int r = -ENOTTY;
f0d66275
DH		 4050 /*
4051 * This union makes it completely explicit to gcc-3.x
4052 * that these two variables' stack usage should be
4053 * combined, not added together.
4054 */
4055 union {
4056 struct kvm_pit_state ps;
e9f42757 4057 struct kvm_pit_state2 ps2;
c5ff41ce 4058 struct kvm_pit_config pit_config;
f0d66275 4059 } u;
1fe779f8
CO		 4060
4061 switch (ioctl) {
4062 case KVM_SET_TSS_ADDR:
4063 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4064 break;
b927a3ce
SY		 4065 case KVM_SET_IDENTITY_MAP_ADDR: {
4066 u64 ident_addr;
4067
1af1ac91
DH		 4068 mutex_lock(&kvm->lock);
4069 r = -EINVAL;
4070 if (kvm->created_vcpus)
4071 goto set_identity_unlock;
b927a3ce
SY		 4072 r = -EFAULT;
4073 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4074 goto set_identity_unlock;
b927a3ce 4075 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4076set_identity_unlock:
4077 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4078 break;
4079 }
1fe779f8
CO		 4080 case KVM_SET_NR_MMU_PAGES:
4081 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4082 break;
4083 case KVM_GET_NR_MMU_PAGES:
4084 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4085 break;
3ddea128 4086 case KVM_CREATE_IRQCHIP: {
3ddea128 4087 mutex_lock(&kvm->lock);
09941366 4088
3ddea128 4089 r = -EEXIST;
35e6eaa3 4090 if (irqchip_in_kernel(kvm))
3ddea128 4091 goto create_irqchip_unlock;
09941366 4092
3e515705 4093 r = -EINVAL;
557abc40 4094 if (kvm->created_vcpus)
3e515705 4095 goto create_irqchip_unlock;
09941366
RK		 4096
4097 r = kvm_pic_init(kvm);
4098 if (r)
3ddea128 4099 goto create_irqchip_unlock;
09941366
RK		 4100
4101 r = kvm_ioapic_init(kvm);
4102 if (r) {
09941366 4103 kvm_pic_destroy(kvm);
3ddea128 4104 goto create_irqchip_unlock;
09941366
RK		 4105 }
4106
399ec807
AK		 4107 r = kvm_setup_default_irq_routing(kvm);
4108 if (r) {
72bb2fcd 4109 kvm_ioapic_destroy(kvm);
09941366 4110 kvm_pic_destroy(kvm);
71ba994c 4111 goto create_irqchip_unlock;
399ec807 4112 }
49776faf 4113 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4114 smp_wmb();
49776faf 4115 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4116 create_irqchip_unlock:
4117 mutex_unlock(&kvm->lock);
1fe779f8 4118 break;
3ddea128 4119 }
7837699f 4120 case KVM_CREATE_PIT:
c5ff41ce
JK		 4121 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4122 goto create_pit;
4123 case KVM_CREATE_PIT2:
4124 r = -EFAULT;
4125 if (copy_from_user(&u.pit_config, argp,
4126 sizeof(struct kvm_pit_config)))
4127 goto out;
4128 create_pit:
250715a6 4129 mutex_lock(&kvm->lock);
269e05e4
AK		 4130 r = -EEXIST;
4131 if (kvm->arch.vpit)
4132 goto create_pit_unlock;
7837699f 4133 r = -ENOMEM;
c5ff41ce 4134 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4135 if (kvm->arch.vpit)
4136 r = 0;
269e05e4 4137 create_pit_unlock:
250715a6 4138 mutex_unlock(&kvm->lock);
7837699f 4139 break;
1fe779f8
CO		 4140 case KVM_GET_IRQCHIP: {
4141 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4142 struct kvm_irqchip *chip;
1fe779f8 4143
ff5c2c03
SL		 4144 chip = memdup_user(argp, sizeof(*chip));
4145 if (IS_ERR(chip)) {
4146 r = PTR_ERR(chip);
1fe779f8 4147 goto out;
ff5c2c03
SL		 4148 }
4149
1fe779f8 4150 r = -ENXIO;
826da321 4151 if (!irqchip_kernel(kvm))
f0d66275
DH		 4152 goto get_irqchip_out;
4153 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4154 if (r)
f0d66275 4155 goto get_irqchip_out;
1fe779f8 4156 r = -EFAULT;
f0d66275
DH		 4157 if (copy_to_user(argp, chip, sizeof *chip))
4158 goto get_irqchip_out;
1fe779f8 4159 r = 0;
f0d66275
DH		 4160 get_irqchip_out:
4161 kfree(chip);
1fe779f8
CO		 4162 break;
4163 }
4164 case KVM_SET_IRQCHIP: {
4165 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4166 struct kvm_irqchip *chip;
1fe779f8 4167
ff5c2c03
SL		 4168 chip = memdup_user(argp, sizeof(*chip));
4169 if (IS_ERR(chip)) {
4170 r = PTR_ERR(chip);
1fe779f8 4171 goto out;
ff5c2c03
SL		 4172 }
4173
1fe779f8 4174 r = -ENXIO;
826da321 4175 if (!irqchip_kernel(kvm))
f0d66275
DH		 4176 goto set_irqchip_out;
4177 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4178 if (r)
f0d66275 4179 goto set_irqchip_out;
1fe779f8 4180 r = 0;
f0d66275
DH		 4181 set_irqchip_out:
4182 kfree(chip);
1fe779f8
CO		 4183 break;
4184 }
e0f63cb9 4185 case KVM_GET_PIT: {
e0f63cb9 4186 r = -EFAULT;
f0d66275 4187 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4188 goto out;
4189 r = -ENXIO;
4190 if (!kvm->arch.vpit)
4191 goto out;
f0d66275 4192 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4193 if (r)
4194 goto out;
4195 r = -EFAULT;
f0d66275 4196 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4197 goto out;
4198 r = 0;
4199 break;
4200 }
4201 case KVM_SET_PIT: {
e0f63cb9 4202 r = -EFAULT;
f0d66275 4203 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4204 goto out;
4205 r = -ENXIO;
4206 if (!kvm->arch.vpit)
4207 goto out;
f0d66275 4208 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4209 break;
4210 }
e9f42757
BK		 4211 case KVM_GET_PIT2: {
4212 r = -ENXIO;
4213 if (!kvm->arch.vpit)
4214 goto out;
4215 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4216 if (r)
4217 goto out;
4218 r = -EFAULT;
4219 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4220 goto out;
4221 r = 0;
4222 break;
4223 }
4224 case KVM_SET_PIT2: {
4225 r = -EFAULT;
4226 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4227 goto out;
4228 r = -ENXIO;
4229 if (!kvm->arch.vpit)
4230 goto out;
4231 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4232 break;
4233 }
52d939a0
MT		 4234 case KVM_REINJECT_CONTROL: {
4235 struct kvm_reinject_control control;
4236 r = -EFAULT;
4237 if (copy_from_user(&control, argp, sizeof(control)))
4238 goto out;
4239 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4240 break;
4241 }
d71ba788
PB		 4242 case KVM_SET_BOOT_CPU_ID:
4243 r = 0;
4244 mutex_lock(&kvm->lock);
557abc40 4245 if (kvm->created_vcpus)
d71ba788
PB		 4246 r = -EBUSY;
4247 else
4248 kvm->arch.bsp_vcpu_id = arg;
4249 mutex_unlock(&kvm->lock);
4250 break;
ffde22ac
ES		 4251 case KVM_XEN_HVM_CONFIG: {
4252 r = -EFAULT;
4253 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4254 sizeof(struct kvm_xen_hvm_config)))
4255 goto out;
4256 r = -EINVAL;
4257 if (kvm->arch.xen_hvm_config.flags)
4258 goto out;
4259 r = 0;
4260 break;
4261 }
afbcf7ab 4262 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4263 struct kvm_clock_data user_ns;
4264 u64 now_ns;
afbcf7ab
GC		 4265
4266 r = -EFAULT;
4267 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4268 goto out;
4269
4270 r = -EINVAL;
4271 if (user_ns.flags)
4272 goto out;
4273
4274 r = 0;
0bc48bea
RK		 4275 /*
4276 * TODO: userspace has to take care of races with VCPU_RUN, so
4277 * kvm_gen_update_masterclock() can be cut down to locked
4278 * pvclock_update_vm_gtod_copy().
4279 */
4280 kvm_gen_update_masterclock(kvm);
e891a32e 4281 now_ns = get_kvmclock_ns(kvm);
108b249c 4282 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4283 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4284 break;
4285 }
4286 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4287 struct kvm_clock_data user_ns;
4288 u64 now_ns;
4289
e891a32e 4290 now_ns = get_kvmclock_ns(kvm);
108b249c 4291 user_ns.clock = now_ns;
e3fd9a93 4292 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4293 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4294
4295 r = -EFAULT;
4296 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4297 goto out;
4298 r = 0;
4299 break;
4300 }
90de4a18
NA		 4301 case KVM_ENABLE_CAP: {
4302 struct kvm_enable_cap cap;
afbcf7ab 4303
90de4a18
NA		 4304 r = -EFAULT;
4305 if (copy_from_user(&cap, argp, sizeof(cap)))
4306 goto out;
4307 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4308 break;
4309 }
1fe779f8 4310 default:
ad6260da 4311 r = -ENOTTY;
1fe779f8
CO		 4312 }
4313out:
4314 return r;
4315}
4316
a16b043c 4317static void kvm_init_msr_list(void)
043405e1
CO		 4318{
4319 u32 dummy[2];
4320 unsigned i, j;
4321
62ef68bb 4322 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4323 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4324 continue;
93c4adc7
PB		 4325
4326 /*
4327 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4328 * to the guests in some cases.
93c4adc7
PB		 4329 */
4330 switch (msrs_to_save[i]) {
4331 case MSR_IA32_BNDCFGS:
4332 if (!kvm_x86_ops->mpx_supported())
4333 continue;
4334 break;
9dbe6cf9
PB		 4335 case MSR_TSC_AUX:
4336 if (!kvm_x86_ops->rdtscp_supported())
4337 continue;
4338 break;
93c4adc7
PB		 4339 default:
4340 break;
4341 }
4342
043405e1
CO		 4343 if (j < i)
4344 msrs_to_save[j] = msrs_to_save[i];
4345 j++;
4346 }
4347 num_msrs_to_save = j;
62ef68bb
PB		 4348
4349 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4350 switch (emulated_msrs[i]) {
6d396b55
PB		 4351 case MSR_IA32_SMBASE:
4352 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4353 continue;
4354 break;
62ef68bb
PB		 4355 default:
4356 break;
4357 }
4358
4359 if (j < i)
4360 emulated_msrs[j] = emulated_msrs[i];
4361 j++;
4362 }
4363 num_emulated_msrs = j;
043405e1
CO		 4364}
4365
bda9020e
MT		 4366static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4367 const void *v)
bbd9b64e 4368{
70252a10
AK		 4369 int handled = 0;
4370 int n;
4371
4372 do {
4373 n = min(len, 8);
bce87cce 4374 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4375 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4376 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4377 break;
4378 handled += n;
4379 addr += n;
4380 len -= n;
4381 v += n;
4382 } while (len);
bbd9b64e 4383
70252a10 4384 return handled;
bbd9b64e
CO		 4385}
4386
bda9020e 4387static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4388{
70252a10
AK		 4389 int handled = 0;
4390 int n;
4391
4392 do {
4393 n = min(len, 8);
bce87cce 4394 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4395 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4396 addr, n, v))
4397 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4398 break;
4399 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4400 handled += n;
4401 addr += n;
4402 len -= n;
4403 v += n;
4404 } while (len);
bbd9b64e 4405
70252a10 4406 return handled;
bbd9b64e
CO		 4407}
4408
2dafc6c2
GN		 4409static void kvm_set_segment(struct kvm_vcpu *vcpu,
4410 struct kvm_segment *var, int seg)
4411{
4412 kvm_x86_ops->set_segment(vcpu, var, seg);
4413}
4414
4415void kvm_get_segment(struct kvm_vcpu *vcpu,
4416 struct kvm_segment *var, int seg)
4417{
4418 kvm_x86_ops->get_segment(vcpu, var, seg);
4419}
4420
54987b7a
PB		 4421gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4422 struct x86_exception *exception)
02f59dc9
JR		 4423{
4424 gpa_t t_gpa;
02f59dc9
JR		 4425
4426 BUG_ON(!mmu_is_nested(vcpu));
4427
4428 /* NPT walks are always user-walks */
4429 access |= PFERR_USER_MASK;
54987b7a 4430 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4431
4432 return t_gpa;
4433}
4434
ab9ae313
AK		 4435gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4436 struct x86_exception *exception)
1871c602
GN		 4437{
4438 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4439 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4440}
4441
ab9ae313
AK		 4442 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4443 struct x86_exception *exception)
1871c602
GN		 4444{
4445 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4446 access |= PFERR_FETCH_MASK;
ab9ae313 4447 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4448}
4449
ab9ae313
AK		 4450gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4451 struct x86_exception *exception)
1871c602
GN		 4452{
4453 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4454 access |= PFERR_WRITE_MASK;
ab9ae313 4455 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4456}
4457
4458/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4459gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4460 struct x86_exception *exception)
1871c602 4461{
ab9ae313 4462 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4463}
4464
4465static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4466 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4467 struct x86_exception *exception)
bbd9b64e
CO		 4468{
4469 void *data = val;
10589a46 4470 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4471
4472 while (bytes) {
14dfe855 4473 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4474 exception);
bbd9b64e 4475 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4476 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4477 int ret;
4478
bcc55cba 4479 if (gpa == UNMAPPED_GVA)
ab9ae313 4480 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4481 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4482 offset, toread);
10589a46 4483 if (ret < 0) {
c3cd7ffa 4484 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4485 goto out;
4486 }
bbd9b64e 4487
77c2002e
IE		 4488 bytes -= toread;
4489 data += toread;
4490 addr += toread;
bbd9b64e 4491 }
10589a46 4492out:
10589a46 4493 return r;
bbd9b64e 4494}
77c2002e 4495
1871c602 4496/* used for instruction fetching */
0f65dd70
AK		 4497static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4498 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4499 struct x86_exception *exception)
1871c602 4500{
0f65dd70 4501 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4502 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4503 unsigned offset;
4504 int ret;
0f65dd70 4505
44583cba
PB		 4506 /* Inline kvm_read_guest_virt_helper for speed. */
4507 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4508 exception);
4509 if (unlikely(gpa == UNMAPPED_GVA))
4510 return X86EMUL_PROPAGATE_FAULT;
4511
4512 offset = addr & (PAGE_SIZE-1);
4513 if (WARN_ON(offset + bytes > PAGE_SIZE))
4514 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4515 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4516 offset, bytes);
44583cba
PB		 4517 if (unlikely(ret < 0))
4518 return X86EMUL_IO_NEEDED;
4519
4520 return X86EMUL_CONTINUE;
1871c602
GN		 4521}
4522
064aea77 4523int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4524 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4525 struct x86_exception *exception)
1871c602 4526{
0f65dd70 4527 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4528 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4529
1871c602 4530 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4531 exception);
1871c602 4532}
064aea77 4533EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4534
0f65dd70
AK		 4535static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4536 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4537 struct x86_exception *exception)
1871c602 4538{
0f65dd70 4539 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4540 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4541}
4542
7a036a6f
RK		 4543static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4544 unsigned long addr, void *val, unsigned int bytes)
4545{
4546 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4547 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4548
4549 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4550}
4551
6a4d7550 4552int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4553 gva_t addr, void *val,
2dafc6c2 4554 unsigned int bytes,
bcc55cba 4555 struct x86_exception *exception)
77c2002e 4556{
0f65dd70 4557 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4558 void *data = val;
4559 int r = X86EMUL_CONTINUE;
4560
4561 while (bytes) {
14dfe855
JR		 4562 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4563 PFERR_WRITE_MASK,
ab9ae313 4564 exception);
77c2002e
IE		 4565 unsigned offset = addr & (PAGE_SIZE-1);
4566 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4567 int ret;
4568
bcc55cba 4569 if (gpa == UNMAPPED_GVA)
ab9ae313 4570 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4571 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4572 if (ret < 0) {
c3cd7ffa 4573 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4574 goto out;
4575 }
4576
4577 bytes -= towrite;
4578 data += towrite;
4579 addr += towrite;
4580 }
4581out:
4582 return r;
4583}
6a4d7550 4584EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4585
0f89b207
TL		 4586static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4587 gpa_t gpa, bool write)
4588{
4589 /* For APIC access vmexit */
4590 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4591 return 1;
4592
4593 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4594 trace_vcpu_match_mmio(gva, gpa, write, true);
4595 return 1;
4596 }
4597
4598 return 0;
4599}
4600
af7cc7d1
XG		 4601static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4602 gpa_t *gpa, struct x86_exception *exception,
4603 bool write)
4604{
97d64b78
AK		 4605 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4606 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4607
be94f6b7
HH		 4608 /*
4609 * currently PKRU is only applied to ept enabled guest so
4610 * there is no pkey in EPT page table for L1 guest or EPT
4611 * shadow page table for L2 guest.
4612 */
97d64b78 4613 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4614 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4615 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4616 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4617 (gva & (PAGE_SIZE - 1));
4f022648 4618 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4619 return 1;
4620 }
4621
af7cc7d1
XG		 4622 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4623
4624 if (*gpa == UNMAPPED_GVA)
4625 return -1;
4626
0f89b207 4627 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4628}
4629
3200f405 4630int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4631 const void *val, int bytes)
bbd9b64e
CO		 4632{
4633 int ret;
4634
54bf36aa 4635 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4636 if (ret < 0)
bbd9b64e 4637 return 0;
0eb05bf2 4638 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4639 return 1;
4640}
4641
77d197b2
XG		 4642struct read_write_emulator_ops {
4643 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4644 int bytes);
4645 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4646 void *val, int bytes);
4647 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4648 int bytes, void *val);
4649 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4650 void *val, int bytes);
4651 bool write;
4652};
4653
4654static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4655{
4656 if (vcpu->mmio_read_completed) {
77d197b2 4657 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4658 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4659 vcpu->mmio_read_completed = 0;
4660 return 1;
4661 }
4662
4663 return 0;
4664}
4665
4666static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4667 void *val, int bytes)
4668{
54bf36aa 4669 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4670}
4671
4672static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4673 void *val, int bytes)
4674{
4675 return emulator_write_phys(vcpu, gpa, val, bytes);
4676}
4677
4678static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4679{
4680 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4681 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4682}
4683
4684static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4685 void *val, int bytes)
4686{
4687 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4688 return X86EMUL_IO_NEEDED;
4689}
4690
4691static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4692 void *val, int bytes)
4693{
f78146b0
AK		 4694 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4695
87da7e66 4696 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4697 return X86EMUL_CONTINUE;
4698}
4699
0fbe9b0b 4700static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4701 .read_write_prepare = read_prepare,
4702 .read_write_emulate = read_emulate,
4703 .read_write_mmio = vcpu_mmio_read,
4704 .read_write_exit_mmio = read_exit_mmio,
4705};
4706
0fbe9b0b 4707static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4708 .read_write_emulate = write_emulate,
4709 .read_write_mmio = write_mmio,
4710 .read_write_exit_mmio = write_exit_mmio,
4711 .write = true,
4712};
4713
22388a3c
XG		 4714static int emulator_read_write_onepage(unsigned long addr, void *val,
4715 unsigned int bytes,
4716 struct x86_exception *exception,
4717 struct kvm_vcpu *vcpu,
0fbe9b0b 4718 const struct read_write_emulator_ops *ops)
bbd9b64e 4719{
af7cc7d1
XG		 4720 gpa_t gpa;
4721 int handled, ret;
22388a3c 4722 bool write = ops->write;
f78146b0 4723 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4724 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4725
4726 /*
4727 * If the exit was due to a NPF we may already have a GPA.
4728 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4729 * Note, this cannot be used on string operations since string
4730 * operation using rep will only have the initial GPA from the NPF
4731 * occurred.
4732 */
4733 if (vcpu->arch.gpa_available &&
4734 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4735 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4736 gpa = vcpu->arch.gpa_val;
4737 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4738 } else {
4739 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4740 if (ret < 0)
4741 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4742 }
10589a46 4743
618232e2 4744 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4745 return X86EMUL_CONTINUE;
4746
bbd9b64e
CO		 4747 /*
4748 * Is this MMIO handled locally?
4749 */
22388a3c 4750 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4751 if (handled == bytes)
bbd9b64e 4752 return X86EMUL_CONTINUE;
bbd9b64e 4753
70252a10
AK		 4754 gpa += handled;
4755 bytes -= handled;
4756 val += handled;
4757
87da7e66
XG		 4758 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4759 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4760 frag->gpa = gpa;
4761 frag->data = val;
4762 frag->len = bytes;
f78146b0 4763 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4764}
4765
52eb5a6d
XL		 4766static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4767 unsigned long addr,
22388a3c
XG		 4768 void *val, unsigned int bytes,
4769 struct x86_exception *exception,
0fbe9b0b 4770 const struct read_write_emulator_ops *ops)
bbd9b64e 4771{
0f65dd70 4772 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4773 gpa_t gpa;
4774 int rc;
4775
4776 if (ops->read_write_prepare &&
4777 ops->read_write_prepare(vcpu, val, bytes))
4778 return X86EMUL_CONTINUE;
4779
4780 vcpu->mmio_nr_fragments = 0;
0f65dd70 4781
bbd9b64e
CO		 4782 /* Crossing a page boundary? */
4783 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4784 int now;
bbd9b64e
CO		 4785
4786 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4787 rc = emulator_read_write_onepage(addr, val, now, exception,
4788 vcpu, ops);
4789
bbd9b64e
CO		 4790 if (rc != X86EMUL_CONTINUE)
4791 return rc;
4792 addr += now;
bac15531
NA		 4793 if (ctxt->mode != X86EMUL_MODE_PROT64)
4794 addr = (u32)addr;
bbd9b64e
CO		 4795 val += now;
4796 bytes -= now;
4797 }
22388a3c 4798
f78146b0
AK		 4799 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4800 vcpu, ops);
4801 if (rc != X86EMUL_CONTINUE)
4802 return rc;
4803
4804 if (!vcpu->mmio_nr_fragments)
4805 return rc;
4806
4807 gpa = vcpu->mmio_fragments[0].gpa;
4808
4809 vcpu->mmio_needed = 1;
4810 vcpu->mmio_cur_fragment = 0;
4811
87da7e66 4812 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4813 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4814 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4815 vcpu->run->mmio.phys_addr = gpa;
4816
4817 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4818}
4819
4820static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4821 unsigned long addr,
4822 void *val,
4823 unsigned int bytes,
4824 struct x86_exception *exception)
4825{
4826 return emulator_read_write(ctxt, addr, val, bytes,
4827 exception, &read_emultor);
4828}
4829
52eb5a6d 4830static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4831 unsigned long addr,
4832 const void *val,
4833 unsigned int bytes,
4834 struct x86_exception *exception)
4835{
4836 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4837 exception, &write_emultor);
bbd9b64e 4838}
bbd9b64e 4839
daea3e73
AK		 4840#define CMPXCHG_TYPE(t, ptr, old, new) \
4841 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4842
4843#ifdef CONFIG_X86_64
4844# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4845#else
4846# define CMPXCHG64(ptr, old, new) \
9749a6c0 4847 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4848#endif
4849
0f65dd70
AK		 4850static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4851 unsigned long addr,
bbd9b64e
CO		 4852 const void *old,
4853 const void *new,
4854 unsigned int bytes,
0f65dd70 4855 struct x86_exception *exception)
bbd9b64e 4856{
0f65dd70 4857 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4858 gpa_t gpa;
4859 struct page *page;
4860 char *kaddr;
4861 bool exchanged;
2bacc55c 4862
daea3e73
AK		 4863 /* guests cmpxchg8b have to be emulated atomically */
4864 if (bytes > 8 || (bytes & (bytes - 1)))
4865 goto emul_write;
10589a46 4866
daea3e73 4867 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4868
daea3e73
AK		 4869 if (gpa == UNMAPPED_GVA ||
4870 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4871 goto emul_write;
2bacc55c 4872
daea3e73
AK		 4873 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4874 goto emul_write;
72dc67a6 4875
54bf36aa 4876 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4877 if (is_error_page(page))
c19b8bd6 4878 goto emul_write;
72dc67a6 4879
8fd75e12 4880 kaddr = kmap_atomic(page);
daea3e73
AK		 4881 kaddr += offset_in_page(gpa);
4882 switch (bytes) {
4883 case 1:
4884 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4885 break;
4886 case 2:
4887 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4888 break;
4889 case 4:
4890 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4891 break;
4892 case 8:
4893 exchanged = CMPXCHG64(kaddr, old, new);
4894 break;
4895 default:
4896 BUG();
2bacc55c 4897 }
8fd75e12 4898 kunmap_atomic(kaddr);
daea3e73
AK		 4899 kvm_release_page_dirty(page);
4900
4901 if (!exchanged)
4902 return X86EMUL_CMPXCHG_FAILED;
4903
54bf36aa 4904 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4905 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4906
4907 return X86EMUL_CONTINUE;
4a5f48f6 4908
3200f405 4909emul_write:
daea3e73 4910 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4911
0f65dd70 4912 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4913}
4914
cf8f70bf
GN		 4915static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4916{
cbfc6c91 4917 int r = 0, i;
cf8f70bf 4918
cbfc6c91
WL		 4919 for (i = 0; i < vcpu->arch.pio.count; i++) {
4920 if (vcpu->arch.pio.in)
4921 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4922 vcpu->arch.pio.size, pd);
4923 else
4924 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4925 vcpu->arch.pio.port, vcpu->arch.pio.size,
4926 pd);
4927 if (r)
4928 break;
4929 pd += vcpu->arch.pio.size;
4930 }
cf8f70bf
GN		 4931 return r;
4932}
4933
6f6fbe98
XG		 4934static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4935 unsigned short port, void *val,
4936 unsigned int count, bool in)
cf8f70bf 4937{
cf8f70bf 4938 vcpu->arch.pio.port = port;
6f6fbe98 4939 vcpu->arch.pio.in = in;
7972995b 4940 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4941 vcpu->arch.pio.size = size;
4942
4943 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4944 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4945 return 1;
4946 }
4947
4948 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4949 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4950 vcpu->run->io.size = size;
4951 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4952 vcpu->run->io.count = count;
4953 vcpu->run->io.port = port;
4954
4955 return 0;
4956}
4957
6f6fbe98
XG		 4958static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4959 int size, unsigned short port, void *val,
4960 unsigned int count)
cf8f70bf 4961{
ca1d4a9e 4962 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4963 int ret;
ca1d4a9e 4964
6f6fbe98
XG		 4965 if (vcpu->arch.pio.count)
4966 goto data_avail;
cf8f70bf 4967
cbfc6c91
WL		 4968 memset(vcpu->arch.pio_data, 0, size * count);
4969
6f6fbe98
XG		 4970 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4971 if (ret) {
4972data_avail:
4973 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4974 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4975 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4976 return 1;
4977 }
4978
cf8f70bf
GN		 4979 return 0;
4980}
4981
6f6fbe98
XG		 4982static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4983 int size, unsigned short port,
4984 const void *val, unsigned int count)
4985{
4986 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4987
4988 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4989 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4990 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4991}
4992
bbd9b64e
CO		 4993static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4994{
4995 return kvm_x86_ops->get_segment_base(vcpu, seg);
4996}
4997
3cb16fe7 4998static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4999{
3cb16fe7 5000 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5001}
5002
ae6a2375 5003static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5004{
5005 if (!need_emulate_wbinvd(vcpu))
5006 return X86EMUL_CONTINUE;
5007
5008 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5009 int cpu = get_cpu();
5010
5011 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5012 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5013 wbinvd_ipi, NULL, 1);
2eec7343 5014 put_cpu();
f5f48ee1 5015 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5016 } else
5017 wbinvd();
f5f48ee1
SY		 5018 return X86EMUL_CONTINUE;
5019}
5cb56059
JS		 5020
5021int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5022{
6affcbed
KH		 5023 kvm_emulate_wbinvd_noskip(vcpu);
5024 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5025}
f5f48ee1
SY		 5026EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5027
5cb56059
JS		 5028
5029
bcaf5cc5
AK		 5030static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5031{
5cb56059 5032 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5033}
5034
52eb5a6d
XL		 5035static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5036 unsigned long *dest)
bbd9b64e 5037{
16f8a6f9 5038 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5039}
5040
52eb5a6d
XL		 5041static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5042 unsigned long value)
bbd9b64e 5043{
338dbc97 5044
717746e3 5045 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5046}
5047
52a46617 5048static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5049{
52a46617 5050 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5051}
5052
717746e3 5053static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5054{
717746e3 5055 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5056 unsigned long value;
5057
5058 switch (cr) {
5059 case 0:
5060 value = kvm_read_cr0(vcpu);
5061 break;
5062 case 2:
5063 value = vcpu->arch.cr2;
5064 break;
5065 case 3:
9f8fe504 5066 value = kvm_read_cr3(vcpu);
52a46617
GN		 5067 break;
5068 case 4:
5069 value = kvm_read_cr4(vcpu);
5070 break;
5071 case 8:
5072 value = kvm_get_cr8(vcpu);
5073 break;
5074 default:
a737f256 5075 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5076 return 0;
5077 }
5078
5079 return value;
5080}
5081
717746e3 5082static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5083{
717746e3 5084 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5085 int res = 0;
5086
52a46617
GN		 5087 switch (cr) {
5088 case 0:
49a9b07e 5089 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5090 break;
5091 case 2:
5092 vcpu->arch.cr2 = val;
5093 break;
5094 case 3:
2390218b 5095 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5096 break;
5097 case 4:
a83b29c6 5098 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5099 break;
5100 case 8:
eea1cff9 5101 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5102 break;
5103 default:
a737f256 5104 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5105 res = -1;
52a46617 5106 }
0f12244f
GN		 5107
5108 return res;
52a46617
GN		 5109}
5110
717746e3 5111static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5112{
717746e3 5113 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5114}
5115
4bff1e86 5116static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5117{
4bff1e86 5118 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5119}
5120
4bff1e86 5121static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5122{
4bff1e86 5123 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5124}
5125
1ac9d0cf
AK		 5126static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5127{
5128 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5129}
5130
5131static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5132{
5133 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5134}
5135
4bff1e86
AK		 5136static unsigned long emulator_get_cached_segment_base(
5137 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5138{
4bff1e86 5139 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5140}
5141
1aa36616
AK		 5142static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5143 struct desc_struct *desc, u32 *base3,
5144 int seg)
2dafc6c2
GN		 5145{
5146 struct kvm_segment var;
5147
4bff1e86 5148 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5149 *selector = var.selector;
2dafc6c2 5150
378a8b09
GN		 5151 if (var.unusable) {
5152 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5153 if (base3)
5154 *base3 = 0;
2dafc6c2 5155 return false;
378a8b09 5156 }
2dafc6c2
GN		 5157
5158 if (var.g)
5159 var.limit >>= 12;
5160 set_desc_limit(desc, var.limit);
5161 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5162#ifdef CONFIG_X86_64
5163 if (base3)
5164 *base3 = var.base >> 32;
5165#endif
2dafc6c2
GN		 5166 desc->type = var.type;
5167 desc->s = var.s;
5168 desc->dpl = var.dpl;
5169 desc->p = var.present;
5170 desc->avl = var.avl;
5171 desc->l = var.l;
5172 desc->d = var.db;
5173 desc->g = var.g;
5174
5175 return true;
5176}
5177
1aa36616
AK		 5178static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5179 struct desc_struct *desc, u32 base3,
5180 int seg)
2dafc6c2 5181{
4bff1e86 5182 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5183 struct kvm_segment var;
5184
1aa36616 5185 var.selector = selector;
2dafc6c2 5186 var.base = get_desc_base(desc);
5601d05b
GN		 5187#ifdef CONFIG_X86_64
5188 var.base |= ((u64)base3) << 32;
5189#endif
2dafc6c2
GN		 5190 var.limit = get_desc_limit(desc);
5191 if (desc->g)
5192 var.limit = (var.limit << 12) | 0xfff;
5193 var.type = desc->type;
2dafc6c2
GN		 5194 var.dpl = desc->dpl;
5195 var.db = desc->d;
5196 var.s = desc->s;
5197 var.l = desc->l;
5198 var.g = desc->g;
5199 var.avl = desc->avl;
5200 var.present = desc->p;
5201 var.unusable = !var.present;
5202 var.padding = 0;
5203
5204 kvm_set_segment(vcpu, &var, seg);
5205 return;
5206}
5207
717746e3
AK		 5208static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5209 u32 msr_index, u64 *pdata)
5210{
609e36d3
PB		 5211 struct msr_data msr;
5212 int r;
5213
5214 msr.index = msr_index;
5215 msr.host_initiated = false;
5216 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5217 if (r)
5218 return r;
5219
5220 *pdata = msr.data;
5221 return 0;
717746e3
AK		 5222}
5223
5224static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5225 u32 msr_index, u64 data)
5226{
8fe8ab46
WA		 5227 struct msr_data msr;
5228
5229 msr.data = data;
5230 msr.index = msr_index;
5231 msr.host_initiated = false;
5232 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5233}
5234
64d60670
PB		 5235static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5236{
5237 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5238
5239 return vcpu->arch.smbase;
5240}
5241
5242static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5243{
5244 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5245
5246 vcpu->arch.smbase = smbase;
5247}
5248
67f4d428
NA		 5249static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5250 u32 pmc)
5251{
c6702c9d 5252 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5253}
5254
222d21aa
AK		 5255static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5256 u32 pmc, u64 *pdata)
5257{
c6702c9d 5258 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5259}
5260
6c3287f7
AK		 5261static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5262{
5263 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5264}
5265
2953538e 5266static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5267 struct x86_instruction_info *info,
c4f035c6
AK		 5268 enum x86_intercept_stage stage)
5269{
2953538e 5270 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5271}
5272
e911eb3b
YZ		 5273static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5274 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5275{
e911eb3b 5276 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5277}
5278
dd856efa
AK		 5279static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5280{
5281 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5282}
5283
5284static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5285{
5286 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5287}
5288
801806d9
NA		 5289static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5290{
5291 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5292}
5293
6ed071f0
LP		 5294static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5295{
5296 return emul_to_vcpu(ctxt)->arch.hflags;
5297}
5298
5299static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5300{
5301 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5302}
5303
0234bf88
LP		 5304static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5305{
5306 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5307}
5308
0225fb50 5309static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5310 .read_gpr = emulator_read_gpr,
5311 .write_gpr = emulator_write_gpr,
1871c602 5312 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5313 .write_std = kvm_write_guest_virt_system,
7a036a6f 5314 .read_phys = kvm_read_guest_phys_system,
1871c602 5315 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5316 .read_emulated = emulator_read_emulated,
5317 .write_emulated = emulator_write_emulated,
5318 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5319 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5320 .pio_in_emulated = emulator_pio_in_emulated,
5321 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5322 .get_segment = emulator_get_segment,
5323 .set_segment = emulator_set_segment,
5951c442 5324 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5325 .get_gdt = emulator_get_gdt,
160ce1f1 5326 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5327 .set_gdt = emulator_set_gdt,
5328 .set_idt = emulator_set_idt,
52a46617
GN		 5329 .get_cr = emulator_get_cr,
5330 .set_cr = emulator_set_cr,
9c537244 5331 .cpl = emulator_get_cpl,
35aa5375
GN		 5332 .get_dr = emulator_get_dr,
5333 .set_dr = emulator_set_dr,
64d60670
PB		 5334 .get_smbase = emulator_get_smbase,
5335 .set_smbase = emulator_set_smbase,
717746e3
AK		 5336 .set_msr = emulator_set_msr,
5337 .get_msr = emulator_get_msr,
67f4d428 5338 .check_pmc = emulator_check_pmc,
222d21aa 5339 .read_pmc = emulator_read_pmc,
6c3287f7 5340 .halt = emulator_halt,
bcaf5cc5 5341 .wbinvd = emulator_wbinvd,
d6aa1000 5342 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5343 .intercept = emulator_intercept,
bdb42f5a 5344 .get_cpuid = emulator_get_cpuid,
801806d9 5345 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5346 .get_hflags = emulator_get_hflags,
5347 .set_hflags = emulator_set_hflags,
0234bf88 5348 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5349};
5350
95cb2295
GN		 5351static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5352{
37ccdcbe 5353 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5354 /*
5355 * an sti; sti; sequence only disable interrupts for the first
5356 * instruction. So, if the last instruction, be it emulated or
5357 * not, left the system with the INT_STI flag enabled, it
5358 * means that the last instruction is an sti. We should not
5359 * leave the flag on in this case. The same goes for mov ss
5360 */
37ccdcbe
PB		 5361 if (int_shadow & mask)
5362 mask = 0;
6addfc42 5363 if (unlikely(int_shadow || mask)) {
95cb2295 5364 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5365 if (!mask)
5366 kvm_make_request(KVM_REQ_EVENT, vcpu);
5367 }
95cb2295
GN		 5368}
5369
ef54bcfe 5370static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5371{
5372 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5373 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5374 return kvm_propagate_fault(vcpu, &ctxt->exception);
5375
5376 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5377 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5378 ctxt->exception.error_code);
54b8486f 5379 else
da9cb575 5380 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5381 return false;
54b8486f
GN		 5382}
5383
8ec4722d
MG		 5384static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5385{
adf52235 5386 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5387 int cs_db, cs_l;
5388
8ec4722d
MG		 5389 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5390
adf52235 5391 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5392 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5393
adf52235
TY		 5394 ctxt->eip = kvm_rip_read(vcpu);
5395 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5396 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5397 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5398 cs_db ? X86EMUL_MODE_PROT32 :
5399 X86EMUL_MODE_PROT16;
a584539b 5400 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5401 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5402 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5403
dd856efa 5404 init_decode_cache(ctxt);
7ae441ea 5405 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5406}
5407
71f9833b 5408int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5409{
9d74191a 5410 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5411 int ret;
5412
5413 init_emulate_ctxt(vcpu);
5414
9dac77fa
AK		 5415 ctxt->op_bytes = 2;
5416 ctxt->ad_bytes = 2;
5417 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5418 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5419
5420 if (ret != X86EMUL_CONTINUE)
5421 return EMULATE_FAIL;
5422
9dac77fa 5423 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5424 kvm_rip_write(vcpu, ctxt->eip);
5425 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5426
5427 if (irq == NMI_VECTOR)
7460fb4a 5428 vcpu->arch.nmi_pending = 0;
63995653
MG		 5429 else
5430 vcpu->arch.interrupt.pending = false;
5431
5432 return EMULATE_DONE;
5433}
5434EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5435
6d77dbfc
GN		 5436static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5437{
fc3a9157
JR		 5438 int r = EMULATE_DONE;
5439
6d77dbfc
GN		 5440 ++vcpu->stat.insn_emulation_fail;
5441 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5442 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5443 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5444 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5445 vcpu->run->internal.ndata = 0;
1f4dcb3b 5446 r = EMULATE_USER_EXIT;
fc3a9157 5447 }
6d77dbfc 5448 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5449
5450 return r;
6d77dbfc
GN		 5451}
5452
93c05d3e 5453static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5454 bool write_fault_to_shadow_pgtable,
5455 int emulation_type)
a6f177ef 5456{
95b3cf69 5457 gpa_t gpa = cr2;
ba049e93 5458 kvm_pfn_t pfn;
a6f177ef 5459
991eebf9
GN		 5460 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5461 return false;
5462
95b3cf69
XG		 5463 if (!vcpu->arch.mmu.direct_map) {
5464 /*
5465 * Write permission should be allowed since only
5466 * write access need to be emulated.
5467 */
5468 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5469
95b3cf69
XG		 5470 /*
5471 * If the mapping is invalid in guest, let cpu retry
5472 * it to generate fault.
5473 */
5474 if (gpa == UNMAPPED_GVA)
5475 return true;
5476 }
a6f177ef 5477
8e3d9d06
XG		 5478 /*
5479 * Do not retry the unhandleable instruction if it faults on the
5480 * readonly host memory, otherwise it will goto a infinite loop:
5481 * retry instruction -> write #PF -> emulation fail -> retry
5482 * instruction -> ...
5483 */
5484 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5485
5486 /*
5487 * If the instruction failed on the error pfn, it can not be fixed,
5488 * report the error to userspace.
5489 */
5490 if (is_error_noslot_pfn(pfn))
5491 return false;
5492
5493 kvm_release_pfn_clean(pfn);
5494
5495 /* The instructions are well-emulated on direct mmu. */
5496 if (vcpu->arch.mmu.direct_map) {
5497 unsigned int indirect_shadow_pages;
5498
5499 spin_lock(&vcpu->kvm->mmu_lock);
5500 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5501 spin_unlock(&vcpu->kvm->mmu_lock);
5502
5503 if (indirect_shadow_pages)
5504 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5505
a6f177ef 5506 return true;
8e3d9d06 5507 }
a6f177ef 5508
95b3cf69
XG		 5509 /*
5510 * if emulation was due to access to shadowed page table
5511 * and it failed try to unshadow page and re-enter the
5512 * guest to let CPU execute the instruction.
5513 */
5514 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5515
5516 /*
5517 * If the access faults on its page table, it can not
5518 * be fixed by unprotecting shadow page and it should
5519 * be reported to userspace.
5520 */
5521 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5522}
5523
1cb3f3ae
XG		 5524static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5525 unsigned long cr2, int emulation_type)
5526{
5527 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5528 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5529
5530 last_retry_eip = vcpu->arch.last_retry_eip;
5531 last_retry_addr = vcpu->arch.last_retry_addr;
5532
5533 /*
5534 * If the emulation is caused by #PF and it is non-page_table
5535 * writing instruction, it means the VM-EXIT is caused by shadow
5536 * page protected, we can zap the shadow page and retry this
5537 * instruction directly.
5538 *
5539 * Note: if the guest uses a non-page-table modifying instruction
5540 * on the PDE that points to the instruction, then we will unmap
5541 * the instruction and go to an infinite loop. So, we cache the
5542 * last retried eip and the last fault address, if we meet the eip
5543 * and the address again, we can break out of the potential infinite
5544 * loop.
5545 */
5546 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5547
5548 if (!(emulation_type & EMULTYPE_RETRY))
5549 return false;
5550
5551 if (x86_page_table_writing_insn(ctxt))
5552 return false;
5553
5554 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5555 return false;
5556
5557 vcpu->arch.last_retry_eip = ctxt->eip;
5558 vcpu->arch.last_retry_addr = cr2;
5559
5560 if (!vcpu->arch.mmu.direct_map)
5561 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5562
22368028 5563 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5564
5565 return true;
5566}
5567
716d51ab
GN		 5568static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5569static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5570
64d60670 5571static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5572{
64d60670 5573 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5574 /* This is a good place to trace that we are exiting SMM. */
5575 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5576
c43203ca
PB		 5577 /* Process a latched INIT or SMI, if any. */
5578 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5579 }
699023e2
PB		 5580
5581 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5582}
5583
5584static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5585{
5586 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5587
a584539b 5588 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5589
5590 if (changed & HF_SMM_MASK)
5591 kvm_smm_changed(vcpu);
a584539b
PB		 5592}
5593
4a1e10d5
PB		 5594static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5595 unsigned long *db)
5596{
5597 u32 dr6 = 0;
5598 int i;
5599 u32 enable, rwlen;
5600
5601 enable = dr7;
5602 rwlen = dr7 >> 16;
5603 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5604 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5605 dr6 |= (1 << i);
5606 return dr6;
5607}
5608
c8401dda 5609static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5610{
5611 struct kvm_run *kvm_run = vcpu->run;
5612
c8401dda
PB		 5613 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5614 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5615 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5616 kvm_run->debug.arch.exception = DB_VECTOR;
5617 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5618 *r = EMULATE_USER_EXIT;
5619 } else {
5620 /*
5621 * "Certain debug exceptions may clear bit 0-3. The
5622 * remaining contents of the DR6 register are never
5623 * cleared by the processor".
5624 */
5625 vcpu->arch.dr6 &= ~15;
5626 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5627 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5628 }
5629}
5630
6affcbed
KH		 5631int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5632{
5633 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5634 int r = EMULATE_DONE;
5635
5636 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5637
5638 /*
5639 * rflags is the old, "raw" value of the flags. The new value has
5640 * not been saved yet.
5641 *
5642 * This is correct even for TF set by the guest, because "the
5643 * processor will not generate this exception after the instruction
5644 * that sets the TF flag".
5645 */
5646 if (unlikely(rflags & X86_EFLAGS_TF))
5647 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5648 return r == EMULATE_DONE;
5649}
5650EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5651
4a1e10d5
PB		 5652static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5653{
4a1e10d5
PB		 5654 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5655 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5656 struct kvm_run *kvm_run = vcpu->run;
5657 unsigned long eip = kvm_get_linear_rip(vcpu);
5658 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5659 vcpu->arch.guest_debug_dr7,
5660 vcpu->arch.eff_db);
5661
5662 if (dr6 != 0) {
6f43ed01 5663 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5664 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5665 kvm_run->debug.arch.exception = DB_VECTOR;
5666 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5667 *r = EMULATE_USER_EXIT;
5668 return true;
5669 }
5670 }
5671
4161a569
NA		 5672 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5673 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5674 unsigned long eip = kvm_get_linear_rip(vcpu);
5675 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5676 vcpu->arch.dr7,
5677 vcpu->arch.db);
5678
5679 if (dr6 != 0) {
5680 vcpu->arch.dr6 &= ~15;
6f43ed01 5681 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5682 kvm_queue_exception(vcpu, DB_VECTOR);
5683 *r = EMULATE_DONE;
5684 return true;
5685 }
5686 }
5687
5688 return false;
5689}
5690
51d8b661
AP		 5691int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5692 unsigned long cr2,
dc25e89e
AP		 5693 int emulation_type,
5694 void *insn,
5695 int insn_len)
bbd9b64e 5696{
95cb2295 5697 int r;
9d74191a 5698 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5699 bool writeback = true;
93c05d3e 5700 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5701
93c05d3e
XG		 5702 /*
5703 * Clear write_fault_to_shadow_pgtable here to ensure it is
5704 * never reused.
5705 */
5706 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5707 kvm_clear_exception_queue(vcpu);
8d7d8102 5708
571008da 5709 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5710 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5711
5712 /*
5713 * We will reenter on the same instruction since
5714 * we do not set complete_userspace_io. This does not
5715 * handle watchpoints yet, those would be handled in
5716 * the emulate_ops.
5717 */
5718 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5719 return r;
5720
9d74191a
TY		 5721 ctxt->interruptibility = 0;
5722 ctxt->have_exception = false;
e0ad0b47 5723 ctxt->exception.vector = -1;
9d74191a 5724 ctxt->perm_ok = false;
bbd9b64e 5725
b51e974f 5726 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5727
9d74191a 5728 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5729
e46479f8 5730 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5731 ++vcpu->stat.insn_emulation;
1d2887e2 5732 if (r != EMULATION_OK) {
4005996e
AK		 5733 if (emulation_type & EMULTYPE_TRAP_UD)
5734 return EMULATE_FAIL;
991eebf9
GN		 5735 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5736 emulation_type))
bbd9b64e 5737 return EMULATE_DONE;
6ea6e843
PB		 5738 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5739 return EMULATE_DONE;
6d77dbfc
GN		 5740 if (emulation_type & EMULTYPE_SKIP)
5741 return EMULATE_FAIL;
5742 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5743 }
5744 }
5745
ba8afb6b 5746 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5747 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5748 if (ctxt->eflags & X86_EFLAGS_RF)
5749 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5750 return EMULATE_DONE;
5751 }
5752
1cb3f3ae
XG		 5753 if (retry_instruction(ctxt, cr2, emulation_type))
5754 return EMULATE_DONE;
5755
7ae441ea 5756 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5757 changes registers values during IO operation */
7ae441ea
GN		 5758 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5759 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5760 emulator_invalidate_register_cache(ctxt);
7ae441ea 5761 }
4d2179e1 5762
5cd21917 5763restart:
0f89b207
TL		 5764 /* Save the faulting GPA (cr2) in the address field */
5765 ctxt->exception.address = cr2;
5766
9d74191a 5767 r = x86_emulate_insn(ctxt);
bbd9b64e 5768
775fde86
JR		 5769 if (r == EMULATION_INTERCEPTED)
5770 return EMULATE_DONE;
5771
d2ddd1c4 5772 if (r == EMULATION_FAILED) {
991eebf9
GN		 5773 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5774 emulation_type))
c3cd7ffa
GN		 5775 return EMULATE_DONE;
5776
6d77dbfc 5777 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5778 }
5779
9d74191a 5780 if (ctxt->have_exception) {
d2ddd1c4 5781 r = EMULATE_DONE;
ef54bcfe
PB		 5782 if (inject_emulated_exception(vcpu))
5783 return r;
d2ddd1c4 5784 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5785 if (!vcpu->arch.pio.in) {
5786 /* FIXME: return into emulator if single-stepping. */
3457e419 5787 vcpu->arch.pio.count = 0;
0912c977 5788 } else {
7ae441ea 5789 writeback = false;
716d51ab
GN		 5790 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5791 }
ac0a48c3 5792 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5793 } else if (vcpu->mmio_needed) {
5794 if (!vcpu->mmio_is_write)
5795 writeback = false;
ac0a48c3 5796 r = EMULATE_USER_EXIT;
716d51ab 5797 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5798 } else if (r == EMULATION_RESTART)
5cd21917 5799 goto restart;
d2ddd1c4
GN		 5800 else
5801 r = EMULATE_DONE;
f850e2e6 5802
7ae441ea 5803 if (writeback) {
6addfc42 5804 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5805 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5806 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5807 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5808 if (r == EMULATE_DONE &&
5809 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5810 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5811 if (!ctxt->have_exception ||
5812 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5813 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5814
5815 /*
5816 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5817 * do nothing, and it will be requested again as soon as
5818 * the shadow expires. But we still need to check here,
5819 * because POPF has no interrupt shadow.
5820 */
5821 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5822 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5823 } else
5824 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5825
5826 return r;
de7d789a 5827}
51d8b661 5828EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5829
cf8f70bf 5830int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5831{
cf8f70bf 5832 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5833 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5834 size, port, &val, 1);
cf8f70bf 5835 /* do not return to emulator after return from userspace */
7972995b 5836 vcpu->arch.pio.count = 0;
de7d789a
CO		 5837 return ret;
5838}
cf8f70bf 5839EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5840
8370c3d0
TL		 5841static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5842{
5843 unsigned long val;
5844
5845 /* We should only ever be called with arch.pio.count equal to 1 */
5846 BUG_ON(vcpu->arch.pio.count != 1);
5847
5848 /* For size less than 4 we merge, else we zero extend */
5849 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5850 : 0;
5851
5852 /*
5853 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5854 * the copy and tracing
5855 */
5856 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5857 vcpu->arch.pio.port, &val, 1);
5858 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5859
5860 return 1;
5861}
5862
5863int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5864{
5865 unsigned long val;
5866 int ret;
5867
5868 /* For size less than 4 we merge, else we zero extend */
5869 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5870
5871 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5872 &val, 1);
5873 if (ret) {
5874 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5875 return ret;
5876 }
5877
5878 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5879
5880 return 0;
5881}
5882EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5883
251a5fd6 5884static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5885{
0a3aee0d 5886 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5887 return 0;
8cfdc000
ZA		 5888}
5889
5890static void tsc_khz_changed(void *data)
c8076604 5891{
8cfdc000
ZA		 5892 struct cpufreq_freqs *freq = data;
5893 unsigned long khz = 0;
5894
5895 if (data)
5896 khz = freq->new;
5897 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5898 khz = cpufreq_quick_get(raw_smp_processor_id());
5899 if (!khz)
5900 khz = tsc_khz;
0a3aee0d 5901 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5902}
5903
c8076604
GH		 5904static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5905 void *data)
5906{
5907 struct cpufreq_freqs *freq = data;
5908 struct kvm *kvm;
5909 struct kvm_vcpu *vcpu;
5910 int i, send_ipi = 0;
5911
8cfdc000
ZA		 5912 /*
5913 * We allow guests to temporarily run on slowing clocks,
5914 * provided we notify them after, or to run on accelerating
5915 * clocks, provided we notify them before. Thus time never
5916 * goes backwards.
5917 *
5918 * However, we have a problem. We can't atomically update
5919 * the frequency of a given CPU from this function; it is
5920 * merely a notifier, which can be called from any CPU.
5921 * Changing the TSC frequency at arbitrary points in time
5922 * requires a recomputation of local variables related to
5923 * the TSC for each VCPU. We must flag these local variables
5924 * to be updated and be sure the update takes place with the
5925 * new frequency before any guests proceed.
5926 *
5927 * Unfortunately, the combination of hotplug CPU and frequency
5928 * change creates an intractable locking scenario; the order
5929 * of when these callouts happen is undefined with respect to
5930 * CPU hotplug, and they can race with each other. As such,
5931 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5932 * undefined; you can actually have a CPU frequency change take
5933 * place in between the computation of X and the setting of the
5934 * variable. To protect against this problem, all updates of
5935 * the per_cpu tsc_khz variable are done in an interrupt
5936 * protected IPI, and all callers wishing to update the value
5937 * must wait for a synchronous IPI to complete (which is trivial
5938 * if the caller is on the CPU already). This establishes the
5939 * necessary total order on variable updates.
5940 *
5941 * Note that because a guest time update may take place
5942 * anytime after the setting of the VCPU's request bit, the
5943 * correct TSC value must be set before the request. However,
5944 * to ensure the update actually makes it to any guest which
5945 * starts running in hardware virtualization between the set
5946 * and the acquisition of the spinlock, we must also ping the
5947 * CPU after setting the request bit.
5948 *
5949 */
5950
c8076604
GH		 5951 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5952 return 0;
5953 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5954 return 0;
8cfdc000
ZA		 5955
5956 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5957
2f303b74 5958 spin_lock(&kvm_lock);
c8076604 5959 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5960 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5961 if (vcpu->cpu != freq->cpu)
5962 continue;
c285545f 5963 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5964 if (vcpu->cpu != smp_processor_id())
8cfdc000 5965 send_ipi = 1;
c8076604
GH		 5966 }
5967 }
2f303b74 5968 spin_unlock(&kvm_lock);
c8076604
GH		 5969
5970 if (freq->old < freq->new && send_ipi) {
5971 /*
5972 * We upscale the frequency. Must make the guest
5973 * doesn't see old kvmclock values while running with
5974 * the new frequency, otherwise we risk the guest sees
5975 * time go backwards.
5976 *
5977 * In case we update the frequency for another cpu
5978 * (which might be in guest context) send an interrupt
5979 * to kick the cpu out of guest context. Next time
5980 * guest context is entered kvmclock will be updated,
5981 * so the guest will not see stale values.
5982 */
8cfdc000 5983 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5984 }
5985 return 0;
5986}
5987
5988static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5989 .notifier_call = kvmclock_cpufreq_notifier
5990};
5991
251a5fd6 5992static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5993{
251a5fd6
SAS		 5994 tsc_khz_changed(NULL);
5995 return 0;
8cfdc000
ZA		 5996}
5997
b820cc0c
ZA		 5998static void kvm_timer_init(void)
5999{
c285545f 6000 max_tsc_khz = tsc_khz;
460dd42e 6001
b820cc0c 6002 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6003#ifdef CONFIG_CPU_FREQ
6004 struct cpufreq_policy policy;
758f588d
BP		 6005 int cpu;
6006
c285545f 6007 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6008 cpu = get_cpu();
6009 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6010 if (policy.cpuinfo.max_freq)
6011 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6012 put_cpu();
c285545f 6013#endif
b820cc0c
ZA		 6014 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6015 CPUFREQ_TRANSITION_NOTIFIER);
6016 }
c285545f 6017 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6018
73c1b41e 6019 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6020 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6021}
6022
ff9d07a0
ZY		 6023static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6024
f5132b01 6025int kvm_is_in_guest(void)
ff9d07a0 6026{
086c9855 6027 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6028}
6029
6030static int kvm_is_user_mode(void)
6031{
6032 int user_mode = 3;
dcf46b94 6033
086c9855
AS		 6034 if (__this_cpu_read(current_vcpu))
6035 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6036
ff9d07a0
ZY		 6037 return user_mode != 0;
6038}
6039
6040static unsigned long kvm_get_guest_ip(void)
6041{
6042 unsigned long ip = 0;
dcf46b94 6043
086c9855
AS		 6044 if (__this_cpu_read(current_vcpu))
6045 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6046
ff9d07a0
ZY		 6047 return ip;
6048}
6049
6050static struct perf_guest_info_callbacks kvm_guest_cbs = {
6051 .is_in_guest = kvm_is_in_guest,
6052 .is_user_mode = kvm_is_user_mode,
6053 .get_guest_ip = kvm_get_guest_ip,
6054};
6055
6056void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6057{
086c9855 6058 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6059}
6060EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6061
6062void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6063{
086c9855 6064 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6065}
6066EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6067
ce88decf
XG		 6068static void kvm_set_mmio_spte_mask(void)
6069{
6070 u64 mask;
6071 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6072
6073 /*
6074 * Set the reserved bits and the present bit of an paging-structure
6075 * entry to generate page fault with PFER.RSV = 1.
6076 */
885032b9 6077 /* Mask the reserved physical address bits. */
d1431483 6078 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6079
885032b9 6080 /* Set the present bit. */
ce88decf
XG		 6081 mask |= 1ull;
6082
6083#ifdef CONFIG_X86_64
6084 /*
6085 * If reserved bit is not supported, clear the present bit to disable
6086 * mmio page fault.
6087 */
6088 if (maxphyaddr == 52)
6089 mask &= ~1ull;
6090#endif
6091
dcdca5fe 6092 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6093}
6094
16e8d74d
MT		 6095#ifdef CONFIG_X86_64
6096static void pvclock_gtod_update_fn(struct work_struct *work)
6097{
d828199e
MT		 6098 struct kvm *kvm;
6099
6100 struct kvm_vcpu *vcpu;
6101 int i;
6102
2f303b74 6103 spin_lock(&kvm_lock);
d828199e
MT		 6104 list_for_each_entry(kvm, &vm_list, vm_list)
6105 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6106 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6107 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6108 spin_unlock(&kvm_lock);
16e8d74d
MT		 6109}
6110
6111static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6112
6113/*
6114 * Notification about pvclock gtod data update.
6115 */
6116static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6117 void *priv)
6118{
6119 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6120 struct timekeeper *tk = priv;
6121
6122 update_pvclock_gtod(tk);
6123
6124 /* disable master clock if host does not trust, or does not
6125 * use, TSC clocksource
6126 */
6127 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6128 atomic_read(&kvm_guest_has_master_clock) != 0)
6129 queue_work(system_long_wq, &pvclock_gtod_work);
6130
6131 return 0;
6132}
6133
6134static struct notifier_block pvclock_gtod_notifier = {
6135 .notifier_call = pvclock_gtod_notify,
6136};
6137#endif
6138
f8c16bba 6139int kvm_arch_init(void *opaque)
043405e1 6140{
b820cc0c 6141 int r;
6b61edf7 6142 struct kvm_x86_ops *ops = opaque;
f8c16bba 6143
f8c16bba
ZX		 6144 if (kvm_x86_ops) {
6145 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6146 r = -EEXIST;
6147 goto out;
f8c16bba
ZX		 6148 }
6149
6150 if (!ops->cpu_has_kvm_support()) {
6151 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6152 r = -EOPNOTSUPP;
6153 goto out;
f8c16bba
ZX		 6154 }
6155 if (ops->disabled_by_bios()) {
6156 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6157 r = -EOPNOTSUPP;
6158 goto out;
f8c16bba
ZX		 6159 }
6160
013f6a5d
MT		 6161 r = -ENOMEM;
6162 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6163 if (!shared_msrs) {
6164 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6165 goto out;
6166 }
6167
97db56ce
AK		 6168 r = kvm_mmu_module_init();
6169 if (r)
013f6a5d 6170 goto out_free_percpu;
97db56ce 6171
ce88decf 6172 kvm_set_mmio_spte_mask();
97db56ce 6173
f8c16bba 6174 kvm_x86_ops = ops;
920c8377 6175
7b52345e 6176 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6177 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6178 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6179 kvm_timer_init();
c8076604 6180
ff9d07a0
ZY		 6181 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6182
d366bf7e 6183 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6184 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6185
c5cc421b 6186 kvm_lapic_init();
16e8d74d
MT		 6187#ifdef CONFIG_X86_64
6188 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6189#endif
6190
f8c16bba 6191 return 0;
56c6d28a 6192
013f6a5d
MT		 6193out_free_percpu:
6194 free_percpu(shared_msrs);
56c6d28a 6195out:
56c6d28a 6196 return r;
043405e1 6197}
8776e519 6198
f8c16bba
ZX		 6199void kvm_arch_exit(void)
6200{
cef84c30 6201 kvm_lapic_exit();
ff9d07a0
ZY		 6202 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6203
888d256e
JK		 6204 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6205 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6206 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6207 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6208#ifdef CONFIG_X86_64
6209 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6210#endif
f8c16bba 6211 kvm_x86_ops = NULL;
56c6d28a 6212 kvm_mmu_module_exit();
013f6a5d 6213 free_percpu(shared_msrs);
56c6d28a 6214}
f8c16bba 6215
5cb56059 6216int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6217{
6218 ++vcpu->stat.halt_exits;
35754c98 6219 if (lapic_in_kernel(vcpu)) {
a4535290 6220 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6221 return 1;
6222 } else {
6223 vcpu->run->exit_reason = KVM_EXIT_HLT;
6224 return 0;
6225 }
6226}
5cb56059
JS		 6227EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6228
6229int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6230{
6affcbed
KH		 6231 int ret = kvm_skip_emulated_instruction(vcpu);
6232 /*
6233 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6234 * KVM_EXIT_DEBUG here.
6235 */
6236 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6237}
8776e519
HB		 6238EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6239
8ef81a9a 6240#ifdef CONFIG_X86_64
55dd00a7
MT		 6241static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6242 unsigned long clock_type)
6243{
6244 struct kvm_clock_pairing clock_pairing;
6245 struct timespec ts;
80fbd89c 6246 u64 cycle;
55dd00a7
MT		 6247 int ret;
6248
6249 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6250 return -KVM_EOPNOTSUPP;
6251
6252 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6253 return -KVM_EOPNOTSUPP;
6254
6255 clock_pairing.sec = ts.tv_sec;
6256 clock_pairing.nsec = ts.tv_nsec;
6257 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6258 clock_pairing.flags = 0;
6259
6260 ret = 0;
6261 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6262 sizeof(struct kvm_clock_pairing)))
6263 ret = -KVM_EFAULT;
6264
6265 return ret;
6266}
8ef81a9a 6267#endif
55dd00a7 6268
6aef266c
SV		 6269/*
6270 * kvm_pv_kick_cpu_op: Kick a vcpu.
6271 *
6272 * @apicid - apicid of vcpu to be kicked.
6273 */
6274static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6275{
24d2166b 6276 struct kvm_lapic_irq lapic_irq;
6aef266c 6277
24d2166b
R		 6278 lapic_irq.shorthand = 0;
6279 lapic_irq.dest_mode = 0;
ebd28fcb 6280 lapic_irq.level = 0;
24d2166b 6281 lapic_irq.dest_id = apicid;
93bbf0b8 6282 lapic_irq.msi_redir_hint = false;
6aef266c 6283
24d2166b 6284 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6285 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6286}
6287
d62caabb
AS		 6288void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6289{
6290 vcpu->arch.apicv_active = false;
6291 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6292}
6293
8776e519
HB		 6294int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6295{
6296 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6297 int op_64_bit, r;
8776e519 6298
6affcbed 6299 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6300
55cd8e5a
GN		 6301 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6302 return kvm_hv_hypercall(vcpu);
6303
5fdbf976
MT		 6304 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6305 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6306 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6307 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6308 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6309
229456fc 6310 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6311
a449c7aa
NA		 6312 op_64_bit = is_64_bit_mode(vcpu);
6313 if (!op_64_bit) {
8776e519
HB		 6314 nr &= 0xFFFFFFFF;
6315 a0 &= 0xFFFFFFFF;
6316 a1 &= 0xFFFFFFFF;
6317 a2 &= 0xFFFFFFFF;
6318 a3 &= 0xFFFFFFFF;
6319 }
6320
07708c4a
JK		 6321 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6322 ret = -KVM_EPERM;
6323 goto out;
6324 }
6325
8776e519 6326 switch (nr) {
b93463aa
AK		 6327 case KVM_HC_VAPIC_POLL_IRQ:
6328 ret = 0;
6329 break;
6aef266c
SV		 6330 case KVM_HC_KICK_CPU:
6331 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6332 ret = 0;
6333 break;
8ef81a9a 6334#ifdef CONFIG_X86_64
55dd00a7
MT		 6335 case KVM_HC_CLOCK_PAIRING:
6336 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6337 break;
8ef81a9a 6338#endif
8776e519
HB		 6339 default:
6340 ret = -KVM_ENOSYS;
6341 break;
6342 }
07708c4a 6343out:
a449c7aa
NA		 6344 if (!op_64_bit)
6345 ret = (u32)ret;
5fdbf976 6346 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6347 ++vcpu->stat.hypercalls;
2f333bcb 6348 return r;
8776e519
HB		 6349}
6350EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6351
b6785def 6352static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6353{
d6aa1000 6354 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6355 char instruction[3];
5fdbf976 6356 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6357
8776e519 6358 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6359
ce2e852e
DV		 6360 return emulator_write_emulated(ctxt, rip, instruction, 3,
6361 &ctxt->exception);
8776e519
HB		 6362}
6363
851ba692 6364static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6365{
782d422b
MG		 6366 return vcpu->run->request_interrupt_window &&
6367 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6368}
6369
851ba692 6370static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6371{
851ba692
AK		 6372 struct kvm_run *kvm_run = vcpu->run;
6373
91586a3b 6374 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6375 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6376 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6377 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6378 kvm_run->ready_for_interrupt_injection =
6379 pic_in_kernel(vcpu->kvm) ||
782d422b 6380 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6381}
6382
95ba8273
GN		 6383static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6384{
6385 int max_irr, tpr;
6386
6387 if (!kvm_x86_ops->update_cr8_intercept)
6388 return;
6389
bce87cce 6390 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6391 return;
6392
d62caabb
AS		 6393 if (vcpu->arch.apicv_active)
6394 return;
6395
8db3baa2
GN		 6396 if (!vcpu->arch.apic->vapic_addr)
6397 max_irr = kvm_lapic_find_highest_irr(vcpu);
6398 else
6399 max_irr = -1;
95ba8273
GN		 6400
6401 if (max_irr != -1)
6402 max_irr >>= 4;
6403
6404 tpr = kvm_lapic_get_cr8(vcpu);
6405
6406 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6407}
6408
b6b8a145 6409static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6410{
b6b8a145
JK		 6411 int r;
6412
95ba8273 6413 /* try to reinject previous events if any */
664f8e26
WL		 6414 if (vcpu->arch.exception.injected) {
6415 kvm_x86_ops->queue_exception(vcpu);
6416 return 0;
6417 }
6418
6419 /*
6420 * Exceptions must be injected immediately, or the exception
6421 * frame will have the address of the NMI or interrupt handler.
6422 */
6423 if (!vcpu->arch.exception.pending) {
6424 if (vcpu->arch.nmi_injected) {
6425 kvm_x86_ops->set_nmi(vcpu);
6426 return 0;
6427 }
6428
6429 if (vcpu->arch.interrupt.pending) {
6430 kvm_x86_ops->set_irq(vcpu);
6431 return 0;
6432 }
6433 }
6434
6435 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6436 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6437 if (r != 0)
6438 return r;
6439 }
6440
6441 /* try to inject new event if pending */
b59bb7bd 6442 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6443 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6444 vcpu->arch.exception.has_error_code,
6445 vcpu->arch.exception.error_code);
d6e8c854 6446
664f8e26
WL		 6447 vcpu->arch.exception.pending = false;
6448 vcpu->arch.exception.injected = true;
6449
d6e8c854
NA		 6450 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6451 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6452 X86_EFLAGS_RF);
6453
6bdf0662
NA		 6454 if (vcpu->arch.exception.nr == DB_VECTOR &&
6455 (vcpu->arch.dr7 & DR7_GD)) {
6456 vcpu->arch.dr7 &= ~DR7_GD;
6457 kvm_update_dr7(vcpu);
6458 }
6459
cfcd20e5 6460 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6461 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6462 vcpu->arch.smi_pending = false;
52797bf9 6463 ++vcpu->arch.smi_count;
ee2cd4b7 6464 enter_smm(vcpu);
c43203ca 6465 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6466 --vcpu->arch.nmi_pending;
6467 vcpu->arch.nmi_injected = true;
6468 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6469 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6470 /*
6471 * Because interrupts can be injected asynchronously, we are
6472 * calling check_nested_events again here to avoid a race condition.
6473 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6474 * proposal and current concerns. Perhaps we should be setting
6475 * KVM_REQ_EVENT only on certain events and not unconditionally?
6476 */
6477 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6478 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6479 if (r != 0)
6480 return r;
6481 }
95ba8273 6482 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6483 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6484 false);
6485 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6486 }
6487 }
ee2cd4b7 6488
b6b8a145 6489 return 0;
95ba8273
GN		 6490}
6491
7460fb4a
AK		 6492static void process_nmi(struct kvm_vcpu *vcpu)
6493{
6494 unsigned limit = 2;
6495
6496 /*
6497 * x86 is limited to one NMI running, and one NMI pending after it.
6498 * If an NMI is already in progress, limit further NMIs to just one.
6499 * Otherwise, allow two (and we'll inject the first one immediately).
6500 */
6501 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6502 limit = 1;
6503
6504 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6505 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6506 kvm_make_request(KVM_REQ_EVENT, vcpu);
6507}
6508
ee2cd4b7 6509static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6510{
6511 u32 flags = 0;
6512 flags |= seg->g << 23;
6513 flags |= seg->db << 22;
6514 flags |= seg->l << 21;
6515 flags |= seg->avl << 20;
6516 flags |= seg->present << 15;
6517 flags |= seg->dpl << 13;
6518 flags |= seg->s << 12;
6519 flags |= seg->type << 8;
6520 return flags;
6521}
6522
ee2cd4b7 6523static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6524{
6525 struct kvm_segment seg;
6526 int offset;
6527
6528 kvm_get_segment(vcpu, &seg, n);
6529 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6530
6531 if (n < 3)
6532 offset = 0x7f84 + n * 12;
6533 else
6534 offset = 0x7f2c + (n - 3) * 12;
6535
6536 put_smstate(u32, buf, offset + 8, seg.base);
6537 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6538 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6539}
6540
efbb288a 6541#ifdef CONFIG_X86_64
ee2cd4b7 6542static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6543{
6544 struct kvm_segment seg;
6545 int offset;
6546 u16 flags;
6547
6548 kvm_get_segment(vcpu, &seg, n);
6549 offset = 0x7e00 + n * 16;
6550
ee2cd4b7 6551 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6552 put_smstate(u16, buf, offset, seg.selector);
6553 put_smstate(u16, buf, offset + 2, flags);
6554 put_smstate(u32, buf, offset + 4, seg.limit);
6555 put_smstate(u64, buf, offset + 8, seg.base);
6556}
efbb288a 6557#endif
660a5d51 6558
ee2cd4b7 6559static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6560{
6561 struct desc_ptr dt;
6562 struct kvm_segment seg;
6563 unsigned long val;
6564 int i;
6565
6566 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6567 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6568 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6569 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6570
6571 for (i = 0; i < 8; i++)
6572 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6573
6574 kvm_get_dr(vcpu, 6, &val);
6575 put_smstate(u32, buf, 0x7fcc, (u32)val);
6576 kvm_get_dr(vcpu, 7, &val);
6577 put_smstate(u32, buf, 0x7fc8, (u32)val);
6578
6579 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6580 put_smstate(u32, buf, 0x7fc4, seg.selector);
6581 put_smstate(u32, buf, 0x7f64, seg.base);
6582 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6583 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6584
6585 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6586 put_smstate(u32, buf, 0x7fc0, seg.selector);
6587 put_smstate(u32, buf, 0x7f80, seg.base);
6588 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6589 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6590
6591 kvm_x86_ops->get_gdt(vcpu, &dt);
6592 put_smstate(u32, buf, 0x7f74, dt.address);
6593 put_smstate(u32, buf, 0x7f70, dt.size);
6594
6595 kvm_x86_ops->get_idt(vcpu, &dt);
6596 put_smstate(u32, buf, 0x7f58, dt.address);
6597 put_smstate(u32, buf, 0x7f54, dt.size);
6598
6599 for (i = 0; i < 6; i++)
ee2cd4b7 6600 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6601
6602 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6603
6604 /* revision id */
6605 put_smstate(u32, buf, 0x7efc, 0x00020000);
6606 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6607}
6608
ee2cd4b7 6609static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6610{
6611#ifdef CONFIG_X86_64
6612 struct desc_ptr dt;
6613 struct kvm_segment seg;
6614 unsigned long val;
6615 int i;
6616
6617 for (i = 0; i < 16; i++)
6618 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6619
6620 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6621 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6622
6623 kvm_get_dr(vcpu, 6, &val);
6624 put_smstate(u64, buf, 0x7f68, val);
6625 kvm_get_dr(vcpu, 7, &val);
6626 put_smstate(u64, buf, 0x7f60, val);
6627
6628 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6629 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6630 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6631
6632 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6633
6634 /* revision id */
6635 put_smstate(u32, buf, 0x7efc, 0x00020064);
6636
6637 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6638
6639 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6640 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6641 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6642 put_smstate(u32, buf, 0x7e94, seg.limit);
6643 put_smstate(u64, buf, 0x7e98, seg.base);
6644
6645 kvm_x86_ops->get_idt(vcpu, &dt);
6646 put_smstate(u32, buf, 0x7e84, dt.size);
6647 put_smstate(u64, buf, 0x7e88, dt.address);
6648
6649 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6650 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6651 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6652 put_smstate(u32, buf, 0x7e74, seg.limit);
6653 put_smstate(u64, buf, 0x7e78, seg.base);
6654
6655 kvm_x86_ops->get_gdt(vcpu, &dt);
6656 put_smstate(u32, buf, 0x7e64, dt.size);
6657 put_smstate(u64, buf, 0x7e68, dt.address);
6658
6659 for (i = 0; i < 6; i++)
ee2cd4b7 6660 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6661#else
6662 WARN_ON_ONCE(1);
6663#endif
6664}
6665
ee2cd4b7 6666static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6667{
660a5d51 6668 struct kvm_segment cs, ds;
18c3626e 6669 struct desc_ptr dt;
660a5d51
PB		 6670 char buf[512];
6671 u32 cr0;
6672
660a5d51 6673 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6674 memset(buf, 0, 512);
d6321d49 6675 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6676 enter_smm_save_state_64(vcpu, buf);
660a5d51 6677 else
ee2cd4b7 6678 enter_smm_save_state_32(vcpu, buf);
660a5d51 6679
0234bf88
LP		 6680 /*
6681 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6682 * vCPU state (e.g. leave guest mode) after we've saved the state into
6683 * the SMM state-save area.
6684 */
6685 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6686
6687 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6688 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6689
6690 if (kvm_x86_ops->get_nmi_mask(vcpu))
6691 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6692 else
6693 kvm_x86_ops->set_nmi_mask(vcpu, true);
6694
6695 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6696 kvm_rip_write(vcpu, 0x8000);
6697
6698 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6699 kvm_x86_ops->set_cr0(vcpu, cr0);
6700 vcpu->arch.cr0 = cr0;
6701
6702 kvm_x86_ops->set_cr4(vcpu, 0);
6703
18c3626e
PB		 6704 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6705 dt.address = dt.size = 0;
6706 kvm_x86_ops->set_idt(vcpu, &dt);
6707
660a5d51
PB		 6708 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6709
6710 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6711 cs.base = vcpu->arch.smbase;
6712
6713 ds.selector = 0;
6714 ds.base = 0;
6715
6716 cs.limit = ds.limit = 0xffffffff;
6717 cs.type = ds.type = 0x3;
6718 cs.dpl = ds.dpl = 0;
6719 cs.db = ds.db = 0;
6720 cs.s = ds.s = 1;
6721 cs.l = ds.l = 0;
6722 cs.g = ds.g = 1;
6723 cs.avl = ds.avl = 0;
6724 cs.present = ds.present = 1;
6725 cs.unusable = ds.unusable = 0;
6726 cs.padding = ds.padding = 0;
6727
6728 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6729 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6730 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6731 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6732 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6733 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6734
d6321d49 6735 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6736 kvm_x86_ops->set_efer(vcpu, 0);
6737
6738 kvm_update_cpuid(vcpu);
6739 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6740}
6741
ee2cd4b7 6742static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6743{
6744 vcpu->arch.smi_pending = true;
6745 kvm_make_request(KVM_REQ_EVENT, vcpu);
6746}
6747
2860c4b1
PB		 6748void kvm_make_scan_ioapic_request(struct kvm *kvm)
6749{
6750 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6751}
6752
3d81bc7e 6753static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6754{
5c919412
AS		 6755 u64 eoi_exit_bitmap[4];
6756
3d81bc7e
YZ		 6757 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6758 return;
c7c9c56c 6759
6308630b 6760 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6761
b053b2ae 6762 if (irqchip_split(vcpu->kvm))
6308630b 6763 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6764 else {
76dfafd5 6765 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6766 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6767 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6768 }
5c919412
AS		 6769 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6770 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6771 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6772}
6773
a70656b6
RK		 6774static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6775{
6776 ++vcpu->stat.tlb_flush;
6777 kvm_x86_ops->tlb_flush(vcpu);
6778}
6779
b1394e74
RK		 6780void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6781 unsigned long start, unsigned long end)
6782{
6783 unsigned long apic_address;
6784
6785 /*
6786 * The physical address of apic access page is stored in the VMCS.
6787 * Update it when it becomes invalid.
6788 */
6789 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6790 if (start <= apic_address && apic_address < end)
6791 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6792}
6793
4256f43f
TC		 6794void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6795{
c24ae0dc
TC		 6796 struct page *page = NULL;
6797
35754c98 6798 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6799 return;
6800
4256f43f
TC		 6801 if (!kvm_x86_ops->set_apic_access_page_addr)
6802 return;
6803
c24ae0dc 6804 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6805 if (is_error_page(page))
6806 return;
c24ae0dc
TC		 6807 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6808
6809 /*
6810 * Do not pin apic access page in memory, the MMU notifier
6811 * will call us again if it is migrated or swapped out.
6812 */
6813 put_page(page);
4256f43f
TC		 6814}
6815EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6816
9357d939 6817/*
362c698f 6818 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6819 * exiting to the userspace. Otherwise, the value will be returned to the
6820 * userspace.
6821 */
851ba692 6822static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6823{
6824 int r;
62a193ed
MG		 6825 bool req_int_win =
6826 dm_request_for_irq_injection(vcpu) &&
6827 kvm_cpu_accept_dm_intr(vcpu);
6828
730dca42 6829 bool req_immediate_exit = false;
b6c7a5dc 6830
2fa6e1e1 6831 if (kvm_request_pending(vcpu)) {
a8eeb04a 6832 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6833 kvm_mmu_unload(vcpu);
a8eeb04a 6834 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6835 __kvm_migrate_timers(vcpu);
d828199e
MT		 6836 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6837 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6838 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6839 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6840 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6841 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6842 if (unlikely(r))
6843 goto out;
6844 }
a8eeb04a 6845 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6846 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6847 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6848 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6849 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6850 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6851 r = 0;
6852 goto out;
6853 }
a8eeb04a 6854 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6855 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6856 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6857 r = 0;
6858 goto out;
6859 }
af585b92
GN		 6860 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6861 /* Page is swapped out. Do synthetic halt */
6862 vcpu->arch.apf.halted = true;
6863 r = 1;
6864 goto out;
6865 }
c9aaa895
GC		 6866 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6867 record_steal_time(vcpu);
64d60670
PB		 6868 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6869 process_smi(vcpu);
7460fb4a
AK		 6870 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6871 process_nmi(vcpu);
f5132b01 6872 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6873 kvm_pmu_handle_event(vcpu);
f5132b01 6874 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6875 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6876 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6877 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6878 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6879 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6880 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6881 vcpu->run->eoi.vector =
6882 vcpu->arch.pending_ioapic_eoi;
6883 r = 0;
6884 goto out;
6885 }
6886 }
3d81bc7e
YZ		 6887 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6888 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6889 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6890 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6891 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6892 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6893 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6894 r = 0;
6895 goto out;
6896 }
e516cebb
AS		 6897 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6898 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6899 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6900 r = 0;
6901 goto out;
6902 }
db397571
AS		 6903 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6904 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6905 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6906 r = 0;
6907 goto out;
6908 }
f3b138c5
AS		 6909
6910 /*
6911 * KVM_REQ_HV_STIMER has to be processed after
6912 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6913 * depend on the guest clock being up-to-date
6914 */
1f4b34f8
AS		 6915 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6916 kvm_hv_process_stimers(vcpu);
2f52d58c 6917 }
b93463aa 6918
b463a6f7 6919 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6920 ++vcpu->stat.req_event;
66450a21
JK		 6921 kvm_apic_accept_events(vcpu);
6922 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6923 r = 1;
6924 goto out;
6925 }
6926
b6b8a145
JK		 6927 if (inject_pending_event(vcpu, req_int_win) != 0)
6928 req_immediate_exit = true;
321c5658 6929 else {
cc3d967f 6930 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6931 *
cc3d967f
LP		 6932 * SMIs have three cases:
6933 * 1) They can be nested, and then there is nothing to
6934 * do here because RSM will cause a vmexit anyway.
6935 * 2) There is an ISA-specific reason why SMI cannot be
6936 * injected, and the moment when this changes can be
6937 * intercepted.
6938 * 3) Or the SMI can be pending because
6939 * inject_pending_event has completed the injection
6940 * of an IRQ or NMI from the previous vmexit, and
6941 * then we request an immediate exit to inject the
6942 * SMI.
c43203ca
PB		 6943 */
6944 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6945 if (!kvm_x86_ops->enable_smi_window(vcpu))
6946 req_immediate_exit = true;
321c5658
YS		 6947 if (vcpu->arch.nmi_pending)
6948 kvm_x86_ops->enable_nmi_window(vcpu);
6949 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6950 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6951 WARN_ON(vcpu->arch.exception.pending);
321c5658 6952 }
b463a6f7
AK		 6953
6954 if (kvm_lapic_enabled(vcpu)) {
6955 update_cr8_intercept(vcpu);
6956 kvm_lapic_sync_to_vapic(vcpu);
6957 }
6958 }
6959
d8368af8
AK		 6960 r = kvm_mmu_reload(vcpu);
6961 if (unlikely(r)) {
d905c069 6962 goto cancel_injection;
d8368af8
AK		 6963 }
6964
b6c7a5dc
HB		 6965 preempt_disable();
6966
6967 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 6968
6969 /*
6970 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6971 * IPI are then delayed after guest entry, which ensures that they
6972 * result in virtual interrupt delivery.
6973 */
6974 local_irq_disable();
6b7e2d09
XG		 6975 vcpu->mode = IN_GUEST_MODE;
6976
01b71917
MT		 6977 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6978
0f127d12 6979 /*
b95234c8 6980 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6981 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6982 *
6983 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6984 * pairs with the memory barrier implicit in pi_test_and_set_on
6985 * (see vmx_deliver_posted_interrupt).
6986 *
6987 * 3) This also orders the write to mode from any reads to the page
6988 * tables done while the VCPU is running. Please see the comment
6989 * in kvm_flush_remote_tlbs.
6b7e2d09 6990 */
01b71917 6991 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6992
b95234c8
PB		 6993 /*
6994 * This handles the case where a posted interrupt was
6995 * notified with kvm_vcpu_kick.
6996 */
6997 if (kvm_lapic_enabled(vcpu)) {
6998 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6999 kvm_x86_ops->sync_pir_to_irr(vcpu);
7000 }
32f88400 7001
2fa6e1e1 7002 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7003 || need_resched() || signal_pending(current)) {
6b7e2d09 7004 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7005 smp_wmb();
6c142801
AK		 7006 local_irq_enable();
7007 preempt_enable();
01b71917 7008 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7009 r = 1;
d905c069 7010 goto cancel_injection;
6c142801
AK		 7011 }
7012
fc5b7f3b
DM		 7013 kvm_load_guest_xcr0(vcpu);
7014
c43203ca
PB		 7015 if (req_immediate_exit) {
7016 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7017 smp_send_reschedule(vcpu->cpu);
c43203ca 7018 }
d6185f20 7019
8b89fe1f 7020 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7021 if (lapic_timer_advance_ns)
7022 wait_lapic_expire(vcpu);
6edaa530 7023 guest_enter_irqoff();
b6c7a5dc 7024
42dbaa5a 7025 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7026 set_debugreg(0, 7);
7027 set_debugreg(vcpu->arch.eff_db[0], 0);
7028 set_debugreg(vcpu->arch.eff_db[1], 1);
7029 set_debugreg(vcpu->arch.eff_db[2], 2);
7030 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7031 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7032 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7033 }
b6c7a5dc 7034
851ba692 7035 kvm_x86_ops->run(vcpu);
b6c7a5dc 7036
c77fb5fe
PB		 7037 /*
7038 * Do this here before restoring debug registers on the host. And
7039 * since we do this before handling the vmexit, a DR access vmexit
7040 * can (a) read the correct value of the debug registers, (b) set
7041 * KVM_DEBUGREG_WONT_EXIT again.
7042 */
7043 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7044 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7045 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7046 kvm_update_dr0123(vcpu);
7047 kvm_update_dr6(vcpu);
7048 kvm_update_dr7(vcpu);
7049 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7050 }
7051
24f1e32c
FW		 7052 /*
7053 * If the guest has used debug registers, at least dr7
7054 * will be disabled while returning to the host.
7055 * If we don't have active breakpoints in the host, we don't
7056 * care about the messed up debug address registers. But if
7057 * we have some of them active, restore the old state.
7058 */
59d8eb53 7059 if (hw_breakpoint_active())
24f1e32c 7060 hw_breakpoint_restore();
42dbaa5a 7061
4ba76538 7062 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7063
6b7e2d09 7064 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7065 smp_wmb();
a547c6db 7066
fc5b7f3b
DM		 7067 kvm_put_guest_xcr0(vcpu);
7068
a547c6db 7069 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7070
7071 ++vcpu->stat.exits;
7072
f2485b3e 7073 guest_exit_irqoff();
b6c7a5dc 7074
f2485b3e 7075 local_irq_enable();
b6c7a5dc
HB		 7076 preempt_enable();
7077
f656ce01 7078 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7079
b6c7a5dc
HB		 7080 /*
7081 * Profile KVM exit RIPs:
7082 */
7083 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7084 unsigned long rip = kvm_rip_read(vcpu);
7085 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7086 }
7087
cc578287
ZA		 7088 if (unlikely(vcpu->arch.tsc_always_catchup))
7089 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7090
5cfb1d5a
MT		 7091 if (vcpu->arch.apic_attention)
7092 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7093
618232e2 7094 vcpu->arch.gpa_available = false;
851ba692 7095 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7096 return r;
7097
7098cancel_injection:
7099 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7100 if (unlikely(vcpu->arch.apic_attention))
7101 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7102out:
7103 return r;
7104}
b6c7a5dc 7105
362c698f
PB		 7106static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7107{
bf9f6ac8
FW		 7108 if (!kvm_arch_vcpu_runnable(vcpu) &&
7109 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7110 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7111 kvm_vcpu_block(vcpu);
7112 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7113
7114 if (kvm_x86_ops->post_block)
7115 kvm_x86_ops->post_block(vcpu);
7116
9c8fd1ba
PB		 7117 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7118 return 1;
7119 }
362c698f
PB		 7120
7121 kvm_apic_accept_events(vcpu);
7122 switch(vcpu->arch.mp_state) {
7123 case KVM_MP_STATE_HALTED:
7124 vcpu->arch.pv.pv_unhalted = false;
7125 vcpu->arch.mp_state =
7126 KVM_MP_STATE_RUNNABLE;
7127 case KVM_MP_STATE_RUNNABLE:
7128 vcpu->arch.apf.halted = false;
7129 break;
7130 case KVM_MP_STATE_INIT_RECEIVED:
7131 break;
7132 default:
7133 return -EINTR;
7134 break;
7135 }
7136 return 1;
7137}
09cec754 7138
5d9bc648
PB		 7139static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7140{
0ad3bed6
PB		 7141 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7142 kvm_x86_ops->check_nested_events(vcpu, false);
7143
5d9bc648
PB		 7144 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7145 !vcpu->arch.apf.halted);
7146}
7147
362c698f 7148static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7149{
7150 int r;
f656ce01 7151 struct kvm *kvm = vcpu->kvm;
d7690175 7152
f656ce01 7153 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7154
362c698f 7155 for (;;) {
58f800d5 7156 if (kvm_vcpu_running(vcpu)) {
851ba692 7157 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7158 } else {
362c698f 7159 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7160 }
7161
09cec754
GN		 7162 if (r <= 0)
7163 break;
7164
72875d8a 7165 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7166 if (kvm_cpu_has_pending_timer(vcpu))
7167 kvm_inject_pending_timer_irqs(vcpu);
7168
782d422b
MG		 7169 if (dm_request_for_irq_injection(vcpu) &&
7170 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7171 r = 0;
7172 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7173 ++vcpu->stat.request_irq_exits;
362c698f 7174 break;
09cec754 7175 }
af585b92
GN		 7176
7177 kvm_check_async_pf_completion(vcpu);
7178
09cec754
GN		 7179 if (signal_pending(current)) {
7180 r = -EINTR;
851ba692 7181 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7182 ++vcpu->stat.signal_exits;
362c698f 7183 break;
09cec754
GN		 7184 }
7185 if (need_resched()) {
f656ce01 7186 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7187 cond_resched();
f656ce01 7188 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7189 }
b6c7a5dc
HB		 7190 }
7191
f656ce01 7192 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7193
7194 return r;
7195}
7196
716d51ab
GN		 7197static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7198{
7199 int r;
7200 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7201 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7202 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7203 if (r != EMULATE_DONE)
7204 return 0;
7205 return 1;
7206}
7207
7208static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7209{
7210 BUG_ON(!vcpu->arch.pio.count);
7211
7212 return complete_emulated_io(vcpu);
7213}
7214
f78146b0
AK		 7215/*
7216 * Implements the following, as a state machine:
7217 *
7218 * read:
7219 * for each fragment
87da7e66
XG		 7220 * for each mmio piece in the fragment
7221 * write gpa, len
7222 * exit
7223 * copy data
f78146b0
AK		 7224 * execute insn
7225 *
7226 * write:
7227 * for each fragment
87da7e66
XG		 7228 * for each mmio piece in the fragment
7229 * write gpa, len
7230 * copy data
7231 * exit
f78146b0 7232 */
716d51ab 7233static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7234{
7235 struct kvm_run *run = vcpu->run;
f78146b0 7236 struct kvm_mmio_fragment *frag;
87da7e66 7237 unsigned len;
5287f194 7238
716d51ab 7239 BUG_ON(!vcpu->mmio_needed);
5287f194 7240
716d51ab 7241 /* Complete previous fragment */
87da7e66
XG		 7242 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7243 len = min(8u, frag->len);
716d51ab 7244 if (!vcpu->mmio_is_write)
87da7e66
XG		 7245 memcpy(frag->data, run->mmio.data, len);
7246
7247 if (frag->len <= 8) {
7248 /* Switch to the next fragment. */
7249 frag++;
7250 vcpu->mmio_cur_fragment++;
7251 } else {
7252 /* Go forward to the next mmio piece. */
7253 frag->data += len;
7254 frag->gpa += len;
7255 frag->len -= len;
7256 }
7257
a08d3b3b 7258 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7259 vcpu->mmio_needed = 0;
0912c977
PB		 7260
7261 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7262 if (vcpu->mmio_is_write)
716d51ab
GN		 7263 return 1;
7264 vcpu->mmio_read_completed = 1;
7265 return complete_emulated_io(vcpu);
7266 }
87da7e66 7267
716d51ab
GN		 7268 run->exit_reason = KVM_EXIT_MMIO;
7269 run->mmio.phys_addr = frag->gpa;
7270 if (vcpu->mmio_is_write)
87da7e66
XG		 7271 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7272 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7273 run->mmio.is_write = vcpu->mmio_is_write;
7274 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7275 return 0;
5287f194
AK		 7276}
7277
716d51ab 7278
b6c7a5dc
HB		 7279int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7280{
7281 int r;
b6c7a5dc 7282
accb757d 7283 vcpu_load(vcpu);
20b7035c 7284 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7285 kvm_load_guest_fpu(vcpu);
7286
a4535290 7287 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7288 if (kvm_run->immediate_exit) {
7289 r = -EINTR;
7290 goto out;
7291 }
b6c7a5dc 7292 kvm_vcpu_block(vcpu);
66450a21 7293 kvm_apic_accept_events(vcpu);
72875d8a 7294 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7295 r = -EAGAIN;
a0595000
JS		 7296 if (signal_pending(current)) {
7297 r = -EINTR;
7298 vcpu->run->exit_reason = KVM_EXIT_INTR;
7299 ++vcpu->stat.signal_exits;
7300 }
ac9f6dc0 7301 goto out;
b6c7a5dc
HB		 7302 }
7303
b6c7a5dc 7304 /* re-sync apic's tpr */
35754c98 7305 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7306 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7307 r = -EINVAL;
7308 goto out;
7309 }
7310 }
b6c7a5dc 7311
716d51ab
GN		 7312 if (unlikely(vcpu->arch.complete_userspace_io)) {
7313 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7314 vcpu->arch.complete_userspace_io = NULL;
7315 r = cui(vcpu);
7316 if (r <= 0)
5663d8f9 7317 goto out;
716d51ab
GN		 7318 } else
7319 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7320
460df4c1
PB		 7321 if (kvm_run->immediate_exit)
7322 r = -EINTR;
7323 else
7324 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7325
7326out:
5663d8f9 7327 kvm_put_guest_fpu(vcpu);
f1d86e46 7328 post_kvm_run_save(vcpu);
20b7035c 7329 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7330
accb757d 7331 vcpu_put(vcpu);
b6c7a5dc
HB		 7332 return r;
7333}
7334
7335int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7336{
1fc9b76b
CD		 7337 vcpu_load(vcpu);
7338
7ae441ea
GN		 7339 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7340 /*
7341 * We are here if userspace calls get_regs() in the middle of
7342 * instruction emulation. Registers state needs to be copied
4a969980 7343 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7344 * that usually, but some bad designed PV devices (vmware
7345 * backdoor interface) need this to work
7346 */
dd856efa 7347 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7348 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7349 }
5fdbf976
MT		 7350 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7351 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7352 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7353 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7354 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7355 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7356 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7357 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7358#ifdef CONFIG_X86_64
5fdbf976
MT		 7359 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7360 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7361 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7362 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7363 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7364 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7365 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7366 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7367#endif
7368
5fdbf976 7369 regs->rip = kvm_rip_read(vcpu);
91586a3b 7370 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7371
1fc9b76b 7372 vcpu_put(vcpu);
b6c7a5dc
HB		 7373 return 0;
7374}
7375
7376int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7377{
875656fe
CD		 7378 vcpu_load(vcpu);
7379
7ae441ea
GN		 7380 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7381 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7382
5fdbf976
MT		 7383 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7384 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7385 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7386 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7387 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7388 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7389 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7390 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7391#ifdef CONFIG_X86_64
5fdbf976
MT		 7392 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7393 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7394 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7395 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7396 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7397 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7398 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7399 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7400#endif
7401
5fdbf976 7402 kvm_rip_write(vcpu, regs->rip);
d73235d1 7403 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7404
b4f14abd
JK		 7405 vcpu->arch.exception.pending = false;
7406
3842d135
AK		 7407 kvm_make_request(KVM_REQ_EVENT, vcpu);
7408
875656fe 7409 vcpu_put(vcpu);
b6c7a5dc
HB		 7410 return 0;
7411}
7412
b6c7a5dc
HB		 7413void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7414{
7415 struct kvm_segment cs;
7416
3e6e0aab 7417 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7418 *db = cs.db;
7419 *l = cs.l;
7420}
7421EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7422
7423int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7424 struct kvm_sregs *sregs)
7425{
89a27f4d 7426 struct desc_ptr dt;
b6c7a5dc 7427
bcdec41c
CD		 7428 vcpu_load(vcpu);
7429
3e6e0aab
GT		 7430 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7431 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7432 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7433 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7434 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7435 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7436
3e6e0aab
GT		 7437 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7438 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7439
7440 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7441 sregs->idt.limit = dt.size;
7442 sregs->idt.base = dt.address;
b6c7a5dc 7443 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7444 sregs->gdt.limit = dt.size;
7445 sregs->gdt.base = dt.address;
b6c7a5dc 7446
4d4ec087 7447 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7448 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7449 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7450 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7451 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7452 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7453 sregs->apic_base = kvm_get_apic_base(vcpu);
7454
923c61bb 7455 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7456
36752c9b 7457 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7458 set_bit(vcpu->arch.interrupt.nr,
7459 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7460
bcdec41c 7461 vcpu_put(vcpu);
b6c7a5dc
HB		 7462 return 0;
7463}
7464
62d9f0db
MT		 7465int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7466 struct kvm_mp_state *mp_state)
7467{
fd232561
CD		 7468 vcpu_load(vcpu);
7469
66450a21 7470 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7471 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7472 vcpu->arch.pv.pv_unhalted)
7473 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7474 else
7475 mp_state->mp_state = vcpu->arch.mp_state;
7476
fd232561 7477 vcpu_put(vcpu);
62d9f0db
MT		 7478 return 0;
7479}
7480
7481int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7482 struct kvm_mp_state *mp_state)
7483{
bce87cce 7484 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7485 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7486 return -EINVAL;
7487
28bf2888
DH		 7488 /* INITs are latched while in SMM */
7489 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7490 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7491 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7492 return -EINVAL;
7493
66450a21
JK		 7494 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7495 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7496 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7497 } else
7498 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7499 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7500 return 0;
7501}
7502
7f3d35fd
KW		 7503int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7504 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7505{
9d74191a 7506 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7507 int ret;
e01c2426 7508
8ec4722d 7509 init_emulate_ctxt(vcpu);
c697518a 7510
7f3d35fd 7511 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7512 has_error_code, error_code);
c697518a 7513
c697518a 7514 if (ret)
19d04437 7515 return EMULATE_FAIL;
37817f29 7516
9d74191a
TY		 7517 kvm_rip_write(vcpu, ctxt->eip);
7518 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7519 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7520 return EMULATE_DONE;
37817f29
IE		 7521}
7522EXPORT_SYMBOL_GPL(kvm_task_switch);
7523
b6c7a5dc
HB		 7524int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7525 struct kvm_sregs *sregs)
7526{
58cb628d 7527 struct msr_data apic_base_msr;
b6c7a5dc 7528 int mmu_reset_needed = 0;
63f42e02 7529 int pending_vec, max_bits, idx;
89a27f4d 7530 struct desc_ptr dt;
b4ef9d4e
CD		 7531 int ret = -EINVAL;
7532
7533 vcpu_load(vcpu);
b6c7a5dc 7534
d6321d49
RK		 7535 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7536 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7537 goto out;
6d1068b3 7538
d3802286
JM		 7539 apic_base_msr.data = sregs->apic_base;
7540 apic_base_msr.host_initiated = true;
7541 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7542 goto out;
6d1068b3 7543
89a27f4d
GN		 7544 dt.size = sregs->idt.limit;
7545 dt.address = sregs->idt.base;
b6c7a5dc 7546 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7547 dt.size = sregs->gdt.limit;
7548 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7549 kvm_x86_ops->set_gdt(vcpu, &dt);
7550
ad312c7c 7551 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7552 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7553 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7554 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7555
2d3ad1f4 7556 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7557
f6801dff 7558 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7559 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7560
4d4ec087 7561 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7562 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7563 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7564
fc78f519 7565 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7566 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7567 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7568 kvm_update_cpuid(vcpu);
63f42e02
XG		 7569
7570 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7571 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7572 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7573 mmu_reset_needed = 1;
7574 }
63f42e02 7575 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7576
7577 if (mmu_reset_needed)
7578 kvm_mmu_reset_context(vcpu);
7579
a50abc3b 7580 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7581 pending_vec = find_first_bit(
7582 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7583 if (pending_vec < max_bits) {
66fd3f7f 7584 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7585 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7586 }
7587
3e6e0aab
GT		 7588 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7589 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7590 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7591 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7592 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7593 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7594
3e6e0aab
GT		 7595 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7596 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7597
5f0269f5
ME		 7598 update_cr8_intercept(vcpu);
7599
9c3e4aab 7600 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7601 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7602 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7603 !is_protmode(vcpu))
9c3e4aab
MT		 7604 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7605
3842d135
AK		 7606 kvm_make_request(KVM_REQ_EVENT, vcpu);
7607
b4ef9d4e
CD		 7608 ret = 0;
7609out:
7610 vcpu_put(vcpu);
7611 return ret;
b6c7a5dc
HB		 7612}
7613
d0bfb940
JK		 7614int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7615 struct kvm_guest_debug *dbg)
b6c7a5dc 7616{
355be0b9 7617 unsigned long rflags;
ae675ef0 7618 int i, r;
b6c7a5dc 7619
4f926bf2
JK		 7620 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7621 r = -EBUSY;
7622 if (vcpu->arch.exception.pending)
2122ff5e 7623 goto out;
4f926bf2
JK		 7624 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7625 kvm_queue_exception(vcpu, DB_VECTOR);
7626 else
7627 kvm_queue_exception(vcpu, BP_VECTOR);
7628 }
7629
91586a3b
JK		 7630 /*
7631 * Read rflags as long as potentially injected trace flags are still
7632 * filtered out.
7633 */
7634 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7635
7636 vcpu->guest_debug = dbg->control;
7637 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7638 vcpu->guest_debug = 0;
7639
7640 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7641 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7642 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7643 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7644 } else {
7645 for (i = 0; i < KVM_NR_DB_REGS; i++)
7646 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7647 }
c8639010 7648 kvm_update_dr7(vcpu);
ae675ef0 7649
f92653ee
JK		 7650 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7651 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7652 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7653
91586a3b
JK		 7654 /*
7655 * Trigger an rflags update that will inject or remove the trace
7656 * flags.
7657 */
7658 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7659
a96036b8 7660 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7661
4f926bf2 7662 r = 0;
d0bfb940 7663
2122ff5e 7664out:
b6c7a5dc
HB		 7665
7666 return r;
7667}
7668
8b006791
ZX		 7669/*
7670 * Translate a guest virtual address to a guest physical address.
7671 */
7672int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7673 struct kvm_translation *tr)
7674{
7675 unsigned long vaddr = tr->linear_address;
7676 gpa_t gpa;
f656ce01 7677 int idx;
8b006791 7678
f656ce01 7679 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7680 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7681 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7682 tr->physical_address = gpa;
7683 tr->valid = gpa != UNMAPPED_GVA;
7684 tr->writeable = 1;
7685 tr->usermode = 0;
8b006791
ZX		 7686
7687 return 0;
7688}
7689
d0752060
HB		 7690int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7691{
c47ada30 7692 struct fxregs_state *fxsave =
7366ed77 7693 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7694
d0752060
HB		 7695 memcpy(fpu->fpr, fxsave->st_space, 128);
7696 fpu->fcw = fxsave->cwd;
7697 fpu->fsw = fxsave->swd;
7698 fpu->ftwx = fxsave->twd;
7699 fpu->last_opcode = fxsave->fop;
7700 fpu->last_ip = fxsave->rip;
7701 fpu->last_dp = fxsave->rdp;
7702 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7703
d0752060
HB		 7704 return 0;
7705}
7706
7707int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7708{
c47ada30 7709 struct fxregs_state *fxsave =
7366ed77 7710 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7711
d0752060
HB		 7712 memcpy(fxsave->st_space, fpu->fpr, 128);
7713 fxsave->cwd = fpu->fcw;
7714 fxsave->swd = fpu->fsw;
7715 fxsave->twd = fpu->ftwx;
7716 fxsave->fop = fpu->last_opcode;
7717 fxsave->rip = fpu->last_ip;
7718 fxsave->rdp = fpu->last_dp;
7719 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7720
d0752060
HB		 7721 return 0;
7722}
7723
0ee6a517 7724static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7725{
bf935b0b 7726 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7727 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7728 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7729 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7730
2acf923e
DC		 7731 /*
7732 * Ensure guest xcr0 is valid for loading
7733 */
d91cab78 7734 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7735
ad312c7c 7736 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7737}
d0752060 7738
f775b13e 7739/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 7740void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7741{
f775b13e
RR		 7742 preempt_disable();
7743 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 7744 /* PKRU is separately restored in kvm_x86_ops->run. */
7745 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7746 ~XFEATURE_MASK_PKRU);
f775b13e 7747 preempt_enable();
0c04851c 7748 trace_kvm_fpu(1);
d0752060 7749}
d0752060 7750
f775b13e 7751/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 7752void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7753{
f775b13e 7754 preempt_disable();
4f836347 7755 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 7756 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7757 preempt_enable();
f096ed85 7758 ++vcpu->stat.fpu_reload;
0c04851c 7759 trace_kvm_fpu(0);
d0752060 7760}
e9b11c17
ZX		 7761
7762void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7763{
bd768e14
IY		 7764 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7765
12f9a48f 7766 kvmclock_reset(vcpu);
7f1ea208 7767
e9b11c17 7768 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7769 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7770}
7771
7772struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7773 unsigned int id)
7774{
c447e76b
LL		 7775 struct kvm_vcpu *vcpu;
7776
6755bae8
ZA		 7777 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7778 printk_once(KERN_WARNING
7779 "kvm: SMP vm created on host with unstable TSC; "
7780 "guest TSC will not be reliable\n");
c447e76b
LL		 7781
7782 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7783
c447e76b 7784 return vcpu;
26e5215f 7785}
e9b11c17 7786
26e5215f
AK		 7787int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7788{
19efffa2 7789 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 7790 vcpu_load(vcpu);
d28bc9dd 7791 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7792 kvm_mmu_setup(vcpu);
e9b11c17 7793 vcpu_put(vcpu);
ec7660cc 7794 return 0;
e9b11c17
ZX		 7795}
7796
31928aa5 7797void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7798{
8fe8ab46 7799 struct msr_data msr;
332967a3 7800 struct kvm *kvm = vcpu->kvm;
42897d86 7801
d3457c87
RK		 7802 kvm_hv_vcpu_postcreate(vcpu);
7803
ec7660cc 7804 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 7805 return;
ec7660cc 7806 vcpu_load(vcpu);
8fe8ab46
WA		 7807 msr.data = 0x0;
7808 msr.index = MSR_IA32_TSC;
7809 msr.host_initiated = true;
7810 kvm_write_tsc(vcpu, &msr);
42897d86 7811 vcpu_put(vcpu);
ec7660cc 7812 mutex_unlock(&vcpu->mutex);
42897d86 7813
630994b3
MT		 7814 if (!kvmclock_periodic_sync)
7815 return;
7816
332967a3
AJ		 7817 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7818 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7819}
7820
d40ccc62 7821void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7822{
344d9588
GN		 7823 vcpu->arch.apf.msr_val = 0;
7824
ec7660cc 7825 vcpu_load(vcpu);
e9b11c17
ZX		 7826 kvm_mmu_unload(vcpu);
7827 vcpu_put(vcpu);
7828
7829 kvm_x86_ops->vcpu_free(vcpu);
7830}
7831
d28bc9dd 7832void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7833{
e69fab5d
PB		 7834 vcpu->arch.hflags = 0;
7835
c43203ca 7836 vcpu->arch.smi_pending = 0;
52797bf9 7837 vcpu->arch.smi_count = 0;
7460fb4a
AK		 7838 atomic_set(&vcpu->arch.nmi_queued, 0);
7839 vcpu->arch.nmi_pending = 0;
448fa4a9 7840 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7841 kvm_clear_interrupt_queue(vcpu);
7842 kvm_clear_exception_queue(vcpu);
664f8e26 7843 vcpu->arch.exception.pending = false;
448fa4a9 7844
42dbaa5a 7845 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7846 kvm_update_dr0123(vcpu);
6f43ed01 7847 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7848 kvm_update_dr6(vcpu);
42dbaa5a 7849 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7850 kvm_update_dr7(vcpu);
42dbaa5a 7851
1119022c
NA		 7852 vcpu->arch.cr2 = 0;
7853
3842d135 7854 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7855 vcpu->arch.apf.msr_val = 0;
c9aaa895 7856 vcpu->arch.st.msr_val = 0;
3842d135 7857
12f9a48f
GC		 7858 kvmclock_reset(vcpu);
7859
af585b92
GN		 7860 kvm_clear_async_pf_completion_queue(vcpu);
7861 kvm_async_pf_hash_reset(vcpu);
7862 vcpu->arch.apf.halted = false;
3842d135 7863
a554d207
WL		 7864 if (kvm_mpx_supported()) {
7865 void *mpx_state_buffer;
7866
7867 /*
7868 * To avoid have the INIT path from kvm_apic_has_events() that be
7869 * called with loaded FPU and does not let userspace fix the state.
7870 */
f775b13e
RR		 7871 if (init_event)
7872 kvm_put_guest_fpu(vcpu);
a554d207
WL		 7873 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7874 XFEATURE_MASK_BNDREGS);
7875 if (mpx_state_buffer)
7876 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7877 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7878 XFEATURE_MASK_BNDCSR);
7879 if (mpx_state_buffer)
7880 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 7881 if (init_event)
7882 kvm_load_guest_fpu(vcpu);
a554d207
WL		 7883 }
7884
64d60670 7885 if (!init_event) {
d28bc9dd 7886 kvm_pmu_reset(vcpu);
64d60670 7887 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7888
7889 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7890 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7891
7892 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7893 }
f5132b01 7894
66f7b72e
JS		 7895 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7896 vcpu->arch.regs_avail = ~0;
7897 vcpu->arch.regs_dirty = ~0;
7898
a554d207
WL		 7899 vcpu->arch.ia32_xss = 0;
7900
d28bc9dd 7901 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7902}
7903
2b4a273b 7904void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7905{
7906 struct kvm_segment cs;
7907
7908 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7909 cs.selector = vector << 8;
7910 cs.base = vector << 12;
7911 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7912 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7913}
7914
13a34e06 7915int kvm_arch_hardware_enable(void)
e9b11c17 7916{
ca84d1a2
ZA		 7917 struct kvm *kvm;
7918 struct kvm_vcpu *vcpu;
7919 int i;
0dd6a6ed
ZA		 7920 int ret;
7921 u64 local_tsc;
7922 u64 max_tsc = 0;
7923 bool stable, backwards_tsc = false;
18863bdd
AK		 7924
7925 kvm_shared_msr_cpu_online();
13a34e06 7926 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7927 if (ret != 0)
7928 return ret;
7929
4ea1636b 7930 local_tsc = rdtsc();
0dd6a6ed
ZA		 7931 stable = !check_tsc_unstable();
7932 list_for_each_entry(kvm, &vm_list, vm_list) {
7933 kvm_for_each_vcpu(i, vcpu, kvm) {
7934 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7935 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7936 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7937 backwards_tsc = true;
7938 if (vcpu->arch.last_host_tsc > max_tsc)
7939 max_tsc = vcpu->arch.last_host_tsc;
7940 }
7941 }
7942 }
7943
7944 /*
7945 * Sometimes, even reliable TSCs go backwards. This happens on
7946 * platforms that reset TSC during suspend or hibernate actions, but
7947 * maintain synchronization. We must compensate. Fortunately, we can
7948 * detect that condition here, which happens early in CPU bringup,
7949 * before any KVM threads can be running. Unfortunately, we can't
7950 * bring the TSCs fully up to date with real time, as we aren't yet far
7951 * enough into CPU bringup that we know how much real time has actually
108b249c 7952 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7953 * variables that haven't been updated yet.
7954 *
7955 * So we simply find the maximum observed TSC above, then record the
7956 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7957 * the adjustment will be applied. Note that we accumulate
7958 * adjustments, in case multiple suspend cycles happen before some VCPU
7959 * gets a chance to run again. In the event that no KVM threads get a
7960 * chance to run, we will miss the entire elapsed period, as we'll have
7961 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7962 * loose cycle time. This isn't too big a deal, since the loss will be
7963 * uniform across all VCPUs (not to mention the scenario is extremely
7964 * unlikely). It is possible that a second hibernate recovery happens
7965 * much faster than a first, causing the observed TSC here to be
7966 * smaller; this would require additional padding adjustment, which is
7967 * why we set last_host_tsc to the local tsc observed here.
7968 *
7969 * N.B. - this code below runs only on platforms with reliable TSC,
7970 * as that is the only way backwards_tsc is set above. Also note
7971 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7972 * have the same delta_cyc adjustment applied if backwards_tsc
7973 * is detected. Note further, this adjustment is only done once,
7974 * as we reset last_host_tsc on all VCPUs to stop this from being
7975 * called multiple times (one for each physical CPU bringup).
7976 *
4a969980 7977 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7978 * will be compensated by the logic in vcpu_load, which sets the TSC to
7979 * catchup mode. This will catchup all VCPUs to real time, but cannot
7980 * guarantee that they stay in perfect synchronization.
7981 */
7982 if (backwards_tsc) {
7983 u64 delta_cyc = max_tsc - local_tsc;
7984 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7985 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7986 kvm_for_each_vcpu(i, vcpu, kvm) {
7987 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7988 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7989 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7990 }
7991
7992 /*
7993 * We have to disable TSC offset matching.. if you were
7994 * booting a VM while issuing an S4 host suspend....
7995 * you may have some problem. Solving this issue is
7996 * left as an exercise to the reader.
7997 */
7998 kvm->arch.last_tsc_nsec = 0;
7999 kvm->arch.last_tsc_write = 0;
8000 }
8001
8002 }
8003 return 0;
e9b11c17
ZX		 8004}
8005
13a34e06 8006void kvm_arch_hardware_disable(void)
e9b11c17 8007{
13a34e06
RK		 8008 kvm_x86_ops->hardware_disable();
8009 drop_user_return_notifiers();
e9b11c17
ZX		 8010}
8011
8012int kvm_arch_hardware_setup(void)
8013{
9e9c3fe4
NA		 8014 int r;
8015
8016 r = kvm_x86_ops->hardware_setup();
8017 if (r != 0)
8018 return r;
8019
35181e86
HZ		 8020 if (kvm_has_tsc_control) {
8021 /*
8022 * Make sure the user can only configure tsc_khz values that
8023 * fit into a signed integer.
8024 * A min value is not calculated needed because it will always
8025 * be 1 on all machines.
8026 */
8027 u64 max = min(0x7fffffffULL,
8028 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8029 kvm_max_guest_tsc_khz = max;
8030
ad721883 8031 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8032 }
ad721883 8033
9e9c3fe4
NA		 8034 kvm_init_msr_list();
8035 return 0;
e9b11c17
ZX		 8036}
8037
8038void kvm_arch_hardware_unsetup(void)
8039{
8040 kvm_x86_ops->hardware_unsetup();
8041}
8042
8043void kvm_arch_check_processor_compat(void *rtn)
8044{
8045 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8046}
8047
8048bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8049{
8050 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8051}
8052EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8053
8054bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8055{
8056 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8057}
8058
54e9818f 8059struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8060EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8061
e9b11c17
ZX		 8062int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8063{
8064 struct page *page;
e9b11c17
ZX		 8065 int r;
8066
b2a05fef 8067 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8068 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8069 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8070 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8071 else
a4535290 8072 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8073
8074 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8075 if (!page) {
8076 r = -ENOMEM;
8077 goto fail;
8078 }
ad312c7c 8079 vcpu->arch.pio_data = page_address(page);
e9b11c17 8080
cc578287 8081 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8082
e9b11c17
ZX		 8083 r = kvm_mmu_create(vcpu);
8084 if (r < 0)
8085 goto fail_free_pio_data;
8086
26de7988 8087 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8088 r = kvm_create_lapic(vcpu);
8089 if (r < 0)
8090 goto fail_mmu_destroy;
54e9818f
GN		 8091 } else
8092 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8093
890ca9ae
HY		 8094 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8095 GFP_KERNEL);
8096 if (!vcpu->arch.mce_banks) {
8097 r = -ENOMEM;
443c39bc 8098 goto fail_free_lapic;
890ca9ae
HY		 8099 }
8100 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8101
f1797359
WY		 8102 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8103 r = -ENOMEM;
f5f48ee1 8104 goto fail_free_mce_banks;
f1797359 8105 }
f5f48ee1 8106
0ee6a517 8107 fx_init(vcpu);
66f7b72e 8108
4344ee98 8109 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8110
5a4f55cd
EK		 8111 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8112
74545705
RK		 8113 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8114
af585b92 8115 kvm_async_pf_hash_reset(vcpu);
f5132b01 8116 kvm_pmu_init(vcpu);
af585b92 8117
1c1a9ce9 8118 vcpu->arch.pending_external_vector = -1;
de63ad4c 8119 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8120
5c919412
AS		 8121 kvm_hv_vcpu_init(vcpu);
8122
e9b11c17 8123 return 0;
0ee6a517 8124
f5f48ee1
SY		 8125fail_free_mce_banks:
8126 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8127fail_free_lapic:
8128 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8129fail_mmu_destroy:
8130 kvm_mmu_destroy(vcpu);
8131fail_free_pio_data:
ad312c7c 8132 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8133fail:
8134 return r;
8135}
8136
8137void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8138{
f656ce01
MT		 8139 int idx;
8140
1f4b34f8 8141 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8142 kvm_pmu_destroy(vcpu);
36cb93fd 8143 kfree(vcpu->arch.mce_banks);
e9b11c17 8144 kvm_free_lapic(vcpu);
f656ce01 8145 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8146 kvm_mmu_destroy(vcpu);
f656ce01 8147 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8148 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8149 if (!lapic_in_kernel(vcpu))
54e9818f 8150 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8151}
d19a9cd2 8152
e790d9ef
RK		 8153void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8154{
ae97a3b8 8155 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8156}
8157
e08b9637 8158int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8159{
e08b9637
CO		 8160 if (type)
8161 return -EINVAL;
8162
6ef768fa 8163 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8164 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8165 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8166 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8167 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8168
5550af4d
SY		 8169 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8170 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8171 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8172 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8173 &kvm->arch.irq_sources_bitmap);
5550af4d 8174
038f8c11 8175 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8176 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8177 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8178 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8179
108b249c 8180 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8181 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8182
7e44e449 8183 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8184 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8185
0eb05bf2 8186 kvm_page_track_init(kvm);
13d268ca 8187 kvm_mmu_init_vm(kvm);
0eb05bf2 8188
03543133
SS		 8189 if (kvm_x86_ops->vm_init)
8190 return kvm_x86_ops->vm_init(kvm);
8191
d89f5eff 8192 return 0;
d19a9cd2
ZX		 8193}
8194
8195static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8196{
ec7660cc 8197 vcpu_load(vcpu);
d19a9cd2
ZX		 8198 kvm_mmu_unload(vcpu);
8199 vcpu_put(vcpu);
8200}
8201
8202static void kvm_free_vcpus(struct kvm *kvm)
8203{
8204 unsigned int i;
988a2cae 8205 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8206
8207 /*
8208 * Unpin any mmu pages first.
8209 */
af585b92
GN		 8210 kvm_for_each_vcpu(i, vcpu, kvm) {
8211 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8212 kvm_unload_vcpu_mmu(vcpu);
af585b92 8213 }
988a2cae
GN		 8214 kvm_for_each_vcpu(i, vcpu, kvm)
8215 kvm_arch_vcpu_free(vcpu);
8216
8217 mutex_lock(&kvm->lock);
8218 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8219 kvm->vcpus[i] = NULL;
d19a9cd2 8220
988a2cae
GN		 8221 atomic_set(&kvm->online_vcpus, 0);
8222 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8223}
8224
ad8ba2cd
SY		 8225void kvm_arch_sync_events(struct kvm *kvm)
8226{
332967a3 8227 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8228 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8229 kvm_free_pit(kvm);
ad8ba2cd
SY		 8230}
8231
1d8007bd 8232int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8233{
8234 int i, r;
25188b99 8235 unsigned long hva;
f0d648bd
PB		 8236 struct kvm_memslots *slots = kvm_memslots(kvm);
8237 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8238
8239 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8240 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8241 return -EINVAL;
9da0e4d5 8242
f0d648bd
PB		 8243 slot = id_to_memslot(slots, id);
8244 if (size) {
b21629da 8245 if (slot->npages)
f0d648bd
PB		 8246 return -EEXIST;
8247
8248 /*
8249 * MAP_SHARED to prevent internal slot pages from being moved
8250 * by fork()/COW.
8251 */
8252 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8253 MAP_SHARED | MAP_ANONYMOUS, 0);
8254 if (IS_ERR((void *)hva))
8255 return PTR_ERR((void *)hva);
8256 } else {
8257 if (!slot->npages)
8258 return 0;
8259
8260 hva = 0;
8261 }
8262
8263 old = *slot;
9da0e4d5 8264 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8265 struct kvm_userspace_memory_region m;
9da0e4d5 8266
1d8007bd
PB		 8267 m.slot = id | (i << 16);
8268 m.flags = 0;
8269 m.guest_phys_addr = gpa;
f0d648bd 8270 m.userspace_addr = hva;
1d8007bd 8271 m.memory_size = size;
9da0e4d5
PB		 8272 r = __kvm_set_memory_region(kvm, &m);
8273 if (r < 0)
8274 return r;
8275 }
8276
f0d648bd
PB		 8277 if (!size) {
8278 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8279 WARN_ON(r < 0);
8280 }
8281
9da0e4d5
PB		 8282 return 0;
8283}
8284EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8285
1d8007bd 8286int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8287{
8288 int r;
8289
8290 mutex_lock(&kvm->slots_lock);
1d8007bd 8291 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8292 mutex_unlock(&kvm->slots_lock);
8293
8294 return r;
8295}
8296EXPORT_SYMBOL_GPL(x86_set_memory_region);
8297
d19a9cd2
ZX		 8298void kvm_arch_destroy_vm(struct kvm *kvm)
8299{
27469d29
AH		 8300 if (current->mm == kvm->mm) {
8301 /*
8302 * Free memory regions allocated on behalf of userspace,
8303 * unless the the memory map has changed due to process exit
8304 * or fd copying.
8305 */
1d8007bd
PB		 8306 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8307 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8308 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8309 }
03543133
SS		 8310 if (kvm_x86_ops->vm_destroy)
8311 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8312 kvm_pic_destroy(kvm);
8313 kvm_ioapic_destroy(kvm);
d19a9cd2 8314 kvm_free_vcpus(kvm);
af1bae54 8315 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8316 kvm_mmu_uninit_vm(kvm);
2beb6dad 8317 kvm_page_track_cleanup(kvm);
d19a9cd2 8318}
0de10343 8319
5587027c 8320void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8321 struct kvm_memory_slot *dont)
8322{
8323 int i;
8324
d89cc617
TY		 8325 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8326 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8327 kvfree(free->arch.rmap[i]);
d89cc617 8328 free->arch.rmap[i] = NULL;
77d11309 8329 }
d89cc617
TY		 8330 if (i == 0)
8331 continue;
8332
8333 if (!dont || free->arch.lpage_info[i - 1] !=
8334 dont->arch.lpage_info[i - 1]) {
548ef284 8335 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8336 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8337 }
8338 }
21ebbeda
XG		 8339
8340 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8341}
8342
5587027c
AK		 8343int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8344 unsigned long npages)
db3fe4eb
TY		 8345{
8346 int i;
8347
d89cc617 8348 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8349 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8350 unsigned long ugfn;
8351 int lpages;
d89cc617 8352 int level = i + 1;
db3fe4eb
TY		 8353
8354 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8355 slot->base_gfn, level) + 1;
8356
d89cc617 8357 slot->arch.rmap[i] =
a7c3e901 8358 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8359 if (!slot->arch.rmap[i])
77d11309 8360 goto out_free;
d89cc617
TY		 8361 if (i == 0)
8362 continue;
77d11309 8363
a7c3e901 8364 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8365 if (!linfo)
db3fe4eb
TY		 8366 goto out_free;
8367
92f94f1e
XG		 8368 slot->arch.lpage_info[i - 1] = linfo;
8369
db3fe4eb 8370 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8371 linfo[0].disallow_lpage = 1;
db3fe4eb 8372 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8373 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8374 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8375 /*
8376 * If the gfn and userspace address are not aligned wrt each
8377 * other, or if explicitly asked to, disable large page
8378 * support for this slot
8379 */
8380 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8381 !kvm_largepages_enabled()) {
8382 unsigned long j;
8383
8384 for (j = 0; j < lpages; ++j)
92f94f1e 8385 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8386 }
8387 }
8388
21ebbeda
XG		 8389 if (kvm_page_track_create_memslot(slot, npages))
8390 goto out_free;
8391
db3fe4eb
TY		 8392 return 0;
8393
8394out_free:
d89cc617 8395 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8396 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8397 slot->arch.rmap[i] = NULL;
8398 if (i == 0)
8399 continue;
8400
548ef284 8401 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8402 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8403 }
8404 return -ENOMEM;
8405}
8406
15f46015 8407void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8408{
e6dff7d1
TY		 8409 /*
8410 * memslots->generation has been incremented.
8411 * mmio generation may have reached its maximum value.
8412 */
54bf36aa 8413 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8414}
8415
f7784b8e
MT		 8416int kvm_arch_prepare_memory_region(struct kvm *kvm,
8417 struct kvm_memory_slot *memslot,
09170a49 8418 const struct kvm_userspace_memory_region *mem,
7b6195a9 8419 enum kvm_mr_change change)
0de10343 8420{
f7784b8e
MT		 8421 return 0;
8422}
8423
88178fd4
KH		 8424static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8425 struct kvm_memory_slot *new)
8426{
8427 /* Still write protect RO slot */
8428 if (new->flags & KVM_MEM_READONLY) {
8429 kvm_mmu_slot_remove_write_access(kvm, new);
8430 return;
8431 }
8432
8433 /*
8434 * Call kvm_x86_ops dirty logging hooks when they are valid.
8435 *
8436 * kvm_x86_ops->slot_disable_log_dirty is called when:
8437 *
8438 * - KVM_MR_CREATE with dirty logging is disabled
8439 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8440 *
8441 * The reason is, in case of PML, we need to set D-bit for any slots
8442 * with dirty logging disabled in order to eliminate unnecessary GPA
8443 * logging in PML buffer (and potential PML buffer full VMEXT). This
8444 * guarantees leaving PML enabled during guest's lifetime won't have
8445 * any additonal overhead from PML when guest is running with dirty
8446 * logging disabled for memory slots.
8447 *
8448 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8449 * to dirty logging mode.
8450 *
8451 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8452 *
8453 * In case of write protect:
8454 *
8455 * Write protect all pages for dirty logging.
8456 *
8457 * All the sptes including the large sptes which point to this
8458 * slot are set to readonly. We can not create any new large
8459 * spte on this slot until the end of the logging.
8460 *
8461 * See the comments in fast_page_fault().
8462 */
8463 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8464 if (kvm_x86_ops->slot_enable_log_dirty)
8465 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8466 else
8467 kvm_mmu_slot_remove_write_access(kvm, new);
8468 } else {
8469 if (kvm_x86_ops->slot_disable_log_dirty)
8470 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8471 }
8472}
8473
f7784b8e 8474void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8475 const struct kvm_userspace_memory_region *mem,
8482644a 8476 const struct kvm_memory_slot *old,
f36f3f28 8477 const struct kvm_memory_slot *new,
8482644a 8478 enum kvm_mr_change change)
f7784b8e 8479{
8482644a 8480 int nr_mmu_pages = 0;
f7784b8e 8481
48c0e4e9
XG		 8482 if (!kvm->arch.n_requested_mmu_pages)
8483 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8484
48c0e4e9 8485 if (nr_mmu_pages)
0de10343 8486 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8487
3ea3b7fa
WL		 8488 /*
8489 * Dirty logging tracks sptes in 4k granularity, meaning that large
8490 * sptes have to be split. If live migration is successful, the guest
8491 * in the source machine will be destroyed and large sptes will be
8492 * created in the destination. However, if the guest continues to run
8493 * in the source machine (for example if live migration fails), small
8494 * sptes will remain around and cause bad performance.
8495 *
8496 * Scan sptes if dirty logging has been stopped, dropping those
8497 * which can be collapsed into a single large-page spte. Later
8498 * page faults will create the large-page sptes.
8499 */
8500 if ((change != KVM_MR_DELETE) &&
8501 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8502 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8503 kvm_mmu_zap_collapsible_sptes(kvm, new);
8504
c972f3b1 8505 /*
88178fd4 8506 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8507 *
88178fd4
KH		 8508 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8509 * been zapped so no dirty logging staff is needed for old slot. For
8510 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8511 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8512 *
8513 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8514 */
88178fd4 8515 if (change != KVM_MR_DELETE)
f36f3f28 8516 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8517}
1d737c8a 8518
2df72e9b 8519void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8520{
6ca18b69 8521 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8522}
8523
2df72e9b
MT		 8524void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8525 struct kvm_memory_slot *slot)
8526{
ae7cd873 8527 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8528}
8529
5d9bc648
PB		 8530static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8531{
8532 if (!list_empty_careful(&vcpu->async_pf.done))
8533 return true;
8534
8535 if (kvm_apic_has_events(vcpu))
8536 return true;
8537
8538 if (vcpu->arch.pv.pv_unhalted)
8539 return true;
8540
a5f01f8e
WL		 8541 if (vcpu->arch.exception.pending)
8542 return true;
8543
47a66eed
Z		 8544 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8545 (vcpu->arch.nmi_pending &&
8546 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8547 return true;
8548
47a66eed
Z		 8549 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8550 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8551 return true;
8552
5d9bc648
PB		 8553 if (kvm_arch_interrupt_allowed(vcpu) &&
8554 kvm_cpu_has_interrupt(vcpu))
8555 return true;
8556
1f4b34f8
AS		 8557 if (kvm_hv_has_stimer_pending(vcpu))
8558 return true;
8559
5d9bc648
PB		 8560 return false;
8561}
8562
1d737c8a
ZX		 8563int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8564{
5d9bc648 8565 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8566}
5736199a 8567
199b5763
LM		 8568bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8569{
de63ad4c 8570 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8571}
8572
b6d33834 8573int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8574{
b6d33834 8575 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8576}
78646121
GN		 8577
8578int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8579{
8580 return kvm_x86_ops->interrupt_allowed(vcpu);
8581}
229456fc 8582
82b32774 8583unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8584{
82b32774
NA		 8585 if (is_64_bit_mode(vcpu))
8586 return kvm_rip_read(vcpu);
8587 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8588 kvm_rip_read(vcpu));
8589}
8590EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8591
82b32774
NA		 8592bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8593{
8594 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8595}
8596EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8597
94fe45da
JK		 8598unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8599{
8600 unsigned long rflags;
8601
8602 rflags = kvm_x86_ops->get_rflags(vcpu);
8603 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8604 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8605 return rflags;
8606}
8607EXPORT_SYMBOL_GPL(kvm_get_rflags);
8608
6addfc42 8609static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8610{
8611 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8612 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8613 rflags |= X86_EFLAGS_TF;
94fe45da 8614 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8615}
8616
8617void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8618{
8619 __kvm_set_rflags(vcpu, rflags);
3842d135 8620 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8621}
8622EXPORT_SYMBOL_GPL(kvm_set_rflags);
8623
56028d08
GN		 8624void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8625{
8626 int r;
8627
fb67e14f 8628 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8629 work->wakeup_all)
56028d08
GN		 8630 return;
8631
8632 r = kvm_mmu_reload(vcpu);
8633 if (unlikely(r))
8634 return;
8635
fb67e14f
XG		 8636 if (!vcpu->arch.mmu.direct_map &&
8637 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8638 return;
8639
56028d08
GN		 8640 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8641}
8642
af585b92
GN		 8643static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8644{
8645 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8646}
8647
8648static inline u32 kvm_async_pf_next_probe(u32 key)
8649{
8650 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8651}
8652
8653static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8654{
8655 u32 key = kvm_async_pf_hash_fn(gfn);
8656
8657 while (vcpu->arch.apf.gfns[key] != ~0)
8658 key = kvm_async_pf_next_probe(key);
8659
8660 vcpu->arch.apf.gfns[key] = gfn;
8661}
8662
8663static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8664{
8665 int i;
8666 u32 key = kvm_async_pf_hash_fn(gfn);
8667
8668 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8669 (vcpu->arch.apf.gfns[key] != gfn &&
8670 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8671 key = kvm_async_pf_next_probe(key);
8672
8673 return key;
8674}
8675
8676bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8677{
8678 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8679}
8680
8681static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8682{
8683 u32 i, j, k;
8684
8685 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8686 while (true) {
8687 vcpu->arch.apf.gfns[i] = ~0;
8688 do {
8689 j = kvm_async_pf_next_probe(j);
8690 if (vcpu->arch.apf.gfns[j] == ~0)
8691 return;
8692 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8693 /*
8694 * k lies cyclically in ]i,j]
8695 * | i.k.j |
8696 * |....j i.k.| or |.k..j i...|
8697 */
8698 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8699 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8700 i = j;
8701 }
8702}
8703
7c90705b
GN		 8704static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8705{
4e335d9e
PB		 8706
8707 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8708 sizeof(val));
7c90705b
GN		 8709}
8710
9a6e7c39
WL		 8711static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8712{
8713
8714 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8715 sizeof(u32));
8716}
8717
af585b92
GN		 8718void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8719 struct kvm_async_pf *work)
8720{
6389ee94
AK		 8721 struct x86_exception fault;
8722
7c90705b 8723 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8724 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8725
8726 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8727 (vcpu->arch.apf.send_user_only &&
8728 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8729 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8730 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8731 fault.vector = PF_VECTOR;
8732 fault.error_code_valid = true;
8733 fault.error_code = 0;
8734 fault.nested_page_fault = false;
8735 fault.address = work->arch.token;
adfe20fb 8736 fault.async_page_fault = true;
6389ee94 8737 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8738 }
af585b92
GN		 8739}
8740
8741void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8742 struct kvm_async_pf *work)
8743{
6389ee94 8744 struct x86_exception fault;
9a6e7c39 8745 u32 val;
6389ee94 8746
f2e10669 8747 if (work->wakeup_all)
7c90705b
GN		 8748 work->arch.token = ~0; /* broadcast wakeup */
8749 else
8750 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8751 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8752
9a6e7c39
WL		 8753 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8754 !apf_get_user(vcpu, &val)) {
8755 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8756 vcpu->arch.exception.pending &&
8757 vcpu->arch.exception.nr == PF_VECTOR &&
8758 !apf_put_user(vcpu, 0)) {
8759 vcpu->arch.exception.injected = false;
8760 vcpu->arch.exception.pending = false;
8761 vcpu->arch.exception.nr = 0;
8762 vcpu->arch.exception.has_error_code = false;
8763 vcpu->arch.exception.error_code = 0;
8764 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8765 fault.vector = PF_VECTOR;
8766 fault.error_code_valid = true;
8767 fault.error_code = 0;
8768 fault.nested_page_fault = false;
8769 fault.address = work->arch.token;
8770 fault.async_page_fault = true;
8771 kvm_inject_page_fault(vcpu, &fault);
8772 }
7c90705b 8773 }
e6d53e3b 8774 vcpu->arch.apf.halted = false;
a4fa1635 8775 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8776}
8777
8778bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8779{
8780 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8781 return true;
8782 else
9bc1f09f 8783 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8784}
8785
5544eb9b
PB		 8786void kvm_arch_start_assignment(struct kvm *kvm)
8787{
8788 atomic_inc(&kvm->arch.assigned_device_count);
8789}
8790EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8791
8792void kvm_arch_end_assignment(struct kvm *kvm)
8793{
8794 atomic_dec(&kvm->arch.assigned_device_count);
8795}
8796EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8797
8798bool kvm_arch_has_assigned_device(struct kvm *kvm)
8799{
8800 return atomic_read(&kvm->arch.assigned_device_count);
8801}
8802EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8803
e0f0bbc5
AW		 8804void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8805{
8806 atomic_inc(&kvm->arch.noncoherent_dma_count);
8807}
8808EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8809
8810void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8811{
8812 atomic_dec(&kvm->arch.noncoherent_dma_count);
8813}
8814EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8815
8816bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8817{
8818 return atomic_read(&kvm->arch.noncoherent_dma_count);
8819}
8820EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8821
14717e20
AW		 8822bool kvm_arch_has_irq_bypass(void)
8823{
8824 return kvm_x86_ops->update_pi_irte != NULL;
8825}
8826
87276880
FW		 8827int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8828 struct irq_bypass_producer *prod)
8829{
8830 struct kvm_kernel_irqfd *irqfd =
8831 container_of(cons, struct kvm_kernel_irqfd, consumer);
8832
14717e20 8833 irqfd->producer = prod;
87276880 8834
14717e20
AW		 8835 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8836 prod->irq, irqfd->gsi, 1);
87276880
FW		 8837}
8838
8839void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8840 struct irq_bypass_producer *prod)
8841{
8842 int ret;
8843 struct kvm_kernel_irqfd *irqfd =
8844 container_of(cons, struct kvm_kernel_irqfd, consumer);
8845
87276880
FW		 8846 WARN_ON(irqfd->producer != prod);
8847 irqfd->producer = NULL;
8848
8849 /*
8850 * When producer of consumer is unregistered, we change back to
8851 * remapped mode, so we can re-use the current implementation
bb3541f1 8852 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8853 * int this case doesn't want to receive the interrupts.
8854 */
8855 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8856 if (ret)
8857 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8858 " fails: %d\n", irqfd->consumer.token, ret);
8859}
8860
8861int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8862 uint32_t guest_irq, bool set)
8863{
8864 if (!kvm_x86_ops->update_pi_irte)
8865 return -EINVAL;
8866
8867 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8868}
8869
52004014
FW		 8870bool kvm_vector_hashing_enabled(void)
8871{
8872 return vector_hashing;
8873}
8874EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8875
229456fc 8876EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8877EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8878EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8879EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8880EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8881EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8882EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8883EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8884EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8885EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8886EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8887EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8888EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8889EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8890EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8891EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8892EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8893EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8894EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git