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* gen-engine.c (print_run_body): Avoid multi-line strings.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
f4f1b9f1
CD		 12002-06-02 Chris Demetriou <cgd@broadcom.com>
2 Ed Satterthwaite <ehs@broadcom.com>
3
4 * mips.igen (mdmx): New (pseudo-)model.
5 * mdmx.c, mdmx.igen: New files.
6 * Makefile.in (SIM_OBJS): Add mdmx.o.
7 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
8 New typedefs.
9 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
10 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
11 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
12 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
13 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
14 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
15 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
16 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
17 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
18 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
19 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
20 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
21 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
22 (qh_fmtsel): New macros.
23 (_sim_cpu): New member "acc".
24 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
25 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
26
5accf1ff
CD		 272002-05-01 Chris Demetriou <cgd@broadcom.com>
28
29 * interp.c: Use 'deprecated' rather than 'depreciated.'
30 * sim-main.h: Likewise.
31
402586aa
CD		 322002-05-01 Chris Demetriou <cgd@broadcom.com>
33
34 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
35 which wouldn't compile anyway.
36 * sim-main.h (unpredictable_action): New function prototype.
37 (Unpredictable): Define to call igen function unpredictable().
38 (NotWordValue): New macro to call igen function not_word_value().
39 (UndefinedResult): Remove.
40 * interp.c (undefined_result): Remove.
41 (unpredictable_action): New function.
42 * mips.igen (not_word_value, unpredictable): New functions.
43 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
44 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
45 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
46 NotWordValue() to check for unpredictable inputs, then
47 Unpredictable() to handle them.
48
c9b9995a
CD		 492002-02-24 Chris Demetriou <cgd@broadcom.com>
50
51 * mips.igen: Fix formatting of calls to Unpredictable().
52
e1015982
AC		 532002-04-20 Andrew Cagney <ac131313@redhat.com>
54
55 * interp.c (sim_open): Revert previous change.
56
b882a66b
AO		 572002-04-18 Alexandre Oliva <aoliva@redhat.com>
58
59 * interp.c (sim_open): Disable chunk of code that wrote code in
60 vector table entries.
61
c429b7dd
CD		 622002-03-19 Chris Demetriou <cgd@broadcom.com>
63
64 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
65 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
66 unused definitions.
67
37d146fa
CD		 682002-03-19 Chris Demetriou <cgd@broadcom.com>
69
70 * cp1.c: Fix many formatting issues.
71
07892c0b
CD		 722002-03-19 Chris G. Demetriou <cgd@broadcom.com>
73
74 * cp1.c (fpu_format_name): New function to replace...
75 (DOFMT): This. Delete, and update all callers.
76 (fpu_rounding_mode_name): New function to replace...
77 (RMMODE): This. Delete, and update all callers.
78
487f79b7
CD		 792002-03-19 Chris G. Demetriou <cgd@broadcom.com>
80
81 * interp.c: Move FPU support routines from here to...
82 * cp1.c: Here. New file.
83 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
84 (cp1.o): New target.
85
1e799e28
CD		 862002-03-12 Chris Demetriou <cgd@broadcom.com>
87
88 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
89 * mips.igen (mips32, mips64): New models, add to all instructions
90 and functions as appropriate.
91 (loadstore_ea, check_u64): New variant for model mips64.
92 (check_fmt_p): New variant for models mipsV and mips64, remove
93 mipsV model marking fro other variant.
94 (SLL) Rename to...
95 (SLLa) this.
96 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
97 for mips32 and mips64.
98 (DCLO, DCLZ): New instructions for mips64.
99
82f728db
CD		 1002002-03-07 Chris Demetriou <cgd@broadcom.com>
101
102 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
103 immediate or code as a hex value with the "%#lx" format.
104 (ANDI): Likewise, and fix printed instruction name.
105
b96e7ef1
CD		 1062002-03-05 Chris Demetriou <cgd@broadcom.com>
107
108 * sim-main.h (UndefinedResult, Unpredictable): New macros
109 which currently do nothing.
110
d35d4f70
CD		 1112002-03-05 Chris Demetriou <cgd@broadcom.com>
112
113 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
114 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
115 (status_CU3): New definitions.
116
117 * sim-main.h (ExceptionCause): Add new values for MIPS32
118 and MIPS64: MDMX, MCheck, CacheErr. Update comments
119 for DebugBreakPoint and NMIReset to note their status in
120 MIPS32 and MIPS64.
121 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
122 (SignalExceptionCacheErr): New exception macros.
123
3ad6f714
CD		 1242002-03-05 Chris Demetriou <cgd@broadcom.com>
125
126 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
127 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
128 is always enabled.
129 (SignalExceptionCoProcessorUnusable): Take as argument the
130 unusable coprocessor number.
131
86b77b47
CD		 1322002-03-05 Chris Demetriou <cgd@broadcom.com>
133
134 * mips.igen: Fix formatting of all SignalException calls.
135
97a88e93 1362002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 137
138 * sim-main.h (SIGNEXTEND): Remove.
139
97a88e93 1402002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 141
142 * mips.igen: Remove gencode comment from top of file, fix
143 spelling in another comment.
144
97a88e93 1452002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 146
147 * mips.igen (check_fmt, check_fmt_p): New functions to check
148 whether specific floating point formats are usable.
149 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
150 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
151 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
152 Use the new functions.
153 (do_c_cond_fmt): Remove format checks...
154 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
155
97a88e93 1562002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 157
158 * mips.igen: Fix formatting of check_fpu calls.
159
41774c9d
CD		 1602002-03-03 Chris Demetriou <cgd@broadcom.com>
161
162 * mips.igen (FLOOR.L.fmt): Store correct destination register.
163
4a0bd876
CD		 1642002-03-03 Chris Demetriou <cgd@broadcom.com>
165
166 * mips.igen: Remove whitespace at end of lines.
167
09297648
CD		 1682002-03-02 Chris Demetriou <cgd@broadcom.com>
169
170 * mips.igen (loadstore_ea): New function to do effective
171 address calculations.
172 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
173 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
174 CACHE): Use loadstore_ea to do effective address computations.
175
043b7057
CD		 1762002-03-02 Chris Demetriou <cgd@broadcom.com>
177
178 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
179 * mips.igen (LL, CxC1, MxC1): Likewise.
180
c1e8ada4
CD		 1812002-03-02 Chris Demetriou <cgd@broadcom.com>
182
183 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
184 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
185 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
186 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
187 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
188 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
189 Don't split opcode fields by hand, use the opcode field values
190 provided by igen.
191
3e1dca16
CD		 1922002-03-01 Chris Demetriou <cgd@broadcom.com>
193
194 * mips.igen (do_divu): Fix spacing.
195
196 * mips.igen (do_dsllv): Move to be right before DSLLV,
197 to match the rest of the do_<shift> functions.
198
fff8d27d
CD		 1992002-03-01 Chris Demetriou <cgd@broadcom.com>
200
201 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
202 DSRL32, do_dsrlv): Trace inputs and results.
203
0d3e762b
CD		 2042002-03-01 Chris Demetriou <cgd@broadcom.com>
205
206 * mips.igen (CACHE): Provide instruction-printing string.
207
208 * interp.c (signal_exception): Comment tokens after #endif.
209
eb5fcf93
CD		 2102002-02-28 Chris Demetriou <cgd@broadcom.com>
211
212 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
213 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
214 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
215 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
216 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
217 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
218 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
219 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
220
bb22bd7d
CD		 2212002-02-28 Chris Demetriou <cgd@broadcom.com>
222
223 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
224 instruction-printing string.
225 (LWU): Use '64' as the filter flag.
226
91a177cf
CD		 2272002-02-28 Chris Demetriou <cgd@broadcom.com>
228
229 * mips.igen (SDXC1): Fix instruction-printing string.
230
387f484a
CD		 2312002-02-28 Chris Demetriou <cgd@broadcom.com>
232
233 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
234 filter flags "32,f".
235
3d81f391
CD		 2362002-02-27 Chris Demetriou <cgd@broadcom.com>
237
238 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
239 as the filter flag.
240
af5107af
CD		 2412002-02-27 Chris Demetriou <cgd@broadcom.com>
242
243 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
244 add a comma) so that it more closely match the MIPS ISA
245 documentation opcode partitioning.
246 (PREF): Put useful names on opcode fields, and include
247 instruction-printing string.
248
ca971540
CD		 2492002-02-27 Chris Demetriou <cgd@broadcom.com>
250
251 * mips.igen (check_u64): New function which in the future will
252 check whether 64-bit instructions are usable and signal an
253 exception if not. Currently a no-op.
254 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
255 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
256 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
257 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
258
259 * mips.igen (check_fpu): New function which in the future will
260 check whether FPU instructions are usable and signal an exception
261 if not. Currently a no-op.
262 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
263 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
264 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
265 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
266 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
267 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
268 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
269 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
270
1c47a468
CD		 2712002-02-27 Chris Demetriou <cgd@broadcom.com>
272
273 * mips.igen (do_load_left, do_load_right): Move to be immediately
274 following do_load.
275 (do_store_left, do_store_right): Move to be immediately following
276 do_store.
277
603a98e7
CD		 2782002-02-27 Chris Demetriou <cgd@broadcom.com>
279
280 * mips.igen (mipsV): New model name. Also, add it to
281 all instructions and functions where it is appropriate.
282
c5d00cc7
CD		 2832002-02-18 Chris Demetriou <cgd@broadcom.com>
284
285 * mips.igen: For all functions and instructions, list model
286 names that support that instruction one per line.
287
074e9cb8
CD		 2882002-02-11 Chris Demetriou <cgd@broadcom.com>
289
290 * mips.igen: Add some additional comments about supported
291 models, and about which instructions go where.
292 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
293 order as is used in the rest of the file.
294
9805e229
CD		 2952002-02-11 Chris Demetriou <cgd@broadcom.com>
296
297 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
298 indicating that ALU32_END or ALU64_END are there to check
299 for overflow.
300 (DADD): Likewise, but also remove previous comment about
301 overflow checking.
302
f701dad2
CD		 3032002-02-10 Chris Demetriou <cgd@broadcom.com>
304
305 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
306 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
307 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
308 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
309 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
310 fields (i.e., add and move commas) so that they more closely
311 match the MIPS ISA documentation opcode partitioning.
312
3132002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 314
315 * mips.igen (ADDI): Print immediate value.
316 (BREAK): Print code.
317 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
318 (SLL): Print "nop" specially, and don't run the code
319 that does the shift for the "nop" case.
320
9e52972e
FF		 3212001-11-17 Fred Fish <fnf@redhat.com>
322
323 * sim-main.h (float_operation): Move enum declaration outside
324 of _sim_cpu struct declaration.
325
c0efbca4
JB		 3262001-04-12 Jim Blandy <jimb@redhat.com>
327
328 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
329 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
330 set of the FCSR.
331 * sim-main.h (COCIDX): Remove definition; this isn't supported by
332 PENDING_FILL, and you can get the intended effect gracefully by
333 calling PENDING_SCHED directly.
334
fb891446
BE		 3352001-02-23 Ben Elliston <bje@redhat.com>
336
337 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
338 already defined elsewhere.
339
8030f857
BE		 3402001-02-19 Ben Elliston <bje@redhat.com>
341
342 * sim-main.h (sim_monitor): Return an int.
343 * interp.c (sim_monitor): Add return values.
344 (signal_exception): Handle error conditions from sim_monitor.
345
56b48a7a
CD		 3462001-02-08 Ben Elliston <bje@redhat.com>
347
348 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
349 (store_memory): Likewise, pass cia to sim_core_write*.
350
d3ee60d9
FCE		 3512000-10-19 Frank Ch. Eigler <fche@redhat.com>
352
353 On advice from Chris G. Demetriou <cgd@sibyte.com>:
354 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
355
071da002
AC		 356Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
357
358 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
359 * Makefile.in: Don't delete *.igen when cleaning directory.
360
a28c02cd
AC		 361Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
362
363 * m16.igen (break): Call SignalException not sim_engine_halt.
364
80ee11fa
AC		 365Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
366
367 From Jason Eckhardt:
368 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
369
673388c0
AC		 370Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
371
372 * mips.igen (MxC1, DMxC1): Fix printf formatting.
373
4c0deff4
NC		 3742000-05-24 Michael Hayes <mhayes@cygnus.com>
375
376 * mips.igen (do_dmultx): Fix typo.
377
eb2d80b4
AC		 378Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
379
380 * configure: Regenerated to track ../common/aclocal.m4 changes.
381
dd37a34b
AC		 382Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
383
384 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
385
4c0deff4
NC		 3862000-04-12 Frank Ch. Eigler <fche@redhat.com>
387
388 * sim-main.h (GPR_CLEAR): Define macro.
389
e30db738
AC		 390Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
391
392 * interp.c (decode_coproc): Output long using %lx and not %s.
393
cb7450ea
FCE		 3942000-03-21 Frank Ch. Eigler <fche@redhat.com>
395
396 * interp.c (sim_open): Sort & extend dummy memory regions for
397 --board=jmr3904 for eCos.
398
a3027dd7
FCE		 3992000-03-02 Frank Ch. Eigler <fche@redhat.com>
400
401 * configure: Regenerated.
402
403Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
404
405 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
406 calls, conditional on the simulator being in verbose mode.
407
dfcd3bfb
JM		 408Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
409
410 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
411 cache don't get ReservedInstruction traps.
412
c2d11a7d
JM		 4131999-11-29 Mark Salter <msalter@cygnus.com>
414
415 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
416 to clear status bits in sdisr register. This is how the hardware works.
417
418 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
419 being used by cygmon.
420
4ce44c66
JM		 4211999-11-11 Andrew Haley <aph@cygnus.com>
422
423 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
424 instructions.
425
cff3e48b
JM		 426Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
427
428 * mips.igen (MULT): Correct previous mis-applied patch.
429
d4f3574e
SS		 430Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
431
432 * mips.igen (delayslot32): Handle sequence like
433 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
434 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
435 (MULT): Actually pass the third register...
436
4371999-09-03 Mark Salter <msalter@cygnus.com>
438
439 * interp.c (sim_open): Added more memory aliases for additional
440 hardware being touched by cygmon on jmr3904 board.
441
442Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
443
444 * configure: Regenerated to track ../common/aclocal.m4 changes.
445
a0b3c4fd
JM		 446Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
447
448 * interp.c (sim_store_register): Handle case where client - GDB -
449 specifies that a 4 byte register is 8 bytes in size.
450 (sim_fetch_register): Ditto.
451
adf40b2e
JM		 4521999-07-14 Frank Ch. Eigler <fche@cygnus.com>
453
454 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
455 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
456 (idt_monitor_base): Base address for IDT monitor traps.
457 (pmon_monitor_base): Ditto for PMON.
458 (lsipmon_monitor_base): Ditto for LSI PMON.
459 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
460 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
461 (sim_firmware_command): New function.
462 (mips_option_handler): Call it for OPTION_FIRMWARE.
463 (sim_open): Allocate memory for idt_monitor region. If "--board"
464 option was given, add no monitor by default. Add BREAK hooks only if
465 monitors are also there.
466
43e526b9
JM		 467Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
468
469 * interp.c (sim_monitor): Flush output before reading input.
470
471Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
472
473 * tconfig.in (SIM_HANDLES_LMA): Always define.
474
475Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
476
477 From Mark Salter <msalter@cygnus.com>:
478 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
479 (sim_open): Add setup for BSP board.
480
9846de1b
JM		 481Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
482
483 * mips.igen (MULT, MULTU): Add syntax for two operand version.
484 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
485 them as unimplemented.
486
cd0fc7c3
SS		 4871999-05-08 Felix Lee <flee@cygnus.com>
488
489 * configure: Regenerated to track ../common/aclocal.m4 changes.
490
7a292a7a
SS		 4911999-04-21 Frank Ch. Eigler <fche@cygnus.com>
492
493 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
494
495Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
496
497 * configure.in: Any mips64vr5*-*-* target should have
498 -DTARGET_ENABLE_FR=1.
499 (default_endian): Any mips64vr*el-*-* target should default to
500 LITTLE_ENDIAN.
501 * configure: Re-generate.
502
5031999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
504
505 * mips.igen (ldl): Extend from _16_, not 32.
506
507Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
508
509 * interp.c (sim_store_register): Force registers written to by GDB
510 into an un-interpreted state.
511
c906108c
SS		 5121999-02-05 Frank Ch. Eigler <fche@cygnus.com>
513
514 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
515 CPU, start periodic background I/O polls.
516 (tx3904sio_poll): New function: periodic I/O poller.
517
5181998-12-30 Frank Ch. Eigler <fche@cygnus.com>
519
520 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
521
522Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
523
524 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
525 case statement.
526
5271998-12-29 Frank Ch. Eigler <fche@cygnus.com>
528
529 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
530 (load_word): Call SIM_CORE_SIGNAL hook on error.
531 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
532 starting. For exception dispatching, pass PC instead of NULL_CIA.
533 (decode_coproc): Use COP0_BADVADDR to store faulting address.
534 * sim-main.h (COP0_BADVADDR): Define.
535 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
536 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
537 (_sim_cpu): Add exc_* fields to store register value snapshots.
538 * mips.igen (*): Replace memory-related SignalException* calls
539 with references to SIM_CORE_SIGNAL hook.
540
541 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
542 fix.
543 * sim-main.c (*): Minor warning cleanups.
544
5451998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
546
547 * m16.igen (DADDIU5): Correct type-o.
548
549Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
550
551 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
552 variables.
553
554Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
555
556 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
557 to include path.
558 (interp.o): Add dependency on itable.h
559 (oengine.c, gencode): Delete remaining references.
560 (BUILT_SRC_FROM_GEN): Clean up.
561
5621998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
563
564 * vr4run.c: New.
565 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
566 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
567 tmp-run-hack) : New.
568 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
569 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
570 Drop the "64" qualifier to get the HACK generator working.
571 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
572 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
573 qualifier to get the hack generator working.
574 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
575 (DSLL): Use do_dsll.
576 (DSLLV): Use do_dsllv.
577 (DSRA): Use do_dsra.
578 (DSRL): Use do_dsrl.
579 (DSRLV): Use do_dsrlv.
580 (BC1): Move *vr4100 to get the HACK generator working.
581 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
582 get the HACK generator working.
583 (MACC) Rename to get the HACK generator working.
584 (DMACC,MACCS,DMACCS): Add the 64.
585
5861998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
587
588 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
589 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
590
5911998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
592
593 * mips/interp.c (DEBUG): Cleanups.
594
5951998-12-10 Frank Ch. Eigler <fche@cygnus.com>
596
597 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
598 (tx3904sio_tickle): fflush after a stdout character output.
599
6001998-12-03 Frank Ch. Eigler <fche@cygnus.com>
601
602 * interp.c (sim_close): Uninstall modules.
603
604Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
605
606 * sim-main.h, interp.c (sim_monitor): Change to global
607 function.
608
609Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
610
611 * configure.in (vr4100): Only include vr4100 instructions in
612 simulator.
613 * configure: Re-generate.
614 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
615
616Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
617
618 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
619 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
620 true alternative.
621
622 * configure.in (sim_default_gen, sim_use_gen): Replace with
623 sim_gen.
624 (--enable-sim-igen): Delete config option. Always using IGEN.
625 * configure: Re-generate.
626
627 * Makefile.in (gencode): Kill, kill, kill.
628 * gencode.c: Ditto.
629
630Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
631
632 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
633 bit mips16 igen simulator.
634 * configure: Re-generate.
635
636 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
637 as part of vr4100 ISA.
638 * vr.igen: Mark all instructions as 64 bit only.
639
640Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
641
642 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
643 Pacify GCC.
644
645Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
646
647 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
648 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
649 * configure: Re-generate.
650
651 * m16.igen (BREAK): Define breakpoint instruction.
652 (JALX32): Mark instruction as mips16 and not r3900.
653 * mips.igen (C.cond.fmt): Fix typo in instruction format.
654
655 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
656
657Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
658
659 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
660 insn as a debug breakpoint.
661
662 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
663 pending.slot_size.
664 (PENDING_SCHED): Clean up trace statement.
665 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
666 (PENDING_FILL): Delay write by only one cycle.
667 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
668
669 * sim-main.c (pending_tick): Clean up trace statements. Add trace
670 of pending writes.
671 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
672 32 & 64.
673 (pending_tick): Move incrementing of index to FOR statement.
674 (pending_tick): Only update PENDING_OUT after a write has occured.
675
676 * configure.in: Add explicit mips-lsi-* target. Use gencode to
677 build simulator.
678 * configure: Re-generate.
679
680 * interp.c (sim_engine_run OLD): Delete explicit call to
681 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
682
683Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
684
685 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
686 interrupt level number to match changed SignalExceptionInterrupt
687 macro.
688
689Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
690
691 * interp.c: #include "itable.h" if WITH_IGEN.
692 (get_insn_name): New function.
693 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
694 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
695
696Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
697
698 * configure: Rebuilt to inhale new common/aclocal.m4.
699
700Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
701
702 * dv-tx3904sio.c: Include sim-assert.h.
703
704Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
705
706 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
707 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
708 Reorganize target-specific sim-hardware checks.
709 * configure: rebuilt.
710 * interp.c (sim_open): For tx39 target boards, set
711 OPERATING_ENVIRONMENT, add tx3904sio devices.
712 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
713 ROM executables. Install dv-sockser into sim-modules list.
714
715 * dv-tx3904irc.c: Compiler warning clean-up.
716 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
717 frequent hw-trace messages.
718
719Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
720
721 * vr.igen (MulAcc): Identify as a vr4100 specific function.
722
723Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
724
725 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
726
727 * vr.igen: New file.
728 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
729 * mips.igen: Define vr4100 model. Include vr.igen.
730Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
731
732 * mips.igen (check_mf_hilo): Correct check.
733
734Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
735
736 * sim-main.h (interrupt_event): Add prototype.
737
738 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
739 register_ptr, register_value.
740 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
741
742 * sim-main.h (tracefh): Make extern.
743
744Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
745
746 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
747 Reduce unnecessarily high timer event frequency.
748 * dv-tx3904cpu.c: Ditto for interrupt event.
749
750Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
751
752 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
753 to allay warnings.
754 (interrupt_event): Made non-static.
755
756 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
757 interchange of configuration values for external vs. internal
758 clock dividers.
759
760Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
761
762 * mips.igen (BREAK): Moved code to here for
763 simulator-reserved break instructions.
764 * gencode.c (build_instruction): Ditto.
765 * interp.c (signal_exception): Code moved from here. Non-
766 reserved instructions now use exception vector, rather
767 than halting sim.
768 * sim-main.h: Moved magic constants to here.
769
770Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
771
772 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
773 register upon non-zero interrupt event level, clear upon zero
774 event value.
775 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
776 by passing zero event value.
777 (*_io_{read,write}_buffer): Endianness fixes.
778 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
779 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
780
781 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
782 serial I/O and timer module at base address 0xFFFF0000.
783
784Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
785
786 * mips.igen (SWC1) : Correct the handling of ReverseEndian
787 and BigEndianCPU.
788
789Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
790
791 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
792 parts.
793 * configure: Update.
794
795Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
796
797 * dv-tx3904tmr.c: New file - implements tx3904 timer.
798 * dv-tx3904{irc,cpu}.c: Mild reformatting.
799 * configure.in: Include tx3904tmr in hw_device list.
800 * configure: Rebuilt.
801 * interp.c (sim_open): Instantiate three timer instances.
802 Fix address typo of tx3904irc instance.
803
804Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
805
806 * interp.c (signal_exception): SystemCall exception now uses
807 the exception vector.
808
809Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
810
811 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
812 to allay warnings.
813
814Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
815
816 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
817
818Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
819
820 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
821
822 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
823 sim-main.h. Declare a struct hw_descriptor instead of struct
824 hw_device_descriptor.
825
826Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
827
828 * mips.igen (do_store_left, do_load_left): Compute nr of left and
829 right bits and then re-align left hand bytes to correct byte
830 lanes. Fix incorrect computation in do_store_left when loading
831 bytes from second word.
832
833Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
834
835 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
836 * interp.c (sim_open): Only create a device tree when HW is
837 enabled.
838
839 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
840 * interp.c (signal_exception): Ditto.
841
842Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
843
844 * gencode.c: Mark BEGEZALL as LIKELY.
845
846Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
847
848 * sim-main.h (ALU32_END): Sign extend 32 bit results.
849 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
850
851Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
852
853 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
854 modules. Recognize TX39 target with "mips*tx39" pattern.
855 * configure: Rebuilt.
856 * sim-main.h (*): Added many macros defining bits in
857 TX39 control registers.
858 (SignalInterrupt): Send actual PC instead of NULL.
859 (SignalNMIReset): New exception type.
860 * interp.c (board): New variable for future use to identify
861 a particular board being simulated.
862 (mips_option_handler,mips_options): Added "--board" option.
863 (interrupt_event): Send actual PC.
864 (sim_open): Make memory layout conditional on board setting.
865 (signal_exception): Initial implementation of hardware interrupt
866 handling. Accept another break instruction variant for simulator
867 exit.
868 (decode_coproc): Implement RFE instruction for TX39.
869 (mips.igen): Decode RFE instruction as such.
870 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
871 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
872 bbegin to implement memory map.
873 * dv-tx3904cpu.c: New file.
874 * dv-tx3904irc.c: New file.
875
876Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
877
878 * mips.igen (check_mt_hilo): Create a separate r3900 version.
879
880Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
881
882 * tx.igen (madd,maddu): Replace calls to check_op_hilo
883 with calls to check_div_hilo.
884
885Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
886
887 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
888 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
889 Add special r3900 version of do_mult_hilo.
890 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
891 with calls to check_mult_hilo.
892 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
893 with calls to check_div_hilo.
894
895Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
896
897 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
898 Document a replacement.
899
900Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
901
902 * interp.c (sim_monitor): Make mon_printf work.
903
904Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
905
906 * sim-main.h (INSN_NAME): New arg `cpu'.
907
908Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
909
910 * configure: Regenerated to track ../common/aclocal.m4 changes.
911
912Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
913
914 * configure: Regenerated to track ../common/aclocal.m4 changes.
915 * config.in: Ditto.
916
917Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
918
919 * acconfig.h: New file.
920 * configure.in: Reverted change of Apr 24; use sinclude again.
921
922Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
923
924 * configure: Regenerated to track ../common/aclocal.m4 changes.
925 * config.in: Ditto.
926
927Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
928
929 * configure.in: Don't call sinclude.
930
931Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
932
933 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
934
935Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
936
937 * mips.igen (ERET): Implement.
938
939 * interp.c (decode_coproc): Return sign-extended EPC.
940
941 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
942
943 * interp.c (signal_exception): Do not ignore Trap.
944 (signal_exception): On TRAP, restart at exception address.
945 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
946 (signal_exception): Update.
947 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
948 so that TRAP instructions are caught.
949
950Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
951
952 * sim-main.h (struct hilo_access, struct hilo_history): Define,
953 contains HI/LO access history.
954 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
955 (HIACCESS, LOACCESS): Delete, replace with
956 (HIHISTORY, LOHISTORY): New macros.
957 (CHECKHILO): Delete all, moved to mips.igen
958
959 * gencode.c (build_instruction): Do not generate checks for
960 correct HI/LO register usage.
961
962 * interp.c (old_engine_run): Delete checks for correct HI/LO
963 register usage.
964
965 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
966 check_mf_cycles): New functions.
967 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
968 do_divu, domultx, do_mult, do_multu): Use.
969
970 * tx.igen ("madd", "maddu"): Use.
971
972Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
973
974 * mips.igen (DSRAV): Use function do_dsrav.
975 (SRAV): Use new function do_srav.
976
977 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
978 (B): Sign extend 11 bit immediate.
979 (EXT-B*): Shift 16 bit immediate left by 1.
980 (ADDIU*): Don't sign extend immediate value.
981
982Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
983
984 * m16run.c (sim_engine_run): Restore CIA after handling an event.
985
986 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
987 functions.
988
989 * mips.igen (delayslot32, nullify_next_insn): New functions.
990 (m16.igen): Always include.
991 (do_*): Add more tracing.
992
993 * m16.igen (delayslot16): Add NIA argument, could be called by a
994 32 bit MIPS16 instruction.
995
996 * interp.c (ifetch16): Move function from here.
997 * sim-main.c (ifetch16): To here.
998
999 * sim-main.c (ifetch16, ifetch32): Update to match current
1000 implementations of LH, LW.
1001 (signal_exception): Don't print out incorrect hex value of illegal
1002 instruction.
1003
1004Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1005
1006 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1007 instruction.
1008
1009 * m16.igen: Implement MIPS16 instructions.
1010
1011 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1012 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1013 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1014 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1015 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1016 bodies of corresponding code from 32 bit insn to these. Also used
1017 by MIPS16 versions of functions.
1018
1019 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1020 (IMEM16): Drop NR argument from macro.
1021
1022Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1023
1024 * Makefile.in (SIM_OBJS): Add sim-main.o.
1025
1026 * sim-main.h (address_translation, load_memory, store_memory,
1027 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1028 as INLINE_SIM_MAIN.
1029 (pr_addr, pr_uword64): Declare.
1030 (sim-main.c): Include when H_REVEALS_MODULE_P.
1031
1032 * interp.c (address_translation, load_memory, store_memory,
1033 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1034 from here.
1035 * sim-main.c: To here. Fix compilation problems.
1036
1037 * configure.in: Enable inlining.
1038 * configure: Re-config.
1039
1040Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1041
1042 * configure: Regenerated to track ../common/aclocal.m4 changes.
1043
1044Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1045
1046 * mips.igen: Include tx.igen.
1047 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1048 * tx.igen: New file, contains MADD and MADDU.
1049
1050 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1051 the hardwired constant `7'.
1052 (store_memory): Ditto.
1053 (LOADDRMASK): Move definition to sim-main.h.
1054
1055 mips.igen (MTC0): Enable for r3900.
1056 (ADDU): Add trace.
1057
1058 mips.igen (do_load_byte): Delete.
1059 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1060 do_store_right): New functions.
1061 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1062
1063 configure.in: Let the tx39 use igen again.
1064 configure: Update.
1065
1066Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1067
1068 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1069 not an address sized quantity. Return zero for cache sizes.
1070
1071Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1072
1073 * mips.igen (r3900): r3900 does not support 64 bit integer
1074 operations.
1075
1076Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1077
1078 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1079 than igen one.
1080 * configure : Rebuild.
1081
1082Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1083
1084 * configure: Regenerated to track ../common/aclocal.m4 changes.
1085
1086Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1087
1088 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1089
1090Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1091
1092 * configure: Regenerated to track ../common/aclocal.m4 changes.
1093 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1094
1095Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1096
1097 * configure: Regenerated to track ../common/aclocal.m4 changes.
1098
1099Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1100
1101 * interp.c (Max, Min): Comment out functions. Not yet used.
1102
1103Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1104
1105 * configure: Regenerated to track ../common/aclocal.m4 changes.
1106
1107Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1108
1109 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1110 configurable settings for stand-alone simulator.
1111
1112 * configure.in: Added X11 search, just in case.
1113
1114 * configure: Regenerated.
1115
1116Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1117
1118 * interp.c (sim_write, sim_read, load_memory, store_memory):
1119 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1120
1121Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1122
1123 * sim-main.h (GETFCC): Return an unsigned value.
1124
1125Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1126
1127 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1128 (DADD): Result destination is RD not RT.
1129
1130Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1131
1132 * sim-main.h (HIACCESS, LOACCESS): Always define.
1133
1134 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1135
1136 * interp.c (sim_info): Delete.
1137
1138Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1139
1140 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1141 (mips_option_handler): New argument `cpu'.
1142 (sim_open): Update call to sim_add_option_table.
1143
1144Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1145
1146 * mips.igen (CxC1): Add tracing.
1147
1148Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1149
1150 * sim-main.h (Max, Min): Declare.
1151
1152 * interp.c (Max, Min): New functions.
1153
1154 * mips.igen (BC1): Add tracing.
1155
1156Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1157
1158 * interp.c Added memory map for stack in vr4100
1159
1160Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1161
1162 * interp.c (load_memory): Add missing "break"'s.
1163
1164Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1165
1166 * interp.c (sim_store_register, sim_fetch_register): Pass in
1167 length parameter. Return -1.
1168
1169Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1170
1171 * interp.c: Added hardware init hook, fixed warnings.
1172
1173Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1174
1175 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1176
1177Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1178
1179 * interp.c (ifetch16): New function.
1180
1181 * sim-main.h (IMEM32): Rename IMEM.
1182 (IMEM16_IMMED): Define.
1183 (IMEM16): Define.
1184 (DELAY_SLOT): Update.
1185
1186 * m16run.c (sim_engine_run): New file.
1187
1188 * m16.igen: All instructions except LB.
1189 (LB): Call do_load_byte.
1190 * mips.igen (do_load_byte): New function.
1191 (LB): Call do_load_byte.
1192
1193 * mips.igen: Move spec for insn bit size and high bit from here.
1194 * Makefile.in (tmp-igen, tmp-m16): To here.
1195
1196 * m16.dc: New file, decode mips16 instructions.
1197
1198 * Makefile.in (SIM_NO_ALL): Define.
1199 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1200
1201Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1202
1203 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1204 point unit to 32 bit registers.
1205 * configure: Re-generate.
1206
1207Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1208
1209 * configure.in (sim_use_gen): Make IGEN the default simulator
1210 generator for generic 32 and 64 bit mips targets.
1211 * configure: Re-generate.
1212
1213Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1214
1215 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1216 bitsize.
1217
1218 * interp.c (sim_fetch_register, sim_store_register): Read/write
1219 FGR from correct location.
1220 (sim_open): Set size of FGR's according to
1221 WITH_TARGET_FLOATING_POINT_BITSIZE.
1222
1223 * sim-main.h (FGR): Store floating point registers in a separate
1224 array.
1225
1226Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1227
1228 * configure: Regenerated to track ../common/aclocal.m4 changes.
1229
1230Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1231
1232 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1233
1234 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1235
1236 * interp.c (pending_tick): New function. Deliver pending writes.
1237
1238 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1239 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1240 it can handle mixed sized quantites and single bits.
1241
1242Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1243
1244 * interp.c (oengine.h): Do not include when building with IGEN.
1245 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1246 (sim_info): Ditto for PROCESSOR_64BIT.
1247 (sim_monitor): Replace ut_reg with unsigned_word.
1248 (*): Ditto for t_reg.
1249 (LOADDRMASK): Define.
1250 (sim_open): Remove defunct check that host FP is IEEE compliant,
1251 using software to emulate floating point.
1252 (value_fpr, ...): Always compile, was conditional on HASFPU.
1253
1254Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1255
1256 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1257 size.
1258
1259 * interp.c (SD, CPU): Define.
1260 (mips_option_handler): Set flags in each CPU.
1261 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1262 (sim_close): Do not clear STATE, deleted anyway.
1263 (sim_write, sim_read): Assume CPU zero's vm should be used for
1264 data transfers.
1265 (sim_create_inferior): Set the PC for all processors.
1266 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1267 argument.
1268 (mips16_entry): Pass correct nr of args to store_word, load_word.
1269 (ColdReset): Cold reset all cpu's.
1270 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1271 (sim_monitor, load_memory, store_memory, signal_exception): Use
1272 `CPU' instead of STATE_CPU.
1273
1274
1275 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1276 SD or CPU_.
1277
1278 * sim-main.h (signal_exception): Add sim_cpu arg.
1279 (SignalException*): Pass both SD and CPU to signal_exception.
1280 * interp.c (signal_exception): Update.
1281
1282 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1283 Ditto
1284 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1285 address_translation): Ditto
1286 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1287
1288Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1289
1290 * configure: Regenerated to track ../common/aclocal.m4 changes.
1291
1292Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1293
1294 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1295
1296 * mips.igen (model): Map processor names onto BFD name.
1297
1298 * sim-main.h (CPU_CIA): Delete.
1299 (SET_CIA, GET_CIA): Define
1300
1301Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1302
1303 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1304 regiser.
1305
1306 * configure.in (default_endian): Configure a big-endian simulator
1307 by default.
1308 * configure: Re-generate.
1309
1310Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1311
1312 * configure: Regenerated to track ../common/aclocal.m4 changes.
1313
1314Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1315
1316 * interp.c (sim_monitor): Handle Densan monitor outbyte
1317 and inbyte functions.
1318
13191997-12-29 Felix Lee <flee@cygnus.com>
1320
1321 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1322
1323Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1324
1325 * Makefile.in (tmp-igen): Arrange for $zero to always be
1326 reset to zero after every instruction.
1327
1328Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1329
1330 * configure: Regenerated to track ../common/aclocal.m4 changes.
1331 * config.in: Ditto.
1332
1333Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1334
1335 * mips.igen (MSUB): Fix to work like MADD.
1336 * gencode.c (MSUB): Similarly.
1337
1338Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1339
1340 * configure: Regenerated to track ../common/aclocal.m4 changes.
1341
1342Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1343
1344 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1345
1346Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1347
1348 * sim-main.h (sim-fpu.h): Include.
1349
1350 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1351 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1352 using host independant sim_fpu module.
1353
1354Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1355
1356 * interp.c (signal_exception): Report internal errors with SIGABRT
1357 not SIGQUIT.
1358
1359 * sim-main.h (C0_CONFIG): New register.
1360 (signal.h): No longer include.
1361
1362 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1363
1364Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1365
1366 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1367
1368Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1369
1370 * mips.igen: Tag vr5000 instructions.
1371 (ANDI): Was missing mipsIV model, fix assembler syntax.
1372 (do_c_cond_fmt): New function.
1373 (C.cond.fmt): Handle mips I-III which do not support CC field
1374 separatly.
1375 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1376 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1377 in IV3.2 spec.
1378 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1379 vr5000 which saves LO in a GPR separatly.
1380
1381 * configure.in (enable-sim-igen): For vr5000, select vr5000
1382 specific instructions.
1383 * configure: Re-generate.
1384
1385Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1386
1387 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1388
1389 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1390 fmt_uninterpreted_64 bit cases to switch. Convert to
1391 fmt_formatted,
1392
1393 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1394
1395 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1396 as specified in IV3.2 spec.
1397 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1398
1399Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1400
1401 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1402 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1403 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1404 PENDING_FILL versions of instructions. Simplify.
1405 (X): New function.
1406 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1407 instructions.
1408 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1409 a signed value.
1410 (MTHI, MFHI): Disable code checking HI-LO.
1411
1412 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1413 global.
1414 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1415
1416Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1417
1418 * gencode.c (build_mips16_operands): Replace IPC with cia.
1419
1420 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1421 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1422 IPC to `cia'.
1423 (UndefinedResult): Replace function with macro/function
1424 combination.
1425 (sim_engine_run): Don't save PC in IPC.
1426
1427 * sim-main.h (IPC): Delete.
1428
1429
1430 * interp.c (signal_exception, store_word, load_word,
1431 address_translation, load_memory, store_memory, cache_op,
1432 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1433 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1434 current instruction address - cia - argument.
1435 (sim_read, sim_write): Call address_translation directly.
1436 (sim_engine_run): Rename variable vaddr to cia.
1437 (signal_exception): Pass cia to sim_monitor
1438
1439 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1440 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1441 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1442
1443 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1444 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1445 SIM_ASSERT.
1446
1447 * interp.c (signal_exception): Pass restart address to
1448 sim_engine_restart.
1449
1450 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1451 idecode.o): Add dependency.
1452
1453 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1454 Delete definitions
1455 (DELAY_SLOT): Update NIA not PC with branch address.
1456 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1457
1458 * mips.igen: Use CIA not PC in branch calculations.
1459 (illegal): Call SignalException.
1460 (BEQ, ADDIU): Fix assembler.
1461
1462Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * m16.igen (JALX): Was missing.
1465
1466 * configure.in (enable-sim-igen): New configuration option.
1467 * configure: Re-generate.
1468
1469 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1470
1471 * interp.c (load_memory, store_memory): Delete parameter RAW.
1472 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1473 bypassing {load,store}_memory.
1474
1475 * sim-main.h (ByteSwapMem): Delete definition.
1476
1477 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1478
1479 * interp.c (sim_do_command, sim_commands): Delete mips specific
1480 commands. Handled by module sim-options.
1481
1482 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1483 (WITH_MODULO_MEMORY): Define.
1484
1485 * interp.c (sim_info): Delete code printing memory size.
1486
1487 * interp.c (mips_size): Nee sim_size, delete function.
1488 (power2): Delete.
1489 (monitor, monitor_base, monitor_size): Delete global variables.
1490 (sim_open, sim_close): Delete code creating monitor and other
1491 memory regions. Use sim-memopts module, via sim_do_commandf, to
1492 manage memory regions.
1493 (load_memory, store_memory): Use sim-core for memory model.
1494
1495 * interp.c (address_translation): Delete all memory map code
1496 except line forcing 32 bit addresses.
1497
1498Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1499
1500 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1501 trace options.
1502
1503 * interp.c (logfh, logfile): Delete globals.
1504 (sim_open, sim_close): Delete code opening & closing log file.
1505 (mips_option_handler): Delete -l and -n options.
1506 (OPTION mips_options): Ditto.
1507
1508 * interp.c (OPTION mips_options): Rename option trace to dinero.
1509 (mips_option_handler): Update.
1510
1511Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 * interp.c (fetch_str): New function.
1514 (sim_monitor): Rewrite using sim_read & sim_write.
1515 (sim_open): Check magic number.
1516 (sim_open): Write monitor vectors into memory using sim_write.
1517 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1518 (sim_read, sim_write): Simplify - transfer data one byte at a
1519 time.
1520 (load_memory, store_memory): Clarify meaning of parameter RAW.
1521
1522 * sim-main.h (isHOST): Defete definition.
1523 (isTARGET): Mark as depreciated.
1524 (address_translation): Delete parameter HOST.
1525
1526 * interp.c (address_translation): Delete parameter HOST.
1527
1528Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1529
1530 * mips.igen:
1531
1532 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1533 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1534
1535Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1536
1537 * mips.igen: Add model filter field to records.
1538
1539Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1540
1541 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1542
1543 interp.c (sim_engine_run): Do not compile function sim_engine_run
1544 when WITH_IGEN == 1.
1545
1546 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1547 target architecture.
1548
1549 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1550 igen. Replace with configuration variables sim_igen_flags /
1551 sim_m16_flags.
1552
1553 * m16.igen: New file. Copy mips16 insns here.
1554 * mips.igen: From here.
1555
1556Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1557
1558 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1559 to top.
1560 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1561
1562Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1563
1564 * gencode.c (build_instruction): Follow sim_write's lead in using
1565 BigEndianMem instead of !ByteSwapMem.
1566
1567Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1568
1569 * configure.in (sim_gen): Dependent on target, select type of
1570 generator. Always select old style generator.
1571
1572 configure: Re-generate.
1573
1574 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1575 targets.
1576 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1577 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1578 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1579 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1580 SIM_@sim_gen@_*, set by autoconf.
1581
1582Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1583
1584 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1585
1586 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1587 CURRENT_FLOATING_POINT instead.
1588
1589 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1590 (address_translation): Raise exception InstructionFetch when
1591 translation fails and isINSTRUCTION.
1592
1593 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1594 sim_engine_run): Change type of of vaddr and paddr to
1595 address_word.
1596 (address_translation, prefetch, load_memory, store_memory,
1597 cache_op): Change type of vAddr and pAddr to address_word.
1598
1599 * gencode.c (build_instruction): Change type of vaddr and paddr to
1600 address_word.
1601
1602Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1603
1604 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1605 macro to obtain result of ALU op.
1606
1607Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1608
1609 * interp.c (sim_info): Call profile_print.
1610
1611Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1612
1613 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1614
1615 * sim-main.h (WITH_PROFILE): Do not define, defined in
1616 common/sim-config.h. Use sim-profile module.
1617 (simPROFILE): Delete defintion.
1618
1619 * interp.c (PROFILE): Delete definition.
1620 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1621 (sim_close): Delete code writing profile histogram.
1622 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1623 Delete.
1624 (sim_engine_run): Delete code profiling the PC.
1625
1626Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1627
1628 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1629
1630 * interp.c (sim_monitor): Make register pointers of type
1631 unsigned_word*.
1632
1633 * sim-main.h: Make registers of type unsigned_word not
1634 signed_word.
1635
1636Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1637
1638 * interp.c (sync_operation): Rename from SyncOperation, make
1639 global, add SD argument.
1640 (prefetch): Rename from Prefetch, make global, add SD argument.
1641 (decode_coproc): Make global.
1642
1643 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1644
1645 * gencode.c (build_instruction): Generate DecodeCoproc not
1646 decode_coproc calls.
1647
1648 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1649 (SizeFGR): Move to sim-main.h
1650 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1651 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1652 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1653 sim-main.h.
1654 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1655 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1656 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1657 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1658 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1659 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1660
1661 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1662 exception.
1663 (sim-alu.h): Include.
1664 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1665 (sim_cia): Typedef to instruction_address.
1666
1667Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1668
1669 * Makefile.in (interp.o): Rename generated file engine.c to
1670 oengine.c.
1671
1672 * interp.c: Update.
1673
1674Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1675
1676 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1677
1678Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1679
1680 * gencode.c (build_instruction): For "FPSQRT", output correct
1681 number of arguments to Recip.
1682
1683Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1684
1685 * Makefile.in (interp.o): Depends on sim-main.h
1686
1687 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1688
1689 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1690 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1691 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1692 STATE, DSSTATE): Define
1693 (GPR, FGRIDX, ..): Define.
1694
1695 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1696 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1697 (GPR, FGRIDX, ...): Delete macros.
1698
1699 * interp.c: Update names to match defines from sim-main.h
1700
1701Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1702
1703 * interp.c (sim_monitor): Add SD argument.
1704 (sim_warning): Delete. Replace calls with calls to
1705 sim_io_eprintf.
1706 (sim_error): Delete. Replace calls with sim_io_error.
1707 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1708 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1709 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1710 argument.
1711 (mips_size): Rename from sim_size. Add SD argument.
1712
1713 * interp.c (simulator): Delete global variable.
1714 (callback): Delete global variable.
1715 (mips_option_handler, sim_open, sim_write, sim_read,
1716 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1717 sim_size,sim_monitor): Use sim_io_* not callback->*.
1718 (sim_open): ZALLOC simulator struct.
1719 (PROFILE): Do not define.
1720
1721Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1722
1723 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1724 support.h with corresponding code.
1725
1726 * sim-main.h (word64, uword64), support.h: Move definition to
1727 sim-main.h.
1728 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1729
1730 * support.h: Delete
1731 * Makefile.in: Update dependencies
1732 * interp.c: Do not include.
1733
1734Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1735
1736 * interp.c (address_translation, load_memory, store_memory,
1737 cache_op): Rename to from AddressTranslation et.al., make global,
1738 add SD argument
1739
1740 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1741 CacheOp): Define.
1742
1743 * interp.c (SignalException): Rename to signal_exception, make
1744 global.
1745
1746 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1747
1748 * sim-main.h (SignalException, SignalExceptionInterrupt,
1749 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1750 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1751 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1752 Define.
1753
1754 * interp.c, support.h: Use.
1755
1756Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1757
1758 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1759 to value_fpr / store_fpr. Add SD argument.
1760 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1761 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1762
1763 * sim-main.h (ValueFPR, StoreFPR): Define.
1764
1765Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1766
1767 * interp.c (sim_engine_run): Check consistency between configure
1768 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1769 and HASFPU.
1770
1771 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1772 (mips_fpu): Configure WITH_FLOATING_POINT.
1773 (mips_endian): Configure WITH_TARGET_ENDIAN.
1774 * configure: Update.
1775
1776Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1777
1778 * configure: Regenerated to track ../common/aclocal.m4 changes.
1779
1780Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1781
1782 * configure: Regenerated.
1783
1784Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1785
1786 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1787
1788Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1789
1790 * gencode.c (print_igen_insn_models): Assume certain architectures
1791 include all mips* instructions.
1792 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1793 instruction.
1794
1795 * Makefile.in (tmp.igen): Add target. Generate igen input from
1796 gencode file.
1797
1798 * gencode.c (FEATURE_IGEN): Define.
1799 (main): Add --igen option. Generate output in igen format.
1800 (process_instructions): Format output according to igen option.
1801 (print_igen_insn_format): New function.
1802 (print_igen_insn_models): New function.
1803 (process_instructions): Only issue warnings and ignore
1804 instructions when no FEATURE_IGEN.
1805
1806Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1807
1808 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1809 MIPS targets.
1810
1811Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1812
1813 * configure: Regenerated to track ../common/aclocal.m4 changes.
1814
1815Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1816
1817 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1818 SIM_RESERVED_BITS): Delete, moved to common.
1819 (SIM_EXTRA_CFLAGS): Update.
1820
1821Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1822
1823 * configure.in: Configure non-strict memory alignment.
1824 * configure: Regenerated to track ../common/aclocal.m4 changes.
1825
1826Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1827
1828 * configure: Regenerated to track ../common/aclocal.m4 changes.
1829
1830Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1831
1832 * gencode.c (SDBBP,DERET): Added (3900) insns.
1833 (RFE): Turn on for 3900.
1834 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1835 (dsstate): Made global.
1836 (SUBTARGET_R3900): Added.
1837 (CANCELDELAYSLOT): New.
1838 (SignalException): Ignore SystemCall rather than ignore and
1839 terminate. Add DebugBreakPoint handling.
1840 (decode_coproc): New insns RFE, DERET; and new registers Debug
1841 and DEPC protected by SUBTARGET_R3900.
1842 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1843 bits explicitly.
1844 * Makefile.in,configure.in: Add mips subtarget option.
1845 * configure: Update.
1846
1847Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1848
1849 * gencode.c: Add r3900 (tx39).
1850
1851
1852Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1853
1854 * gencode.c (build_instruction): Don't need to subtract 4 for
1855 JALR, just 2.
1856
1857Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1858
1859 * interp.c: Correct some HASFPU problems.
1860
1861Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1862
1863 * configure: Regenerated to track ../common/aclocal.m4 changes.
1864
1865Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1866
1867 * interp.c (mips_options): Fix samples option short form, should
1868 be `x'.
1869
1870Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1871
1872 * interp.c (sim_info): Enable info code. Was just returning.
1873
1874Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1875
1876 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1877 MFC0.
1878
1879Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1880
1881 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1882 constants.
1883 (build_instruction): Ditto for LL.
1884
1885Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1886
1887 * configure: Regenerated to track ../common/aclocal.m4 changes.
1888
1889Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1890
1891 * configure: Regenerated to track ../common/aclocal.m4 changes.
1892 * config.in: Ditto.
1893
1894Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1895
1896 * interp.c (sim_open): Add call to sim_analyze_program, update
1897 call to sim_config.
1898
1899Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1900
1901 * interp.c (sim_kill): Delete.
1902 (sim_create_inferior): Add ABFD argument. Set PC from same.
1903 (sim_load): Move code initializing trap handlers from here.
1904 (sim_open): To here.
1905 (sim_load): Delete, use sim-hload.c.
1906
1907 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1908
1909Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1910
1911 * configure: Regenerated to track ../common/aclocal.m4 changes.
1912 * config.in: Ditto.
1913
1914Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1915
1916 * interp.c (sim_open): Add ABFD argument.
1917 (sim_load): Move call to sim_config from here.
1918 (sim_open): To here. Check return status.
1919
1920Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1921
1922 * gencode.c (build_instruction): Two arg MADD should
1923 not assign result to $0.
1924
1925Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1926
1927 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1928 * sim/mips/configure.in: Regenerate.
1929
1930Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1931
1932 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1933 signed8, unsigned8 et.al. types.
1934
1935 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1936 hosts when selecting subreg.
1937
1938Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1939
1940 * interp.c (sim_engine_run): Reset the ZERO register to zero
1941 regardless of FEATURE_WARN_ZERO.
1942 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1943
1944Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1945
1946 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1947 (SignalException): For BreakPoints ignore any mode bits and just
1948 save the PC.
1949 (SignalException): Always set the CAUSE register.
1950
1951Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1952
1953 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1954 exception has been taken.
1955
1956 * interp.c: Implement the ERET and mt/f sr instructions.
1957
1958Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1959
1960 * interp.c (SignalException): Don't bother restarting an
1961 interrupt.
1962
1963Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1964
1965 * interp.c (SignalException): Really take an interrupt.
1966 (interrupt_event): Only deliver interrupts when enabled.
1967
1968Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1969
1970 * interp.c (sim_info): Only print info when verbose.
1971 (sim_info) Use sim_io_printf for output.
1972
1973Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1974
1975 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1976 mips architectures.
1977
1978Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1979
1980 * interp.c (sim_do_command): Check for common commands if a
1981 simulator specific command fails.
1982
1983Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1984
1985 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1986 and simBE when DEBUG is defined.
1987
1988Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1989
1990 * interp.c (interrupt_event): New function. Pass exception event
1991 onto exception handler.
1992
1993 * configure.in: Check for stdlib.h.
1994 * configure: Regenerate.
1995
1996 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1997 variable declaration.
1998 (build_instruction): Initialize memval1.
1999 (build_instruction): Add UNUSED attribute to byte, bigend,
2000 reverse.
2001 (build_operands): Ditto.
2002
2003 * interp.c: Fix GCC warnings.
2004 (sim_get_quit_code): Delete.
2005
2006 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2007 * Makefile.in: Ditto.
2008 * configure: Re-generate.
2009
2010 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2011
2012Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2013
2014 * interp.c (mips_option_handler): New function parse argumes using
2015 sim-options.
2016 (myname): Replace with STATE_MY_NAME.
2017 (sim_open): Delete check for host endianness - performed by
2018 sim_config.
2019 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2020 (sim_open): Move much of the initialization from here.
2021 (sim_load): To here. After the image has been loaded and
2022 endianness set.
2023 (sim_open): Move ColdReset from here.
2024 (sim_create_inferior): To here.
2025 (sim_open): Make FP check less dependant on host endianness.
2026
2027 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2028 run.
2029 * interp.c (sim_set_callbacks): Delete.
2030
2031 * interp.c (membank, membank_base, membank_size): Replace with
2032 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2033 (sim_open): Remove call to callback->init. gdb/run do this.
2034
2035 * interp.c: Update
2036
2037 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2038
2039 * interp.c (big_endian_p): Delete, replaced by
2040 current_target_byte_order.
2041
2042Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2043
2044 * interp.c (host_read_long, host_read_word, host_swap_word,
2045 host_swap_long): Delete. Using common sim-endian.
2046 (sim_fetch_register, sim_store_register): Use H2T.
2047 (pipeline_ticks): Delete. Handled by sim-events.
2048 (sim_info): Update.
2049 (sim_engine_run): Update.
2050
2051Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2052
2053 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2054 reason from here.
2055 (SignalException): To here. Signal using sim_engine_halt.
2056 (sim_stop_reason): Delete, moved to common.
2057
2058Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2059
2060 * interp.c (sim_open): Add callback argument.
2061 (sim_set_callbacks): Delete SIM_DESC argument.
2062 (sim_size): Ditto.
2063
2064Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2065
2066 * Makefile.in (SIM_OBJS): Add common modules.
2067
2068 * interp.c (sim_set_callbacks): Also set SD callback.
2069 (set_endianness, xfer_*, swap_*): Delete.
2070 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2071 Change to functions using sim-endian macros.
2072 (control_c, sim_stop): Delete, use common version.
2073 (simulate): Convert into.
2074 (sim_engine_run): This function.
2075 (sim_resume): Delete.
2076
2077 * interp.c (simulation): New variable - the simulator object.
2078 (sim_kind): Delete global - merged into simulation.
2079 (sim_load): Cleanup. Move PC assignment from here.
2080 (sim_create_inferior): To here.
2081
2082 * sim-main.h: New file.
2083 * interp.c (sim-main.h): Include.
2084
2085Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2086
2087 * configure: Regenerated to track ../common/aclocal.m4 changes.
2088
2089Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2090
2091 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2092
2093Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2094
2095 * gencode.c (build_instruction): DIV instructions: check
2096 for division by zero and integer overflow before using
2097 host's division operation.
2098
2099Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2100
2101 * Makefile.in (SIM_OBJS): Add sim-load.o.
2102 * interp.c: #include bfd.h.
2103 (target_byte_order): Delete.
2104 (sim_kind, myname, big_endian_p): New static locals.
2105 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2106 after argument parsing. Recognize -E arg, set endianness accordingly.
2107 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2108 load file into simulator. Set PC from bfd.
2109 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2110 (set_endianness): Use big_endian_p instead of target_byte_order.
2111
2112Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2113
2114 * interp.c (sim_size): Delete prototype - conflicts with
2115 definition in remote-sim.h. Correct definition.
2116
2117Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2118
2119 * configure: Regenerated to track ../common/aclocal.m4 changes.
2120 * config.in: Ditto.
2121
2122Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2123
2124 * interp.c (sim_open): New arg `kind'.
2125
2126 * configure: Regenerated to track ../common/aclocal.m4 changes.
2127
2128Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2129
2130 * configure: Regenerated to track ../common/aclocal.m4 changes.
2131
2132Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2133
2134 * interp.c (sim_open): Set optind to 0 before calling getopt.
2135
2136Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2137
2138 * configure: Regenerated to track ../common/aclocal.m4 changes.
2139
2140Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2141
2142 * interp.c : Replace uses of pr_addr with pr_uword64
2143 where the bit length is always 64 independent of SIM_ADDR.
2144 (pr_uword64) : added.
2145
2146Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2147
2148 * configure: Re-generate.
2149
2150Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2151
2152 * configure: Regenerate to track ../common/aclocal.m4 changes.
2153
2154Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2155
2156 * interp.c (sim_open): New SIM_DESC result. Argument is now
2157 in argv form.
2158 (other sim_*): New SIM_DESC argument.
2159
2160Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2161
2162 * interp.c: Fix printing of addresses for non-64-bit targets.
2163 (pr_addr): Add function to print address based on size.
2164
2165Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2166
2167 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2168
2169Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2170
2171 * gencode.c (build_mips16_operands): Correct computation of base
2172 address for extended PC relative instruction.
2173
2174Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2175
2176 * interp.c (mips16_entry): Add support for floating point cases.
2177 (SignalException): Pass floating point cases to mips16_entry.
2178 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2179 registers.
2180 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2181 or fmt_word.
2182 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2183 and then set the state to fmt_uninterpreted.
2184 (COP_SW): Temporarily set the state to fmt_word while calling
2185 ValueFPR.
2186
2187Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2188
2189 * gencode.c (build_instruction): The high order may be set in the
2190 comparison flags at any ISA level, not just ISA 4.
2191
2192Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2193
2194 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2195 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2196 * configure.in: sinclude ../common/aclocal.m4.
2197 * configure: Regenerated.
2198
2199Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2200
2201 * configure: Rebuild after change to aclocal.m4.
2202
2203Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2204
2205 * configure configure.in Makefile.in: Update to new configure
2206 scheme which is more compatible with WinGDB builds.
2207 * configure.in: Improve comment on how to run autoconf.
2208 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2209 * Makefile.in: Use autoconf substitution to install common
2210 makefile fragment.
2211
2212Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2213
2214 * gencode.c (build_instruction): Use BigEndianCPU instead of
2215 ByteSwapMem.
2216
2217Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2218
2219 * interp.c (sim_monitor): Make output to stdout visible in
2220 wingdb's I/O log window.
2221
2222Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2223
2224 * support.h: Undo previous change to SIGTRAP
2225 and SIGQUIT values.
2226
2227Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2228
2229 * interp.c (store_word, load_word): New static functions.
2230 (mips16_entry): New static function.
2231 (SignalException): Look for mips16 entry and exit instructions.
2232 (simulate): Use the correct index when setting fpr_state after
2233 doing a pending move.
2234
2235Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2236
2237 * interp.c: Fix byte-swapping code throughout to work on
2238 both little- and big-endian hosts.
2239
2240Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2241
2242 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2243 with gdb/config/i386/xm-windows.h.
2244
2245Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2246
2247 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2248 that messes up arithmetic shifts.
2249
2250Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2251
2252 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2253 SIGTRAP and SIGQUIT for _WIN32.
2254
2255Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2256
2257 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2258 force a 64 bit multiplication.
2259 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2260 destination register is 0, since that is the default mips16 nop
2261 instruction.
2262
2263Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2264
2265 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2266 (build_endian_shift): Don't check proc64.
2267 (build_instruction): Always set memval to uword64. Cast op2 to
2268 uword64 when shifting it left in memory instructions. Always use
2269 the same code for stores--don't special case proc64.
2270
2271 * gencode.c (build_mips16_operands): Fix base PC value for PC
2272 relative operands.
2273 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2274 jal instruction.
2275 * interp.c (simJALDELAYSLOT): Define.
2276 (JALDELAYSLOT): Define.
2277 (INDELAYSLOT, INJALDELAYSLOT): Define.
2278 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2279
2280Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2281
2282 * interp.c (sim_open): add flush_cache as a PMON routine
2283 (sim_monitor): handle flush_cache by ignoring it
2284
2285Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2286
2287 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2288 BigEndianMem.
2289 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2290 (BigEndianMem): Rename to ByteSwapMem and change sense.
2291 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2292 BigEndianMem references to !ByteSwapMem.
2293 (set_endianness): New function, with prototype.
2294 (sim_open): Call set_endianness.
2295 (sim_info): Use simBE instead of BigEndianMem.
2296 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2297 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2298 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2299 ifdefs, keeping the prototype declaration.
2300 (swap_word): Rewrite correctly.
2301 (ColdReset): Delete references to CONFIG. Delete endianness related
2302 code; moved to set_endianness.
2303
2304Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2305
2306 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2307 * interp.c (CHECKHILO): Define away.
2308 (simSIGINT): New macro.
2309 (membank_size): Increase from 1MB to 2MB.
2310 (control_c): New function.
2311 (sim_resume): Rename parameter signal to signal_number. Add local
2312 variable prev. Call signal before and after simulate.
2313 (sim_stop_reason): Add simSIGINT support.
2314 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2315 functions always.
2316 (sim_warning): Delete call to SignalException. Do call printf_filtered
2317 if logfh is NULL.
2318 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2319 a call to sim_warning.
2320
2321Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2322
2323 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2324 16 bit instructions.
2325
2326Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2327
2328 Add support for mips16 (16 bit MIPS implementation):
2329 * gencode.c (inst_type): Add mips16 instruction encoding types.
2330 (GETDATASIZEINSN): Define.
2331 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2332 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2333 mtlo.
2334 (MIPS16_DECODE): New table, for mips16 instructions.
2335 (bitmap_val): New static function.
2336 (struct mips16_op): Define.
2337 (mips16_op_table): New table, for mips16 operands.
2338 (build_mips16_operands): New static function.
2339 (process_instructions): If PC is odd, decode a mips16
2340 instruction. Break out instruction handling into new
2341 build_instruction function.
2342 (build_instruction): New static function, broken out of
2343 process_instructions. Check modifiers rather than flags for SHIFT
2344 bit count and m[ft]{hi,lo} direction.
2345 (usage): Pass program name to fprintf.
2346 (main): Remove unused variable this_option_optind. Change
2347 ``*loptarg++'' to ``loptarg++''.
2348 (my_strtoul): Parenthesize && within ||.
2349 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2350 (simulate): If PC is odd, fetch a 16 bit instruction, and
2351 increment PC by 2 rather than 4.
2352 * configure.in: Add case for mips16*-*-*.
2353 * configure: Rebuild.
2354
2355Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2356
2357 * interp.c: Allow -t to enable tracing in standalone simulator.
2358 Fix garbage output in trace file and error messages.
2359
2360Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2361
2362 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2363 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2364 * configure.in: Simplify using macros in ../common/aclocal.m4.
2365 * configure: Regenerated.
2366 * tconfig.in: New file.
2367
2368Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2369
2370 * interp.c: Fix bugs in 64-bit port.
2371 Use ansi function declarations for msvc compiler.
2372 Initialize and test file pointer in trace code.
2373 Prevent duplicate definition of LAST_EMED_REGNUM.
2374
2375Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2376
2377 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2378
2379Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2380
2381 * interp.c (SignalException): Check for explicit terminating
2382 breakpoint value.
2383 * gencode.c: Pass instruction value through SignalException()
2384 calls for Trap, Breakpoint and Syscall.
2385
2386Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2387
2388 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2389 only used on those hosts that provide it.
2390 * configure.in: Add sqrt() to list of functions to be checked for.
2391 * config.in: Re-generated.
2392 * configure: Re-generated.
2393
2394Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2395
2396 * gencode.c (process_instructions): Call build_endian_shift when
2397 expanding STORE RIGHT, to fix swr.
2398 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2399 clear the high bits.
2400 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2401 Fix float to int conversions to produce signed values.
2402
2403Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2404
2405 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2406 (process_instructions): Correct handling of nor instruction.
2407 Correct shift count for 32 bit shift instructions. Correct sign
2408 extension for arithmetic shifts to not shift the number of bits in
2409 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2410 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2411 Fix madd.
2412 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2413 It's OK to have a mult follow a mult. What's not OK is to have a
2414 mult follow an mfhi.
2415 (Convert): Comment out incorrect rounding code.
2416
2417Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2418
2419 * interp.c (sim_monitor): Improved monitor printf
2420 simulation. Tidied up simulator warnings, and added "--log" option
2421 for directing warning message output.
2422 * gencode.c: Use sim_warning() rather than WARNING macro.
2423
2424Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2425
2426 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2427 getopt1.o, rather than on gencode.c. Link objects together.
2428 Don't link against -liberty.
2429 (gencode.o, getopt.o, getopt1.o): New targets.
2430 * gencode.c: Include <ctype.h> and "ansidecl.h".
2431 (AND): Undefine after including "ansidecl.h".
2432 (ULONG_MAX): Define if not defined.
2433 (OP_*): Don't define macros; now defined in opcode/mips.h.
2434 (main): Call my_strtoul rather than strtoul.
2435 (my_strtoul): New static function.
2436
2437Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2438
2439 * gencode.c (process_instructions): Generate word64 and uword64
2440 instead of `long long' and `unsigned long long' data types.
2441 * interp.c: #include sysdep.h to get signals, and define default
2442 for SIGBUS.
2443 * (Convert): Work around for Visual-C++ compiler bug with type
2444 conversion.
2445 * support.h: Make things compile under Visual-C++ by using
2446 __int64 instead of `long long'. Change many refs to long long
2447 into word64/uword64 typedefs.
2448
2449Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2450
2451 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2452 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2453 (docdir): Removed.
2454 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2455 (AC_PROG_INSTALL): Added.
2456 (AC_PROG_CC): Moved to before configure.host call.
2457 * configure: Rebuilt.
2458
2459Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2460
2461 * configure.in: Define @SIMCONF@ depending on mips target.
2462 * configure: Rebuild.
2463 * Makefile.in (run): Add @SIMCONF@ to control simulator
2464 construction.
2465 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2466 * interp.c: Remove some debugging, provide more detailed error
2467 messages, update memory accesses to use LOADDRMASK.
2468
2469Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2470
2471 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2472 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2473 stamp-h.
2474 * configure: Rebuild.
2475 * config.in: New file, generated by autoheader.
2476 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2477 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2478 HAVE_ANINT and HAVE_AINT, as appropriate.
2479 * Makefile.in (run): Use @LIBS@ rather than -lm.
2480 (interp.o): Depend upon config.h.
2481 (Makefile): Just rebuild Makefile.
2482 (clean): Remove stamp-h.
2483 (mostlyclean): Make the same as clean, not as distclean.
2484 (config.h, stamp-h): New targets.
2485
2486Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2487
2488 * interp.c (ColdReset): Fix boolean test. Make all simulator
2489 globals static.
2490
2491Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2492
2493 * interp.c (xfer_direct_word, xfer_direct_long,
2494 swap_direct_word, swap_direct_long, xfer_big_word,
2495 xfer_big_long, xfer_little_word, xfer_little_long,
2496 swap_word,swap_long): Added.
2497 * interp.c (ColdReset): Provide function indirection to
2498 host<->simulated_target transfer routines.
2499 * interp.c (sim_store_register, sim_fetch_register): Updated to
2500 make use of indirected transfer routines.
2501
2502Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2503
2504 * gencode.c (process_instructions): Ensure FP ABS instruction
2505 recognised.
2506 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2507 system call support.
2508
2509Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2510
2511 * interp.c (sim_do_command): Complain if callback structure not
2512 initialised.
2513
2514Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2515
2516 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2517 support for Sun hosts.
2518 * Makefile.in (gencode): Ensure the host compiler and libraries
2519 used for cross-hosted build.
2520
2521Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2522
2523 * interp.c, gencode.c: Some more (TODO) tidying.
2524
2525Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2526
2527 * gencode.c, interp.c: Replaced explicit long long references with
2528 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2529 * support.h (SET64LO, SET64HI): Macros added.
2530
2531Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2532
2533 * configure: Regenerate with autoconf 2.7.
2534
2535Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2536
2537 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2538 * support.h: Remove superfluous "1" from #if.
2539 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2540
2541Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2542
2543 * interp.c (StoreFPR): Control UndefinedResult() call on
2544 WARN_RESULT manifest.
2545
2546Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2547
2548 * gencode.c: Tidied instruction decoding, and added FP instruction
2549 support.
2550
2551 * interp.c: Added dineroIII, and BSD profiling support. Also
2552 run-time FP handling.
2553
2554Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2555
2556 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2557 gencode.c, interp.c, support.h: created.
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