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* MAINTAINERS: Reflect that multi-arch is enabled for VAX.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
e1015982
AC		 12002-04-20 Andrew Cagney <ac131313@redhat.com>
2
3 * interp.c (sim_open): Revert previous change.
4
b882a66b
AO		 52002-04-18 Alexandre Oliva <aoliva@redhat.com>
6
7 * interp.c (sim_open): Disable chunk of code that wrote code in
8 vector table entries.
9
c429b7dd
CD		 102002-03-19 Chris Demetriou <cgd@broadcom.com>
11
12 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
13 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
14 unused definitions.
15
37d146fa
CD		 162002-03-19 Chris Demetriou <cgd@broadcom.com>
17
18 * cp1.c: Fix many formatting issues.
19
07892c0b
CD		 202002-03-19 Chris G. Demetriou <cgd@broadcom.com>
21
22 * cp1.c (fpu_format_name): New function to replace...
23 (DOFMT): This. Delete, and update all callers.
24 (fpu_rounding_mode_name): New function to replace...
25 (RMMODE): This. Delete, and update all callers.
26
487f79b7
CD		 272002-03-19 Chris G. Demetriou <cgd@broadcom.com>
28
29 * interp.c: Move FPU support routines from here to...
30 * cp1.c: Here. New file.
31 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
32 (cp1.o): New target.
33
1e799e28
CD		 342002-03-12 Chris Demetriou <cgd@broadcom.com>
35
36 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
37 * mips.igen (mips32, mips64): New models, add to all instructions
38 and functions as appropriate.
39 (loadstore_ea, check_u64): New variant for model mips64.
40 (check_fmt_p): New variant for models mipsV and mips64, remove
41 mipsV model marking fro other variant.
42 (SLL) Rename to...
43 (SLLa) this.
44 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
45 for mips32 and mips64.
46 (DCLO, DCLZ): New instructions for mips64.
47
82f728db
CD		 482002-03-07 Chris Demetriou <cgd@broadcom.com>
49
50 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
51 immediate or code as a hex value with the "%#lx" format.
52 (ANDI): Likewise, and fix printed instruction name.
53
b96e7ef1
CD		 542002-03-05 Chris Demetriou <cgd@broadcom.com>
55
56 * sim-main.h (UndefinedResult, Unpredictable): New macros
57 which currently do nothing.
58
d35d4f70
CD		 592002-03-05 Chris Demetriou <cgd@broadcom.com>
60
61 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
62 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
63 (status_CU3): New definitions.
64
65 * sim-main.h (ExceptionCause): Add new values for MIPS32
66 and MIPS64: MDMX, MCheck, CacheErr. Update comments
67 for DebugBreakPoint and NMIReset to note their status in
68 MIPS32 and MIPS64.
69 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
70 (SignalExceptionCacheErr): New exception macros.
71
3ad6f714
CD		 722002-03-05 Chris Demetriou <cgd@broadcom.com>
73
74 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
75 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
76 is always enabled.
77 (SignalExceptionCoProcessorUnusable): Take as argument the
78 unusable coprocessor number.
79
86b77b47
CD		 802002-03-05 Chris Demetriou <cgd@broadcom.com>
81
82 * mips.igen: Fix formatting of all SignalException calls.
83
97a88e93 842002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 85
86 * sim-main.h (SIGNEXTEND): Remove.
87
97a88e93 882002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 89
90 * mips.igen: Remove gencode comment from top of file, fix
91 spelling in another comment.
92
97a88e93 932002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 94
95 * mips.igen (check_fmt, check_fmt_p): New functions to check
96 whether specific floating point formats are usable.
97 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
98 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
99 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
100 Use the new functions.
101 (do_c_cond_fmt): Remove format checks...
102 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
103
97a88e93 1042002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 105
106 * mips.igen: Fix formatting of check_fpu calls.
107
41774c9d
CD		 1082002-03-03 Chris Demetriou <cgd@broadcom.com>
109
110 * mips.igen (FLOOR.L.fmt): Store correct destination register.
111
4a0bd876
CD		 1122002-03-03 Chris Demetriou <cgd@broadcom.com>
113
114 * mips.igen: Remove whitespace at end of lines.
115
09297648
CD		 1162002-03-02 Chris Demetriou <cgd@broadcom.com>
117
118 * mips.igen (loadstore_ea): New function to do effective
119 address calculations.
120 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
121 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
122 CACHE): Use loadstore_ea to do effective address computations.
123
043b7057
CD		 1242002-03-02 Chris Demetriou <cgd@broadcom.com>
125
126 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
127 * mips.igen (LL, CxC1, MxC1): Likewise.
128
c1e8ada4
CD		 1292002-03-02 Chris Demetriou <cgd@broadcom.com>
130
131 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
132 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
133 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
134 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
135 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
136 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
137 Don't split opcode fields by hand, use the opcode field values
138 provided by igen.
139
3e1dca16
CD		 1402002-03-01 Chris Demetriou <cgd@broadcom.com>
141
142 * mips.igen (do_divu): Fix spacing.
143
144 * mips.igen (do_dsllv): Move to be right before DSLLV,
145 to match the rest of the do_<shift> functions.
146
fff8d27d
CD		 1472002-03-01 Chris Demetriou <cgd@broadcom.com>
148
149 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
150 DSRL32, do_dsrlv): Trace inputs and results.
151
0d3e762b
CD		 1522002-03-01 Chris Demetriou <cgd@broadcom.com>
153
154 * mips.igen (CACHE): Provide instruction-printing string.
155
156 * interp.c (signal_exception): Comment tokens after #endif.
157
eb5fcf93
CD		 1582002-02-28 Chris Demetriou <cgd@broadcom.com>
159
160 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
161 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
162 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
163 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
164 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
165 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
166 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
167 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
168
bb22bd7d
CD		 1692002-02-28 Chris Demetriou <cgd@broadcom.com>
170
171 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
172 instruction-printing string.
173 (LWU): Use '64' as the filter flag.
174
91a177cf
CD		 1752002-02-28 Chris Demetriou <cgd@broadcom.com>
176
177 * mips.igen (SDXC1): Fix instruction-printing string.
178
387f484a
CD		 1792002-02-28 Chris Demetriou <cgd@broadcom.com>
180
181 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
182 filter flags "32,f".
183
3d81f391
CD		 1842002-02-27 Chris Demetriou <cgd@broadcom.com>
185
186 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
187 as the filter flag.
188
af5107af
CD		 1892002-02-27 Chris Demetriou <cgd@broadcom.com>
190
191 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
192 add a comma) so that it more closely match the MIPS ISA
193 documentation opcode partitioning.
194 (PREF): Put useful names on opcode fields, and include
195 instruction-printing string.
196
ca971540
CD		 1972002-02-27 Chris Demetriou <cgd@broadcom.com>
198
199 * mips.igen (check_u64): New function which in the future will
200 check whether 64-bit instructions are usable and signal an
201 exception if not. Currently a no-op.
202 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
203 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
204 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
205 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
206
207 * mips.igen (check_fpu): New function which in the future will
208 check whether FPU instructions are usable and signal an exception
209 if not. Currently a no-op.
210 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
211 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
212 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
213 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
214 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
215 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
216 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
217 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
218
1c47a468
CD		 2192002-02-27 Chris Demetriou <cgd@broadcom.com>
220
221 * mips.igen (do_load_left, do_load_right): Move to be immediately
222 following do_load.
223 (do_store_left, do_store_right): Move to be immediately following
224 do_store.
225
603a98e7
CD		 2262002-02-27 Chris Demetriou <cgd@broadcom.com>
227
228 * mips.igen (mipsV): New model name. Also, add it to
229 all instructions and functions where it is appropriate.
230
c5d00cc7
CD		 2312002-02-18 Chris Demetriou <cgd@broadcom.com>
232
233 * mips.igen: For all functions and instructions, list model
234 names that support that instruction one per line.
235
074e9cb8
CD		 2362002-02-11 Chris Demetriou <cgd@broadcom.com>
237
238 * mips.igen: Add some additional comments about supported
239 models, and about which instructions go where.
240 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
241 order as is used in the rest of the file.
242
9805e229
CD		 2432002-02-11 Chris Demetriou <cgd@broadcom.com>
244
245 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
246 indicating that ALU32_END or ALU64_END are there to check
247 for overflow.
248 (DADD): Likewise, but also remove previous comment about
249 overflow checking.
250
f701dad2
CD		 2512002-02-10 Chris Demetriou <cgd@broadcom.com>
252
253 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
254 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
255 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
256 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
257 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
258 fields (i.e., add and move commas) so that they more closely
259 match the MIPS ISA documentation opcode partitioning.
260
2612002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 262
263 * mips.igen (ADDI): Print immediate value.
264 (BREAK): Print code.
265 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
266 (SLL): Print "nop" specially, and don't run the code
267 that does the shift for the "nop" case.
268
9e52972e
FF		 2692001-11-17 Fred Fish <fnf@redhat.com>
270
271 * sim-main.h (float_operation): Move enum declaration outside
272 of _sim_cpu struct declaration.
273
c0efbca4
JB		 2742001-04-12 Jim Blandy <jimb@redhat.com>
275
276 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
277 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
278 set of the FCSR.
279 * sim-main.h (COCIDX): Remove definition; this isn't supported by
280 PENDING_FILL, and you can get the intended effect gracefully by
281 calling PENDING_SCHED directly.
282
fb891446
BE		 2832001-02-23 Ben Elliston <bje@redhat.com>
284
285 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
286 already defined elsewhere.
287
8030f857
BE		 2882001-02-19 Ben Elliston <bje@redhat.com>
289
290 * sim-main.h (sim_monitor): Return an int.
291 * interp.c (sim_monitor): Add return values.
292 (signal_exception): Handle error conditions from sim_monitor.
293
56b48a7a
CD		 2942001-02-08 Ben Elliston <bje@redhat.com>
295
296 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
297 (store_memory): Likewise, pass cia to sim_core_write*.
298
d3ee60d9
FCE		 2992000-10-19 Frank Ch. Eigler <fche@redhat.com>
300
301 On advice from Chris G. Demetriou <cgd@sibyte.com>:
302 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
303
071da002
AC		 304Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
305
306 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
307 * Makefile.in: Don't delete *.igen when cleaning directory.
308
a28c02cd
AC		 309Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
310
311 * m16.igen (break): Call SignalException not sim_engine_halt.
312
80ee11fa
AC		 313Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
314
315 From Jason Eckhardt:
316 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
317
673388c0
AC		 318Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
319
320 * mips.igen (MxC1, DMxC1): Fix printf formatting.
321
4c0deff4
NC		 3222000-05-24 Michael Hayes <mhayes@cygnus.com>
323
324 * mips.igen (do_dmultx): Fix typo.
325
eb2d80b4
AC		 326Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
327
328 * configure: Regenerated to track ../common/aclocal.m4 changes.
329
dd37a34b
AC		 330Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
331
332 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
333
4c0deff4
NC		 3342000-04-12 Frank Ch. Eigler <fche@redhat.com>
335
336 * sim-main.h (GPR_CLEAR): Define macro.
337
e30db738
AC		 338Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
339
340 * interp.c (decode_coproc): Output long using %lx and not %s.
341
cb7450ea
FCE		 3422000-03-21 Frank Ch. Eigler <fche@redhat.com>
343
344 * interp.c (sim_open): Sort & extend dummy memory regions for
345 --board=jmr3904 for eCos.
346
a3027dd7
FCE		 3472000-03-02 Frank Ch. Eigler <fche@redhat.com>
348
349 * configure: Regenerated.
350
351Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
352
353 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
354 calls, conditional on the simulator being in verbose mode.
355
dfcd3bfb
JM		 356Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
357
358 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
359 cache don't get ReservedInstruction traps.
360
c2d11a7d
JM		 3611999-11-29 Mark Salter <msalter@cygnus.com>
362
363 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
364 to clear status bits in sdisr register. This is how the hardware works.
365
366 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
367 being used by cygmon.
368
4ce44c66
JM		 3691999-11-11 Andrew Haley <aph@cygnus.com>
370
371 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
372 instructions.
373
cff3e48b
JM		 374Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
375
376 * mips.igen (MULT): Correct previous mis-applied patch.
377
d4f3574e
SS		 378Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
379
380 * mips.igen (delayslot32): Handle sequence like
381 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
382 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
383 (MULT): Actually pass the third register...
384
3851999-09-03 Mark Salter <msalter@cygnus.com>
386
387 * interp.c (sim_open): Added more memory aliases for additional
388 hardware being touched by cygmon on jmr3904 board.
389
390Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
391
392 * configure: Regenerated to track ../common/aclocal.m4 changes.
393
a0b3c4fd
JM		 394Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
395
396 * interp.c (sim_store_register): Handle case where client - GDB -
397 specifies that a 4 byte register is 8 bytes in size.
398 (sim_fetch_register): Ditto.
399
adf40b2e
JM		 4001999-07-14 Frank Ch. Eigler <fche@cygnus.com>
401
402 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
403 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
404 (idt_monitor_base): Base address for IDT monitor traps.
405 (pmon_monitor_base): Ditto for PMON.
406 (lsipmon_monitor_base): Ditto for LSI PMON.
407 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
408 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
409 (sim_firmware_command): New function.
410 (mips_option_handler): Call it for OPTION_FIRMWARE.
411 (sim_open): Allocate memory for idt_monitor region. If "--board"
412 option was given, add no monitor by default. Add BREAK hooks only if
413 monitors are also there.
414
43e526b9
JM		 415Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
416
417 * interp.c (sim_monitor): Flush output before reading input.
418
419Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
420
421 * tconfig.in (SIM_HANDLES_LMA): Always define.
422
423Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
424
425 From Mark Salter <msalter@cygnus.com>:
426 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
427 (sim_open): Add setup for BSP board.
428
9846de1b
JM		 429Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
430
431 * mips.igen (MULT, MULTU): Add syntax for two operand version.
432 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
433 them as unimplemented.
434
cd0fc7c3
SS		 4351999-05-08 Felix Lee <flee@cygnus.com>
436
437 * configure: Regenerated to track ../common/aclocal.m4 changes.
438
7a292a7a
SS		 4391999-04-21 Frank Ch. Eigler <fche@cygnus.com>
440
441 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
442
443Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
444
445 * configure.in: Any mips64vr5*-*-* target should have
446 -DTARGET_ENABLE_FR=1.
447 (default_endian): Any mips64vr*el-*-* target should default to
448 LITTLE_ENDIAN.
449 * configure: Re-generate.
450
4511999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
452
453 * mips.igen (ldl): Extend from _16_, not 32.
454
455Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
456
457 * interp.c (sim_store_register): Force registers written to by GDB
458 into an un-interpreted state.
459
c906108c
SS		 4601999-02-05 Frank Ch. Eigler <fche@cygnus.com>
461
462 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
463 CPU, start periodic background I/O polls.
464 (tx3904sio_poll): New function: periodic I/O poller.
465
4661998-12-30 Frank Ch. Eigler <fche@cygnus.com>
467
468 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
469
470Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
471
472 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
473 case statement.
474
4751998-12-29 Frank Ch. Eigler <fche@cygnus.com>
476
477 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
478 (load_word): Call SIM_CORE_SIGNAL hook on error.
479 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
480 starting. For exception dispatching, pass PC instead of NULL_CIA.
481 (decode_coproc): Use COP0_BADVADDR to store faulting address.
482 * sim-main.h (COP0_BADVADDR): Define.
483 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
484 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
485 (_sim_cpu): Add exc_* fields to store register value snapshots.
486 * mips.igen (*): Replace memory-related SignalException* calls
487 with references to SIM_CORE_SIGNAL hook.
488
489 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
490 fix.
491 * sim-main.c (*): Minor warning cleanups.
492
4931998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
494
495 * m16.igen (DADDIU5): Correct type-o.
496
497Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
498
499 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
500 variables.
501
502Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
503
504 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
505 to include path.
506 (interp.o): Add dependency on itable.h
507 (oengine.c, gencode): Delete remaining references.
508 (BUILT_SRC_FROM_GEN): Clean up.
509
5101998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
511
512 * vr4run.c: New.
513 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
514 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
515 tmp-run-hack) : New.
516 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
517 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
518 Drop the "64" qualifier to get the HACK generator working.
519 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
520 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
521 qualifier to get the hack generator working.
522 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
523 (DSLL): Use do_dsll.
524 (DSLLV): Use do_dsllv.
525 (DSRA): Use do_dsra.
526 (DSRL): Use do_dsrl.
527 (DSRLV): Use do_dsrlv.
528 (BC1): Move *vr4100 to get the HACK generator working.
529 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
530 get the HACK generator working.
531 (MACC) Rename to get the HACK generator working.
532 (DMACC,MACCS,DMACCS): Add the 64.
533
5341998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
535
536 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
537 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
538
5391998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
540
541 * mips/interp.c (DEBUG): Cleanups.
542
5431998-12-10 Frank Ch. Eigler <fche@cygnus.com>
544
545 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
546 (tx3904sio_tickle): fflush after a stdout character output.
547
5481998-12-03 Frank Ch. Eigler <fche@cygnus.com>
549
550 * interp.c (sim_close): Uninstall modules.
551
552Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
553
554 * sim-main.h, interp.c (sim_monitor): Change to global
555 function.
556
557Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
558
559 * configure.in (vr4100): Only include vr4100 instructions in
560 simulator.
561 * configure: Re-generate.
562 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
563
564Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
565
566 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
567 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
568 true alternative.
569
570 * configure.in (sim_default_gen, sim_use_gen): Replace with
571 sim_gen.
572 (--enable-sim-igen): Delete config option. Always using IGEN.
573 * configure: Re-generate.
574
575 * Makefile.in (gencode): Kill, kill, kill.
576 * gencode.c: Ditto.
577
578Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
579
580 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
581 bit mips16 igen simulator.
582 * configure: Re-generate.
583
584 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
585 as part of vr4100 ISA.
586 * vr.igen: Mark all instructions as 64 bit only.
587
588Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
589
590 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
591 Pacify GCC.
592
593Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
594
595 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
596 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
597 * configure: Re-generate.
598
599 * m16.igen (BREAK): Define breakpoint instruction.
600 (JALX32): Mark instruction as mips16 and not r3900.
601 * mips.igen (C.cond.fmt): Fix typo in instruction format.
602
603 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
604
605Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
606
607 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
608 insn as a debug breakpoint.
609
610 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
611 pending.slot_size.
612 (PENDING_SCHED): Clean up trace statement.
613 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
614 (PENDING_FILL): Delay write by only one cycle.
615 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
616
617 * sim-main.c (pending_tick): Clean up trace statements. Add trace
618 of pending writes.
619 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
620 32 & 64.
621 (pending_tick): Move incrementing of index to FOR statement.
622 (pending_tick): Only update PENDING_OUT after a write has occured.
623
624 * configure.in: Add explicit mips-lsi-* target. Use gencode to
625 build simulator.
626 * configure: Re-generate.
627
628 * interp.c (sim_engine_run OLD): Delete explicit call to
629 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
630
631Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
632
633 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
634 interrupt level number to match changed SignalExceptionInterrupt
635 macro.
636
637Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
638
639 * interp.c: #include "itable.h" if WITH_IGEN.
640 (get_insn_name): New function.
641 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
642 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
643
644Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
645
646 * configure: Rebuilt to inhale new common/aclocal.m4.
647
648Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
649
650 * dv-tx3904sio.c: Include sim-assert.h.
651
652Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
653
654 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
655 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
656 Reorganize target-specific sim-hardware checks.
657 * configure: rebuilt.
658 * interp.c (sim_open): For tx39 target boards, set
659 OPERATING_ENVIRONMENT, add tx3904sio devices.
660 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
661 ROM executables. Install dv-sockser into sim-modules list.
662
663 * dv-tx3904irc.c: Compiler warning clean-up.
664 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
665 frequent hw-trace messages.
666
667Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
668
669 * vr.igen (MulAcc): Identify as a vr4100 specific function.
670
671Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
672
673 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
674
675 * vr.igen: New file.
676 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
677 * mips.igen: Define vr4100 model. Include vr.igen.
678Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
679
680 * mips.igen (check_mf_hilo): Correct check.
681
682Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
683
684 * sim-main.h (interrupt_event): Add prototype.
685
686 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
687 register_ptr, register_value.
688 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
689
690 * sim-main.h (tracefh): Make extern.
691
692Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
693
694 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
695 Reduce unnecessarily high timer event frequency.
696 * dv-tx3904cpu.c: Ditto for interrupt event.
697
698Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
699
700 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
701 to allay warnings.
702 (interrupt_event): Made non-static.
703
704 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
705 interchange of configuration values for external vs. internal
706 clock dividers.
707
708Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
709
710 * mips.igen (BREAK): Moved code to here for
711 simulator-reserved break instructions.
712 * gencode.c (build_instruction): Ditto.
713 * interp.c (signal_exception): Code moved from here. Non-
714 reserved instructions now use exception vector, rather
715 than halting sim.
716 * sim-main.h: Moved magic constants to here.
717
718Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
719
720 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
721 register upon non-zero interrupt event level, clear upon zero
722 event value.
723 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
724 by passing zero event value.
725 (*_io_{read,write}_buffer): Endianness fixes.
726 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
727 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
728
729 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
730 serial I/O and timer module at base address 0xFFFF0000.
731
732Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
733
734 * mips.igen (SWC1) : Correct the handling of ReverseEndian
735 and BigEndianCPU.
736
737Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
738
739 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
740 parts.
741 * configure: Update.
742
743Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
744
745 * dv-tx3904tmr.c: New file - implements tx3904 timer.
746 * dv-tx3904{irc,cpu}.c: Mild reformatting.
747 * configure.in: Include tx3904tmr in hw_device list.
748 * configure: Rebuilt.
749 * interp.c (sim_open): Instantiate three timer instances.
750 Fix address typo of tx3904irc instance.
751
752Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
753
754 * interp.c (signal_exception): SystemCall exception now uses
755 the exception vector.
756
757Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
758
759 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
760 to allay warnings.
761
762Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
763
764 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
765
766Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
767
768 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
769
770 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
771 sim-main.h. Declare a struct hw_descriptor instead of struct
772 hw_device_descriptor.
773
774Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
775
776 * mips.igen (do_store_left, do_load_left): Compute nr of left and
777 right bits and then re-align left hand bytes to correct byte
778 lanes. Fix incorrect computation in do_store_left when loading
779 bytes from second word.
780
781Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
782
783 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
784 * interp.c (sim_open): Only create a device tree when HW is
785 enabled.
786
787 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
788 * interp.c (signal_exception): Ditto.
789
790Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
791
792 * gencode.c: Mark BEGEZALL as LIKELY.
793
794Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
795
796 * sim-main.h (ALU32_END): Sign extend 32 bit results.
797 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
798
799Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
800
801 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
802 modules. Recognize TX39 target with "mips*tx39" pattern.
803 * configure: Rebuilt.
804 * sim-main.h (*): Added many macros defining bits in
805 TX39 control registers.
806 (SignalInterrupt): Send actual PC instead of NULL.
807 (SignalNMIReset): New exception type.
808 * interp.c (board): New variable for future use to identify
809 a particular board being simulated.
810 (mips_option_handler,mips_options): Added "--board" option.
811 (interrupt_event): Send actual PC.
812 (sim_open): Make memory layout conditional on board setting.
813 (signal_exception): Initial implementation of hardware interrupt
814 handling. Accept another break instruction variant for simulator
815 exit.
816 (decode_coproc): Implement RFE instruction for TX39.
817 (mips.igen): Decode RFE instruction as such.
818 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
819 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
820 bbegin to implement memory map.
821 * dv-tx3904cpu.c: New file.
822 * dv-tx3904irc.c: New file.
823
824Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
825
826 * mips.igen (check_mt_hilo): Create a separate r3900 version.
827
828Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
829
830 * tx.igen (madd,maddu): Replace calls to check_op_hilo
831 with calls to check_div_hilo.
832
833Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
834
835 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
836 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
837 Add special r3900 version of do_mult_hilo.
838 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
839 with calls to check_mult_hilo.
840 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
841 with calls to check_div_hilo.
842
843Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
844
845 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
846 Document a replacement.
847
848Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
849
850 * interp.c (sim_monitor): Make mon_printf work.
851
852Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
853
854 * sim-main.h (INSN_NAME): New arg `cpu'.
855
856Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
857
858 * configure: Regenerated to track ../common/aclocal.m4 changes.
859
860Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
861
862 * configure: Regenerated to track ../common/aclocal.m4 changes.
863 * config.in: Ditto.
864
865Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
866
867 * acconfig.h: New file.
868 * configure.in: Reverted change of Apr 24; use sinclude again.
869
870Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
871
872 * configure: Regenerated to track ../common/aclocal.m4 changes.
873 * config.in: Ditto.
874
875Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
876
877 * configure.in: Don't call sinclude.
878
879Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
880
881 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
882
883Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
884
885 * mips.igen (ERET): Implement.
886
887 * interp.c (decode_coproc): Return sign-extended EPC.
888
889 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
890
891 * interp.c (signal_exception): Do not ignore Trap.
892 (signal_exception): On TRAP, restart at exception address.
893 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
894 (signal_exception): Update.
895 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
896 so that TRAP instructions are caught.
897
898Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
899
900 * sim-main.h (struct hilo_access, struct hilo_history): Define,
901 contains HI/LO access history.
902 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
903 (HIACCESS, LOACCESS): Delete, replace with
904 (HIHISTORY, LOHISTORY): New macros.
905 (CHECKHILO): Delete all, moved to mips.igen
906
907 * gencode.c (build_instruction): Do not generate checks for
908 correct HI/LO register usage.
909
910 * interp.c (old_engine_run): Delete checks for correct HI/LO
911 register usage.
912
913 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
914 check_mf_cycles): New functions.
915 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
916 do_divu, domultx, do_mult, do_multu): Use.
917
918 * tx.igen ("madd", "maddu"): Use.
919
920Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
921
922 * mips.igen (DSRAV): Use function do_dsrav.
923 (SRAV): Use new function do_srav.
924
925 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
926 (B): Sign extend 11 bit immediate.
927 (EXT-B*): Shift 16 bit immediate left by 1.
928 (ADDIU*): Don't sign extend immediate value.
929
930Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
931
932 * m16run.c (sim_engine_run): Restore CIA after handling an event.
933
934 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
935 functions.
936
937 * mips.igen (delayslot32, nullify_next_insn): New functions.
938 (m16.igen): Always include.
939 (do_*): Add more tracing.
940
941 * m16.igen (delayslot16): Add NIA argument, could be called by a
942 32 bit MIPS16 instruction.
943
944 * interp.c (ifetch16): Move function from here.
945 * sim-main.c (ifetch16): To here.
946
947 * sim-main.c (ifetch16, ifetch32): Update to match current
948 implementations of LH, LW.
949 (signal_exception): Don't print out incorrect hex value of illegal
950 instruction.
951
952Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
953
954 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
955 instruction.
956
957 * m16.igen: Implement MIPS16 instructions.
958
959 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
960 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
961 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
962 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
963 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
964 bodies of corresponding code from 32 bit insn to these. Also used
965 by MIPS16 versions of functions.
966
967 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
968 (IMEM16): Drop NR argument from macro.
969
970Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
971
972 * Makefile.in (SIM_OBJS): Add sim-main.o.
973
974 * sim-main.h (address_translation, load_memory, store_memory,
975 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
976 as INLINE_SIM_MAIN.
977 (pr_addr, pr_uword64): Declare.
978 (sim-main.c): Include when H_REVEALS_MODULE_P.
979
980 * interp.c (address_translation, load_memory, store_memory,
981 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
982 from here.
983 * sim-main.c: To here. Fix compilation problems.
984
985 * configure.in: Enable inlining.
986 * configure: Re-config.
987
988Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
989
990 * configure: Regenerated to track ../common/aclocal.m4 changes.
991
992Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
993
994 * mips.igen: Include tx.igen.
995 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
996 * tx.igen: New file, contains MADD and MADDU.
997
998 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
999 the hardwired constant `7'.
1000 (store_memory): Ditto.
1001 (LOADDRMASK): Move definition to sim-main.h.
1002
1003 mips.igen (MTC0): Enable for r3900.
1004 (ADDU): Add trace.
1005
1006 mips.igen (do_load_byte): Delete.
1007 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1008 do_store_right): New functions.
1009 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1010
1011 configure.in: Let the tx39 use igen again.
1012 configure: Update.
1013
1014Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1015
1016 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1017 not an address sized quantity. Return zero for cache sizes.
1018
1019Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1020
1021 * mips.igen (r3900): r3900 does not support 64 bit integer
1022 operations.
1023
1024Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1025
1026 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1027 than igen one.
1028 * configure : Rebuild.
1029
1030Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1031
1032 * configure: Regenerated to track ../common/aclocal.m4 changes.
1033
1034Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1035
1036 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1037
1038Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1039
1040 * configure: Regenerated to track ../common/aclocal.m4 changes.
1041 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1042
1043Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1044
1045 * configure: Regenerated to track ../common/aclocal.m4 changes.
1046
1047Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1048
1049 * interp.c (Max, Min): Comment out functions. Not yet used.
1050
1051Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1052
1053 * configure: Regenerated to track ../common/aclocal.m4 changes.
1054
1055Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1056
1057 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1058 configurable settings for stand-alone simulator.
1059
1060 * configure.in: Added X11 search, just in case.
1061
1062 * configure: Regenerated.
1063
1064Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1065
1066 * interp.c (sim_write, sim_read, load_memory, store_memory):
1067 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1068
1069Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1070
1071 * sim-main.h (GETFCC): Return an unsigned value.
1072
1073Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1074
1075 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1076 (DADD): Result destination is RD not RT.
1077
1078Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1079
1080 * sim-main.h (HIACCESS, LOACCESS): Always define.
1081
1082 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1083
1084 * interp.c (sim_info): Delete.
1085
1086Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1087
1088 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1089 (mips_option_handler): New argument `cpu'.
1090 (sim_open): Update call to sim_add_option_table.
1091
1092Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1093
1094 * mips.igen (CxC1): Add tracing.
1095
1096Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1097
1098 * sim-main.h (Max, Min): Declare.
1099
1100 * interp.c (Max, Min): New functions.
1101
1102 * mips.igen (BC1): Add tracing.
1103
1104Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1105
1106 * interp.c Added memory map for stack in vr4100
1107
1108Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1109
1110 * interp.c (load_memory): Add missing "break"'s.
1111
1112Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1113
1114 * interp.c (sim_store_register, sim_fetch_register): Pass in
1115 length parameter. Return -1.
1116
1117Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1118
1119 * interp.c: Added hardware init hook, fixed warnings.
1120
1121Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1122
1123 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1124
1125Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1126
1127 * interp.c (ifetch16): New function.
1128
1129 * sim-main.h (IMEM32): Rename IMEM.
1130 (IMEM16_IMMED): Define.
1131 (IMEM16): Define.
1132 (DELAY_SLOT): Update.
1133
1134 * m16run.c (sim_engine_run): New file.
1135
1136 * m16.igen: All instructions except LB.
1137 (LB): Call do_load_byte.
1138 * mips.igen (do_load_byte): New function.
1139 (LB): Call do_load_byte.
1140
1141 * mips.igen: Move spec for insn bit size and high bit from here.
1142 * Makefile.in (tmp-igen, tmp-m16): To here.
1143
1144 * m16.dc: New file, decode mips16 instructions.
1145
1146 * Makefile.in (SIM_NO_ALL): Define.
1147 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1148
1149Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1150
1151 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1152 point unit to 32 bit registers.
1153 * configure: Re-generate.
1154
1155Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1156
1157 * configure.in (sim_use_gen): Make IGEN the default simulator
1158 generator for generic 32 and 64 bit mips targets.
1159 * configure: Re-generate.
1160
1161Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1162
1163 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1164 bitsize.
1165
1166 * interp.c (sim_fetch_register, sim_store_register): Read/write
1167 FGR from correct location.
1168 (sim_open): Set size of FGR's according to
1169 WITH_TARGET_FLOATING_POINT_BITSIZE.
1170
1171 * sim-main.h (FGR): Store floating point registers in a separate
1172 array.
1173
1174Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1175
1176 * configure: Regenerated to track ../common/aclocal.m4 changes.
1177
1178Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1179
1180 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1181
1182 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1183
1184 * interp.c (pending_tick): New function. Deliver pending writes.
1185
1186 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1187 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1188 it can handle mixed sized quantites and single bits.
1189
1190Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1191
1192 * interp.c (oengine.h): Do not include when building with IGEN.
1193 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1194 (sim_info): Ditto for PROCESSOR_64BIT.
1195 (sim_monitor): Replace ut_reg with unsigned_word.
1196 (*): Ditto for t_reg.
1197 (LOADDRMASK): Define.
1198 (sim_open): Remove defunct check that host FP is IEEE compliant,
1199 using software to emulate floating point.
1200 (value_fpr, ...): Always compile, was conditional on HASFPU.
1201
1202Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1203
1204 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1205 size.
1206
1207 * interp.c (SD, CPU): Define.
1208 (mips_option_handler): Set flags in each CPU.
1209 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1210 (sim_close): Do not clear STATE, deleted anyway.
1211 (sim_write, sim_read): Assume CPU zero's vm should be used for
1212 data transfers.
1213 (sim_create_inferior): Set the PC for all processors.
1214 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1215 argument.
1216 (mips16_entry): Pass correct nr of args to store_word, load_word.
1217 (ColdReset): Cold reset all cpu's.
1218 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1219 (sim_monitor, load_memory, store_memory, signal_exception): Use
1220 `CPU' instead of STATE_CPU.
1221
1222
1223 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1224 SD or CPU_.
1225
1226 * sim-main.h (signal_exception): Add sim_cpu arg.
1227 (SignalException*): Pass both SD and CPU to signal_exception.
1228 * interp.c (signal_exception): Update.
1229
1230 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1231 Ditto
1232 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1233 address_translation): Ditto
1234 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1235
1236Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1237
1238 * configure: Regenerated to track ../common/aclocal.m4 changes.
1239
1240Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1241
1242 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1243
1244 * mips.igen (model): Map processor names onto BFD name.
1245
1246 * sim-main.h (CPU_CIA): Delete.
1247 (SET_CIA, GET_CIA): Define
1248
1249Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1250
1251 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1252 regiser.
1253
1254 * configure.in (default_endian): Configure a big-endian simulator
1255 by default.
1256 * configure: Re-generate.
1257
1258Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1259
1260 * configure: Regenerated to track ../common/aclocal.m4 changes.
1261
1262Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1263
1264 * interp.c (sim_monitor): Handle Densan monitor outbyte
1265 and inbyte functions.
1266
12671997-12-29 Felix Lee <flee@cygnus.com>
1268
1269 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1270
1271Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1272
1273 * Makefile.in (tmp-igen): Arrange for $zero to always be
1274 reset to zero after every instruction.
1275
1276Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1277
1278 * configure: Regenerated to track ../common/aclocal.m4 changes.
1279 * config.in: Ditto.
1280
1281Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1282
1283 * mips.igen (MSUB): Fix to work like MADD.
1284 * gencode.c (MSUB): Similarly.
1285
1286Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1287
1288 * configure: Regenerated to track ../common/aclocal.m4 changes.
1289
1290Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1291
1292 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1293
1294Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1295
1296 * sim-main.h (sim-fpu.h): Include.
1297
1298 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1299 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1300 using host independant sim_fpu module.
1301
1302Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1303
1304 * interp.c (signal_exception): Report internal errors with SIGABRT
1305 not SIGQUIT.
1306
1307 * sim-main.h (C0_CONFIG): New register.
1308 (signal.h): No longer include.
1309
1310 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1311
1312Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1313
1314 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1315
1316Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1317
1318 * mips.igen: Tag vr5000 instructions.
1319 (ANDI): Was missing mipsIV model, fix assembler syntax.
1320 (do_c_cond_fmt): New function.
1321 (C.cond.fmt): Handle mips I-III which do not support CC field
1322 separatly.
1323 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1324 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1325 in IV3.2 spec.
1326 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1327 vr5000 which saves LO in a GPR separatly.
1328
1329 * configure.in (enable-sim-igen): For vr5000, select vr5000
1330 specific instructions.
1331 * configure: Re-generate.
1332
1333Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1334
1335 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1336
1337 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1338 fmt_uninterpreted_64 bit cases to switch. Convert to
1339 fmt_formatted,
1340
1341 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1342
1343 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1344 as specified in IV3.2 spec.
1345 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1346
1347Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1348
1349 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1350 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1351 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1352 PENDING_FILL versions of instructions. Simplify.
1353 (X): New function.
1354 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1355 instructions.
1356 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1357 a signed value.
1358 (MTHI, MFHI): Disable code checking HI-LO.
1359
1360 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1361 global.
1362 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1363
1364Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1365
1366 * gencode.c (build_mips16_operands): Replace IPC with cia.
1367
1368 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1369 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1370 IPC to `cia'.
1371 (UndefinedResult): Replace function with macro/function
1372 combination.
1373 (sim_engine_run): Don't save PC in IPC.
1374
1375 * sim-main.h (IPC): Delete.
1376
1377
1378 * interp.c (signal_exception, store_word, load_word,
1379 address_translation, load_memory, store_memory, cache_op,
1380 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1381 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1382 current instruction address - cia - argument.
1383 (sim_read, sim_write): Call address_translation directly.
1384 (sim_engine_run): Rename variable vaddr to cia.
1385 (signal_exception): Pass cia to sim_monitor
1386
1387 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1388 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1389 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1390
1391 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1392 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1393 SIM_ASSERT.
1394
1395 * interp.c (signal_exception): Pass restart address to
1396 sim_engine_restart.
1397
1398 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1399 idecode.o): Add dependency.
1400
1401 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1402 Delete definitions
1403 (DELAY_SLOT): Update NIA not PC with branch address.
1404 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1405
1406 * mips.igen: Use CIA not PC in branch calculations.
1407 (illegal): Call SignalException.
1408 (BEQ, ADDIU): Fix assembler.
1409
1410Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1411
1412 * m16.igen (JALX): Was missing.
1413
1414 * configure.in (enable-sim-igen): New configuration option.
1415 * configure: Re-generate.
1416
1417 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1418
1419 * interp.c (load_memory, store_memory): Delete parameter RAW.
1420 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1421 bypassing {load,store}_memory.
1422
1423 * sim-main.h (ByteSwapMem): Delete definition.
1424
1425 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1426
1427 * interp.c (sim_do_command, sim_commands): Delete mips specific
1428 commands. Handled by module sim-options.
1429
1430 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1431 (WITH_MODULO_MEMORY): Define.
1432
1433 * interp.c (sim_info): Delete code printing memory size.
1434
1435 * interp.c (mips_size): Nee sim_size, delete function.
1436 (power2): Delete.
1437 (monitor, monitor_base, monitor_size): Delete global variables.
1438 (sim_open, sim_close): Delete code creating monitor and other
1439 memory regions. Use sim-memopts module, via sim_do_commandf, to
1440 manage memory regions.
1441 (load_memory, store_memory): Use sim-core for memory model.
1442
1443 * interp.c (address_translation): Delete all memory map code
1444 except line forcing 32 bit addresses.
1445
1446Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1447
1448 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1449 trace options.
1450
1451 * interp.c (logfh, logfile): Delete globals.
1452 (sim_open, sim_close): Delete code opening & closing log file.
1453 (mips_option_handler): Delete -l and -n options.
1454 (OPTION mips_options): Ditto.
1455
1456 * interp.c (OPTION mips_options): Rename option trace to dinero.
1457 (mips_option_handler): Update.
1458
1459Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1460
1461 * interp.c (fetch_str): New function.
1462 (sim_monitor): Rewrite using sim_read & sim_write.
1463 (sim_open): Check magic number.
1464 (sim_open): Write monitor vectors into memory using sim_write.
1465 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1466 (sim_read, sim_write): Simplify - transfer data one byte at a
1467 time.
1468 (load_memory, store_memory): Clarify meaning of parameter RAW.
1469
1470 * sim-main.h (isHOST): Defete definition.
1471 (isTARGET): Mark as depreciated.
1472 (address_translation): Delete parameter HOST.
1473
1474 * interp.c (address_translation): Delete parameter HOST.
1475
1476Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1477
1478 * mips.igen:
1479
1480 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1481 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1482
1483Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1484
1485 * mips.igen: Add model filter field to records.
1486
1487Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1488
1489 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1490
1491 interp.c (sim_engine_run): Do not compile function sim_engine_run
1492 when WITH_IGEN == 1.
1493
1494 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1495 target architecture.
1496
1497 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1498 igen. Replace with configuration variables sim_igen_flags /
1499 sim_m16_flags.
1500
1501 * m16.igen: New file. Copy mips16 insns here.
1502 * mips.igen: From here.
1503
1504Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1505
1506 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1507 to top.
1508 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1509
1510Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1511
1512 * gencode.c (build_instruction): Follow sim_write's lead in using
1513 BigEndianMem instead of !ByteSwapMem.
1514
1515Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1516
1517 * configure.in (sim_gen): Dependent on target, select type of
1518 generator. Always select old style generator.
1519
1520 configure: Re-generate.
1521
1522 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1523 targets.
1524 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1525 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1526 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1527 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1528 SIM_@sim_gen@_*, set by autoconf.
1529
1530Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1531
1532 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1533
1534 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1535 CURRENT_FLOATING_POINT instead.
1536
1537 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1538 (address_translation): Raise exception InstructionFetch when
1539 translation fails and isINSTRUCTION.
1540
1541 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1542 sim_engine_run): Change type of of vaddr and paddr to
1543 address_word.
1544 (address_translation, prefetch, load_memory, store_memory,
1545 cache_op): Change type of vAddr and pAddr to address_word.
1546
1547 * gencode.c (build_instruction): Change type of vaddr and paddr to
1548 address_word.
1549
1550Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1551
1552 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1553 macro to obtain result of ALU op.
1554
1555Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1556
1557 * interp.c (sim_info): Call profile_print.
1558
1559Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1560
1561 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1562
1563 * sim-main.h (WITH_PROFILE): Do not define, defined in
1564 common/sim-config.h. Use sim-profile module.
1565 (simPROFILE): Delete defintion.
1566
1567 * interp.c (PROFILE): Delete definition.
1568 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1569 (sim_close): Delete code writing profile histogram.
1570 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1571 Delete.
1572 (sim_engine_run): Delete code profiling the PC.
1573
1574Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1575
1576 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1577
1578 * interp.c (sim_monitor): Make register pointers of type
1579 unsigned_word*.
1580
1581 * sim-main.h: Make registers of type unsigned_word not
1582 signed_word.
1583
1584Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1585
1586 * interp.c (sync_operation): Rename from SyncOperation, make
1587 global, add SD argument.
1588 (prefetch): Rename from Prefetch, make global, add SD argument.
1589 (decode_coproc): Make global.
1590
1591 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1592
1593 * gencode.c (build_instruction): Generate DecodeCoproc not
1594 decode_coproc calls.
1595
1596 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1597 (SizeFGR): Move to sim-main.h
1598 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1599 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1600 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1601 sim-main.h.
1602 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1603 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1604 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1605 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1606 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1607 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1608
1609 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1610 exception.
1611 (sim-alu.h): Include.
1612 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1613 (sim_cia): Typedef to instruction_address.
1614
1615Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1616
1617 * Makefile.in (interp.o): Rename generated file engine.c to
1618 oengine.c.
1619
1620 * interp.c: Update.
1621
1622Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1623
1624 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1625
1626Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1627
1628 * gencode.c (build_instruction): For "FPSQRT", output correct
1629 number of arguments to Recip.
1630
1631Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632
1633 * Makefile.in (interp.o): Depends on sim-main.h
1634
1635 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1636
1637 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1638 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1639 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1640 STATE, DSSTATE): Define
1641 (GPR, FGRIDX, ..): Define.
1642
1643 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1644 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1645 (GPR, FGRIDX, ...): Delete macros.
1646
1647 * interp.c: Update names to match defines from sim-main.h
1648
1649Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * interp.c (sim_monitor): Add SD argument.
1652 (sim_warning): Delete. Replace calls with calls to
1653 sim_io_eprintf.
1654 (sim_error): Delete. Replace calls with sim_io_error.
1655 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1656 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1657 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1658 argument.
1659 (mips_size): Rename from sim_size. Add SD argument.
1660
1661 * interp.c (simulator): Delete global variable.
1662 (callback): Delete global variable.
1663 (mips_option_handler, sim_open, sim_write, sim_read,
1664 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1665 sim_size,sim_monitor): Use sim_io_* not callback->*.
1666 (sim_open): ZALLOC simulator struct.
1667 (PROFILE): Do not define.
1668
1669Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1670
1671 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1672 support.h with corresponding code.
1673
1674 * sim-main.h (word64, uword64), support.h: Move definition to
1675 sim-main.h.
1676 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1677
1678 * support.h: Delete
1679 * Makefile.in: Update dependencies
1680 * interp.c: Do not include.
1681
1682Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1683
1684 * interp.c (address_translation, load_memory, store_memory,
1685 cache_op): Rename to from AddressTranslation et.al., make global,
1686 add SD argument
1687
1688 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1689 CacheOp): Define.
1690
1691 * interp.c (SignalException): Rename to signal_exception, make
1692 global.
1693
1694 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1695
1696 * sim-main.h (SignalException, SignalExceptionInterrupt,
1697 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1698 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1699 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1700 Define.
1701
1702 * interp.c, support.h: Use.
1703
1704Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1705
1706 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1707 to value_fpr / store_fpr. Add SD argument.
1708 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1709 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1710
1711 * sim-main.h (ValueFPR, StoreFPR): Define.
1712
1713Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1714
1715 * interp.c (sim_engine_run): Check consistency between configure
1716 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1717 and HASFPU.
1718
1719 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1720 (mips_fpu): Configure WITH_FLOATING_POINT.
1721 (mips_endian): Configure WITH_TARGET_ENDIAN.
1722 * configure: Update.
1723
1724Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1725
1726 * configure: Regenerated to track ../common/aclocal.m4 changes.
1727
1728Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1729
1730 * configure: Regenerated.
1731
1732Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1733
1734 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1735
1736Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1737
1738 * gencode.c (print_igen_insn_models): Assume certain architectures
1739 include all mips* instructions.
1740 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1741 instruction.
1742
1743 * Makefile.in (tmp.igen): Add target. Generate igen input from
1744 gencode file.
1745
1746 * gencode.c (FEATURE_IGEN): Define.
1747 (main): Add --igen option. Generate output in igen format.
1748 (process_instructions): Format output according to igen option.
1749 (print_igen_insn_format): New function.
1750 (print_igen_insn_models): New function.
1751 (process_instructions): Only issue warnings and ignore
1752 instructions when no FEATURE_IGEN.
1753
1754Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1755
1756 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1757 MIPS targets.
1758
1759Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1760
1761 * configure: Regenerated to track ../common/aclocal.m4 changes.
1762
1763Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1764
1765 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1766 SIM_RESERVED_BITS): Delete, moved to common.
1767 (SIM_EXTRA_CFLAGS): Update.
1768
1769Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1770
1771 * configure.in: Configure non-strict memory alignment.
1772 * configure: Regenerated to track ../common/aclocal.m4 changes.
1773
1774Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1775
1776 * configure: Regenerated to track ../common/aclocal.m4 changes.
1777
1778Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1779
1780 * gencode.c (SDBBP,DERET): Added (3900) insns.
1781 (RFE): Turn on for 3900.
1782 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1783 (dsstate): Made global.
1784 (SUBTARGET_R3900): Added.
1785 (CANCELDELAYSLOT): New.
1786 (SignalException): Ignore SystemCall rather than ignore and
1787 terminate. Add DebugBreakPoint handling.
1788 (decode_coproc): New insns RFE, DERET; and new registers Debug
1789 and DEPC protected by SUBTARGET_R3900.
1790 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1791 bits explicitly.
1792 * Makefile.in,configure.in: Add mips subtarget option.
1793 * configure: Update.
1794
1795Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1796
1797 * gencode.c: Add r3900 (tx39).
1798
1799
1800Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1801
1802 * gencode.c (build_instruction): Don't need to subtract 4 for
1803 JALR, just 2.
1804
1805Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1806
1807 * interp.c: Correct some HASFPU problems.
1808
1809Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1810
1811 * configure: Regenerated to track ../common/aclocal.m4 changes.
1812
1813Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1814
1815 * interp.c (mips_options): Fix samples option short form, should
1816 be `x'.
1817
1818Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1819
1820 * interp.c (sim_info): Enable info code. Was just returning.
1821
1822Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1823
1824 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1825 MFC0.
1826
1827Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1828
1829 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1830 constants.
1831 (build_instruction): Ditto for LL.
1832
1833Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1834
1835 * configure: Regenerated to track ../common/aclocal.m4 changes.
1836
1837Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1838
1839 * configure: Regenerated to track ../common/aclocal.m4 changes.
1840 * config.in: Ditto.
1841
1842Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1843
1844 * interp.c (sim_open): Add call to sim_analyze_program, update
1845 call to sim_config.
1846
1847Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1848
1849 * interp.c (sim_kill): Delete.
1850 (sim_create_inferior): Add ABFD argument. Set PC from same.
1851 (sim_load): Move code initializing trap handlers from here.
1852 (sim_open): To here.
1853 (sim_load): Delete, use sim-hload.c.
1854
1855 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1856
1857Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1858
1859 * configure: Regenerated to track ../common/aclocal.m4 changes.
1860 * config.in: Ditto.
1861
1862Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1863
1864 * interp.c (sim_open): Add ABFD argument.
1865 (sim_load): Move call to sim_config from here.
1866 (sim_open): To here. Check return status.
1867
1868Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1869
1870 * gencode.c (build_instruction): Two arg MADD should
1871 not assign result to $0.
1872
1873Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1874
1875 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1876 * sim/mips/configure.in: Regenerate.
1877
1878Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1879
1880 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1881 signed8, unsigned8 et.al. types.
1882
1883 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1884 hosts when selecting subreg.
1885
1886Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1887
1888 * interp.c (sim_engine_run): Reset the ZERO register to zero
1889 regardless of FEATURE_WARN_ZERO.
1890 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1891
1892Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1893
1894 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1895 (SignalException): For BreakPoints ignore any mode bits and just
1896 save the PC.
1897 (SignalException): Always set the CAUSE register.
1898
1899Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1900
1901 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1902 exception has been taken.
1903
1904 * interp.c: Implement the ERET and mt/f sr instructions.
1905
1906Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1907
1908 * interp.c (SignalException): Don't bother restarting an
1909 interrupt.
1910
1911Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1912
1913 * interp.c (SignalException): Really take an interrupt.
1914 (interrupt_event): Only deliver interrupts when enabled.
1915
1916Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1917
1918 * interp.c (sim_info): Only print info when verbose.
1919 (sim_info) Use sim_io_printf for output.
1920
1921Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1922
1923 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1924 mips architectures.
1925
1926Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1927
1928 * interp.c (sim_do_command): Check for common commands if a
1929 simulator specific command fails.
1930
1931Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1932
1933 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1934 and simBE when DEBUG is defined.
1935
1936Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1937
1938 * interp.c (interrupt_event): New function. Pass exception event
1939 onto exception handler.
1940
1941 * configure.in: Check for stdlib.h.
1942 * configure: Regenerate.
1943
1944 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1945 variable declaration.
1946 (build_instruction): Initialize memval1.
1947 (build_instruction): Add UNUSED attribute to byte, bigend,
1948 reverse.
1949 (build_operands): Ditto.
1950
1951 * interp.c: Fix GCC warnings.
1952 (sim_get_quit_code): Delete.
1953
1954 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1955 * Makefile.in: Ditto.
1956 * configure: Re-generate.
1957
1958 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1959
1960Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1961
1962 * interp.c (mips_option_handler): New function parse argumes using
1963 sim-options.
1964 (myname): Replace with STATE_MY_NAME.
1965 (sim_open): Delete check for host endianness - performed by
1966 sim_config.
1967 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1968 (sim_open): Move much of the initialization from here.
1969 (sim_load): To here. After the image has been loaded and
1970 endianness set.
1971 (sim_open): Move ColdReset from here.
1972 (sim_create_inferior): To here.
1973 (sim_open): Make FP check less dependant on host endianness.
1974
1975 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1976 run.
1977 * interp.c (sim_set_callbacks): Delete.
1978
1979 * interp.c (membank, membank_base, membank_size): Replace with
1980 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1981 (sim_open): Remove call to callback->init. gdb/run do this.
1982
1983 * interp.c: Update
1984
1985 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1986
1987 * interp.c (big_endian_p): Delete, replaced by
1988 current_target_byte_order.
1989
1990Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1991
1992 * interp.c (host_read_long, host_read_word, host_swap_word,
1993 host_swap_long): Delete. Using common sim-endian.
1994 (sim_fetch_register, sim_store_register): Use H2T.
1995 (pipeline_ticks): Delete. Handled by sim-events.
1996 (sim_info): Update.
1997 (sim_engine_run): Update.
1998
1999Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2000
2001 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2002 reason from here.
2003 (SignalException): To here. Signal using sim_engine_halt.
2004 (sim_stop_reason): Delete, moved to common.
2005
2006Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2007
2008 * interp.c (sim_open): Add callback argument.
2009 (sim_set_callbacks): Delete SIM_DESC argument.
2010 (sim_size): Ditto.
2011
2012Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2013
2014 * Makefile.in (SIM_OBJS): Add common modules.
2015
2016 * interp.c (sim_set_callbacks): Also set SD callback.
2017 (set_endianness, xfer_*, swap_*): Delete.
2018 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2019 Change to functions using sim-endian macros.
2020 (control_c, sim_stop): Delete, use common version.
2021 (simulate): Convert into.
2022 (sim_engine_run): This function.
2023 (sim_resume): Delete.
2024
2025 * interp.c (simulation): New variable - the simulator object.
2026 (sim_kind): Delete global - merged into simulation.
2027 (sim_load): Cleanup. Move PC assignment from here.
2028 (sim_create_inferior): To here.
2029
2030 * sim-main.h: New file.
2031 * interp.c (sim-main.h): Include.
2032
2033Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2034
2035 * configure: Regenerated to track ../common/aclocal.m4 changes.
2036
2037Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2038
2039 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2040
2041Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2042
2043 * gencode.c (build_instruction): DIV instructions: check
2044 for division by zero and integer overflow before using
2045 host's division operation.
2046
2047Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2048
2049 * Makefile.in (SIM_OBJS): Add sim-load.o.
2050 * interp.c: #include bfd.h.
2051 (target_byte_order): Delete.
2052 (sim_kind, myname, big_endian_p): New static locals.
2053 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2054 after argument parsing. Recognize -E arg, set endianness accordingly.
2055 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2056 load file into simulator. Set PC from bfd.
2057 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2058 (set_endianness): Use big_endian_p instead of target_byte_order.
2059
2060Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2061
2062 * interp.c (sim_size): Delete prototype - conflicts with
2063 definition in remote-sim.h. Correct definition.
2064
2065Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2066
2067 * configure: Regenerated to track ../common/aclocal.m4 changes.
2068 * config.in: Ditto.
2069
2070Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2071
2072 * interp.c (sim_open): New arg `kind'.
2073
2074 * configure: Regenerated to track ../common/aclocal.m4 changes.
2075
2076Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2077
2078 * configure: Regenerated to track ../common/aclocal.m4 changes.
2079
2080Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2081
2082 * interp.c (sim_open): Set optind to 0 before calling getopt.
2083
2084Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2085
2086 * configure: Regenerated to track ../common/aclocal.m4 changes.
2087
2088Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2089
2090 * interp.c : Replace uses of pr_addr with pr_uword64
2091 where the bit length is always 64 independent of SIM_ADDR.
2092 (pr_uword64) : added.
2093
2094Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2095
2096 * configure: Re-generate.
2097
2098Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2099
2100 * configure: Regenerate to track ../common/aclocal.m4 changes.
2101
2102Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2103
2104 * interp.c (sim_open): New SIM_DESC result. Argument is now
2105 in argv form.
2106 (other sim_*): New SIM_DESC argument.
2107
2108Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2109
2110 * interp.c: Fix printing of addresses for non-64-bit targets.
2111 (pr_addr): Add function to print address based on size.
2112
2113Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2114
2115 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2116
2117Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2118
2119 * gencode.c (build_mips16_operands): Correct computation of base
2120 address for extended PC relative instruction.
2121
2122Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2123
2124 * interp.c (mips16_entry): Add support for floating point cases.
2125 (SignalException): Pass floating point cases to mips16_entry.
2126 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2127 registers.
2128 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2129 or fmt_word.
2130 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2131 and then set the state to fmt_uninterpreted.
2132 (COP_SW): Temporarily set the state to fmt_word while calling
2133 ValueFPR.
2134
2135Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2136
2137 * gencode.c (build_instruction): The high order may be set in the
2138 comparison flags at any ISA level, not just ISA 4.
2139
2140Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2141
2142 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2143 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2144 * configure.in: sinclude ../common/aclocal.m4.
2145 * configure: Regenerated.
2146
2147Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2148
2149 * configure: Rebuild after change to aclocal.m4.
2150
2151Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2152
2153 * configure configure.in Makefile.in: Update to new configure
2154 scheme which is more compatible with WinGDB builds.
2155 * configure.in: Improve comment on how to run autoconf.
2156 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2157 * Makefile.in: Use autoconf substitution to install common
2158 makefile fragment.
2159
2160Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2161
2162 * gencode.c (build_instruction): Use BigEndianCPU instead of
2163 ByteSwapMem.
2164
2165Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2166
2167 * interp.c (sim_monitor): Make output to stdout visible in
2168 wingdb's I/O log window.
2169
2170Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2171
2172 * support.h: Undo previous change to SIGTRAP
2173 and SIGQUIT values.
2174
2175Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2176
2177 * interp.c (store_word, load_word): New static functions.
2178 (mips16_entry): New static function.
2179 (SignalException): Look for mips16 entry and exit instructions.
2180 (simulate): Use the correct index when setting fpr_state after
2181 doing a pending move.
2182
2183Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2184
2185 * interp.c: Fix byte-swapping code throughout to work on
2186 both little- and big-endian hosts.
2187
2188Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2189
2190 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2191 with gdb/config/i386/xm-windows.h.
2192
2193Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2194
2195 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2196 that messes up arithmetic shifts.
2197
2198Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2199
2200 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2201 SIGTRAP and SIGQUIT for _WIN32.
2202
2203Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2204
2205 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2206 force a 64 bit multiplication.
2207 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2208 destination register is 0, since that is the default mips16 nop
2209 instruction.
2210
2211Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2212
2213 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2214 (build_endian_shift): Don't check proc64.
2215 (build_instruction): Always set memval to uword64. Cast op2 to
2216 uword64 when shifting it left in memory instructions. Always use
2217 the same code for stores--don't special case proc64.
2218
2219 * gencode.c (build_mips16_operands): Fix base PC value for PC
2220 relative operands.
2221 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2222 jal instruction.
2223 * interp.c (simJALDELAYSLOT): Define.
2224 (JALDELAYSLOT): Define.
2225 (INDELAYSLOT, INJALDELAYSLOT): Define.
2226 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2227
2228Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2229
2230 * interp.c (sim_open): add flush_cache as a PMON routine
2231 (sim_monitor): handle flush_cache by ignoring it
2232
2233Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2234
2235 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2236 BigEndianMem.
2237 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2238 (BigEndianMem): Rename to ByteSwapMem and change sense.
2239 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2240 BigEndianMem references to !ByteSwapMem.
2241 (set_endianness): New function, with prototype.
2242 (sim_open): Call set_endianness.
2243 (sim_info): Use simBE instead of BigEndianMem.
2244 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2245 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2246 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2247 ifdefs, keeping the prototype declaration.
2248 (swap_word): Rewrite correctly.
2249 (ColdReset): Delete references to CONFIG. Delete endianness related
2250 code; moved to set_endianness.
2251
2252Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2253
2254 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2255 * interp.c (CHECKHILO): Define away.
2256 (simSIGINT): New macro.
2257 (membank_size): Increase from 1MB to 2MB.
2258 (control_c): New function.
2259 (sim_resume): Rename parameter signal to signal_number. Add local
2260 variable prev. Call signal before and after simulate.
2261 (sim_stop_reason): Add simSIGINT support.
2262 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2263 functions always.
2264 (sim_warning): Delete call to SignalException. Do call printf_filtered
2265 if logfh is NULL.
2266 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2267 a call to sim_warning.
2268
2269Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2270
2271 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2272 16 bit instructions.
2273
2274Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2275
2276 Add support for mips16 (16 bit MIPS implementation):
2277 * gencode.c (inst_type): Add mips16 instruction encoding types.
2278 (GETDATASIZEINSN): Define.
2279 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2280 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2281 mtlo.
2282 (MIPS16_DECODE): New table, for mips16 instructions.
2283 (bitmap_val): New static function.
2284 (struct mips16_op): Define.
2285 (mips16_op_table): New table, for mips16 operands.
2286 (build_mips16_operands): New static function.
2287 (process_instructions): If PC is odd, decode a mips16
2288 instruction. Break out instruction handling into new
2289 build_instruction function.
2290 (build_instruction): New static function, broken out of
2291 process_instructions. Check modifiers rather than flags for SHIFT
2292 bit count and m[ft]{hi,lo} direction.
2293 (usage): Pass program name to fprintf.
2294 (main): Remove unused variable this_option_optind. Change
2295 ``*loptarg++'' to ``loptarg++''.
2296 (my_strtoul): Parenthesize && within ||.
2297 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2298 (simulate): If PC is odd, fetch a 16 bit instruction, and
2299 increment PC by 2 rather than 4.
2300 * configure.in: Add case for mips16*-*-*.
2301 * configure: Rebuild.
2302
2303Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2304
2305 * interp.c: Allow -t to enable tracing in standalone simulator.
2306 Fix garbage output in trace file and error messages.
2307
2308Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2309
2310 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2311 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2312 * configure.in: Simplify using macros in ../common/aclocal.m4.
2313 * configure: Regenerated.
2314 * tconfig.in: New file.
2315
2316Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2317
2318 * interp.c: Fix bugs in 64-bit port.
2319 Use ansi function declarations for msvc compiler.
2320 Initialize and test file pointer in trace code.
2321 Prevent duplicate definition of LAST_EMED_REGNUM.
2322
2323Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2324
2325 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2326
2327Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2328
2329 * interp.c (SignalException): Check for explicit terminating
2330 breakpoint value.
2331 * gencode.c: Pass instruction value through SignalException()
2332 calls for Trap, Breakpoint and Syscall.
2333
2334Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2335
2336 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2337 only used on those hosts that provide it.
2338 * configure.in: Add sqrt() to list of functions to be checked for.
2339 * config.in: Re-generated.
2340 * configure: Re-generated.
2341
2342Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2343
2344 * gencode.c (process_instructions): Call build_endian_shift when
2345 expanding STORE RIGHT, to fix swr.
2346 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2347 clear the high bits.
2348 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2349 Fix float to int conversions to produce signed values.
2350
2351Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2352
2353 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2354 (process_instructions): Correct handling of nor instruction.
2355 Correct shift count for 32 bit shift instructions. Correct sign
2356 extension for arithmetic shifts to not shift the number of bits in
2357 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2358 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2359 Fix madd.
2360 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2361 It's OK to have a mult follow a mult. What's not OK is to have a
2362 mult follow an mfhi.
2363 (Convert): Comment out incorrect rounding code.
2364
2365Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2366
2367 * interp.c (sim_monitor): Improved monitor printf
2368 simulation. Tidied up simulator warnings, and added "--log" option
2369 for directing warning message output.
2370 * gencode.c: Use sim_warning() rather than WARNING macro.
2371
2372Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2373
2374 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2375 getopt1.o, rather than on gencode.c. Link objects together.
2376 Don't link against -liberty.
2377 (gencode.o, getopt.o, getopt1.o): New targets.
2378 * gencode.c: Include <ctype.h> and "ansidecl.h".
2379 (AND): Undefine after including "ansidecl.h".
2380 (ULONG_MAX): Define if not defined.
2381 (OP_*): Don't define macros; now defined in opcode/mips.h.
2382 (main): Call my_strtoul rather than strtoul.
2383 (my_strtoul): New static function.
2384
2385Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2386
2387 * gencode.c (process_instructions): Generate word64 and uword64
2388 instead of `long long' and `unsigned long long' data types.
2389 * interp.c: #include sysdep.h to get signals, and define default
2390 for SIGBUS.
2391 * (Convert): Work around for Visual-C++ compiler bug with type
2392 conversion.
2393 * support.h: Make things compile under Visual-C++ by using
2394 __int64 instead of `long long'. Change many refs to long long
2395 into word64/uword64 typedefs.
2396
2397Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2398
2399 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2400 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2401 (docdir): Removed.
2402 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2403 (AC_PROG_INSTALL): Added.
2404 (AC_PROG_CC): Moved to before configure.host call.
2405 * configure: Rebuilt.
2406
2407Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2408
2409 * configure.in: Define @SIMCONF@ depending on mips target.
2410 * configure: Rebuild.
2411 * Makefile.in (run): Add @SIMCONF@ to control simulator
2412 construction.
2413 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2414 * interp.c: Remove some debugging, provide more detailed error
2415 messages, update memory accesses to use LOADDRMASK.
2416
2417Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2418
2419 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2420 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2421 stamp-h.
2422 * configure: Rebuild.
2423 * config.in: New file, generated by autoheader.
2424 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2425 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2426 HAVE_ANINT and HAVE_AINT, as appropriate.
2427 * Makefile.in (run): Use @LIBS@ rather than -lm.
2428 (interp.o): Depend upon config.h.
2429 (Makefile): Just rebuild Makefile.
2430 (clean): Remove stamp-h.
2431 (mostlyclean): Make the same as clean, not as distclean.
2432 (config.h, stamp-h): New targets.
2433
2434Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2435
2436 * interp.c (ColdReset): Fix boolean test. Make all simulator
2437 globals static.
2438
2439Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2440
2441 * interp.c (xfer_direct_word, xfer_direct_long,
2442 swap_direct_word, swap_direct_long, xfer_big_word,
2443 xfer_big_long, xfer_little_word, xfer_little_long,
2444 swap_word,swap_long): Added.
2445 * interp.c (ColdReset): Provide function indirection to
2446 host<->simulated_target transfer routines.
2447 * interp.c (sim_store_register, sim_fetch_register): Updated to
2448 make use of indirected transfer routines.
2449
2450Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2451
2452 * gencode.c (process_instructions): Ensure FP ABS instruction
2453 recognised.
2454 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2455 system call support.
2456
2457Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2458
2459 * interp.c (sim_do_command): Complain if callback structure not
2460 initialised.
2461
2462Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2463
2464 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2465 support for Sun hosts.
2466 * Makefile.in (gencode): Ensure the host compiler and libraries
2467 used for cross-hosted build.
2468
2469Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2470
2471 * interp.c, gencode.c: Some more (TODO) tidying.
2472
2473Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2474
2475 * gencode.c, interp.c: Replaced explicit long long references with
2476 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2477 * support.h (SET64LO, SET64HI): Macros added.
2478
2479Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2480
2481 * configure: Regenerate with autoconf 2.7.
2482
2483Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2484
2485 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2486 * support.h: Remove superfluous "1" from #if.
2487 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2488
2489Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2490
2491 * interp.c (StoreFPR): Control UndefinedResult() call on
2492 WARN_RESULT manifest.
2493
2494Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2495
2496 * gencode.c: Tidied instruction decoding, and added FP instruction
2497 support.
2498
2499 * interp.c: Added dineroIII, and BSD profiling support. Also
2500 run-time FP handling.
2501
2502Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2503
2504 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2505 gencode.c, interp.c, support.h: created.
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