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* gdbarch.sh (BREAKPOINT_FROM_PC): Return a const buffer.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
c429b7dd
CD		 12002-03-19 Chris Demetriou <cgd@broadcom.com>
2
3 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
4 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
5 unused definitions.
6
37d146fa
CD		 72002-03-19 Chris Demetriou <cgd@broadcom.com>
8
9 * cp1.c: Fix many formatting issues.
10
07892c0b
CD		 112002-03-19 Chris G. Demetriou <cgd@broadcom.com>
12
13 * cp1.c (fpu_format_name): New function to replace...
14 (DOFMT): This. Delete, and update all callers.
15 (fpu_rounding_mode_name): New function to replace...
16 (RMMODE): This. Delete, and update all callers.
17
487f79b7
CD		 182002-03-19 Chris G. Demetriou <cgd@broadcom.com>
19
20 * interp.c: Move FPU support routines from here to...
21 * cp1.c: Here. New file.
22 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
23 (cp1.o): New target.
24
1e799e28
CD		 252002-03-12 Chris Demetriou <cgd@broadcom.com>
26
27 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
28 * mips.igen (mips32, mips64): New models, add to all instructions
29 and functions as appropriate.
30 (loadstore_ea, check_u64): New variant for model mips64.
31 (check_fmt_p): New variant for models mipsV and mips64, remove
32 mipsV model marking fro other variant.
33 (SLL) Rename to...
34 (SLLa) this.
35 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
36 for mips32 and mips64.
37 (DCLO, DCLZ): New instructions for mips64.
38
82f728db
CD		 392002-03-07 Chris Demetriou <cgd@broadcom.com>
40
41 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
42 immediate or code as a hex value with the "%#lx" format.
43 (ANDI): Likewise, and fix printed instruction name.
44
b96e7ef1
CD		 452002-03-05 Chris Demetriou <cgd@broadcom.com>
46
47 * sim-main.h (UndefinedResult, Unpredictable): New macros
48 which currently do nothing.
49
d35d4f70
CD		 502002-03-05 Chris Demetriou <cgd@broadcom.com>
51
52 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
53 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
54 (status_CU3): New definitions.
55
56 * sim-main.h (ExceptionCause): Add new values for MIPS32
57 and MIPS64: MDMX, MCheck, CacheErr. Update comments
58 for DebugBreakPoint and NMIReset to note their status in
59 MIPS32 and MIPS64.
60 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
61 (SignalExceptionCacheErr): New exception macros.
62
3ad6f714
CD		 632002-03-05 Chris Demetriou <cgd@broadcom.com>
64
65 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
66 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
67 is always enabled.
68 (SignalExceptionCoProcessorUnusable): Take as argument the
69 unusable coprocessor number.
70
86b77b47
CD		 712002-03-05 Chris Demetriou <cgd@broadcom.com>
72
73 * mips.igen: Fix formatting of all SignalException calls.
74
97a88e93 752002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 76
77 * sim-main.h (SIGNEXTEND): Remove.
78
97a88e93 792002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 80
81 * mips.igen: Remove gencode comment from top of file, fix
82 spelling in another comment.
83
97a88e93 842002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 85
86 * mips.igen (check_fmt, check_fmt_p): New functions to check
87 whether specific floating point formats are usable.
88 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
89 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
90 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
91 Use the new functions.
92 (do_c_cond_fmt): Remove format checks...
93 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
94
97a88e93 952002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 96
97 * mips.igen: Fix formatting of check_fpu calls.
98
41774c9d
CD		 992002-03-03 Chris Demetriou <cgd@broadcom.com>
100
101 * mips.igen (FLOOR.L.fmt): Store correct destination register.
102
4a0bd876
CD		 1032002-03-03 Chris Demetriou <cgd@broadcom.com>
104
105 * mips.igen: Remove whitespace at end of lines.
106
09297648
CD		 1072002-03-02 Chris Demetriou <cgd@broadcom.com>
108
109 * mips.igen (loadstore_ea): New function to do effective
110 address calculations.
111 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
112 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
113 CACHE): Use loadstore_ea to do effective address computations.
114
043b7057
CD		 1152002-03-02 Chris Demetriou <cgd@broadcom.com>
116
117 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
118 * mips.igen (LL, CxC1, MxC1): Likewise.
119
c1e8ada4
CD		 1202002-03-02 Chris Demetriou <cgd@broadcom.com>
121
122 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
123 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
124 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
125 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
126 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
127 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
128 Don't split opcode fields by hand, use the opcode field values
129 provided by igen.
130
3e1dca16
CD		 1312002-03-01 Chris Demetriou <cgd@broadcom.com>
132
133 * mips.igen (do_divu): Fix spacing.
134
135 * mips.igen (do_dsllv): Move to be right before DSLLV,
136 to match the rest of the do_<shift> functions.
137
fff8d27d
CD		 1382002-03-01 Chris Demetriou <cgd@broadcom.com>
139
140 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
141 DSRL32, do_dsrlv): Trace inputs and results.
142
0d3e762b
CD		 1432002-03-01 Chris Demetriou <cgd@broadcom.com>
144
145 * mips.igen (CACHE): Provide instruction-printing string.
146
147 * interp.c (signal_exception): Comment tokens after #endif.
148
eb5fcf93
CD		 1492002-02-28 Chris Demetriou <cgd@broadcom.com>
150
151 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
152 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
153 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
154 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
155 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
156 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
157 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
158 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
159
bb22bd7d
CD		 1602002-02-28 Chris Demetriou <cgd@broadcom.com>
161
162 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
163 instruction-printing string.
164 (LWU): Use '64' as the filter flag.
165
91a177cf
CD		 1662002-02-28 Chris Demetriou <cgd@broadcom.com>
167
168 * mips.igen (SDXC1): Fix instruction-printing string.
169
387f484a
CD		 1702002-02-28 Chris Demetriou <cgd@broadcom.com>
171
172 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
173 filter flags "32,f".
174
3d81f391
CD		 1752002-02-27 Chris Demetriou <cgd@broadcom.com>
176
177 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
178 as the filter flag.
179
af5107af
CD		 1802002-02-27 Chris Demetriou <cgd@broadcom.com>
181
182 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
183 add a comma) so that it more closely match the MIPS ISA
184 documentation opcode partitioning.
185 (PREF): Put useful names on opcode fields, and include
186 instruction-printing string.
187
ca971540
CD		 1882002-02-27 Chris Demetriou <cgd@broadcom.com>
189
190 * mips.igen (check_u64): New function which in the future will
191 check whether 64-bit instructions are usable and signal an
192 exception if not. Currently a no-op.
193 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
194 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
195 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
196 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
197
198 * mips.igen (check_fpu): New function which in the future will
199 check whether FPU instructions are usable and signal an exception
200 if not. Currently a no-op.
201 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
202 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
203 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
204 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
205 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
206 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
207 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
208 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
209
1c47a468
CD		 2102002-02-27 Chris Demetriou <cgd@broadcom.com>
211
212 * mips.igen (do_load_left, do_load_right): Move to be immediately
213 following do_load.
214 (do_store_left, do_store_right): Move to be immediately following
215 do_store.
216
603a98e7
CD		 2172002-02-27 Chris Demetriou <cgd@broadcom.com>
218
219 * mips.igen (mipsV): New model name. Also, add it to
220 all instructions and functions where it is appropriate.
221
c5d00cc7
CD		 2222002-02-18 Chris Demetriou <cgd@broadcom.com>
223
224 * mips.igen: For all functions and instructions, list model
225 names that support that instruction one per line.
226
074e9cb8
CD		 2272002-02-11 Chris Demetriou <cgd@broadcom.com>
228
229 * mips.igen: Add some additional comments about supported
230 models, and about which instructions go where.
231 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
232 order as is used in the rest of the file.
233
9805e229
CD		 2342002-02-11 Chris Demetriou <cgd@broadcom.com>
235
236 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
237 indicating that ALU32_END or ALU64_END are there to check
238 for overflow.
239 (DADD): Likewise, but also remove previous comment about
240 overflow checking.
241
f701dad2
CD		 2422002-02-10 Chris Demetriou <cgd@broadcom.com>
243
244 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
245 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
246 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
247 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
248 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
249 fields (i.e., add and move commas) so that they more closely
250 match the MIPS ISA documentation opcode partitioning.
251
2522002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 253
254 * mips.igen (ADDI): Print immediate value.
255 (BREAK): Print code.
256 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
257 (SLL): Print "nop" specially, and don't run the code
258 that does the shift for the "nop" case.
259
9e52972e
FF		 2602001-11-17 Fred Fish <fnf@redhat.com>
261
262 * sim-main.h (float_operation): Move enum declaration outside
263 of _sim_cpu struct declaration.
264
c0efbca4
JB		 2652001-04-12 Jim Blandy <jimb@redhat.com>
266
267 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
268 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
269 set of the FCSR.
270 * sim-main.h (COCIDX): Remove definition; this isn't supported by
271 PENDING_FILL, and you can get the intended effect gracefully by
272 calling PENDING_SCHED directly.
273
fb891446
BE		 2742001-02-23 Ben Elliston <bje@redhat.com>
275
276 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
277 already defined elsewhere.
278
8030f857
BE		 2792001-02-19 Ben Elliston <bje@redhat.com>
280
281 * sim-main.h (sim_monitor): Return an int.
282 * interp.c (sim_monitor): Add return values.
283 (signal_exception): Handle error conditions from sim_monitor.
284
56b48a7a
CD		 2852001-02-08 Ben Elliston <bje@redhat.com>
286
287 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
288 (store_memory): Likewise, pass cia to sim_core_write*.
289
d3ee60d9
FCE		 2902000-10-19 Frank Ch. Eigler <fche@redhat.com>
291
292 On advice from Chris G. Demetriou <cgd@sibyte.com>:
293 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
294
071da002
AC		 295Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
296
297 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
298 * Makefile.in: Don't delete *.igen when cleaning directory.
299
a28c02cd
AC		 300Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
301
302 * m16.igen (break): Call SignalException not sim_engine_halt.
303
80ee11fa
AC		 304Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
305
306 From Jason Eckhardt:
307 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
308
673388c0
AC		 309Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
310
311 * mips.igen (MxC1, DMxC1): Fix printf formatting.
312
4c0deff4
NC		 3132000-05-24 Michael Hayes <mhayes@cygnus.com>
314
315 * mips.igen (do_dmultx): Fix typo.
316
eb2d80b4
AC		 317Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
318
319 * configure: Regenerated to track ../common/aclocal.m4 changes.
320
dd37a34b
AC		 321Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
322
323 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
324
4c0deff4
NC		 3252000-04-12 Frank Ch. Eigler <fche@redhat.com>
326
327 * sim-main.h (GPR_CLEAR): Define macro.
328
e30db738
AC		 329Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
330
331 * interp.c (decode_coproc): Output long using %lx and not %s.
332
cb7450ea
FCE		 3332000-03-21 Frank Ch. Eigler <fche@redhat.com>
334
335 * interp.c (sim_open): Sort & extend dummy memory regions for
336 --board=jmr3904 for eCos.
337
a3027dd7
FCE		 3382000-03-02 Frank Ch. Eigler <fche@redhat.com>
339
340 * configure: Regenerated.
341
342Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
343
344 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
345 calls, conditional on the simulator being in verbose mode.
346
dfcd3bfb
JM		 347Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
348
349 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
350 cache don't get ReservedInstruction traps.
351
c2d11a7d
JM		 3521999-11-29 Mark Salter <msalter@cygnus.com>
353
354 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
355 to clear status bits in sdisr register. This is how the hardware works.
356
357 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
358 being used by cygmon.
359
4ce44c66
JM		 3601999-11-11 Andrew Haley <aph@cygnus.com>
361
362 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
363 instructions.
364
cff3e48b
JM		 365Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
366
367 * mips.igen (MULT): Correct previous mis-applied patch.
368
d4f3574e
SS		 369Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
370
371 * mips.igen (delayslot32): Handle sequence like
372 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
373 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
374 (MULT): Actually pass the third register...
375
3761999-09-03 Mark Salter <msalter@cygnus.com>
377
378 * interp.c (sim_open): Added more memory aliases for additional
379 hardware being touched by cygmon on jmr3904 board.
380
381Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
382
383 * configure: Regenerated to track ../common/aclocal.m4 changes.
384
a0b3c4fd
JM		 385Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
386
387 * interp.c (sim_store_register): Handle case where client - GDB -
388 specifies that a 4 byte register is 8 bytes in size.
389 (sim_fetch_register): Ditto.
390
adf40b2e
JM		 3911999-07-14 Frank Ch. Eigler <fche@cygnus.com>
392
393 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
394 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
395 (idt_monitor_base): Base address for IDT monitor traps.
396 (pmon_monitor_base): Ditto for PMON.
397 (lsipmon_monitor_base): Ditto for LSI PMON.
398 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
399 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
400 (sim_firmware_command): New function.
401 (mips_option_handler): Call it for OPTION_FIRMWARE.
402 (sim_open): Allocate memory for idt_monitor region. If "--board"
403 option was given, add no monitor by default. Add BREAK hooks only if
404 monitors are also there.
405
43e526b9
JM		 406Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
407
408 * interp.c (sim_monitor): Flush output before reading input.
409
410Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
411
412 * tconfig.in (SIM_HANDLES_LMA): Always define.
413
414Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
415
416 From Mark Salter <msalter@cygnus.com>:
417 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
418 (sim_open): Add setup for BSP board.
419
9846de1b
JM		 420Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
421
422 * mips.igen (MULT, MULTU): Add syntax for two operand version.
423 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
424 them as unimplemented.
425
cd0fc7c3
SS		 4261999-05-08 Felix Lee <flee@cygnus.com>
427
428 * configure: Regenerated to track ../common/aclocal.m4 changes.
429
7a292a7a
SS		 4301999-04-21 Frank Ch. Eigler <fche@cygnus.com>
431
432 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
433
434Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
435
436 * configure.in: Any mips64vr5*-*-* target should have
437 -DTARGET_ENABLE_FR=1.
438 (default_endian): Any mips64vr*el-*-* target should default to
439 LITTLE_ENDIAN.
440 * configure: Re-generate.
441
4421999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
443
444 * mips.igen (ldl): Extend from _16_, not 32.
445
446Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
447
448 * interp.c (sim_store_register): Force registers written to by GDB
449 into an un-interpreted state.
450
c906108c
SS		 4511999-02-05 Frank Ch. Eigler <fche@cygnus.com>
452
453 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
454 CPU, start periodic background I/O polls.
455 (tx3904sio_poll): New function: periodic I/O poller.
456
4571998-12-30 Frank Ch. Eigler <fche@cygnus.com>
458
459 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
460
461Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
462
463 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
464 case statement.
465
4661998-12-29 Frank Ch. Eigler <fche@cygnus.com>
467
468 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
469 (load_word): Call SIM_CORE_SIGNAL hook on error.
470 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
471 starting. For exception dispatching, pass PC instead of NULL_CIA.
472 (decode_coproc): Use COP0_BADVADDR to store faulting address.
473 * sim-main.h (COP0_BADVADDR): Define.
474 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
475 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
476 (_sim_cpu): Add exc_* fields to store register value snapshots.
477 * mips.igen (*): Replace memory-related SignalException* calls
478 with references to SIM_CORE_SIGNAL hook.
479
480 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
481 fix.
482 * sim-main.c (*): Minor warning cleanups.
483
4841998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
485
486 * m16.igen (DADDIU5): Correct type-o.
487
488Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
489
490 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
491 variables.
492
493Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
494
495 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
496 to include path.
497 (interp.o): Add dependency on itable.h
498 (oengine.c, gencode): Delete remaining references.
499 (BUILT_SRC_FROM_GEN): Clean up.
500
5011998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
502
503 * vr4run.c: New.
504 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
505 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
506 tmp-run-hack) : New.
507 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
508 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
509 Drop the "64" qualifier to get the HACK generator working.
510 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
511 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
512 qualifier to get the hack generator working.
513 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
514 (DSLL): Use do_dsll.
515 (DSLLV): Use do_dsllv.
516 (DSRA): Use do_dsra.
517 (DSRL): Use do_dsrl.
518 (DSRLV): Use do_dsrlv.
519 (BC1): Move *vr4100 to get the HACK generator working.
520 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
521 get the HACK generator working.
522 (MACC) Rename to get the HACK generator working.
523 (DMACC,MACCS,DMACCS): Add the 64.
524
5251998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
526
527 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
528 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
529
5301998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
531
532 * mips/interp.c (DEBUG): Cleanups.
533
5341998-12-10 Frank Ch. Eigler <fche@cygnus.com>
535
536 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
537 (tx3904sio_tickle): fflush after a stdout character output.
538
5391998-12-03 Frank Ch. Eigler <fche@cygnus.com>
540
541 * interp.c (sim_close): Uninstall modules.
542
543Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
544
545 * sim-main.h, interp.c (sim_monitor): Change to global
546 function.
547
548Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
549
550 * configure.in (vr4100): Only include vr4100 instructions in
551 simulator.
552 * configure: Re-generate.
553 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
554
555Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
556
557 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
558 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
559 true alternative.
560
561 * configure.in (sim_default_gen, sim_use_gen): Replace with
562 sim_gen.
563 (--enable-sim-igen): Delete config option. Always using IGEN.
564 * configure: Re-generate.
565
566 * Makefile.in (gencode): Kill, kill, kill.
567 * gencode.c: Ditto.
568
569Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
570
571 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
572 bit mips16 igen simulator.
573 * configure: Re-generate.
574
575 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
576 as part of vr4100 ISA.
577 * vr.igen: Mark all instructions as 64 bit only.
578
579Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
580
581 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
582 Pacify GCC.
583
584Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
585
586 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
587 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
588 * configure: Re-generate.
589
590 * m16.igen (BREAK): Define breakpoint instruction.
591 (JALX32): Mark instruction as mips16 and not r3900.
592 * mips.igen (C.cond.fmt): Fix typo in instruction format.
593
594 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
595
596Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
597
598 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
599 insn as a debug breakpoint.
600
601 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
602 pending.slot_size.
603 (PENDING_SCHED): Clean up trace statement.
604 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
605 (PENDING_FILL): Delay write by only one cycle.
606 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
607
608 * sim-main.c (pending_tick): Clean up trace statements. Add trace
609 of pending writes.
610 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
611 32 & 64.
612 (pending_tick): Move incrementing of index to FOR statement.
613 (pending_tick): Only update PENDING_OUT after a write has occured.
614
615 * configure.in: Add explicit mips-lsi-* target. Use gencode to
616 build simulator.
617 * configure: Re-generate.
618
619 * interp.c (sim_engine_run OLD): Delete explicit call to
620 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
621
622Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
623
624 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
625 interrupt level number to match changed SignalExceptionInterrupt
626 macro.
627
628Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
629
630 * interp.c: #include "itable.h" if WITH_IGEN.
631 (get_insn_name): New function.
632 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
633 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
634
635Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
636
637 * configure: Rebuilt to inhale new common/aclocal.m4.
638
639Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
640
641 * dv-tx3904sio.c: Include sim-assert.h.
642
643Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
644
645 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
646 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
647 Reorganize target-specific sim-hardware checks.
648 * configure: rebuilt.
649 * interp.c (sim_open): For tx39 target boards, set
650 OPERATING_ENVIRONMENT, add tx3904sio devices.
651 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
652 ROM executables. Install dv-sockser into sim-modules list.
653
654 * dv-tx3904irc.c: Compiler warning clean-up.
655 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
656 frequent hw-trace messages.
657
658Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
659
660 * vr.igen (MulAcc): Identify as a vr4100 specific function.
661
662Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
663
664 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
665
666 * vr.igen: New file.
667 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
668 * mips.igen: Define vr4100 model. Include vr.igen.
669Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
670
671 * mips.igen (check_mf_hilo): Correct check.
672
673Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
674
675 * sim-main.h (interrupt_event): Add prototype.
676
677 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
678 register_ptr, register_value.
679 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
680
681 * sim-main.h (tracefh): Make extern.
682
683Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
684
685 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
686 Reduce unnecessarily high timer event frequency.
687 * dv-tx3904cpu.c: Ditto for interrupt event.
688
689Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
690
691 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
692 to allay warnings.
693 (interrupt_event): Made non-static.
694
695 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
696 interchange of configuration values for external vs. internal
697 clock dividers.
698
699Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
700
701 * mips.igen (BREAK): Moved code to here for
702 simulator-reserved break instructions.
703 * gencode.c (build_instruction): Ditto.
704 * interp.c (signal_exception): Code moved from here. Non-
705 reserved instructions now use exception vector, rather
706 than halting sim.
707 * sim-main.h: Moved magic constants to here.
708
709Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
710
711 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
712 register upon non-zero interrupt event level, clear upon zero
713 event value.
714 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
715 by passing zero event value.
716 (*_io_{read,write}_buffer): Endianness fixes.
717 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
718 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
719
720 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
721 serial I/O and timer module at base address 0xFFFF0000.
722
723Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
724
725 * mips.igen (SWC1) : Correct the handling of ReverseEndian
726 and BigEndianCPU.
727
728Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
729
730 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
731 parts.
732 * configure: Update.
733
734Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
735
736 * dv-tx3904tmr.c: New file - implements tx3904 timer.
737 * dv-tx3904{irc,cpu}.c: Mild reformatting.
738 * configure.in: Include tx3904tmr in hw_device list.
739 * configure: Rebuilt.
740 * interp.c (sim_open): Instantiate three timer instances.
741 Fix address typo of tx3904irc instance.
742
743Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
744
745 * interp.c (signal_exception): SystemCall exception now uses
746 the exception vector.
747
748Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
749
750 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
751 to allay warnings.
752
753Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
754
755 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
756
757Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
758
759 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
760
761 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
762 sim-main.h. Declare a struct hw_descriptor instead of struct
763 hw_device_descriptor.
764
765Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
766
767 * mips.igen (do_store_left, do_load_left): Compute nr of left and
768 right bits and then re-align left hand bytes to correct byte
769 lanes. Fix incorrect computation in do_store_left when loading
770 bytes from second word.
771
772Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
773
774 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
775 * interp.c (sim_open): Only create a device tree when HW is
776 enabled.
777
778 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
779 * interp.c (signal_exception): Ditto.
780
781Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
782
783 * gencode.c: Mark BEGEZALL as LIKELY.
784
785Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
786
787 * sim-main.h (ALU32_END): Sign extend 32 bit results.
788 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
789
790Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
791
792 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
793 modules. Recognize TX39 target with "mips*tx39" pattern.
794 * configure: Rebuilt.
795 * sim-main.h (*): Added many macros defining bits in
796 TX39 control registers.
797 (SignalInterrupt): Send actual PC instead of NULL.
798 (SignalNMIReset): New exception type.
799 * interp.c (board): New variable for future use to identify
800 a particular board being simulated.
801 (mips_option_handler,mips_options): Added "--board" option.
802 (interrupt_event): Send actual PC.
803 (sim_open): Make memory layout conditional on board setting.
804 (signal_exception): Initial implementation of hardware interrupt
805 handling. Accept another break instruction variant for simulator
806 exit.
807 (decode_coproc): Implement RFE instruction for TX39.
808 (mips.igen): Decode RFE instruction as such.
809 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
810 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
811 bbegin to implement memory map.
812 * dv-tx3904cpu.c: New file.
813 * dv-tx3904irc.c: New file.
814
815Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
816
817 * mips.igen (check_mt_hilo): Create a separate r3900 version.
818
819Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
820
821 * tx.igen (madd,maddu): Replace calls to check_op_hilo
822 with calls to check_div_hilo.
823
824Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
825
826 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
827 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
828 Add special r3900 version of do_mult_hilo.
829 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
830 with calls to check_mult_hilo.
831 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
832 with calls to check_div_hilo.
833
834Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
835
836 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
837 Document a replacement.
838
839Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
840
841 * interp.c (sim_monitor): Make mon_printf work.
842
843Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
844
845 * sim-main.h (INSN_NAME): New arg `cpu'.
846
847Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
848
849 * configure: Regenerated to track ../common/aclocal.m4 changes.
850
851Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
852
853 * configure: Regenerated to track ../common/aclocal.m4 changes.
854 * config.in: Ditto.
855
856Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
857
858 * acconfig.h: New file.
859 * configure.in: Reverted change of Apr 24; use sinclude again.
860
861Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
862
863 * configure: Regenerated to track ../common/aclocal.m4 changes.
864 * config.in: Ditto.
865
866Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
867
868 * configure.in: Don't call sinclude.
869
870Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
871
872 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
873
874Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
875
876 * mips.igen (ERET): Implement.
877
878 * interp.c (decode_coproc): Return sign-extended EPC.
879
880 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
881
882 * interp.c (signal_exception): Do not ignore Trap.
883 (signal_exception): On TRAP, restart at exception address.
884 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
885 (signal_exception): Update.
886 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
887 so that TRAP instructions are caught.
888
889Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
890
891 * sim-main.h (struct hilo_access, struct hilo_history): Define,
892 contains HI/LO access history.
893 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
894 (HIACCESS, LOACCESS): Delete, replace with
895 (HIHISTORY, LOHISTORY): New macros.
896 (CHECKHILO): Delete all, moved to mips.igen
897
898 * gencode.c (build_instruction): Do not generate checks for
899 correct HI/LO register usage.
900
901 * interp.c (old_engine_run): Delete checks for correct HI/LO
902 register usage.
903
904 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
905 check_mf_cycles): New functions.
906 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
907 do_divu, domultx, do_mult, do_multu): Use.
908
909 * tx.igen ("madd", "maddu"): Use.
910
911Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
912
913 * mips.igen (DSRAV): Use function do_dsrav.
914 (SRAV): Use new function do_srav.
915
916 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
917 (B): Sign extend 11 bit immediate.
918 (EXT-B*): Shift 16 bit immediate left by 1.
919 (ADDIU*): Don't sign extend immediate value.
920
921Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
922
923 * m16run.c (sim_engine_run): Restore CIA after handling an event.
924
925 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
926 functions.
927
928 * mips.igen (delayslot32, nullify_next_insn): New functions.
929 (m16.igen): Always include.
930 (do_*): Add more tracing.
931
932 * m16.igen (delayslot16): Add NIA argument, could be called by a
933 32 bit MIPS16 instruction.
934
935 * interp.c (ifetch16): Move function from here.
936 * sim-main.c (ifetch16): To here.
937
938 * sim-main.c (ifetch16, ifetch32): Update to match current
939 implementations of LH, LW.
940 (signal_exception): Don't print out incorrect hex value of illegal
941 instruction.
942
943Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
944
945 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
946 instruction.
947
948 * m16.igen: Implement MIPS16 instructions.
949
950 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
951 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
952 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
953 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
954 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
955 bodies of corresponding code from 32 bit insn to these. Also used
956 by MIPS16 versions of functions.
957
958 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
959 (IMEM16): Drop NR argument from macro.
960
961Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
962
963 * Makefile.in (SIM_OBJS): Add sim-main.o.
964
965 * sim-main.h (address_translation, load_memory, store_memory,
966 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
967 as INLINE_SIM_MAIN.
968 (pr_addr, pr_uword64): Declare.
969 (sim-main.c): Include when H_REVEALS_MODULE_P.
970
971 * interp.c (address_translation, load_memory, store_memory,
972 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
973 from here.
974 * sim-main.c: To here. Fix compilation problems.
975
976 * configure.in: Enable inlining.
977 * configure: Re-config.
978
979Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
980
981 * configure: Regenerated to track ../common/aclocal.m4 changes.
982
983Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
984
985 * mips.igen: Include tx.igen.
986 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
987 * tx.igen: New file, contains MADD and MADDU.
988
989 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
990 the hardwired constant `7'.
991 (store_memory): Ditto.
992 (LOADDRMASK): Move definition to sim-main.h.
993
994 mips.igen (MTC0): Enable for r3900.
995 (ADDU): Add trace.
996
997 mips.igen (do_load_byte): Delete.
998 (do_load, do_store, do_load_left, do_load_write, do_store_left,
999 do_store_right): New functions.
1000 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1001
1002 configure.in: Let the tx39 use igen again.
1003 configure: Update.
1004
1005Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1006
1007 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1008 not an address sized quantity. Return zero for cache sizes.
1009
1010Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1011
1012 * mips.igen (r3900): r3900 does not support 64 bit integer
1013 operations.
1014
1015Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1016
1017 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1018 than igen one.
1019 * configure : Rebuild.
1020
1021Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1022
1023 * configure: Regenerated to track ../common/aclocal.m4 changes.
1024
1025Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1026
1027 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1028
1029Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1030
1031 * configure: Regenerated to track ../common/aclocal.m4 changes.
1032 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1033
1034Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1035
1036 * configure: Regenerated to track ../common/aclocal.m4 changes.
1037
1038Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1039
1040 * interp.c (Max, Min): Comment out functions. Not yet used.
1041
1042Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1043
1044 * configure: Regenerated to track ../common/aclocal.m4 changes.
1045
1046Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1047
1048 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1049 configurable settings for stand-alone simulator.
1050
1051 * configure.in: Added X11 search, just in case.
1052
1053 * configure: Regenerated.
1054
1055Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1056
1057 * interp.c (sim_write, sim_read, load_memory, store_memory):
1058 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1059
1060Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1061
1062 * sim-main.h (GETFCC): Return an unsigned value.
1063
1064Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1065
1066 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1067 (DADD): Result destination is RD not RT.
1068
1069Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1070
1071 * sim-main.h (HIACCESS, LOACCESS): Always define.
1072
1073 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1074
1075 * interp.c (sim_info): Delete.
1076
1077Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1078
1079 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1080 (mips_option_handler): New argument `cpu'.
1081 (sim_open): Update call to sim_add_option_table.
1082
1083Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1084
1085 * mips.igen (CxC1): Add tracing.
1086
1087Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1088
1089 * sim-main.h (Max, Min): Declare.
1090
1091 * interp.c (Max, Min): New functions.
1092
1093 * mips.igen (BC1): Add tracing.
1094
1095Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1096
1097 * interp.c Added memory map for stack in vr4100
1098
1099Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1100
1101 * interp.c (load_memory): Add missing "break"'s.
1102
1103Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1104
1105 * interp.c (sim_store_register, sim_fetch_register): Pass in
1106 length parameter. Return -1.
1107
1108Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1109
1110 * interp.c: Added hardware init hook, fixed warnings.
1111
1112Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1113
1114 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1115
1116Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1117
1118 * interp.c (ifetch16): New function.
1119
1120 * sim-main.h (IMEM32): Rename IMEM.
1121 (IMEM16_IMMED): Define.
1122 (IMEM16): Define.
1123 (DELAY_SLOT): Update.
1124
1125 * m16run.c (sim_engine_run): New file.
1126
1127 * m16.igen: All instructions except LB.
1128 (LB): Call do_load_byte.
1129 * mips.igen (do_load_byte): New function.
1130 (LB): Call do_load_byte.
1131
1132 * mips.igen: Move spec for insn bit size and high bit from here.
1133 * Makefile.in (tmp-igen, tmp-m16): To here.
1134
1135 * m16.dc: New file, decode mips16 instructions.
1136
1137 * Makefile.in (SIM_NO_ALL): Define.
1138 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1139
1140Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1141
1142 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1143 point unit to 32 bit registers.
1144 * configure: Re-generate.
1145
1146Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1147
1148 * configure.in (sim_use_gen): Make IGEN the default simulator
1149 generator for generic 32 and 64 bit mips targets.
1150 * configure: Re-generate.
1151
1152Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1153
1154 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1155 bitsize.
1156
1157 * interp.c (sim_fetch_register, sim_store_register): Read/write
1158 FGR from correct location.
1159 (sim_open): Set size of FGR's according to
1160 WITH_TARGET_FLOATING_POINT_BITSIZE.
1161
1162 * sim-main.h (FGR): Store floating point registers in a separate
1163 array.
1164
1165Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1166
1167 * configure: Regenerated to track ../common/aclocal.m4 changes.
1168
1169Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1170
1171 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1172
1173 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1174
1175 * interp.c (pending_tick): New function. Deliver pending writes.
1176
1177 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1178 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1179 it can handle mixed sized quantites and single bits.
1180
1181Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1182
1183 * interp.c (oengine.h): Do not include when building with IGEN.
1184 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1185 (sim_info): Ditto for PROCESSOR_64BIT.
1186 (sim_monitor): Replace ut_reg with unsigned_word.
1187 (*): Ditto for t_reg.
1188 (LOADDRMASK): Define.
1189 (sim_open): Remove defunct check that host FP is IEEE compliant,
1190 using software to emulate floating point.
1191 (value_fpr, ...): Always compile, was conditional on HASFPU.
1192
1193Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1194
1195 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1196 size.
1197
1198 * interp.c (SD, CPU): Define.
1199 (mips_option_handler): Set flags in each CPU.
1200 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1201 (sim_close): Do not clear STATE, deleted anyway.
1202 (sim_write, sim_read): Assume CPU zero's vm should be used for
1203 data transfers.
1204 (sim_create_inferior): Set the PC for all processors.
1205 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1206 argument.
1207 (mips16_entry): Pass correct nr of args to store_word, load_word.
1208 (ColdReset): Cold reset all cpu's.
1209 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1210 (sim_monitor, load_memory, store_memory, signal_exception): Use
1211 `CPU' instead of STATE_CPU.
1212
1213
1214 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1215 SD or CPU_.
1216
1217 * sim-main.h (signal_exception): Add sim_cpu arg.
1218 (SignalException*): Pass both SD and CPU to signal_exception.
1219 * interp.c (signal_exception): Update.
1220
1221 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1222 Ditto
1223 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1224 address_translation): Ditto
1225 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1226
1227Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1228
1229 * configure: Regenerated to track ../common/aclocal.m4 changes.
1230
1231Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1232
1233 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1234
1235 * mips.igen (model): Map processor names onto BFD name.
1236
1237 * sim-main.h (CPU_CIA): Delete.
1238 (SET_CIA, GET_CIA): Define
1239
1240Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1241
1242 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1243 regiser.
1244
1245 * configure.in (default_endian): Configure a big-endian simulator
1246 by default.
1247 * configure: Re-generate.
1248
1249Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1250
1251 * configure: Regenerated to track ../common/aclocal.m4 changes.
1252
1253Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1254
1255 * interp.c (sim_monitor): Handle Densan monitor outbyte
1256 and inbyte functions.
1257
12581997-12-29 Felix Lee <flee@cygnus.com>
1259
1260 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1261
1262Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1263
1264 * Makefile.in (tmp-igen): Arrange for $zero to always be
1265 reset to zero after every instruction.
1266
1267Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1268
1269 * configure: Regenerated to track ../common/aclocal.m4 changes.
1270 * config.in: Ditto.
1271
1272Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1273
1274 * mips.igen (MSUB): Fix to work like MADD.
1275 * gencode.c (MSUB): Similarly.
1276
1277Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1278
1279 * configure: Regenerated to track ../common/aclocal.m4 changes.
1280
1281Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1282
1283 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1284
1285Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1286
1287 * sim-main.h (sim-fpu.h): Include.
1288
1289 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1290 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1291 using host independant sim_fpu module.
1292
1293Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1294
1295 * interp.c (signal_exception): Report internal errors with SIGABRT
1296 not SIGQUIT.
1297
1298 * sim-main.h (C0_CONFIG): New register.
1299 (signal.h): No longer include.
1300
1301 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1302
1303Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1304
1305 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1306
1307Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1308
1309 * mips.igen: Tag vr5000 instructions.
1310 (ANDI): Was missing mipsIV model, fix assembler syntax.
1311 (do_c_cond_fmt): New function.
1312 (C.cond.fmt): Handle mips I-III which do not support CC field
1313 separatly.
1314 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1315 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1316 in IV3.2 spec.
1317 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1318 vr5000 which saves LO in a GPR separatly.
1319
1320 * configure.in (enable-sim-igen): For vr5000, select vr5000
1321 specific instructions.
1322 * configure: Re-generate.
1323
1324Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1325
1326 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1327
1328 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1329 fmt_uninterpreted_64 bit cases to switch. Convert to
1330 fmt_formatted,
1331
1332 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1333
1334 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1335 as specified in IV3.2 spec.
1336 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1337
1338Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1339
1340 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1341 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1342 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1343 PENDING_FILL versions of instructions. Simplify.
1344 (X): New function.
1345 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1346 instructions.
1347 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1348 a signed value.
1349 (MTHI, MFHI): Disable code checking HI-LO.
1350
1351 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1352 global.
1353 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1354
1355Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1356
1357 * gencode.c (build_mips16_operands): Replace IPC with cia.
1358
1359 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1360 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1361 IPC to `cia'.
1362 (UndefinedResult): Replace function with macro/function
1363 combination.
1364 (sim_engine_run): Don't save PC in IPC.
1365
1366 * sim-main.h (IPC): Delete.
1367
1368
1369 * interp.c (signal_exception, store_word, load_word,
1370 address_translation, load_memory, store_memory, cache_op,
1371 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1372 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1373 current instruction address - cia - argument.
1374 (sim_read, sim_write): Call address_translation directly.
1375 (sim_engine_run): Rename variable vaddr to cia.
1376 (signal_exception): Pass cia to sim_monitor
1377
1378 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1379 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1380 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1381
1382 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1383 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1384 SIM_ASSERT.
1385
1386 * interp.c (signal_exception): Pass restart address to
1387 sim_engine_restart.
1388
1389 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1390 idecode.o): Add dependency.
1391
1392 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1393 Delete definitions
1394 (DELAY_SLOT): Update NIA not PC with branch address.
1395 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1396
1397 * mips.igen: Use CIA not PC in branch calculations.
1398 (illegal): Call SignalException.
1399 (BEQ, ADDIU): Fix assembler.
1400
1401Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1402
1403 * m16.igen (JALX): Was missing.
1404
1405 * configure.in (enable-sim-igen): New configuration option.
1406 * configure: Re-generate.
1407
1408 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1409
1410 * interp.c (load_memory, store_memory): Delete parameter RAW.
1411 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1412 bypassing {load,store}_memory.
1413
1414 * sim-main.h (ByteSwapMem): Delete definition.
1415
1416 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1417
1418 * interp.c (sim_do_command, sim_commands): Delete mips specific
1419 commands. Handled by module sim-options.
1420
1421 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1422 (WITH_MODULO_MEMORY): Define.
1423
1424 * interp.c (sim_info): Delete code printing memory size.
1425
1426 * interp.c (mips_size): Nee sim_size, delete function.
1427 (power2): Delete.
1428 (monitor, monitor_base, monitor_size): Delete global variables.
1429 (sim_open, sim_close): Delete code creating monitor and other
1430 memory regions. Use sim-memopts module, via sim_do_commandf, to
1431 manage memory regions.
1432 (load_memory, store_memory): Use sim-core for memory model.
1433
1434 * interp.c (address_translation): Delete all memory map code
1435 except line forcing 32 bit addresses.
1436
1437Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1438
1439 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1440 trace options.
1441
1442 * interp.c (logfh, logfile): Delete globals.
1443 (sim_open, sim_close): Delete code opening & closing log file.
1444 (mips_option_handler): Delete -l and -n options.
1445 (OPTION mips_options): Ditto.
1446
1447 * interp.c (OPTION mips_options): Rename option trace to dinero.
1448 (mips_option_handler): Update.
1449
1450Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1451
1452 * interp.c (fetch_str): New function.
1453 (sim_monitor): Rewrite using sim_read & sim_write.
1454 (sim_open): Check magic number.
1455 (sim_open): Write monitor vectors into memory using sim_write.
1456 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1457 (sim_read, sim_write): Simplify - transfer data one byte at a
1458 time.
1459 (load_memory, store_memory): Clarify meaning of parameter RAW.
1460
1461 * sim-main.h (isHOST): Defete definition.
1462 (isTARGET): Mark as depreciated.
1463 (address_translation): Delete parameter HOST.
1464
1465 * interp.c (address_translation): Delete parameter HOST.
1466
1467Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1468
1469 * mips.igen:
1470
1471 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1472 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1473
1474Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1475
1476 * mips.igen: Add model filter field to records.
1477
1478Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1479
1480 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1481
1482 interp.c (sim_engine_run): Do not compile function sim_engine_run
1483 when WITH_IGEN == 1.
1484
1485 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1486 target architecture.
1487
1488 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1489 igen. Replace with configuration variables sim_igen_flags /
1490 sim_m16_flags.
1491
1492 * m16.igen: New file. Copy mips16 insns here.
1493 * mips.igen: From here.
1494
1495Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1496
1497 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1498 to top.
1499 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1500
1501Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1502
1503 * gencode.c (build_instruction): Follow sim_write's lead in using
1504 BigEndianMem instead of !ByteSwapMem.
1505
1506Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1507
1508 * configure.in (sim_gen): Dependent on target, select type of
1509 generator. Always select old style generator.
1510
1511 configure: Re-generate.
1512
1513 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1514 targets.
1515 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1516 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1517 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1518 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1519 SIM_@sim_gen@_*, set by autoconf.
1520
1521Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1522
1523 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1524
1525 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1526 CURRENT_FLOATING_POINT instead.
1527
1528 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1529 (address_translation): Raise exception InstructionFetch when
1530 translation fails and isINSTRUCTION.
1531
1532 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1533 sim_engine_run): Change type of of vaddr and paddr to
1534 address_word.
1535 (address_translation, prefetch, load_memory, store_memory,
1536 cache_op): Change type of vAddr and pAddr to address_word.
1537
1538 * gencode.c (build_instruction): Change type of vaddr and paddr to
1539 address_word.
1540
1541Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1542
1543 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1544 macro to obtain result of ALU op.
1545
1546Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1547
1548 * interp.c (sim_info): Call profile_print.
1549
1550Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1551
1552 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1553
1554 * sim-main.h (WITH_PROFILE): Do not define, defined in
1555 common/sim-config.h. Use sim-profile module.
1556 (simPROFILE): Delete defintion.
1557
1558 * interp.c (PROFILE): Delete definition.
1559 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1560 (sim_close): Delete code writing profile histogram.
1561 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1562 Delete.
1563 (sim_engine_run): Delete code profiling the PC.
1564
1565Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1566
1567 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1568
1569 * interp.c (sim_monitor): Make register pointers of type
1570 unsigned_word*.
1571
1572 * sim-main.h: Make registers of type unsigned_word not
1573 signed_word.
1574
1575Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1576
1577 * interp.c (sync_operation): Rename from SyncOperation, make
1578 global, add SD argument.
1579 (prefetch): Rename from Prefetch, make global, add SD argument.
1580 (decode_coproc): Make global.
1581
1582 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1583
1584 * gencode.c (build_instruction): Generate DecodeCoproc not
1585 decode_coproc calls.
1586
1587 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1588 (SizeFGR): Move to sim-main.h
1589 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1590 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1591 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1592 sim-main.h.
1593 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1594 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1595 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1596 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1597 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1598 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1599
1600 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1601 exception.
1602 (sim-alu.h): Include.
1603 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1604 (sim_cia): Typedef to instruction_address.
1605
1606Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1607
1608 * Makefile.in (interp.o): Rename generated file engine.c to
1609 oengine.c.
1610
1611 * interp.c: Update.
1612
1613Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1614
1615 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1616
1617Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 * gencode.c (build_instruction): For "FPSQRT", output correct
1620 number of arguments to Recip.
1621
1622Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1623
1624 * Makefile.in (interp.o): Depends on sim-main.h
1625
1626 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1627
1628 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1629 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1630 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1631 STATE, DSSTATE): Define
1632 (GPR, FGRIDX, ..): Define.
1633
1634 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1635 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1636 (GPR, FGRIDX, ...): Delete macros.
1637
1638 * interp.c: Update names to match defines from sim-main.h
1639
1640Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641
1642 * interp.c (sim_monitor): Add SD argument.
1643 (sim_warning): Delete. Replace calls with calls to
1644 sim_io_eprintf.
1645 (sim_error): Delete. Replace calls with sim_io_error.
1646 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1647 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1648 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1649 argument.
1650 (mips_size): Rename from sim_size. Add SD argument.
1651
1652 * interp.c (simulator): Delete global variable.
1653 (callback): Delete global variable.
1654 (mips_option_handler, sim_open, sim_write, sim_read,
1655 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1656 sim_size,sim_monitor): Use sim_io_* not callback->*.
1657 (sim_open): ZALLOC simulator struct.
1658 (PROFILE): Do not define.
1659
1660Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1661
1662 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1663 support.h with corresponding code.
1664
1665 * sim-main.h (word64, uword64), support.h: Move definition to
1666 sim-main.h.
1667 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1668
1669 * support.h: Delete
1670 * Makefile.in: Update dependencies
1671 * interp.c: Do not include.
1672
1673Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1674
1675 * interp.c (address_translation, load_memory, store_memory,
1676 cache_op): Rename to from AddressTranslation et.al., make global,
1677 add SD argument
1678
1679 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1680 CacheOp): Define.
1681
1682 * interp.c (SignalException): Rename to signal_exception, make
1683 global.
1684
1685 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1686
1687 * sim-main.h (SignalException, SignalExceptionInterrupt,
1688 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1689 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1690 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1691 Define.
1692
1693 * interp.c, support.h: Use.
1694
1695Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1696
1697 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1698 to value_fpr / store_fpr. Add SD argument.
1699 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1700 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1701
1702 * sim-main.h (ValueFPR, StoreFPR): Define.
1703
1704Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1705
1706 * interp.c (sim_engine_run): Check consistency between configure
1707 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1708 and HASFPU.
1709
1710 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1711 (mips_fpu): Configure WITH_FLOATING_POINT.
1712 (mips_endian): Configure WITH_TARGET_ENDIAN.
1713 * configure: Update.
1714
1715Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1716
1717 * configure: Regenerated to track ../common/aclocal.m4 changes.
1718
1719Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1720
1721 * configure: Regenerated.
1722
1723Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1724
1725 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1726
1727Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1728
1729 * gencode.c (print_igen_insn_models): Assume certain architectures
1730 include all mips* instructions.
1731 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1732 instruction.
1733
1734 * Makefile.in (tmp.igen): Add target. Generate igen input from
1735 gencode file.
1736
1737 * gencode.c (FEATURE_IGEN): Define.
1738 (main): Add --igen option. Generate output in igen format.
1739 (process_instructions): Format output according to igen option.
1740 (print_igen_insn_format): New function.
1741 (print_igen_insn_models): New function.
1742 (process_instructions): Only issue warnings and ignore
1743 instructions when no FEATURE_IGEN.
1744
1745Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1746
1747 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1748 MIPS targets.
1749
1750Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1751
1752 * configure: Regenerated to track ../common/aclocal.m4 changes.
1753
1754Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1755
1756 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1757 SIM_RESERVED_BITS): Delete, moved to common.
1758 (SIM_EXTRA_CFLAGS): Update.
1759
1760Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1761
1762 * configure.in: Configure non-strict memory alignment.
1763 * configure: Regenerated to track ../common/aclocal.m4 changes.
1764
1765Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1766
1767 * configure: Regenerated to track ../common/aclocal.m4 changes.
1768
1769Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1770
1771 * gencode.c (SDBBP,DERET): Added (3900) insns.
1772 (RFE): Turn on for 3900.
1773 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1774 (dsstate): Made global.
1775 (SUBTARGET_R3900): Added.
1776 (CANCELDELAYSLOT): New.
1777 (SignalException): Ignore SystemCall rather than ignore and
1778 terminate. Add DebugBreakPoint handling.
1779 (decode_coproc): New insns RFE, DERET; and new registers Debug
1780 and DEPC protected by SUBTARGET_R3900.
1781 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1782 bits explicitly.
1783 * Makefile.in,configure.in: Add mips subtarget option.
1784 * configure: Update.
1785
1786Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1787
1788 * gencode.c: Add r3900 (tx39).
1789
1790
1791Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1792
1793 * gencode.c (build_instruction): Don't need to subtract 4 for
1794 JALR, just 2.
1795
1796Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1797
1798 * interp.c: Correct some HASFPU problems.
1799
1800Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1801
1802 * configure: Regenerated to track ../common/aclocal.m4 changes.
1803
1804Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1805
1806 * interp.c (mips_options): Fix samples option short form, should
1807 be `x'.
1808
1809Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1810
1811 * interp.c (sim_info): Enable info code. Was just returning.
1812
1813Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1814
1815 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1816 MFC0.
1817
1818Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1819
1820 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1821 constants.
1822 (build_instruction): Ditto for LL.
1823
1824Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1825
1826 * configure: Regenerated to track ../common/aclocal.m4 changes.
1827
1828Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1829
1830 * configure: Regenerated to track ../common/aclocal.m4 changes.
1831 * config.in: Ditto.
1832
1833Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1834
1835 * interp.c (sim_open): Add call to sim_analyze_program, update
1836 call to sim_config.
1837
1838Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1839
1840 * interp.c (sim_kill): Delete.
1841 (sim_create_inferior): Add ABFD argument. Set PC from same.
1842 (sim_load): Move code initializing trap handlers from here.
1843 (sim_open): To here.
1844 (sim_load): Delete, use sim-hload.c.
1845
1846 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1847
1848Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1849
1850 * configure: Regenerated to track ../common/aclocal.m4 changes.
1851 * config.in: Ditto.
1852
1853Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * interp.c (sim_open): Add ABFD argument.
1856 (sim_load): Move call to sim_config from here.
1857 (sim_open): To here. Check return status.
1858
1859Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1860
1861 * gencode.c (build_instruction): Two arg MADD should
1862 not assign result to $0.
1863
1864Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1865
1866 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1867 * sim/mips/configure.in: Regenerate.
1868
1869Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1870
1871 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1872 signed8, unsigned8 et.al. types.
1873
1874 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1875 hosts when selecting subreg.
1876
1877Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1878
1879 * interp.c (sim_engine_run): Reset the ZERO register to zero
1880 regardless of FEATURE_WARN_ZERO.
1881 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1882
1883Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1884
1885 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1886 (SignalException): For BreakPoints ignore any mode bits and just
1887 save the PC.
1888 (SignalException): Always set the CAUSE register.
1889
1890Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1891
1892 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1893 exception has been taken.
1894
1895 * interp.c: Implement the ERET and mt/f sr instructions.
1896
1897Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1898
1899 * interp.c (SignalException): Don't bother restarting an
1900 interrupt.
1901
1902Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1903
1904 * interp.c (SignalException): Really take an interrupt.
1905 (interrupt_event): Only deliver interrupts when enabled.
1906
1907Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1908
1909 * interp.c (sim_info): Only print info when verbose.
1910 (sim_info) Use sim_io_printf for output.
1911
1912Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1913
1914 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1915 mips architectures.
1916
1917Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1918
1919 * interp.c (sim_do_command): Check for common commands if a
1920 simulator specific command fails.
1921
1922Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1923
1924 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1925 and simBE when DEBUG is defined.
1926
1927Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1928
1929 * interp.c (interrupt_event): New function. Pass exception event
1930 onto exception handler.
1931
1932 * configure.in: Check for stdlib.h.
1933 * configure: Regenerate.
1934
1935 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1936 variable declaration.
1937 (build_instruction): Initialize memval1.
1938 (build_instruction): Add UNUSED attribute to byte, bigend,
1939 reverse.
1940 (build_operands): Ditto.
1941
1942 * interp.c: Fix GCC warnings.
1943 (sim_get_quit_code): Delete.
1944
1945 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1946 * Makefile.in: Ditto.
1947 * configure: Re-generate.
1948
1949 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1950
1951Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1952
1953 * interp.c (mips_option_handler): New function parse argumes using
1954 sim-options.
1955 (myname): Replace with STATE_MY_NAME.
1956 (sim_open): Delete check for host endianness - performed by
1957 sim_config.
1958 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1959 (sim_open): Move much of the initialization from here.
1960 (sim_load): To here. After the image has been loaded and
1961 endianness set.
1962 (sim_open): Move ColdReset from here.
1963 (sim_create_inferior): To here.
1964 (sim_open): Make FP check less dependant on host endianness.
1965
1966 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1967 run.
1968 * interp.c (sim_set_callbacks): Delete.
1969
1970 * interp.c (membank, membank_base, membank_size): Replace with
1971 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1972 (sim_open): Remove call to callback->init. gdb/run do this.
1973
1974 * interp.c: Update
1975
1976 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1977
1978 * interp.c (big_endian_p): Delete, replaced by
1979 current_target_byte_order.
1980
1981Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1982
1983 * interp.c (host_read_long, host_read_word, host_swap_word,
1984 host_swap_long): Delete. Using common sim-endian.
1985 (sim_fetch_register, sim_store_register): Use H2T.
1986 (pipeline_ticks): Delete. Handled by sim-events.
1987 (sim_info): Update.
1988 (sim_engine_run): Update.
1989
1990Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1991
1992 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1993 reason from here.
1994 (SignalException): To here. Signal using sim_engine_halt.
1995 (sim_stop_reason): Delete, moved to common.
1996
1997Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1998
1999 * interp.c (sim_open): Add callback argument.
2000 (sim_set_callbacks): Delete SIM_DESC argument.
2001 (sim_size): Ditto.
2002
2003Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2004
2005 * Makefile.in (SIM_OBJS): Add common modules.
2006
2007 * interp.c (sim_set_callbacks): Also set SD callback.
2008 (set_endianness, xfer_*, swap_*): Delete.
2009 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2010 Change to functions using sim-endian macros.
2011 (control_c, sim_stop): Delete, use common version.
2012 (simulate): Convert into.
2013 (sim_engine_run): This function.
2014 (sim_resume): Delete.
2015
2016 * interp.c (simulation): New variable - the simulator object.
2017 (sim_kind): Delete global - merged into simulation.
2018 (sim_load): Cleanup. Move PC assignment from here.
2019 (sim_create_inferior): To here.
2020
2021 * sim-main.h: New file.
2022 * interp.c (sim-main.h): Include.
2023
2024Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2025
2026 * configure: Regenerated to track ../common/aclocal.m4 changes.
2027
2028Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2029
2030 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2031
2032Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2033
2034 * gencode.c (build_instruction): DIV instructions: check
2035 for division by zero and integer overflow before using
2036 host's division operation.
2037
2038Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2039
2040 * Makefile.in (SIM_OBJS): Add sim-load.o.
2041 * interp.c: #include bfd.h.
2042 (target_byte_order): Delete.
2043 (sim_kind, myname, big_endian_p): New static locals.
2044 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2045 after argument parsing. Recognize -E arg, set endianness accordingly.
2046 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2047 load file into simulator. Set PC from bfd.
2048 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2049 (set_endianness): Use big_endian_p instead of target_byte_order.
2050
2051Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2052
2053 * interp.c (sim_size): Delete prototype - conflicts with
2054 definition in remote-sim.h. Correct definition.
2055
2056Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2057
2058 * configure: Regenerated to track ../common/aclocal.m4 changes.
2059 * config.in: Ditto.
2060
2061Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2062
2063 * interp.c (sim_open): New arg `kind'.
2064
2065 * configure: Regenerated to track ../common/aclocal.m4 changes.
2066
2067Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2068
2069 * configure: Regenerated to track ../common/aclocal.m4 changes.
2070
2071Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2072
2073 * interp.c (sim_open): Set optind to 0 before calling getopt.
2074
2075Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2076
2077 * configure: Regenerated to track ../common/aclocal.m4 changes.
2078
2079Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2080
2081 * interp.c : Replace uses of pr_addr with pr_uword64
2082 where the bit length is always 64 independent of SIM_ADDR.
2083 (pr_uword64) : added.
2084
2085Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2086
2087 * configure: Re-generate.
2088
2089Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2090
2091 * configure: Regenerate to track ../common/aclocal.m4 changes.
2092
2093Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2094
2095 * interp.c (sim_open): New SIM_DESC result. Argument is now
2096 in argv form.
2097 (other sim_*): New SIM_DESC argument.
2098
2099Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2100
2101 * interp.c: Fix printing of addresses for non-64-bit targets.
2102 (pr_addr): Add function to print address based on size.
2103
2104Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2105
2106 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2107
2108Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2109
2110 * gencode.c (build_mips16_operands): Correct computation of base
2111 address for extended PC relative instruction.
2112
2113Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2114
2115 * interp.c (mips16_entry): Add support for floating point cases.
2116 (SignalException): Pass floating point cases to mips16_entry.
2117 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2118 registers.
2119 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2120 or fmt_word.
2121 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2122 and then set the state to fmt_uninterpreted.
2123 (COP_SW): Temporarily set the state to fmt_word while calling
2124 ValueFPR.
2125
2126Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2127
2128 * gencode.c (build_instruction): The high order may be set in the
2129 comparison flags at any ISA level, not just ISA 4.
2130
2131Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2132
2133 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2134 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2135 * configure.in: sinclude ../common/aclocal.m4.
2136 * configure: Regenerated.
2137
2138Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2139
2140 * configure: Rebuild after change to aclocal.m4.
2141
2142Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2143
2144 * configure configure.in Makefile.in: Update to new configure
2145 scheme which is more compatible with WinGDB builds.
2146 * configure.in: Improve comment on how to run autoconf.
2147 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2148 * Makefile.in: Use autoconf substitution to install common
2149 makefile fragment.
2150
2151Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2152
2153 * gencode.c (build_instruction): Use BigEndianCPU instead of
2154 ByteSwapMem.
2155
2156Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2157
2158 * interp.c (sim_monitor): Make output to stdout visible in
2159 wingdb's I/O log window.
2160
2161Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2162
2163 * support.h: Undo previous change to SIGTRAP
2164 and SIGQUIT values.
2165
2166Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2167
2168 * interp.c (store_word, load_word): New static functions.
2169 (mips16_entry): New static function.
2170 (SignalException): Look for mips16 entry and exit instructions.
2171 (simulate): Use the correct index when setting fpr_state after
2172 doing a pending move.
2173
2174Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2175
2176 * interp.c: Fix byte-swapping code throughout to work on
2177 both little- and big-endian hosts.
2178
2179Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2180
2181 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2182 with gdb/config/i386/xm-windows.h.
2183
2184Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2185
2186 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2187 that messes up arithmetic shifts.
2188
2189Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2190
2191 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2192 SIGTRAP and SIGQUIT for _WIN32.
2193
2194Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2195
2196 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2197 force a 64 bit multiplication.
2198 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2199 destination register is 0, since that is the default mips16 nop
2200 instruction.
2201
2202Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2203
2204 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2205 (build_endian_shift): Don't check proc64.
2206 (build_instruction): Always set memval to uword64. Cast op2 to
2207 uword64 when shifting it left in memory instructions. Always use
2208 the same code for stores--don't special case proc64.
2209
2210 * gencode.c (build_mips16_operands): Fix base PC value for PC
2211 relative operands.
2212 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2213 jal instruction.
2214 * interp.c (simJALDELAYSLOT): Define.
2215 (JALDELAYSLOT): Define.
2216 (INDELAYSLOT, INJALDELAYSLOT): Define.
2217 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2218
2219Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2220
2221 * interp.c (sim_open): add flush_cache as a PMON routine
2222 (sim_monitor): handle flush_cache by ignoring it
2223
2224Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2225
2226 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2227 BigEndianMem.
2228 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2229 (BigEndianMem): Rename to ByteSwapMem and change sense.
2230 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2231 BigEndianMem references to !ByteSwapMem.
2232 (set_endianness): New function, with prototype.
2233 (sim_open): Call set_endianness.
2234 (sim_info): Use simBE instead of BigEndianMem.
2235 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2236 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2237 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2238 ifdefs, keeping the prototype declaration.
2239 (swap_word): Rewrite correctly.
2240 (ColdReset): Delete references to CONFIG. Delete endianness related
2241 code; moved to set_endianness.
2242
2243Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2244
2245 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2246 * interp.c (CHECKHILO): Define away.
2247 (simSIGINT): New macro.
2248 (membank_size): Increase from 1MB to 2MB.
2249 (control_c): New function.
2250 (sim_resume): Rename parameter signal to signal_number. Add local
2251 variable prev. Call signal before and after simulate.
2252 (sim_stop_reason): Add simSIGINT support.
2253 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2254 functions always.
2255 (sim_warning): Delete call to SignalException. Do call printf_filtered
2256 if logfh is NULL.
2257 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2258 a call to sim_warning.
2259
2260Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2261
2262 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2263 16 bit instructions.
2264
2265Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2266
2267 Add support for mips16 (16 bit MIPS implementation):
2268 * gencode.c (inst_type): Add mips16 instruction encoding types.
2269 (GETDATASIZEINSN): Define.
2270 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2271 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2272 mtlo.
2273 (MIPS16_DECODE): New table, for mips16 instructions.
2274 (bitmap_val): New static function.
2275 (struct mips16_op): Define.
2276 (mips16_op_table): New table, for mips16 operands.
2277 (build_mips16_operands): New static function.
2278 (process_instructions): If PC is odd, decode a mips16
2279 instruction. Break out instruction handling into new
2280 build_instruction function.
2281 (build_instruction): New static function, broken out of
2282 process_instructions. Check modifiers rather than flags for SHIFT
2283 bit count and m[ft]{hi,lo} direction.
2284 (usage): Pass program name to fprintf.
2285 (main): Remove unused variable this_option_optind. Change
2286 ``*loptarg++'' to ``loptarg++''.
2287 (my_strtoul): Parenthesize && within ||.
2288 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2289 (simulate): If PC is odd, fetch a 16 bit instruction, and
2290 increment PC by 2 rather than 4.
2291 * configure.in: Add case for mips16*-*-*.
2292 * configure: Rebuild.
2293
2294Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2295
2296 * interp.c: Allow -t to enable tracing in standalone simulator.
2297 Fix garbage output in trace file and error messages.
2298
2299Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2300
2301 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2302 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2303 * configure.in: Simplify using macros in ../common/aclocal.m4.
2304 * configure: Regenerated.
2305 * tconfig.in: New file.
2306
2307Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2308
2309 * interp.c: Fix bugs in 64-bit port.
2310 Use ansi function declarations for msvc compiler.
2311 Initialize and test file pointer in trace code.
2312 Prevent duplicate definition of LAST_EMED_REGNUM.
2313
2314Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2315
2316 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2317
2318Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2319
2320 * interp.c (SignalException): Check for explicit terminating
2321 breakpoint value.
2322 * gencode.c: Pass instruction value through SignalException()
2323 calls for Trap, Breakpoint and Syscall.
2324
2325Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2326
2327 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2328 only used on those hosts that provide it.
2329 * configure.in: Add sqrt() to list of functions to be checked for.
2330 * config.in: Re-generated.
2331 * configure: Re-generated.
2332
2333Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2334
2335 * gencode.c (process_instructions): Call build_endian_shift when
2336 expanding STORE RIGHT, to fix swr.
2337 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2338 clear the high bits.
2339 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2340 Fix float to int conversions to produce signed values.
2341
2342Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2343
2344 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2345 (process_instructions): Correct handling of nor instruction.
2346 Correct shift count for 32 bit shift instructions. Correct sign
2347 extension for arithmetic shifts to not shift the number of bits in
2348 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2349 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2350 Fix madd.
2351 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2352 It's OK to have a mult follow a mult. What's not OK is to have a
2353 mult follow an mfhi.
2354 (Convert): Comment out incorrect rounding code.
2355
2356Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2357
2358 * interp.c (sim_monitor): Improved monitor printf
2359 simulation. Tidied up simulator warnings, and added "--log" option
2360 for directing warning message output.
2361 * gencode.c: Use sim_warning() rather than WARNING macro.
2362
2363Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2364
2365 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2366 getopt1.o, rather than on gencode.c. Link objects together.
2367 Don't link against -liberty.
2368 (gencode.o, getopt.o, getopt1.o): New targets.
2369 * gencode.c: Include <ctype.h> and "ansidecl.h".
2370 (AND): Undefine after including "ansidecl.h".
2371 (ULONG_MAX): Define if not defined.
2372 (OP_*): Don't define macros; now defined in opcode/mips.h.
2373 (main): Call my_strtoul rather than strtoul.
2374 (my_strtoul): New static function.
2375
2376Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2377
2378 * gencode.c (process_instructions): Generate word64 and uword64
2379 instead of `long long' and `unsigned long long' data types.
2380 * interp.c: #include sysdep.h to get signals, and define default
2381 for SIGBUS.
2382 * (Convert): Work around for Visual-C++ compiler bug with type
2383 conversion.
2384 * support.h: Make things compile under Visual-C++ by using
2385 __int64 instead of `long long'. Change many refs to long long
2386 into word64/uword64 typedefs.
2387
2388Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2389
2390 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2391 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2392 (docdir): Removed.
2393 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2394 (AC_PROG_INSTALL): Added.
2395 (AC_PROG_CC): Moved to before configure.host call.
2396 * configure: Rebuilt.
2397
2398Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2399
2400 * configure.in: Define @SIMCONF@ depending on mips target.
2401 * configure: Rebuild.
2402 * Makefile.in (run): Add @SIMCONF@ to control simulator
2403 construction.
2404 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2405 * interp.c: Remove some debugging, provide more detailed error
2406 messages, update memory accesses to use LOADDRMASK.
2407
2408Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2409
2410 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2411 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2412 stamp-h.
2413 * configure: Rebuild.
2414 * config.in: New file, generated by autoheader.
2415 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2416 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2417 HAVE_ANINT and HAVE_AINT, as appropriate.
2418 * Makefile.in (run): Use @LIBS@ rather than -lm.
2419 (interp.o): Depend upon config.h.
2420 (Makefile): Just rebuild Makefile.
2421 (clean): Remove stamp-h.
2422 (mostlyclean): Make the same as clean, not as distclean.
2423 (config.h, stamp-h): New targets.
2424
2425Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2426
2427 * interp.c (ColdReset): Fix boolean test. Make all simulator
2428 globals static.
2429
2430Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2431
2432 * interp.c (xfer_direct_word, xfer_direct_long,
2433 swap_direct_word, swap_direct_long, xfer_big_word,
2434 xfer_big_long, xfer_little_word, xfer_little_long,
2435 swap_word,swap_long): Added.
2436 * interp.c (ColdReset): Provide function indirection to
2437 host<->simulated_target transfer routines.
2438 * interp.c (sim_store_register, sim_fetch_register): Updated to
2439 make use of indirected transfer routines.
2440
2441Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2442
2443 * gencode.c (process_instructions): Ensure FP ABS instruction
2444 recognised.
2445 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2446 system call support.
2447
2448Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2449
2450 * interp.c (sim_do_command): Complain if callback structure not
2451 initialised.
2452
2453Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2454
2455 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2456 support for Sun hosts.
2457 * Makefile.in (gencode): Ensure the host compiler and libraries
2458 used for cross-hosted build.
2459
2460Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2461
2462 * interp.c, gencode.c: Some more (TODO) tidying.
2463
2464Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2465
2466 * gencode.c, interp.c: Replaced explicit long long references with
2467 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2468 * support.h (SET64LO, SET64HI): Macros added.
2469
2470Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2471
2472 * configure: Regenerate with autoconf 2.7.
2473
2474Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2475
2476 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2477 * support.h: Remove superfluous "1" from #if.
2478 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2479
2480Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2481
2482 * interp.c (StoreFPR): Control UndefinedResult() call on
2483 WARN_RESULT manifest.
2484
2485Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2486
2487 * gencode.c: Tidied instruction decoding, and added FP instruction
2488 support.
2489
2490 * interp.c: Added dineroIII, and BSD profiling support. Also
2491 run-time FP handling.
2492
2493Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2494
2495 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2496 gencode.c, interp.c, support.h: created.
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