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Power10 string operations
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
66ef5847
AM		 12020-05-11 Alan Modra <amodra@gmail.com>
2
3 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
4 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
5
4f3e9537
PB		 62020-05-11 Peter Bergner <bergner@linux.ibm.com>
7
8 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
9 mnemonics.
10
ec40e91c
AM		 112020-05-11 Alan Modra <amodra@gmail.com>
12
13 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
14 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
15 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
16 (prefix_opcodes): Add xxeval.
17
d7e97a76
AM		 182020-05-11 Alan Modra <amodra@gmail.com>
19
20 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
21 xxgenpcvwm, xxgenpcvdm.
22
fdefed7c
AM		 232020-05-11 Alan Modra <amodra@gmail.com>
24
25 * ppc-opc.c (MP, VXVAM_MASK): Define.
26 (VXVAPS_MASK): Use VXVA_MASK.
27 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
28 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
29 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
30 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
31
aa3c112f
AM		 322020-05-11 Alan Modra <amodra@gmail.com>
33 Peter Bergner <bergner@linux.ibm.com>
34
35 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
36 New functions.
37 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
38 YMSK2, XA6a, XA6ap, XB6a entries.
39 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
40 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
41 (PPCVSX4): Define.
42 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
43 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
44 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
45 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
46 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
47 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
48 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
49 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
50 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
51 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
52 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
53 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
54 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
55 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
56
6edbfd3b
AM		 572020-05-11 Alan Modra <amodra@gmail.com>
58
59 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
60 (insert_xts, extract_xts): New functions.
61 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
62 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
63 (VXRC_MASK, VXSH_MASK): Define.
64 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
65 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
66 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
67 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
68 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
69 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
70 xxblendvh, xxblendvw, xxblendvd, xxpermx.
71
c7d7aea2
AM		 722020-05-11 Alan Modra <amodra@gmail.com>
73
74 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
75 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
76 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
77 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
78 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
79
94ba9882
AM		 802020-05-11 Alan Modra <amodra@gmail.com>
81
82 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
83 (XTP, DQXP, DQXP_MASK): Define.
84 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
85 (prefix_opcodes): Add plxvp and pstxvp.
86
f4791f1a
AM		 872020-05-11 Alan Modra <amodra@gmail.com>
88
89 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
90 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
91 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
92
3ff0a5ba
PB		 932020-05-11 Peter Bergner <bergner@linux.ibm.com>
94
95 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
96
afef4fe9
PB		 972020-05-11 Peter Bergner <bergner@linux.ibm.com>
98
99 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
100 (L1OPT): Define.
101 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
102
1224c05d
PB		 1032020-05-11 Peter Bergner <bergner@linux.ibm.com>
104
105 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
106
6bbb0c05
AM		 1072020-05-11 Alan Modra <amodra@gmail.com>
108
109 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
110
7c1f4227
AM		 1112020-05-11 Alan Modra <amodra@gmail.com>
112
113 * ppc-dis.c (ppc_opts): Add "power10" entry.
114 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
115 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
116
73199c2b
NC		 1172020-05-11 Nick Clifton <nickc@redhat.com>
118
119 * po/fr.po: Updated French translation.
120
09c1e68a
AC		 1212020-04-30 Alex Coplan <alex.coplan@arm.com>
122
123 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
124 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
125 (operand_general_constraint_met_p): validate
126 AARCH64_OPND_UNDEFINED.
127 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
128 for FLD_imm16_2.
129 * aarch64-asm-2.c: Regenerated.
130 * aarch64-dis-2.c: Regenerated.
131 * aarch64-opc-2.c: Regenerated.
132
9654d51a
NC		 1332020-04-29 Nick Clifton <nickc@redhat.com>
134
135 PR 22699
136 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
137 and SETRC insns.
138
c2e71e57
NC		 1392020-04-29 Nick Clifton <nickc@redhat.com>
140
141 * po/sv.po: Updated Swedish translation.
142
5c936ef5
NC		 1432020-04-29 Nick Clifton <nickc@redhat.com>
144
145 PR 22699
146 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
147 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
148 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
149 IMM0_8U case.
150
bb2a1453
AS		 1512020-04-21 Andreas Schwab <schwab@linux-m68k.org>
152
153 PR 25848
154 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
155 cmpi only on m68020up and cpu32.
156
c2e5c986
SD		 1572020-04-20 Sudakshina Das <sudi.das@arm.com>
158
159 * aarch64-asm.c (aarch64_ins_none): New.
160 * aarch64-asm.h (ins_none): New declaration.
161 * aarch64-dis.c (aarch64_ext_none): New.
162 * aarch64-dis.h (ext_none): New declaration.
163 * aarch64-opc.c (aarch64_print_operand): Update case for
164 AARCH64_OPND_BARRIER_PSB.
165 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
166 (AARCH64_OPERANDS): Update inserter/extracter for
167 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
168 * aarch64-asm-2.c: Regenerated.
169 * aarch64-dis-2.c: Regenerated.
170 * aarch64-opc-2.c: Regenerated.
171
8a6e1d1d
SD		 1722020-04-20 Sudakshina Das <sudi.das@arm.com>
173
174 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
175 (aarch64_feature_ras, RAS): Likewise.
176 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
177 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
178 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
179 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
180 * aarch64-asm-2.c: Regenerated.
181 * aarch64-dis-2.c: Regenerated.
182 * aarch64-opc-2.c: Regenerated.
183
e409955d
FS		 1842020-04-17 Fredrik Strupe <fredrik@strupe.net>
185
186 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
187 (print_insn_neon): Support disassembly of conditional
188 instructions.
189
c54a9b56
DF		 1902020-02-16 David Faust <david.faust@oracle.com>
191
192 * bpf-desc.c: Regenerate.
193 * bpf-desc.h: Likewise.
194 * bpf-opc.c: Regenerate.
195 * bpf-opc.h: Likewise.
196
bb651e8b
CL		 1972020-04-07 Lili Cui <lili.cui@intel.com>
198
199 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
200 (prefix_table): New instructions (see prefixes above).
201 (rm_table): Likewise
202 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
203 CPU_ANY_TSXLDTRK_FLAGS.
204 (cpu_flags): Add CpuTSXLDTRK.
205 * i386-opc.h (enum): Add CpuTSXLDTRK.
206 (i386_cpu_flags): Add cputsxldtrk.
207 * i386-opc.tbl: Add XSUSPLDTRK insns.
208 * i386-init.h: Regenerate.
209 * i386-tbl.h: Likewise.
210
4b27d27c
L		 2112020-04-02 Lili Cui <lili.cui@intel.com>
212
213 * i386-dis.c (prefix_table): New instructions serialize.
214 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
215 CPU_ANY_SERIALIZE_FLAGS.
216 (cpu_flags): Add CpuSERIALIZE.
217 * i386-opc.h (enum): Add CpuSERIALIZE.
218 (i386_cpu_flags): Add cpuserialize.
219 * i386-opc.tbl: Add SERIALIZE insns.
220 * i386-init.h: Regenerate.
221 * i386-tbl.h: Likewise.
222
832a5807
AM		 2232020-03-26 Alan Modra <amodra@gmail.com>
224
225 * disassemble.h (opcodes_assert): Declare.
226 (OPCODES_ASSERT): Define.
227 * disassemble.c: Don't include assert.h. Include opintl.h.
228 (opcodes_assert): New function.
229 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
230 (bfd_h8_disassemble): Reduce size of data array. Correctly
231 calculate maxlen. Omit insn decoding when insn length exceeds
232 maxlen. Exit from nibble loop when looking for E, before
233 accessing next data byte. Move processing of E outside loop.
234 Replace tests of maxlen in loop with assertions.
235
4c4addbe
AM		 2362020-03-26 Alan Modra <amodra@gmail.com>
237
238 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
239
a18cd0ca
AM		 2402020-03-25 Alan Modra <amodra@gmail.com>
241
242 * z80-dis.c (suffix): Init mybuf.
243
57cb32b3
AM		 2442020-03-22 Alan Modra <amodra@gmail.com>
245
246 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
247 successflly read from section.
248
beea5cc1
AM		 2492020-03-22 Alan Modra <amodra@gmail.com>
250
251 * arc-dis.c (find_format): Use ISO C string concatenation rather
252 than line continuation within a string. Don't access needs_limm
253 before testing opcode != NULL.
254
03704c77
AM		 2552020-03-22 Alan Modra <amodra@gmail.com>
256
257 * ns32k-dis.c (print_insn_arg): Update comment.
258 (print_insn_ns32k): Reduce size of index_offset array, and
259 initialize, passing -1 to print_insn_arg for args that are not
260 an index. Don't exit arg loop early. Abort on bad arg number.
261
d1023b5d
AM		 2622020-03-22 Alan Modra <amodra@gmail.com>
263
264 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
265 * s12z-opc.c: Formatting.
266 (operands_f): Return an int.
267 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
268 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
269 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
270 (exg_sex_discrim): Likewise.
271 (create_immediate_operand, create_bitfield_operand),
272 (create_register_operand_with_size, create_register_all_operand),
273 (create_register_all16_operand, create_simple_memory_operand),
274 (create_memory_operand, create_memory_auto_operand): Don't
275 segfault on malloc failure.
276 (z_ext24_decode): Return an int status, negative on fail, zero
277 on success.
278 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
279 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
280 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
281 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
282 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
283 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
284 (loop_primitive_decode, shift_decode, psh_pul_decode),
285 (bit_field_decode): Similarly.
286 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
287 to return value, update callers.
288 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
289 Don't segfault on NULL operand.
290 (decode_operation): Return OP_INVALID on first fail.
291 (decode_s12z): Check all reads, returning -1 on fail.
292
340f3ac8
AM		 2932020-03-20 Alan Modra <amodra@gmail.com>
294
295 * metag-dis.c (print_insn_metag): Don't ignore status from
296 read_memory_func.
297
fe90ae8a
AM		 2982020-03-20 Alan Modra <amodra@gmail.com>
299
300 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
301 Initialize parts of buffer not written when handling a possible
302 2-byte insn at end of section. Don't attempt decoding of such
303 an insn by the 4-byte machinery.
304
833d919c
AM		 3052020-03-20 Alan Modra <amodra@gmail.com>
306
307 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
308 partially filled buffer. Prevent lookup of 4-byte insns when
309 only VLE 2-byte insns are possible due to section size. Print
310 ".word" rather than ".long" for 2-byte leftovers.
311
327ef784
NC		 3122020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
313
314 PR 25641
315 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
316
1673df32
JB		 3172020-03-13 Jan Beulich <jbeulich@suse.com>
318
319 * i386-dis.c (X86_64_0D): Rename to ...
320 (X86_64_0E): ... this.
321
384f3689
L		 3222020-03-09 H.J. Lu <hongjiu.lu@intel.com>
323
324 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
325 * Makefile.in: Regenerated.
326
865e2027
JB		 3272020-03-09 Jan Beulich <jbeulich@suse.com>
328
329 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
330 3-operand pseudos.
331 * i386-tbl.h: Re-generate.
332
2f13234b
JB		 3332020-03-09 Jan Beulich <jbeulich@suse.com>
334
335 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
336 vprot*, vpsha*, and vpshl*.
337 * i386-tbl.h: Re-generate.
338
3fabc179
JB		 3392020-03-09 Jan Beulich <jbeulich@suse.com>
340
341 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
342 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
343 * i386-tbl.h: Re-generate.
344
3677e4c1
JB		 3452020-03-09 Jan Beulich <jbeulich@suse.com>
346
347 * i386-gen.c (set_bitfield): Ignore zero-length field names.
348 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
349 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
350 * i386-tbl.h: Re-generate.
351
4c4898e8
JB		 3522020-03-09 Jan Beulich <jbeulich@suse.com>
353
354 * i386-gen.c (struct template_arg, struct template_instance,
355 struct template_param, struct template, templates,
356 parse_template, expand_templates): New.
357 (process_i386_opcodes): Various local variables moved to
358 expand_templates. Call parse_template and expand_templates.
359 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
360 * i386-tbl.h: Re-generate.
361
bc49bfd8
JB		 3622020-03-06 Jan Beulich <jbeulich@suse.com>
363
364 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
365 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
366 register and memory source templates. Replace VexW= by VexW*
367 where applicable.
368 * i386-tbl.h: Re-generate.
369
4873e243
JB		 3702020-03-06 Jan Beulich <jbeulich@suse.com>
371
372 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
373 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
374 * i386-tbl.h: Re-generate.
375
672a349b
JB		 3762020-03-06 Jan Beulich <jbeulich@suse.com>
377
378 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
379 * i386-tbl.h: Re-generate.
380
4ed21b58
JB		 3812020-03-06 Jan Beulich <jbeulich@suse.com>
382
383 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
384 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
385 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
386 VexW0 on SSE2AVX variants.
387 (vmovq): Drop NoRex64 from XMM/XMM variants.
388 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
389 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
390 applicable use VexW0.
391 * i386-tbl.h: Re-generate.
392
643bb870
JB		 3932020-03-06 Jan Beulich <jbeulich@suse.com>
394
395 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
396 * i386-opc.h (Rex64): Delete.
397 (struct i386_opcode_modifier): Remove rex64 field.
398 * i386-opc.tbl (crc32): Drop Rex64.
399 Replace Rex64 with Size64 everywhere else.
400 * i386-tbl.h: Re-generate.
401
a23b33b3
JB		 4022020-03-06 Jan Beulich <jbeulich@suse.com>
403
404 * i386-dis.c (OP_E_memory): Exclude recording of used address
405 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
406 addressed memory operands for MPX insns.
407
a0497384
JB		 4082020-03-06 Jan Beulich <jbeulich@suse.com>
409
410 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
411 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
412 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
413 (ptwrite): Split into non-64-bit and 64-bit forms.
414 * i386-tbl.h: Re-generate.
415
b630c145
JB		 4162020-03-06 Jan Beulich <jbeulich@suse.com>
417
418 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
419 template.
420 * i386-tbl.h: Re-generate.
421
a847e322
JB		 4222020-03-04 Jan Beulich <jbeulich@suse.com>
423
424 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
425 (prefix_table): Move vmmcall here. Add vmgexit.
426 (rm_table): Replace vmmcall entry by prefix_table[] escape.
427 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
428 (cpu_flags): Add CpuSEV_ES entry.
429 * i386-opc.h (CpuSEV_ES): New.
430 (union i386_cpu_flags): Add cpusev_es field.
431 * i386-opc.tbl (vmgexit): New.
432 * i386-init.h, i386-tbl.h: Re-generate.
433
3cd7f3e3
L		 4342020-03-03 H.J. Lu <hongjiu.lu@intel.com>
435
436 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
437 with MnemonicSize.
438 * i386-opc.h (IGNORESIZE): New.
439 (DEFAULTSIZE): Likewise.
440 (IgnoreSize): Removed.
441 (DefaultSize): Likewise.
442 (MnemonicSize): New.
443 (i386_opcode_modifier): Replace ignoresize/defaultsize with
444 mnemonicsize.
445 * i386-opc.tbl (IgnoreSize): New.
446 (DefaultSize): Likewise.
447 * i386-tbl.h: Regenerated.
448
b8ba1385
SB		 4492020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
450
451 PR 25627
452 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
453 instructions.
454
10d97a0f
L		 4552020-03-03 H.J. Lu <hongjiu.lu@intel.com>
456
457 PR gas/25622
458 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
459 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
460 * i386-tbl.h: Regenerated.
461
dc1e8a47
AM		 4622020-02-26 Alan Modra <amodra@gmail.com>
463
464 * aarch64-asm.c: Indent labels correctly.
465 * aarch64-dis.c: Likewise.
466 * aarch64-gen.c: Likewise.
467 * aarch64-opc.c: Likewise.
468 * alpha-dis.c: Likewise.
469 * i386-dis.c: Likewise.
470 * nds32-asm.c: Likewise.
471 * nfp-dis.c: Likewise.
472 * visium-dis.c: Likewise.
473
265b4673
CZ		 4742020-02-25 Claudiu Zissulescu <claziss@gmail.com>
475
476 * arc-regs.h (int_vector_base): Make it available for all ARC
477 CPUs.
478
bd0cf5a6
NC		 4792020-02-20 Nelson Chu <nelson.chu@sifive.com>
480
481 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
482 changed.
483
fa164239
JW		 4842020-02-19 Nelson Chu <nelson.chu@sifive.com>
485
486 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
487 c.mv/c.li if rs1 is zero.
488
272a84b1
L		 4892020-02-17 H.J. Lu <hongjiu.lu@intel.com>
490
491 * i386-gen.c (cpu_flag_init): Replace CpuABM with
492 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
493 CPU_POPCNT_FLAGS.
494 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
495 * i386-opc.h (CpuABM): Removed.
496 (CpuPOPCNT): New.
497 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
498 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
499 popcnt. Remove CpuABM from lzcnt.
500 * i386-init.h: Regenerated.
501 * i386-tbl.h: Likewise.
502
1f730c46
JB		 5032020-02-17 Jan Beulich <jbeulich@suse.com>
504
505 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
506 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
507 VexW1 instead of open-coding them.
508 * i386-tbl.h: Re-generate.
509
c8f8eebc
JB		 5102020-02-17 Jan Beulich <jbeulich@suse.com>
511
512 * i386-opc.tbl (AddrPrefixOpReg): Define.
513 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
514 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
515 templates. Drop NoRex64.
516 * i386-tbl.h: Re-generate.
517
b9915cbc
JB		 5182020-02-17 Jan Beulich <jbeulich@suse.com>
519
520 PR gas/6518
521 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
522 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
523 into Intel syntax instance (with Unpsecified) and AT&T one
524 (without).
525 (vcvtneps2bf16): Likewise, along with folding the two so far
526 separate ones.
527 * i386-tbl.h: Re-generate.
528
ce504911
L		 5292020-02-16 H.J. Lu <hongjiu.lu@intel.com>
530
531 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
532 CPU_ANY_SSE4A_FLAGS.
533
dabec65d
AM		 5342020-02-17 Alan Modra <amodra@gmail.com>
535
536 * i386-gen.c (cpu_flag_init): Correct last change.
537
af5c13b0
L		 5382020-02-16 H.J. Lu <hongjiu.lu@intel.com>
539
540 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
541 CPU_ANY_SSE4_FLAGS.
542
6867aac0
L		 5432020-02-14 H.J. Lu <hongjiu.lu@intel.com>
544
545 * i386-opc.tbl (movsx): Remove Intel syntax comments.
546 (movzx): Likewise.
547
65fca059
JB		 5482020-02-14 Jan Beulich <jbeulich@suse.com>
549
550 PR gas/25438
551 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
552 destination for Cpu64-only variant.
553 (movzx): Fold patterns.
554 * i386-tbl.h: Re-generate.
555
7deea9aa
JB		 5562020-02-13 Jan Beulich <jbeulich@suse.com>
557
558 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
559 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
560 CPU_ANY_SSE4_FLAGS entry.
561 * i386-init.h: Re-generate.
562
6c0946d0
JB		 5632020-02-12 Jan Beulich <jbeulich@suse.com>
564
565 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
566 with Unspecified, making the present one AT&T syntax only.
567 * i386-tbl.h: Re-generate.
568
ddb56fe6
JB		 5692020-02-12 Jan Beulich <jbeulich@suse.com>
570
571 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
572 * i386-tbl.h: Re-generate.
573
5990e377
JB		 5742020-02-12 Jan Beulich <jbeulich@suse.com>
575
576 PR gas/24546
577 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
578 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
579 Amd64 and Intel64 templates.
580 (call, jmp): Likewise for far indirect variants. Dro
581 Unspecified.
582 * i386-tbl.h: Re-generate.
583
50128d0c
JB		 5842020-02-11 Jan Beulich <jbeulich@suse.com>
585
586 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
587 * i386-opc.h (ShortForm): Delete.
588 (struct i386_opcode_modifier): Remove shortform field.
589 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
590 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
591 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
592 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
593 Drop ShortForm.
594 * i386-tbl.h: Re-generate.
595
1e05b5c4
JB		 5962020-02-11 Jan Beulich <jbeulich@suse.com>
597
598 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
599 fucompi): Drop ShortForm from operand-less templates.
600 * i386-tbl.h: Re-generate.
601
2f5dd314
AM		 6022020-02-11 Alan Modra <amodra@gmail.com>
603
604 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
605 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
606 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
607 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
608 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
609
5aae9ae9
MM		 6102020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
611
612 * arm-dis.c (print_insn_cde): Define 'V' parse character.
613 (cde_opcodes): Add VCX* instructions.
614
4934a27c
MM		 6152020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
616 Matthew Malcomson <matthew.malcomson@arm.com>
617
618 * arm-dis.c (struct cdeopcode32): New.
619 (CDE_OPCODE): New macro.
620 (cde_opcodes): New disassembly table.
621 (regnames): New option to table.
622 (cde_coprocs): New global variable.
623 (print_insn_cde): New
624 (print_insn_thumb32): Use print_insn_cde.
625 (parse_arm_disassembler_options): Parse coprocN args.
626
4b5aaf5f
L		 6272020-02-10 H.J. Lu <hongjiu.lu@intel.com>
628
629 PR gas/25516
630 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
631 with ISA64.
632 * i386-opc.h (AMD64): Removed.
633 (Intel64): Likewose.
634 (AMD64): New.
635 (INTEL64): Likewise.
636 (INTEL64ONLY): Likewise.
637 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
638 * i386-opc.tbl (Amd64): New.
639 (Intel64): Likewise.
640 (Intel64Only): Likewise.
641 Replace AMD64 with Amd64. Update sysenter/sysenter with
642 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
643 * i386-tbl.h: Regenerated.
644
9fc0b501
SB		 6452020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
646
647 PR 25469
648 * z80-dis.c: Add support for GBZ80 opcodes.
649
c5d7be0c
AM		 6502020-02-04 Alan Modra <amodra@gmail.com>
651
652 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
653
44e4546f
AM		 6542020-02-03 Alan Modra <amodra@gmail.com>
655
656 * m32c-ibld.c: Regenerate.
657
b2b1453a
AM		 6582020-02-01 Alan Modra <amodra@gmail.com>
659
660 * frv-ibld.c: Regenerate.
661
4102be5c
JB		 6622020-01-31 Jan Beulich <jbeulich@suse.com>
663
664 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
665 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
666 (OP_E_memory): Replace xmm_mdq_mode case label by
667 vex_scalar_w_dq_mode one.
668 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
669
825bd36c
JB		 6702020-01-31 Jan Beulich <jbeulich@suse.com>
671
672 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
673 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
674 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
675 (intel_operand_size): Drop vex_w_dq_mode case label.
676
c3036ed0
RS		 6772020-01-31 Richard Sandiford <richard.sandiford@arm.com>
678
679 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
680 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
681
0c115f84
AM		 6822020-01-30 Alan Modra <amodra@gmail.com>
683
684 * m32c-ibld.c: Regenerate.
685
bd434cc4
JM		 6862020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
687
688 * bpf-opc.c: Regenerate.
689
aeab2b26
JB		 6902020-01-30 Jan Beulich <jbeulich@suse.com>
691
692 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
693 (dis386): Use them to replace C2/C3 table entries.
694 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
695 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
696 ones. Use Size64 instead of DefaultSize on Intel64 ones.
697 * i386-tbl.h: Re-generate.
698
62b3f548
JB		 6992020-01-30 Jan Beulich <jbeulich@suse.com>
700
701 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
702 forms.
703 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
704 DefaultSize.
705 * i386-tbl.h: Re-generate.
706
1bd8ae10
AM		 7072020-01-30 Alan Modra <amodra@gmail.com>
708
709 * tic4x-dis.c (tic4x_dp): Make unsigned.
710
bc31405e
L		 7112020-01-27 H.J. Lu <hongjiu.lu@intel.com>
712 Jan Beulich <jbeulich@suse.com>
713
714 PR binutils/25445
715 * i386-dis.c (MOVSXD_Fixup): New function.
716 (movsxd_mode): New enum.
717 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
718 (intel_operand_size): Handle movsxd_mode.
719 (OP_E_register): Likewise.
720 (OP_G): Likewise.
721 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
722 register on movsxd. Add movsxd with 16-bit destination register
723 for AMD64 and Intel64 ISAs.
724 * i386-tbl.h: Regenerated.
725
7568c93b
TC		 7262020-01-27 Tamar Christina <tamar.christina@arm.com>
727
728 PR 25403
729 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
730 * aarch64-asm-2.c: Regenerate
731 * aarch64-dis-2.c: Likewise.
732 * aarch64-opc-2.c: Likewise.
733
c006a730
JB		 7342020-01-21 Jan Beulich <jbeulich@suse.com>
735
736 * i386-opc.tbl (sysret): Drop DefaultSize.
737 * i386-tbl.h: Re-generate.
738
c906a69a
JB		 7392020-01-21 Jan Beulich <jbeulich@suse.com>
740
741 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
742 Dword.
743 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
744 * i386-tbl.h: Re-generate.
745
26916852
NC		 7462020-01-20 Nick Clifton <nickc@redhat.com>
747
748 * po/de.po: Updated German translation.
749 * po/pt_BR.po: Updated Brazilian Portuguese translation.
750 * po/uk.po: Updated Ukranian translation.
751
4d6cbb64
AM		 7522020-01-20 Alan Modra <amodra@gmail.com>
753
754 * hppa-dis.c (fput_const): Remove useless cast.
755
2bddb71a
AM		 7562020-01-20 Alan Modra <amodra@gmail.com>
757
758 * arm-dis.c (print_insn_arm): Wrap 'T' value.
759
1b1bb2c6
NC		 7602020-01-18 Nick Clifton <nickc@redhat.com>
761
762 * configure: Regenerate.
763 * po/opcodes.pot: Regenerate.
764
ae774686
NC		 7652020-01-18 Nick Clifton <nickc@redhat.com>
766
767 Binutils 2.34 branch created.
768
07f1f3aa
CB		 7692020-01-17 Christian Biesinger <cbiesinger@google.com>
770
771 * opintl.h: Fix spelling error (seperate).
772
42e04b36
L		 7732020-01-17 H.J. Lu <hongjiu.lu@intel.com>
774
775 * i386-opc.tbl: Add {vex} pseudo prefix.
776 * i386-tbl.h: Regenerated.
777
2da2eaf4
AV		 7782020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
779
780 PR 25376
781 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
782 (neon_opcodes): Likewise.
783 (select_arm_features): Make sure we enable MVE bits when selecting
784 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
785 any architecture.
786
d0849eed
JB		 7872020-01-16 Jan Beulich <jbeulich@suse.com>
788
789 * i386-opc.tbl: Drop stale comment from XOP section.
790
9cf70a44
JB		 7912020-01-16 Jan Beulich <jbeulich@suse.com>
792
793 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
794 (extractps): Add VexWIG to SSE2AVX forms.
795 * i386-tbl.h: Re-generate.
796
4814632e
JB		 7972020-01-16 Jan Beulich <jbeulich@suse.com>
798
799 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
800 Size64 from and use VexW1 on SSE2AVX forms.
801 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
802 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
803 * i386-tbl.h: Re-generate.
804
aad09917
AM		 8052020-01-15 Alan Modra <amodra@gmail.com>
806
807 * tic4x-dis.c (tic4x_version): Make unsigned long.
808 (optab, optab_special, registernames): New file scope vars.
809 (tic4x_print_register): Set up registernames rather than
810 malloc'd registertable.
811 (tic4x_disassemble): Delete optable and optable_special. Use
812 optab and optab_special instead. Throw away old optab,
813 optab_special and registernames when info->mach changes.
814
7a6bf3be
SB		 8152020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
816
817 PR 25377
818 * z80-dis.c (suffix): Use .db instruction to generate double
819 prefix.
820
ca1eaac0
AM		 8212020-01-14 Alan Modra <amodra@gmail.com>
822
823 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
824 values to unsigned before shifting.
825
1d67fe3b
TT		 8262020-01-13 Thomas Troeger <tstroege@gmx.de>
827
828 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
829 flow instructions.
830 (print_insn_thumb16, print_insn_thumb32): Likewise.
831 (print_insn): Initialize the insn info.
832 * i386-dis.c (print_insn): Initialize the insn info fields, and
833 detect jumps.
834
5e4f7e05
CZ		 8352012-01-13 Claudiu Zissulescu <claziss@gmail.com>
836
837 * arc-opc.c (C_NE): Make it required.
838
b9fe6b8a
CZ		 8392012-01-13 Claudiu Zissulescu <claziss@gmail.com>
840
841 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
842 reserved register name.
843
90dee485
AM		 8442020-01-13 Alan Modra <amodra@gmail.com>
845
846 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
847 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
848
febda64f
AM		 8492020-01-13 Alan Modra <amodra@gmail.com>
850
851 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
852 result of wasm_read_leb128 in a uint64_t and check that bits
853 are not lost when copying to other locals. Use uint32_t for
854 most locals. Use PRId64 when printing int64_t.
855
df08b588
AM		 8562020-01-13 Alan Modra <amodra@gmail.com>
857
858 * score-dis.c: Formatting.
859 * score7-dis.c: Formatting.
860
b2c759ce
AM		 8612020-01-13 Alan Modra <amodra@gmail.com>
862
863 * score-dis.c (print_insn_score48): Use unsigned variables for
864 unsigned values. Don't left shift negative values.
865 (print_insn_score32): Likewise.
866 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
867
5496abe1
AM		 8682020-01-13 Alan Modra <amodra@gmail.com>
869
870 * tic4x-dis.c (tic4x_print_register): Remove dead code.
871
202e762b
AM		 8722020-01-13 Alan Modra <amodra@gmail.com>
873
874 * fr30-ibld.c: Regenerate.
875
7ef412cf
AM		 8762020-01-13 Alan Modra <amodra@gmail.com>
877
878 * xgate-dis.c (print_insn): Don't left shift signed value.
879 (ripBits): Formatting, use 1u.
880
7f578b95
AM		 8812020-01-10 Alan Modra <amodra@gmail.com>
882
883 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
884 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
885
441af85b
AM		 8862020-01-10 Alan Modra <amodra@gmail.com>
887
888 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
889 and XRREG value earlier to avoid a shift with negative exponent.
890 * m10200-dis.c (disassemble): Similarly.
891
bce58db4
NC		 8922020-01-09 Nick Clifton <nickc@redhat.com>
893
894 PR 25224
895 * z80-dis.c (ld_ii_ii): Use correct cast.
896
40c75bc8
SB		 8972020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
898
899 PR 25224
900 * z80-dis.c (ld_ii_ii): Use character constant when checking
901 opcode byte value.
902
d835a58b
JB		 9032020-01-09 Jan Beulich <jbeulich@suse.com>
904
905 * i386-dis.c (SEP_Fixup): New.
906 (SEP): Define.
907 (dis386_twobyte): Use it for sysenter/sysexit.
908 (enum x86_64_isa): Change amd64 enumerator to value 1.
909 (OP_J): Compare isa64 against intel64 instead of amd64.
910 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
911 forms.
912 * i386-tbl.h: Re-generate.
913
030a2e78
AM		 9142020-01-08 Alan Modra <amodra@gmail.com>
915
916 * z8k-dis.c: Include libiberty.h
917 (instr_data_s): Make max_fetched unsigned.
918 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
919 Don't exceed byte_info bounds.
920 (output_instr): Make num_bytes unsigned.
921 (unpack_instr): Likewise for nibl_count and loop.
922 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
923 idx unsigned.
924 * z8k-opc.h: Regenerate.
925
bb82aefe
SV		 9262020-01-07 Shahab Vahedi <shahab@synopsys.com>
927
928 * arc-tbl.h (llock): Use 'LLOCK' as class.
929 (llockd): Likewise.
930 (scond): Use 'SCOND' as class.
931 (scondd): Likewise.
932 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
933 (scondd): Likewise.
934
cc6aa1a6
AM		 9352020-01-06 Alan Modra <amodra@gmail.com>
936
937 * m32c-ibld.c: Regenerate.
938
660e62b1
AM		 9392020-01-06 Alan Modra <amodra@gmail.com>
940
941 PR 25344
942 * z80-dis.c (suffix): Don't use a local struct buffer copy.
943 Peek at next byte to prevent recursion on repeated prefix bytes.
944 Ensure uninitialised "mybuf" is not accessed.
945 (print_insn_z80): Don't zero n_fetch and n_used here,..
946 (print_insn_z80_buf): ..do it here instead.
947
c9ae58fe
AM		 9482020-01-04 Alan Modra <amodra@gmail.com>
949
950 * m32r-ibld.c: Regenerate.
951
5f57d4ec
AM		 9522020-01-04 Alan Modra <amodra@gmail.com>
953
954 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
955
2c5c1196
AM		 9562020-01-04 Alan Modra <amodra@gmail.com>
957
958 * crx-dis.c (match_opcode): Avoid shift left of signed value.
959
2e98c6c5
AM		 9602020-01-04 Alan Modra <amodra@gmail.com>
961
962 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
963
567dfba2
JB		 9642020-01-03 Jan Beulich <jbeulich@suse.com>
965
5437a02a
JB		 966 * aarch64-tbl.h (aarch64_opcode_table): Use
967 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
968
9692020-01-03 Jan Beulich <jbeulich@suse.com>
970
971 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 972 forms of SUDOT and USDOT.
973
8c45011a
JB		 9742020-01-03 Jan Beulich <jbeulich@suse.com>
975
5437a02a 976 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 977 uzip{1,2}.
978 * opcodes/aarch64-dis-2.c: Re-generate.
979
f4950f76
JB		 9802020-01-03 Jan Beulich <jbeulich@suse.com>
981
5437a02a 982 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 983 FMMLA encoding.
984 * opcodes/aarch64-dis-2.c: Re-generate.
985
6655dba2
SB		 9862020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
987
988 * z80-dis.c: Add support for eZ80 and Z80 instructions.
989
b14ce8bf
AM		 9902020-01-01 Alan Modra <amodra@gmail.com>
991
992 Update year range in copyright notice of all files.
993
0b114740 994For older changes see ChangeLog-2019
3499769a 995\f
0b114740 996Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 997
998Copying and distribution of this file, with or without modification,
999are permitted in any medium without royalty provided the copyright
1000notice and this notice are preserved.
1001
1002Local Variables:
1003mode: change-log
1004left-margin: 8
1005fill-column: 74
1006version-control: never
1007End:
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