]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/mips/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
2002-06-03 Chris Demetriou <cgd@broadcom.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
bad673a9
CD		 12002-06-03 Chris Demetriou <cgd@broadcom.com>
2
3 * cp1.c: Clean up comments which describe FP formats.
4 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
5
7cbea089
CD		 62002-06-03 Chris Demetriou <cgd@broadcom.com>
7 Ed Satterthwaite <ehs@broadcom.com>
8
9 * configure.in (mipsisa64sb1*-*-*): New target for supporting
10 Broadcom SiByte SB-1 processor configurations.
11 * configure: Regenerate.
12 * sb1.igen: New file.
13 * mips.igen: Include sb1.igen.
14 (sb1): New model.
15 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
16 * mdmx.igen: Add "sb1" model to all appropriate functions and
17 instructions.
18 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
19 (ob_func, ob_acc): Reference the above.
20 (qh_acc): Adjust to keep the same size as ob_acc.
21 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
22 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
23
909daa82
CD		 242002-06-03 Chris Demetriou <cgd@broadcom.com>
25
26 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
27
f4f1b9f1
CD		 282002-06-02 Chris Demetriou <cgd@broadcom.com>
29 Ed Satterthwaite <ehs@broadcom.com>
30
31 * mips.igen (mdmx): New (pseudo-)model.
32 * mdmx.c, mdmx.igen: New files.
33 * Makefile.in (SIM_OBJS): Add mdmx.o.
34 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
35 New typedefs.
36 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
37 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
38 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
39 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
40 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
41 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
42 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
43 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
44 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
45 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
46 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
47 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
48 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
49 (qh_fmtsel): New macros.
50 (_sim_cpu): New member "acc".
51 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
52 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
53
5accf1ff
CD		 542002-05-01 Chris Demetriou <cgd@broadcom.com>
55
56 * interp.c: Use 'deprecated' rather than 'depreciated.'
57 * sim-main.h: Likewise.
58
402586aa
CD		 592002-05-01 Chris Demetriou <cgd@broadcom.com>
60
61 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
62 which wouldn't compile anyway.
63 * sim-main.h (unpredictable_action): New function prototype.
64 (Unpredictable): Define to call igen function unpredictable().
65 (NotWordValue): New macro to call igen function not_word_value().
66 (UndefinedResult): Remove.
67 * interp.c (undefined_result): Remove.
68 (unpredictable_action): New function.
69 * mips.igen (not_word_value, unpredictable): New functions.
70 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
71 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
72 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
73 NotWordValue() to check for unpredictable inputs, then
74 Unpredictable() to handle them.
75
c9b9995a
CD		 762002-02-24 Chris Demetriou <cgd@broadcom.com>
77
78 * mips.igen: Fix formatting of calls to Unpredictable().
79
e1015982
AC		 802002-04-20 Andrew Cagney <ac131313@redhat.com>
81
82 * interp.c (sim_open): Revert previous change.
83
b882a66b
AO		 842002-04-18 Alexandre Oliva <aoliva@redhat.com>
85
86 * interp.c (sim_open): Disable chunk of code that wrote code in
87 vector table entries.
88
c429b7dd
CD		 892002-03-19 Chris Demetriou <cgd@broadcom.com>
90
91 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
92 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
93 unused definitions.
94
37d146fa
CD		 952002-03-19 Chris Demetriou <cgd@broadcom.com>
96
97 * cp1.c: Fix many formatting issues.
98
07892c0b
CD		 992002-03-19 Chris G. Demetriou <cgd@broadcom.com>
100
101 * cp1.c (fpu_format_name): New function to replace...
102 (DOFMT): This. Delete, and update all callers.
103 (fpu_rounding_mode_name): New function to replace...
104 (RMMODE): This. Delete, and update all callers.
105
487f79b7
CD		 1062002-03-19 Chris G. Demetriou <cgd@broadcom.com>
107
108 * interp.c: Move FPU support routines from here to...
109 * cp1.c: Here. New file.
110 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
111 (cp1.o): New target.
112
1e799e28
CD		 1132002-03-12 Chris Demetriou <cgd@broadcom.com>
114
115 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
116 * mips.igen (mips32, mips64): New models, add to all instructions
117 and functions as appropriate.
118 (loadstore_ea, check_u64): New variant for model mips64.
119 (check_fmt_p): New variant for models mipsV and mips64, remove
120 mipsV model marking fro other variant.
121 (SLL) Rename to...
122 (SLLa) this.
123 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
124 for mips32 and mips64.
125 (DCLO, DCLZ): New instructions for mips64.
126
82f728db
CD		 1272002-03-07 Chris Demetriou <cgd@broadcom.com>
128
129 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
130 immediate or code as a hex value with the "%#lx" format.
131 (ANDI): Likewise, and fix printed instruction name.
132
b96e7ef1
CD		 1332002-03-05 Chris Demetriou <cgd@broadcom.com>
134
135 * sim-main.h (UndefinedResult, Unpredictable): New macros
136 which currently do nothing.
137
d35d4f70
CD		 1382002-03-05 Chris Demetriou <cgd@broadcom.com>
139
140 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
141 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
142 (status_CU3): New definitions.
143
144 * sim-main.h (ExceptionCause): Add new values for MIPS32
145 and MIPS64: MDMX, MCheck, CacheErr. Update comments
146 for DebugBreakPoint and NMIReset to note their status in
147 MIPS32 and MIPS64.
148 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
149 (SignalExceptionCacheErr): New exception macros.
150
3ad6f714
CD		 1512002-03-05 Chris Demetriou <cgd@broadcom.com>
152
153 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
154 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
155 is always enabled.
156 (SignalExceptionCoProcessorUnusable): Take as argument the
157 unusable coprocessor number.
158
86b77b47
CD		 1592002-03-05 Chris Demetriou <cgd@broadcom.com>
160
161 * mips.igen: Fix formatting of all SignalException calls.
162
97a88e93 1632002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 164
165 * sim-main.h (SIGNEXTEND): Remove.
166
97a88e93 1672002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 168
169 * mips.igen: Remove gencode comment from top of file, fix
170 spelling in another comment.
171
97a88e93 1722002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 173
174 * mips.igen (check_fmt, check_fmt_p): New functions to check
175 whether specific floating point formats are usable.
176 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
177 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
178 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
179 Use the new functions.
180 (do_c_cond_fmt): Remove format checks...
181 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
182
97a88e93 1832002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 184
185 * mips.igen: Fix formatting of check_fpu calls.
186
41774c9d
CD		 1872002-03-03 Chris Demetriou <cgd@broadcom.com>
188
189 * mips.igen (FLOOR.L.fmt): Store correct destination register.
190
4a0bd876
CD		 1912002-03-03 Chris Demetriou <cgd@broadcom.com>
192
193 * mips.igen: Remove whitespace at end of lines.
194
09297648
CD		 1952002-03-02 Chris Demetriou <cgd@broadcom.com>
196
197 * mips.igen (loadstore_ea): New function to do effective
198 address calculations.
199 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
200 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
201 CACHE): Use loadstore_ea to do effective address computations.
202
043b7057
CD		 2032002-03-02 Chris Demetriou <cgd@broadcom.com>
204
205 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
206 * mips.igen (LL, CxC1, MxC1): Likewise.
207
c1e8ada4
CD		 2082002-03-02 Chris Demetriou <cgd@broadcom.com>
209
210 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
211 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
212 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
213 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
214 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
215 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
216 Don't split opcode fields by hand, use the opcode field values
217 provided by igen.
218
3e1dca16
CD		 2192002-03-01 Chris Demetriou <cgd@broadcom.com>
220
221 * mips.igen (do_divu): Fix spacing.
222
223 * mips.igen (do_dsllv): Move to be right before DSLLV,
224 to match the rest of the do_<shift> functions.
225
fff8d27d
CD		 2262002-03-01 Chris Demetriou <cgd@broadcom.com>
227
228 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
229 DSRL32, do_dsrlv): Trace inputs and results.
230
0d3e762b
CD		 2312002-03-01 Chris Demetriou <cgd@broadcom.com>
232
233 * mips.igen (CACHE): Provide instruction-printing string.
234
235 * interp.c (signal_exception): Comment tokens after #endif.
236
eb5fcf93
CD		 2372002-02-28 Chris Demetriou <cgd@broadcom.com>
238
239 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
240 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
241 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
242 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
243 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
244 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
245 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
246 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
247
bb22bd7d
CD		 2482002-02-28 Chris Demetriou <cgd@broadcom.com>
249
250 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
251 instruction-printing string.
252 (LWU): Use '64' as the filter flag.
253
91a177cf
CD		 2542002-02-28 Chris Demetriou <cgd@broadcom.com>
255
256 * mips.igen (SDXC1): Fix instruction-printing string.
257
387f484a
CD		 2582002-02-28 Chris Demetriou <cgd@broadcom.com>
259
260 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
261 filter flags "32,f".
262
3d81f391
CD		 2632002-02-27 Chris Demetriou <cgd@broadcom.com>
264
265 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
266 as the filter flag.
267
af5107af
CD		 2682002-02-27 Chris Demetriou <cgd@broadcom.com>
269
270 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
271 add a comma) so that it more closely match the MIPS ISA
272 documentation opcode partitioning.
273 (PREF): Put useful names on opcode fields, and include
274 instruction-printing string.
275
ca971540
CD		 2762002-02-27 Chris Demetriou <cgd@broadcom.com>
277
278 * mips.igen (check_u64): New function which in the future will
279 check whether 64-bit instructions are usable and signal an
280 exception if not. Currently a no-op.
281 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
282 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
283 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
284 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
285
286 * mips.igen (check_fpu): New function which in the future will
287 check whether FPU instructions are usable and signal an exception
288 if not. Currently a no-op.
289 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
290 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
291 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
292 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
293 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
294 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
295 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
296 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
297
1c47a468
CD		 2982002-02-27 Chris Demetriou <cgd@broadcom.com>
299
300 * mips.igen (do_load_left, do_load_right): Move to be immediately
301 following do_load.
302 (do_store_left, do_store_right): Move to be immediately following
303 do_store.
304
603a98e7
CD		 3052002-02-27 Chris Demetriou <cgd@broadcom.com>
306
307 * mips.igen (mipsV): New model name. Also, add it to
308 all instructions and functions where it is appropriate.
309
c5d00cc7
CD		 3102002-02-18 Chris Demetriou <cgd@broadcom.com>
311
312 * mips.igen: For all functions and instructions, list model
313 names that support that instruction one per line.
314
074e9cb8
CD		 3152002-02-11 Chris Demetriou <cgd@broadcom.com>
316
317 * mips.igen: Add some additional comments about supported
318 models, and about which instructions go where.
319 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
320 order as is used in the rest of the file.
321
9805e229
CD		 3222002-02-11 Chris Demetriou <cgd@broadcom.com>
323
324 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
325 indicating that ALU32_END or ALU64_END are there to check
326 for overflow.
327 (DADD): Likewise, but also remove previous comment about
328 overflow checking.
329
f701dad2
CD		 3302002-02-10 Chris Demetriou <cgd@broadcom.com>
331
332 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
333 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
334 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
335 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
336 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
337 fields (i.e., add and move commas) so that they more closely
338 match the MIPS ISA documentation opcode partitioning.
339
3402002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 341
342 * mips.igen (ADDI): Print immediate value.
343 (BREAK): Print code.
344 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
345 (SLL): Print "nop" specially, and don't run the code
346 that does the shift for the "nop" case.
347
9e52972e
FF		 3482001-11-17 Fred Fish <fnf@redhat.com>
349
350 * sim-main.h (float_operation): Move enum declaration outside
351 of _sim_cpu struct declaration.
352
c0efbca4
JB		 3532001-04-12 Jim Blandy <jimb@redhat.com>
354
355 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
356 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
357 set of the FCSR.
358 * sim-main.h (COCIDX): Remove definition; this isn't supported by
359 PENDING_FILL, and you can get the intended effect gracefully by
360 calling PENDING_SCHED directly.
361
fb891446
BE		 3622001-02-23 Ben Elliston <bje@redhat.com>
363
364 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
365 already defined elsewhere.
366
8030f857
BE		 3672001-02-19 Ben Elliston <bje@redhat.com>
368
369 * sim-main.h (sim_monitor): Return an int.
370 * interp.c (sim_monitor): Add return values.
371 (signal_exception): Handle error conditions from sim_monitor.
372
56b48a7a
CD		 3732001-02-08 Ben Elliston <bje@redhat.com>
374
375 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
376 (store_memory): Likewise, pass cia to sim_core_write*.
377
d3ee60d9
FCE		 3782000-10-19 Frank Ch. Eigler <fche@redhat.com>
379
380 On advice from Chris G. Demetriou <cgd@sibyte.com>:
381 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
382
071da002
AC		 383Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
384
385 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
386 * Makefile.in: Don't delete *.igen when cleaning directory.
387
a28c02cd
AC		 388Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
389
390 * m16.igen (break): Call SignalException not sim_engine_halt.
391
80ee11fa
AC		 392Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
393
394 From Jason Eckhardt:
395 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
396
673388c0
AC		 397Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
398
399 * mips.igen (MxC1, DMxC1): Fix printf formatting.
400
4c0deff4
NC		 4012000-05-24 Michael Hayes <mhayes@cygnus.com>
402
403 * mips.igen (do_dmultx): Fix typo.
404
eb2d80b4
AC		 405Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
406
407 * configure: Regenerated to track ../common/aclocal.m4 changes.
408
dd37a34b
AC		 409Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
410
411 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
412
4c0deff4
NC		 4132000-04-12 Frank Ch. Eigler <fche@redhat.com>
414
415 * sim-main.h (GPR_CLEAR): Define macro.
416
e30db738
AC		 417Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
418
419 * interp.c (decode_coproc): Output long using %lx and not %s.
420
cb7450ea
FCE		 4212000-03-21 Frank Ch. Eigler <fche@redhat.com>
422
423 * interp.c (sim_open): Sort & extend dummy memory regions for
424 --board=jmr3904 for eCos.
425
a3027dd7
FCE		 4262000-03-02 Frank Ch. Eigler <fche@redhat.com>
427
428 * configure: Regenerated.
429
430Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
431
432 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
433 calls, conditional on the simulator being in verbose mode.
434
dfcd3bfb
JM		 435Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
436
437 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
438 cache don't get ReservedInstruction traps.
439
c2d11a7d
JM		 4401999-11-29 Mark Salter <msalter@cygnus.com>
441
442 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
443 to clear status bits in sdisr register. This is how the hardware works.
444
445 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
446 being used by cygmon.
447
4ce44c66
JM		 4481999-11-11 Andrew Haley <aph@cygnus.com>
449
450 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
451 instructions.
452
cff3e48b
JM		 453Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
454
455 * mips.igen (MULT): Correct previous mis-applied patch.
456
d4f3574e
SS		 457Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
458
459 * mips.igen (delayslot32): Handle sequence like
460 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
461 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
462 (MULT): Actually pass the third register...
463
4641999-09-03 Mark Salter <msalter@cygnus.com>
465
466 * interp.c (sim_open): Added more memory aliases for additional
467 hardware being touched by cygmon on jmr3904 board.
468
469Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
470
471 * configure: Regenerated to track ../common/aclocal.m4 changes.
472
a0b3c4fd
JM		 473Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
474
475 * interp.c (sim_store_register): Handle case where client - GDB -
476 specifies that a 4 byte register is 8 bytes in size.
477 (sim_fetch_register): Ditto.
478
adf40b2e
JM		 4791999-07-14 Frank Ch. Eigler <fche@cygnus.com>
480
481 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
482 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
483 (idt_monitor_base): Base address for IDT monitor traps.
484 (pmon_monitor_base): Ditto for PMON.
485 (lsipmon_monitor_base): Ditto for LSI PMON.
486 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
487 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
488 (sim_firmware_command): New function.
489 (mips_option_handler): Call it for OPTION_FIRMWARE.
490 (sim_open): Allocate memory for idt_monitor region. If "--board"
491 option was given, add no monitor by default. Add BREAK hooks only if
492 monitors are also there.
493
43e526b9
JM		 494Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
495
496 * interp.c (sim_monitor): Flush output before reading input.
497
498Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
499
500 * tconfig.in (SIM_HANDLES_LMA): Always define.
501
502Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
503
504 From Mark Salter <msalter@cygnus.com>:
505 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
506 (sim_open): Add setup for BSP board.
507
9846de1b
JM		 508Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
509
510 * mips.igen (MULT, MULTU): Add syntax for two operand version.
511 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
512 them as unimplemented.
513
cd0fc7c3
SS		 5141999-05-08 Felix Lee <flee@cygnus.com>
515
516 * configure: Regenerated to track ../common/aclocal.m4 changes.
517
7a292a7a
SS		 5181999-04-21 Frank Ch. Eigler <fche@cygnus.com>
519
520 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
521
522Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
523
524 * configure.in: Any mips64vr5*-*-* target should have
525 -DTARGET_ENABLE_FR=1.
526 (default_endian): Any mips64vr*el-*-* target should default to
527 LITTLE_ENDIAN.
528 * configure: Re-generate.
529
5301999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
531
532 * mips.igen (ldl): Extend from _16_, not 32.
533
534Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
535
536 * interp.c (sim_store_register): Force registers written to by GDB
537 into an un-interpreted state.
538
c906108c
SS		 5391999-02-05 Frank Ch. Eigler <fche@cygnus.com>
540
541 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
542 CPU, start periodic background I/O polls.
543 (tx3904sio_poll): New function: periodic I/O poller.
544
5451998-12-30 Frank Ch. Eigler <fche@cygnus.com>
546
547 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
548
549Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
550
551 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
552 case statement.
553
5541998-12-29 Frank Ch. Eigler <fche@cygnus.com>
555
556 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
557 (load_word): Call SIM_CORE_SIGNAL hook on error.
558 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
559 starting. For exception dispatching, pass PC instead of NULL_CIA.
560 (decode_coproc): Use COP0_BADVADDR to store faulting address.
561 * sim-main.h (COP0_BADVADDR): Define.
562 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
563 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
564 (_sim_cpu): Add exc_* fields to store register value snapshots.
565 * mips.igen (*): Replace memory-related SignalException* calls
566 with references to SIM_CORE_SIGNAL hook.
567
568 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
569 fix.
570 * sim-main.c (*): Minor warning cleanups.
571
5721998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
573
574 * m16.igen (DADDIU5): Correct type-o.
575
576Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
577
578 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
579 variables.
580
581Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
582
583 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
584 to include path.
585 (interp.o): Add dependency on itable.h
586 (oengine.c, gencode): Delete remaining references.
587 (BUILT_SRC_FROM_GEN): Clean up.
588
5891998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
590
591 * vr4run.c: New.
592 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
593 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
594 tmp-run-hack) : New.
595 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
596 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
597 Drop the "64" qualifier to get the HACK generator working.
598 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
599 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
600 qualifier to get the hack generator working.
601 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
602 (DSLL): Use do_dsll.
603 (DSLLV): Use do_dsllv.
604 (DSRA): Use do_dsra.
605 (DSRL): Use do_dsrl.
606 (DSRLV): Use do_dsrlv.
607 (BC1): Move *vr4100 to get the HACK generator working.
608 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
609 get the HACK generator working.
610 (MACC) Rename to get the HACK generator working.
611 (DMACC,MACCS,DMACCS): Add the 64.
612
6131998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
614
615 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
616 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
617
6181998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
619
620 * mips/interp.c (DEBUG): Cleanups.
621
6221998-12-10 Frank Ch. Eigler <fche@cygnus.com>
623
624 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
625 (tx3904sio_tickle): fflush after a stdout character output.
626
6271998-12-03 Frank Ch. Eigler <fche@cygnus.com>
628
629 * interp.c (sim_close): Uninstall modules.
630
631Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
632
633 * sim-main.h, interp.c (sim_monitor): Change to global
634 function.
635
636Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
637
638 * configure.in (vr4100): Only include vr4100 instructions in
639 simulator.
640 * configure: Re-generate.
641 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
642
643Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
644
645 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
646 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
647 true alternative.
648
649 * configure.in (sim_default_gen, sim_use_gen): Replace with
650 sim_gen.
651 (--enable-sim-igen): Delete config option. Always using IGEN.
652 * configure: Re-generate.
653
654 * Makefile.in (gencode): Kill, kill, kill.
655 * gencode.c: Ditto.
656
657Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
658
659 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
660 bit mips16 igen simulator.
661 * configure: Re-generate.
662
663 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
664 as part of vr4100 ISA.
665 * vr.igen: Mark all instructions as 64 bit only.
666
667Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
668
669 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
670 Pacify GCC.
671
672Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
673
674 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
675 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
676 * configure: Re-generate.
677
678 * m16.igen (BREAK): Define breakpoint instruction.
679 (JALX32): Mark instruction as mips16 and not r3900.
680 * mips.igen (C.cond.fmt): Fix typo in instruction format.
681
682 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
683
684Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
685
686 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
687 insn as a debug breakpoint.
688
689 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
690 pending.slot_size.
691 (PENDING_SCHED): Clean up trace statement.
692 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
693 (PENDING_FILL): Delay write by only one cycle.
694 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
695
696 * sim-main.c (pending_tick): Clean up trace statements. Add trace
697 of pending writes.
698 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
699 32 & 64.
700 (pending_tick): Move incrementing of index to FOR statement.
701 (pending_tick): Only update PENDING_OUT after a write has occured.
702
703 * configure.in: Add explicit mips-lsi-* target. Use gencode to
704 build simulator.
705 * configure: Re-generate.
706
707 * interp.c (sim_engine_run OLD): Delete explicit call to
708 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
709
710Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
711
712 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
713 interrupt level number to match changed SignalExceptionInterrupt
714 macro.
715
716Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
717
718 * interp.c: #include "itable.h" if WITH_IGEN.
719 (get_insn_name): New function.
720 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
721 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
722
723Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
724
725 * configure: Rebuilt to inhale new common/aclocal.m4.
726
727Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
728
729 * dv-tx3904sio.c: Include sim-assert.h.
730
731Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
732
733 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
734 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
735 Reorganize target-specific sim-hardware checks.
736 * configure: rebuilt.
737 * interp.c (sim_open): For tx39 target boards, set
738 OPERATING_ENVIRONMENT, add tx3904sio devices.
739 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
740 ROM executables. Install dv-sockser into sim-modules list.
741
742 * dv-tx3904irc.c: Compiler warning clean-up.
743 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
744 frequent hw-trace messages.
745
746Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
747
748 * vr.igen (MulAcc): Identify as a vr4100 specific function.
749
750Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
751
752 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
753
754 * vr.igen: New file.
755 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
756 * mips.igen: Define vr4100 model. Include vr.igen.
757Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
758
759 * mips.igen (check_mf_hilo): Correct check.
760
761Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
762
763 * sim-main.h (interrupt_event): Add prototype.
764
765 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
766 register_ptr, register_value.
767 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
768
769 * sim-main.h (tracefh): Make extern.
770
771Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
772
773 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
774 Reduce unnecessarily high timer event frequency.
775 * dv-tx3904cpu.c: Ditto for interrupt event.
776
777Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
778
779 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
780 to allay warnings.
781 (interrupt_event): Made non-static.
782
783 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
784 interchange of configuration values for external vs. internal
785 clock dividers.
786
787Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
788
789 * mips.igen (BREAK): Moved code to here for
790 simulator-reserved break instructions.
791 * gencode.c (build_instruction): Ditto.
792 * interp.c (signal_exception): Code moved from here. Non-
793 reserved instructions now use exception vector, rather
794 than halting sim.
795 * sim-main.h: Moved magic constants to here.
796
797Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
798
799 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
800 register upon non-zero interrupt event level, clear upon zero
801 event value.
802 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
803 by passing zero event value.
804 (*_io_{read,write}_buffer): Endianness fixes.
805 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
806 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
807
808 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
809 serial I/O and timer module at base address 0xFFFF0000.
810
811Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
812
813 * mips.igen (SWC1) : Correct the handling of ReverseEndian
814 and BigEndianCPU.
815
816Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
817
818 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
819 parts.
820 * configure: Update.
821
822Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
823
824 * dv-tx3904tmr.c: New file - implements tx3904 timer.
825 * dv-tx3904{irc,cpu}.c: Mild reformatting.
826 * configure.in: Include tx3904tmr in hw_device list.
827 * configure: Rebuilt.
828 * interp.c (sim_open): Instantiate three timer instances.
829 Fix address typo of tx3904irc instance.
830
831Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
832
833 * interp.c (signal_exception): SystemCall exception now uses
834 the exception vector.
835
836Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
837
838 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
839 to allay warnings.
840
841Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
842
843 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
844
845Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
846
847 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
848
849 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
850 sim-main.h. Declare a struct hw_descriptor instead of struct
851 hw_device_descriptor.
852
853Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
854
855 * mips.igen (do_store_left, do_load_left): Compute nr of left and
856 right bits and then re-align left hand bytes to correct byte
857 lanes. Fix incorrect computation in do_store_left when loading
858 bytes from second word.
859
860Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
861
862 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
863 * interp.c (sim_open): Only create a device tree when HW is
864 enabled.
865
866 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
867 * interp.c (signal_exception): Ditto.
868
869Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
870
871 * gencode.c: Mark BEGEZALL as LIKELY.
872
873Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
874
875 * sim-main.h (ALU32_END): Sign extend 32 bit results.
876 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
877
878Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
879
880 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
881 modules. Recognize TX39 target with "mips*tx39" pattern.
882 * configure: Rebuilt.
883 * sim-main.h (*): Added many macros defining bits in
884 TX39 control registers.
885 (SignalInterrupt): Send actual PC instead of NULL.
886 (SignalNMIReset): New exception type.
887 * interp.c (board): New variable for future use to identify
888 a particular board being simulated.
889 (mips_option_handler,mips_options): Added "--board" option.
890 (interrupt_event): Send actual PC.
891 (sim_open): Make memory layout conditional on board setting.
892 (signal_exception): Initial implementation of hardware interrupt
893 handling. Accept another break instruction variant for simulator
894 exit.
895 (decode_coproc): Implement RFE instruction for TX39.
896 (mips.igen): Decode RFE instruction as such.
897 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
898 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
899 bbegin to implement memory map.
900 * dv-tx3904cpu.c: New file.
901 * dv-tx3904irc.c: New file.
902
903Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
904
905 * mips.igen (check_mt_hilo): Create a separate r3900 version.
906
907Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
908
909 * tx.igen (madd,maddu): Replace calls to check_op_hilo
910 with calls to check_div_hilo.
911
912Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
913
914 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
915 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
916 Add special r3900 version of do_mult_hilo.
917 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
918 with calls to check_mult_hilo.
919 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
920 with calls to check_div_hilo.
921
922Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
923
924 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
925 Document a replacement.
926
927Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
928
929 * interp.c (sim_monitor): Make mon_printf work.
930
931Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
932
933 * sim-main.h (INSN_NAME): New arg `cpu'.
934
935Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
936
937 * configure: Regenerated to track ../common/aclocal.m4 changes.
938
939Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
940
941 * configure: Regenerated to track ../common/aclocal.m4 changes.
942 * config.in: Ditto.
943
944Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
945
946 * acconfig.h: New file.
947 * configure.in: Reverted change of Apr 24; use sinclude again.
948
949Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
950
951 * configure: Regenerated to track ../common/aclocal.m4 changes.
952 * config.in: Ditto.
953
954Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
955
956 * configure.in: Don't call sinclude.
957
958Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
959
960 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
961
962Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
963
964 * mips.igen (ERET): Implement.
965
966 * interp.c (decode_coproc): Return sign-extended EPC.
967
968 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
969
970 * interp.c (signal_exception): Do not ignore Trap.
971 (signal_exception): On TRAP, restart at exception address.
972 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
973 (signal_exception): Update.
974 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
975 so that TRAP instructions are caught.
976
977Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
978
979 * sim-main.h (struct hilo_access, struct hilo_history): Define,
980 contains HI/LO access history.
981 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
982 (HIACCESS, LOACCESS): Delete, replace with
983 (HIHISTORY, LOHISTORY): New macros.
984 (CHECKHILO): Delete all, moved to mips.igen
985
986 * gencode.c (build_instruction): Do not generate checks for
987 correct HI/LO register usage.
988
989 * interp.c (old_engine_run): Delete checks for correct HI/LO
990 register usage.
991
992 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
993 check_mf_cycles): New functions.
994 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
995 do_divu, domultx, do_mult, do_multu): Use.
996
997 * tx.igen ("madd", "maddu"): Use.
998
999Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1000
1001 * mips.igen (DSRAV): Use function do_dsrav.
1002 (SRAV): Use new function do_srav.
1003
1004 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1005 (B): Sign extend 11 bit immediate.
1006 (EXT-B*): Shift 16 bit immediate left by 1.
1007 (ADDIU*): Don't sign extend immediate value.
1008
1009Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1010
1011 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1012
1013 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1014 functions.
1015
1016 * mips.igen (delayslot32, nullify_next_insn): New functions.
1017 (m16.igen): Always include.
1018 (do_*): Add more tracing.
1019
1020 * m16.igen (delayslot16): Add NIA argument, could be called by a
1021 32 bit MIPS16 instruction.
1022
1023 * interp.c (ifetch16): Move function from here.
1024 * sim-main.c (ifetch16): To here.
1025
1026 * sim-main.c (ifetch16, ifetch32): Update to match current
1027 implementations of LH, LW.
1028 (signal_exception): Don't print out incorrect hex value of illegal
1029 instruction.
1030
1031Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1032
1033 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1034 instruction.
1035
1036 * m16.igen: Implement MIPS16 instructions.
1037
1038 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1039 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1040 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1041 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1042 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1043 bodies of corresponding code from 32 bit insn to these. Also used
1044 by MIPS16 versions of functions.
1045
1046 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1047 (IMEM16): Drop NR argument from macro.
1048
1049Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1050
1051 * Makefile.in (SIM_OBJS): Add sim-main.o.
1052
1053 * sim-main.h (address_translation, load_memory, store_memory,
1054 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1055 as INLINE_SIM_MAIN.
1056 (pr_addr, pr_uword64): Declare.
1057 (sim-main.c): Include when H_REVEALS_MODULE_P.
1058
1059 * interp.c (address_translation, load_memory, store_memory,
1060 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1061 from here.
1062 * sim-main.c: To here. Fix compilation problems.
1063
1064 * configure.in: Enable inlining.
1065 * configure: Re-config.
1066
1067Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1068
1069 * configure: Regenerated to track ../common/aclocal.m4 changes.
1070
1071Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1072
1073 * mips.igen: Include tx.igen.
1074 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1075 * tx.igen: New file, contains MADD and MADDU.
1076
1077 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1078 the hardwired constant `7'.
1079 (store_memory): Ditto.
1080 (LOADDRMASK): Move definition to sim-main.h.
1081
1082 mips.igen (MTC0): Enable for r3900.
1083 (ADDU): Add trace.
1084
1085 mips.igen (do_load_byte): Delete.
1086 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1087 do_store_right): New functions.
1088 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1089
1090 configure.in: Let the tx39 use igen again.
1091 configure: Update.
1092
1093Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1094
1095 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1096 not an address sized quantity. Return zero for cache sizes.
1097
1098Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1099
1100 * mips.igen (r3900): r3900 does not support 64 bit integer
1101 operations.
1102
1103Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1104
1105 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1106 than igen one.
1107 * configure : Rebuild.
1108
1109Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1110
1111 * configure: Regenerated to track ../common/aclocal.m4 changes.
1112
1113Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1114
1115 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1116
1117Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1118
1119 * configure: Regenerated to track ../common/aclocal.m4 changes.
1120 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1121
1122Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1123
1124 * configure: Regenerated to track ../common/aclocal.m4 changes.
1125
1126Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1127
1128 * interp.c (Max, Min): Comment out functions. Not yet used.
1129
1130Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1131
1132 * configure: Regenerated to track ../common/aclocal.m4 changes.
1133
1134Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1135
1136 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1137 configurable settings for stand-alone simulator.
1138
1139 * configure.in: Added X11 search, just in case.
1140
1141 * configure: Regenerated.
1142
1143Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1144
1145 * interp.c (sim_write, sim_read, load_memory, store_memory):
1146 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1147
1148Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1149
1150 * sim-main.h (GETFCC): Return an unsigned value.
1151
1152Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1153
1154 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1155 (DADD): Result destination is RD not RT.
1156
1157Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1158
1159 * sim-main.h (HIACCESS, LOACCESS): Always define.
1160
1161 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1162
1163 * interp.c (sim_info): Delete.
1164
1165Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1166
1167 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1168 (mips_option_handler): New argument `cpu'.
1169 (sim_open): Update call to sim_add_option_table.
1170
1171Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1172
1173 * mips.igen (CxC1): Add tracing.
1174
1175Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1176
1177 * sim-main.h (Max, Min): Declare.
1178
1179 * interp.c (Max, Min): New functions.
1180
1181 * mips.igen (BC1): Add tracing.
1182
1183Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1184
1185 * interp.c Added memory map for stack in vr4100
1186
1187Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1188
1189 * interp.c (load_memory): Add missing "break"'s.
1190
1191Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1192
1193 * interp.c (sim_store_register, sim_fetch_register): Pass in
1194 length parameter. Return -1.
1195
1196Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1197
1198 * interp.c: Added hardware init hook, fixed warnings.
1199
1200Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1201
1202 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1203
1204Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1205
1206 * interp.c (ifetch16): New function.
1207
1208 * sim-main.h (IMEM32): Rename IMEM.
1209 (IMEM16_IMMED): Define.
1210 (IMEM16): Define.
1211 (DELAY_SLOT): Update.
1212
1213 * m16run.c (sim_engine_run): New file.
1214
1215 * m16.igen: All instructions except LB.
1216 (LB): Call do_load_byte.
1217 * mips.igen (do_load_byte): New function.
1218 (LB): Call do_load_byte.
1219
1220 * mips.igen: Move spec for insn bit size and high bit from here.
1221 * Makefile.in (tmp-igen, tmp-m16): To here.
1222
1223 * m16.dc: New file, decode mips16 instructions.
1224
1225 * Makefile.in (SIM_NO_ALL): Define.
1226 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1227
1228Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1229
1230 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1231 point unit to 32 bit registers.
1232 * configure: Re-generate.
1233
1234Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1235
1236 * configure.in (sim_use_gen): Make IGEN the default simulator
1237 generator for generic 32 and 64 bit mips targets.
1238 * configure: Re-generate.
1239
1240Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1241
1242 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1243 bitsize.
1244
1245 * interp.c (sim_fetch_register, sim_store_register): Read/write
1246 FGR from correct location.
1247 (sim_open): Set size of FGR's according to
1248 WITH_TARGET_FLOATING_POINT_BITSIZE.
1249
1250 * sim-main.h (FGR): Store floating point registers in a separate
1251 array.
1252
1253Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1254
1255 * configure: Regenerated to track ../common/aclocal.m4 changes.
1256
1257Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1258
1259 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1260
1261 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1262
1263 * interp.c (pending_tick): New function. Deliver pending writes.
1264
1265 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1266 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1267 it can handle mixed sized quantites and single bits.
1268
1269Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1270
1271 * interp.c (oengine.h): Do not include when building with IGEN.
1272 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1273 (sim_info): Ditto for PROCESSOR_64BIT.
1274 (sim_monitor): Replace ut_reg with unsigned_word.
1275 (*): Ditto for t_reg.
1276 (LOADDRMASK): Define.
1277 (sim_open): Remove defunct check that host FP is IEEE compliant,
1278 using software to emulate floating point.
1279 (value_fpr, ...): Always compile, was conditional on HASFPU.
1280
1281Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1282
1283 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1284 size.
1285
1286 * interp.c (SD, CPU): Define.
1287 (mips_option_handler): Set flags in each CPU.
1288 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1289 (sim_close): Do not clear STATE, deleted anyway.
1290 (sim_write, sim_read): Assume CPU zero's vm should be used for
1291 data transfers.
1292 (sim_create_inferior): Set the PC for all processors.
1293 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1294 argument.
1295 (mips16_entry): Pass correct nr of args to store_word, load_word.
1296 (ColdReset): Cold reset all cpu's.
1297 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1298 (sim_monitor, load_memory, store_memory, signal_exception): Use
1299 `CPU' instead of STATE_CPU.
1300
1301
1302 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1303 SD or CPU_.
1304
1305 * sim-main.h (signal_exception): Add sim_cpu arg.
1306 (SignalException*): Pass both SD and CPU to signal_exception.
1307 * interp.c (signal_exception): Update.
1308
1309 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1310 Ditto
1311 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1312 address_translation): Ditto
1313 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1314
1315Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1316
1317 * configure: Regenerated to track ../common/aclocal.m4 changes.
1318
1319Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1320
1321 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1322
1323 * mips.igen (model): Map processor names onto BFD name.
1324
1325 * sim-main.h (CPU_CIA): Delete.
1326 (SET_CIA, GET_CIA): Define
1327
1328Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1329
1330 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1331 regiser.
1332
1333 * configure.in (default_endian): Configure a big-endian simulator
1334 by default.
1335 * configure: Re-generate.
1336
1337Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1338
1339 * configure: Regenerated to track ../common/aclocal.m4 changes.
1340
1341Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1342
1343 * interp.c (sim_monitor): Handle Densan monitor outbyte
1344 and inbyte functions.
1345
13461997-12-29 Felix Lee <flee@cygnus.com>
1347
1348 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1349
1350Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1351
1352 * Makefile.in (tmp-igen): Arrange for $zero to always be
1353 reset to zero after every instruction.
1354
1355Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1356
1357 * configure: Regenerated to track ../common/aclocal.m4 changes.
1358 * config.in: Ditto.
1359
1360Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1361
1362 * mips.igen (MSUB): Fix to work like MADD.
1363 * gencode.c (MSUB): Similarly.
1364
1365Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1366
1367 * configure: Regenerated to track ../common/aclocal.m4 changes.
1368
1369Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1370
1371 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1372
1373Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1374
1375 * sim-main.h (sim-fpu.h): Include.
1376
1377 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1378 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1379 using host independant sim_fpu module.
1380
1381Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1382
1383 * interp.c (signal_exception): Report internal errors with SIGABRT
1384 not SIGQUIT.
1385
1386 * sim-main.h (C0_CONFIG): New register.
1387 (signal.h): No longer include.
1388
1389 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1390
1391Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1392
1393 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1394
1395Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1396
1397 * mips.igen: Tag vr5000 instructions.
1398 (ANDI): Was missing mipsIV model, fix assembler syntax.
1399 (do_c_cond_fmt): New function.
1400 (C.cond.fmt): Handle mips I-III which do not support CC field
1401 separatly.
1402 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1403 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1404 in IV3.2 spec.
1405 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1406 vr5000 which saves LO in a GPR separatly.
1407
1408 * configure.in (enable-sim-igen): For vr5000, select vr5000
1409 specific instructions.
1410 * configure: Re-generate.
1411
1412Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1413
1414 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1415
1416 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1417 fmt_uninterpreted_64 bit cases to switch. Convert to
1418 fmt_formatted,
1419
1420 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1421
1422 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1423 as specified in IV3.2 spec.
1424 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1425
1426Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1427
1428 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1429 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1430 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1431 PENDING_FILL versions of instructions. Simplify.
1432 (X): New function.
1433 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1434 instructions.
1435 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1436 a signed value.
1437 (MTHI, MFHI): Disable code checking HI-LO.
1438
1439 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1440 global.
1441 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1442
1443Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1444
1445 * gencode.c (build_mips16_operands): Replace IPC with cia.
1446
1447 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1448 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1449 IPC to `cia'.
1450 (UndefinedResult): Replace function with macro/function
1451 combination.
1452 (sim_engine_run): Don't save PC in IPC.
1453
1454 * sim-main.h (IPC): Delete.
1455
1456
1457 * interp.c (signal_exception, store_word, load_word,
1458 address_translation, load_memory, store_memory, cache_op,
1459 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1460 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1461 current instruction address - cia - argument.
1462 (sim_read, sim_write): Call address_translation directly.
1463 (sim_engine_run): Rename variable vaddr to cia.
1464 (signal_exception): Pass cia to sim_monitor
1465
1466 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1467 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1468 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1469
1470 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1471 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1472 SIM_ASSERT.
1473
1474 * interp.c (signal_exception): Pass restart address to
1475 sim_engine_restart.
1476
1477 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1478 idecode.o): Add dependency.
1479
1480 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1481 Delete definitions
1482 (DELAY_SLOT): Update NIA not PC with branch address.
1483 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1484
1485 * mips.igen: Use CIA not PC in branch calculations.
1486 (illegal): Call SignalException.
1487 (BEQ, ADDIU): Fix assembler.
1488
1489Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1490
1491 * m16.igen (JALX): Was missing.
1492
1493 * configure.in (enable-sim-igen): New configuration option.
1494 * configure: Re-generate.
1495
1496 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1497
1498 * interp.c (load_memory, store_memory): Delete parameter RAW.
1499 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1500 bypassing {load,store}_memory.
1501
1502 * sim-main.h (ByteSwapMem): Delete definition.
1503
1504 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1505
1506 * interp.c (sim_do_command, sim_commands): Delete mips specific
1507 commands. Handled by module sim-options.
1508
1509 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1510 (WITH_MODULO_MEMORY): Define.
1511
1512 * interp.c (sim_info): Delete code printing memory size.
1513
1514 * interp.c (mips_size): Nee sim_size, delete function.
1515 (power2): Delete.
1516 (monitor, monitor_base, monitor_size): Delete global variables.
1517 (sim_open, sim_close): Delete code creating monitor and other
1518 memory regions. Use sim-memopts module, via sim_do_commandf, to
1519 manage memory regions.
1520 (load_memory, store_memory): Use sim-core for memory model.
1521
1522 * interp.c (address_translation): Delete all memory map code
1523 except line forcing 32 bit addresses.
1524
1525Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1526
1527 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1528 trace options.
1529
1530 * interp.c (logfh, logfile): Delete globals.
1531 (sim_open, sim_close): Delete code opening & closing log file.
1532 (mips_option_handler): Delete -l and -n options.
1533 (OPTION mips_options): Ditto.
1534
1535 * interp.c (OPTION mips_options): Rename option trace to dinero.
1536 (mips_option_handler): Update.
1537
1538Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1539
1540 * interp.c (fetch_str): New function.
1541 (sim_monitor): Rewrite using sim_read & sim_write.
1542 (sim_open): Check magic number.
1543 (sim_open): Write monitor vectors into memory using sim_write.
1544 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1545 (sim_read, sim_write): Simplify - transfer data one byte at a
1546 time.
1547 (load_memory, store_memory): Clarify meaning of parameter RAW.
1548
1549 * sim-main.h (isHOST): Defete definition.
1550 (isTARGET): Mark as depreciated.
1551 (address_translation): Delete parameter HOST.
1552
1553 * interp.c (address_translation): Delete parameter HOST.
1554
1555Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1556
1557 * mips.igen:
1558
1559 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1560 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1561
1562Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1563
1564 * mips.igen: Add model filter field to records.
1565
1566Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1567
1568 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1569
1570 interp.c (sim_engine_run): Do not compile function sim_engine_run
1571 when WITH_IGEN == 1.
1572
1573 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1574 target architecture.
1575
1576 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1577 igen. Replace with configuration variables sim_igen_flags /
1578 sim_m16_flags.
1579
1580 * m16.igen: New file. Copy mips16 insns here.
1581 * mips.igen: From here.
1582
1583Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1584
1585 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1586 to top.
1587 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1588
1589Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1590
1591 * gencode.c (build_instruction): Follow sim_write's lead in using
1592 BigEndianMem instead of !ByteSwapMem.
1593
1594Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1595
1596 * configure.in (sim_gen): Dependent on target, select type of
1597 generator. Always select old style generator.
1598
1599 configure: Re-generate.
1600
1601 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1602 targets.
1603 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1604 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1605 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1606 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1607 SIM_@sim_gen@_*, set by autoconf.
1608
1609Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1610
1611 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1612
1613 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1614 CURRENT_FLOATING_POINT instead.
1615
1616 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1617 (address_translation): Raise exception InstructionFetch when
1618 translation fails and isINSTRUCTION.
1619
1620 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1621 sim_engine_run): Change type of of vaddr and paddr to
1622 address_word.
1623 (address_translation, prefetch, load_memory, store_memory,
1624 cache_op): Change type of vAddr and pAddr to address_word.
1625
1626 * gencode.c (build_instruction): Change type of vaddr and paddr to
1627 address_word.
1628
1629Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1630
1631 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1632 macro to obtain result of ALU op.
1633
1634Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1635
1636 * interp.c (sim_info): Call profile_print.
1637
1638Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1639
1640 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1641
1642 * sim-main.h (WITH_PROFILE): Do not define, defined in
1643 common/sim-config.h. Use sim-profile module.
1644 (simPROFILE): Delete defintion.
1645
1646 * interp.c (PROFILE): Delete definition.
1647 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1648 (sim_close): Delete code writing profile histogram.
1649 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1650 Delete.
1651 (sim_engine_run): Delete code profiling the PC.
1652
1653Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1654
1655 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1656
1657 * interp.c (sim_monitor): Make register pointers of type
1658 unsigned_word*.
1659
1660 * sim-main.h: Make registers of type unsigned_word not
1661 signed_word.
1662
1663Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1664
1665 * interp.c (sync_operation): Rename from SyncOperation, make
1666 global, add SD argument.
1667 (prefetch): Rename from Prefetch, make global, add SD argument.
1668 (decode_coproc): Make global.
1669
1670 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1671
1672 * gencode.c (build_instruction): Generate DecodeCoproc not
1673 decode_coproc calls.
1674
1675 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1676 (SizeFGR): Move to sim-main.h
1677 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1678 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1679 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1680 sim-main.h.
1681 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1682 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1683 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1684 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1685 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1686 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1687
1688 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1689 exception.
1690 (sim-alu.h): Include.
1691 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1692 (sim_cia): Typedef to instruction_address.
1693
1694Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1695
1696 * Makefile.in (interp.o): Rename generated file engine.c to
1697 oengine.c.
1698
1699 * interp.c: Update.
1700
1701Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1702
1703 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1704
1705Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1706
1707 * gencode.c (build_instruction): For "FPSQRT", output correct
1708 number of arguments to Recip.
1709
1710Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1711
1712 * Makefile.in (interp.o): Depends on sim-main.h
1713
1714 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1715
1716 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1717 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1718 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1719 STATE, DSSTATE): Define
1720 (GPR, FGRIDX, ..): Define.
1721
1722 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1723 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1724 (GPR, FGRIDX, ...): Delete macros.
1725
1726 * interp.c: Update names to match defines from sim-main.h
1727
1728Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1729
1730 * interp.c (sim_monitor): Add SD argument.
1731 (sim_warning): Delete. Replace calls with calls to
1732 sim_io_eprintf.
1733 (sim_error): Delete. Replace calls with sim_io_error.
1734 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1735 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1736 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1737 argument.
1738 (mips_size): Rename from sim_size. Add SD argument.
1739
1740 * interp.c (simulator): Delete global variable.
1741 (callback): Delete global variable.
1742 (mips_option_handler, sim_open, sim_write, sim_read,
1743 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1744 sim_size,sim_monitor): Use sim_io_* not callback->*.
1745 (sim_open): ZALLOC simulator struct.
1746 (PROFILE): Do not define.
1747
1748Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1749
1750 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1751 support.h with corresponding code.
1752
1753 * sim-main.h (word64, uword64), support.h: Move definition to
1754 sim-main.h.
1755 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1756
1757 * support.h: Delete
1758 * Makefile.in: Update dependencies
1759 * interp.c: Do not include.
1760
1761Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1762
1763 * interp.c (address_translation, load_memory, store_memory,
1764 cache_op): Rename to from AddressTranslation et.al., make global,
1765 add SD argument
1766
1767 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1768 CacheOp): Define.
1769
1770 * interp.c (SignalException): Rename to signal_exception, make
1771 global.
1772
1773 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1774
1775 * sim-main.h (SignalException, SignalExceptionInterrupt,
1776 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1777 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1778 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1779 Define.
1780
1781 * interp.c, support.h: Use.
1782
1783Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1784
1785 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1786 to value_fpr / store_fpr. Add SD argument.
1787 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1788 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1789
1790 * sim-main.h (ValueFPR, StoreFPR): Define.
1791
1792Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1793
1794 * interp.c (sim_engine_run): Check consistency between configure
1795 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1796 and HASFPU.
1797
1798 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1799 (mips_fpu): Configure WITH_FLOATING_POINT.
1800 (mips_endian): Configure WITH_TARGET_ENDIAN.
1801 * configure: Update.
1802
1803Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1804
1805 * configure: Regenerated to track ../common/aclocal.m4 changes.
1806
1807Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1808
1809 * configure: Regenerated.
1810
1811Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1812
1813 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1814
1815Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1816
1817 * gencode.c (print_igen_insn_models): Assume certain architectures
1818 include all mips* instructions.
1819 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1820 instruction.
1821
1822 * Makefile.in (tmp.igen): Add target. Generate igen input from
1823 gencode file.
1824
1825 * gencode.c (FEATURE_IGEN): Define.
1826 (main): Add --igen option. Generate output in igen format.
1827 (process_instructions): Format output according to igen option.
1828 (print_igen_insn_format): New function.
1829 (print_igen_insn_models): New function.
1830 (process_instructions): Only issue warnings and ignore
1831 instructions when no FEATURE_IGEN.
1832
1833Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1834
1835 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1836 MIPS targets.
1837
1838Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1839
1840 * configure: Regenerated to track ../common/aclocal.m4 changes.
1841
1842Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1843
1844 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1845 SIM_RESERVED_BITS): Delete, moved to common.
1846 (SIM_EXTRA_CFLAGS): Update.
1847
1848Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1849
1850 * configure.in: Configure non-strict memory alignment.
1851 * configure: Regenerated to track ../common/aclocal.m4 changes.
1852
1853Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * configure: Regenerated to track ../common/aclocal.m4 changes.
1856
1857Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1858
1859 * gencode.c (SDBBP,DERET): Added (3900) insns.
1860 (RFE): Turn on for 3900.
1861 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1862 (dsstate): Made global.
1863 (SUBTARGET_R3900): Added.
1864 (CANCELDELAYSLOT): New.
1865 (SignalException): Ignore SystemCall rather than ignore and
1866 terminate. Add DebugBreakPoint handling.
1867 (decode_coproc): New insns RFE, DERET; and new registers Debug
1868 and DEPC protected by SUBTARGET_R3900.
1869 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1870 bits explicitly.
1871 * Makefile.in,configure.in: Add mips subtarget option.
1872 * configure: Update.
1873
1874Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1875
1876 * gencode.c: Add r3900 (tx39).
1877
1878
1879Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1880
1881 * gencode.c (build_instruction): Don't need to subtract 4 for
1882 JALR, just 2.
1883
1884Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1885
1886 * interp.c: Correct some HASFPU problems.
1887
1888Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1889
1890 * configure: Regenerated to track ../common/aclocal.m4 changes.
1891
1892Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1893
1894 * interp.c (mips_options): Fix samples option short form, should
1895 be `x'.
1896
1897Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1898
1899 * interp.c (sim_info): Enable info code. Was just returning.
1900
1901Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1902
1903 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1904 MFC0.
1905
1906Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1907
1908 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1909 constants.
1910 (build_instruction): Ditto for LL.
1911
1912Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1913
1914 * configure: Regenerated to track ../common/aclocal.m4 changes.
1915
1916Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1917
1918 * configure: Regenerated to track ../common/aclocal.m4 changes.
1919 * config.in: Ditto.
1920
1921Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1922
1923 * interp.c (sim_open): Add call to sim_analyze_program, update
1924 call to sim_config.
1925
1926Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1927
1928 * interp.c (sim_kill): Delete.
1929 (sim_create_inferior): Add ABFD argument. Set PC from same.
1930 (sim_load): Move code initializing trap handlers from here.
1931 (sim_open): To here.
1932 (sim_load): Delete, use sim-hload.c.
1933
1934 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1935
1936Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1937
1938 * configure: Regenerated to track ../common/aclocal.m4 changes.
1939 * config.in: Ditto.
1940
1941Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1942
1943 * interp.c (sim_open): Add ABFD argument.
1944 (sim_load): Move call to sim_config from here.
1945 (sim_open): To here. Check return status.
1946
1947Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1948
1949 * gencode.c (build_instruction): Two arg MADD should
1950 not assign result to $0.
1951
1952Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1953
1954 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1955 * sim/mips/configure.in: Regenerate.
1956
1957Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1958
1959 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1960 signed8, unsigned8 et.al. types.
1961
1962 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1963 hosts when selecting subreg.
1964
1965Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1966
1967 * interp.c (sim_engine_run): Reset the ZERO register to zero
1968 regardless of FEATURE_WARN_ZERO.
1969 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1970
1971Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1972
1973 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1974 (SignalException): For BreakPoints ignore any mode bits and just
1975 save the PC.
1976 (SignalException): Always set the CAUSE register.
1977
1978Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1979
1980 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1981 exception has been taken.
1982
1983 * interp.c: Implement the ERET and mt/f sr instructions.
1984
1985Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1986
1987 * interp.c (SignalException): Don't bother restarting an
1988 interrupt.
1989
1990Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1991
1992 * interp.c (SignalException): Really take an interrupt.
1993 (interrupt_event): Only deliver interrupts when enabled.
1994
1995Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1996
1997 * interp.c (sim_info): Only print info when verbose.
1998 (sim_info) Use sim_io_printf for output.
1999
2000Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2001
2002 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2003 mips architectures.
2004
2005Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2006
2007 * interp.c (sim_do_command): Check for common commands if a
2008 simulator specific command fails.
2009
2010Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2011
2012 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2013 and simBE when DEBUG is defined.
2014
2015Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2016
2017 * interp.c (interrupt_event): New function. Pass exception event
2018 onto exception handler.
2019
2020 * configure.in: Check for stdlib.h.
2021 * configure: Regenerate.
2022
2023 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2024 variable declaration.
2025 (build_instruction): Initialize memval1.
2026 (build_instruction): Add UNUSED attribute to byte, bigend,
2027 reverse.
2028 (build_operands): Ditto.
2029
2030 * interp.c: Fix GCC warnings.
2031 (sim_get_quit_code): Delete.
2032
2033 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2034 * Makefile.in: Ditto.
2035 * configure: Re-generate.
2036
2037 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2038
2039Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2040
2041 * interp.c (mips_option_handler): New function parse argumes using
2042 sim-options.
2043 (myname): Replace with STATE_MY_NAME.
2044 (sim_open): Delete check for host endianness - performed by
2045 sim_config.
2046 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2047 (sim_open): Move much of the initialization from here.
2048 (sim_load): To here. After the image has been loaded and
2049 endianness set.
2050 (sim_open): Move ColdReset from here.
2051 (sim_create_inferior): To here.
2052 (sim_open): Make FP check less dependant on host endianness.
2053
2054 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2055 run.
2056 * interp.c (sim_set_callbacks): Delete.
2057
2058 * interp.c (membank, membank_base, membank_size): Replace with
2059 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2060 (sim_open): Remove call to callback->init. gdb/run do this.
2061
2062 * interp.c: Update
2063
2064 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2065
2066 * interp.c (big_endian_p): Delete, replaced by
2067 current_target_byte_order.
2068
2069Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2070
2071 * interp.c (host_read_long, host_read_word, host_swap_word,
2072 host_swap_long): Delete. Using common sim-endian.
2073 (sim_fetch_register, sim_store_register): Use H2T.
2074 (pipeline_ticks): Delete. Handled by sim-events.
2075 (sim_info): Update.
2076 (sim_engine_run): Update.
2077
2078Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2079
2080 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2081 reason from here.
2082 (SignalException): To here. Signal using sim_engine_halt.
2083 (sim_stop_reason): Delete, moved to common.
2084
2085Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2086
2087 * interp.c (sim_open): Add callback argument.
2088 (sim_set_callbacks): Delete SIM_DESC argument.
2089 (sim_size): Ditto.
2090
2091Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2092
2093 * Makefile.in (SIM_OBJS): Add common modules.
2094
2095 * interp.c (sim_set_callbacks): Also set SD callback.
2096 (set_endianness, xfer_*, swap_*): Delete.
2097 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2098 Change to functions using sim-endian macros.
2099 (control_c, sim_stop): Delete, use common version.
2100 (simulate): Convert into.
2101 (sim_engine_run): This function.
2102 (sim_resume): Delete.
2103
2104 * interp.c (simulation): New variable - the simulator object.
2105 (sim_kind): Delete global - merged into simulation.
2106 (sim_load): Cleanup. Move PC assignment from here.
2107 (sim_create_inferior): To here.
2108
2109 * sim-main.h: New file.
2110 * interp.c (sim-main.h): Include.
2111
2112Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2113
2114 * configure: Regenerated to track ../common/aclocal.m4 changes.
2115
2116Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2117
2118 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2119
2120Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2121
2122 * gencode.c (build_instruction): DIV instructions: check
2123 for division by zero and integer overflow before using
2124 host's division operation.
2125
2126Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2127
2128 * Makefile.in (SIM_OBJS): Add sim-load.o.
2129 * interp.c: #include bfd.h.
2130 (target_byte_order): Delete.
2131 (sim_kind, myname, big_endian_p): New static locals.
2132 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2133 after argument parsing. Recognize -E arg, set endianness accordingly.
2134 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2135 load file into simulator. Set PC from bfd.
2136 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2137 (set_endianness): Use big_endian_p instead of target_byte_order.
2138
2139Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2140
2141 * interp.c (sim_size): Delete prototype - conflicts with
2142 definition in remote-sim.h. Correct definition.
2143
2144Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2145
2146 * configure: Regenerated to track ../common/aclocal.m4 changes.
2147 * config.in: Ditto.
2148
2149Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2150
2151 * interp.c (sim_open): New arg `kind'.
2152
2153 * configure: Regenerated to track ../common/aclocal.m4 changes.
2154
2155Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2156
2157 * configure: Regenerated to track ../common/aclocal.m4 changes.
2158
2159Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2160
2161 * interp.c (sim_open): Set optind to 0 before calling getopt.
2162
2163Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2164
2165 * configure: Regenerated to track ../common/aclocal.m4 changes.
2166
2167Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2168
2169 * interp.c : Replace uses of pr_addr with pr_uword64
2170 where the bit length is always 64 independent of SIM_ADDR.
2171 (pr_uword64) : added.
2172
2173Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2174
2175 * configure: Re-generate.
2176
2177Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2178
2179 * configure: Regenerate to track ../common/aclocal.m4 changes.
2180
2181Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2182
2183 * interp.c (sim_open): New SIM_DESC result. Argument is now
2184 in argv form.
2185 (other sim_*): New SIM_DESC argument.
2186
2187Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2188
2189 * interp.c: Fix printing of addresses for non-64-bit targets.
2190 (pr_addr): Add function to print address based on size.
2191
2192Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2193
2194 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2195
2196Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2197
2198 * gencode.c (build_mips16_operands): Correct computation of base
2199 address for extended PC relative instruction.
2200
2201Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2202
2203 * interp.c (mips16_entry): Add support for floating point cases.
2204 (SignalException): Pass floating point cases to mips16_entry.
2205 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2206 registers.
2207 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2208 or fmt_word.
2209 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2210 and then set the state to fmt_uninterpreted.
2211 (COP_SW): Temporarily set the state to fmt_word while calling
2212 ValueFPR.
2213
2214Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2215
2216 * gencode.c (build_instruction): The high order may be set in the
2217 comparison flags at any ISA level, not just ISA 4.
2218
2219Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2220
2221 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2222 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2223 * configure.in: sinclude ../common/aclocal.m4.
2224 * configure: Regenerated.
2225
2226Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2227
2228 * configure: Rebuild after change to aclocal.m4.
2229
2230Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2231
2232 * configure configure.in Makefile.in: Update to new configure
2233 scheme which is more compatible with WinGDB builds.
2234 * configure.in: Improve comment on how to run autoconf.
2235 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2236 * Makefile.in: Use autoconf substitution to install common
2237 makefile fragment.
2238
2239Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2240
2241 * gencode.c (build_instruction): Use BigEndianCPU instead of
2242 ByteSwapMem.
2243
2244Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2245
2246 * interp.c (sim_monitor): Make output to stdout visible in
2247 wingdb's I/O log window.
2248
2249Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2250
2251 * support.h: Undo previous change to SIGTRAP
2252 and SIGQUIT values.
2253
2254Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2255
2256 * interp.c (store_word, load_word): New static functions.
2257 (mips16_entry): New static function.
2258 (SignalException): Look for mips16 entry and exit instructions.
2259 (simulate): Use the correct index when setting fpr_state after
2260 doing a pending move.
2261
2262Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2263
2264 * interp.c: Fix byte-swapping code throughout to work on
2265 both little- and big-endian hosts.
2266
2267Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2268
2269 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2270 with gdb/config/i386/xm-windows.h.
2271
2272Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2273
2274 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2275 that messes up arithmetic shifts.
2276
2277Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2278
2279 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2280 SIGTRAP and SIGQUIT for _WIN32.
2281
2282Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2283
2284 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2285 force a 64 bit multiplication.
2286 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2287 destination register is 0, since that is the default mips16 nop
2288 instruction.
2289
2290Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2291
2292 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2293 (build_endian_shift): Don't check proc64.
2294 (build_instruction): Always set memval to uword64. Cast op2 to
2295 uword64 when shifting it left in memory instructions. Always use
2296 the same code for stores--don't special case proc64.
2297
2298 * gencode.c (build_mips16_operands): Fix base PC value for PC
2299 relative operands.
2300 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2301 jal instruction.
2302 * interp.c (simJALDELAYSLOT): Define.
2303 (JALDELAYSLOT): Define.
2304 (INDELAYSLOT, INJALDELAYSLOT): Define.
2305 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2306
2307Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2308
2309 * interp.c (sim_open): add flush_cache as a PMON routine
2310 (sim_monitor): handle flush_cache by ignoring it
2311
2312Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2313
2314 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2315 BigEndianMem.
2316 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2317 (BigEndianMem): Rename to ByteSwapMem and change sense.
2318 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2319 BigEndianMem references to !ByteSwapMem.
2320 (set_endianness): New function, with prototype.
2321 (sim_open): Call set_endianness.
2322 (sim_info): Use simBE instead of BigEndianMem.
2323 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2324 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2325 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2326 ifdefs, keeping the prototype declaration.
2327 (swap_word): Rewrite correctly.
2328 (ColdReset): Delete references to CONFIG. Delete endianness related
2329 code; moved to set_endianness.
2330
2331Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2332
2333 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2334 * interp.c (CHECKHILO): Define away.
2335 (simSIGINT): New macro.
2336 (membank_size): Increase from 1MB to 2MB.
2337 (control_c): New function.
2338 (sim_resume): Rename parameter signal to signal_number. Add local
2339 variable prev. Call signal before and after simulate.
2340 (sim_stop_reason): Add simSIGINT support.
2341 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2342 functions always.
2343 (sim_warning): Delete call to SignalException. Do call printf_filtered
2344 if logfh is NULL.
2345 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2346 a call to sim_warning.
2347
2348Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2349
2350 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2351 16 bit instructions.
2352
2353Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2354
2355 Add support for mips16 (16 bit MIPS implementation):
2356 * gencode.c (inst_type): Add mips16 instruction encoding types.
2357 (GETDATASIZEINSN): Define.
2358 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2359 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2360 mtlo.
2361 (MIPS16_DECODE): New table, for mips16 instructions.
2362 (bitmap_val): New static function.
2363 (struct mips16_op): Define.
2364 (mips16_op_table): New table, for mips16 operands.
2365 (build_mips16_operands): New static function.
2366 (process_instructions): If PC is odd, decode a mips16
2367 instruction. Break out instruction handling into new
2368 build_instruction function.
2369 (build_instruction): New static function, broken out of
2370 process_instructions. Check modifiers rather than flags for SHIFT
2371 bit count and m[ft]{hi,lo} direction.
2372 (usage): Pass program name to fprintf.
2373 (main): Remove unused variable this_option_optind. Change
2374 ``*loptarg++'' to ``loptarg++''.
2375 (my_strtoul): Parenthesize && within ||.
2376 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2377 (simulate): If PC is odd, fetch a 16 bit instruction, and
2378 increment PC by 2 rather than 4.
2379 * configure.in: Add case for mips16*-*-*.
2380 * configure: Rebuild.
2381
2382Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2383
2384 * interp.c: Allow -t to enable tracing in standalone simulator.
2385 Fix garbage output in trace file and error messages.
2386
2387Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2388
2389 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2390 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2391 * configure.in: Simplify using macros in ../common/aclocal.m4.
2392 * configure: Regenerated.
2393 * tconfig.in: New file.
2394
2395Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2396
2397 * interp.c: Fix bugs in 64-bit port.
2398 Use ansi function declarations for msvc compiler.
2399 Initialize and test file pointer in trace code.
2400 Prevent duplicate definition of LAST_EMED_REGNUM.
2401
2402Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2403
2404 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2405
2406Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2407
2408 * interp.c (SignalException): Check for explicit terminating
2409 breakpoint value.
2410 * gencode.c: Pass instruction value through SignalException()
2411 calls for Trap, Breakpoint and Syscall.
2412
2413Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2414
2415 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2416 only used on those hosts that provide it.
2417 * configure.in: Add sqrt() to list of functions to be checked for.
2418 * config.in: Re-generated.
2419 * configure: Re-generated.
2420
2421Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2422
2423 * gencode.c (process_instructions): Call build_endian_shift when
2424 expanding STORE RIGHT, to fix swr.
2425 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2426 clear the high bits.
2427 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2428 Fix float to int conversions to produce signed values.
2429
2430Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2431
2432 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2433 (process_instructions): Correct handling of nor instruction.
2434 Correct shift count for 32 bit shift instructions. Correct sign
2435 extension for arithmetic shifts to not shift the number of bits in
2436 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2437 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2438 Fix madd.
2439 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2440 It's OK to have a mult follow a mult. What's not OK is to have a
2441 mult follow an mfhi.
2442 (Convert): Comment out incorrect rounding code.
2443
2444Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2445
2446 * interp.c (sim_monitor): Improved monitor printf
2447 simulation. Tidied up simulator warnings, and added "--log" option
2448 for directing warning message output.
2449 * gencode.c: Use sim_warning() rather than WARNING macro.
2450
2451Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2452
2453 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2454 getopt1.o, rather than on gencode.c. Link objects together.
2455 Don't link against -liberty.
2456 (gencode.o, getopt.o, getopt1.o): New targets.
2457 * gencode.c: Include <ctype.h> and "ansidecl.h".
2458 (AND): Undefine after including "ansidecl.h".
2459 (ULONG_MAX): Define if not defined.
2460 (OP_*): Don't define macros; now defined in opcode/mips.h.
2461 (main): Call my_strtoul rather than strtoul.
2462 (my_strtoul): New static function.
2463
2464Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2465
2466 * gencode.c (process_instructions): Generate word64 and uword64
2467 instead of `long long' and `unsigned long long' data types.
2468 * interp.c: #include sysdep.h to get signals, and define default
2469 for SIGBUS.
2470 * (Convert): Work around for Visual-C++ compiler bug with type
2471 conversion.
2472 * support.h: Make things compile under Visual-C++ by using
2473 __int64 instead of `long long'. Change many refs to long long
2474 into word64/uword64 typedefs.
2475
2476Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2477
2478 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2479 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2480 (docdir): Removed.
2481 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2482 (AC_PROG_INSTALL): Added.
2483 (AC_PROG_CC): Moved to before configure.host call.
2484 * configure: Rebuilt.
2485
2486Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2487
2488 * configure.in: Define @SIMCONF@ depending on mips target.
2489 * configure: Rebuild.
2490 * Makefile.in (run): Add @SIMCONF@ to control simulator
2491 construction.
2492 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2493 * interp.c: Remove some debugging, provide more detailed error
2494 messages, update memory accesses to use LOADDRMASK.
2495
2496Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2497
2498 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2499 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2500 stamp-h.
2501 * configure: Rebuild.
2502 * config.in: New file, generated by autoheader.
2503 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2504 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2505 HAVE_ANINT and HAVE_AINT, as appropriate.
2506 * Makefile.in (run): Use @LIBS@ rather than -lm.
2507 (interp.o): Depend upon config.h.
2508 (Makefile): Just rebuild Makefile.
2509 (clean): Remove stamp-h.
2510 (mostlyclean): Make the same as clean, not as distclean.
2511 (config.h, stamp-h): New targets.
2512
2513Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2514
2515 * interp.c (ColdReset): Fix boolean test. Make all simulator
2516 globals static.
2517
2518Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2519
2520 * interp.c (xfer_direct_word, xfer_direct_long,
2521 swap_direct_word, swap_direct_long, xfer_big_word,
2522 xfer_big_long, xfer_little_word, xfer_little_long,
2523 swap_word,swap_long): Added.
2524 * interp.c (ColdReset): Provide function indirection to
2525 host<->simulated_target transfer routines.
2526 * interp.c (sim_store_register, sim_fetch_register): Updated to
2527 make use of indirected transfer routines.
2528
2529Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2530
2531 * gencode.c (process_instructions): Ensure FP ABS instruction
2532 recognised.
2533 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2534 system call support.
2535
2536Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2537
2538 * interp.c (sim_do_command): Complain if callback structure not
2539 initialised.
2540
2541Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2542
2543 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2544 support for Sun hosts.
2545 * Makefile.in (gencode): Ensure the host compiler and libraries
2546 used for cross-hosted build.
2547
2548Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2549
2550 * interp.c, gencode.c: Some more (TODO) tidying.
2551
2552Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2553
2554 * gencode.c, interp.c: Replaced explicit long long references with
2555 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2556 * support.h (SET64LO, SET64HI): Macros added.
2557
2558Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2559
2560 * configure: Regenerate with autoconf 2.7.
2561
2562Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2563
2564 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2565 * support.h: Remove superfluous "1" from #if.
2566 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2567
2568Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2569
2570 * interp.c (StoreFPR): Control UndefinedResult() call on
2571 WARN_RESULT manifest.
2572
2573Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2574
2575 * gencode.c: Tidied instruction decoding, and added FP instruction
2576 support.
2577
2578 * interp.c: Added dineroIII, and BSD profiling support. Also
2579 run-time FP handling.
2580
2581Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2582
2583 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2584 gencode.c, interp.c, support.h: created.
A mirror of the official binutils-gdb repository