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0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
4 | * (C) Copyright 2008 Armadeus Systems nc | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <malloc.h> | |
26 | #include <net.h> | |
27 | #include <miiphy.h> | |
28 | #include "fec_mxc.h" | |
29 | ||
30 | #include <asm/arch/clock.h> | |
31 | #include <asm/arch/imx-regs.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/errno.h> | |
e2a66e60 | 34 | #include <linux/compiler.h> |
0b23fb36 IY |
35 | |
36 | DECLARE_GLOBAL_DATA_PTR; | |
37 | ||
bc1ce150 MV |
38 | /* |
39 | * Timeout the transfer after 5 mS. This is usually a bit more, since | |
40 | * the code in the tightloops this timeout is used in adds some overhead. | |
41 | */ | |
42 | #define FEC_XFER_TIMEOUT 5000 | |
43 | ||
0b23fb36 IY |
44 | #ifndef CONFIG_MII |
45 | #error "CONFIG_MII has to be defined!" | |
46 | #endif | |
47 | ||
5c1ad3e6 EN |
48 | #ifndef CONFIG_FEC_XCV_TYPE |
49 | #define CONFIG_FEC_XCV_TYPE MII100 | |
392b8502 MV |
50 | #endif |
51 | ||
be7e87e2 MV |
52 | /* |
53 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
54 | * sending and after receiving. | |
55 | */ | |
5c1ad3e6 EN |
56 | #ifdef CONFIG_MX28 |
57 | #define CONFIG_FEC_MXC_SWAP_PACKET | |
58 | #endif | |
59 | ||
60 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) | |
61 | ||
62 | /* Check various alignment issues at compile time */ | |
63 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) | |
64 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" | |
65 | #endif | |
66 | ||
67 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ | |
68 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) | |
69 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" | |
be7e87e2 MV |
70 | #endif |
71 | ||
0b23fb36 IY |
72 | #undef DEBUG |
73 | ||
74 | struct nbuf { | |
75 | uint8_t data[1500]; /**< actual data */ | |
76 | int length; /**< actual length */ | |
77 | int used; /**< buffer in use or not */ | |
78 | uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ | |
79 | }; | |
80 | ||
5c1ad3e6 | 81 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
82 | static void swap_packet(uint32_t *packet, int length) |
83 | { | |
84 | int i; | |
85 | ||
86 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
87 | packet[i] = __swab32(packet[i]); | |
88 | } | |
89 | #endif | |
90 | ||
0b23fb36 IY |
91 | /* |
92 | * MII-interface related functions | |
93 | */ | |
13947f43 TK |
94 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, |
95 | uint8_t regAddr) | |
0b23fb36 | 96 | { |
0b23fb36 IY |
97 | uint32_t reg; /* convenient holder for the PHY register */ |
98 | uint32_t phy; /* convenient holder for the PHY */ | |
99 | uint32_t start; | |
13947f43 | 100 | int val; |
0b23fb36 IY |
101 | |
102 | /* | |
103 | * reading from any PHY's register is done by properly | |
104 | * programming the FEC's MII data register. | |
105 | */ | |
d133b881 | 106 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
107 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; |
108 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
109 | ||
110 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 111 | phy | reg, ð->mii_data); |
0b23fb36 IY |
112 | |
113 | /* | |
114 | * wait for the related interrupt | |
115 | */ | |
a60d1e5b | 116 | start = get_timer(0); |
d133b881 | 117 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
118 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
119 | printf("Read MDIO failed...\n"); | |
120 | return -1; | |
121 | } | |
122 | } | |
123 | ||
124 | /* | |
125 | * clear mii interrupt bit | |
126 | */ | |
d133b881 | 127 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
128 | |
129 | /* | |
130 | * it's now safe to read the PHY's register | |
131 | */ | |
13947f43 TK |
132 | val = (unsigned short)readl(ð->mii_data); |
133 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, | |
134 | regAddr, val); | |
135 | return val; | |
0b23fb36 IY |
136 | } |
137 | ||
575c5cc0 | 138 | static void fec_mii_setspeed(struct ethernet_regs *eth) |
4294b248 SB |
139 | { |
140 | /* | |
141 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
142 | * and do not drop the Preamble. | |
143 | */ | |
144 | writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, | |
575c5cc0 TK |
145 | ð->mii_speed); |
146 | debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); | |
4294b248 | 147 | } |
0b23fb36 | 148 | |
13947f43 TK |
149 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, |
150 | uint8_t regAddr, uint16_t data) | |
151 | { | |
0b23fb36 IY |
152 | uint32_t reg; /* convenient holder for the PHY register */ |
153 | uint32_t phy; /* convenient holder for the PHY */ | |
154 | uint32_t start; | |
155 | ||
156 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; | |
157 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
158 | ||
159 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 160 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 IY |
161 | |
162 | /* | |
163 | * wait for the MII interrupt | |
164 | */ | |
a60d1e5b | 165 | start = get_timer(0); |
d133b881 | 166 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
167 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
168 | printf("Write MDIO failed...\n"); | |
169 | return -1; | |
170 | } | |
171 | } | |
172 | ||
173 | /* | |
174 | * clear MII interrupt bit | |
175 | */ | |
d133b881 | 176 | writel(FEC_IEVENT_MII, ð->ievent); |
13947f43 | 177 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, |
0b23fb36 IY |
178 | regAddr, data); |
179 | ||
180 | return 0; | |
181 | } | |
182 | ||
13947f43 TK |
183 | int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr) |
184 | { | |
185 | return fec_mdio_read(bus->priv, phyAddr, regAddr); | |
186 | } | |
187 | ||
188 | int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr, | |
189 | u16 data) | |
190 | { | |
191 | return fec_mdio_write(bus->priv, phyAddr, regAddr, data); | |
192 | } | |
193 | ||
194 | #ifndef CONFIG_PHYLIB | |
0b23fb36 IY |
195 | static int miiphy_restart_aneg(struct eth_device *dev) |
196 | { | |
b774fe9d SB |
197 | int ret = 0; |
198 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) | |
9e27e9dc | 199 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 200 | struct ethernet_regs *eth = fec->bus->priv; |
9e27e9dc | 201 | |
0b23fb36 IY |
202 | /* |
203 | * Wake up from sleep if necessary | |
204 | * Reset PHY, then delay 300ns | |
205 | */ | |
cb17b92d | 206 | #ifdef CONFIG_MX27 |
13947f43 | 207 | fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); |
cb17b92d | 208 | #endif |
13947f43 | 209 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
0b23fb36 IY |
210 | udelay(1000); |
211 | ||
212 | /* | |
213 | * Set the auto-negotiation advertisement register bits | |
214 | */ | |
13947f43 | 215 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
8ef583a0 MF |
216 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
217 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
13947f43 | 218 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
8ef583a0 | 219 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
220 | |
221 | if (fec->mii_postcall) | |
222 | ret = fec->mii_postcall(fec->phy_id); | |
223 | ||
b774fe9d | 224 | #endif |
2e5f4421 | 225 | return ret; |
0b23fb36 IY |
226 | } |
227 | ||
228 | static int miiphy_wait_aneg(struct eth_device *dev) | |
229 | { | |
230 | uint32_t start; | |
13947f43 | 231 | int status; |
9e27e9dc | 232 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 233 | struct ethernet_regs *eth = fec->bus->priv; |
0b23fb36 IY |
234 | |
235 | /* | |
236 | * Wait for AN completion | |
237 | */ | |
a60d1e5b | 238 | start = get_timer(0); |
0b23fb36 IY |
239 | do { |
240 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
241 | printf("%s: Autonegotiation timeout\n", dev->name); | |
242 | return -1; | |
243 | } | |
244 | ||
13947f43 TK |
245 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
246 | if (status < 0) { | |
247 | printf("%s: Autonegotiation failed. status: %d\n", | |
0b23fb36 IY |
248 | dev->name, status); |
249 | return -1; | |
250 | } | |
8ef583a0 | 251 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
252 | |
253 | return 0; | |
254 | } | |
13947f43 TK |
255 | #endif |
256 | ||
0b23fb36 IY |
257 | static int fec_rx_task_enable(struct fec_priv *fec) |
258 | { | |
c0b5a3bb | 259 | writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); |
0b23fb36 IY |
260 | return 0; |
261 | } | |
262 | ||
263 | static int fec_rx_task_disable(struct fec_priv *fec) | |
264 | { | |
265 | return 0; | |
266 | } | |
267 | ||
268 | static int fec_tx_task_enable(struct fec_priv *fec) | |
269 | { | |
c0b5a3bb | 270 | writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); |
0b23fb36 IY |
271 | return 0; |
272 | } | |
273 | ||
274 | static int fec_tx_task_disable(struct fec_priv *fec) | |
275 | { | |
276 | return 0; | |
277 | } | |
278 | ||
279 | /** | |
280 | * Initialize receive task's buffer descriptors | |
281 | * @param[in] fec all we know about the device yet | |
282 | * @param[in] count receive buffer count to be allocated | |
5c1ad3e6 | 283 | * @param[in] dsize desired size of each receive buffer |
0b23fb36 IY |
284 | * @return 0 on success |
285 | * | |
286 | * For this task we need additional memory for the data buffers. And each | |
287 | * data buffer requires some alignment. Thy must be aligned to a specific | |
5c1ad3e6 | 288 | * boundary each. |
0b23fb36 | 289 | */ |
5c1ad3e6 | 290 | static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
0b23fb36 | 291 | { |
5c1ad3e6 EN |
292 | uint32_t size; |
293 | int i; | |
294 | ||
0b23fb36 | 295 | /* |
5c1ad3e6 EN |
296 | * Allocate memory for the buffers. This allocation respects the |
297 | * alignment | |
0b23fb36 | 298 | */ |
5c1ad3e6 EN |
299 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
300 | for (i = 0; i < count; i++) { | |
301 | uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); | |
302 | if (data_ptr == 0) { | |
303 | uint8_t *data = memalign(ARCH_DMA_MINALIGN, | |
304 | size); | |
305 | if (!data) { | |
306 | printf("%s: error allocating rxbuf %d\n", | |
307 | __func__, i); | |
308 | goto err; | |
309 | } | |
310 | writel((uint32_t)data, &fec->rbd_base[i].data_pointer); | |
311 | } /* needs allocation */ | |
312 | writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status); | |
313 | writew(0, &fec->rbd_base[i].data_length); | |
314 | } | |
315 | ||
316 | /* Mark the last RBD to close the ring. */ | |
317 | writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status); | |
0b23fb36 IY |
318 | fec->rbd_index = 0; |
319 | ||
320 | return 0; | |
5c1ad3e6 EN |
321 | |
322 | err: | |
323 | for (; i >= 0; i--) { | |
324 | uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); | |
325 | free((void *)data_ptr); | |
326 | } | |
327 | ||
328 | return -ENOMEM; | |
0b23fb36 IY |
329 | } |
330 | ||
331 | /** | |
332 | * Initialize transmit task's buffer descriptors | |
333 | * @param[in] fec all we know about the device yet | |
334 | * | |
335 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
336 | * Note: There is a race condition in the hardware. When only one BD is in | |
337 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
338 | * This bit in combination with the READY bit results into double transmit | |
339 | * of each data buffer. It seems the state machine checks READY earlier then | |
340 | * resetting it after the first transfer. | |
341 | * Using two BDs solves this issue. | |
342 | */ | |
343 | static void fec_tbd_init(struct fec_priv *fec) | |
344 | { | |
5c1ad3e6 EN |
345 | unsigned addr = (unsigned)fec->tbd_base; |
346 | unsigned size = roundup(2 * sizeof(struct fec_bd), | |
347 | ARCH_DMA_MINALIGN); | |
0b23fb36 IY |
348 | writew(0x0000, &fec->tbd_base[0].status); |
349 | writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); | |
350 | fec->tbd_index = 0; | |
5c1ad3e6 | 351 | flush_dcache_range(addr, addr+size); |
0b23fb36 IY |
352 | } |
353 | ||
354 | /** | |
355 | * Mark the given read buffer descriptor as free | |
356 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
357 | * @param[in] pRbd buffer descriptor to mark free again | |
358 | */ | |
359 | static void fec_rbd_clean(int last, struct fec_bd *pRbd) | |
360 | { | |
5c1ad3e6 | 361 | unsigned short flags = FEC_RBD_EMPTY; |
0b23fb36 | 362 | if (last) |
5c1ad3e6 EN |
363 | flags |= FEC_RBD_WRAP; |
364 | writew(flags, &pRbd->status); | |
0b23fb36 IY |
365 | writew(0, &pRbd->data_length); |
366 | } | |
367 | ||
be252b65 FE |
368 | static int fec_get_hwaddr(struct eth_device *dev, int dev_id, |
369 | unsigned char *mac) | |
0b23fb36 | 370 | { |
be252b65 | 371 | imx_get_mac_from_fuse(dev_id, mac); |
2e236bf2 | 372 | return !is_valid_ether_addr(mac); |
0b23fb36 IY |
373 | } |
374 | ||
4294b248 | 375 | static int fec_set_hwaddr(struct eth_device *dev) |
0b23fb36 | 376 | { |
4294b248 | 377 | uchar *mac = dev->enetaddr; |
0b23fb36 IY |
378 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
379 | ||
380 | writel(0, &fec->eth->iaddr1); | |
381 | writel(0, &fec->eth->iaddr2); | |
382 | writel(0, &fec->eth->gaddr1); | |
383 | writel(0, &fec->eth->gaddr2); | |
384 | ||
385 | /* | |
386 | * Set physical address | |
387 | */ | |
388 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], | |
389 | &fec->eth->paddr1); | |
390 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
13947f43 TK |
395 | static void fec_eth_phy_config(struct eth_device *dev) |
396 | { | |
397 | #ifdef CONFIG_PHYLIB | |
398 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
399 | struct phy_device *phydev; | |
400 | ||
401 | phydev = phy_connect(fec->bus, fec->phy_id, dev, | |
402 | PHY_INTERFACE_MODE_RGMII); | |
403 | if (phydev) { | |
404 | fec->phydev = phydev; | |
405 | phy_config(phydev); | |
406 | } | |
407 | #endif | |
408 | } | |
409 | ||
a5990b26 MV |
410 | /* |
411 | * Do initial configuration of the FEC registers | |
412 | */ | |
413 | static void fec_reg_setup(struct fec_priv *fec) | |
414 | { | |
415 | uint32_t rcntrl; | |
416 | ||
417 | /* | |
418 | * Set interrupt mask register | |
419 | */ | |
420 | writel(0x00000000, &fec->eth->imask); | |
421 | ||
422 | /* | |
423 | * Clear FEC-Lite interrupt event register(IEVENT) | |
424 | */ | |
425 | writel(0xffffffff, &fec->eth->ievent); | |
426 | ||
427 | ||
428 | /* | |
429 | * Set FEC-Lite receive control register(R_CNTRL): | |
430 | */ | |
431 | ||
432 | /* Start with frame length = 1518, common for all modes. */ | |
433 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
9d2d924a | 434 | if (fec->xcv_type != SEVENWIRE) /* xMII modes */ |
435 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
436 | if (fec->xcv_type == RGMII) | |
a5990b26 MV |
437 | rcntrl |= FEC_RCNTRL_RGMII; |
438 | else if (fec->xcv_type == RMII) | |
439 | rcntrl |= FEC_RCNTRL_RMII; | |
a5990b26 MV |
440 | |
441 | writel(rcntrl, &fec->eth->r_cntrl); | |
442 | } | |
443 | ||
0b23fb36 IY |
444 | /** |
445 | * Start the FEC engine | |
446 | * @param[in] dev Our device to handle | |
447 | */ | |
448 | static int fec_open(struct eth_device *edev) | |
449 | { | |
450 | struct fec_priv *fec = (struct fec_priv *)edev->priv; | |
28774cba | 451 | int speed; |
5c1ad3e6 EN |
452 | uint32_t addr, size; |
453 | int i; | |
0b23fb36 IY |
454 | |
455 | debug("fec_open: fec_open(dev)\n"); | |
456 | /* full-duplex, heartbeat disabled */ | |
457 | writel(1 << 2, &fec->eth->x_cntrl); | |
458 | fec->rbd_index = 0; | |
459 | ||
5c1ad3e6 EN |
460 | /* Invalidate all descriptors */ |
461 | for (i = 0; i < FEC_RBD_NUM - 1; i++) | |
462 | fec_rbd_clean(0, &fec->rbd_base[i]); | |
463 | fec_rbd_clean(1, &fec->rbd_base[i]); | |
464 | ||
465 | /* Flush the descriptors into RAM */ | |
466 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
467 | ARCH_DMA_MINALIGN); | |
468 | addr = (uint32_t)fec->rbd_base; | |
469 | flush_dcache_range(addr, addr + size); | |
470 | ||
28774cba | 471 | #ifdef FEC_QUIRK_ENET_MAC |
2ef2b950 JL |
472 | /* Enable ENET HW endian SWAP */ |
473 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
474 | &fec->eth->ecntrl); | |
475 | /* Enable ENET store and forward mode */ | |
476 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
477 | &fec->eth->x_wmrk); | |
478 | #endif | |
0b23fb36 IY |
479 | /* |
480 | * Enable FEC-Lite controller | |
481 | */ | |
cb17b92d JR |
482 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
483 | &fec->eth->ecntrl); | |
96912453 | 484 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) |
740d6ae5 JR |
485 | udelay(100); |
486 | /* | |
487 | * setup the MII gasket for RMII mode | |
488 | */ | |
489 | ||
490 | /* disable the gasket */ | |
491 | writew(0, &fec->eth->miigsk_enr); | |
492 | ||
493 | /* wait for the gasket to be disabled */ | |
494 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
495 | udelay(2); | |
496 | ||
497 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
498 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
499 | ||
500 | /* re-enable the gasket */ | |
501 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
502 | ||
503 | /* wait until MII gasket is ready */ | |
504 | int max_loops = 10; | |
505 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
506 | if (--max_loops <= 0) { | |
507 | printf("WAIT for MII Gasket ready timed out\n"); | |
508 | break; | |
509 | } | |
510 | } | |
511 | #endif | |
0b23fb36 | 512 | |
13947f43 TK |
513 | #ifdef CONFIG_PHYLIB |
514 | if (!fec->phydev) | |
515 | fec_eth_phy_config(edev); | |
516 | if (fec->phydev) { | |
517 | /* Start up the PHY */ | |
11af8d65 TT |
518 | int ret = phy_startup(fec->phydev); |
519 | ||
520 | if (ret) { | |
521 | printf("Could not initialize PHY %s\n", | |
522 | fec->phydev->dev->name); | |
523 | return ret; | |
524 | } | |
13947f43 TK |
525 | speed = fec->phydev->speed; |
526 | } else { | |
527 | speed = _100BASET; | |
528 | } | |
529 | #else | |
0b23fb36 | 530 | miiphy_wait_aneg(edev); |
28774cba | 531 | speed = miiphy_speed(edev->name, fec->phy_id); |
9e27e9dc | 532 | miiphy_duplex(edev->name, fec->phy_id); |
13947f43 | 533 | #endif |
0b23fb36 | 534 | |
28774cba TK |
535 | #ifdef FEC_QUIRK_ENET_MAC |
536 | { | |
537 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; | |
538 | u32 rcr = (readl(&fec->eth->r_cntrl) & | |
539 | ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | | |
540 | FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; | |
541 | if (speed == _1000BASET) | |
542 | ecr |= FEC_ECNTRL_SPEED; | |
543 | else if (speed != _100BASET) | |
544 | rcr |= FEC_RCNTRL_RMII_10T; | |
545 | writel(ecr, &fec->eth->ecntrl); | |
546 | writel(rcr, &fec->eth->r_cntrl); | |
547 | } | |
548 | #endif | |
549 | debug("%s:Speed=%i\n", __func__, speed); | |
550 | ||
0b23fb36 IY |
551 | /* |
552 | * Enable SmartDMA receive task | |
553 | */ | |
554 | fec_rx_task_enable(fec); | |
555 | ||
556 | udelay(100000); | |
557 | return 0; | |
558 | } | |
559 | ||
560 | static int fec_init(struct eth_device *dev, bd_t* bd) | |
561 | { | |
0b23fb36 | 562 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
9e27e9dc | 563 | uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; |
5c1ad3e6 EN |
564 | uint32_t size; |
565 | int i, ret; | |
0b23fb36 | 566 | |
e9319f11 JR |
567 | /* Initialize MAC address */ |
568 | fec_set_hwaddr(dev); | |
569 | ||
0b23fb36 | 570 | /* |
5c1ad3e6 EN |
571 | * Allocate transmit descriptors, there are two in total. This |
572 | * allocation respects cache alignment. | |
0b23fb36 | 573 | */ |
5c1ad3e6 EN |
574 | if (!fec->tbd_base) { |
575 | size = roundup(2 * sizeof(struct fec_bd), | |
576 | ARCH_DMA_MINALIGN); | |
577 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
578 | if (!fec->tbd_base) { | |
579 | ret = -ENOMEM; | |
580 | goto err1; | |
581 | } | |
582 | memset(fec->tbd_base, 0, size); | |
583 | fec_tbd_init(fec); | |
584 | flush_dcache_range((unsigned)fec->tbd_base, size); | |
0b23fb36 | 585 | } |
0b23fb36 | 586 | |
5c1ad3e6 EN |
587 | /* |
588 | * Allocate receive descriptors. This allocation respects cache | |
589 | * alignment. | |
590 | */ | |
591 | if (!fec->rbd_base) { | |
592 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
593 | ARCH_DMA_MINALIGN); | |
594 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
595 | if (!fec->rbd_base) { | |
596 | ret = -ENOMEM; | |
597 | goto err2; | |
598 | } | |
599 | memset(fec->rbd_base, 0, size); | |
600 | /* | |
601 | * Initialize RxBD ring | |
602 | */ | |
603 | if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { | |
604 | ret = -ENOMEM; | |
605 | goto err3; | |
606 | } | |
607 | flush_dcache_range((unsigned)fec->rbd_base, | |
608 | (unsigned)fec->rbd_base + size); | |
609 | } | |
0b23fb36 | 610 | |
a5990b26 | 611 | fec_reg_setup(fec); |
9eb3770b | 612 | |
f41471e6 | 613 | if (fec->xcv_type != SEVENWIRE) |
575c5cc0 | 614 | fec_mii_setspeed(fec->bus->priv); |
9eb3770b | 615 | |
0b23fb36 IY |
616 | /* |
617 | * Set Opcode/Pause Duration Register | |
618 | */ | |
619 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ | |
620 | writel(0x2, &fec->eth->x_wmrk); | |
621 | /* | |
622 | * Set multicast address filter | |
623 | */ | |
624 | writel(0x00000000, &fec->eth->gaddr1); | |
625 | writel(0x00000000, &fec->eth->gaddr2); | |
626 | ||
627 | ||
628 | /* clear MIB RAM */ | |
9e27e9dc MV |
629 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) |
630 | writel(0, i); | |
0b23fb36 IY |
631 | |
632 | /* FIFO receive start register */ | |
633 | writel(0x520, &fec->eth->r_fstart); | |
634 | ||
635 | /* size and address of each buffer */ | |
636 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
637 | writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); | |
638 | writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); | |
639 | ||
13947f43 | 640 | #ifndef CONFIG_PHYLIB |
0b23fb36 IY |
641 | if (fec->xcv_type != SEVENWIRE) |
642 | miiphy_restart_aneg(dev); | |
13947f43 | 643 | #endif |
0b23fb36 IY |
644 | fec_open(dev); |
645 | return 0; | |
5c1ad3e6 EN |
646 | |
647 | err3: | |
648 | free(fec->rbd_base); | |
649 | err2: | |
650 | free(fec->tbd_base); | |
651 | err1: | |
652 | return ret; | |
0b23fb36 IY |
653 | } |
654 | ||
655 | /** | |
656 | * Halt the FEC engine | |
657 | * @param[in] dev Our device to handle | |
658 | */ | |
659 | static void fec_halt(struct eth_device *dev) | |
660 | { | |
9e27e9dc | 661 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
0b23fb36 IY |
662 | int counter = 0xffff; |
663 | ||
664 | /* | |
665 | * issue graceful stop command to the FEC transmitter if necessary | |
666 | */ | |
cb17b92d | 667 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
0b23fb36 IY |
668 | &fec->eth->x_cntrl); |
669 | ||
670 | debug("eth_halt: wait for stop regs\n"); | |
671 | /* | |
672 | * wait for graceful stop to register | |
673 | */ | |
674 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) | |
cb17b92d | 675 | udelay(1); |
0b23fb36 IY |
676 | |
677 | /* | |
678 | * Disable SmartDMA tasks | |
679 | */ | |
680 | fec_tx_task_disable(fec); | |
681 | fec_rx_task_disable(fec); | |
682 | ||
683 | /* | |
684 | * Disable the Ethernet Controller | |
685 | * Note: this will also reset the BD index counter! | |
686 | */ | |
740d6ae5 JR |
687 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
688 | &fec->eth->ecntrl); | |
0b23fb36 IY |
689 | fec->rbd_index = 0; |
690 | fec->tbd_index = 0; | |
0b23fb36 IY |
691 | debug("eth_halt: done\n"); |
692 | } | |
693 | ||
694 | /** | |
695 | * Transmit one frame | |
696 | * @param[in] dev Our ethernet device to handle | |
697 | * @param[in] packet Pointer to the data to be transmitted | |
698 | * @param[in] length Data count in bytes | |
699 | * @return 0 on success | |
700 | */ | |
442dac4c | 701 | static int fec_send(struct eth_device *dev, void *packet, int length) |
0b23fb36 IY |
702 | { |
703 | unsigned int status; | |
efe24d2e | 704 | uint32_t size, end; |
5c1ad3e6 | 705 | uint32_t addr; |
bc1ce150 MV |
706 | int timeout = FEC_XFER_TIMEOUT; |
707 | int ret = 0; | |
0b23fb36 IY |
708 | |
709 | /* | |
710 | * This routine transmits one frame. This routine only accepts | |
711 | * 6-byte Ethernet addresses. | |
712 | */ | |
713 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
714 | ||
715 | /* | |
716 | * Check for valid length of data. | |
717 | */ | |
718 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 719 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
720 | return -1; |
721 | } | |
722 | ||
723 | /* | |
5c1ad3e6 EN |
724 | * Setup the transmit buffer. We are always using the first buffer for |
725 | * transmission, the second will be empty and only used to stop the DMA | |
726 | * engine. We also flush the packet to RAM here to avoid cache trouble. | |
0b23fb36 | 727 | */ |
5c1ad3e6 | 728 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
729 | swap_packet((uint32_t *)packet, length); |
730 | #endif | |
5c1ad3e6 EN |
731 | |
732 | addr = (uint32_t)packet; | |
efe24d2e MV |
733 | end = roundup(addr + length, ARCH_DMA_MINALIGN); |
734 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
735 | flush_dcache_range(addr, end); | |
5c1ad3e6 | 736 | |
0b23fb36 | 737 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
5c1ad3e6 EN |
738 | writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
739 | ||
0b23fb36 IY |
740 | /* |
741 | * update BD's status now | |
742 | * This block: | |
743 | * - is always the last in a chain (means no chain) | |
744 | * - should transmitt the CRC | |
745 | * - might be the last BD in the list, so the address counter should | |
746 | * wrap (-> keep the WRAP flag) | |
747 | */ | |
748 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
749 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
750 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
751 | ||
5c1ad3e6 EN |
752 | /* |
753 | * Flush data cache. This code flushes both TX descriptors to RAM. | |
754 | * After this code, the descriptors will be safely in RAM and we | |
755 | * can start DMA. | |
756 | */ | |
757 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
758 | addr = (uint32_t)fec->tbd_base; | |
759 | flush_dcache_range(addr, addr + size); | |
760 | ||
0b23fb36 IY |
761 | /* |
762 | * Enable SmartDMA transmit task | |
763 | */ | |
764 | fec_tx_task_enable(fec); | |
765 | ||
766 | /* | |
5c1ad3e6 EN |
767 | * Wait until frame is sent. On each turn of the wait cycle, we must |
768 | * invalidate data cache to see what's really in RAM. Also, we need | |
769 | * barrier here. | |
0b23fb36 | 770 | */ |
67449098 | 771 | while (--timeout) { |
c0b5a3bb | 772 | if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) |
bc1ce150 | 773 | break; |
0b23fb36 | 774 | } |
5c1ad3e6 | 775 | |
67449098 MV |
776 | if (!timeout) |
777 | ret = -EINVAL; | |
778 | ||
779 | invalidate_dcache_range(addr, addr + size); | |
780 | if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) | |
781 | ret = -EINVAL; | |
782 | ||
783 | debug("fec_send: status 0x%x index %d ret %i\n", | |
0b23fb36 | 784 | readw(&fec->tbd_base[fec->tbd_index].status), |
67449098 | 785 | fec->tbd_index, ret); |
0b23fb36 IY |
786 | /* for next transmission use the other buffer */ |
787 | if (fec->tbd_index) | |
788 | fec->tbd_index = 0; | |
789 | else | |
790 | fec->tbd_index = 1; | |
791 | ||
bc1ce150 | 792 | return ret; |
0b23fb36 IY |
793 | } |
794 | ||
795 | /** | |
796 | * Pull one frame from the card | |
797 | * @param[in] dev Our ethernet device to handle | |
798 | * @return Length of packet read | |
799 | */ | |
800 | static int fec_recv(struct eth_device *dev) | |
801 | { | |
802 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
803 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; | |
804 | unsigned long ievent; | |
805 | int frame_length, len = 0; | |
806 | struct nbuf *frame; | |
807 | uint16_t bd_status; | |
efe24d2e | 808 | uint32_t addr, size, end; |
5c1ad3e6 | 809 | int i; |
e2a66e60 | 810 | uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN); |
0b23fb36 IY |
811 | |
812 | /* | |
813 | * Check if any critical events have happened | |
814 | */ | |
815 | ievent = readl(&fec->eth->ievent); | |
816 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 817 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 IY |
818 | if (ievent & FEC_IEVENT_BABR) { |
819 | fec_halt(dev); | |
820 | fec_init(dev, fec->bd); | |
821 | printf("some error: 0x%08lx\n", ievent); | |
822 | return 0; | |
823 | } | |
824 | if (ievent & FEC_IEVENT_HBERR) { | |
825 | /* Heartbeat error */ | |
826 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
827 | &fec->eth->x_cntrl); | |
828 | } | |
829 | if (ievent & FEC_IEVENT_GRA) { | |
830 | /* Graceful stop complete */ | |
831 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
832 | fec_halt(dev); | |
833 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), | |
834 | &fec->eth->x_cntrl); | |
835 | fec_init(dev, fec->bd); | |
836 | } | |
837 | } | |
838 | ||
839 | /* | |
5c1ad3e6 EN |
840 | * Read the buffer status. Before the status can be read, the data cache |
841 | * must be invalidated, because the data in RAM might have been changed | |
842 | * by DMA. The descriptors are properly aligned to cachelines so there's | |
843 | * no need to worry they'd overlap. | |
844 | * | |
845 | * WARNING: By invalidating the descriptor here, we also invalidate | |
846 | * the descriptors surrounding this one. Therefore we can NOT change the | |
847 | * contents of this descriptor nor the surrounding ones. The problem is | |
848 | * that in order to mark the descriptor as processed, we need to change | |
849 | * the descriptor. The solution is to mark the whole cache line when all | |
850 | * descriptors in the cache line are processed. | |
0b23fb36 | 851 | */ |
5c1ad3e6 EN |
852 | addr = (uint32_t)rbd; |
853 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
854 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
855 | invalidate_dcache_range(addr, addr + size); | |
856 | ||
0b23fb36 IY |
857 | bd_status = readw(&rbd->status); |
858 | debug("fec_recv: status 0x%x\n", bd_status); | |
859 | ||
860 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
861 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
862 | ((readw(&rbd->data_length) - 4) > 14)) { | |
863 | /* | |
864 | * Get buffer address and size | |
865 | */ | |
866 | frame = (struct nbuf *)readl(&rbd->data_pointer); | |
867 | frame_length = readw(&rbd->data_length) - 4; | |
5c1ad3e6 EN |
868 | /* |
869 | * Invalidate data cache over the buffer | |
870 | */ | |
871 | addr = (uint32_t)frame; | |
efe24d2e MV |
872 | end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); |
873 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
874 | invalidate_dcache_range(addr, end); | |
5c1ad3e6 | 875 | |
0b23fb36 IY |
876 | /* |
877 | * Fill the buffer and pass it to upper layers | |
878 | */ | |
5c1ad3e6 | 879 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
880 | swap_packet((uint32_t *)frame->data, frame_length); |
881 | #endif | |
0b23fb36 IY |
882 | memcpy(buff, frame->data, frame_length); |
883 | NetReceive(buff, frame_length); | |
884 | len = frame_length; | |
885 | } else { | |
886 | if (bd_status & FEC_RBD_ERR) | |
887 | printf("error frame: 0x%08lx 0x%08x\n", | |
888 | (ulong)rbd->data_pointer, | |
889 | bd_status); | |
890 | } | |
5c1ad3e6 | 891 | |
0b23fb36 | 892 | /* |
5c1ad3e6 EN |
893 | * Free the current buffer, restart the engine and move forward |
894 | * to the next buffer. Here we check if the whole cacheline of | |
895 | * descriptors was already processed and if so, we mark it free | |
896 | * as whole. | |
0b23fb36 | 897 | */ |
5c1ad3e6 EN |
898 | size = RXDESC_PER_CACHELINE - 1; |
899 | if ((fec->rbd_index & size) == size) { | |
900 | i = fec->rbd_index - size; | |
901 | addr = (uint32_t)&fec->rbd_base[i]; | |
902 | for (; i <= fec->rbd_index ; i++) { | |
903 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), | |
904 | &fec->rbd_base[i]); | |
905 | } | |
906 | flush_dcache_range(addr, | |
907 | addr + ARCH_DMA_MINALIGN); | |
908 | } | |
909 | ||
0b23fb36 IY |
910 | fec_rx_task_enable(fec); |
911 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
912 | } | |
913 | debug("fec_recv: stop\n"); | |
914 | ||
915 | return len; | |
916 | } | |
917 | ||
9e27e9dc | 918 | static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) |
0b23fb36 | 919 | { |
0b23fb36 | 920 | struct eth_device *edev; |
9e27e9dc | 921 | struct fec_priv *fec; |
13947f43 | 922 | struct mii_dev *bus; |
0b23fb36 | 923 | unsigned char ethaddr[6]; |
e382fb48 MV |
924 | uint32_t start; |
925 | int ret = 0; | |
0b23fb36 IY |
926 | |
927 | /* create and fill edev struct */ | |
928 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
929 | if (!edev) { | |
9e27e9dc | 930 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
e382fb48 MV |
931 | ret = -ENOMEM; |
932 | goto err1; | |
9e27e9dc MV |
933 | } |
934 | ||
935 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); | |
936 | if (!fec) { | |
937 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); | |
e382fb48 MV |
938 | ret = -ENOMEM; |
939 | goto err2; | |
0b23fb36 | 940 | } |
9e27e9dc | 941 | |
de0b9576 | 942 | memset(edev, 0, sizeof(*edev)); |
9e27e9dc MV |
943 | memset(fec, 0, sizeof(*fec)); |
944 | ||
0b23fb36 IY |
945 | edev->priv = fec; |
946 | edev->init = fec_init; | |
947 | edev->send = fec_send; | |
948 | edev->recv = fec_recv; | |
949 | edev->halt = fec_halt; | |
fb57ec97 | 950 | edev->write_hwaddr = fec_set_hwaddr; |
0b23fb36 | 951 | |
9e27e9dc | 952 | fec->eth = (struct ethernet_regs *)base_addr; |
0b23fb36 IY |
953 | fec->bd = bd; |
954 | ||
392b8502 | 955 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
0b23fb36 IY |
956 | |
957 | /* Reset chip. */ | |
cb17b92d | 958 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
e382fb48 MV |
959 | start = get_timer(0); |
960 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
961 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
962 | printf("FEC MXC: Timeout reseting chip\n"); | |
963 | goto err3; | |
964 | } | |
0b23fb36 | 965 | udelay(10); |
e382fb48 | 966 | } |
0b23fb36 | 967 | |
a5990b26 | 968 | fec_reg_setup(fec); |
0b23fb36 | 969 | |
9e27e9dc MV |
970 | if (dev_id == -1) { |
971 | sprintf(edev->name, "FEC"); | |
972 | fec->dev_id = 0; | |
973 | } else { | |
974 | sprintf(edev->name, "FEC%i", dev_id); | |
975 | fec->dev_id = dev_id; | |
976 | } | |
977 | fec->phy_id = phy_id; | |
0b23fb36 | 978 | |
13947f43 TK |
979 | bus = mdio_alloc(); |
980 | if (!bus) { | |
981 | printf("mdio_alloc failed\n"); | |
982 | ret = -ENOMEM; | |
983 | goto err3; | |
984 | } | |
985 | bus->read = fec_phy_read; | |
986 | bus->write = fec_phy_write; | |
987 | sprintf(bus->name, edev->name); | |
5c1ad3e6 | 988 | #ifdef CONFIG_MX28 |
13947f43 TK |
989 | /* |
990 | * The i.MX28 has two ethernet interfaces, but they are not equal. | |
991 | * Only the first one can access the MDIO bus. | |
992 | */ | |
993 | bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE; | |
994 | #else | |
995 | bus->priv = fec->eth; | |
996 | #endif | |
575c5cc0 | 997 | fec_mii_setspeed(bus->priv); |
13947f43 TK |
998 | ret = mdio_register(bus); |
999 | if (ret) { | |
1000 | printf("mdio_register failed\n"); | |
1001 | free(bus); | |
1002 | ret = -ENOMEM; | |
1003 | goto err3; | |
1004 | } | |
1005 | fec->bus = bus; | |
0b23fb36 IY |
1006 | eth_register(edev); |
1007 | ||
be252b65 FE |
1008 | if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { |
1009 | debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); | |
4294b248 | 1010 | memcpy(edev->enetaddr, ethaddr, 6); |
0b23fb36 | 1011 | } |
13947f43 TK |
1012 | /* Configure phy */ |
1013 | fec_eth_phy_config(edev); | |
e382fb48 MV |
1014 | return ret; |
1015 | ||
1016 | err3: | |
1017 | free(fec); | |
1018 | err2: | |
1019 | free(edev); | |
1020 | err1: | |
1021 | return ret; | |
0b23fb36 IY |
1022 | } |
1023 | ||
9e27e9dc MV |
1024 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) |
1025 | { | |
9e27e9dc | 1026 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); |
eef24480 TK |
1027 | return fec_probe(bd, dev_id, phy_id, addr); |
1028 | } | |
0b23fb36 | 1029 | |
eef24480 TK |
1030 | #ifdef CONFIG_FEC_MXC_PHYADDR |
1031 | int fecmxc_initialize(bd_t *bd) | |
1032 | { | |
1033 | return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, | |
1034 | IMX_FEC_BASE); | |
0b23fb36 | 1035 | } |
eef24480 | 1036 | #endif |
2e5f4421 | 1037 | |
13947f43 | 1038 | #ifndef CONFIG_PHYLIB |
2e5f4421 MV |
1039 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) |
1040 | { | |
1041 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
1042 | fec->mii_postcall = cb; | |
1043 | return 0; | |
1044 | } | |
13947f43 | 1045 | #endif |