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x86/kvmclock: convert to SPDX identifiers
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
3b8a5df6 139unsigned int __read_mostly lapic_timer_advance_ns = 1000;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
c595ceee 198 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 199 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
200 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
201 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
202 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
203 { "mmu_flooded", VM_STAT(mmu_flooded) },
204 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 205 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 206 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 207 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 208 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 209 { "max_mmu_page_hash_collisions",
210 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 211 { NULL }
212};
213
2acf923e
DC		 214u64 __read_mostly host_xcr0;
215
b666a4b6
MO		 216struct kmem_cache *x86_fpu_cache;
217EXPORT_SYMBOL_GPL(x86_fpu_cache);
218
b6785def 219static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 220
af585b92
GN		 221static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
222{
223 int i;
224 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
225 vcpu->arch.apf.gfns[i] = ~0;
226}
227
18863bdd
AK		 228static void kvm_on_user_return(struct user_return_notifier *urn)
229{
230 unsigned slot;
18863bdd
AK		 231 struct kvm_shared_msrs *locals
232 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 233 struct kvm_shared_msr_values *values;
1650b4eb
IA		 234 unsigned long flags;
235
236 /*
237 * Disabling irqs at this point since the following code could be
238 * interrupted and executed through kvm_arch_hardware_disable()
239 */
240 local_irq_save(flags);
241 if (locals->registered) {
242 locals->registered = false;
243 user_return_notifier_unregister(urn);
244 }
245 local_irq_restore(flags);
18863bdd 246 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 247 values = &locals->values[slot];
248 if (values->host != values->curr) {
249 wrmsrl(shared_msrs_global.msrs[slot], values->host);
250 values->curr = values->host;
18863bdd
AK		 251 }
252 }
18863bdd
AK		 253}
254
2bf78fa7 255static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 256{
18863bdd 257 u64 value;
013f6a5d
MT		 258 unsigned int cpu = smp_processor_id();
259 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 260
2bf78fa7
SY		 261 /* only read, and nobody should modify it at this time,
262 * so don't need lock */
263 if (slot >= shared_msrs_global.nr) {
264 printk(KERN_ERR "kvm: invalid MSR slot!");
265 return;
266 }
267 rdmsrl_safe(msr, &value);
268 smsr->values[slot].host = value;
269 smsr->values[slot].curr = value;
270}
271
272void kvm_define_shared_msr(unsigned slot, u32 msr)
273{
0123be42 274 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 275 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 276 if (slot >= shared_msrs_global.nr)
277 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 278}
279EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
280
281static void kvm_shared_msr_cpu_online(void)
282{
283 unsigned i;
18863bdd
AK		 284
285 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 286 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 287}
288
8b3c3104 289int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 290{
013f6a5d
MT		 291 unsigned int cpu = smp_processor_id();
292 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 293 int err;
18863bdd 294
2bf78fa7 295 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 296 return 0;
2bf78fa7 297 smsr->values[slot].curr = value;
8b3c3104
AH		 298 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
299 if (err)
300 return 1;
301
18863bdd
AK		 302 if (!smsr->registered) {
303 smsr->urn.on_user_return = kvm_on_user_return;
304 user_return_notifier_register(&smsr->urn);
305 smsr->registered = true;
306 }
8b3c3104 307 return 0;
18863bdd
AK		 308}
309EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
310
13a34e06 311static void drop_user_return_notifiers(void)
3548bab5 312{
013f6a5d
MT		 313 unsigned int cpu = smp_processor_id();
314 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 315
316 if (smsr->registered)
317 kvm_on_user_return(&smsr->urn);
318}
319
6866b83e
CO		 320u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
321{
8a5a87d9 322 return vcpu->arch.apic_base;
6866b83e
CO		 323}
324EXPORT_SYMBOL_GPL(kvm_get_apic_base);
325
58871649
JM		 326enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
327{
328 return kvm_apic_mode(kvm_get_apic_base(vcpu));
329}
330EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
331
58cb628d
JK		 332int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
333{
58871649
JM		 334 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
335 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 336 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
337 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 338
58871649 339 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 340 return 1;
58871649
JM		 341 if (!msr_info->host_initiated) {
342 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
343 return 1;
344 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
345 return 1;
346 }
58cb628d
JK		 347
348 kvm_lapic_set_base(vcpu, msr_info->data);
349 return 0;
6866b83e
CO		 350}
351EXPORT_SYMBOL_GPL(kvm_set_apic_base);
352
2605fc21 353asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 354{
355 /* Fault while not rebooting. We want the trace. */
356 BUG();
357}
358EXPORT_SYMBOL_GPL(kvm_spurious_fault);
359
3fd28fce
ED		 360#define EXCPT_BENIGN 0
361#define EXCPT_CONTRIBUTORY 1
362#define EXCPT_PF 2
363
364static int exception_class(int vector)
365{
366 switch (vector) {
367 case PF_VECTOR:
368 return EXCPT_PF;
369 case DE_VECTOR:
370 case TS_VECTOR:
371 case NP_VECTOR:
372 case SS_VECTOR:
373 case GP_VECTOR:
374 return EXCPT_CONTRIBUTORY;
375 default:
376 break;
377 }
378 return EXCPT_BENIGN;
379}
380
d6e8c854
NA		 381#define EXCPT_FAULT 0
382#define EXCPT_TRAP 1
383#define EXCPT_ABORT 2
384#define EXCPT_INTERRUPT 3
385
386static int exception_type(int vector)
387{
388 unsigned int mask;
389
390 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
391 return EXCPT_INTERRUPT;
392
393 mask = 1 << vector;
394
395 /* #DB is trap, as instruction watchpoints are handled elsewhere */
396 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
397 return EXCPT_TRAP;
398
399 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
400 return EXCPT_ABORT;
401
402 /* Reserved exceptions will result in fault */
403 return EXCPT_FAULT;
404}
405
da998b46
JM		 406void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
407{
408 unsigned nr = vcpu->arch.exception.nr;
409 bool has_payload = vcpu->arch.exception.has_payload;
410 unsigned long payload = vcpu->arch.exception.payload;
411
412 if (!has_payload)
413 return;
414
415 switch (nr) {
f10c729f
JM		 416 case DB_VECTOR:
417 /*
418 * "Certain debug exceptions may clear bit 0-3. The
419 * remaining contents of the DR6 register are never
420 * cleared by the processor".
421 */
422 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
423 /*
424 * DR6.RTM is set by all #DB exceptions that don't clear it.
425 */
426 vcpu->arch.dr6 |= DR6_RTM;
427 vcpu->arch.dr6 |= payload;
428 /*
429 * Bit 16 should be set in the payload whenever the #DB
430 * exception should clear DR6.RTM. This makes the payload
431 * compatible with the pending debug exceptions under VMX.
432 * Though not currently documented in the SDM, this also
433 * makes the payload compatible with the exit qualification
434 * for #DB exceptions under VMX.
435 */
436 vcpu->arch.dr6 ^= payload & DR6_RTM;
437 break;
da998b46
JM		 438 case PF_VECTOR:
439 vcpu->arch.cr2 = payload;
440 break;
441 }
442
443 vcpu->arch.exception.has_payload = false;
444 vcpu->arch.exception.payload = 0;
445}
446EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
447
3fd28fce 448static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 449 unsigned nr, bool has_error, u32 error_code,
91e86d22 450 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 451{
452 u32 prev_nr;
453 int class1, class2;
454
3842d135
AK		 455 kvm_make_request(KVM_REQ_EVENT, vcpu);
456
664f8e26 457 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 458 queue:
3ffb2468
NA		 459 if (has_error && !is_protmode(vcpu))
460 has_error = false;
664f8e26
WL		 461 if (reinject) {
462 /*
463 * On vmentry, vcpu->arch.exception.pending is only
464 * true if an event injection was blocked by
465 * nested_run_pending. In that case, however,
466 * vcpu_enter_guest requests an immediate exit,
467 * and the guest shouldn't proceed far enough to
468 * need reinjection.
469 */
470 WARN_ON_ONCE(vcpu->arch.exception.pending);
471 vcpu->arch.exception.injected = true;
91e86d22
JM		 472 if (WARN_ON_ONCE(has_payload)) {
473 /*
474 * A reinjected event has already
475 * delivered its payload.
476 */
477 has_payload = false;
478 payload = 0;
479 }
664f8e26
WL		 480 } else {
481 vcpu->arch.exception.pending = true;
482 vcpu->arch.exception.injected = false;
483 }
3fd28fce
ED		 484 vcpu->arch.exception.has_error_code = has_error;
485 vcpu->arch.exception.nr = nr;
486 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 487 vcpu->arch.exception.has_payload = has_payload;
488 vcpu->arch.exception.payload = payload;
da998b46
JM		 489 /*
490 * In guest mode, payload delivery should be deferred,
491 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 492 * CR2 is modified (or intercept #DB before DR6 is
493 * modified under nVMX). However, for ABI
494 * compatibility with KVM_GET_VCPU_EVENTS and
495 * KVM_SET_VCPU_EVENTS, we can't delay payload
496 * delivery unless userspace has enabled this
497 * functionality via the per-VM capability,
498 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 499 */
500 if (!vcpu->kvm->arch.exception_payload_enabled ||
501 !is_guest_mode(vcpu))
502 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 503 return;
504 }
505
506 /* to check exception */
507 prev_nr = vcpu->arch.exception.nr;
508 if (prev_nr == DF_VECTOR) {
509 /* triple fault -> shutdown */
a8eeb04a 510 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 511 return;
512 }
513 class1 = exception_class(prev_nr);
514 class2 = exception_class(nr);
515 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
516 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 517 /*
518 * Generate double fault per SDM Table 5-5. Set
519 * exception.pending = true so that the double fault
520 * can trigger a nested vmexit.
521 */
3fd28fce 522 vcpu->arch.exception.pending = true;
664f8e26 523 vcpu->arch.exception.injected = false;
3fd28fce
ED		 524 vcpu->arch.exception.has_error_code = true;
525 vcpu->arch.exception.nr = DF_VECTOR;
526 vcpu->arch.exception.error_code = 0;
c851436a
JM		 527 vcpu->arch.exception.has_payload = false;
528 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 529 } else
530 /* replace previous exception with a new one in a hope
531 that instruction re-execution will regenerate lost
532 exception */
533 goto queue;
534}
535
298101da
AK		 536void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
537{
91e86d22 538 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 539}
540EXPORT_SYMBOL_GPL(kvm_queue_exception);
541
ce7ddec4
JR		 542void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
543{
91e86d22 544 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 545}
546EXPORT_SYMBOL_GPL(kvm_requeue_exception);
547
f10c729f
JM		 548static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
549 unsigned long payload)
550{
551 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
552}
553
da998b46
JM		 554static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
555 u32 error_code, unsigned long payload)
556{
557 kvm_multiple_exception(vcpu, nr, true, error_code,
558 true, payload, false);
559}
560
6affcbed 561int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 562{
db8fcefa
AP		 563 if (err)
564 kvm_inject_gp(vcpu, 0);
565 else
6affcbed
KH		 566 return kvm_skip_emulated_instruction(vcpu);
567
568 return 1;
db8fcefa
AP		 569}
570EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 571
6389ee94 572void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 573{
574 ++vcpu->stat.pf_guest;
adfe20fb
WL		 575 vcpu->arch.exception.nested_apf =
576 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 577 if (vcpu->arch.exception.nested_apf) {
adfe20fb 578 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 579 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
580 } else {
581 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
582 fault->address);
583 }
c3c91fee 584}
27d6c865 585EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 586
ef54bcfe 587static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 588{
6389ee94
AK		 589 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
590 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 591 else
44dd3ffa 592 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 593
594 return fault->nested_page_fault;
d4f8cf66
JR		 595}
596
3419ffc8
SY		 597void kvm_inject_nmi(struct kvm_vcpu *vcpu)
598{
7460fb4a
AK		 599 atomic_inc(&vcpu->arch.nmi_queued);
600 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 601}
602EXPORT_SYMBOL_GPL(kvm_inject_nmi);
603
298101da
AK		 604void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
605{
91e86d22 606 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 607}
608EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
609
ce7ddec4
JR		 610void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
611{
91e86d22 612 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 613}
614EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
615
0a79b009
AK		 616/*
617 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
618 * a #GP and return false.
619 */
620bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 621{
0a79b009
AK		 622 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
623 return true;
624 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
625 return false;
298101da 626}
0a79b009 627EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 628
16f8a6f9
NA		 629bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
630{
631 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
632 return true;
633
634 kvm_queue_exception(vcpu, UD_VECTOR);
635 return false;
636}
637EXPORT_SYMBOL_GPL(kvm_require_dr);
638
ec92fe44
JR		 639/*
640 * This function will be used to read from the physical memory of the currently
54bf36aa 641 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 642 * can read from guest physical or from the guest's guest physical memory.
643 */
644int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
645 gfn_t ngfn, void *data, int offset, int len,
646 u32 access)
647{
54987b7a 648 struct x86_exception exception;
ec92fe44
JR		 649 gfn_t real_gfn;
650 gpa_t ngpa;
651
652 ngpa = gfn_to_gpa(ngfn);
54987b7a 653 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 654 if (real_gfn == UNMAPPED_GVA)
655 return -EFAULT;
656
657 real_gfn = gpa_to_gfn(real_gfn);
658
54bf36aa 659 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 660}
661EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
662
69b0049a 663static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 664 void *data, int offset, int len, u32 access)
665{
666 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
667 data, offset, len, access);
668}
669
a03490ed
CO		 670/*
671 * Load the pae pdptrs. Return true is they are all valid.
672 */
ff03a073 673int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 674{
675 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
676 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
677 int i;
678 int ret;
ff03a073 679 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 680
ff03a073
JR		 681 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
682 offset * sizeof(u64), sizeof(pdpte),
683 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 684 if (ret < 0) {
685 ret = 0;
686 goto out;
687 }
688 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 689 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 690 (pdpte[i] &
44dd3ffa 691 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 692 ret = 0;
693 goto out;
694 }
695 }
696 ret = 1;
697
ff03a073 698 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 699 __set_bit(VCPU_EXREG_PDPTR,
700 (unsigned long *)&vcpu->arch.regs_avail);
701 __set_bit(VCPU_EXREG_PDPTR,
702 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 703out:
a03490ed
CO		 704
705 return ret;
706}
cc4b6871 707EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 708
9ed38ffa 709bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 710{
ff03a073 711 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 712 bool changed = true;
3d06b8bf
JR		 713 int offset;
714 gfn_t gfn;
d835dfec
AK		 715 int r;
716
d35b34a9 717 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 718 return false;
719
6de4f3ad
AK		 720 if (!test_bit(VCPU_EXREG_PDPTR,
721 (unsigned long *)&vcpu->arch.regs_avail))
722 return true;
723
a512177e
PB		 724 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
725 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 726 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
727 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 728 if (r < 0)
729 goto out;
ff03a073 730 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 731out:
d835dfec
AK		 732
733 return changed;
734}
9ed38ffa 735EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 736
49a9b07e 737int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 738{
aad82703 739 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 740 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 741
f9a48e6a
AK		 742 cr0 |= X86_CR0_ET;
743
ab344828 744#ifdef CONFIG_X86_64
0f12244f
GN		 745 if (cr0 & 0xffffffff00000000UL)
746 return 1;
ab344828
GN		 747#endif
748
749 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 750
0f12244f
GN		 751 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
752 return 1;
a03490ed 753
0f12244f
GN		 754 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
755 return 1;
a03490ed
CO		 756
757 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
758#ifdef CONFIG_X86_64
f6801dff 759 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 760 int cs_db, cs_l;
761
0f12244f
GN		 762 if (!is_pae(vcpu))
763 return 1;
a03490ed 764 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 765 if (cs_l)
766 return 1;
a03490ed
CO		 767 } else
768#endif
ff03a073 769 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 770 kvm_read_cr3(vcpu)))
0f12244f 771 return 1;
a03490ed
CO		 772 }
773
ad756a16
MJ		 774 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
775 return 1;
776
a03490ed 777 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 778
d170c419 779 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 780 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 781 kvm_async_pf_hash_reset(vcpu);
782 }
e5f3f027 783
aad82703
SY		 784 if ((cr0 ^ old_cr0) & update_bits)
785 kvm_mmu_reset_context(vcpu);
b18d5431 786
879ae188
LE		 787 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
788 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
789 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 790 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
791
0f12244f
GN		 792 return 0;
793}
2d3ad1f4 794EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 795
2d3ad1f4 796void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 797{
49a9b07e 798 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 799}
2d3ad1f4 800EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 801
42bdf991
MT		 802static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
803{
804 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
805 !vcpu->guest_xcr0_loaded) {
806 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 807 if (vcpu->arch.xcr0 != host_xcr0)
808 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 809 vcpu->guest_xcr0_loaded = 1;
810 }
811}
812
813static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
814{
815 if (vcpu->guest_xcr0_loaded) {
816 if (vcpu->arch.xcr0 != host_xcr0)
817 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
818 vcpu->guest_xcr0_loaded = 0;
819 }
820}
821
69b0049a 822static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 823{
56c103ec
LJ		 824 u64 xcr0 = xcr;
825 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 826 u64 valid_bits;
2acf923e
DC		 827
828 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
829 if (index != XCR_XFEATURE_ENABLED_MASK)
830 return 1;
d91cab78 831 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 832 return 1;
d91cab78 833 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 834 return 1;
46c34cb0
PB		 835
836 /*
837 * Do not allow the guest to set bits that we do not support
838 * saving. However, xcr0 bit 0 is always set, even if the
839 * emulated CPU does not support XSAVE (see fx_init).
840 */
d91cab78 841 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 842 if (xcr0 & ~valid_bits)
2acf923e 843 return 1;
46c34cb0 844
d91cab78
DH		 845 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
846 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 847 return 1;
848
d91cab78
DH		 849 if (xcr0 & XFEATURE_MASK_AVX512) {
850 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 851 return 1;
d91cab78 852 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 853 return 1;
854 }
2acf923e 855 vcpu->arch.xcr0 = xcr0;
56c103ec 856
d91cab78 857 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 858 kvm_update_cpuid(vcpu);
2acf923e
DC		 859 return 0;
860}
861
862int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
863{
764bcbc5
Z		 864 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
865 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 866 kvm_inject_gp(vcpu, 0);
867 return 1;
868 }
869 return 0;
870}
871EXPORT_SYMBOL_GPL(kvm_set_xcr);
872
a83b29c6 873int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 874{
fc78f519 875 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 876 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 877 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 878
0f12244f
GN		 879 if (cr4 & CR4_RESERVED_BITS)
880 return 1;
a03490ed 881
d6321d49 882 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 883 return 1;
884
d6321d49 885 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 886 return 1;
887
d6321d49 888 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 889 return 1;
890
d6321d49 891 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 892 return 1;
893
d6321d49 894 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 895 return 1;
896
fd8cb433 897 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 898 return 1;
899
ae3e61e1
PB		 900 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
901 return 1;
902
a03490ed 903 if (is_long_mode(vcpu)) {
0f12244f
GN		 904 if (!(cr4 & X86_CR4_PAE))
905 return 1;
a2edf57f
AK		 906 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
907 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 908 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
909 kvm_read_cr3(vcpu)))
0f12244f
GN		 910 return 1;
911
ad756a16 912 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 913 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 914 return 1;
915
916 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
917 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
918 return 1;
919 }
920
5e1746d6 921 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 922 return 1;
a03490ed 923
ad756a16
MJ		 924 if (((cr4 ^ old_cr4) & pdptr_bits) ||
925 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 926 kvm_mmu_reset_context(vcpu);
0f12244f 927
b9baba86 928 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 929 kvm_update_cpuid(vcpu);
2acf923e 930
0f12244f
GN		 931 return 0;
932}
2d3ad1f4 933EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 934
2390218b 935int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 936{
ade61e28 937 bool skip_tlb_flush = false;
ac146235 938#ifdef CONFIG_X86_64
c19986fe
JS		 939 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
940
ade61e28 941 if (pcid_enabled) {
208320ba
JS		 942 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
943 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 944 }
ac146235 945#endif
9d88fca7 946
9f8fe504 947 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 948 if (!skip_tlb_flush) {
949 kvm_mmu_sync_roots(vcpu);
ade61e28 950 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 951 }
0f12244f 952 return 0;
d835dfec
AK		 953 }
954
d1cd3ce9 955 if (is_long_mode(vcpu) &&
a780a3ea 956 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 957 return 1;
958 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 959 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 960 return 1;
a03490ed 961
ade61e28 962 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 963 vcpu->arch.cr3 = cr3;
aff48baa 964 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 965
0f12244f
GN		 966 return 0;
967}
2d3ad1f4 968EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 969
eea1cff9 970int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 971{
0f12244f
GN		 972 if (cr8 & CR8_RESERVED_BITS)
973 return 1;
35754c98 974 if (lapic_in_kernel(vcpu))
a03490ed
CO		 975 kvm_lapic_set_tpr(vcpu, cr8);
976 else
ad312c7c 977 vcpu->arch.cr8 = cr8;
0f12244f
GN		 978 return 0;
979}
2d3ad1f4 980EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 981
2d3ad1f4 982unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 983{
35754c98 984 if (lapic_in_kernel(vcpu))
a03490ed
CO		 985 return kvm_lapic_get_cr8(vcpu);
986 else
ad312c7c 987 return vcpu->arch.cr8;
a03490ed 988}
2d3ad1f4 989EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 990
ae561ede
NA		 991static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
992{
993 int i;
994
995 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
996 for (i = 0; i < KVM_NR_DB_REGS; i++)
997 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
998 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
999 }
1000}
1001
73aaf249
JK		 1002static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1003{
1004 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1005 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1006}
1007
c8639010
JK		 1008static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1009{
1010 unsigned long dr7;
1011
1012 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1013 dr7 = vcpu->arch.guest_debug_dr7;
1014 else
1015 dr7 = vcpu->arch.dr7;
1016 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1017 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1018 if (dr7 & DR7_BP_EN_MASK)
1019 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1020}
1021
6f43ed01
NA		 1022static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1023{
1024 u64 fixed = DR6_FIXED_1;
1025
d6321d49 1026 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1027 fixed |= DR6_RTM;
1028 return fixed;
1029}
1030
338dbc97 1031static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1032{
1033 switch (dr) {
1034 case 0 ... 3:
1035 vcpu->arch.db[dr] = val;
1036 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1037 vcpu->arch.eff_db[dr] = val;
1038 break;
1039 case 4:
020df079
GN		 1040 /* fall through */
1041 case 6:
338dbc97
GN		 1042 if (val & 0xffffffff00000000ULL)
1043 return -1; /* #GP */
6f43ed01 1044 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1045 kvm_update_dr6(vcpu);
020df079
GN		 1046 break;
1047 case 5:
020df079
GN		 1048 /* fall through */
1049 default: /* 7 */
338dbc97
GN		 1050 if (val & 0xffffffff00000000ULL)
1051 return -1; /* #GP */
020df079 1052 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1053 kvm_update_dr7(vcpu);
020df079
GN		 1054 break;
1055 }
1056
1057 return 0;
1058}
338dbc97
GN		 1059
1060int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1061{
16f8a6f9 1062 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1063 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1064 return 1;
1065 }
1066 return 0;
338dbc97 1067}
020df079
GN		 1068EXPORT_SYMBOL_GPL(kvm_set_dr);
1069
16f8a6f9 1070int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1071{
1072 switch (dr) {
1073 case 0 ... 3:
1074 *val = vcpu->arch.db[dr];
1075 break;
1076 case 4:
020df079
GN		 1077 /* fall through */
1078 case 6:
73aaf249
JK		 1079 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1080 *val = vcpu->arch.dr6;
1081 else
1082 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1083 break;
1084 case 5:
020df079
GN		 1085 /* fall through */
1086 default: /* 7 */
1087 *val = vcpu->arch.dr7;
1088 break;
1089 }
338dbc97
GN		 1090 return 0;
1091}
020df079
GN		 1092EXPORT_SYMBOL_GPL(kvm_get_dr);
1093
022cd0e8
AK		 1094bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1095{
1096 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1097 u64 data;
1098 int err;
1099
c6702c9d 1100 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1101 if (err)
1102 return err;
1103 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1104 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1105 return err;
1106}
1107EXPORT_SYMBOL_GPL(kvm_rdpmc);
1108
043405e1
CO		 1109/*
1110 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1111 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1112 *
1113 * This list is modified at module load time to reflect the
e3267cbb 1114 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1115 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1116 * may depend on host virtualization features rather than host cpu features.
043405e1 1117 */
e3267cbb 1118
043405e1
CO		 1119static u32 msrs_to_save[] = {
1120 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1121 MSR_STAR,
043405e1
CO		 1122#ifdef CONFIG_X86_64
1123 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1124#endif
b3897a49 1125 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1126 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1127 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1128};
1129
1130static unsigned num_msrs_to_save;
1131
62ef68bb
PB		 1132static u32 emulated_msrs[] = {
1133 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1134 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1135 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1136 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1137 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1138 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1139 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1140 HV_X64_MSR_RESET,
11c4b1ca 1141 HV_X64_MSR_VP_INDEX,
9eec50b8 1142 HV_X64_MSR_VP_RUNTIME,
5c919412 1143 HV_X64_MSR_SCONTROL,
1f4b34f8 1144 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1145 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1146 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1147 HV_X64_MSR_TSC_EMULATION_STATUS,
1148
1149 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1150 MSR_KVM_PV_EOI_EN,
1151
ba904635 1152 MSR_IA32_TSC_ADJUST,
a3e06bbe 1153 MSR_IA32_TSCDEADLINE,
043405e1 1154 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1155 MSR_IA32_MCG_STATUS,
1156 MSR_IA32_MCG_CTL,
c45dcc71 1157 MSR_IA32_MCG_EXT_CTL,
64d60670 1158 MSR_IA32_SMBASE,
52797bf9 1159 MSR_SMI_COUNT,
db2336a8
KH		 1160 MSR_PLATFORM_INFO,
1161 MSR_MISC_FEATURES_ENABLES,
bc226f07 1162 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1163};
1164
62ef68bb
PB		 1165static unsigned num_emulated_msrs;
1166
801e459a
TL		 1167/*
1168 * List of msr numbers which are used to expose MSR-based features that
1169 * can be used by a hypervisor to validate requested CPU features.
1170 */
1171static u32 msr_based_features[] = {
1389309c
PB		 1172 MSR_IA32_VMX_BASIC,
1173 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1174 MSR_IA32_VMX_PINBASED_CTLS,
1175 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1176 MSR_IA32_VMX_PROCBASED_CTLS,
1177 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1178 MSR_IA32_VMX_EXIT_CTLS,
1179 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1180 MSR_IA32_VMX_ENTRY_CTLS,
1181 MSR_IA32_VMX_MISC,
1182 MSR_IA32_VMX_CR0_FIXED0,
1183 MSR_IA32_VMX_CR0_FIXED1,
1184 MSR_IA32_VMX_CR4_FIXED0,
1185 MSR_IA32_VMX_CR4_FIXED1,
1186 MSR_IA32_VMX_VMCS_ENUM,
1187 MSR_IA32_VMX_PROCBASED_CTLS2,
1188 MSR_IA32_VMX_EPT_VPID_CAP,
1189 MSR_IA32_VMX_VMFUNC,
1190
d1d93fa9 1191 MSR_F10H_DECFG,
518e7b94 1192 MSR_IA32_UCODE_REV,
cd283252 1193 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1194};
1195
1196static unsigned int num_msr_based_features;
1197
5b76a3cf
PB		 1198u64 kvm_get_arch_capabilities(void)
1199{
1200 u64 data;
1201
1202 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1203
1204 /*
1205 * If we're doing cache flushes (either "always" or "cond")
1206 * we will do one whenever the guest does a vmlaunch/vmresume.
1207 * If an outer hypervisor is doing the cache flush for us
1208 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1209 * capability to the guest too, and if EPT is disabled we're not
1210 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1211 * require a nested hypervisor to do a flush of its own.
1212 */
1213 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1214 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1215
1216 return data;
1217}
1218EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1219
66421c1e
WL		 1220static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1221{
1222 switch (msr->index) {
cd283252 1223 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1224 msr->data = kvm_get_arch_capabilities();
1225 break;
1226 case MSR_IA32_UCODE_REV:
cd283252 1227 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1228 break;
66421c1e
WL		 1229 default:
1230 if (kvm_x86_ops->get_msr_feature(msr))
1231 return 1;
1232 }
1233 return 0;
1234}
1235
801e459a
TL		 1236static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1237{
1238 struct kvm_msr_entry msr;
66421c1e 1239 int r;
801e459a
TL		 1240
1241 msr.index = index;
66421c1e
WL		 1242 r = kvm_get_msr_feature(&msr);
1243 if (r)
1244 return r;
801e459a
TL		 1245
1246 *data = msr.data;
1247
1248 return 0;
1249}
1250
384bb783 1251bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1252{
b69e8cae 1253 if (efer & efer_reserved_bits)
384bb783 1254 return false;
15c4a640 1255
1b4d56b8 1256 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1257 return false;
1b2fd70c 1258
1b4d56b8 1259 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1260 return false;
d8017474 1261
384bb783
JK		 1262 return true;
1263}
1264EXPORT_SYMBOL_GPL(kvm_valid_efer);
1265
1266static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1267{
1268 u64 old_efer = vcpu->arch.efer;
1269
1270 if (!kvm_valid_efer(vcpu, efer))
1271 return 1;
1272
1273 if (is_paging(vcpu)
1274 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1275 return 1;
1276
15c4a640 1277 efer &= ~EFER_LMA;
f6801dff 1278 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1279
a3d204e2
SY		 1280 kvm_x86_ops->set_efer(vcpu, efer);
1281
aad82703
SY		 1282 /* Update reserved bits */
1283 if ((efer ^ old_efer) & EFER_NX)
1284 kvm_mmu_reset_context(vcpu);
1285
b69e8cae 1286 return 0;
15c4a640
CO		 1287}
1288
f2b4b7dd
JR		 1289void kvm_enable_efer_bits(u64 mask)
1290{
1291 efer_reserved_bits &= ~mask;
1292}
1293EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1294
15c4a640
CO		 1295/*
1296 * Writes msr value into into the appropriate "register".
1297 * Returns 0 on success, non-0 otherwise.
1298 * Assumes vcpu_load() was already called.
1299 */
8fe8ab46 1300int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1301{
854e8bb1
NA		 1302 switch (msr->index) {
1303 case MSR_FS_BASE:
1304 case MSR_GS_BASE:
1305 case MSR_KERNEL_GS_BASE:
1306 case MSR_CSTAR:
1307 case MSR_LSTAR:
fd8cb433 1308 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1309 return 1;
1310 break;
1311 case MSR_IA32_SYSENTER_EIP:
1312 case MSR_IA32_SYSENTER_ESP:
1313 /*
1314 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1315 * non-canonical address is written on Intel but not on
1316 * AMD (which ignores the top 32-bits, because it does
1317 * not implement 64-bit SYSENTER).
1318 *
1319 * 64-bit code should hence be able to write a non-canonical
1320 * value on AMD. Making the address canonical ensures that
1321 * vmentry does not fail on Intel after writing a non-canonical
1322 * value, and that something deterministic happens if the guest
1323 * invokes 64-bit SYSENTER.
1324 */
fd8cb433 1325 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1326 }
8fe8ab46 1327 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1328}
854e8bb1 1329EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1330
313a3dc7
CO		 1331/*
1332 * Adapt set_msr() to msr_io()'s calling convention
1333 */
609e36d3
PB		 1334static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1335{
1336 struct msr_data msr;
1337 int r;
1338
1339 msr.index = index;
1340 msr.host_initiated = true;
1341 r = kvm_get_msr(vcpu, &msr);
1342 if (r)
1343 return r;
1344
1345 *data = msr.data;
1346 return 0;
1347}
1348
313a3dc7
CO		 1349static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1350{
8fe8ab46
WA		 1351 struct msr_data msr;
1352
1353 msr.data = *data;
1354 msr.index = index;
1355 msr.host_initiated = true;
1356 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1357}
1358
16e8d74d
MT		 1359#ifdef CONFIG_X86_64
1360struct pvclock_gtod_data {
1361 seqcount_t seq;
1362
1363 struct { /* extract of a clocksource struct */
1364 int vclock_mode;
a5a1d1c2
TG		 1365 u64 cycle_last;
1366 u64 mask;
16e8d74d
MT		 1367 u32 mult;
1368 u32 shift;
1369 } clock;
1370
cbcf2dd3
TG		 1371 u64 boot_ns;
1372 u64 nsec_base;
55dd00a7 1373 u64 wall_time_sec;
16e8d74d
MT		 1374};
1375
1376static struct pvclock_gtod_data pvclock_gtod_data;
1377
1378static void update_pvclock_gtod(struct timekeeper *tk)
1379{
1380 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1381 u64 boot_ns;
1382
876e7881 1383 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1384
1385 write_seqcount_begin(&vdata->seq);
1386
1387 /* copy pvclock gtod data */
876e7881
PZ		 1388 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1389 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1390 vdata->clock.mask = tk->tkr_mono.mask;
1391 vdata->clock.mult = tk->tkr_mono.mult;
1392 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1393
cbcf2dd3 1394 vdata->boot_ns = boot_ns;
876e7881 1395 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1396
55dd00a7
MT		 1397 vdata->wall_time_sec = tk->xtime_sec;
1398
16e8d74d
MT		 1399 write_seqcount_end(&vdata->seq);
1400}
1401#endif
1402
bab5bb39
NK		 1403void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1404{
1405 /*
1406 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1407 * vcpu_enter_guest. This function is only called from
1408 * the physical CPU that is running vcpu.
1409 */
1410 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1411}
16e8d74d 1412
18068523
GOC		 1413static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1414{
9ed3c444
AK		 1415 int version;
1416 int r;
50d0a0f9 1417 struct pvclock_wall_clock wc;
87aeb54f 1418 struct timespec64 boot;
18068523
GOC		 1419
1420 if (!wall_clock)
1421 return;
1422
9ed3c444
AK		 1423 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1424 if (r)
1425 return;
1426
1427 if (version & 1)
1428 ++version; /* first time write, random junk */
1429
1430 ++version;
18068523 1431
1dab1345
NK		 1432 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1433 return;
18068523 1434
50d0a0f9
GH		 1435 /*
1436 * The guest calculates current wall clock time by adding
34c238a1 1437 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1438 * wall clock specified here. guest system time equals host
1439 * system time for us, thus we must fill in host boot time here.
1440 */
87aeb54f 1441 getboottime64(&boot);
50d0a0f9 1442
4b648665 1443 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1444 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1445 boot = timespec64_sub(boot, ts);
4b648665 1446 }
87aeb54f 1447 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1448 wc.nsec = boot.tv_nsec;
1449 wc.version = version;
18068523
GOC		 1450
1451 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1452
1453 version++;
1454 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1455}
1456
50d0a0f9
GH		 1457static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1458{
b51012de
PB		 1459 do_shl32_div32(dividend, divisor);
1460 return dividend;
50d0a0f9
GH		 1461}
1462
3ae13faa 1463static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1464 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1465{
5f4e3f88 1466 uint64_t scaled64;
50d0a0f9
GH		 1467 int32_t shift = 0;
1468 uint64_t tps64;
1469 uint32_t tps32;
1470
3ae13faa
PB		 1471 tps64 = base_hz;
1472 scaled64 = scaled_hz;
50933623 1473 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1474 tps64 >>= 1;
1475 shift--;
1476 }
1477
1478 tps32 = (uint32_t)tps64;
50933623
JK		 1479 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1480 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1481 scaled64 >>= 1;
1482 else
1483 tps32 <<= 1;
50d0a0f9
GH		 1484 shift++;
1485 }
1486
5f4e3f88
ZA		 1487 *pshift = shift;
1488 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1489
3ae13faa
PB		 1490 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1491 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1492}
1493
d828199e 1494#ifdef CONFIG_X86_64
16e8d74d 1495static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1496#endif
16e8d74d 1497
c8076604 1498static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1499static unsigned long max_tsc_khz;
c8076604 1500
cc578287 1501static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1502{
cc578287
ZA		 1503 u64 v = (u64)khz * (1000000 + ppm);
1504 do_div(v, 1000000);
1505 return v;
1e993611
JR		 1506}
1507
381d585c
HZ		 1508static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1509{
1510 u64 ratio;
1511
1512 /* Guest TSC same frequency as host TSC? */
1513 if (!scale) {
1514 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1515 return 0;
1516 }
1517
1518 /* TSC scaling supported? */
1519 if (!kvm_has_tsc_control) {
1520 if (user_tsc_khz > tsc_khz) {
1521 vcpu->arch.tsc_catchup = 1;
1522 vcpu->arch.tsc_always_catchup = 1;
1523 return 0;
1524 } else {
1525 WARN(1, "user requested TSC rate below hardware speed\n");
1526 return -1;
1527 }
1528 }
1529
1530 /* TSC scaling required - calculate ratio */
1531 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1532 user_tsc_khz, tsc_khz);
1533
1534 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1535 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1536 user_tsc_khz);
1537 return -1;
1538 }
1539
1540 vcpu->arch.tsc_scaling_ratio = ratio;
1541 return 0;
1542}
1543
4941b8cb 1544static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1545{
cc578287
ZA		 1546 u32 thresh_lo, thresh_hi;
1547 int use_scaling = 0;
217fc9cf 1548
03ba32ca 1549 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1550 if (user_tsc_khz == 0) {
ad721883
HZ		 1551 /* set tsc_scaling_ratio to a safe value */
1552 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1553 return -1;
ad721883 1554 }
03ba32ca 1555
c285545f 1556 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1557 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1558 &vcpu->arch.virtual_tsc_shift,
1559 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1560 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1561
1562 /*
1563 * Compute the variation in TSC rate which is acceptable
1564 * within the range of tolerance and decide if the
1565 * rate being applied is within that bounds of the hardware
1566 * rate. If so, no scaling or compensation need be done.
1567 */
1568 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1569 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1570 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1571 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1572 use_scaling = 1;
1573 }
4941b8cb 1574 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1575}
1576
1577static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1578{
e26101b1 1579 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1580 vcpu->arch.virtual_tsc_mult,
1581 vcpu->arch.virtual_tsc_shift);
e26101b1 1582 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1583 return tsc;
1584}
1585
b0c39dc6
VK		 1586static inline int gtod_is_based_on_tsc(int mode)
1587{
1588 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1589}
1590
69b0049a 1591static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1592{
1593#ifdef CONFIG_X86_64
1594 bool vcpus_matched;
b48aa97e
MT		 1595 struct kvm_arch *ka = &vcpu->kvm->arch;
1596 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1597
1598 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1599 atomic_read(&vcpu->kvm->online_vcpus));
1600
7f187922
MT		 1601 /*
1602 * Once the masterclock is enabled, always perform request in
1603 * order to update it.
1604 *
1605 * In order to enable masterclock, the host clocksource must be TSC
1606 * and the vcpus need to have matched TSCs. When that happens,
1607 * perform request to enable masterclock.
1608 */
1609 if (ka->use_master_clock ||
b0c39dc6 1610 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1611 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1612
1613 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1614 atomic_read(&vcpu->kvm->online_vcpus),
1615 ka->use_master_clock, gtod->clock.vclock_mode);
1616#endif
1617}
1618
ba904635
WA		 1619static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1620{
e79f245d 1621 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1622 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1623}
1624
35181e86
HZ		 1625/*
1626 * Multiply tsc by a fixed point number represented by ratio.
1627 *
1628 * The most significant 64-N bits (mult) of ratio represent the
1629 * integral part of the fixed point number; the remaining N bits
1630 * (frac) represent the fractional part, ie. ratio represents a fixed
1631 * point number (mult + frac * 2^(-N)).
1632 *
1633 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1634 */
1635static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1636{
1637 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1638}
1639
1640u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1641{
1642 u64 _tsc = tsc;
1643 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1644
1645 if (ratio != kvm_default_tsc_scaling_ratio)
1646 _tsc = __scale_tsc(ratio, tsc);
1647
1648 return _tsc;
1649}
1650EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1651
07c1419a
HZ		 1652static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1653{
1654 u64 tsc;
1655
1656 tsc = kvm_scale_tsc(vcpu, rdtsc());
1657
1658 return target_tsc - tsc;
1659}
1660
4ba76538
HZ		 1661u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1662{
e79f245d
KA		 1663 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1664
1665 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1666}
1667EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1668
a545ab6a
LC		 1669static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1670{
326e7425 1671 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1672}
1673
b0c39dc6
VK		 1674static inline bool kvm_check_tsc_unstable(void)
1675{
1676#ifdef CONFIG_X86_64
1677 /*
1678 * TSC is marked unstable when we're running on Hyper-V,
1679 * 'TSC page' clocksource is good.
1680 */
1681 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1682 return false;
1683#endif
1684 return check_tsc_unstable();
1685}
1686
8fe8ab46 1687void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1688{
1689 struct kvm *kvm = vcpu->kvm;
f38e098f 1690 u64 offset, ns, elapsed;
99e3e30a 1691 unsigned long flags;
b48aa97e 1692 bool matched;
0d3da0d2 1693 bool already_matched;
8fe8ab46 1694 u64 data = msr->data;
c5e8ec8e 1695 bool synchronizing = false;
99e3e30a 1696
038f8c11 1697 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1698 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1699 ns = ktime_get_boot_ns();
f38e098f 1700 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1701
03ba32ca 1702 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1703 if (data == 0 && msr->host_initiated) {
1704 /*
1705 * detection of vcpu initialization -- need to sync
1706 * with other vCPUs. This particularly helps to keep
1707 * kvm_clock stable after CPU hotplug
1708 */
1709 synchronizing = true;
1710 } else {
1711 u64 tsc_exp = kvm->arch.last_tsc_write +
1712 nsec_to_cycles(vcpu, elapsed);
1713 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1714 /*
1715 * Special case: TSC write with a small delta (1 second)
1716 * of virtual cycle time against real time is
1717 * interpreted as an attempt to synchronize the CPU.
1718 */
1719 synchronizing = data < tsc_exp + tsc_hz &&
1720 data + tsc_hz > tsc_exp;
1721 }
c5e8ec8e 1722 }
f38e098f
ZA		 1723
1724 /*
5d3cb0f6
ZA		 1725 * For a reliable TSC, we can match TSC offsets, and for an unstable
1726 * TSC, we add elapsed time in this computation. We could let the
1727 * compensation code attempt to catch up if we fall behind, but
1728 * it's better to try to match offsets from the beginning.
1729 */
c5e8ec8e 1730 if (synchronizing &&
5d3cb0f6 1731 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1732 if (!kvm_check_tsc_unstable()) {
e26101b1 1733 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1734 pr_debug("kvm: matched tsc offset for %llu\n", data);
1735 } else {
857e4099 1736 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1737 data += delta;
07c1419a 1738 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1739 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1740 }
b48aa97e 1741 matched = true;
0d3da0d2 1742 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1743 } else {
1744 /*
1745 * We split periods of matched TSC writes into generations.
1746 * For each generation, we track the original measured
1747 * nanosecond time, offset, and write, so if TSCs are in
1748 * sync, we can match exact offset, and if not, we can match
4a969980 1749 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1750 *
1751 * These values are tracked in kvm->arch.cur_xxx variables.
1752 */
1753 kvm->arch.cur_tsc_generation++;
1754 kvm->arch.cur_tsc_nsec = ns;
1755 kvm->arch.cur_tsc_write = data;
1756 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1757 matched = false;
0d3da0d2 1758 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1759 kvm->arch.cur_tsc_generation, data);
f38e098f 1760 }
e26101b1
ZA		 1761
1762 /*
1763 * We also track th most recent recorded KHZ, write and time to
1764 * allow the matching interval to be extended at each write.
1765 */
f38e098f
ZA		 1766 kvm->arch.last_tsc_nsec = ns;
1767 kvm->arch.last_tsc_write = data;
5d3cb0f6 1768 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1769
b183aa58 1770 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1771
1772 /* Keep track of which generation this VCPU has synchronized to */
1773 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1774 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1775 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1776
d6321d49 1777 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1778 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1779
a545ab6a 1780 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1781 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1782
1783 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1784 if (!matched) {
b48aa97e 1785 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1786 } else if (!already_matched) {
1787 kvm->arch.nr_vcpus_matched_tsc++;
1788 }
b48aa97e
MT		 1789
1790 kvm_track_tsc_matching(vcpu);
1791 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1792}
e26101b1 1793
99e3e30a
ZA		 1794EXPORT_SYMBOL_GPL(kvm_write_tsc);
1795
58ea6767
HZ		 1796static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1797 s64 adjustment)
1798{
326e7425
LS		 1799 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1800 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1801}
1802
1803static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1804{
1805 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1806 WARN_ON(adjustment < 0);
1807 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1808 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1809}
1810
d828199e
MT		 1811#ifdef CONFIG_X86_64
1812
a5a1d1c2 1813static u64 read_tsc(void)
d828199e 1814{
a5a1d1c2 1815 u64 ret = (u64)rdtsc_ordered();
03b9730b 1816 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1817
1818 if (likely(ret >= last))
1819 return ret;
1820
1821 /*
1822 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1823 * predictable (it's just a function of time and the likely is
d828199e
MT		 1824 * very likely) and there's a data dependence, so force GCC
1825 * to generate a branch instead. I don't barrier() because
1826 * we don't actually need a barrier, and if this function
1827 * ever gets inlined it will generate worse code.
1828 */
1829 asm volatile ("");
1830 return last;
1831}
1832
b0c39dc6 1833static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1834{
1835 long v;
1836 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1837 u64 tsc_pg_val;
1838
1839 switch (gtod->clock.vclock_mode) {
1840 case VCLOCK_HVCLOCK:
1841 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1842 tsc_timestamp);
1843 if (tsc_pg_val != U64_MAX) {
1844 /* TSC page valid */
1845 *mode = VCLOCK_HVCLOCK;
1846 v = (tsc_pg_val - gtod->clock.cycle_last) &
1847 gtod->clock.mask;
1848 } else {
1849 /* TSC page invalid */
1850 *mode = VCLOCK_NONE;
1851 }
1852 break;
1853 case VCLOCK_TSC:
1854 *mode = VCLOCK_TSC;
1855 *tsc_timestamp = read_tsc();
1856 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1857 gtod->clock.mask;
1858 break;
1859 default:
1860 *mode = VCLOCK_NONE;
1861 }
d828199e 1862
b0c39dc6
VK		 1863 if (*mode == VCLOCK_NONE)
1864 *tsc_timestamp = v = 0;
d828199e 1865
d828199e
MT		 1866 return v * gtod->clock.mult;
1867}
1868
b0c39dc6 1869static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1870{
cbcf2dd3 1871 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1872 unsigned long seq;
d828199e 1873 int mode;
cbcf2dd3 1874 u64 ns;
d828199e 1875
d828199e
MT		 1876 do {
1877 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1878 ns = gtod->nsec_base;
b0c39dc6 1879 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1880 ns >>= gtod->clock.shift;
cbcf2dd3 1881 ns += gtod->boot_ns;
d828199e 1882 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1883 *t = ns;
d828199e
MT		 1884
1885 return mode;
1886}
1887
899a31f5 1888static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1889{
1890 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1891 unsigned long seq;
1892 int mode;
1893 u64 ns;
1894
1895 do {
1896 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1897 ts->tv_sec = gtod->wall_time_sec;
1898 ns = gtod->nsec_base;
b0c39dc6 1899 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1900 ns >>= gtod->clock.shift;
1901 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1902
1903 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1904 ts->tv_nsec = ns;
1905
1906 return mode;
1907}
1908
b0c39dc6
VK		 1909/* returns true if host is using TSC based clocksource */
1910static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1911{
d828199e 1912 /* checked again under seqlock below */
b0c39dc6 1913 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1914 return false;
1915
b0c39dc6
VK		 1916 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1917 tsc_timestamp));
d828199e 1918}
55dd00a7 1919
b0c39dc6 1920/* returns true if host is using TSC based clocksource */
899a31f5 1921static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1922 u64 *tsc_timestamp)
55dd00a7
MT		 1923{
1924 /* checked again under seqlock below */
b0c39dc6 1925 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1926 return false;
1927
b0c39dc6 1928 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1929}
d828199e
MT		 1930#endif
1931
1932/*
1933 *
b48aa97e
MT		 1934 * Assuming a stable TSC across physical CPUS, and a stable TSC
1935 * across virtual CPUs, the following condition is possible.
1936 * Each numbered line represents an event visible to both
d828199e
MT		 1937 * CPUs at the next numbered event.
1938 *
1939 * "timespecX" represents host monotonic time. "tscX" represents
1940 * RDTSC value.
1941 *
1942 * VCPU0 on CPU0 | VCPU1 on CPU1
1943 *
1944 * 1. read timespec0,tsc0
1945 * 2. | timespec1 = timespec0 + N
1946 * | tsc1 = tsc0 + M
1947 * 3. transition to guest | transition to guest
1948 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1949 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1950 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1951 *
1952 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1953 *
1954 * - ret0 < ret1
1955 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1956 * ...
1957 * - 0 < N - M => M < N
1958 *
1959 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1960 * always the case (the difference between two distinct xtime instances
1961 * might be smaller then the difference between corresponding TSC reads,
1962 * when updating guest vcpus pvclock areas).
1963 *
1964 * To avoid that problem, do not allow visibility of distinct
1965 * system_timestamp/tsc_timestamp values simultaneously: use a master
1966 * copy of host monotonic time values. Update that master copy
1967 * in lockstep.
1968 *
b48aa97e 1969 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1970 *
1971 */
1972
1973static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1974{
1975#ifdef CONFIG_X86_64
1976 struct kvm_arch *ka = &kvm->arch;
1977 int vclock_mode;
b48aa97e
MT		 1978 bool host_tsc_clocksource, vcpus_matched;
1979
1980 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1981 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1982
1983 /*
1984 * If the host uses TSC clock, then passthrough TSC as stable
1985 * to the guest.
1986 */
b48aa97e 1987 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1988 &ka->master_kernel_ns,
1989 &ka->master_cycle_now);
1990
16a96021 1991 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1992 && !ka->backwards_tsc_observed
54750f2c 1993 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1994
d828199e
MT		 1995 if (ka->use_master_clock)
1996 atomic_set(&kvm_guest_has_master_clock, 1);
1997
1998 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1999 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2000 vcpus_matched);
d828199e
MT		 2001#endif
2002}
2003
2860c4b1
PB		 2004void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2005{
2006 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2007}
2008
2e762ff7
MT		 2009static void kvm_gen_update_masterclock(struct kvm *kvm)
2010{
2011#ifdef CONFIG_X86_64
2012 int i;
2013 struct kvm_vcpu *vcpu;
2014 struct kvm_arch *ka = &kvm->arch;
2015
2016 spin_lock(&ka->pvclock_gtod_sync_lock);
2017 kvm_make_mclock_inprogress_request(kvm);
2018 /* no guest entries from this point */
2019 pvclock_update_vm_gtod_copy(kvm);
2020
2021 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2022 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2023
2024 /* guest entries allowed */
2025 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2026 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2027
2028 spin_unlock(&ka->pvclock_gtod_sync_lock);
2029#endif
2030}
2031
e891a32e 2032u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2033{
108b249c 2034 struct kvm_arch *ka = &kvm->arch;
8b953440 2035 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2036 u64 ret;
108b249c 2037
8b953440
PB		 2038 spin_lock(&ka->pvclock_gtod_sync_lock);
2039 if (!ka->use_master_clock) {
2040 spin_unlock(&ka->pvclock_gtod_sync_lock);
2041 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 2042 }
2043
8b953440
PB		 2044 hv_clock.tsc_timestamp = ka->master_cycle_now;
2045 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2046 spin_unlock(&ka->pvclock_gtod_sync_lock);
2047
e2c2206a
WL		 2048 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2049 get_cpu();
2050
e70b57a6
WL		 2051 if (__this_cpu_read(cpu_tsc_khz)) {
2052 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2053 &hv_clock.tsc_shift,
2054 &hv_clock.tsc_to_system_mul);
2055 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2056 } else
2057 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2058
2059 put_cpu();
2060
2061 return ret;
108b249c
PB		 2062}
2063
0d6dd2ff
PB		 2064static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2065{
2066 struct kvm_vcpu_arch *vcpu = &v->arch;
2067 struct pvclock_vcpu_time_info guest_hv_clock;
2068
4e335d9e 2069 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2070 &guest_hv_clock, sizeof(guest_hv_clock))))
2071 return;
2072
2073 /* This VCPU is paused, but it's legal for a guest to read another
2074 * VCPU's kvmclock, so we really have to follow the specification where
2075 * it says that version is odd if data is being modified, and even after
2076 * it is consistent.
2077 *
2078 * Version field updates must be kept separate. This is because
2079 * kvm_write_guest_cached might use a "rep movs" instruction, and
2080 * writes within a string instruction are weakly ordered. So there
2081 * are three writes overall.
2082 *
2083 * As a small optimization, only write the version field in the first
2084 * and third write. The vcpu->pv_time cache is still valid, because the
2085 * version field is the first in the struct.
2086 */
2087 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2088
51c4b8bb
LA		 2089 if (guest_hv_clock.version & 1)
2090 ++guest_hv_clock.version; /* first time write, random junk */
2091
0d6dd2ff 2092 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2093 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2094 &vcpu->hv_clock,
2095 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2096
2097 smp_wmb();
2098
2099 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2100 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2101
2102 if (vcpu->pvclock_set_guest_stopped_request) {
2103 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2104 vcpu->pvclock_set_guest_stopped_request = false;
2105 }
2106
2107 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2108
4e335d9e
PB		 2109 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2110 &vcpu->hv_clock,
2111 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2112
2113 smp_wmb();
2114
2115 vcpu->hv_clock.version++;
4e335d9e
PB		 2116 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2117 &vcpu->hv_clock,
2118 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2119}
2120
34c238a1 2121static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2122{
78db6a50 2123 unsigned long flags, tgt_tsc_khz;
18068523 2124 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2125 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2126 s64 kernel_ns;
d828199e 2127 u64 tsc_timestamp, host_tsc;
51d59c6b 2128 u8 pvclock_flags;
d828199e
MT		 2129 bool use_master_clock;
2130
2131 kernel_ns = 0;
2132 host_tsc = 0;
18068523 2133
d828199e
MT		 2134 /*
2135 * If the host uses TSC clock, then passthrough TSC as stable
2136 * to the guest.
2137 */
2138 spin_lock(&ka->pvclock_gtod_sync_lock);
2139 use_master_clock = ka->use_master_clock;
2140 if (use_master_clock) {
2141 host_tsc = ka->master_cycle_now;
2142 kernel_ns = ka->master_kernel_ns;
2143 }
2144 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2145
2146 /* Keep irq disabled to prevent changes to the clock */
2147 local_irq_save(flags);
78db6a50
PB		 2148 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2149 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2150 local_irq_restore(flags);
2151 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2152 return 1;
2153 }
d828199e 2154 if (!use_master_clock) {
4ea1636b 2155 host_tsc = rdtsc();
108b249c 2156 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2157 }
2158
4ba76538 2159 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2160
c285545f
ZA		 2161 /*
2162 * We may have to catch up the TSC to match elapsed wall clock
2163 * time for two reasons, even if kvmclock is used.
2164 * 1) CPU could have been running below the maximum TSC rate
2165 * 2) Broken TSC compensation resets the base at each VCPU
2166 * entry to avoid unknown leaps of TSC even when running
2167 * again on the same CPU. This may cause apparent elapsed
2168 * time to disappear, and the guest to stand still or run
2169 * very slowly.
2170 */
2171 if (vcpu->tsc_catchup) {
2172 u64 tsc = compute_guest_tsc(v, kernel_ns);
2173 if (tsc > tsc_timestamp) {
f1e2b260 2174 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2175 tsc_timestamp = tsc;
2176 }
50d0a0f9
GH		 2177 }
2178
18068523
GOC		 2179 local_irq_restore(flags);
2180
0d6dd2ff 2181 /* With all the info we got, fill in the values */
18068523 2182
78db6a50
PB		 2183 if (kvm_has_tsc_control)
2184 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2185
2186 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2187 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2188 &vcpu->hv_clock.tsc_shift,
2189 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2190 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2191 }
2192
1d5f066e 2193 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2194 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2195 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2196
d828199e 2197 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2198 pvclock_flags = 0;
d828199e
MT		 2199 if (use_master_clock)
2200 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2201
78c0337a
MT		 2202 vcpu->hv_clock.flags = pvclock_flags;
2203
095cf55d
PB		 2204 if (vcpu->pv_time_enabled)
2205 kvm_setup_pvclock_page(v);
2206 if (v == kvm_get_vcpu(v->kvm, 0))
2207 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2208 return 0;
c8076604
GH		 2209}
2210
0061d53d
MT		 2211/*
2212 * kvmclock updates which are isolated to a given vcpu, such as
2213 * vcpu->cpu migration, should not allow system_timestamp from
2214 * the rest of the vcpus to remain static. Otherwise ntp frequency
2215 * correction applies to one vcpu's system_timestamp but not
2216 * the others.
2217 *
2218 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2219 * We need to rate-limit these requests though, as they can
2220 * considerably slow guests that have a large number of vcpus.
2221 * The time for a remote vcpu to update its kvmclock is bound
2222 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2223 */
2224
7e44e449
AJ		 2225#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2226
2227static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2228{
2229 int i;
7e44e449
AJ		 2230 struct delayed_work *dwork = to_delayed_work(work);
2231 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2232 kvmclock_update_work);
2233 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2234 struct kvm_vcpu *vcpu;
2235
2236 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2237 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2238 kvm_vcpu_kick(vcpu);
2239 }
2240}
2241
7e44e449
AJ		 2242static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2243{
2244 struct kvm *kvm = v->kvm;
2245
105b21bb 2246 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2247 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2248 KVMCLOCK_UPDATE_DELAY);
2249}
2250
332967a3
AJ		 2251#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2252
2253static void kvmclock_sync_fn(struct work_struct *work)
2254{
2255 struct delayed_work *dwork = to_delayed_work(work);
2256 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2257 kvmclock_sync_work);
2258 struct kvm *kvm = container_of(ka, struct kvm, arch);
2259
630994b3
MT		 2260 if (!kvmclock_periodic_sync)
2261 return;
2262
332967a3
AJ		 2263 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2264 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2265 KVMCLOCK_SYNC_PERIOD);
2266}
2267
9ffd986c 2268static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2269{
890ca9ae
HY		 2270 u64 mcg_cap = vcpu->arch.mcg_cap;
2271 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2272 u32 msr = msr_info->index;
2273 u64 data = msr_info->data;
890ca9ae 2274
15c4a640 2275 switch (msr) {
15c4a640 2276 case MSR_IA32_MCG_STATUS:
890ca9ae 2277 vcpu->arch.mcg_status = data;
15c4a640 2278 break;
c7ac679c 2279 case MSR_IA32_MCG_CTL:
44883f01
PB		 2280 if (!(mcg_cap & MCG_CTL_P) &&
2281 (data || !msr_info->host_initiated))
890ca9ae
HY		 2282 return 1;
2283 if (data != 0 && data != ~(u64)0)
44883f01 2284 return 1;
890ca9ae
HY		 2285 vcpu->arch.mcg_ctl = data;
2286 break;
2287 default:
2288 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2289 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2290 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2291 /* only 0 or all 1s can be written to IA32_MCi_CTL
2292 * some Linux kernels though clear bit 10 in bank 4 to
2293 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2294 * this to avoid an uncatched #GP in the guest
2295 */
890ca9ae 2296 if ((offset & 0x3) == 0 &&
114be429 2297 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2298 return -1;
9ffd986c
WL		 2299 if (!msr_info->host_initiated &&
2300 (offset & 0x3) == 1 && data != 0)
2301 return -1;
890ca9ae
HY		 2302 vcpu->arch.mce_banks[offset] = data;
2303 break;
2304 }
2305 return 1;
2306 }
2307 return 0;
2308}
2309
ffde22ac
ES		 2310static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2311{
2312 struct kvm *kvm = vcpu->kvm;
2313 int lm = is_long_mode(vcpu);
2314 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2315 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2316 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2317 : kvm->arch.xen_hvm_config.blob_size_32;
2318 u32 page_num = data & ~PAGE_MASK;
2319 u64 page_addr = data & PAGE_MASK;
2320 u8 *page;
2321 int r;
2322
2323 r = -E2BIG;
2324 if (page_num >= blob_size)
2325 goto out;
2326 r = -ENOMEM;
ff5c2c03
SL		 2327 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2328 if (IS_ERR(page)) {
2329 r = PTR_ERR(page);
ffde22ac 2330 goto out;
ff5c2c03 2331 }
54bf36aa 2332 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2333 goto out_free;
2334 r = 0;
2335out_free:
2336 kfree(page);
2337out:
2338 return r;
2339}
2340
344d9588
GN		 2341static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2342{
2343 gpa_t gpa = data & ~0x3f;
2344
52a5c155
WL		 2345 /* Bits 3:5 are reserved, Should be zero */
2346 if (data & 0x38)
344d9588
GN		 2347 return 1;
2348
2349 vcpu->arch.apf.msr_val = data;
2350
2351 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2352 kvm_clear_async_pf_completion_queue(vcpu);
2353 kvm_async_pf_hash_reset(vcpu);
2354 return 0;
2355 }
2356
4e335d9e 2357 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2358 sizeof(u32)))
344d9588
GN		 2359 return 1;
2360
6adba527 2361 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2362 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2363 kvm_async_pf_wakeup_all(vcpu);
2364 return 0;
2365}
2366
12f9a48f
GC		 2367static void kvmclock_reset(struct kvm_vcpu *vcpu)
2368{
0b79459b 2369 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2370}
2371
f38a7b75
WL		 2372static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2373{
2374 ++vcpu->stat.tlb_flush;
2375 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2376}
2377
c9aaa895
GC		 2378static void record_steal_time(struct kvm_vcpu *vcpu)
2379{
2380 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2381 return;
2382
4e335d9e 2383 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2384 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2385 return;
2386
f38a7b75
WL		 2387 /*
2388 * Doing a TLB flush here, on the guest's behalf, can avoid
2389 * expensive IPIs.
2390 */
2391 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2392 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2393
35f3fae1
WL		 2394 if (vcpu->arch.st.steal.version & 1)
2395 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2396
2397 vcpu->arch.st.steal.version += 1;
2398
4e335d9e 2399 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2400 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2401
2402 smp_wmb();
2403
c54cdf14
LC		 2404 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2405 vcpu->arch.st.last_steal;
2406 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2407
4e335d9e 2408 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2409 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2410
2411 smp_wmb();
2412
2413 vcpu->arch.st.steal.version += 1;
c9aaa895 2414
4e335d9e 2415 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2416 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2417}
2418
8fe8ab46 2419int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2420{
5753785f 2421 bool pr = false;
8fe8ab46
WA		 2422 u32 msr = msr_info->index;
2423 u64 data = msr_info->data;
5753785f 2424
15c4a640 2425 switch (msr) {
2e32b719 2426 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2427 case MSR_IA32_UCODE_WRITE:
2428 case MSR_VM_HSAVE_PA:
2429 case MSR_AMD64_PATCH_LOADER:
2430 case MSR_AMD64_BU_CFG2:
405a353a 2431 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2432 break;
2433
518e7b94
WL		 2434 case MSR_IA32_UCODE_REV:
2435 if (msr_info->host_initiated)
2436 vcpu->arch.microcode_version = data;
2437 break;
15c4a640 2438 case MSR_EFER:
b69e8cae 2439 return set_efer(vcpu, data);
8f1589d9
AP		 2440 case MSR_K7_HWCR:
2441 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2442 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2443 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2444 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2445 if (data != 0) {
a737f256
CD		 2446 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2447 data);
8f1589d9
AP		 2448 return 1;
2449 }
15c4a640 2450 break;
f7c6d140
AP		 2451 case MSR_FAM10H_MMIO_CONF_BASE:
2452 if (data != 0) {
a737f256
CD		 2453 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2454 "0x%llx\n", data);
f7c6d140
AP		 2455 return 1;
2456 }
15c4a640 2457 break;
b5e2fec0
AG		 2458 case MSR_IA32_DEBUGCTLMSR:
2459 if (!data) {
2460 /* We support the non-activated case already */
2461 break;
2462 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2463 /* Values other than LBR and BTF are vendor-specific,
2464 thus reserved and should throw a #GP */
2465 return 1;
2466 }
a737f256
CD		 2467 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2468 __func__, data);
b5e2fec0 2469 break;
9ba075a6 2470 case 0x200 ... 0x2ff:
ff53604b 2471 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2472 case MSR_IA32_APICBASE:
58cb628d 2473 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2474 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2475 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2476 case MSR_IA32_TSCDEADLINE:
2477 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2478 break;
ba904635 2479 case MSR_IA32_TSC_ADJUST:
d6321d49 2480 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2481 if (!msr_info->host_initiated) {
d913b904 2482 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2483 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2484 }
2485 vcpu->arch.ia32_tsc_adjust_msr = data;
2486 }
2487 break;
15c4a640 2488 case MSR_IA32_MISC_ENABLE:
ad312c7c 2489 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2490 break;
64d60670
PB		 2491 case MSR_IA32_SMBASE:
2492 if (!msr_info->host_initiated)
2493 return 1;
2494 vcpu->arch.smbase = data;
2495 break;
dd259935
PB		 2496 case MSR_IA32_TSC:
2497 kvm_write_tsc(vcpu, msr_info);
2498 break;
52797bf9
LA		 2499 case MSR_SMI_COUNT:
2500 if (!msr_info->host_initiated)
2501 return 1;
2502 vcpu->arch.smi_count = data;
2503 break;
11c6bffa 2504 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2505 case MSR_KVM_WALL_CLOCK:
2506 vcpu->kvm->arch.wall_clock = data;
2507 kvm_write_wall_clock(vcpu->kvm, data);
2508 break;
11c6bffa 2509 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2510 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2511 struct kvm_arch *ka = &vcpu->kvm->arch;
2512
12f9a48f 2513 kvmclock_reset(vcpu);
18068523 2514
54750f2c
MT		 2515 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2516 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2517
2518 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2519 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2520
2521 ka->boot_vcpu_runs_old_kvmclock = tmp;
2522 }
2523
18068523 2524 vcpu->arch.time = data;
0061d53d 2525 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2526
2527 /* we verify if the enable bit is set... */
2528 if (!(data & 1))
2529 break;
2530
4e335d9e 2531 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2532 &vcpu->arch.pv_time, data & ~1ULL,
2533 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2534 vcpu->arch.pv_time_enabled = false;
2535 else
2536 vcpu->arch.pv_time_enabled = true;
32cad84f 2537
18068523
GOC		 2538 break;
2539 }
344d9588
GN		 2540 case MSR_KVM_ASYNC_PF_EN:
2541 if (kvm_pv_enable_async_pf(vcpu, data))
2542 return 1;
2543 break;
c9aaa895
GC		 2544 case MSR_KVM_STEAL_TIME:
2545
2546 if (unlikely(!sched_info_on()))
2547 return 1;
2548
2549 if (data & KVM_STEAL_RESERVED_MASK)
2550 return 1;
2551
4e335d9e 2552 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2553 data & KVM_STEAL_VALID_BITS,
2554 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2555 return 1;
2556
2557 vcpu->arch.st.msr_val = data;
2558
2559 if (!(data & KVM_MSR_ENABLED))
2560 break;
2561
c9aaa895
GC		 2562 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2563
2564 break;
ae7a2a3f 2565 case MSR_KVM_PV_EOI_EN:
72bbf935 2566 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2567 return 1;
2568 break;
c9aaa895 2569
890ca9ae
HY		 2570 case MSR_IA32_MCG_CTL:
2571 case MSR_IA32_MCG_STATUS:
81760dcc 2572 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2573 return set_msr_mce(vcpu, msr_info);
71db6023 2574
6912ac32
WH		 2575 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2576 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2577 pr = true; /* fall through */
2578 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2579 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2580 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2581 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2582
2583 if (pr || data != 0)
a737f256
CD		 2584 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2585 "0x%x data 0x%llx\n", msr, data);
5753785f 2586 break;
84e0cefa
JS		 2587 case MSR_K7_CLK_CTL:
2588 /*
2589 * Ignore all writes to this no longer documented MSR.
2590 * Writes are only relevant for old K7 processors,
2591 * all pre-dating SVM, but a recommended workaround from
4a969980 2592 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2593 * affected processor models on the command line, hence
2594 * the need to ignore the workaround.
2595 */
2596 break;
55cd8e5a 2597 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2598 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2599 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2600 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2601 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2602 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2603 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2604 return kvm_hv_set_msr_common(vcpu, msr, data,
2605 msr_info->host_initiated);
91c9c3ed 2606 case MSR_IA32_BBL_CR_CTL3:
2607 /* Drop writes to this legacy MSR -- see rdmsr
2608 * counterpart for further detail.
2609 */
fab0aa3b
EM		 2610 if (report_ignored_msrs)
2611 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2612 msr, data);
91c9c3ed 2613 break;
2b036c6b 2614 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2615 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2616 return 1;
2617 vcpu->arch.osvw.length = data;
2618 break;
2619 case MSR_AMD64_OSVW_STATUS:
d6321d49 2620 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2621 return 1;
2622 vcpu->arch.osvw.status = data;
2623 break;
db2336a8
KH		 2624 case MSR_PLATFORM_INFO:
2625 if (!msr_info->host_initiated ||
db2336a8
KH		 2626 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2627 cpuid_fault_enabled(vcpu)))
2628 return 1;
2629 vcpu->arch.msr_platform_info = data;
2630 break;
2631 case MSR_MISC_FEATURES_ENABLES:
2632 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2633 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2634 !supports_cpuid_fault(vcpu)))
2635 return 1;
2636 vcpu->arch.msr_misc_features_enables = data;
2637 break;
15c4a640 2638 default:
ffde22ac
ES		 2639 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2640 return xen_hvm_config(vcpu, data);
c6702c9d 2641 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2642 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2643 if (!ignore_msrs) {
ae0f5499 2644 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2645 msr, data);
ed85c068
AP		 2646 return 1;
2647 } else {
fab0aa3b
EM		 2648 if (report_ignored_msrs)
2649 vcpu_unimpl(vcpu,
2650 "ignored wrmsr: 0x%x data 0x%llx\n",
2651 msr, data);
ed85c068
AP		 2652 break;
2653 }
15c4a640
CO		 2654 }
2655 return 0;
2656}
2657EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2658
2659
2660/*
2661 * Reads an msr value (of 'msr_index') into 'pdata'.
2662 * Returns 0 on success, non-0 otherwise.
2663 * Assumes vcpu_load() was already called.
2664 */
609e36d3 2665int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2666{
609e36d3 2667 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2668}
ff651cb6 2669EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2670
44883f01 2671static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2672{
2673 u64 data;
890ca9ae
HY		 2674 u64 mcg_cap = vcpu->arch.mcg_cap;
2675 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2676
2677 switch (msr) {
15c4a640
CO		 2678 case MSR_IA32_P5_MC_ADDR:
2679 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2680 data = 0;
2681 break;
15c4a640 2682 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2683 data = vcpu->arch.mcg_cap;
2684 break;
c7ac679c 2685 case MSR_IA32_MCG_CTL:
44883f01 2686 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2687 return 1;
2688 data = vcpu->arch.mcg_ctl;
2689 break;
2690 case MSR_IA32_MCG_STATUS:
2691 data = vcpu->arch.mcg_status;
2692 break;
2693 default:
2694 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2695 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2696 u32 offset = msr - MSR_IA32_MC0_CTL;
2697 data = vcpu->arch.mce_banks[offset];
2698 break;
2699 }
2700 return 1;
2701 }
2702 *pdata = data;
2703 return 0;
2704}
2705
609e36d3 2706int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2707{
609e36d3 2708 switch (msr_info->index) {
890ca9ae 2709 case MSR_IA32_PLATFORM_ID:
15c4a640 2710 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2711 case MSR_IA32_DEBUGCTLMSR:
2712 case MSR_IA32_LASTBRANCHFROMIP:
2713 case MSR_IA32_LASTBRANCHTOIP:
2714 case MSR_IA32_LASTINTFROMIP:
2715 case MSR_IA32_LASTINTTOIP:
60af2ecd 2716 case MSR_K8_SYSCFG:
3afb1121
PB		 2717 case MSR_K8_TSEG_ADDR:
2718 case MSR_K8_TSEG_MASK:
60af2ecd 2719 case MSR_K7_HWCR:
61a6bd67 2720 case MSR_VM_HSAVE_PA:
1fdbd48c 2721 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2722 case MSR_AMD64_NB_CFG:
f7c6d140 2723 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2724 case MSR_AMD64_BU_CFG2:
0c2df2a1 2725 case MSR_IA32_PERF_CTL:
405a353a 2726 case MSR_AMD64_DC_CFG:
609e36d3 2727 msr_info->data = 0;
15c4a640 2728 break;
c51eb52b 2729 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2730 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2731 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2732 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2733 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2734 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2735 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2736 msr_info->data = 0;
5753785f 2737 break;
742bc670 2738 case MSR_IA32_UCODE_REV:
518e7b94 2739 msr_info->data = vcpu->arch.microcode_version;
742bc670 2740 break;
dd259935
PB		 2741 case MSR_IA32_TSC:
2742 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2743 break;
9ba075a6 2744 case MSR_MTRRcap:
9ba075a6 2745 case 0x200 ... 0x2ff:
ff53604b 2746 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2747 case 0xcd: /* fsb frequency */
609e36d3 2748 msr_info->data = 3;
15c4a640 2749 break;
7b914098
JS		 2750 /*
2751 * MSR_EBC_FREQUENCY_ID
2752 * Conservative value valid for even the basic CPU models.
2753 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2754 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2755 * and 266MHz for model 3, or 4. Set Core Clock
2756 * Frequency to System Bus Frequency Ratio to 1 (bits
2757 * 31:24) even though these are only valid for CPU
2758 * models > 2, however guests may end up dividing or
2759 * multiplying by zero otherwise.
2760 */
2761 case MSR_EBC_FREQUENCY_ID:
609e36d3 2762 msr_info->data = 1 << 24;
7b914098 2763 break;
15c4a640 2764 case MSR_IA32_APICBASE:
609e36d3 2765 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2766 break;
0105d1a5 2767 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2768 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2769 break;
a3e06bbe 2770 case MSR_IA32_TSCDEADLINE:
609e36d3 2771 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2772 break;
ba904635 2773 case MSR_IA32_TSC_ADJUST:
609e36d3 2774 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2775 break;
15c4a640 2776 case MSR_IA32_MISC_ENABLE:
609e36d3 2777 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2778 break;
64d60670
PB		 2779 case MSR_IA32_SMBASE:
2780 if (!msr_info->host_initiated)
2781 return 1;
2782 msr_info->data = vcpu->arch.smbase;
15c4a640 2783 break;
52797bf9
LA		 2784 case MSR_SMI_COUNT:
2785 msr_info->data = vcpu->arch.smi_count;
2786 break;
847f0ad8
AG		 2787 case MSR_IA32_PERF_STATUS:
2788 /* TSC increment by tick */
609e36d3 2789 msr_info->data = 1000ULL;
847f0ad8 2790 /* CPU multiplier */
b0996ae4 2791 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2792 break;
15c4a640 2793 case MSR_EFER:
609e36d3 2794 msr_info->data = vcpu->arch.efer;
15c4a640 2795 break;
18068523 2796 case MSR_KVM_WALL_CLOCK:
11c6bffa 2797 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2798 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2799 break;
2800 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2801 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2802 msr_info->data = vcpu->arch.time;
18068523 2803 break;
344d9588 2804 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2805 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2806 break;
c9aaa895 2807 case MSR_KVM_STEAL_TIME:
609e36d3 2808 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2809 break;
1d92128f 2810 case MSR_KVM_PV_EOI_EN:
609e36d3 2811 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2812 break;
890ca9ae
HY		 2813 case MSR_IA32_P5_MC_ADDR:
2814 case MSR_IA32_P5_MC_TYPE:
2815 case MSR_IA32_MCG_CAP:
2816 case MSR_IA32_MCG_CTL:
2817 case MSR_IA32_MCG_STATUS:
81760dcc 2818 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2819 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2820 msr_info->host_initiated);
84e0cefa
JS		 2821 case MSR_K7_CLK_CTL:
2822 /*
2823 * Provide expected ramp-up count for K7. All other
2824 * are set to zero, indicating minimum divisors for
2825 * every field.
2826 *
2827 * This prevents guest kernels on AMD host with CPU
2828 * type 6, model 8 and higher from exploding due to
2829 * the rdmsr failing.
2830 */
609e36d3 2831 msr_info->data = 0x20000000;
84e0cefa 2832 break;
55cd8e5a 2833 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2834 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2835 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2836 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2837 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2838 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2839 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2840 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2841 msr_info->index, &msr_info->data,
2842 msr_info->host_initiated);
55cd8e5a 2843 break;
91c9c3ed 2844 case MSR_IA32_BBL_CR_CTL3:
2845 /* This legacy MSR exists but isn't fully documented in current
2846 * silicon. It is however accessed by winxp in very narrow
2847 * scenarios where it sets bit #19, itself documented as
2848 * a "reserved" bit. Best effort attempt to source coherent
2849 * read data here should the balance of the register be
2850 * interpreted by the guest:
2851 *
2852 * L2 cache control register 3: 64GB range, 256KB size,
2853 * enabled, latency 0x1, configured
2854 */
609e36d3 2855 msr_info->data = 0xbe702111;
91c9c3ed 2856 break;
2b036c6b 2857 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2858 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2859 return 1;
609e36d3 2860 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2861 break;
2862 case MSR_AMD64_OSVW_STATUS:
d6321d49 2863 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2864 return 1;
609e36d3 2865 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2866 break;
db2336a8 2867 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2868 if (!msr_info->host_initiated &&
2869 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2870 return 1;
db2336a8
KH		 2871 msr_info->data = vcpu->arch.msr_platform_info;
2872 break;
2873 case MSR_MISC_FEATURES_ENABLES:
2874 msr_info->data = vcpu->arch.msr_misc_features_enables;
2875 break;
15c4a640 2876 default:
c6702c9d 2877 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2878 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2879 if (!ignore_msrs) {
ae0f5499
BD		 2880 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2881 msr_info->index);
ed85c068
AP		 2882 return 1;
2883 } else {
fab0aa3b
EM		 2884 if (report_ignored_msrs)
2885 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2886 msr_info->index);
609e36d3 2887 msr_info->data = 0;
ed85c068
AP		 2888 }
2889 break;
15c4a640 2890 }
15c4a640
CO		 2891 return 0;
2892}
2893EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2894
313a3dc7
CO		 2895/*
2896 * Read or write a bunch of msrs. All parameters are kernel addresses.
2897 *
2898 * @return number of msrs set successfully.
2899 */
2900static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2901 struct kvm_msr_entry *entries,
2902 int (*do_msr)(struct kvm_vcpu *vcpu,
2903 unsigned index, u64 *data))
2904{
801e459a 2905 int i;
313a3dc7 2906
313a3dc7
CO		 2907 for (i = 0; i < msrs->nmsrs; ++i)
2908 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2909 break;
2910
313a3dc7
CO		 2911 return i;
2912}
2913
2914/*
2915 * Read or write a bunch of msrs. Parameters are user addresses.
2916 *
2917 * @return number of msrs set successfully.
2918 */
2919static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2920 int (*do_msr)(struct kvm_vcpu *vcpu,
2921 unsigned index, u64 *data),
2922 int writeback)
2923{
2924 struct kvm_msrs msrs;
2925 struct kvm_msr_entry *entries;
2926 int r, n;
2927 unsigned size;
2928
2929 r = -EFAULT;
0e96f31e 2930 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 2931 goto out;
2932
2933 r = -E2BIG;
2934 if (msrs.nmsrs >= MAX_IO_MSRS)
2935 goto out;
2936
313a3dc7 2937 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2938 entries = memdup_user(user_msrs->entries, size);
2939 if (IS_ERR(entries)) {
2940 r = PTR_ERR(entries);
313a3dc7 2941 goto out;
ff5c2c03 2942 }
313a3dc7
CO		 2943
2944 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2945 if (r < 0)
2946 goto out_free;
2947
2948 r = -EFAULT;
2949 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2950 goto out_free;
2951
2952 r = n;
2953
2954out_free:
7a73c028 2955 kfree(entries);
313a3dc7
CO		 2956out:
2957 return r;
2958}
2959
4d5422ce
WL		 2960static inline bool kvm_can_mwait_in_guest(void)
2961{
2962 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2963 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2964 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2965}
2966
784aa3d7 2967int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2968{
4d5422ce 2969 int r = 0;
018d00d2
ZX		 2970
2971 switch (ext) {
2972 case KVM_CAP_IRQCHIP:
2973 case KVM_CAP_HLT:
2974 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2975 case KVM_CAP_SET_TSS_ADDR:
07716717 2976 case KVM_CAP_EXT_CPUID:
9c15bb1d 2977 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2978 case KVM_CAP_CLOCKSOURCE:
7837699f 2979 case KVM_CAP_PIT:
a28e4f5a 2980 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2981 case KVM_CAP_MP_STATE:
ed848624 2982 case KVM_CAP_SYNC_MMU:
a355c85c 2983 case KVM_CAP_USER_NMI:
52d939a0 2984 case KVM_CAP_REINJECT_CONTROL:
4925663a 2985 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2986 case KVM_CAP_IOEVENTFD:
f848a5a8 2987 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2988 case KVM_CAP_PIT2:
e9f42757 2989 case KVM_CAP_PIT_STATE2:
b927a3ce 2990 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2991 case KVM_CAP_XEN_HVM:
3cfc3092 2992 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2993 case KVM_CAP_HYPERV:
10388a07 2994 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2995 case KVM_CAP_HYPERV_SPIN:
5c919412 2996 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2997 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2998 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2999 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3000 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3001 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 3002 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3003 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3004 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3005 case KVM_CAP_DEBUGREGS:
d2be1651 3006 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3007 case KVM_CAP_XSAVE:
344d9588 3008 case KVM_CAP_ASYNC_PF:
92a1f12d 3009 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3010 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3011 case KVM_CAP_READONLY_MEM:
5f66b620 3012 case KVM_CAP_HYPERV_TIME:
100943c5 3013 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3014 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3015 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3016 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3017 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3018 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 3019 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3020 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3021 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3022 r = 1;
3023 break;
01643c51
KH		 3024 case KVM_CAP_SYNC_REGS:
3025 r = KVM_SYNC_X86_VALID_FIELDS;
3026 break;
e3fd9a93
PB		 3027 case KVM_CAP_ADJUST_CLOCK:
3028 r = KVM_CLOCK_TSC_STABLE;
3029 break;
4d5422ce 3030 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 3031 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 3032 if(kvm_can_mwait_in_guest())
3033 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3034 break;
6d396b55
PB		 3035 case KVM_CAP_X86_SMM:
3036 /* SMBASE is usually relocated above 1M on modern chipsets,
3037 * and SMM handlers might indeed rely on 4G segment limits,
3038 * so do not report SMM to be available if real mode is
3039 * emulated via vm86 mode. Still, do not go to great lengths
3040 * to avoid userspace's usage of the feature, because it is a
3041 * fringe case that is not enabled except via specific settings
3042 * of the module parameters.
3043 */
bc226f07 3044 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3045 break;
774ead3a
AK		 3046 case KVM_CAP_VAPIC:
3047 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3048 break;
f725230a 3049 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3050 r = KVM_SOFT_MAX_VCPUS;
3051 break;
3052 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3053 r = KVM_MAX_VCPUS;
3054 break;
a988b910 3055 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 3056 r = KVM_USER_MEM_SLOTS;
a988b910 3057 break;
a68a6a72
MT		 3058 case KVM_CAP_PV_MMU: /* obsolete */
3059 r = 0;
2f333bcb 3060 break;
890ca9ae
HY		 3061 case KVM_CAP_MCE:
3062 r = KVM_MAX_MCE_BANKS;
3063 break;
2d5b5a66 3064 case KVM_CAP_XCRS:
d366bf7e 3065 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3066 break;
92a1f12d
JR		 3067 case KVM_CAP_TSC_CONTROL:
3068 r = kvm_has_tsc_control;
3069 break;
37131313
RK		 3070 case KVM_CAP_X2APIC_API:
3071 r = KVM_X2APIC_API_VALID_FLAGS;
3072 break;
8fcc4b59
JM		 3073 case KVM_CAP_NESTED_STATE:
3074 r = kvm_x86_ops->get_nested_state ?
3075 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
3076 break;
018d00d2 3077 default:
018d00d2
ZX		 3078 break;
3079 }
3080 return r;
3081
3082}
3083
043405e1
CO		 3084long kvm_arch_dev_ioctl(struct file *filp,
3085 unsigned int ioctl, unsigned long arg)
3086{
3087 void __user *argp = (void __user *)arg;
3088 long r;
3089
3090 switch (ioctl) {
3091 case KVM_GET_MSR_INDEX_LIST: {
3092 struct kvm_msr_list __user *user_msr_list = argp;
3093 struct kvm_msr_list msr_list;
3094 unsigned n;
3095
3096 r = -EFAULT;
0e96f31e 3097 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3098 goto out;
3099 n = msr_list.nmsrs;
62ef68bb 3100 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3101 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3102 goto out;
3103 r = -E2BIG;
e125e7b6 3104 if (n < msr_list.nmsrs)
043405e1
CO		 3105 goto out;
3106 r = -EFAULT;
3107 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3108 num_msrs_to_save * sizeof(u32)))
3109 goto out;
e125e7b6 3110 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3111 &emulated_msrs,
62ef68bb 3112 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3113 goto out;
3114 r = 0;
3115 break;
3116 }
9c15bb1d
BP		 3117 case KVM_GET_SUPPORTED_CPUID:
3118 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3119 struct kvm_cpuid2 __user *cpuid_arg = argp;
3120 struct kvm_cpuid2 cpuid;
3121
3122 r = -EFAULT;
0e96f31e 3123 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3124 goto out;
9c15bb1d
BP		 3125
3126 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3127 ioctl);
674eea0f
AK		 3128 if (r)
3129 goto out;
3130
3131 r = -EFAULT;
0e96f31e 3132 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3133 goto out;
3134 r = 0;
3135 break;
3136 }
890ca9ae 3137 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3138 r = -EFAULT;
c45dcc71
AR		 3139 if (copy_to_user(argp, &kvm_mce_cap_supported,
3140 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3141 goto out;
3142 r = 0;
3143 break;
801e459a
TL		 3144 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3145 struct kvm_msr_list __user *user_msr_list = argp;
3146 struct kvm_msr_list msr_list;
3147 unsigned int n;
3148
3149 r = -EFAULT;
3150 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3151 goto out;
3152 n = msr_list.nmsrs;
3153 msr_list.nmsrs = num_msr_based_features;
3154 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3155 goto out;
3156 r = -E2BIG;
3157 if (n < msr_list.nmsrs)
3158 goto out;
3159 r = -EFAULT;
3160 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3161 num_msr_based_features * sizeof(u32)))
3162 goto out;
3163 r = 0;
3164 break;
3165 }
3166 case KVM_GET_MSRS:
3167 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3168 break;
890ca9ae 3169 }
043405e1
CO		 3170 default:
3171 r = -EINVAL;
3172 }
3173out:
3174 return r;
3175}
3176
f5f48ee1
SY		 3177static void wbinvd_ipi(void *garbage)
3178{
3179 wbinvd();
3180}
3181
3182static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3183{
e0f0bbc5 3184 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3185}
3186
313a3dc7
CO		 3187void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3188{
f5f48ee1
SY		 3189 /* Address WBINVD may be executed by guest */
3190 if (need_emulate_wbinvd(vcpu)) {
3191 if (kvm_x86_ops->has_wbinvd_exit())
3192 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3193 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3194 smp_call_function_single(vcpu->cpu,
3195 wbinvd_ipi, NULL, 1);
3196 }
3197
313a3dc7 3198 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3199
0dd6a6ed
ZA		 3200 /* Apply any externally detected TSC adjustments (due to suspend) */
3201 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3202 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3203 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3204 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3205 }
8f6055cb 3206
b0c39dc6 3207 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3208 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3209 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3210 if (tsc_delta < 0)
3211 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3212
b0c39dc6 3213 if (kvm_check_tsc_unstable()) {
07c1419a 3214 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3215 vcpu->arch.last_guest_tsc);
a545ab6a 3216 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3217 vcpu->arch.tsc_catchup = 1;
c285545f 3218 }
a749e247
PB		 3219
3220 if (kvm_lapic_hv_timer_in_use(vcpu))
3221 kvm_lapic_restart_hv_timer(vcpu);
3222
d98d07ca
MT		 3223 /*
3224 * On a host with synchronized TSC, there is no need to update
3225 * kvmclock on vcpu->cpu migration
3226 */
3227 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3228 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3229 if (vcpu->cpu != cpu)
1bd2009e 3230 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3231 vcpu->cpu = cpu;
6b7d7e76 3232 }
c9aaa895 3233
c9aaa895 3234 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3235}
3236
0b9f6c46
PX		 3237static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3238{
3239 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3240 return;
3241
fa55eedd 3242 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3243
4e335d9e 3244 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3245 &vcpu->arch.st.steal.preempted,
3246 offsetof(struct kvm_steal_time, preempted),
3247 sizeof(vcpu->arch.st.steal.preempted));
3248}
3249
313a3dc7
CO		 3250void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3251{
cc0d907c 3252 int idx;
de63ad4c
LM		 3253
3254 if (vcpu->preempted)
3255 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3256
931f261b
AA		 3257 /*
3258 * Disable page faults because we're in atomic context here.
3259 * kvm_write_guest_offset_cached() would call might_fault()
3260 * that relies on pagefault_disable() to tell if there's a
3261 * bug. NOTE: the write to guest memory may not go through if
3262 * during postcopy live migration or if there's heavy guest
3263 * paging.
3264 */
3265 pagefault_disable();
cc0d907c
AA		 3266 /*
3267 * kvm_memslots() will be called by
3268 * kvm_write_guest_offset_cached() so take the srcu lock.
3269 */
3270 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3271 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3272 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3273 pagefault_enable();
02daab21 3274 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3275 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3276 /*
f9dcf08e
RK		 3277 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3278 * on every vmexit, but if not, we might have a stale dr6 from the
3279 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3280 */
f9dcf08e 3281 set_debugreg(0, 6);
313a3dc7
CO		 3282}
3283
313a3dc7
CO		 3284static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3285 struct kvm_lapic_state *s)
3286{
fa59cc00 3287 if (vcpu->arch.apicv_active)
d62caabb
AS		 3288 kvm_x86_ops->sync_pir_to_irr(vcpu);
3289
a92e2543 3290 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3291}
3292
3293static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3294 struct kvm_lapic_state *s)
3295{
a92e2543
RK		 3296 int r;
3297
3298 r = kvm_apic_set_state(vcpu, s);
3299 if (r)
3300 return r;
cb142eb7 3301 update_cr8_intercept(vcpu);
313a3dc7
CO		 3302
3303 return 0;
3304}
3305
127a457a
MG		 3306static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3307{
3308 return (!lapic_in_kernel(vcpu) ||
3309 kvm_apic_accept_pic_intr(vcpu));
3310}
3311
782d422b
MG		 3312/*
3313 * if userspace requested an interrupt window, check that the
3314 * interrupt window is open.
3315 *
3316 * No need to exit to userspace if we already have an interrupt queued.
3317 */
3318static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3319{
3320 return kvm_arch_interrupt_allowed(vcpu) &&
3321 !kvm_cpu_has_interrupt(vcpu) &&
3322 !kvm_event_needs_reinjection(vcpu) &&
3323 kvm_cpu_accept_dm_intr(vcpu);
3324}
3325
f77bc6a4
ZX		 3326static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3327 struct kvm_interrupt *irq)
3328{
02cdb50f 3329 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3330 return -EINVAL;
1c1a9ce9
SR		 3331
3332 if (!irqchip_in_kernel(vcpu->kvm)) {
3333 kvm_queue_interrupt(vcpu, irq->irq, false);
3334 kvm_make_request(KVM_REQ_EVENT, vcpu);
3335 return 0;
3336 }
3337
3338 /*
3339 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3340 * fail for in-kernel 8259.
3341 */
3342 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3343 return -ENXIO;
f77bc6a4 3344
1c1a9ce9
SR		 3345 if (vcpu->arch.pending_external_vector != -1)
3346 return -EEXIST;
f77bc6a4 3347
1c1a9ce9 3348 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3349 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3350 return 0;
3351}
3352
c4abb7c9
JK		 3353static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3354{
c4abb7c9 3355 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3356
3357 return 0;
3358}
3359
f077825a
PB		 3360static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3361{
64d60670
PB		 3362 kvm_make_request(KVM_REQ_SMI, vcpu);
3363
f077825a
PB		 3364 return 0;
3365}
3366
b209749f
AK		 3367static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3368 struct kvm_tpr_access_ctl *tac)
3369{
3370 if (tac->flags)
3371 return -EINVAL;
3372 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3373 return 0;
3374}
3375
890ca9ae
HY		 3376static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3377 u64 mcg_cap)
3378{
3379 int r;
3380 unsigned bank_num = mcg_cap & 0xff, bank;
3381
3382 r = -EINVAL;
a9e38c3e 3383 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3384 goto out;
c45dcc71 3385 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3386 goto out;
3387 r = 0;
3388 vcpu->arch.mcg_cap = mcg_cap;
3389 /* Init IA32_MCG_CTL to all 1s */
3390 if (mcg_cap & MCG_CTL_P)
3391 vcpu->arch.mcg_ctl = ~(u64)0;
3392 /* Init IA32_MCi_CTL to all 1s */
3393 for (bank = 0; bank < bank_num; bank++)
3394 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3395
3396 if (kvm_x86_ops->setup_mce)
3397 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3398out:
3399 return r;
3400}
3401
3402static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3403 struct kvm_x86_mce *mce)
3404{
3405 u64 mcg_cap = vcpu->arch.mcg_cap;
3406 unsigned bank_num = mcg_cap & 0xff;
3407 u64 *banks = vcpu->arch.mce_banks;
3408
3409 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3410 return -EINVAL;
3411 /*
3412 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3413 * reporting is disabled
3414 */
3415 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3416 vcpu->arch.mcg_ctl != ~(u64)0)
3417 return 0;
3418 banks += 4 * mce->bank;
3419 /*
3420 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3421 * reporting is disabled for the bank
3422 */
3423 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3424 return 0;
3425 if (mce->status & MCI_STATUS_UC) {
3426 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3427 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3428 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3429 return 0;
3430 }
3431 if (banks[1] & MCI_STATUS_VAL)
3432 mce->status |= MCI_STATUS_OVER;
3433 banks[2] = mce->addr;
3434 banks[3] = mce->misc;
3435 vcpu->arch.mcg_status = mce->mcg_status;
3436 banks[1] = mce->status;
3437 kvm_queue_exception(vcpu, MC_VECTOR);
3438 } else if (!(banks[1] & MCI_STATUS_VAL)
3439 || !(banks[1] & MCI_STATUS_UC)) {
3440 if (banks[1] & MCI_STATUS_VAL)
3441 mce->status |= MCI_STATUS_OVER;
3442 banks[2] = mce->addr;
3443 banks[3] = mce->misc;
3444 banks[1] = mce->status;
3445 } else
3446 banks[1] |= MCI_STATUS_OVER;
3447 return 0;
3448}
3449
3cfc3092
JK		 3450static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3451 struct kvm_vcpu_events *events)
3452{
7460fb4a 3453 process_nmi(vcpu);
59073aaf 3454
664f8e26 3455 /*
59073aaf
JM		 3456 * The API doesn't provide the instruction length for software
3457 * exceptions, so don't report them. As long as the guest RIP
3458 * isn't advanced, we should expect to encounter the exception
3459 * again.
664f8e26 3460 */
59073aaf
JM		 3461 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3462 events->exception.injected = 0;
3463 events->exception.pending = 0;
3464 } else {
3465 events->exception.injected = vcpu->arch.exception.injected;
3466 events->exception.pending = vcpu->arch.exception.pending;
3467 /*
3468 * For ABI compatibility, deliberately conflate
3469 * pending and injected exceptions when
3470 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3471 */
3472 if (!vcpu->kvm->arch.exception_payload_enabled)
3473 events->exception.injected |=
3474 vcpu->arch.exception.pending;
3475 }
3cfc3092
JK		 3476 events->exception.nr = vcpu->arch.exception.nr;
3477 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3478 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3479 events->exception_has_payload = vcpu->arch.exception.has_payload;
3480 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3481
03b82a30 3482 events->interrupt.injected =
04140b41 3483 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3484 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3485 events->interrupt.soft = 0;
37ccdcbe 3486 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3487
3488 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3489 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3490 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3491 events->nmi.pad = 0;
3cfc3092 3492
66450a21 3493 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3494
f077825a
PB		 3495 events->smi.smm = is_smm(vcpu);
3496 events->smi.pending = vcpu->arch.smi_pending;
3497 events->smi.smm_inside_nmi =
3498 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3499 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3500
dab4b911 3501 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3502 | KVM_VCPUEVENT_VALID_SHADOW
3503 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3504 if (vcpu->kvm->arch.exception_payload_enabled)
3505 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3506
97e69aa6 3507 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3508}
3509
6ef4e07e
XG		 3510static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3511
3cfc3092
JK		 3512static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3513 struct kvm_vcpu_events *events)
3514{
dab4b911 3515 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3516 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3517 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3518 | KVM_VCPUEVENT_VALID_SMM
3519 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3520 return -EINVAL;
3521
59073aaf
JM		 3522 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3523 if (!vcpu->kvm->arch.exception_payload_enabled)
3524 return -EINVAL;
3525 if (events->exception.pending)
3526 events->exception.injected = 0;
3527 else
3528 events->exception_has_payload = 0;
3529 } else {
3530 events->exception.pending = 0;
3531 events->exception_has_payload = 0;
3532 }
3533
3534 if ((events->exception.injected || events->exception.pending) &&
3535 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3536 return -EINVAL;
3537
28bf2888
DH		 3538 /* INITs are latched while in SMM */
3539 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3540 (events->smi.smm || events->smi.pending) &&
3541 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3542 return -EINVAL;
3543
7460fb4a 3544 process_nmi(vcpu);
59073aaf
JM		 3545 vcpu->arch.exception.injected = events->exception.injected;
3546 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3547 vcpu->arch.exception.nr = events->exception.nr;
3548 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3549 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3550 vcpu->arch.exception.has_payload = events->exception_has_payload;
3551 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3552
04140b41 3553 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3554 vcpu->arch.interrupt.nr = events->interrupt.nr;
3555 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3556 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3557 kvm_x86_ops->set_interrupt_shadow(vcpu,
3558 events->interrupt.shadow);
3cfc3092
JK		 3559
3560 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3561 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3562 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3563 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3564
66450a21 3565 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3566 lapic_in_kernel(vcpu))
66450a21 3567 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3568
f077825a 3569 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3570 u32 hflags = vcpu->arch.hflags;
f077825a 3571 if (events->smi.smm)
6ef4e07e 3572 hflags |= HF_SMM_MASK;
f077825a 3573 else
6ef4e07e
XG		 3574 hflags &= ~HF_SMM_MASK;
3575 kvm_set_hflags(vcpu, hflags);
3576
f077825a 3577 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3578
3579 if (events->smi.smm) {
3580 if (events->smi.smm_inside_nmi)
3581 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3582 else
f4ef1910
WL		 3583 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3584 if (lapic_in_kernel(vcpu)) {
3585 if (events->smi.latched_init)
3586 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3587 else
3588 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3589 }
f077825a
PB		 3590 }
3591 }
3592
3842d135
AK		 3593 kvm_make_request(KVM_REQ_EVENT, vcpu);
3594
3cfc3092
JK		 3595 return 0;
3596}
3597
a1efbe77
JK		 3598static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3599 struct kvm_debugregs *dbgregs)
3600{
73aaf249
JK		 3601 unsigned long val;
3602
a1efbe77 3603 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3604 kvm_get_dr(vcpu, 6, &val);
73aaf249 3605 dbgregs->dr6 = val;
a1efbe77
JK		 3606 dbgregs->dr7 = vcpu->arch.dr7;
3607 dbgregs->flags = 0;
97e69aa6 3608 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3609}
3610
3611static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3612 struct kvm_debugregs *dbgregs)
3613{
3614 if (dbgregs->flags)
3615 return -EINVAL;
3616
d14bdb55
PB		 3617 if (dbgregs->dr6 & ~0xffffffffull)
3618 return -EINVAL;
3619 if (dbgregs->dr7 & ~0xffffffffull)
3620 return -EINVAL;
3621
a1efbe77 3622 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3623 kvm_update_dr0123(vcpu);
a1efbe77 3624 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3625 kvm_update_dr6(vcpu);
a1efbe77 3626 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3627 kvm_update_dr7(vcpu);
a1efbe77 3628
a1efbe77
JK		 3629 return 0;
3630}
3631
df1daba7
PB		 3632#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3633
3634static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3635{
b666a4b6 3636 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3637 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3638 u64 valid;
3639
3640 /*
3641 * Copy legacy XSAVE area, to avoid complications with CPUID
3642 * leaves 0 and 1 in the loop below.
3643 */
3644 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3645
3646 /* Set XSTATE_BV */
00c87e9a 3647 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3648 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3649
3650 /*
3651 * Copy each region from the possibly compacted offset to the
3652 * non-compacted offset.
3653 */
d91cab78 3654 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3655 while (valid) {
3656 u64 feature = valid & -valid;
3657 int index = fls64(feature) - 1;
3658 void *src = get_xsave_addr(xsave, feature);
3659
3660 if (src) {
3661 u32 size, offset, ecx, edx;
3662 cpuid_count(XSTATE_CPUID, index,
3663 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3664 if (feature == XFEATURE_MASK_PKRU)
3665 memcpy(dest + offset, &vcpu->arch.pkru,
3666 sizeof(vcpu->arch.pkru));
3667 else
3668 memcpy(dest + offset, src, size);
3669
df1daba7
PB		 3670 }
3671
3672 valid -= feature;
3673 }
3674}
3675
3676static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3677{
b666a4b6 3678 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3679 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3680 u64 valid;
3681
3682 /*
3683 * Copy legacy XSAVE area, to avoid complications with CPUID
3684 * leaves 0 and 1 in the loop below.
3685 */
3686 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3687
3688 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3689 xsave->header.xfeatures = xstate_bv;
782511b0 3690 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3691 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3692
3693 /*
3694 * Copy each region from the non-compacted offset to the
3695 * possibly compacted offset.
3696 */
d91cab78 3697 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3698 while (valid) {
3699 u64 feature = valid & -valid;
3700 int index = fls64(feature) - 1;
3701 void *dest = get_xsave_addr(xsave, feature);
3702
3703 if (dest) {
3704 u32 size, offset, ecx, edx;
3705 cpuid_count(XSTATE_CPUID, index,
3706 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3707 if (feature == XFEATURE_MASK_PKRU)
3708 memcpy(&vcpu->arch.pkru, src + offset,
3709 sizeof(vcpu->arch.pkru));
3710 else
3711 memcpy(dest, src + offset, size);
ee4100da 3712 }
df1daba7
PB		 3713
3714 valid -= feature;
3715 }
3716}
3717
2d5b5a66
SY		 3718static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3719 struct kvm_xsave *guest_xsave)
3720{
d366bf7e 3721 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3722 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3723 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3724 } else {
2d5b5a66 3725 memcpy(guest_xsave->region,
b666a4b6 3726 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3727 sizeof(struct fxregs_state));
2d5b5a66 3728 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3729 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3730 }
3731}
3732
a575813b
WL		 3733#define XSAVE_MXCSR_OFFSET 24
3734
2d5b5a66
SY		 3735static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3736 struct kvm_xsave *guest_xsave)
3737{
3738 u64 xstate_bv =
3739 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3740 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3741
d366bf7e 3742 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3743 /*
3744 * Here we allow setting states that are not present in
3745 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3746 * with old userspace.
3747 */
a575813b
WL		 3748 if (xstate_bv & ~kvm_supported_xcr0() ||
3749 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3750 return -EINVAL;
df1daba7 3751 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3752 } else {
a575813b
WL		 3753 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3754 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3755 return -EINVAL;
b666a4b6 3756 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3757 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3758 }
3759 return 0;
3760}
3761
3762static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3763 struct kvm_xcrs *guest_xcrs)
3764{
d366bf7e 3765 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3766 guest_xcrs->nr_xcrs = 0;
3767 return;
3768 }
3769
3770 guest_xcrs->nr_xcrs = 1;
3771 guest_xcrs->flags = 0;
3772 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3773 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3774}
3775
3776static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3777 struct kvm_xcrs *guest_xcrs)
3778{
3779 int i, r = 0;
3780
d366bf7e 3781 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3782 return -EINVAL;
3783
3784 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3785 return -EINVAL;
3786
3787 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3788 /* Only support XCR0 currently */
c67a04cb 3789 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3790 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3791 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3792 break;
3793 }
3794 if (r)
3795 r = -EINVAL;
3796 return r;
3797}
3798
1c0b28c2
EM		 3799/*
3800 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3801 * stopped by the hypervisor. This function will be called from the host only.
3802 * EINVAL is returned when the host attempts to set the flag for a guest that
3803 * does not support pv clocks.
3804 */
3805static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3806{
0b79459b 3807 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3808 return -EINVAL;
51d59c6b 3809 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3810 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3811 return 0;
3812}
3813
5c919412
AS		 3814static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3815 struct kvm_enable_cap *cap)
3816{
57b119da
VK		 3817 int r;
3818 uint16_t vmcs_version;
3819 void __user *user_ptr;
3820
5c919412
AS		 3821 if (cap->flags)
3822 return -EINVAL;
3823
3824 switch (cap->cap) {
efc479e6
RK		 3825 case KVM_CAP_HYPERV_SYNIC2:
3826 if (cap->args[0])
3827 return -EINVAL;
5c919412 3828 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3829 if (!irqchip_in_kernel(vcpu->kvm))
3830 return -EINVAL;
efc479e6
RK		 3831 return kvm_hv_activate_synic(vcpu, cap->cap ==
3832 KVM_CAP_HYPERV_SYNIC2);
57b119da 3833 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 3834 if (!kvm_x86_ops->nested_enable_evmcs)
3835 return -ENOTTY;
57b119da
VK		 3836 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3837 if (!r) {
3838 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3839 if (copy_to_user(user_ptr, &vmcs_version,
3840 sizeof(vmcs_version)))
3841 r = -EFAULT;
3842 }
3843 return r;
3844
5c919412
AS		 3845 default:
3846 return -EINVAL;
3847 }
3848}
3849
313a3dc7
CO		 3850long kvm_arch_vcpu_ioctl(struct file *filp,
3851 unsigned int ioctl, unsigned long arg)
3852{
3853 struct kvm_vcpu *vcpu = filp->private_data;
3854 void __user *argp = (void __user *)arg;
3855 int r;
d1ac91d8
AK		 3856 union {
3857 struct kvm_lapic_state *lapic;
3858 struct kvm_xsave *xsave;
3859 struct kvm_xcrs *xcrs;
3860 void *buffer;
3861 } u;
3862
9b062471
CD		 3863 vcpu_load(vcpu);
3864
d1ac91d8 3865 u.buffer = NULL;
313a3dc7
CO		 3866 switch (ioctl) {
3867 case KVM_GET_LAPIC: {
2204ae3c 3868 r = -EINVAL;
bce87cce 3869 if (!lapic_in_kernel(vcpu))
2204ae3c 3870 goto out;
d1ac91d8 3871 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3872
b772ff36 3873 r = -ENOMEM;
d1ac91d8 3874 if (!u.lapic)
b772ff36 3875 goto out;
d1ac91d8 3876 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3877 if (r)
3878 goto out;
3879 r = -EFAULT;
d1ac91d8 3880 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3881 goto out;
3882 r = 0;
3883 break;
3884 }
3885 case KVM_SET_LAPIC: {
2204ae3c 3886 r = -EINVAL;
bce87cce 3887 if (!lapic_in_kernel(vcpu))
2204ae3c 3888 goto out;
ff5c2c03 3889 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3890 if (IS_ERR(u.lapic)) {
3891 r = PTR_ERR(u.lapic);
3892 goto out_nofree;
3893 }
ff5c2c03 3894
d1ac91d8 3895 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3896 break;
3897 }
f77bc6a4
ZX		 3898 case KVM_INTERRUPT: {
3899 struct kvm_interrupt irq;
3900
3901 r = -EFAULT;
0e96f31e 3902 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 3903 goto out;
3904 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3905 break;
3906 }
c4abb7c9
JK		 3907 case KVM_NMI: {
3908 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3909 break;
3910 }
f077825a
PB		 3911 case KVM_SMI: {
3912 r = kvm_vcpu_ioctl_smi(vcpu);
3913 break;
3914 }
313a3dc7
CO		 3915 case KVM_SET_CPUID: {
3916 struct kvm_cpuid __user *cpuid_arg = argp;
3917 struct kvm_cpuid cpuid;
3918
3919 r = -EFAULT;
0e96f31e 3920 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 3921 goto out;
3922 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3923 break;
3924 }
07716717
DK		 3925 case KVM_SET_CPUID2: {
3926 struct kvm_cpuid2 __user *cpuid_arg = argp;
3927 struct kvm_cpuid2 cpuid;
3928
3929 r = -EFAULT;
0e96f31e 3930 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 3931 goto out;
3932 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3933 cpuid_arg->entries);
07716717
DK		 3934 break;
3935 }
3936 case KVM_GET_CPUID2: {
3937 struct kvm_cpuid2 __user *cpuid_arg = argp;
3938 struct kvm_cpuid2 cpuid;
3939
3940 r = -EFAULT;
0e96f31e 3941 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 3942 goto out;
3943 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3944 cpuid_arg->entries);
07716717
DK		 3945 if (r)
3946 goto out;
3947 r = -EFAULT;
0e96f31e 3948 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 3949 goto out;
3950 r = 0;
3951 break;
3952 }
801e459a
TL		 3953 case KVM_GET_MSRS: {
3954 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3955 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3956 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3957 break;
801e459a
TL		 3958 }
3959 case KVM_SET_MSRS: {
3960 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3961 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3962 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3963 break;
801e459a 3964 }
b209749f
AK		 3965 case KVM_TPR_ACCESS_REPORTING: {
3966 struct kvm_tpr_access_ctl tac;
3967
3968 r = -EFAULT;
0e96f31e 3969 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 3970 goto out;
3971 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3972 if (r)
3973 goto out;
3974 r = -EFAULT;
0e96f31e 3975 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 3976 goto out;
3977 r = 0;
3978 break;
3979 };
b93463aa
AK		 3980 case KVM_SET_VAPIC_ADDR: {
3981 struct kvm_vapic_addr va;
7301d6ab 3982 int idx;
b93463aa
AK		 3983
3984 r = -EINVAL;
35754c98 3985 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3986 goto out;
3987 r = -EFAULT;
0e96f31e 3988 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 3989 goto out;
7301d6ab 3990 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3991 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3992 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3993 break;
3994 }
890ca9ae
HY		 3995 case KVM_X86_SETUP_MCE: {
3996 u64 mcg_cap;
3997
3998 r = -EFAULT;
0e96f31e 3999 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4000 goto out;
4001 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4002 break;
4003 }
4004 case KVM_X86_SET_MCE: {
4005 struct kvm_x86_mce mce;
4006
4007 r = -EFAULT;
0e96f31e 4008 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4009 goto out;
4010 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4011 break;
4012 }
3cfc3092
JK		 4013 case KVM_GET_VCPU_EVENTS: {
4014 struct kvm_vcpu_events events;
4015
4016 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4017
4018 r = -EFAULT;
4019 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4020 break;
4021 r = 0;
4022 break;
4023 }
4024 case KVM_SET_VCPU_EVENTS: {
4025 struct kvm_vcpu_events events;
4026
4027 r = -EFAULT;
4028 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4029 break;
4030
4031 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4032 break;
4033 }
a1efbe77
JK		 4034 case KVM_GET_DEBUGREGS: {
4035 struct kvm_debugregs dbgregs;
4036
4037 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4038
4039 r = -EFAULT;
4040 if (copy_to_user(argp, &dbgregs,
4041 sizeof(struct kvm_debugregs)))
4042 break;
4043 r = 0;
4044 break;
4045 }
4046 case KVM_SET_DEBUGREGS: {
4047 struct kvm_debugregs dbgregs;
4048
4049 r = -EFAULT;
4050 if (copy_from_user(&dbgregs, argp,
4051 sizeof(struct kvm_debugregs)))
4052 break;
4053
4054 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4055 break;
4056 }
2d5b5a66 4057 case KVM_GET_XSAVE: {
d1ac91d8 4058 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 4059 r = -ENOMEM;
d1ac91d8 4060 if (!u.xsave)
2d5b5a66
SY		 4061 break;
4062
d1ac91d8 4063 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4064
4065 r = -EFAULT;
d1ac91d8 4066 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4067 break;
4068 r = 0;
4069 break;
4070 }
4071 case KVM_SET_XSAVE: {
ff5c2c03 4072 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4073 if (IS_ERR(u.xsave)) {
4074 r = PTR_ERR(u.xsave);
4075 goto out_nofree;
4076 }
2d5b5a66 4077
d1ac91d8 4078 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4079 break;
4080 }
4081 case KVM_GET_XCRS: {
d1ac91d8 4082 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 4083 r = -ENOMEM;
d1ac91d8 4084 if (!u.xcrs)
2d5b5a66
SY		 4085 break;
4086
d1ac91d8 4087 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4088
4089 r = -EFAULT;
d1ac91d8 4090 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4091 sizeof(struct kvm_xcrs)))
4092 break;
4093 r = 0;
4094 break;
4095 }
4096 case KVM_SET_XCRS: {
ff5c2c03 4097 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4098 if (IS_ERR(u.xcrs)) {
4099 r = PTR_ERR(u.xcrs);
4100 goto out_nofree;
4101 }
2d5b5a66 4102
d1ac91d8 4103 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4104 break;
4105 }
92a1f12d
JR		 4106 case KVM_SET_TSC_KHZ: {
4107 u32 user_tsc_khz;
4108
4109 r = -EINVAL;
92a1f12d
JR		 4110 user_tsc_khz = (u32)arg;
4111
4112 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4113 goto out;
4114
cc578287
ZA		 4115 if (user_tsc_khz == 0)
4116 user_tsc_khz = tsc_khz;
4117
381d585c
HZ		 4118 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4119 r = 0;
92a1f12d 4120
92a1f12d
JR		 4121 goto out;
4122 }
4123 case KVM_GET_TSC_KHZ: {
cc578287 4124 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4125 goto out;
4126 }
1c0b28c2
EM		 4127 case KVM_KVMCLOCK_CTRL: {
4128 r = kvm_set_guest_paused(vcpu);
4129 goto out;
4130 }
5c919412
AS		 4131 case KVM_ENABLE_CAP: {
4132 struct kvm_enable_cap cap;
4133
4134 r = -EFAULT;
4135 if (copy_from_user(&cap, argp, sizeof(cap)))
4136 goto out;
4137 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4138 break;
4139 }
8fcc4b59
JM		 4140 case KVM_GET_NESTED_STATE: {
4141 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4142 u32 user_data_size;
4143
4144 r = -EINVAL;
4145 if (!kvm_x86_ops->get_nested_state)
4146 break;
4147
4148 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4149 r = -EFAULT;
8fcc4b59 4150 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4151 break;
8fcc4b59
JM		 4152
4153 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4154 user_data_size);
4155 if (r < 0)
26b471c7 4156 break;
8fcc4b59
JM		 4157
4158 if (r > user_data_size) {
4159 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4160 r = -EFAULT;
4161 else
4162 r = -E2BIG;
4163 break;
8fcc4b59 4164 }
26b471c7 4165
8fcc4b59
JM		 4166 r = 0;
4167 break;
4168 }
4169 case KVM_SET_NESTED_STATE: {
4170 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4171 struct kvm_nested_state kvm_state;
4172
4173 r = -EINVAL;
4174 if (!kvm_x86_ops->set_nested_state)
4175 break;
4176
26b471c7 4177 r = -EFAULT;
8fcc4b59 4178 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4179 break;
8fcc4b59 4180
26b471c7 4181 r = -EINVAL;
8fcc4b59 4182 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4183 break;
8fcc4b59
JM		 4184
4185 if (kvm_state.flags &
8cab6507
VK		 4186 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4187 | KVM_STATE_NESTED_EVMCS))
26b471c7 4188 break;
8fcc4b59
JM		 4189
4190 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4191 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4192 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4193 break;
8fcc4b59
JM		 4194
4195 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4196 break;
4197 }
2bc39970
VK		 4198 case KVM_GET_SUPPORTED_HV_CPUID: {
4199 struct kvm_cpuid2 __user *cpuid_arg = argp;
4200 struct kvm_cpuid2 cpuid;
4201
4202 r = -EFAULT;
4203 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4204 goto out;
4205
4206 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4207 cpuid_arg->entries);
4208 if (r)
4209 goto out;
4210
4211 r = -EFAULT;
4212 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4213 goto out;
4214 r = 0;
4215 break;
4216 }
313a3dc7
CO		 4217 default:
4218 r = -EINVAL;
4219 }
4220out:
d1ac91d8 4221 kfree(u.buffer);
9b062471
CD		 4222out_nofree:
4223 vcpu_put(vcpu);
313a3dc7
CO		 4224 return r;
4225}
4226
1499fa80 4227vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4228{
4229 return VM_FAULT_SIGBUS;
4230}
4231
1fe779f8
CO		 4232static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4233{
4234 int ret;
4235
4236 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4237 return -EINVAL;
1fe779f8
CO		 4238 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4239 return ret;
4240}
4241
b927a3ce
SY		 4242static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4243 u64 ident_addr)
4244{
2ac52ab8 4245 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4246}
4247
1fe779f8
CO		 4248static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4249 u32 kvm_nr_mmu_pages)
4250{
4251 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4252 return -EINVAL;
4253
79fac95e 4254 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4255
4256 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4257 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4258
79fac95e 4259 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4260 return 0;
4261}
4262
4263static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4264{
39de71ec 4265 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4266}
4267
1fe779f8
CO		 4268static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4269{
90bca052 4270 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4271 int r;
4272
4273 r = 0;
4274 switch (chip->chip_id) {
4275 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4276 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4277 sizeof(struct kvm_pic_state));
4278 break;
4279 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4280 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4281 sizeof(struct kvm_pic_state));
4282 break;
4283 case KVM_IRQCHIP_IOAPIC:
33392b49 4284 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4285 break;
4286 default:
4287 r = -EINVAL;
4288 break;
4289 }
4290 return r;
4291}
4292
4293static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4294{
90bca052 4295 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4296 int r;
4297
4298 r = 0;
4299 switch (chip->chip_id) {
4300 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4301 spin_lock(&pic->lock);
4302 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4303 sizeof(struct kvm_pic_state));
90bca052 4304 spin_unlock(&pic->lock);
1fe779f8
CO		 4305 break;
4306 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4307 spin_lock(&pic->lock);
4308 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4309 sizeof(struct kvm_pic_state));
90bca052 4310 spin_unlock(&pic->lock);
1fe779f8
CO		 4311 break;
4312 case KVM_IRQCHIP_IOAPIC:
33392b49 4313 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4314 break;
4315 default:
4316 r = -EINVAL;
4317 break;
4318 }
90bca052 4319 kvm_pic_update_irq(pic);
1fe779f8
CO		 4320 return r;
4321}
4322
e0f63cb9
SY		 4323static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4324{
34f3941c
RK		 4325 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4326
4327 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4328
4329 mutex_lock(&kps->lock);
4330 memcpy(ps, &kps->channels, sizeof(*ps));
4331 mutex_unlock(&kps->lock);
2da29bcc 4332 return 0;
e0f63cb9
SY		 4333}
4334
4335static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4336{
0185604c 4337 int i;
09edea72
RK		 4338 struct kvm_pit *pit = kvm->arch.vpit;
4339
4340 mutex_lock(&pit->pit_state.lock);
34f3941c 4341 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4342 for (i = 0; i < 3; i++)
09edea72
RK		 4343 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4344 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4345 return 0;
e9f42757
BK		 4346}
4347
4348static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4349{
e9f42757
BK		 4350 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4351 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4352 sizeof(ps->channels));
4353 ps->flags = kvm->arch.vpit->pit_state.flags;
4354 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4355 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4356 return 0;
e9f42757
BK		 4357}
4358
4359static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4360{
2da29bcc 4361 int start = 0;
0185604c 4362 int i;
e9f42757 4363 u32 prev_legacy, cur_legacy;
09edea72
RK		 4364 struct kvm_pit *pit = kvm->arch.vpit;
4365
4366 mutex_lock(&pit->pit_state.lock);
4367 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4368 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4369 if (!prev_legacy && cur_legacy)
4370 start = 1;
09edea72
RK		 4371 memcpy(&pit->pit_state.channels, &ps->channels,
4372 sizeof(pit->pit_state.channels));
4373 pit->pit_state.flags = ps->flags;
0185604c 4374 for (i = 0; i < 3; i++)
09edea72 4375 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4376 start && i == 0);
09edea72 4377 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4378 return 0;
e0f63cb9
SY		 4379}
4380
52d939a0
MT		 4381static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4382 struct kvm_reinject_control *control)
4383{
71474e2f
RK		 4384 struct kvm_pit *pit = kvm->arch.vpit;
4385
4386 if (!pit)
52d939a0 4387 return -ENXIO;
b39c90b6 4388
71474e2f
RK		 4389 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4390 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4391 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4392 */
4393 mutex_lock(&pit->pit_state.lock);
4394 kvm_pit_set_reinject(pit, control->pit_reinject);
4395 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4396
52d939a0
MT		 4397 return 0;
4398}
4399
95d4c16c 4400/**
60c34612
TY		 4401 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4402 * @kvm: kvm instance
4403 * @log: slot id and address to which we copy the log
95d4c16c 4404 *
e108ff2f
PB		 4405 * Steps 1-4 below provide general overview of dirty page logging. See
4406 * kvm_get_dirty_log_protect() function description for additional details.
4407 *
4408 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4409 * always flush the TLB (step 4) even if previous step failed and the dirty
4410 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4411 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4412 * writes will be marked dirty for next log read.
95d4c16c 4413 *
60c34612
TY		 4414 * 1. Take a snapshot of the bit and clear it if needed.
4415 * 2. Write protect the corresponding page.
e108ff2f
PB		 4416 * 3. Copy the snapshot to the userspace.
4417 * 4. Flush TLB's if needed.
5bb064dc 4418 */
60c34612 4419int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4420{
8fe65a82 4421 bool flush = false;
e108ff2f 4422 int r;
5bb064dc 4423
79fac95e 4424 mutex_lock(&kvm->slots_lock);
5bb064dc 4425
88178fd4
KH		 4426 /*
4427 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4428 */
4429 if (kvm_x86_ops->flush_log_dirty)
4430 kvm_x86_ops->flush_log_dirty(kvm);
4431
8fe65a82 4432 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4433
4434 /*
4435 * All the TLBs can be flushed out of mmu lock, see the comments in
4436 * kvm_mmu_slot_remove_write_access().
4437 */
e108ff2f 4438 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4439 if (flush)
2a31b9db
PB		 4440 kvm_flush_remote_tlbs(kvm);
4441
4442 mutex_unlock(&kvm->slots_lock);
4443 return r;
4444}
4445
4446int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4447{
4448 bool flush = false;
4449 int r;
4450
4451 mutex_lock(&kvm->slots_lock);
4452
4453 /*
4454 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4455 */
4456 if (kvm_x86_ops->flush_log_dirty)
4457 kvm_x86_ops->flush_log_dirty(kvm);
4458
4459 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4460
4461 /*
4462 * All the TLBs can be flushed out of mmu lock, see the comments in
4463 * kvm_mmu_slot_remove_write_access().
4464 */
4465 lockdep_assert_held(&kvm->slots_lock);
4466 if (flush)
198c74f4
XG		 4467 kvm_flush_remote_tlbs(kvm);
4468
79fac95e 4469 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4470 return r;
4471}
4472
aa2fbe6d
YZ		 4473int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4474 bool line_status)
23d43cf9
CD		 4475{
4476 if (!irqchip_in_kernel(kvm))
4477 return -ENXIO;
4478
4479 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4480 irq_event->irq, irq_event->level,
4481 line_status);
23d43cf9
CD		 4482 return 0;
4483}
4484
e5d83c74
PB		 4485int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4486 struct kvm_enable_cap *cap)
90de4a18
NA		 4487{
4488 int r;
4489
4490 if (cap->flags)
4491 return -EINVAL;
4492
4493 switch (cap->cap) {
4494 case KVM_CAP_DISABLE_QUIRKS:
4495 kvm->arch.disabled_quirks = cap->args[0];
4496 r = 0;
4497 break;
49df6397
SR		 4498 case KVM_CAP_SPLIT_IRQCHIP: {
4499 mutex_lock(&kvm->lock);
b053b2ae
SR		 4500 r = -EINVAL;
4501 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4502 goto split_irqchip_unlock;
49df6397
SR		 4503 r = -EEXIST;
4504 if (irqchip_in_kernel(kvm))
4505 goto split_irqchip_unlock;
557abc40 4506 if (kvm->created_vcpus)
49df6397
SR		 4507 goto split_irqchip_unlock;
4508 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4509 if (r)
49df6397
SR		 4510 goto split_irqchip_unlock;
4511 /* Pairs with irqchip_in_kernel. */
4512 smp_wmb();
49776faf 4513 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4514 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4515 r = 0;
4516split_irqchip_unlock:
4517 mutex_unlock(&kvm->lock);
4518 break;
4519 }
37131313
RK		 4520 case KVM_CAP_X2APIC_API:
4521 r = -EINVAL;
4522 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4523 break;
4524
4525 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4526 kvm->arch.x2apic_format = true;
c519265f
RK		 4527 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4528 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4529
4530 r = 0;
4531 break;
4d5422ce
WL		 4532 case KVM_CAP_X86_DISABLE_EXITS:
4533 r = -EINVAL;
4534 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4535 break;
4536
4537 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4538 kvm_can_mwait_in_guest())
4539 kvm->arch.mwait_in_guest = true;
766d3571 4540 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4541 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4542 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4543 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4544 r = 0;
4545 break;
6fbbde9a
DS		 4546 case KVM_CAP_MSR_PLATFORM_INFO:
4547 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4548 r = 0;
c4f55198
JM		 4549 break;
4550 case KVM_CAP_EXCEPTION_PAYLOAD:
4551 kvm->arch.exception_payload_enabled = cap->args[0];
4552 r = 0;
6fbbde9a 4553 break;
90de4a18
NA		 4554 default:
4555 r = -EINVAL;
4556 break;
4557 }
4558 return r;
4559}
4560
1fe779f8
CO		 4561long kvm_arch_vm_ioctl(struct file *filp,
4562 unsigned int ioctl, unsigned long arg)
4563{
4564 struct kvm *kvm = filp->private_data;
4565 void __user *argp = (void __user *)arg;
367e1319 4566 int r = -ENOTTY;
f0d66275
DH		 4567 /*
4568 * This union makes it completely explicit to gcc-3.x
4569 * that these two variables' stack usage should be
4570 * combined, not added together.
4571 */
4572 union {
4573 struct kvm_pit_state ps;
e9f42757 4574 struct kvm_pit_state2 ps2;
c5ff41ce 4575 struct kvm_pit_config pit_config;
f0d66275 4576 } u;
1fe779f8
CO		 4577
4578 switch (ioctl) {
4579 case KVM_SET_TSS_ADDR:
4580 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4581 break;
b927a3ce
SY		 4582 case KVM_SET_IDENTITY_MAP_ADDR: {
4583 u64 ident_addr;
4584
1af1ac91
DH		 4585 mutex_lock(&kvm->lock);
4586 r = -EINVAL;
4587 if (kvm->created_vcpus)
4588 goto set_identity_unlock;
b927a3ce 4589 r = -EFAULT;
0e96f31e 4590 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4591 goto set_identity_unlock;
b927a3ce 4592 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4593set_identity_unlock:
4594 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4595 break;
4596 }
1fe779f8
CO		 4597 case KVM_SET_NR_MMU_PAGES:
4598 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4599 break;
4600 case KVM_GET_NR_MMU_PAGES:
4601 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4602 break;
3ddea128 4603 case KVM_CREATE_IRQCHIP: {
3ddea128 4604 mutex_lock(&kvm->lock);
09941366 4605
3ddea128 4606 r = -EEXIST;
35e6eaa3 4607 if (irqchip_in_kernel(kvm))
3ddea128 4608 goto create_irqchip_unlock;
09941366 4609
3e515705 4610 r = -EINVAL;
557abc40 4611 if (kvm->created_vcpus)
3e515705 4612 goto create_irqchip_unlock;
09941366
RK		 4613
4614 r = kvm_pic_init(kvm);
4615 if (r)
3ddea128 4616 goto create_irqchip_unlock;
09941366
RK		 4617
4618 r = kvm_ioapic_init(kvm);
4619 if (r) {
09941366 4620 kvm_pic_destroy(kvm);
3ddea128 4621 goto create_irqchip_unlock;
09941366
RK		 4622 }
4623
399ec807
AK		 4624 r = kvm_setup_default_irq_routing(kvm);
4625 if (r) {
72bb2fcd 4626 kvm_ioapic_destroy(kvm);
09941366 4627 kvm_pic_destroy(kvm);
71ba994c 4628 goto create_irqchip_unlock;
399ec807 4629 }
49776faf 4630 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4631 smp_wmb();
49776faf 4632 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4633 create_irqchip_unlock:
4634 mutex_unlock(&kvm->lock);
1fe779f8 4635 break;
3ddea128 4636 }
7837699f 4637 case KVM_CREATE_PIT:
c5ff41ce
JK		 4638 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4639 goto create_pit;
4640 case KVM_CREATE_PIT2:
4641 r = -EFAULT;
4642 if (copy_from_user(&u.pit_config, argp,
4643 sizeof(struct kvm_pit_config)))
4644 goto out;
4645 create_pit:
250715a6 4646 mutex_lock(&kvm->lock);
269e05e4
AK		 4647 r = -EEXIST;
4648 if (kvm->arch.vpit)
4649 goto create_pit_unlock;
7837699f 4650 r = -ENOMEM;
c5ff41ce 4651 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4652 if (kvm->arch.vpit)
4653 r = 0;
269e05e4 4654 create_pit_unlock:
250715a6 4655 mutex_unlock(&kvm->lock);
7837699f 4656 break;
1fe779f8
CO		 4657 case KVM_GET_IRQCHIP: {
4658 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4659 struct kvm_irqchip *chip;
1fe779f8 4660
ff5c2c03
SL		 4661 chip = memdup_user(argp, sizeof(*chip));
4662 if (IS_ERR(chip)) {
4663 r = PTR_ERR(chip);
1fe779f8 4664 goto out;
ff5c2c03
SL		 4665 }
4666
1fe779f8 4667 r = -ENXIO;
826da321 4668 if (!irqchip_kernel(kvm))
f0d66275
DH		 4669 goto get_irqchip_out;
4670 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4671 if (r)
f0d66275 4672 goto get_irqchip_out;
1fe779f8 4673 r = -EFAULT;
0e96f31e 4674 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4675 goto get_irqchip_out;
1fe779f8 4676 r = 0;
f0d66275
DH		 4677 get_irqchip_out:
4678 kfree(chip);
1fe779f8
CO		 4679 break;
4680 }
4681 case KVM_SET_IRQCHIP: {
4682 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4683 struct kvm_irqchip *chip;
1fe779f8 4684
ff5c2c03
SL		 4685 chip = memdup_user(argp, sizeof(*chip));
4686 if (IS_ERR(chip)) {
4687 r = PTR_ERR(chip);
1fe779f8 4688 goto out;
ff5c2c03
SL		 4689 }
4690
1fe779f8 4691 r = -ENXIO;
826da321 4692 if (!irqchip_kernel(kvm))
f0d66275
DH		 4693 goto set_irqchip_out;
4694 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4695 if (r)
f0d66275 4696 goto set_irqchip_out;
1fe779f8 4697 r = 0;
f0d66275
DH		 4698 set_irqchip_out:
4699 kfree(chip);
1fe779f8
CO		 4700 break;
4701 }
e0f63cb9 4702 case KVM_GET_PIT: {
e0f63cb9 4703 r = -EFAULT;
f0d66275 4704 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4705 goto out;
4706 r = -ENXIO;
4707 if (!kvm->arch.vpit)
4708 goto out;
f0d66275 4709 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4710 if (r)
4711 goto out;
4712 r = -EFAULT;
f0d66275 4713 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4714 goto out;
4715 r = 0;
4716 break;
4717 }
4718 case KVM_SET_PIT: {
e0f63cb9 4719 r = -EFAULT;
0e96f31e 4720 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4721 goto out;
4722 r = -ENXIO;
4723 if (!kvm->arch.vpit)
4724 goto out;
f0d66275 4725 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4726 break;
4727 }
e9f42757
BK		 4728 case KVM_GET_PIT2: {
4729 r = -ENXIO;
4730 if (!kvm->arch.vpit)
4731 goto out;
4732 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4733 if (r)
4734 goto out;
4735 r = -EFAULT;
4736 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4737 goto out;
4738 r = 0;
4739 break;
4740 }
4741 case KVM_SET_PIT2: {
4742 r = -EFAULT;
4743 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4744 goto out;
4745 r = -ENXIO;
4746 if (!kvm->arch.vpit)
4747 goto out;
4748 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4749 break;
4750 }
52d939a0
MT		 4751 case KVM_REINJECT_CONTROL: {
4752 struct kvm_reinject_control control;
4753 r = -EFAULT;
4754 if (copy_from_user(&control, argp, sizeof(control)))
4755 goto out;
4756 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4757 break;
4758 }
d71ba788
PB		 4759 case KVM_SET_BOOT_CPU_ID:
4760 r = 0;
4761 mutex_lock(&kvm->lock);
557abc40 4762 if (kvm->created_vcpus)
d71ba788
PB		 4763 r = -EBUSY;
4764 else
4765 kvm->arch.bsp_vcpu_id = arg;
4766 mutex_unlock(&kvm->lock);
4767 break;
ffde22ac 4768 case KVM_XEN_HVM_CONFIG: {
51776043 4769 struct kvm_xen_hvm_config xhc;
ffde22ac 4770 r = -EFAULT;
51776043 4771 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4772 goto out;
4773 r = -EINVAL;
51776043 4774 if (xhc.flags)
ffde22ac 4775 goto out;
51776043 4776 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4777 r = 0;
4778 break;
4779 }
afbcf7ab 4780 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4781 struct kvm_clock_data user_ns;
4782 u64 now_ns;
afbcf7ab
GC		 4783
4784 r = -EFAULT;
4785 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4786 goto out;
4787
4788 r = -EINVAL;
4789 if (user_ns.flags)
4790 goto out;
4791
4792 r = 0;
0bc48bea
RK		 4793 /*
4794 * TODO: userspace has to take care of races with VCPU_RUN, so
4795 * kvm_gen_update_masterclock() can be cut down to locked
4796 * pvclock_update_vm_gtod_copy().
4797 */
4798 kvm_gen_update_masterclock(kvm);
e891a32e 4799 now_ns = get_kvmclock_ns(kvm);
108b249c 4800 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4801 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4802 break;
4803 }
4804 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4805 struct kvm_clock_data user_ns;
4806 u64 now_ns;
4807
e891a32e 4808 now_ns = get_kvmclock_ns(kvm);
108b249c 4809 user_ns.clock = now_ns;
e3fd9a93 4810 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4811 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4812
4813 r = -EFAULT;
4814 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4815 goto out;
4816 r = 0;
4817 break;
4818 }
5acc5c06
BS		 4819 case KVM_MEMORY_ENCRYPT_OP: {
4820 r = -ENOTTY;
4821 if (kvm_x86_ops->mem_enc_op)
4822 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4823 break;
4824 }
69eaedee
BS		 4825 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4826 struct kvm_enc_region region;
4827
4828 r = -EFAULT;
4829 if (copy_from_user(&region, argp, sizeof(region)))
4830 goto out;
4831
4832 r = -ENOTTY;
4833 if (kvm_x86_ops->mem_enc_reg_region)
4834 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4835 break;
4836 }
4837 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4838 struct kvm_enc_region region;
4839
4840 r = -EFAULT;
4841 if (copy_from_user(&region, argp, sizeof(region)))
4842 goto out;
4843
4844 r = -ENOTTY;
4845 if (kvm_x86_ops->mem_enc_unreg_region)
4846 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4847 break;
4848 }
faeb7833
RK		 4849 case KVM_HYPERV_EVENTFD: {
4850 struct kvm_hyperv_eventfd hvevfd;
4851
4852 r = -EFAULT;
4853 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4854 goto out;
4855 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4856 break;
4857 }
1fe779f8 4858 default:
ad6260da 4859 r = -ENOTTY;
1fe779f8
CO		 4860 }
4861out:
4862 return r;
4863}
4864
a16b043c 4865static void kvm_init_msr_list(void)
043405e1
CO		 4866{
4867 u32 dummy[2];
4868 unsigned i, j;
4869
62ef68bb 4870 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4871 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4872 continue;
93c4adc7
PB		 4873
4874 /*
4875 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4876 * to the guests in some cases.
93c4adc7
PB		 4877 */
4878 switch (msrs_to_save[i]) {
4879 case MSR_IA32_BNDCFGS:
503234b3 4880 if (!kvm_mpx_supported())
93c4adc7
PB		 4881 continue;
4882 break;
9dbe6cf9
PB		 4883 case MSR_TSC_AUX:
4884 if (!kvm_x86_ops->rdtscp_supported())
4885 continue;
4886 break;
93c4adc7
PB		 4887 default:
4888 break;
4889 }
4890
043405e1
CO		 4891 if (j < i)
4892 msrs_to_save[j] = msrs_to_save[i];
4893 j++;
4894 }
4895 num_msrs_to_save = j;
62ef68bb
PB		 4896
4897 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4898 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4899 continue;
62ef68bb
PB		 4900
4901 if (j < i)
4902 emulated_msrs[j] = emulated_msrs[i];
4903 j++;
4904 }
4905 num_emulated_msrs = j;
801e459a
TL		 4906
4907 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4908 struct kvm_msr_entry msr;
4909
4910 msr.index = msr_based_features[i];
66421c1e 4911 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4912 continue;
4913
4914 if (j < i)
4915 msr_based_features[j] = msr_based_features[i];
4916 j++;
4917 }
4918 num_msr_based_features = j;
043405e1
CO		 4919}
4920
bda9020e
MT		 4921static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4922 const void *v)
bbd9b64e 4923{
70252a10
AK		 4924 int handled = 0;
4925 int n;
4926
4927 do {
4928 n = min(len, 8);
bce87cce 4929 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4930 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4931 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4932 break;
4933 handled += n;
4934 addr += n;
4935 len -= n;
4936 v += n;
4937 } while (len);
bbd9b64e 4938
70252a10 4939 return handled;
bbd9b64e
CO		 4940}
4941
bda9020e 4942static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4943{
70252a10
AK		 4944 int handled = 0;
4945 int n;
4946
4947 do {
4948 n = min(len, 8);
bce87cce 4949 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4950 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4951 addr, n, v))
4952 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4953 break;
e39d200f 4954 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4955 handled += n;
4956 addr += n;
4957 len -= n;
4958 v += n;
4959 } while (len);
bbd9b64e 4960
70252a10 4961 return handled;
bbd9b64e
CO		 4962}
4963
2dafc6c2
GN		 4964static void kvm_set_segment(struct kvm_vcpu *vcpu,
4965 struct kvm_segment *var, int seg)
4966{
4967 kvm_x86_ops->set_segment(vcpu, var, seg);
4968}
4969
4970void kvm_get_segment(struct kvm_vcpu *vcpu,
4971 struct kvm_segment *var, int seg)
4972{
4973 kvm_x86_ops->get_segment(vcpu, var, seg);
4974}
4975
54987b7a
PB		 4976gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4977 struct x86_exception *exception)
02f59dc9
JR		 4978{
4979 gpa_t t_gpa;
02f59dc9
JR		 4980
4981 BUG_ON(!mmu_is_nested(vcpu));
4982
4983 /* NPT walks are always user-walks */
4984 access |= PFERR_USER_MASK;
44dd3ffa 4985 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4986
4987 return t_gpa;
4988}
4989
ab9ae313
AK		 4990gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4991 struct x86_exception *exception)
1871c602
GN		 4992{
4993 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4994 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4995}
4996
ab9ae313
AK		 4997 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4998 struct x86_exception *exception)
1871c602
GN		 4999{
5000 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5001 access |= PFERR_FETCH_MASK;
ab9ae313 5002 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5003}
5004
ab9ae313
AK		 5005gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5006 struct x86_exception *exception)
1871c602
GN		 5007{
5008 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5009 access |= PFERR_WRITE_MASK;
ab9ae313 5010 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5011}
5012
5013/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5014gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5015 struct x86_exception *exception)
1871c602 5016{
ab9ae313 5017 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5018}
5019
5020static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5021 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5022 struct x86_exception *exception)
bbd9b64e
CO		 5023{
5024 void *data = val;
10589a46 5025 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5026
5027 while (bytes) {
14dfe855 5028 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5029 exception);
bbd9b64e 5030 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5031 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5032 int ret;
5033
bcc55cba 5034 if (gpa == UNMAPPED_GVA)
ab9ae313 5035 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5036 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5037 offset, toread);
10589a46 5038 if (ret < 0) {
c3cd7ffa 5039 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5040 goto out;
5041 }
bbd9b64e 5042
77c2002e
IE		 5043 bytes -= toread;
5044 data += toread;
5045 addr += toread;
bbd9b64e 5046 }
10589a46 5047out:
10589a46 5048 return r;
bbd9b64e 5049}
77c2002e 5050
1871c602 5051/* used for instruction fetching */
0f65dd70
AK		 5052static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5053 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5054 struct x86_exception *exception)
1871c602 5055{
0f65dd70 5056 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5057 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5058 unsigned offset;
5059 int ret;
0f65dd70 5060
44583cba
PB		 5061 /* Inline kvm_read_guest_virt_helper for speed. */
5062 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5063 exception);
5064 if (unlikely(gpa == UNMAPPED_GVA))
5065 return X86EMUL_PROPAGATE_FAULT;
5066
5067 offset = addr & (PAGE_SIZE-1);
5068 if (WARN_ON(offset + bytes > PAGE_SIZE))
5069 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5070 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5071 offset, bytes);
44583cba
PB		 5072 if (unlikely(ret < 0))
5073 return X86EMUL_IO_NEEDED;
5074
5075 return X86EMUL_CONTINUE;
1871c602
GN		 5076}
5077
ce14e868 5078int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5079 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5080 struct x86_exception *exception)
1871c602
GN		 5081{
5082 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5083
1871c602 5084 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5085 exception);
1871c602 5086}
064aea77 5087EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5088
ce14e868
PB		 5089static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5090 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5091 struct x86_exception *exception, bool system)
1871c602 5092{
0f65dd70 5093 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5094 u32 access = 0;
5095
5096 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5097 access |= PFERR_USER_MASK;
5098
5099 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5100}
5101
7a036a6f
RK		 5102static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5103 unsigned long addr, void *val, unsigned int bytes)
5104{
5105 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5106 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5107
5108 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5109}
5110
ce14e868
PB		 5111static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5112 struct kvm_vcpu *vcpu, u32 access,
5113 struct x86_exception *exception)
77c2002e
IE		 5114{
5115 void *data = val;
5116 int r = X86EMUL_CONTINUE;
5117
5118 while (bytes) {
14dfe855 5119 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5120 access,
ab9ae313 5121 exception);
77c2002e
IE		 5122 unsigned offset = addr & (PAGE_SIZE-1);
5123 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5124 int ret;
5125
bcc55cba 5126 if (gpa == UNMAPPED_GVA)
ab9ae313 5127 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5128 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5129 if (ret < 0) {
c3cd7ffa 5130 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5131 goto out;
5132 }
5133
5134 bytes -= towrite;
5135 data += towrite;
5136 addr += towrite;
5137 }
5138out:
5139 return r;
5140}
ce14e868
PB		 5141
5142static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5143 unsigned int bytes, struct x86_exception *exception,
5144 bool system)
ce14e868
PB		 5145{
5146 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5147 u32 access = PFERR_WRITE_MASK;
5148
5149 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5150 access |= PFERR_USER_MASK;
ce14e868
PB		 5151
5152 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5153 access, exception);
ce14e868
PB		 5154}
5155
5156int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5157 unsigned int bytes, struct x86_exception *exception)
5158{
c595ceee
PB		 5159 /* kvm_write_guest_virt_system can pull in tons of pages. */
5160 vcpu->arch.l1tf_flush_l1d = true;
5161
ce14e868
PB		 5162 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5163 PFERR_WRITE_MASK, exception);
5164}
6a4d7550 5165EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5166
082d06ed
WL		 5167int handle_ud(struct kvm_vcpu *vcpu)
5168{
6c86eedc 5169 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5170 enum emulation_result er;
6c86eedc
WL		 5171 char sig[5]; /* ud2; .ascii "kvm" */
5172 struct x86_exception e;
5173
5174 if (force_emulation_prefix &&
3c9fa24c
PB		 5175 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5176 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5177 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5178 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5179 emul_type = 0;
5180 }
082d06ed 5181
0ce97a2b 5182 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5183 if (er == EMULATE_USER_EXIT)
5184 return 0;
5185 if (er != EMULATE_DONE)
5186 kvm_queue_exception(vcpu, UD_VECTOR);
5187 return 1;
5188}
5189EXPORT_SYMBOL_GPL(handle_ud);
5190
0f89b207
TL		 5191static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5192 gpa_t gpa, bool write)
5193{
5194 /* For APIC access vmexit */
5195 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5196 return 1;
5197
5198 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5199 trace_vcpu_match_mmio(gva, gpa, write, true);
5200 return 1;
5201 }
5202
5203 return 0;
5204}
5205
af7cc7d1
XG		 5206static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5207 gpa_t *gpa, struct x86_exception *exception,
5208 bool write)
5209{
97d64b78
AK		 5210 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5211 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5212
be94f6b7
HH		 5213 /*
5214 * currently PKRU is only applied to ept enabled guest so
5215 * there is no pkey in EPT page table for L1 guest or EPT
5216 * shadow page table for L2 guest.
5217 */
97d64b78 5218 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5219 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5220 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5221 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5222 (gva & (PAGE_SIZE - 1));
4f022648 5223 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5224 return 1;
5225 }
5226
af7cc7d1
XG		 5227 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5228
5229 if (*gpa == UNMAPPED_GVA)
5230 return -1;
5231
0f89b207 5232 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5233}
5234
3200f405 5235int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5236 const void *val, int bytes)
bbd9b64e
CO		 5237{
5238 int ret;
5239
54bf36aa 5240 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5241 if (ret < 0)
bbd9b64e 5242 return 0;
0eb05bf2 5243 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5244 return 1;
5245}
5246
77d197b2
XG		 5247struct read_write_emulator_ops {
5248 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5249 int bytes);
5250 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5251 void *val, int bytes);
5252 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5253 int bytes, void *val);
5254 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5255 void *val, int bytes);
5256 bool write;
5257};
5258
5259static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5260{
5261 if (vcpu->mmio_read_completed) {
77d197b2 5262 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5263 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5264 vcpu->mmio_read_completed = 0;
5265 return 1;
5266 }
5267
5268 return 0;
5269}
5270
5271static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5272 void *val, int bytes)
5273{
54bf36aa 5274 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5275}
5276
5277static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5278 void *val, int bytes)
5279{
5280 return emulator_write_phys(vcpu, gpa, val, bytes);
5281}
5282
5283static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5284{
e39d200f 5285 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5286 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5287}
5288
5289static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5290 void *val, int bytes)
5291{
e39d200f 5292 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5293 return X86EMUL_IO_NEEDED;
5294}
5295
5296static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5297 void *val, int bytes)
5298{
f78146b0
AK		 5299 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5300
87da7e66 5301 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5302 return X86EMUL_CONTINUE;
5303}
5304
0fbe9b0b 5305static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5306 .read_write_prepare = read_prepare,
5307 .read_write_emulate = read_emulate,
5308 .read_write_mmio = vcpu_mmio_read,
5309 .read_write_exit_mmio = read_exit_mmio,
5310};
5311
0fbe9b0b 5312static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5313 .read_write_emulate = write_emulate,
5314 .read_write_mmio = write_mmio,
5315 .read_write_exit_mmio = write_exit_mmio,
5316 .write = true,
5317};
5318
22388a3c
XG		 5319static int emulator_read_write_onepage(unsigned long addr, void *val,
5320 unsigned int bytes,
5321 struct x86_exception *exception,
5322 struct kvm_vcpu *vcpu,
0fbe9b0b 5323 const struct read_write_emulator_ops *ops)
bbd9b64e 5324{
af7cc7d1
XG		 5325 gpa_t gpa;
5326 int handled, ret;
22388a3c 5327 bool write = ops->write;
f78146b0 5328 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5329 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5330
5331 /*
5332 * If the exit was due to a NPF we may already have a GPA.
5333 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5334 * Note, this cannot be used on string operations since string
5335 * operation using rep will only have the initial GPA from the NPF
5336 * occurred.
5337 */
5338 if (vcpu->arch.gpa_available &&
5339 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5340 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5341 gpa = vcpu->arch.gpa_val;
5342 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5343 } else {
5344 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5345 if (ret < 0)
5346 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5347 }
10589a46 5348
618232e2 5349 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5350 return X86EMUL_CONTINUE;
5351
bbd9b64e
CO		 5352 /*
5353 * Is this MMIO handled locally?
5354 */
22388a3c 5355 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5356 if (handled == bytes)
bbd9b64e 5357 return X86EMUL_CONTINUE;
bbd9b64e 5358
70252a10
AK		 5359 gpa += handled;
5360 bytes -= handled;
5361 val += handled;
5362
87da7e66
XG		 5363 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5364 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5365 frag->gpa = gpa;
5366 frag->data = val;
5367 frag->len = bytes;
f78146b0 5368 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5369}
5370
52eb5a6d
XL		 5371static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5372 unsigned long addr,
22388a3c
XG		 5373 void *val, unsigned int bytes,
5374 struct x86_exception *exception,
0fbe9b0b 5375 const struct read_write_emulator_ops *ops)
bbd9b64e 5376{
0f65dd70 5377 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5378 gpa_t gpa;
5379 int rc;
5380
5381 if (ops->read_write_prepare &&
5382 ops->read_write_prepare(vcpu, val, bytes))
5383 return X86EMUL_CONTINUE;
5384
5385 vcpu->mmio_nr_fragments = 0;
0f65dd70 5386
bbd9b64e
CO		 5387 /* Crossing a page boundary? */
5388 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5389 int now;
bbd9b64e
CO		 5390
5391 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5392 rc = emulator_read_write_onepage(addr, val, now, exception,
5393 vcpu, ops);
5394
bbd9b64e
CO		 5395 if (rc != X86EMUL_CONTINUE)
5396 return rc;
5397 addr += now;
bac15531
NA		 5398 if (ctxt->mode != X86EMUL_MODE_PROT64)
5399 addr = (u32)addr;
bbd9b64e
CO		 5400 val += now;
5401 bytes -= now;
5402 }
22388a3c 5403
f78146b0
AK		 5404 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5405 vcpu, ops);
5406 if (rc != X86EMUL_CONTINUE)
5407 return rc;
5408
5409 if (!vcpu->mmio_nr_fragments)
5410 return rc;
5411
5412 gpa = vcpu->mmio_fragments[0].gpa;
5413
5414 vcpu->mmio_needed = 1;
5415 vcpu->mmio_cur_fragment = 0;
5416
87da7e66 5417 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5418 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5419 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5420 vcpu->run->mmio.phys_addr = gpa;
5421
5422 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5423}
5424
5425static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5426 unsigned long addr,
5427 void *val,
5428 unsigned int bytes,
5429 struct x86_exception *exception)
5430{
5431 return emulator_read_write(ctxt, addr, val, bytes,
5432 exception, &read_emultor);
5433}
5434
52eb5a6d 5435static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5436 unsigned long addr,
5437 const void *val,
5438 unsigned int bytes,
5439 struct x86_exception *exception)
5440{
5441 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5442 exception, &write_emultor);
bbd9b64e 5443}
bbd9b64e 5444
daea3e73
AK		 5445#define CMPXCHG_TYPE(t, ptr, old, new) \
5446 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5447
5448#ifdef CONFIG_X86_64
5449# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5450#else
5451# define CMPXCHG64(ptr, old, new) \
9749a6c0 5452 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5453#endif
5454
0f65dd70
AK		 5455static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5456 unsigned long addr,
bbd9b64e
CO		 5457 const void *old,
5458 const void *new,
5459 unsigned int bytes,
0f65dd70 5460 struct x86_exception *exception)
bbd9b64e 5461{
0f65dd70 5462 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5463 gpa_t gpa;
5464 struct page *page;
5465 char *kaddr;
5466 bool exchanged;
2bacc55c 5467
daea3e73
AK		 5468 /* guests cmpxchg8b have to be emulated atomically */
5469 if (bytes > 8 || (bytes & (bytes - 1)))
5470 goto emul_write;
10589a46 5471
daea3e73 5472 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5473
daea3e73
AK		 5474 if (gpa == UNMAPPED_GVA ||
5475 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5476 goto emul_write;
2bacc55c 5477
daea3e73
AK		 5478 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5479 goto emul_write;
72dc67a6 5480
54bf36aa 5481 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5482 if (is_error_page(page))
c19b8bd6 5483 goto emul_write;
72dc67a6 5484
8fd75e12 5485 kaddr = kmap_atomic(page);
daea3e73
AK		 5486 kaddr += offset_in_page(gpa);
5487 switch (bytes) {
5488 case 1:
5489 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5490 break;
5491 case 2:
5492 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5493 break;
5494 case 4:
5495 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5496 break;
5497 case 8:
5498 exchanged = CMPXCHG64(kaddr, old, new);
5499 break;
5500 default:
5501 BUG();
2bacc55c 5502 }
8fd75e12 5503 kunmap_atomic(kaddr);
daea3e73
AK		 5504 kvm_release_page_dirty(page);
5505
5506 if (!exchanged)
5507 return X86EMUL_CMPXCHG_FAILED;
5508
54bf36aa 5509 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5510 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5511
5512 return X86EMUL_CONTINUE;
4a5f48f6 5513
3200f405 5514emul_write:
daea3e73 5515 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5516
0f65dd70 5517 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5518}
5519
cf8f70bf
GN		 5520static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5521{
cbfc6c91 5522 int r = 0, i;
cf8f70bf 5523
cbfc6c91
WL		 5524 for (i = 0; i < vcpu->arch.pio.count; i++) {
5525 if (vcpu->arch.pio.in)
5526 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5527 vcpu->arch.pio.size, pd);
5528 else
5529 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5530 vcpu->arch.pio.port, vcpu->arch.pio.size,
5531 pd);
5532 if (r)
5533 break;
5534 pd += vcpu->arch.pio.size;
5535 }
cf8f70bf
GN		 5536 return r;
5537}
5538
6f6fbe98
XG		 5539static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5540 unsigned short port, void *val,
5541 unsigned int count, bool in)
cf8f70bf 5542{
cf8f70bf 5543 vcpu->arch.pio.port = port;
6f6fbe98 5544 vcpu->arch.pio.in = in;
7972995b 5545 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5546 vcpu->arch.pio.size = size;
5547
5548 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5549 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5550 return 1;
5551 }
5552
5553 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5554 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5555 vcpu->run->io.size = size;
5556 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5557 vcpu->run->io.count = count;
5558 vcpu->run->io.port = port;
5559
5560 return 0;
5561}
5562
6f6fbe98
XG		 5563static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5564 int size, unsigned short port, void *val,
5565 unsigned int count)
cf8f70bf 5566{
ca1d4a9e 5567 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5568 int ret;
ca1d4a9e 5569
6f6fbe98
XG		 5570 if (vcpu->arch.pio.count)
5571 goto data_avail;
cf8f70bf 5572
cbfc6c91
WL		 5573 memset(vcpu->arch.pio_data, 0, size * count);
5574
6f6fbe98
XG		 5575 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5576 if (ret) {
5577data_avail:
5578 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5579 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5580 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5581 return 1;
5582 }
5583
cf8f70bf
GN		 5584 return 0;
5585}
5586
6f6fbe98
XG		 5587static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5588 int size, unsigned short port,
5589 const void *val, unsigned int count)
5590{
5591 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5592
5593 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5594 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5595 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5596}
5597
bbd9b64e
CO		 5598static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5599{
5600 return kvm_x86_ops->get_segment_base(vcpu, seg);
5601}
5602
3cb16fe7 5603static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5604{
3cb16fe7 5605 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5606}
5607
ae6a2375 5608static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5609{
5610 if (!need_emulate_wbinvd(vcpu))
5611 return X86EMUL_CONTINUE;
5612
5613 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5614 int cpu = get_cpu();
5615
5616 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5617 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5618 wbinvd_ipi, NULL, 1);
2eec7343 5619 put_cpu();
f5f48ee1 5620 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5621 } else
5622 wbinvd();
f5f48ee1
SY		 5623 return X86EMUL_CONTINUE;
5624}
5cb56059
JS		 5625
5626int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5627{
6affcbed
KH		 5628 kvm_emulate_wbinvd_noskip(vcpu);
5629 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5630}
f5f48ee1
SY		 5631EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5632
5cb56059
JS		 5633
5634
bcaf5cc5
AK		 5635static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5636{
5cb56059 5637 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5638}
5639
52eb5a6d
XL		 5640static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5641 unsigned long *dest)
bbd9b64e 5642{
16f8a6f9 5643 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5644}
5645
52eb5a6d
XL		 5646static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5647 unsigned long value)
bbd9b64e 5648{
338dbc97 5649
717746e3 5650 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5651}
5652
52a46617 5653static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5654{
52a46617 5655 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5656}
5657
717746e3 5658static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5659{
717746e3 5660 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5661 unsigned long value;
5662
5663 switch (cr) {
5664 case 0:
5665 value = kvm_read_cr0(vcpu);
5666 break;
5667 case 2:
5668 value = vcpu->arch.cr2;
5669 break;
5670 case 3:
9f8fe504 5671 value = kvm_read_cr3(vcpu);
52a46617
GN		 5672 break;
5673 case 4:
5674 value = kvm_read_cr4(vcpu);
5675 break;
5676 case 8:
5677 value = kvm_get_cr8(vcpu);
5678 break;
5679 default:
a737f256 5680 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5681 return 0;
5682 }
5683
5684 return value;
5685}
5686
717746e3 5687static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5688{
717746e3 5689 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5690 int res = 0;
5691
52a46617
GN		 5692 switch (cr) {
5693 case 0:
49a9b07e 5694 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5695 break;
5696 case 2:
5697 vcpu->arch.cr2 = val;
5698 break;
5699 case 3:
2390218b 5700 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5701 break;
5702 case 4:
a83b29c6 5703 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5704 break;
5705 case 8:
eea1cff9 5706 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5707 break;
5708 default:
a737f256 5709 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5710 res = -1;
52a46617 5711 }
0f12244f
GN		 5712
5713 return res;
52a46617
GN		 5714}
5715
717746e3 5716static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5717{
717746e3 5718 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5719}
5720
4bff1e86 5721static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5722{
4bff1e86 5723 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5724}
5725
4bff1e86 5726static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5727{
4bff1e86 5728 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5729}
5730
1ac9d0cf
AK		 5731static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5732{
5733 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5734}
5735
5736static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5737{
5738 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5739}
5740
4bff1e86
AK		 5741static unsigned long emulator_get_cached_segment_base(
5742 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5743{
4bff1e86 5744 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5745}
5746
1aa36616
AK		 5747static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5748 struct desc_struct *desc, u32 *base3,
5749 int seg)
2dafc6c2
GN		 5750{
5751 struct kvm_segment var;
5752
4bff1e86 5753 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5754 *selector = var.selector;
2dafc6c2 5755
378a8b09
GN		 5756 if (var.unusable) {
5757 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5758 if (base3)
5759 *base3 = 0;
2dafc6c2 5760 return false;
378a8b09 5761 }
2dafc6c2
GN		 5762
5763 if (var.g)
5764 var.limit >>= 12;
5765 set_desc_limit(desc, var.limit);
5766 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5767#ifdef CONFIG_X86_64
5768 if (base3)
5769 *base3 = var.base >> 32;
5770#endif
2dafc6c2
GN		 5771 desc->type = var.type;
5772 desc->s = var.s;
5773 desc->dpl = var.dpl;
5774 desc->p = var.present;
5775 desc->avl = var.avl;
5776 desc->l = var.l;
5777 desc->d = var.db;
5778 desc->g = var.g;
5779
5780 return true;
5781}
5782
1aa36616
AK		 5783static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5784 struct desc_struct *desc, u32 base3,
5785 int seg)
2dafc6c2 5786{
4bff1e86 5787 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5788 struct kvm_segment var;
5789
1aa36616 5790 var.selector = selector;
2dafc6c2 5791 var.base = get_desc_base(desc);
5601d05b
GN		 5792#ifdef CONFIG_X86_64
5793 var.base |= ((u64)base3) << 32;
5794#endif
2dafc6c2
GN		 5795 var.limit = get_desc_limit(desc);
5796 if (desc->g)
5797 var.limit = (var.limit << 12) | 0xfff;
5798 var.type = desc->type;
2dafc6c2
GN		 5799 var.dpl = desc->dpl;
5800 var.db = desc->d;
5801 var.s = desc->s;
5802 var.l = desc->l;
5803 var.g = desc->g;
5804 var.avl = desc->avl;
5805 var.present = desc->p;
5806 var.unusable = !var.present;
5807 var.padding = 0;
5808
5809 kvm_set_segment(vcpu, &var, seg);
5810 return;
5811}
5812
717746e3
AK		 5813static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5814 u32 msr_index, u64 *pdata)
5815{
609e36d3
PB		 5816 struct msr_data msr;
5817 int r;
5818
5819 msr.index = msr_index;
5820 msr.host_initiated = false;
5821 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5822 if (r)
5823 return r;
5824
5825 *pdata = msr.data;
5826 return 0;
717746e3
AK		 5827}
5828
5829static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5830 u32 msr_index, u64 data)
5831{
8fe8ab46
WA		 5832 struct msr_data msr;
5833
5834 msr.data = data;
5835 msr.index = msr_index;
5836 msr.host_initiated = false;
5837 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5838}
5839
64d60670
PB		 5840static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5841{
5842 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5843
5844 return vcpu->arch.smbase;
5845}
5846
5847static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5848{
5849 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5850
5851 vcpu->arch.smbase = smbase;
5852}
5853
67f4d428
NA		 5854static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5855 u32 pmc)
5856{
c6702c9d 5857 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5858}
5859
222d21aa
AK		 5860static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5861 u32 pmc, u64 *pdata)
5862{
c6702c9d 5863 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5864}
5865
6c3287f7
AK		 5866static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5867{
5868 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5869}
5870
2953538e 5871static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5872 struct x86_instruction_info *info,
c4f035c6
AK		 5873 enum x86_intercept_stage stage)
5874{
2953538e 5875 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5876}
5877
e911eb3b
YZ		 5878static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5879 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5880{
e911eb3b 5881 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5882}
5883
dd856efa
AK		 5884static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5885{
5886 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5887}
5888
5889static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5890{
5891 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5892}
5893
801806d9
NA		 5894static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5895{
5896 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5897}
5898
6ed071f0
LP		 5899static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5900{
5901 return emul_to_vcpu(ctxt)->arch.hflags;
5902}
5903
5904static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5905{
5906 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5907}
5908
0234bf88
LP		 5909static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5910{
5911 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5912}
5913
0225fb50 5914static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5915 .read_gpr = emulator_read_gpr,
5916 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5917 .read_std = emulator_read_std,
5918 .write_std = emulator_write_std,
7a036a6f 5919 .read_phys = kvm_read_guest_phys_system,
1871c602 5920 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5921 .read_emulated = emulator_read_emulated,
5922 .write_emulated = emulator_write_emulated,
5923 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5924 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5925 .pio_in_emulated = emulator_pio_in_emulated,
5926 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5927 .get_segment = emulator_get_segment,
5928 .set_segment = emulator_set_segment,
5951c442 5929 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5930 .get_gdt = emulator_get_gdt,
160ce1f1 5931 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5932 .set_gdt = emulator_set_gdt,
5933 .set_idt = emulator_set_idt,
52a46617
GN		 5934 .get_cr = emulator_get_cr,
5935 .set_cr = emulator_set_cr,
9c537244 5936 .cpl = emulator_get_cpl,
35aa5375
GN		 5937 .get_dr = emulator_get_dr,
5938 .set_dr = emulator_set_dr,
64d60670
PB		 5939 .get_smbase = emulator_get_smbase,
5940 .set_smbase = emulator_set_smbase,
717746e3
AK		 5941 .set_msr = emulator_set_msr,
5942 .get_msr = emulator_get_msr,
67f4d428 5943 .check_pmc = emulator_check_pmc,
222d21aa 5944 .read_pmc = emulator_read_pmc,
6c3287f7 5945 .halt = emulator_halt,
bcaf5cc5 5946 .wbinvd = emulator_wbinvd,
d6aa1000 5947 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5948 .intercept = emulator_intercept,
bdb42f5a 5949 .get_cpuid = emulator_get_cpuid,
801806d9 5950 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5951 .get_hflags = emulator_get_hflags,
5952 .set_hflags = emulator_set_hflags,
0234bf88 5953 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5954};
5955
95cb2295
GN		 5956static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5957{
37ccdcbe 5958 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5959 /*
5960 * an sti; sti; sequence only disable interrupts for the first
5961 * instruction. So, if the last instruction, be it emulated or
5962 * not, left the system with the INT_STI flag enabled, it
5963 * means that the last instruction is an sti. We should not
5964 * leave the flag on in this case. The same goes for mov ss
5965 */
37ccdcbe
PB		 5966 if (int_shadow & mask)
5967 mask = 0;
6addfc42 5968 if (unlikely(int_shadow || mask)) {
95cb2295 5969 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5970 if (!mask)
5971 kvm_make_request(KVM_REQ_EVENT, vcpu);
5972 }
95cb2295
GN		 5973}
5974
ef54bcfe 5975static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5976{
5977 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5978 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5979 return kvm_propagate_fault(vcpu, &ctxt->exception);
5980
5981 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5982 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5983 ctxt->exception.error_code);
54b8486f 5984 else
da9cb575 5985 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5986 return false;
54b8486f
GN		 5987}
5988
8ec4722d
MG		 5989static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5990{
adf52235 5991 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5992 int cs_db, cs_l;
5993
8ec4722d
MG		 5994 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5995
adf52235 5996 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5997 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5998
adf52235
TY		 5999 ctxt->eip = kvm_rip_read(vcpu);
6000 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6001 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6002 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6003 cs_db ? X86EMUL_MODE_PROT32 :
6004 X86EMUL_MODE_PROT16;
a584539b 6005 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6006 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6007 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6008
dd856efa 6009 init_decode_cache(ctxt);
7ae441ea 6010 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6011}
6012
71f9833b 6013int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6014{
9d74191a 6015 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6016 int ret;
6017
6018 init_emulate_ctxt(vcpu);
6019
9dac77fa
AK		 6020 ctxt->op_bytes = 2;
6021 ctxt->ad_bytes = 2;
6022 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6023 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6024
6025 if (ret != X86EMUL_CONTINUE)
6026 return EMULATE_FAIL;
6027
9dac77fa 6028 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6029 kvm_rip_write(vcpu, ctxt->eip);
6030 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6031
63995653
MG		 6032 return EMULATE_DONE;
6033}
6034EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6035
e2366171 6036static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6037{
fc3a9157
JR		 6038 int r = EMULATE_DONE;
6039
6d77dbfc
GN		 6040 ++vcpu->stat.insn_emulation_fail;
6041 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6042
6043 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6044 return EMULATE_FAIL;
6045
a2b9e6c1 6046 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6047 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6048 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6049 vcpu->run->internal.ndata = 0;
1f4dcb3b 6050 r = EMULATE_USER_EXIT;
fc3a9157 6051 }
e2366171 6052
6d77dbfc 6053 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6054
6055 return r;
6d77dbfc
GN		 6056}
6057
93c05d3e 6058static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6059 bool write_fault_to_shadow_pgtable,
6060 int emulation_type)
a6f177ef 6061{
95b3cf69 6062 gpa_t gpa = cr2;
ba049e93 6063 kvm_pfn_t pfn;
a6f177ef 6064
384bf221 6065 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6066 return false;
6067
6c3dfeb6
SC		 6068 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6069 return false;
6070
44dd3ffa 6071 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6072 /*
6073 * Write permission should be allowed since only
6074 * write access need to be emulated.
6075 */
6076 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6077
95b3cf69
XG		 6078 /*
6079 * If the mapping is invalid in guest, let cpu retry
6080 * it to generate fault.
6081 */
6082 if (gpa == UNMAPPED_GVA)
6083 return true;
6084 }
a6f177ef 6085
8e3d9d06
XG		 6086 /*
6087 * Do not retry the unhandleable instruction if it faults on the
6088 * readonly host memory, otherwise it will goto a infinite loop:
6089 * retry instruction -> write #PF -> emulation fail -> retry
6090 * instruction -> ...
6091 */
6092 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6093
6094 /*
6095 * If the instruction failed on the error pfn, it can not be fixed,
6096 * report the error to userspace.
6097 */
6098 if (is_error_noslot_pfn(pfn))
6099 return false;
6100
6101 kvm_release_pfn_clean(pfn);
6102
6103 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6104 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6105 unsigned int indirect_shadow_pages;
6106
6107 spin_lock(&vcpu->kvm->mmu_lock);
6108 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6109 spin_unlock(&vcpu->kvm->mmu_lock);
6110
6111 if (indirect_shadow_pages)
6112 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6113
a6f177ef 6114 return true;
8e3d9d06 6115 }
a6f177ef 6116
95b3cf69
XG		 6117 /*
6118 * if emulation was due to access to shadowed page table
6119 * and it failed try to unshadow page and re-enter the
6120 * guest to let CPU execute the instruction.
6121 */
6122 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6123
6124 /*
6125 * If the access faults on its page table, it can not
6126 * be fixed by unprotecting shadow page and it should
6127 * be reported to userspace.
6128 */
6129 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6130}
6131
1cb3f3ae
XG		 6132static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6133 unsigned long cr2, int emulation_type)
6134{
6135 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6136 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6137
6138 last_retry_eip = vcpu->arch.last_retry_eip;
6139 last_retry_addr = vcpu->arch.last_retry_addr;
6140
6141 /*
6142 * If the emulation is caused by #PF and it is non-page_table
6143 * writing instruction, it means the VM-EXIT is caused by shadow
6144 * page protected, we can zap the shadow page and retry this
6145 * instruction directly.
6146 *
6147 * Note: if the guest uses a non-page-table modifying instruction
6148 * on the PDE that points to the instruction, then we will unmap
6149 * the instruction and go to an infinite loop. So, we cache the
6150 * last retried eip and the last fault address, if we meet the eip
6151 * and the address again, we can break out of the potential infinite
6152 * loop.
6153 */
6154 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6155
384bf221 6156 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6157 return false;
6158
6c3dfeb6
SC		 6159 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6160 return false;
6161
1cb3f3ae
XG		 6162 if (x86_page_table_writing_insn(ctxt))
6163 return false;
6164
6165 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6166 return false;
6167
6168 vcpu->arch.last_retry_eip = ctxt->eip;
6169 vcpu->arch.last_retry_addr = cr2;
6170
44dd3ffa 6171 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6172 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6173
22368028 6174 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6175
6176 return true;
6177}
6178
716d51ab
GN		 6179static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6180static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6181
64d60670 6182static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6183{
64d60670 6184 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6185 /* This is a good place to trace that we are exiting SMM. */
6186 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6187
c43203ca
PB		 6188 /* Process a latched INIT or SMI, if any. */
6189 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6190 }
699023e2
PB		 6191
6192 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6193}
6194
6195static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6196{
6197 unsigned changed = vcpu->arch.hflags ^ emul_flags;
6198
a584539b 6199 vcpu->arch.hflags = emul_flags;
64d60670
PB		 6200
6201 if (changed & HF_SMM_MASK)
6202 kvm_smm_changed(vcpu);
a584539b
PB		 6203}
6204
4a1e10d5
PB		 6205static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6206 unsigned long *db)
6207{
6208 u32 dr6 = 0;
6209 int i;
6210 u32 enable, rwlen;
6211
6212 enable = dr7;
6213 rwlen = dr7 >> 16;
6214 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6215 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6216 dr6 |= (1 << i);
6217 return dr6;
6218}
6219
c8401dda 6220static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6221{
6222 struct kvm_run *kvm_run = vcpu->run;
6223
c8401dda
PB		 6224 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6225 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6226 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6227 kvm_run->debug.arch.exception = DB_VECTOR;
6228 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6229 *r = EMULATE_USER_EXIT;
6230 } else {
f10c729f 6231 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6232 }
6233}
6234
6affcbed
KH		 6235int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6236{
6237 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6238 int r = EMULATE_DONE;
6239
6240 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6241
6242 /*
6243 * rflags is the old, "raw" value of the flags. The new value has
6244 * not been saved yet.
6245 *
6246 * This is correct even for TF set by the guest, because "the
6247 * processor will not generate this exception after the instruction
6248 * that sets the TF flag".
6249 */
6250 if (unlikely(rflags & X86_EFLAGS_TF))
6251 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6252 return r == EMULATE_DONE;
6253}
6254EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6255
4a1e10d5
PB		 6256static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6257{
4a1e10d5
PB		 6258 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6259 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6260 struct kvm_run *kvm_run = vcpu->run;
6261 unsigned long eip = kvm_get_linear_rip(vcpu);
6262 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6263 vcpu->arch.guest_debug_dr7,
6264 vcpu->arch.eff_db);
6265
6266 if (dr6 != 0) {
6f43ed01 6267 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6268 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6269 kvm_run->debug.arch.exception = DB_VECTOR;
6270 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6271 *r = EMULATE_USER_EXIT;
6272 return true;
6273 }
6274 }
6275
4161a569
NA		 6276 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6277 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6278 unsigned long eip = kvm_get_linear_rip(vcpu);
6279 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6280 vcpu->arch.dr7,
6281 vcpu->arch.db);
6282
6283 if (dr6 != 0) {
6284 vcpu->arch.dr6 &= ~15;
6f43ed01 6285 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6286 kvm_queue_exception(vcpu, DB_VECTOR);
6287 *r = EMULATE_DONE;
6288 return true;
6289 }
6290 }
6291
6292 return false;
6293}
6294
04789b66
LA		 6295static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6296{
2d7921c4
AM		 6297 switch (ctxt->opcode_len) {
6298 case 1:
6299 switch (ctxt->b) {
6300 case 0xe4: /* IN */
6301 case 0xe5:
6302 case 0xec:
6303 case 0xed:
6304 case 0xe6: /* OUT */
6305 case 0xe7:
6306 case 0xee:
6307 case 0xef:
6308 case 0x6c: /* INS */
6309 case 0x6d:
6310 case 0x6e: /* OUTS */
6311 case 0x6f:
6312 return true;
6313 }
6314 break;
6315 case 2:
6316 switch (ctxt->b) {
6317 case 0x33: /* RDPMC */
6318 return true;
6319 }
6320 break;
04789b66
LA		 6321 }
6322
6323 return false;
6324}
6325
51d8b661
AP		 6326int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6327 unsigned long cr2,
dc25e89e
AP		 6328 int emulation_type,
6329 void *insn,
6330 int insn_len)
bbd9b64e 6331{
95cb2295 6332 int r;
9d74191a 6333 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6334 bool writeback = true;
93c05d3e 6335 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6336
c595ceee
PB		 6337 vcpu->arch.l1tf_flush_l1d = true;
6338
93c05d3e
XG		 6339 /*
6340 * Clear write_fault_to_shadow_pgtable here to ensure it is
6341 * never reused.
6342 */
6343 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6344 kvm_clear_exception_queue(vcpu);
8d7d8102 6345
571008da 6346 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6347 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6348
6349 /*
6350 * We will reenter on the same instruction since
6351 * we do not set complete_userspace_io. This does not
6352 * handle watchpoints yet, those would be handled in
6353 * the emulate_ops.
6354 */
d391f120
VK		 6355 if (!(emulation_type & EMULTYPE_SKIP) &&
6356 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6357 return r;
6358
9d74191a
TY		 6359 ctxt->interruptibility = 0;
6360 ctxt->have_exception = false;
e0ad0b47 6361 ctxt->exception.vector = -1;
9d74191a 6362 ctxt->perm_ok = false;
bbd9b64e 6363
b51e974f 6364 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6365
9d74191a 6366 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6367
e46479f8 6368 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6369 ++vcpu->stat.insn_emulation;
1d2887e2 6370 if (r != EMULATION_OK) {
4005996e
AK		 6371 if (emulation_type & EMULTYPE_TRAP_UD)
6372 return EMULATE_FAIL;
991eebf9
GN		 6373 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6374 emulation_type))
bbd9b64e 6375 return EMULATE_DONE;
6ea6e843
PB		 6376 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6377 return EMULATE_DONE;
6d77dbfc
GN		 6378 if (emulation_type & EMULTYPE_SKIP)
6379 return EMULATE_FAIL;
e2366171 6380 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6381 }
6382 }
6383
04789b66
LA		 6384 if ((emulation_type & EMULTYPE_VMWARE) &&
6385 !is_vmware_backdoor_opcode(ctxt))
6386 return EMULATE_FAIL;
6387
ba8afb6b 6388 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6389 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6390 if (ctxt->eflags & X86_EFLAGS_RF)
6391 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6392 return EMULATE_DONE;
6393 }
6394
1cb3f3ae
XG		 6395 if (retry_instruction(ctxt, cr2, emulation_type))
6396 return EMULATE_DONE;
6397
7ae441ea 6398 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6399 changes registers values during IO operation */
7ae441ea
GN		 6400 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6401 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6402 emulator_invalidate_register_cache(ctxt);
7ae441ea 6403 }
4d2179e1 6404
5cd21917 6405restart:
0f89b207
TL		 6406 /* Save the faulting GPA (cr2) in the address field */
6407 ctxt->exception.address = cr2;
6408
9d74191a 6409 r = x86_emulate_insn(ctxt);
bbd9b64e 6410
775fde86
JR		 6411 if (r == EMULATION_INTERCEPTED)
6412 return EMULATE_DONE;
6413
d2ddd1c4 6414 if (r == EMULATION_FAILED) {
991eebf9
GN		 6415 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6416 emulation_type))
c3cd7ffa
GN		 6417 return EMULATE_DONE;
6418
e2366171 6419 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6420 }
6421
9d74191a 6422 if (ctxt->have_exception) {
d2ddd1c4 6423 r = EMULATE_DONE;
ef54bcfe
PB		 6424 if (inject_emulated_exception(vcpu))
6425 return r;
d2ddd1c4 6426 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6427 if (!vcpu->arch.pio.in) {
6428 /* FIXME: return into emulator if single-stepping. */
3457e419 6429 vcpu->arch.pio.count = 0;
0912c977 6430 } else {
7ae441ea 6431 writeback = false;
716d51ab
GN		 6432 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6433 }
ac0a48c3 6434 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6435 } else if (vcpu->mmio_needed) {
6436 if (!vcpu->mmio_is_write)
6437 writeback = false;
ac0a48c3 6438 r = EMULATE_USER_EXIT;
716d51ab 6439 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6440 } else if (r == EMULATION_RESTART)
5cd21917 6441 goto restart;
d2ddd1c4
GN		 6442 else
6443 r = EMULATE_DONE;
f850e2e6 6444
7ae441ea 6445 if (writeback) {
6addfc42 6446 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6447 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6448 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6449 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6450 if (r == EMULATE_DONE &&
6451 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6452 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6453 if (!ctxt->have_exception ||
6454 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6455 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6456
6457 /*
6458 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6459 * do nothing, and it will be requested again as soon as
6460 * the shadow expires. But we still need to check here,
6461 * because POPF has no interrupt shadow.
6462 */
6463 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6464 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6465 } else
6466 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6467
6468 return r;
de7d789a 6469}
c60658d1
SC		 6470
6471int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6472{
6473 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6474}
6475EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6476
6477int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6478 void *insn, int insn_len)
6479{
6480 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6481}
6482EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6483
dca7f128
SC		 6484static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6485 unsigned short port)
de7d789a 6486{
cf8f70bf 6487 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6488 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6489 size, port, &val, 1);
cf8f70bf 6490 /* do not return to emulator after return from userspace */
7972995b 6491 vcpu->arch.pio.count = 0;
de7d789a
CO		 6492 return ret;
6493}
de7d789a 6494
8370c3d0
TL		 6495static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6496{
6497 unsigned long val;
6498
6499 /* We should only ever be called with arch.pio.count equal to 1 */
6500 BUG_ON(vcpu->arch.pio.count != 1);
6501
6502 /* For size less than 4 we merge, else we zero extend */
6503 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6504 : 0;
6505
6506 /*
6507 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6508 * the copy and tracing
6509 */
6510 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6511 vcpu->arch.pio.port, &val, 1);
6512 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6513
6514 return 1;
6515}
6516
dca7f128
SC		 6517static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6518 unsigned short port)
8370c3d0
TL		 6519{
6520 unsigned long val;
6521 int ret;
6522
6523 /* For size less than 4 we merge, else we zero extend */
6524 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6525
6526 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6527 &val, 1);
6528 if (ret) {
6529 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6530 return ret;
6531 }
6532
6533 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6534
6535 return 0;
6536}
dca7f128
SC		 6537
6538int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6539{
6540 int ret = kvm_skip_emulated_instruction(vcpu);
6541
6542 /*
6543 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6544 * KVM_EXIT_DEBUG here.
6545 */
6546 if (in)
6547 return kvm_fast_pio_in(vcpu, size, port) && ret;
6548 else
6549 return kvm_fast_pio_out(vcpu, size, port) && ret;
6550}
6551EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6552
251a5fd6 6553static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6554{
0a3aee0d 6555 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6556 return 0;
8cfdc000
ZA		 6557}
6558
6559static void tsc_khz_changed(void *data)
c8076604 6560{
8cfdc000
ZA		 6561 struct cpufreq_freqs *freq = data;
6562 unsigned long khz = 0;
6563
6564 if (data)
6565 khz = freq->new;
6566 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6567 khz = cpufreq_quick_get(raw_smp_processor_id());
6568 if (!khz)
6569 khz = tsc_khz;
0a3aee0d 6570 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6571}
6572
5fa4ec9c 6573#ifdef CONFIG_X86_64
0092e434
VK		 6574static void kvm_hyperv_tsc_notifier(void)
6575{
0092e434
VK		 6576 struct kvm *kvm;
6577 struct kvm_vcpu *vcpu;
6578 int cpu;
6579
6580 spin_lock(&kvm_lock);
6581 list_for_each_entry(kvm, &vm_list, vm_list)
6582 kvm_make_mclock_inprogress_request(kvm);
6583
6584 hyperv_stop_tsc_emulation();
6585
6586 /* TSC frequency always matches when on Hyper-V */
6587 for_each_present_cpu(cpu)
6588 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6589 kvm_max_guest_tsc_khz = tsc_khz;
6590
6591 list_for_each_entry(kvm, &vm_list, vm_list) {
6592 struct kvm_arch *ka = &kvm->arch;
6593
6594 spin_lock(&ka->pvclock_gtod_sync_lock);
6595
6596 pvclock_update_vm_gtod_copy(kvm);
6597
6598 kvm_for_each_vcpu(cpu, vcpu, kvm)
6599 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6600
6601 kvm_for_each_vcpu(cpu, vcpu, kvm)
6602 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6603
6604 spin_unlock(&ka->pvclock_gtod_sync_lock);
6605 }
6606 spin_unlock(&kvm_lock);
0092e434 6607}
5fa4ec9c 6608#endif
0092e434 6609
c8076604
GH		 6610static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6611 void *data)
6612{
6613 struct cpufreq_freqs *freq = data;
6614 struct kvm *kvm;
6615 struct kvm_vcpu *vcpu;
6616 int i, send_ipi = 0;
6617
8cfdc000
ZA		 6618 /*
6619 * We allow guests to temporarily run on slowing clocks,
6620 * provided we notify them after, or to run on accelerating
6621 * clocks, provided we notify them before. Thus time never
6622 * goes backwards.
6623 *
6624 * However, we have a problem. We can't atomically update
6625 * the frequency of a given CPU from this function; it is
6626 * merely a notifier, which can be called from any CPU.
6627 * Changing the TSC frequency at arbitrary points in time
6628 * requires a recomputation of local variables related to
6629 * the TSC for each VCPU. We must flag these local variables
6630 * to be updated and be sure the update takes place with the
6631 * new frequency before any guests proceed.
6632 *
6633 * Unfortunately, the combination of hotplug CPU and frequency
6634 * change creates an intractable locking scenario; the order
6635 * of when these callouts happen is undefined with respect to
6636 * CPU hotplug, and they can race with each other. As such,
6637 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6638 * undefined; you can actually have a CPU frequency change take
6639 * place in between the computation of X and the setting of the
6640 * variable. To protect against this problem, all updates of
6641 * the per_cpu tsc_khz variable are done in an interrupt
6642 * protected IPI, and all callers wishing to update the value
6643 * must wait for a synchronous IPI to complete (which is trivial
6644 * if the caller is on the CPU already). This establishes the
6645 * necessary total order on variable updates.
6646 *
6647 * Note that because a guest time update may take place
6648 * anytime after the setting of the VCPU's request bit, the
6649 * correct TSC value must be set before the request. However,
6650 * to ensure the update actually makes it to any guest which
6651 * starts running in hardware virtualization between the set
6652 * and the acquisition of the spinlock, we must also ping the
6653 * CPU after setting the request bit.
6654 *
6655 */
6656
c8076604
GH		 6657 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6658 return 0;
6659 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6660 return 0;
8cfdc000
ZA		 6661
6662 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6663
2f303b74 6664 spin_lock(&kvm_lock);
c8076604 6665 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6666 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6667 if (vcpu->cpu != freq->cpu)
6668 continue;
c285545f 6669 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6670 if (vcpu->cpu != smp_processor_id())
8cfdc000 6671 send_ipi = 1;
c8076604
GH		 6672 }
6673 }
2f303b74 6674 spin_unlock(&kvm_lock);
c8076604
GH		 6675
6676 if (freq->old < freq->new && send_ipi) {
6677 /*
6678 * We upscale the frequency. Must make the guest
6679 * doesn't see old kvmclock values while running with
6680 * the new frequency, otherwise we risk the guest sees
6681 * time go backwards.
6682 *
6683 * In case we update the frequency for another cpu
6684 * (which might be in guest context) send an interrupt
6685 * to kick the cpu out of guest context. Next time
6686 * guest context is entered kvmclock will be updated,
6687 * so the guest will not see stale values.
6688 */
8cfdc000 6689 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6690 }
6691 return 0;
6692}
6693
6694static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6695 .notifier_call = kvmclock_cpufreq_notifier
6696};
6697
251a5fd6 6698static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6699{
251a5fd6
SAS		 6700 tsc_khz_changed(NULL);
6701 return 0;
8cfdc000
ZA		 6702}
6703
b820cc0c
ZA		 6704static void kvm_timer_init(void)
6705{
c285545f 6706 max_tsc_khz = tsc_khz;
460dd42e 6707
b820cc0c 6708 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6709#ifdef CONFIG_CPU_FREQ
6710 struct cpufreq_policy policy;
758f588d
BP		 6711 int cpu;
6712
c285545f 6713 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6714 cpu = get_cpu();
6715 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6716 if (policy.cpuinfo.max_freq)
6717 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6718 put_cpu();
c285545f 6719#endif
b820cc0c
ZA		 6720 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6721 CPUFREQ_TRANSITION_NOTIFIER);
6722 }
c285545f 6723 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6724
73c1b41e 6725 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6726 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6727}
6728
dd60d217
AK		 6729DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6730EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6731
f5132b01 6732int kvm_is_in_guest(void)
ff9d07a0 6733{
086c9855 6734 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6735}
6736
6737static int kvm_is_user_mode(void)
6738{
6739 int user_mode = 3;
dcf46b94 6740
086c9855
AS		 6741 if (__this_cpu_read(current_vcpu))
6742 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6743
ff9d07a0
ZY		 6744 return user_mode != 0;
6745}
6746
6747static unsigned long kvm_get_guest_ip(void)
6748{
6749 unsigned long ip = 0;
dcf46b94 6750
086c9855
AS		 6751 if (__this_cpu_read(current_vcpu))
6752 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6753
ff9d07a0
ZY		 6754 return ip;
6755}
6756
6757static struct perf_guest_info_callbacks kvm_guest_cbs = {
6758 .is_in_guest = kvm_is_in_guest,
6759 .is_user_mode = kvm_is_user_mode,
6760 .get_guest_ip = kvm_get_guest_ip,
6761};
6762
ce88decf
XG		 6763static void kvm_set_mmio_spte_mask(void)
6764{
6765 u64 mask;
6766 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6767
6768 /*
6769 * Set the reserved bits and the present bit of an paging-structure
6770 * entry to generate page fault with PFER.RSV = 1.
6771 */
28a1f3ac
JS		 6772
6773 /*
6774 * Mask the uppermost physical address bit, which would be reserved as
6775 * long as the supported physical address width is less than 52.
6776 */
6777 mask = 1ull << 51;
885032b9 6778
885032b9 6779 /* Set the present bit. */
ce88decf
XG		 6780 mask |= 1ull;
6781
ce88decf
XG		 6782 /*
6783 * If reserved bit is not supported, clear the present bit to disable
6784 * mmio page fault.
6785 */
7288bde1 6786 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6787 mask &= ~1ull;
ce88decf 6788
dcdca5fe 6789 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6790}
6791
16e8d74d
MT		 6792#ifdef CONFIG_X86_64
6793static void pvclock_gtod_update_fn(struct work_struct *work)
6794{
d828199e
MT		 6795 struct kvm *kvm;
6796
6797 struct kvm_vcpu *vcpu;
6798 int i;
6799
2f303b74 6800 spin_lock(&kvm_lock);
d828199e
MT		 6801 list_for_each_entry(kvm, &vm_list, vm_list)
6802 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6803 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6804 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6805 spin_unlock(&kvm_lock);
16e8d74d
MT		 6806}
6807
6808static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6809
6810/*
6811 * Notification about pvclock gtod data update.
6812 */
6813static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6814 void *priv)
6815{
6816 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6817 struct timekeeper *tk = priv;
6818
6819 update_pvclock_gtod(tk);
6820
6821 /* disable master clock if host does not trust, or does not
b0c39dc6 6822 * use, TSC based clocksource.
16e8d74d 6823 */
b0c39dc6 6824 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6825 atomic_read(&kvm_guest_has_master_clock) != 0)
6826 queue_work(system_long_wq, &pvclock_gtod_work);
6827
6828 return 0;
6829}
6830
6831static struct notifier_block pvclock_gtod_notifier = {
6832 .notifier_call = pvclock_gtod_notify,
6833};
6834#endif
6835
f8c16bba 6836int kvm_arch_init(void *opaque)
043405e1 6837{
b820cc0c 6838 int r;
6b61edf7 6839 struct kvm_x86_ops *ops = opaque;
f8c16bba 6840
f8c16bba
ZX		 6841 if (kvm_x86_ops) {
6842 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6843 r = -EEXIST;
6844 goto out;
f8c16bba
ZX		 6845 }
6846
6847 if (!ops->cpu_has_kvm_support()) {
6848 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6849 r = -EOPNOTSUPP;
6850 goto out;
f8c16bba
ZX		 6851 }
6852 if (ops->disabled_by_bios()) {
6853 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6854 r = -EOPNOTSUPP;
6855 goto out;
f8c16bba
ZX		 6856 }
6857
b666a4b6
MO		 6858 /*
6859 * KVM explicitly assumes that the guest has an FPU and
6860 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
6861 * vCPU's FPU state as a fxregs_state struct.
6862 */
6863 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
6864 printk(KERN_ERR "kvm: inadequate fpu\n");
6865 r = -EOPNOTSUPP;
6866 goto out;
6867 }
6868
013f6a5d 6869 r = -ENOMEM;
ed8e4812 6870 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 6871 __alignof__(struct fpu), SLAB_ACCOUNT,
6872 NULL);
6873 if (!x86_fpu_cache) {
6874 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
6875 goto out;
6876 }
6877
013f6a5d
MT		 6878 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6879 if (!shared_msrs) {
6880 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 6881 goto out_free_x86_fpu_cache;
013f6a5d
MT		 6882 }
6883
97db56ce
AK		 6884 r = kvm_mmu_module_init();
6885 if (r)
013f6a5d 6886 goto out_free_percpu;
97db56ce 6887
ce88decf 6888 kvm_set_mmio_spte_mask();
97db56ce 6889
f8c16bba 6890 kvm_x86_ops = ops;
920c8377 6891
7b52345e 6892 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6893 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6894 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6895 kvm_timer_init();
c8076604 6896
ff9d07a0
ZY		 6897 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6898
d366bf7e 6899 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6900 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6901
c5cc421b 6902 kvm_lapic_init();
16e8d74d
MT		 6903#ifdef CONFIG_X86_64
6904 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6905
5fa4ec9c 6906 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6907 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6908#endif
6909
f8c16bba 6910 return 0;
56c6d28a 6911
013f6a5d
MT		 6912out_free_percpu:
6913 free_percpu(shared_msrs);
b666a4b6
MO		 6914out_free_x86_fpu_cache:
6915 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 6916out:
56c6d28a 6917 return r;
043405e1 6918}
8776e519 6919
f8c16bba
ZX		 6920void kvm_arch_exit(void)
6921{
0092e434 6922#ifdef CONFIG_X86_64
5fa4ec9c 6923 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6924 clear_hv_tscchange_cb();
6925#endif
cef84c30 6926 kvm_lapic_exit();
ff9d07a0
ZY		 6927 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6928
888d256e
JK		 6929 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6930 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6931 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6932 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6933#ifdef CONFIG_X86_64
6934 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6935#endif
f8c16bba 6936 kvm_x86_ops = NULL;
56c6d28a 6937 kvm_mmu_module_exit();
013f6a5d 6938 free_percpu(shared_msrs);
b666a4b6 6939 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 6940}
f8c16bba 6941
5cb56059 6942int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6943{
6944 ++vcpu->stat.halt_exits;
35754c98 6945 if (lapic_in_kernel(vcpu)) {
a4535290 6946 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6947 return 1;
6948 } else {
6949 vcpu->run->exit_reason = KVM_EXIT_HLT;
6950 return 0;
6951 }
6952}
5cb56059
JS		 6953EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6954
6955int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6956{
6affcbed
KH		 6957 int ret = kvm_skip_emulated_instruction(vcpu);
6958 /*
6959 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6960 * KVM_EXIT_DEBUG here.
6961 */
6962 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6963}
8776e519
HB		 6964EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6965
8ef81a9a 6966#ifdef CONFIG_X86_64
55dd00a7
MT		 6967static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6968 unsigned long clock_type)
6969{
6970 struct kvm_clock_pairing clock_pairing;
899a31f5 6971 struct timespec64 ts;
80fbd89c 6972 u64 cycle;
55dd00a7
MT		 6973 int ret;
6974
6975 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6976 return -KVM_EOPNOTSUPP;
6977
6978 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6979 return -KVM_EOPNOTSUPP;
6980
6981 clock_pairing.sec = ts.tv_sec;
6982 clock_pairing.nsec = ts.tv_nsec;
6983 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6984 clock_pairing.flags = 0;
bcbfbd8e 6985 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 6986
6987 ret = 0;
6988 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6989 sizeof(struct kvm_clock_pairing)))
6990 ret = -KVM_EFAULT;
6991
6992 return ret;
6993}
8ef81a9a 6994#endif
55dd00a7 6995
6aef266c
SV		 6996/*
6997 * kvm_pv_kick_cpu_op: Kick a vcpu.
6998 *
6999 * @apicid - apicid of vcpu to be kicked.
7000 */
7001static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7002{
24d2166b 7003 struct kvm_lapic_irq lapic_irq;
6aef266c 7004
24d2166b
R		 7005 lapic_irq.shorthand = 0;
7006 lapic_irq.dest_mode = 0;
ebd28fcb 7007 lapic_irq.level = 0;
24d2166b 7008 lapic_irq.dest_id = apicid;
93bbf0b8 7009 lapic_irq.msi_redir_hint = false;
6aef266c 7010
24d2166b 7011 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7012 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7013}
7014
d62caabb
AS		 7015void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7016{
7017 vcpu->arch.apicv_active = false;
7018 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7019}
7020
8776e519
HB		 7021int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7022{
7023 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7024 int op_64_bit;
8776e519 7025
696ca779
RK		 7026 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7027 return kvm_hv_hypercall(vcpu);
55cd8e5a 7028
5fdbf976
MT		 7029 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
7030 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
7031 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
7032 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
7033 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 7034
229456fc 7035 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7036
a449c7aa
NA		 7037 op_64_bit = is_64_bit_mode(vcpu);
7038 if (!op_64_bit) {
8776e519
HB		 7039 nr &= 0xFFFFFFFF;
7040 a0 &= 0xFFFFFFFF;
7041 a1 &= 0xFFFFFFFF;
7042 a2 &= 0xFFFFFFFF;
7043 a3 &= 0xFFFFFFFF;
7044 }
7045
07708c4a
JK		 7046 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7047 ret = -KVM_EPERM;
696ca779 7048 goto out;
07708c4a
JK		 7049 }
7050
8776e519 7051 switch (nr) {
b93463aa
AK		 7052 case KVM_HC_VAPIC_POLL_IRQ:
7053 ret = 0;
7054 break;
6aef266c
SV		 7055 case KVM_HC_KICK_CPU:
7056 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7057 ret = 0;
7058 break;
8ef81a9a 7059#ifdef CONFIG_X86_64
55dd00a7
MT		 7060 case KVM_HC_CLOCK_PAIRING:
7061 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7062 break;
4180bf1b
WL		 7063 case KVM_HC_SEND_IPI:
7064 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7065 break;
8ef81a9a 7066#endif
8776e519
HB		 7067 default:
7068 ret = -KVM_ENOSYS;
7069 break;
7070 }
696ca779 7071out:
a449c7aa
NA		 7072 if (!op_64_bit)
7073 ret = (u32)ret;
5fdbf976 7074 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 7075
f11c3a8d 7076 ++vcpu->stat.hypercalls;
6356ee0c 7077 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7078}
7079EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7080
b6785def 7081static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7082{
d6aa1000 7083 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7084 char instruction[3];
5fdbf976 7085 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7086
8776e519 7087 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7088
ce2e852e
DV		 7089 return emulator_write_emulated(ctxt, rip, instruction, 3,
7090 &ctxt->exception);
8776e519
HB		 7091}
7092
851ba692 7093static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7094{
782d422b
MG		 7095 return vcpu->run->request_interrupt_window &&
7096 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7097}
7098
851ba692 7099static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7100{
851ba692
AK		 7101 struct kvm_run *kvm_run = vcpu->run;
7102
91586a3b 7103 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7104 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7105 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7106 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7107 kvm_run->ready_for_interrupt_injection =
7108 pic_in_kernel(vcpu->kvm) ||
782d422b 7109 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7110}
7111
95ba8273
GN		 7112static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7113{
7114 int max_irr, tpr;
7115
7116 if (!kvm_x86_ops->update_cr8_intercept)
7117 return;
7118
bce87cce 7119 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7120 return;
7121
d62caabb
AS		 7122 if (vcpu->arch.apicv_active)
7123 return;
7124
8db3baa2
GN		 7125 if (!vcpu->arch.apic->vapic_addr)
7126 max_irr = kvm_lapic_find_highest_irr(vcpu);
7127 else
7128 max_irr = -1;
95ba8273
GN		 7129
7130 if (max_irr != -1)
7131 max_irr >>= 4;
7132
7133 tpr = kvm_lapic_get_cr8(vcpu);
7134
7135 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7136}
7137
b6b8a145 7138static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7139{
b6b8a145
JK		 7140 int r;
7141
95ba8273 7142 /* try to reinject previous events if any */
664f8e26 7143
1a680e35
LA		 7144 if (vcpu->arch.exception.injected)
7145 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7146 /*
a042c26f
LA		 7147 * Do not inject an NMI or interrupt if there is a pending
7148 * exception. Exceptions and interrupts are recognized at
7149 * instruction boundaries, i.e. the start of an instruction.
7150 * Trap-like exceptions, e.g. #DB, have higher priority than
7151 * NMIs and interrupts, i.e. traps are recognized before an
7152 * NMI/interrupt that's pending on the same instruction.
7153 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7154 * priority, but are only generated (pended) during instruction
7155 * execution, i.e. a pending fault-like exception means the
7156 * fault occurred on the *previous* instruction and must be
7157 * serviced prior to recognizing any new events in order to
7158 * fully complete the previous instruction.
664f8e26 7159 */
1a680e35
LA		 7160 else if (!vcpu->arch.exception.pending) {
7161 if (vcpu->arch.nmi_injected)
664f8e26 7162 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7163 else if (vcpu->arch.interrupt.injected)
664f8e26 7164 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7165 }
7166
1a680e35
LA		 7167 /*
7168 * Call check_nested_events() even if we reinjected a previous event
7169 * in order for caller to determine if it should require immediate-exit
7170 * from L2 to L1 due to pending L1 events which require exit
7171 * from L2 to L1.
7172 */
664f8e26
WL		 7173 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7174 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7175 if (r != 0)
7176 return r;
7177 }
7178
7179 /* try to inject new event if pending */
b59bb7bd 7180 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7181 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7182 vcpu->arch.exception.has_error_code,
7183 vcpu->arch.exception.error_code);
d6e8c854 7184
1a680e35 7185 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7186 vcpu->arch.exception.pending = false;
7187 vcpu->arch.exception.injected = true;
7188
d6e8c854
NA		 7189 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7190 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7191 X86_EFLAGS_RF);
7192
f10c729f
JM		 7193 if (vcpu->arch.exception.nr == DB_VECTOR) {
7194 /*
7195 * This code assumes that nSVM doesn't use
7196 * check_nested_events(). If it does, the
7197 * DR6/DR7 changes should happen before L1
7198 * gets a #VMEXIT for an intercepted #DB in
7199 * L2. (Under VMX, on the other hand, the
7200 * DR6/DR7 changes should not happen in the
7201 * event of a VM-exit to L1 for an intercepted
7202 * #DB in L2.)
7203 */
7204 kvm_deliver_exception_payload(vcpu);
7205 if (vcpu->arch.dr7 & DR7_GD) {
7206 vcpu->arch.dr7 &= ~DR7_GD;
7207 kvm_update_dr7(vcpu);
7208 }
6bdf0662
NA		 7209 }
7210
cfcd20e5 7211 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7212 }
7213
7214 /* Don't consider new event if we re-injected an event */
7215 if (kvm_event_needs_reinjection(vcpu))
7216 return 0;
7217
7218 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7219 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7220 vcpu->arch.smi_pending = false;
52797bf9 7221 ++vcpu->arch.smi_count;
ee2cd4b7 7222 enter_smm(vcpu);
c43203ca 7223 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7224 --vcpu->arch.nmi_pending;
7225 vcpu->arch.nmi_injected = true;
7226 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7227 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7228 /*
7229 * Because interrupts can be injected asynchronously, we are
7230 * calling check_nested_events again here to avoid a race condition.
7231 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7232 * proposal and current concerns. Perhaps we should be setting
7233 * KVM_REQ_EVENT only on certain events and not unconditionally?
7234 */
7235 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7236 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7237 if (r != 0)
7238 return r;
7239 }
95ba8273 7240 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7241 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7242 false);
7243 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7244 }
7245 }
ee2cd4b7 7246
b6b8a145 7247 return 0;
95ba8273
GN		 7248}
7249
7460fb4a
AK		 7250static void process_nmi(struct kvm_vcpu *vcpu)
7251{
7252 unsigned limit = 2;
7253
7254 /*
7255 * x86 is limited to one NMI running, and one NMI pending after it.
7256 * If an NMI is already in progress, limit further NMIs to just one.
7257 * Otherwise, allow two (and we'll inject the first one immediately).
7258 */
7259 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7260 limit = 1;
7261
7262 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7263 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7264 kvm_make_request(KVM_REQ_EVENT, vcpu);
7265}
7266
ee2cd4b7 7267static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7268{
7269 u32 flags = 0;
7270 flags |= seg->g << 23;
7271 flags |= seg->db << 22;
7272 flags |= seg->l << 21;
7273 flags |= seg->avl << 20;
7274 flags |= seg->present << 15;
7275 flags |= seg->dpl << 13;
7276 flags |= seg->s << 12;
7277 flags |= seg->type << 8;
7278 return flags;
7279}
7280
ee2cd4b7 7281static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7282{
7283 struct kvm_segment seg;
7284 int offset;
7285
7286 kvm_get_segment(vcpu, &seg, n);
7287 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7288
7289 if (n < 3)
7290 offset = 0x7f84 + n * 12;
7291 else
7292 offset = 0x7f2c + (n - 3) * 12;
7293
7294 put_smstate(u32, buf, offset + 8, seg.base);
7295 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7296 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7297}
7298
efbb288a 7299#ifdef CONFIG_X86_64
ee2cd4b7 7300static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7301{
7302 struct kvm_segment seg;
7303 int offset;
7304 u16 flags;
7305
7306 kvm_get_segment(vcpu, &seg, n);
7307 offset = 0x7e00 + n * 16;
7308
ee2cd4b7 7309 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7310 put_smstate(u16, buf, offset, seg.selector);
7311 put_smstate(u16, buf, offset + 2, flags);
7312 put_smstate(u32, buf, offset + 4, seg.limit);
7313 put_smstate(u64, buf, offset + 8, seg.base);
7314}
efbb288a 7315#endif
660a5d51 7316
ee2cd4b7 7317static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7318{
7319 struct desc_ptr dt;
7320 struct kvm_segment seg;
7321 unsigned long val;
7322 int i;
7323
7324 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7325 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7326 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7327 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7328
7329 for (i = 0; i < 8; i++)
7330 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7331
7332 kvm_get_dr(vcpu, 6, &val);
7333 put_smstate(u32, buf, 0x7fcc, (u32)val);
7334 kvm_get_dr(vcpu, 7, &val);
7335 put_smstate(u32, buf, 0x7fc8, (u32)val);
7336
7337 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7338 put_smstate(u32, buf, 0x7fc4, seg.selector);
7339 put_smstate(u32, buf, 0x7f64, seg.base);
7340 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7341 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7342
7343 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7344 put_smstate(u32, buf, 0x7fc0, seg.selector);
7345 put_smstate(u32, buf, 0x7f80, seg.base);
7346 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7347 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7348
7349 kvm_x86_ops->get_gdt(vcpu, &dt);
7350 put_smstate(u32, buf, 0x7f74, dt.address);
7351 put_smstate(u32, buf, 0x7f70, dt.size);
7352
7353 kvm_x86_ops->get_idt(vcpu, &dt);
7354 put_smstate(u32, buf, 0x7f58, dt.address);
7355 put_smstate(u32, buf, 0x7f54, dt.size);
7356
7357 for (i = 0; i < 6; i++)
ee2cd4b7 7358 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7359
7360 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7361
7362 /* revision id */
7363 put_smstate(u32, buf, 0x7efc, 0x00020000);
7364 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7365}
7366
ee2cd4b7 7367static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7368{
7369#ifdef CONFIG_X86_64
7370 struct desc_ptr dt;
7371 struct kvm_segment seg;
7372 unsigned long val;
7373 int i;
7374
7375 for (i = 0; i < 16; i++)
7376 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7377
7378 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7379 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7380
7381 kvm_get_dr(vcpu, 6, &val);
7382 put_smstate(u64, buf, 0x7f68, val);
7383 kvm_get_dr(vcpu, 7, &val);
7384 put_smstate(u64, buf, 0x7f60, val);
7385
7386 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7387 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7388 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7389
7390 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7391
7392 /* revision id */
7393 put_smstate(u32, buf, 0x7efc, 0x00020064);
7394
7395 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7396
7397 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7398 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7399 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7400 put_smstate(u32, buf, 0x7e94, seg.limit);
7401 put_smstate(u64, buf, 0x7e98, seg.base);
7402
7403 kvm_x86_ops->get_idt(vcpu, &dt);
7404 put_smstate(u32, buf, 0x7e84, dt.size);
7405 put_smstate(u64, buf, 0x7e88, dt.address);
7406
7407 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7408 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7409 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7410 put_smstate(u32, buf, 0x7e74, seg.limit);
7411 put_smstate(u64, buf, 0x7e78, seg.base);
7412
7413 kvm_x86_ops->get_gdt(vcpu, &dt);
7414 put_smstate(u32, buf, 0x7e64, dt.size);
7415 put_smstate(u64, buf, 0x7e68, dt.address);
7416
7417 for (i = 0; i < 6; i++)
ee2cd4b7 7418 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7419#else
7420 WARN_ON_ONCE(1);
7421#endif
7422}
7423
ee2cd4b7 7424static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7425{
660a5d51 7426 struct kvm_segment cs, ds;
18c3626e 7427 struct desc_ptr dt;
660a5d51
PB		 7428 char buf[512];
7429 u32 cr0;
7430
660a5d51 7431 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7432 memset(buf, 0, 512);
d6321d49 7433 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7434 enter_smm_save_state_64(vcpu, buf);
660a5d51 7435 else
ee2cd4b7 7436 enter_smm_save_state_32(vcpu, buf);
660a5d51 7437
0234bf88
LP		 7438 /*
7439 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7440 * vCPU state (e.g. leave guest mode) after we've saved the state into
7441 * the SMM state-save area.
7442 */
7443 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7444
7445 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7446 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7447
7448 if (kvm_x86_ops->get_nmi_mask(vcpu))
7449 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7450 else
7451 kvm_x86_ops->set_nmi_mask(vcpu, true);
7452
7453 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7454 kvm_rip_write(vcpu, 0x8000);
7455
7456 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7457 kvm_x86_ops->set_cr0(vcpu, cr0);
7458 vcpu->arch.cr0 = cr0;
7459
7460 kvm_x86_ops->set_cr4(vcpu, 0);
7461
18c3626e
PB		 7462 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7463 dt.address = dt.size = 0;
7464 kvm_x86_ops->set_idt(vcpu, &dt);
7465
660a5d51
PB		 7466 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7467
7468 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7469 cs.base = vcpu->arch.smbase;
7470
7471 ds.selector = 0;
7472 ds.base = 0;
7473
7474 cs.limit = ds.limit = 0xffffffff;
7475 cs.type = ds.type = 0x3;
7476 cs.dpl = ds.dpl = 0;
7477 cs.db = ds.db = 0;
7478 cs.s = ds.s = 1;
7479 cs.l = ds.l = 0;
7480 cs.g = ds.g = 1;
7481 cs.avl = ds.avl = 0;
7482 cs.present = ds.present = 1;
7483 cs.unusable = ds.unusable = 0;
7484 cs.padding = ds.padding = 0;
7485
7486 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7487 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7488 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7489 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7490 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7491 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7492
d6321d49 7493 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7494 kvm_x86_ops->set_efer(vcpu, 0);
7495
7496 kvm_update_cpuid(vcpu);
7497 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7498}
7499
ee2cd4b7 7500static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7501{
7502 vcpu->arch.smi_pending = true;
7503 kvm_make_request(KVM_REQ_EVENT, vcpu);
7504}
7505
2860c4b1
PB		 7506void kvm_make_scan_ioapic_request(struct kvm *kvm)
7507{
7508 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7509}
7510
3d81bc7e 7511static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7512{
3d81bc7e
YZ		 7513 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7514 return;
c7c9c56c 7515
6308630b 7516 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7517
b053b2ae 7518 if (irqchip_split(vcpu->kvm))
6308630b 7519 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7520 else {
fa59cc00 7521 if (vcpu->arch.apicv_active)
d62caabb 7522 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7523 if (ioapic_in_kernel(vcpu->kvm))
7524 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7525 }
e40ff1d6
LA		 7526
7527 if (is_guest_mode(vcpu))
7528 vcpu->arch.load_eoi_exitmap_pending = true;
7529 else
7530 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7531}
7532
7533static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7534{
7535 u64 eoi_exit_bitmap[4];
7536
7537 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7538 return;
7539
5c919412
AS		 7540 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7541 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7542 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7543}
7544
93065ac7
MH		 7545int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7546 unsigned long start, unsigned long end,
7547 bool blockable)
b1394e74
RK		 7548{
7549 unsigned long apic_address;
7550
7551 /*
7552 * The physical address of apic access page is stored in the VMCS.
7553 * Update it when it becomes invalid.
7554 */
7555 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7556 if (start <= apic_address && apic_address < end)
7557 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7558
7559 return 0;
b1394e74
RK		 7560}
7561
4256f43f
TC		 7562void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7563{
c24ae0dc
TC		 7564 struct page *page = NULL;
7565
35754c98 7566 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7567 return;
7568
4256f43f
TC		 7569 if (!kvm_x86_ops->set_apic_access_page_addr)
7570 return;
7571
c24ae0dc 7572 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7573 if (is_error_page(page))
7574 return;
c24ae0dc
TC		 7575 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7576
7577 /*
7578 * Do not pin apic access page in memory, the MMU notifier
7579 * will call us again if it is migrated or swapped out.
7580 */
7581 put_page(page);
4256f43f
TC		 7582}
7583EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7584
d264ee0c
SC		 7585void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7586{
7587 smp_send_reschedule(vcpu->cpu);
7588}
7589EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7590
9357d939 7591/*
362c698f 7592 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7593 * exiting to the userspace. Otherwise, the value will be returned to the
7594 * userspace.
7595 */
851ba692 7596static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7597{
7598 int r;
62a193ed
MG		 7599 bool req_int_win =
7600 dm_request_for_irq_injection(vcpu) &&
7601 kvm_cpu_accept_dm_intr(vcpu);
7602
730dca42 7603 bool req_immediate_exit = false;
b6c7a5dc 7604
2fa6e1e1 7605 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7606 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7607 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7608 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7609 kvm_mmu_unload(vcpu);
a8eeb04a 7610 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7611 __kvm_migrate_timers(vcpu);
d828199e
MT		 7612 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7613 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7614 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7615 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7616 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7617 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7618 if (unlikely(r))
7619 goto out;
7620 }
a8eeb04a 7621 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7622 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7623 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7624 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7625 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7626 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7627 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7628 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7629 r = 0;
7630 goto out;
7631 }
a8eeb04a 7632 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7633 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7634 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7635 r = 0;
7636 goto out;
7637 }
af585b92
GN		 7638 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7639 /* Page is swapped out. Do synthetic halt */
7640 vcpu->arch.apf.halted = true;
7641 r = 1;
7642 goto out;
7643 }
c9aaa895
GC		 7644 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7645 record_steal_time(vcpu);
64d60670
PB		 7646 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7647 process_smi(vcpu);
7460fb4a
AK		 7648 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7649 process_nmi(vcpu);
f5132b01 7650 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7651 kvm_pmu_handle_event(vcpu);
f5132b01 7652 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7653 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7654 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7655 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7656 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7657 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7658 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7659 vcpu->run->eoi.vector =
7660 vcpu->arch.pending_ioapic_eoi;
7661 r = 0;
7662 goto out;
7663 }
7664 }
3d81bc7e
YZ		 7665 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7666 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7667 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7668 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7669 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7670 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7671 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7672 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7673 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7674 r = 0;
7675 goto out;
7676 }
e516cebb
AS		 7677 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7678 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7679 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7680 r = 0;
7681 goto out;
7682 }
db397571
AS		 7683 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7684 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7685 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7686 r = 0;
7687 goto out;
7688 }
f3b138c5
AS		 7689
7690 /*
7691 * KVM_REQ_HV_STIMER has to be processed after
7692 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7693 * depend on the guest clock being up-to-date
7694 */
1f4b34f8
AS		 7695 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7696 kvm_hv_process_stimers(vcpu);
2f52d58c 7697 }
b93463aa 7698
b463a6f7 7699 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7700 ++vcpu->stat.req_event;
66450a21
JK		 7701 kvm_apic_accept_events(vcpu);
7702 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7703 r = 1;
7704 goto out;
7705 }
7706
b6b8a145
JK		 7707 if (inject_pending_event(vcpu, req_int_win) != 0)
7708 req_immediate_exit = true;
321c5658 7709 else {
cc3d967f 7710 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7711 *
cc3d967f
LP		 7712 * SMIs have three cases:
7713 * 1) They can be nested, and then there is nothing to
7714 * do here because RSM will cause a vmexit anyway.
7715 * 2) There is an ISA-specific reason why SMI cannot be
7716 * injected, and the moment when this changes can be
7717 * intercepted.
7718 * 3) Or the SMI can be pending because
7719 * inject_pending_event has completed the injection
7720 * of an IRQ or NMI from the previous vmexit, and
7721 * then we request an immediate exit to inject the
7722 * SMI.
c43203ca
PB		 7723 */
7724 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7725 if (!kvm_x86_ops->enable_smi_window(vcpu))
7726 req_immediate_exit = true;
321c5658
YS		 7727 if (vcpu->arch.nmi_pending)
7728 kvm_x86_ops->enable_nmi_window(vcpu);
7729 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7730 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7731 WARN_ON(vcpu->arch.exception.pending);
321c5658 7732 }
b463a6f7
AK		 7733
7734 if (kvm_lapic_enabled(vcpu)) {
7735 update_cr8_intercept(vcpu);
7736 kvm_lapic_sync_to_vapic(vcpu);
7737 }
7738 }
7739
d8368af8
AK		 7740 r = kvm_mmu_reload(vcpu);
7741 if (unlikely(r)) {
d905c069 7742 goto cancel_injection;
d8368af8
AK		 7743 }
7744
b6c7a5dc
HB		 7745 preempt_disable();
7746
7747 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7748
7749 /*
7750 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7751 * IPI are then delayed after guest entry, which ensures that they
7752 * result in virtual interrupt delivery.
7753 */
7754 local_irq_disable();
6b7e2d09
XG		 7755 vcpu->mode = IN_GUEST_MODE;
7756
01b71917
MT		 7757 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7758
0f127d12 7759 /*
b95234c8 7760 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7761 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7762 *
7763 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7764 * pairs with the memory barrier implicit in pi_test_and_set_on
7765 * (see vmx_deliver_posted_interrupt).
7766 *
7767 * 3) This also orders the write to mode from any reads to the page
7768 * tables done while the VCPU is running. Please see the comment
7769 * in kvm_flush_remote_tlbs.
6b7e2d09 7770 */
01b71917 7771 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7772
b95234c8
PB		 7773 /*
7774 * This handles the case where a posted interrupt was
7775 * notified with kvm_vcpu_kick.
7776 */
fa59cc00
LA		 7777 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7778 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7779
2fa6e1e1 7780 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7781 || need_resched() || signal_pending(current)) {
6b7e2d09 7782 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7783 smp_wmb();
6c142801
AK		 7784 local_irq_enable();
7785 preempt_enable();
01b71917 7786 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7787 r = 1;
d905c069 7788 goto cancel_injection;
6c142801
AK		 7789 }
7790
fc5b7f3b
DM		 7791 kvm_load_guest_xcr0(vcpu);
7792
c43203ca
PB		 7793 if (req_immediate_exit) {
7794 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7795 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7796 }
d6185f20 7797
8b89fe1f 7798 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7799 if (lapic_timer_advance_ns)
7800 wait_lapic_expire(vcpu);
6edaa530 7801 guest_enter_irqoff();
b6c7a5dc 7802
42dbaa5a 7803 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7804 set_debugreg(0, 7);
7805 set_debugreg(vcpu->arch.eff_db[0], 0);
7806 set_debugreg(vcpu->arch.eff_db[1], 1);
7807 set_debugreg(vcpu->arch.eff_db[2], 2);
7808 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7809 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7810 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7811 }
b6c7a5dc 7812
851ba692 7813 kvm_x86_ops->run(vcpu);
b6c7a5dc 7814
c77fb5fe
PB		 7815 /*
7816 * Do this here before restoring debug registers on the host. And
7817 * since we do this before handling the vmexit, a DR access vmexit
7818 * can (a) read the correct value of the debug registers, (b) set
7819 * KVM_DEBUGREG_WONT_EXIT again.
7820 */
7821 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7822 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7823 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7824 kvm_update_dr0123(vcpu);
7825 kvm_update_dr6(vcpu);
7826 kvm_update_dr7(vcpu);
7827 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7828 }
7829
24f1e32c
FW		 7830 /*
7831 * If the guest has used debug registers, at least dr7
7832 * will be disabled while returning to the host.
7833 * If we don't have active breakpoints in the host, we don't
7834 * care about the messed up debug address registers. But if
7835 * we have some of them active, restore the old state.
7836 */
59d8eb53 7837 if (hw_breakpoint_active())
24f1e32c 7838 hw_breakpoint_restore();
42dbaa5a 7839
4ba76538 7840 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7841
6b7e2d09 7842 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7843 smp_wmb();
a547c6db 7844
fc5b7f3b
DM		 7845 kvm_put_guest_xcr0(vcpu);
7846
dd60d217 7847 kvm_before_interrupt(vcpu);
a547c6db 7848 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7849 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7850
7851 ++vcpu->stat.exits;
7852
f2485b3e 7853 guest_exit_irqoff();
b6c7a5dc 7854
f2485b3e 7855 local_irq_enable();
b6c7a5dc
HB		 7856 preempt_enable();
7857
f656ce01 7858 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7859
b6c7a5dc
HB		 7860 /*
7861 * Profile KVM exit RIPs:
7862 */
7863 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7864 unsigned long rip = kvm_rip_read(vcpu);
7865 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7866 }
7867
cc578287
ZA		 7868 if (unlikely(vcpu->arch.tsc_always_catchup))
7869 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7870
5cfb1d5a
MT		 7871 if (vcpu->arch.apic_attention)
7872 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7873
618232e2 7874 vcpu->arch.gpa_available = false;
851ba692 7875 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7876 return r;
7877
7878cancel_injection:
7879 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7880 if (unlikely(vcpu->arch.apic_attention))
7881 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7882out:
7883 return r;
7884}
b6c7a5dc 7885
362c698f
PB		 7886static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7887{
bf9f6ac8
FW		 7888 if (!kvm_arch_vcpu_runnable(vcpu) &&
7889 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7890 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7891 kvm_vcpu_block(vcpu);
7892 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7893
7894 if (kvm_x86_ops->post_block)
7895 kvm_x86_ops->post_block(vcpu);
7896
9c8fd1ba
PB		 7897 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7898 return 1;
7899 }
362c698f
PB		 7900
7901 kvm_apic_accept_events(vcpu);
7902 switch(vcpu->arch.mp_state) {
7903 case KVM_MP_STATE_HALTED:
7904 vcpu->arch.pv.pv_unhalted = false;
7905 vcpu->arch.mp_state =
7906 KVM_MP_STATE_RUNNABLE;
7907 case KVM_MP_STATE_RUNNABLE:
7908 vcpu->arch.apf.halted = false;
7909 break;
7910 case KVM_MP_STATE_INIT_RECEIVED:
7911 break;
7912 default:
7913 return -EINTR;
7914 break;
7915 }
7916 return 1;
7917}
09cec754 7918
5d9bc648
PB		 7919static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7920{
0ad3bed6
PB		 7921 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7922 kvm_x86_ops->check_nested_events(vcpu, false);
7923
5d9bc648
PB		 7924 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7925 !vcpu->arch.apf.halted);
7926}
7927
362c698f 7928static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7929{
7930 int r;
f656ce01 7931 struct kvm *kvm = vcpu->kvm;
d7690175 7932
f656ce01 7933 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 7934 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7935
362c698f 7936 for (;;) {
58f800d5 7937 if (kvm_vcpu_running(vcpu)) {
851ba692 7938 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7939 } else {
362c698f 7940 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7941 }
7942
09cec754
GN		 7943 if (r <= 0)
7944 break;
7945
72875d8a 7946 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7947 if (kvm_cpu_has_pending_timer(vcpu))
7948 kvm_inject_pending_timer_irqs(vcpu);
7949
782d422b
MG		 7950 if (dm_request_for_irq_injection(vcpu) &&
7951 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7952 r = 0;
7953 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7954 ++vcpu->stat.request_irq_exits;
362c698f 7955 break;
09cec754 7956 }
af585b92
GN		 7957
7958 kvm_check_async_pf_completion(vcpu);
7959
09cec754
GN		 7960 if (signal_pending(current)) {
7961 r = -EINTR;
851ba692 7962 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7963 ++vcpu->stat.signal_exits;
362c698f 7964 break;
09cec754
GN		 7965 }
7966 if (need_resched()) {
f656ce01 7967 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7968 cond_resched();
f656ce01 7969 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7970 }
b6c7a5dc
HB		 7971 }
7972
f656ce01 7973 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7974
7975 return r;
7976}
7977
716d51ab
GN		 7978static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7979{
7980 int r;
7981 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 7982 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 7983 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7984 if (r != EMULATE_DONE)
7985 return 0;
7986 return 1;
7987}
7988
7989static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7990{
7991 BUG_ON(!vcpu->arch.pio.count);
7992
7993 return complete_emulated_io(vcpu);
7994}
7995
f78146b0
AK		 7996/*
7997 * Implements the following, as a state machine:
7998 *
7999 * read:
8000 * for each fragment
87da7e66
XG		 8001 * for each mmio piece in the fragment
8002 * write gpa, len
8003 * exit
8004 * copy data
f78146b0
AK		 8005 * execute insn
8006 *
8007 * write:
8008 * for each fragment
87da7e66
XG		 8009 * for each mmio piece in the fragment
8010 * write gpa, len
8011 * copy data
8012 * exit
f78146b0 8013 */
716d51ab 8014static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8015{
8016 struct kvm_run *run = vcpu->run;
f78146b0 8017 struct kvm_mmio_fragment *frag;
87da7e66 8018 unsigned len;
5287f194 8019
716d51ab 8020 BUG_ON(!vcpu->mmio_needed);
5287f194 8021
716d51ab 8022 /* Complete previous fragment */
87da7e66
XG		 8023 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8024 len = min(8u, frag->len);
716d51ab 8025 if (!vcpu->mmio_is_write)
87da7e66
XG		 8026 memcpy(frag->data, run->mmio.data, len);
8027
8028 if (frag->len <= 8) {
8029 /* Switch to the next fragment. */
8030 frag++;
8031 vcpu->mmio_cur_fragment++;
8032 } else {
8033 /* Go forward to the next mmio piece. */
8034 frag->data += len;
8035 frag->gpa += len;
8036 frag->len -= len;
8037 }
8038
a08d3b3b 8039 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8040 vcpu->mmio_needed = 0;
0912c977
PB		 8041
8042 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8043 if (vcpu->mmio_is_write)
716d51ab
GN		 8044 return 1;
8045 vcpu->mmio_read_completed = 1;
8046 return complete_emulated_io(vcpu);
8047 }
87da7e66 8048
716d51ab
GN		 8049 run->exit_reason = KVM_EXIT_MMIO;
8050 run->mmio.phys_addr = frag->gpa;
8051 if (vcpu->mmio_is_write)
87da7e66
XG		 8052 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8053 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8054 run->mmio.is_write = vcpu->mmio_is_write;
8055 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8056 return 0;
5287f194
AK		 8057}
8058
822f312d
SAS		 8059/* Swap (qemu) user FPU context for the guest FPU context. */
8060static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8061{
8062 preempt_disable();
240c35a3 8063 copy_fpregs_to_fpstate(&current->thread.fpu);
822f312d 8064 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8065 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d
SAS		 8066 ~XFEATURE_MASK_PKRU);
8067 preempt_enable();
8068 trace_kvm_fpu(1);
8069}
8070
8071/* When vcpu_run ends, restore user space FPU context. */
8072static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8073{
8074 preempt_disable();
b666a4b6 8075 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
240c35a3 8076 copy_kernel_to_fpregs(&current->thread.fpu.state);
822f312d
SAS		 8077 preempt_enable();
8078 ++vcpu->stat.fpu_reload;
8079 trace_kvm_fpu(0);
8080}
8081
b6c7a5dc
HB		 8082int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8083{
8084 int r;
b6c7a5dc 8085
accb757d 8086 vcpu_load(vcpu);
20b7035c 8087 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8088 kvm_load_guest_fpu(vcpu);
8089
a4535290 8090 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8091 if (kvm_run->immediate_exit) {
8092 r = -EINTR;
8093 goto out;
8094 }
b6c7a5dc 8095 kvm_vcpu_block(vcpu);
66450a21 8096 kvm_apic_accept_events(vcpu);
72875d8a 8097 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8098 r = -EAGAIN;
a0595000
JS		 8099 if (signal_pending(current)) {
8100 r = -EINTR;
8101 vcpu->run->exit_reason = KVM_EXIT_INTR;
8102 ++vcpu->stat.signal_exits;
8103 }
ac9f6dc0 8104 goto out;
b6c7a5dc
HB		 8105 }
8106
01643c51
KH		 8107 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8108 r = -EINVAL;
8109 goto out;
8110 }
8111
8112 if (vcpu->run->kvm_dirty_regs) {
8113 r = sync_regs(vcpu);
8114 if (r != 0)
8115 goto out;
8116 }
8117
b6c7a5dc 8118 /* re-sync apic's tpr */
35754c98 8119 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8120 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8121 r = -EINVAL;
8122 goto out;
8123 }
8124 }
b6c7a5dc 8125
716d51ab
GN		 8126 if (unlikely(vcpu->arch.complete_userspace_io)) {
8127 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8128 vcpu->arch.complete_userspace_io = NULL;
8129 r = cui(vcpu);
8130 if (r <= 0)
5663d8f9 8131 goto out;
716d51ab
GN		 8132 } else
8133 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8134
460df4c1
PB		 8135 if (kvm_run->immediate_exit)
8136 r = -EINTR;
8137 else
8138 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8139
8140out:
5663d8f9 8141 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8142 if (vcpu->run->kvm_valid_regs)
8143 store_regs(vcpu);
f1d86e46 8144 post_kvm_run_save(vcpu);
20b7035c 8145 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8146
accb757d 8147 vcpu_put(vcpu);
b6c7a5dc
HB		 8148 return r;
8149}
8150
01643c51 8151static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8152{
7ae441ea
GN		 8153 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8154 /*
8155 * We are here if userspace calls get_regs() in the middle of
8156 * instruction emulation. Registers state needs to be copied
4a969980 8157 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8158 * that usually, but some bad designed PV devices (vmware
8159 * backdoor interface) need this to work
8160 */
dd856efa 8161 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8162 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8163 }
5fdbf976
MT		 8164 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
8165 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
8166 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
8167 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
8168 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
8169 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
8170 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8171 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 8172#ifdef CONFIG_X86_64
5fdbf976
MT		 8173 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
8174 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
8175 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
8176 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
8177 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
8178 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8179 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8180 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 8181#endif
8182
5fdbf976 8183 regs->rip = kvm_rip_read(vcpu);
91586a3b 8184 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8185}
b6c7a5dc 8186
01643c51
KH		 8187int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8188{
8189 vcpu_load(vcpu);
8190 __get_regs(vcpu, regs);
1fc9b76b 8191 vcpu_put(vcpu);
b6c7a5dc
HB		 8192 return 0;
8193}
8194
01643c51 8195static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8196{
7ae441ea
GN		 8197 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8198 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8199
5fdbf976
MT		 8200 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8201 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8202 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8203 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8204 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8205 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8206 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8207 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 8208#ifdef CONFIG_X86_64
5fdbf976
MT		 8209 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8210 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8211 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8212 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8213 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8214 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8215 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8216 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 8217#endif
8218
5fdbf976 8219 kvm_rip_write(vcpu, regs->rip);
d73235d1 8220 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8221
b4f14abd
JK		 8222 vcpu->arch.exception.pending = false;
8223
3842d135 8224 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8225}
3842d135 8226
01643c51
KH		 8227int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8228{
8229 vcpu_load(vcpu);
8230 __set_regs(vcpu, regs);
875656fe 8231 vcpu_put(vcpu);
b6c7a5dc
HB		 8232 return 0;
8233}
8234
b6c7a5dc
HB		 8235void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8236{
8237 struct kvm_segment cs;
8238
3e6e0aab 8239 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8240 *db = cs.db;
8241 *l = cs.l;
8242}
8243EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8244
01643c51 8245static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8246{
89a27f4d 8247 struct desc_ptr dt;
b6c7a5dc 8248
3e6e0aab
GT		 8249 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8250 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8251 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8252 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8253 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8254 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8255
3e6e0aab
GT		 8256 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8257 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8258
8259 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8260 sregs->idt.limit = dt.size;
8261 sregs->idt.base = dt.address;
b6c7a5dc 8262 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8263 sregs->gdt.limit = dt.size;
8264 sregs->gdt.base = dt.address;
b6c7a5dc 8265
4d4ec087 8266 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8267 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8268 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8269 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8270 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8271 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8272 sregs->apic_base = kvm_get_apic_base(vcpu);
8273
0e96f31e 8274 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8275
04140b41 8276 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8277 set_bit(vcpu->arch.interrupt.nr,
8278 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8279}
16d7a191 8280
01643c51
KH		 8281int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8282 struct kvm_sregs *sregs)
8283{
8284 vcpu_load(vcpu);
8285 __get_sregs(vcpu, sregs);
bcdec41c 8286 vcpu_put(vcpu);
b6c7a5dc
HB		 8287 return 0;
8288}
8289
62d9f0db
MT		 8290int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8291 struct kvm_mp_state *mp_state)
8292{
fd232561
CD		 8293 vcpu_load(vcpu);
8294
66450a21 8295 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8296 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8297 vcpu->arch.pv.pv_unhalted)
8298 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8299 else
8300 mp_state->mp_state = vcpu->arch.mp_state;
8301
fd232561 8302 vcpu_put(vcpu);
62d9f0db
MT		 8303 return 0;
8304}
8305
8306int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8307 struct kvm_mp_state *mp_state)
8308{
e83dff5e
CD		 8309 int ret = -EINVAL;
8310
8311 vcpu_load(vcpu);
8312
bce87cce 8313 if (!lapic_in_kernel(vcpu) &&
66450a21 8314 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8315 goto out;
66450a21 8316
28bf2888
DH		 8317 /* INITs are latched while in SMM */
8318 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8319 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8320 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8321 goto out;
28bf2888 8322
66450a21
JK		 8323 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8324 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8325 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8326 } else
8327 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8328 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8329
8330 ret = 0;
8331out:
8332 vcpu_put(vcpu);
8333 return ret;
62d9f0db
MT		 8334}
8335
7f3d35fd
KW		 8336int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8337 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8338{
9d74191a 8339 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8340 int ret;
e01c2426 8341
8ec4722d 8342 init_emulate_ctxt(vcpu);
c697518a 8343
7f3d35fd 8344 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8345 has_error_code, error_code);
c697518a 8346
c697518a 8347 if (ret)
19d04437 8348 return EMULATE_FAIL;
37817f29 8349
9d74191a
TY		 8350 kvm_rip_write(vcpu, ctxt->eip);
8351 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8352 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8353 return EMULATE_DONE;
37817f29
IE		 8354}
8355EXPORT_SYMBOL_GPL(kvm_task_switch);
8356
3140c156 8357static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8358{
74fec5b9
TL		 8359 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8360 (sregs->cr4 & X86_CR4_OSXSAVE))
8361 return -EINVAL;
8362
37b95951 8363 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8364 /*
8365 * When EFER.LME and CR0.PG are set, the processor is in
8366 * 64-bit mode (though maybe in a 32-bit code segment).
8367 * CR4.PAE and EFER.LMA must be set.
8368 */
37b95951 8369 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8370 || !(sregs->efer & EFER_LMA))
8371 return -EINVAL;
8372 } else {
8373 /*
8374 * Not in 64-bit mode: EFER.LMA is clear and the code
8375 * segment cannot be 64-bit.
8376 */
8377 if (sregs->efer & EFER_LMA || sregs->cs.l)
8378 return -EINVAL;
8379 }
8380
8381 return 0;
8382}
8383
01643c51 8384static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8385{
58cb628d 8386 struct msr_data apic_base_msr;
b6c7a5dc 8387 int mmu_reset_needed = 0;
c4d21882 8388 int cpuid_update_needed = 0;
63f42e02 8389 int pending_vec, max_bits, idx;
89a27f4d 8390 struct desc_ptr dt;
b4ef9d4e
CD		 8391 int ret = -EINVAL;
8392
f2981033 8393 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8394 goto out;
f2981033 8395
d3802286
JM		 8396 apic_base_msr.data = sregs->apic_base;
8397 apic_base_msr.host_initiated = true;
8398 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8399 goto out;
6d1068b3 8400
89a27f4d
GN		 8401 dt.size = sregs->idt.limit;
8402 dt.address = sregs->idt.base;
b6c7a5dc 8403 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8404 dt.size = sregs->gdt.limit;
8405 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8406 kvm_x86_ops->set_gdt(vcpu, &dt);
8407
ad312c7c 8408 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8409 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8410 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8411 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8412
2d3ad1f4 8413 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8414
f6801dff 8415 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8416 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8417
4d4ec087 8418 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8419 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8420 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8421
fc78f519 8422 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8423 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8424 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8425 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8426 if (cpuid_update_needed)
00b27a3e 8427 kvm_update_cpuid(vcpu);
63f42e02
XG		 8428
8429 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8430 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8431 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8432 mmu_reset_needed = 1;
8433 }
63f42e02 8434 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8435
8436 if (mmu_reset_needed)
8437 kvm_mmu_reset_context(vcpu);
8438
a50abc3b 8439 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8440 pending_vec = find_first_bit(
8441 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8442 if (pending_vec < max_bits) {
66fd3f7f 8443 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8444 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8445 }
8446
3e6e0aab
GT		 8447 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8448 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8449 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8450 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8451 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8452 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8453
3e6e0aab
GT		 8454 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8455 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8456
5f0269f5
ME		 8457 update_cr8_intercept(vcpu);
8458
9c3e4aab 8459 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8460 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8461 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8462 !is_protmode(vcpu))
9c3e4aab
MT		 8463 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8464
3842d135
AK		 8465 kvm_make_request(KVM_REQ_EVENT, vcpu);
8466
b4ef9d4e
CD		 8467 ret = 0;
8468out:
01643c51
KH		 8469 return ret;
8470}
8471
8472int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8473 struct kvm_sregs *sregs)
8474{
8475 int ret;
8476
8477 vcpu_load(vcpu);
8478 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8479 vcpu_put(vcpu);
8480 return ret;
b6c7a5dc
HB		 8481}
8482
d0bfb940
JK		 8483int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8484 struct kvm_guest_debug *dbg)
b6c7a5dc 8485{
355be0b9 8486 unsigned long rflags;
ae675ef0 8487 int i, r;
b6c7a5dc 8488
66b56562
CD		 8489 vcpu_load(vcpu);
8490
4f926bf2
JK		 8491 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8492 r = -EBUSY;
8493 if (vcpu->arch.exception.pending)
2122ff5e 8494 goto out;
4f926bf2
JK		 8495 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8496 kvm_queue_exception(vcpu, DB_VECTOR);
8497 else
8498 kvm_queue_exception(vcpu, BP_VECTOR);
8499 }
8500
91586a3b
JK		 8501 /*
8502 * Read rflags as long as potentially injected trace flags are still
8503 * filtered out.
8504 */
8505 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8506
8507 vcpu->guest_debug = dbg->control;
8508 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8509 vcpu->guest_debug = 0;
8510
8511 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8512 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8513 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8514 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8515 } else {
8516 for (i = 0; i < KVM_NR_DB_REGS; i++)
8517 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8518 }
c8639010 8519 kvm_update_dr7(vcpu);
ae675ef0 8520
f92653ee
JK		 8521 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8522 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8523 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8524
91586a3b
JK		 8525 /*
8526 * Trigger an rflags update that will inject or remove the trace
8527 * flags.
8528 */
8529 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8530
a96036b8 8531 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8532
4f926bf2 8533 r = 0;
d0bfb940 8534
2122ff5e 8535out:
66b56562 8536 vcpu_put(vcpu);
b6c7a5dc
HB		 8537 return r;
8538}
8539
8b006791
ZX		 8540/*
8541 * Translate a guest virtual address to a guest physical address.
8542 */
8543int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8544 struct kvm_translation *tr)
8545{
8546 unsigned long vaddr = tr->linear_address;
8547 gpa_t gpa;
f656ce01 8548 int idx;
8b006791 8549
1da5b61d
CD		 8550 vcpu_load(vcpu);
8551
f656ce01 8552 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8553 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8554 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8555 tr->physical_address = gpa;
8556 tr->valid = gpa != UNMAPPED_GVA;
8557 tr->writeable = 1;
8558 tr->usermode = 0;
8b006791 8559
1da5b61d 8560 vcpu_put(vcpu);
8b006791
ZX		 8561 return 0;
8562}
8563
d0752060
HB		 8564int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8565{
1393123e 8566 struct fxregs_state *fxsave;
d0752060 8567
1393123e 8568 vcpu_load(vcpu);
d0752060 8569
b666a4b6 8570 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8571 memcpy(fpu->fpr, fxsave->st_space, 128);
8572 fpu->fcw = fxsave->cwd;
8573 fpu->fsw = fxsave->swd;
8574 fpu->ftwx = fxsave->twd;
8575 fpu->last_opcode = fxsave->fop;
8576 fpu->last_ip = fxsave->rip;
8577 fpu->last_dp = fxsave->rdp;
0e96f31e 8578 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8579
1393123e 8580 vcpu_put(vcpu);
d0752060
HB		 8581 return 0;
8582}
8583
8584int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8585{
6a96bc7f
CD		 8586 struct fxregs_state *fxsave;
8587
8588 vcpu_load(vcpu);
8589
b666a4b6 8590 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8591
d0752060
HB		 8592 memcpy(fxsave->st_space, fpu->fpr, 128);
8593 fxsave->cwd = fpu->fcw;
8594 fxsave->swd = fpu->fsw;
8595 fxsave->twd = fpu->ftwx;
8596 fxsave->fop = fpu->last_opcode;
8597 fxsave->rip = fpu->last_ip;
8598 fxsave->rdp = fpu->last_dp;
0e96f31e 8599 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8600
6a96bc7f 8601 vcpu_put(vcpu);
d0752060
HB		 8602 return 0;
8603}
8604
01643c51
KH		 8605static void store_regs(struct kvm_vcpu *vcpu)
8606{
8607 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8608
8609 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8610 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8611
8612 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8613 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8614
8615 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8616 kvm_vcpu_ioctl_x86_get_vcpu_events(
8617 vcpu, &vcpu->run->s.regs.events);
8618}
8619
8620static int sync_regs(struct kvm_vcpu *vcpu)
8621{
8622 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8623 return -EINVAL;
8624
8625 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8626 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8627 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8628 }
8629 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8630 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8631 return -EINVAL;
8632 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8633 }
8634 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8635 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8636 vcpu, &vcpu->run->s.regs.events))
8637 return -EINVAL;
8638 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8639 }
8640
8641 return 0;
8642}
8643
0ee6a517 8644static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8645{
b666a4b6 8646 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 8647 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 8648 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 8649 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8650
2acf923e
DC		 8651 /*
8652 * Ensure guest xcr0 is valid for loading
8653 */
d91cab78 8654 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8655
ad312c7c 8656 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8657}
d0752060 8658
e9b11c17
ZX		 8659void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8660{
bd768e14
IY		 8661 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8662
12f9a48f 8663 kvmclock_reset(vcpu);
7f1ea208 8664
e9b11c17 8665 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8666 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8667}
8668
8669struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8670 unsigned int id)
8671{
c447e76b
LL		 8672 struct kvm_vcpu *vcpu;
8673
b0c39dc6 8674 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8675 printk_once(KERN_WARNING
8676 "kvm: SMP vm created on host with unstable TSC; "
8677 "guest TSC will not be reliable\n");
c447e76b
LL		 8678
8679 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8680
c447e76b 8681 return vcpu;
26e5215f 8682}
e9b11c17 8683
26e5215f
AK		 8684int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8685{
e53d88af 8686 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 8687 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8688 vcpu_load(vcpu);
d28bc9dd 8689 kvm_vcpu_reset(vcpu, false);
e1732991 8690 kvm_init_mmu(vcpu, false);
e9b11c17 8691 vcpu_put(vcpu);
ec7660cc 8692 return 0;
e9b11c17
ZX		 8693}
8694
31928aa5 8695void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8696{
8fe8ab46 8697 struct msr_data msr;
332967a3 8698 struct kvm *kvm = vcpu->kvm;
42897d86 8699
d3457c87
RK		 8700 kvm_hv_vcpu_postcreate(vcpu);
8701
ec7660cc 8702 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8703 return;
ec7660cc 8704 vcpu_load(vcpu);
8fe8ab46
WA		 8705 msr.data = 0x0;
8706 msr.index = MSR_IA32_TSC;
8707 msr.host_initiated = true;
8708 kvm_write_tsc(vcpu, &msr);
42897d86 8709 vcpu_put(vcpu);
ec7660cc 8710 mutex_unlock(&vcpu->mutex);
42897d86 8711
630994b3
MT		 8712 if (!kvmclock_periodic_sync)
8713 return;
8714
332967a3
AJ		 8715 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8716 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8717}
8718
d40ccc62 8719void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8720{
344d9588
GN		 8721 vcpu->arch.apf.msr_val = 0;
8722
ec7660cc 8723 vcpu_load(vcpu);
e9b11c17
ZX		 8724 kvm_mmu_unload(vcpu);
8725 vcpu_put(vcpu);
8726
8727 kvm_x86_ops->vcpu_free(vcpu);
8728}
8729
d28bc9dd 8730void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8731{
b7e31be3
RK		 8732 kvm_lapic_reset(vcpu, init_event);
8733
e69fab5d
PB		 8734 vcpu->arch.hflags = 0;
8735
c43203ca 8736 vcpu->arch.smi_pending = 0;
52797bf9 8737 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8738 atomic_set(&vcpu->arch.nmi_queued, 0);
8739 vcpu->arch.nmi_pending = 0;
448fa4a9 8740 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8741 kvm_clear_interrupt_queue(vcpu);
8742 kvm_clear_exception_queue(vcpu);
664f8e26 8743 vcpu->arch.exception.pending = false;
448fa4a9 8744
42dbaa5a 8745 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8746 kvm_update_dr0123(vcpu);
6f43ed01 8747 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8748 kvm_update_dr6(vcpu);
42dbaa5a 8749 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8750 kvm_update_dr7(vcpu);
42dbaa5a 8751
1119022c
NA		 8752 vcpu->arch.cr2 = 0;
8753
3842d135 8754 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8755 vcpu->arch.apf.msr_val = 0;
c9aaa895 8756 vcpu->arch.st.msr_val = 0;
3842d135 8757
12f9a48f
GC		 8758 kvmclock_reset(vcpu);
8759
af585b92
GN		 8760 kvm_clear_async_pf_completion_queue(vcpu);
8761 kvm_async_pf_hash_reset(vcpu);
8762 vcpu->arch.apf.halted = false;
3842d135 8763
a554d207
WL		 8764 if (kvm_mpx_supported()) {
8765 void *mpx_state_buffer;
8766
8767 /*
8768 * To avoid have the INIT path from kvm_apic_has_events() that be
8769 * called with loaded FPU and does not let userspace fix the state.
8770 */
f775b13e
RR		 8771 if (init_event)
8772 kvm_put_guest_fpu(vcpu);
b666a4b6 8773 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
a554d207
WL		 8774 XFEATURE_MASK_BNDREGS);
8775 if (mpx_state_buffer)
8776 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 8777 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
a554d207
WL		 8778 XFEATURE_MASK_BNDCSR);
8779 if (mpx_state_buffer)
8780 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8781 if (init_event)
8782 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8783 }
8784
64d60670 8785 if (!init_event) {
d28bc9dd 8786 kvm_pmu_reset(vcpu);
64d60670 8787 vcpu->arch.smbase = 0x30000;
db2336a8 8788
db2336a8 8789 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8790
8791 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8792 }
f5132b01 8793
66f7b72e
JS		 8794 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8795 vcpu->arch.regs_avail = ~0;
8796 vcpu->arch.regs_dirty = ~0;
8797
a554d207
WL		 8798 vcpu->arch.ia32_xss = 0;
8799
d28bc9dd 8800 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8801}
8802
2b4a273b 8803void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8804{
8805 struct kvm_segment cs;
8806
8807 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8808 cs.selector = vector << 8;
8809 cs.base = vector << 12;
8810 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8811 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8812}
8813
13a34e06 8814int kvm_arch_hardware_enable(void)
e9b11c17 8815{
ca84d1a2
ZA		 8816 struct kvm *kvm;
8817 struct kvm_vcpu *vcpu;
8818 int i;
0dd6a6ed
ZA		 8819 int ret;
8820 u64 local_tsc;
8821 u64 max_tsc = 0;
8822 bool stable, backwards_tsc = false;
18863bdd
AK		 8823
8824 kvm_shared_msr_cpu_online();
13a34e06 8825 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8826 if (ret != 0)
8827 return ret;
8828
4ea1636b 8829 local_tsc = rdtsc();
b0c39dc6 8830 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8831 list_for_each_entry(kvm, &vm_list, vm_list) {
8832 kvm_for_each_vcpu(i, vcpu, kvm) {
8833 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8834 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8835 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8836 backwards_tsc = true;
8837 if (vcpu->arch.last_host_tsc > max_tsc)
8838 max_tsc = vcpu->arch.last_host_tsc;
8839 }
8840 }
8841 }
8842
8843 /*
8844 * Sometimes, even reliable TSCs go backwards. This happens on
8845 * platforms that reset TSC during suspend or hibernate actions, but
8846 * maintain synchronization. We must compensate. Fortunately, we can
8847 * detect that condition here, which happens early in CPU bringup,
8848 * before any KVM threads can be running. Unfortunately, we can't
8849 * bring the TSCs fully up to date with real time, as we aren't yet far
8850 * enough into CPU bringup that we know how much real time has actually
108b249c 8851 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8852 * variables that haven't been updated yet.
8853 *
8854 * So we simply find the maximum observed TSC above, then record the
8855 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8856 * the adjustment will be applied. Note that we accumulate
8857 * adjustments, in case multiple suspend cycles happen before some VCPU
8858 * gets a chance to run again. In the event that no KVM threads get a
8859 * chance to run, we will miss the entire elapsed period, as we'll have
8860 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8861 * loose cycle time. This isn't too big a deal, since the loss will be
8862 * uniform across all VCPUs (not to mention the scenario is extremely
8863 * unlikely). It is possible that a second hibernate recovery happens
8864 * much faster than a first, causing the observed TSC here to be
8865 * smaller; this would require additional padding adjustment, which is
8866 * why we set last_host_tsc to the local tsc observed here.
8867 *
8868 * N.B. - this code below runs only on platforms with reliable TSC,
8869 * as that is the only way backwards_tsc is set above. Also note
8870 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8871 * have the same delta_cyc adjustment applied if backwards_tsc
8872 * is detected. Note further, this adjustment is only done once,
8873 * as we reset last_host_tsc on all VCPUs to stop this from being
8874 * called multiple times (one for each physical CPU bringup).
8875 *
4a969980 8876 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8877 * will be compensated by the logic in vcpu_load, which sets the TSC to
8878 * catchup mode. This will catchup all VCPUs to real time, but cannot
8879 * guarantee that they stay in perfect synchronization.
8880 */
8881 if (backwards_tsc) {
8882 u64 delta_cyc = max_tsc - local_tsc;
8883 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8884 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8885 kvm_for_each_vcpu(i, vcpu, kvm) {
8886 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8887 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8888 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8889 }
8890
8891 /*
8892 * We have to disable TSC offset matching.. if you were
8893 * booting a VM while issuing an S4 host suspend....
8894 * you may have some problem. Solving this issue is
8895 * left as an exercise to the reader.
8896 */
8897 kvm->arch.last_tsc_nsec = 0;
8898 kvm->arch.last_tsc_write = 0;
8899 }
8900
8901 }
8902 return 0;
e9b11c17
ZX		 8903}
8904
13a34e06 8905void kvm_arch_hardware_disable(void)
e9b11c17 8906{
13a34e06
RK		 8907 kvm_x86_ops->hardware_disable();
8908 drop_user_return_notifiers();
e9b11c17
ZX		 8909}
8910
8911int kvm_arch_hardware_setup(void)
8912{
9e9c3fe4
NA		 8913 int r;
8914
8915 r = kvm_x86_ops->hardware_setup();
8916 if (r != 0)
8917 return r;
8918
35181e86
HZ		 8919 if (kvm_has_tsc_control) {
8920 /*
8921 * Make sure the user can only configure tsc_khz values that
8922 * fit into a signed integer.
273ba457 8923 * A min value is not calculated because it will always
35181e86
HZ		 8924 * be 1 on all machines.
8925 */
8926 u64 max = min(0x7fffffffULL,
8927 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8928 kvm_max_guest_tsc_khz = max;
8929
ad721883 8930 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8931 }
ad721883 8932
9e9c3fe4
NA		 8933 kvm_init_msr_list();
8934 return 0;
e9b11c17
ZX		 8935}
8936
8937void kvm_arch_hardware_unsetup(void)
8938{
8939 kvm_x86_ops->hardware_unsetup();
8940}
8941
8942void kvm_arch_check_processor_compat(void *rtn)
8943{
8944 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8945}
8946
8947bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8948{
8949 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8950}
8951EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8952
8953bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8954{
8955 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8956}
8957
54e9818f 8958struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8959EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8960
e9b11c17
ZX		 8961int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8962{
8963 struct page *page;
e9b11c17
ZX		 8964 int r;
8965
b2a05fef 8966 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8967 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8968 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8969 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8970 else
a4535290 8971 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8972
8973 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8974 if (!page) {
8975 r = -ENOMEM;
8976 goto fail;
8977 }
ad312c7c 8978 vcpu->arch.pio_data = page_address(page);
e9b11c17 8979
cc578287 8980 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8981
e9b11c17
ZX		 8982 r = kvm_mmu_create(vcpu);
8983 if (r < 0)
8984 goto fail_free_pio_data;
8985
26de7988 8986 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8987 r = kvm_create_lapic(vcpu);
8988 if (r < 0)
8989 goto fail_mmu_destroy;
54e9818f
GN		 8990 } else
8991 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8992
890ca9ae
HY		 8993 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8994 GFP_KERNEL);
8995 if (!vcpu->arch.mce_banks) {
8996 r = -ENOMEM;
443c39bc 8997 goto fail_free_lapic;
890ca9ae
HY		 8998 }
8999 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9000
f1797359
WY		 9001 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
9002 r = -ENOMEM;
f5f48ee1 9003 goto fail_free_mce_banks;
f1797359 9004 }
f5f48ee1 9005
0ee6a517 9006 fx_init(vcpu);
66f7b72e 9007
4344ee98 9008 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9009
5a4f55cd
EK		 9010 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9011
74545705
RK		 9012 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9013
af585b92 9014 kvm_async_pf_hash_reset(vcpu);
f5132b01 9015 kvm_pmu_init(vcpu);
af585b92 9016
1c1a9ce9 9017 vcpu->arch.pending_external_vector = -1;
de63ad4c 9018 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9019
5c919412
AS		 9020 kvm_hv_vcpu_init(vcpu);
9021
e9b11c17 9022 return 0;
0ee6a517 9023
f5f48ee1
SY		 9024fail_free_mce_banks:
9025 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9026fail_free_lapic:
9027 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9028fail_mmu_destroy:
9029 kvm_mmu_destroy(vcpu);
9030fail_free_pio_data:
ad312c7c 9031 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9032fail:
9033 return r;
9034}
9035
9036void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9037{
f656ce01
MT		 9038 int idx;
9039
1f4b34f8 9040 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9041 kvm_pmu_destroy(vcpu);
36cb93fd 9042 kfree(vcpu->arch.mce_banks);
e9b11c17 9043 kvm_free_lapic(vcpu);
f656ce01 9044 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9045 kvm_mmu_destroy(vcpu);
f656ce01 9046 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9047 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9048 if (!lapic_in_kernel(vcpu))
54e9818f 9049 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9050}
d19a9cd2 9051
e790d9ef
RK		 9052void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9053{
c595ceee 9054 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9055 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9056}
9057
e08b9637 9058int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9059{
e08b9637
CO		 9060 if (type)
9061 return -EINVAL;
9062
6ef768fa 9063 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9064 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 9065 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 9066 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9067 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9068
5550af4d
SY		 9069 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9070 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9071 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9072 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9073 &kvm->arch.irq_sources_bitmap);
5550af4d 9074
038f8c11 9075 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9076 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9077 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9078
108b249c 9079 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 9080 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9081
6fbbde9a
DS		 9082 kvm->arch.guest_can_read_msr_platform_info = true;
9083
7e44e449 9084 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9085 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9086
cbc0236a 9087 kvm_hv_init_vm(kvm);
0eb05bf2 9088 kvm_page_track_init(kvm);
13d268ca 9089 kvm_mmu_init_vm(kvm);
0eb05bf2 9090
03543133
SS		 9091 if (kvm_x86_ops->vm_init)
9092 return kvm_x86_ops->vm_init(kvm);
9093
d89f5eff 9094 return 0;
d19a9cd2
ZX		 9095}
9096
9097static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9098{
ec7660cc 9099 vcpu_load(vcpu);
d19a9cd2
ZX		 9100 kvm_mmu_unload(vcpu);
9101 vcpu_put(vcpu);
9102}
9103
9104static void kvm_free_vcpus(struct kvm *kvm)
9105{
9106 unsigned int i;
988a2cae 9107 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9108
9109 /*
9110 * Unpin any mmu pages first.
9111 */
af585b92
GN		 9112 kvm_for_each_vcpu(i, vcpu, kvm) {
9113 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9114 kvm_unload_vcpu_mmu(vcpu);
af585b92 9115 }
988a2cae
GN		 9116 kvm_for_each_vcpu(i, vcpu, kvm)
9117 kvm_arch_vcpu_free(vcpu);
9118
9119 mutex_lock(&kvm->lock);
9120 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9121 kvm->vcpus[i] = NULL;
d19a9cd2 9122
988a2cae
GN		 9123 atomic_set(&kvm->online_vcpus, 0);
9124 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9125}
9126
ad8ba2cd
SY		 9127void kvm_arch_sync_events(struct kvm *kvm)
9128{
332967a3 9129 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9130 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9131 kvm_free_pit(kvm);
ad8ba2cd
SY		 9132}
9133
1d8007bd 9134int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9135{
9136 int i, r;
25188b99 9137 unsigned long hva;
f0d648bd
PB		 9138 struct kvm_memslots *slots = kvm_memslots(kvm);
9139 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9140
9141 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9142 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9143 return -EINVAL;
9da0e4d5 9144
f0d648bd
PB		 9145 slot = id_to_memslot(slots, id);
9146 if (size) {
b21629da 9147 if (slot->npages)
f0d648bd
PB		 9148 return -EEXIST;
9149
9150 /*
9151 * MAP_SHARED to prevent internal slot pages from being moved
9152 * by fork()/COW.
9153 */
9154 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9155 MAP_SHARED | MAP_ANONYMOUS, 0);
9156 if (IS_ERR((void *)hva))
9157 return PTR_ERR((void *)hva);
9158 } else {
9159 if (!slot->npages)
9160 return 0;
9161
9162 hva = 0;
9163 }
9164
9165 old = *slot;
9da0e4d5 9166 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9167 struct kvm_userspace_memory_region m;
9da0e4d5 9168
1d8007bd
PB		 9169 m.slot = id | (i << 16);
9170 m.flags = 0;
9171 m.guest_phys_addr = gpa;
f0d648bd 9172 m.userspace_addr = hva;
1d8007bd 9173 m.memory_size = size;
9da0e4d5
PB		 9174 r = __kvm_set_memory_region(kvm, &m);
9175 if (r < 0)
9176 return r;
9177 }
9178
103c763c
EB		 9179 if (!size)
9180 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9181
9da0e4d5
PB		 9182 return 0;
9183}
9184EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9185
1d8007bd 9186int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9187{
9188 int r;
9189
9190 mutex_lock(&kvm->slots_lock);
1d8007bd 9191 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9192 mutex_unlock(&kvm->slots_lock);
9193
9194 return r;
9195}
9196EXPORT_SYMBOL_GPL(x86_set_memory_region);
9197
d19a9cd2
ZX		 9198void kvm_arch_destroy_vm(struct kvm *kvm)
9199{
27469d29
AH		 9200 if (current->mm == kvm->mm) {
9201 /*
9202 * Free memory regions allocated on behalf of userspace,
9203 * unless the the memory map has changed due to process exit
9204 * or fd copying.
9205 */
1d8007bd
PB		 9206 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9207 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9208 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9209 }
03543133
SS		 9210 if (kvm_x86_ops->vm_destroy)
9211 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9212 kvm_pic_destroy(kvm);
9213 kvm_ioapic_destroy(kvm);
d19a9cd2 9214 kvm_free_vcpus(kvm);
af1bae54 9215 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9216 kvm_mmu_uninit_vm(kvm);
2beb6dad 9217 kvm_page_track_cleanup(kvm);
cbc0236a 9218 kvm_hv_destroy_vm(kvm);
d19a9cd2 9219}
0de10343 9220
5587027c 9221void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9222 struct kvm_memory_slot *dont)
9223{
9224 int i;
9225
d89cc617
TY		 9226 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9227 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9228 kvfree(free->arch.rmap[i]);
d89cc617 9229 free->arch.rmap[i] = NULL;
77d11309 9230 }
d89cc617
TY		 9231 if (i == 0)
9232 continue;
9233
9234 if (!dont || free->arch.lpage_info[i - 1] !=
9235 dont->arch.lpage_info[i - 1]) {
548ef284 9236 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9237 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9238 }
9239 }
21ebbeda
XG		 9240
9241 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9242}
9243
5587027c
AK		 9244int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9245 unsigned long npages)
db3fe4eb
TY		 9246{
9247 int i;
9248
d89cc617 9249 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9250 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9251 unsigned long ugfn;
9252 int lpages;
d89cc617 9253 int level = i + 1;
db3fe4eb
TY		 9254
9255 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9256 slot->base_gfn, level) + 1;
9257
d89cc617 9258 slot->arch.rmap[i] =
778e1cdd
KC		 9259 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9260 GFP_KERNEL);
d89cc617 9261 if (!slot->arch.rmap[i])
77d11309 9262 goto out_free;
d89cc617
TY		 9263 if (i == 0)
9264 continue;
77d11309 9265
778e1cdd 9266 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 9267 if (!linfo)
db3fe4eb
TY		 9268 goto out_free;
9269
92f94f1e
XG		 9270 slot->arch.lpage_info[i - 1] = linfo;
9271
db3fe4eb 9272 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9273 linfo[0].disallow_lpage = 1;
db3fe4eb 9274 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9275 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9276 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9277 /*
9278 * If the gfn and userspace address are not aligned wrt each
9279 * other, or if explicitly asked to, disable large page
9280 * support for this slot
9281 */
9282 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9283 !kvm_largepages_enabled()) {
9284 unsigned long j;
9285
9286 for (j = 0; j < lpages; ++j)
92f94f1e 9287 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9288 }
9289 }
9290
21ebbeda
XG		 9291 if (kvm_page_track_create_memslot(slot, npages))
9292 goto out_free;
9293
db3fe4eb
TY		 9294 return 0;
9295
9296out_free:
d89cc617 9297 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9298 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9299 slot->arch.rmap[i] = NULL;
9300 if (i == 0)
9301 continue;
9302
548ef284 9303 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9304 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9305 }
9306 return -ENOMEM;
9307}
9308
15f46015 9309void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 9310{
e6dff7d1
TY		 9311 /*
9312 * memslots->generation has been incremented.
9313 * mmio generation may have reached its maximum value.
9314 */
54bf36aa 9315 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 9316}
9317
f7784b8e
MT		 9318int kvm_arch_prepare_memory_region(struct kvm *kvm,
9319 struct kvm_memory_slot *memslot,
09170a49 9320 const struct kvm_userspace_memory_region *mem,
7b6195a9 9321 enum kvm_mr_change change)
0de10343 9322{
f7784b8e
MT		 9323 return 0;
9324}
9325
88178fd4
KH		 9326static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9327 struct kvm_memory_slot *new)
9328{
9329 /* Still write protect RO slot */
9330 if (new->flags & KVM_MEM_READONLY) {
9331 kvm_mmu_slot_remove_write_access(kvm, new);
9332 return;
9333 }
9334
9335 /*
9336 * Call kvm_x86_ops dirty logging hooks when they are valid.
9337 *
9338 * kvm_x86_ops->slot_disable_log_dirty is called when:
9339 *
9340 * - KVM_MR_CREATE with dirty logging is disabled
9341 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9342 *
9343 * The reason is, in case of PML, we need to set D-bit for any slots
9344 * with dirty logging disabled in order to eliminate unnecessary GPA
9345 * logging in PML buffer (and potential PML buffer full VMEXT). This
9346 * guarantees leaving PML enabled during guest's lifetime won't have
9347 * any additonal overhead from PML when guest is running with dirty
9348 * logging disabled for memory slots.
9349 *
9350 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9351 * to dirty logging mode.
9352 *
9353 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9354 *
9355 * In case of write protect:
9356 *
9357 * Write protect all pages for dirty logging.
9358 *
9359 * All the sptes including the large sptes which point to this
9360 * slot are set to readonly. We can not create any new large
9361 * spte on this slot until the end of the logging.
9362 *
9363 * See the comments in fast_page_fault().
9364 */
9365 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9366 if (kvm_x86_ops->slot_enable_log_dirty)
9367 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9368 else
9369 kvm_mmu_slot_remove_write_access(kvm, new);
9370 } else {
9371 if (kvm_x86_ops->slot_disable_log_dirty)
9372 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9373 }
9374}
9375
f7784b8e 9376void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9377 const struct kvm_userspace_memory_region *mem,
8482644a 9378 const struct kvm_memory_slot *old,
f36f3f28 9379 const struct kvm_memory_slot *new,
8482644a 9380 enum kvm_mr_change change)
f7784b8e 9381{
8482644a 9382 int nr_mmu_pages = 0;
f7784b8e 9383
48c0e4e9
XG		 9384 if (!kvm->arch.n_requested_mmu_pages)
9385 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9386
48c0e4e9 9387 if (nr_mmu_pages)
0de10343 9388 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9389
3ea3b7fa
WL		 9390 /*
9391 * Dirty logging tracks sptes in 4k granularity, meaning that large
9392 * sptes have to be split. If live migration is successful, the guest
9393 * in the source machine will be destroyed and large sptes will be
9394 * created in the destination. However, if the guest continues to run
9395 * in the source machine (for example if live migration fails), small
9396 * sptes will remain around and cause bad performance.
9397 *
9398 * Scan sptes if dirty logging has been stopped, dropping those
9399 * which can be collapsed into a single large-page spte. Later
9400 * page faults will create the large-page sptes.
9401 */
9402 if ((change != KVM_MR_DELETE) &&
9403 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9404 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9405 kvm_mmu_zap_collapsible_sptes(kvm, new);
9406
c972f3b1 9407 /*
88178fd4 9408 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9409 *
88178fd4
KH		 9410 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9411 * been zapped so no dirty logging staff is needed for old slot. For
9412 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9413 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9414 *
9415 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9416 */
88178fd4 9417 if (change != KVM_MR_DELETE)
f36f3f28 9418 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9419}
1d737c8a 9420
2df72e9b 9421void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9422{
6ca18b69 9423 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9424}
9425
2df72e9b
MT		 9426void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9427 struct kvm_memory_slot *slot)
9428{
ae7cd873 9429 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9430}
9431
e6c67d8c
LA		 9432static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9433{
9434 return (is_guest_mode(vcpu) &&
9435 kvm_x86_ops->guest_apic_has_interrupt &&
9436 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9437}
9438
5d9bc648
PB		 9439static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9440{
9441 if (!list_empty_careful(&vcpu->async_pf.done))
9442 return true;
9443
9444 if (kvm_apic_has_events(vcpu))
9445 return true;
9446
9447 if (vcpu->arch.pv.pv_unhalted)
9448 return true;
9449
a5f01f8e
WL		 9450 if (vcpu->arch.exception.pending)
9451 return true;
9452
47a66eed
Z		 9453 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9454 (vcpu->arch.nmi_pending &&
9455 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9456 return true;
9457
47a66eed
Z		 9458 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9459 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9460 return true;
9461
5d9bc648 9462 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9463 (kvm_cpu_has_interrupt(vcpu) ||
9464 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9465 return true;
9466
1f4b34f8
AS		 9467 if (kvm_hv_has_stimer_pending(vcpu))
9468 return true;
9469
5d9bc648
PB		 9470 return false;
9471}
9472
1d737c8a
ZX		 9473int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9474{
5d9bc648 9475 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9476}
5736199a 9477
199b5763
LM		 9478bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9479{
de63ad4c 9480 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9481}
9482
b6d33834 9483int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9484{
b6d33834 9485 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9486}
78646121
GN		 9487
9488int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9489{
9490 return kvm_x86_ops->interrupt_allowed(vcpu);
9491}
229456fc 9492
82b32774 9493unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9494{
82b32774
NA		 9495 if (is_64_bit_mode(vcpu))
9496 return kvm_rip_read(vcpu);
9497 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9498 kvm_rip_read(vcpu));
9499}
9500EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9501
82b32774
NA		 9502bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9503{
9504 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9505}
9506EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9507
94fe45da
JK		 9508unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9509{
9510 unsigned long rflags;
9511
9512 rflags = kvm_x86_ops->get_rflags(vcpu);
9513 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9514 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9515 return rflags;
9516}
9517EXPORT_SYMBOL_GPL(kvm_get_rflags);
9518
6addfc42 9519static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9520{
9521 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9522 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9523 rflags |= X86_EFLAGS_TF;
94fe45da 9524 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9525}
9526
9527void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9528{
9529 __kvm_set_rflags(vcpu, rflags);
3842d135 9530 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9531}
9532EXPORT_SYMBOL_GPL(kvm_set_rflags);
9533
56028d08
GN		 9534void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9535{
9536 int r;
9537
44dd3ffa 9538 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9539 work->wakeup_all)
56028d08
GN		 9540 return;
9541
9542 r = kvm_mmu_reload(vcpu);
9543 if (unlikely(r))
9544 return;
9545
44dd3ffa
VK		 9546 if (!vcpu->arch.mmu->direct_map &&
9547 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9548 return;
9549
44dd3ffa 9550 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9551}
9552
af585b92
GN		 9553static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9554{
9555 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9556}
9557
9558static inline u32 kvm_async_pf_next_probe(u32 key)
9559{
9560 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9561}
9562
9563static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9564{
9565 u32 key = kvm_async_pf_hash_fn(gfn);
9566
9567 while (vcpu->arch.apf.gfns[key] != ~0)
9568 key = kvm_async_pf_next_probe(key);
9569
9570 vcpu->arch.apf.gfns[key] = gfn;
9571}
9572
9573static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9574{
9575 int i;
9576 u32 key = kvm_async_pf_hash_fn(gfn);
9577
9578 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9579 (vcpu->arch.apf.gfns[key] != gfn &&
9580 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9581 key = kvm_async_pf_next_probe(key);
9582
9583 return key;
9584}
9585
9586bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9587{
9588 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9589}
9590
9591static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9592{
9593 u32 i, j, k;
9594
9595 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9596 while (true) {
9597 vcpu->arch.apf.gfns[i] = ~0;
9598 do {
9599 j = kvm_async_pf_next_probe(j);
9600 if (vcpu->arch.apf.gfns[j] == ~0)
9601 return;
9602 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9603 /*
9604 * k lies cyclically in ]i,j]
9605 * | i.k.j |
9606 * |....j i.k.| or |.k..j i...|
9607 */
9608 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9609 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9610 i = j;
9611 }
9612}
9613
7c90705b
GN		 9614static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9615{
4e335d9e
PB		 9616
9617 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9618 sizeof(val));
7c90705b
GN		 9619}
9620
9a6e7c39
WL		 9621static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9622{
9623
9624 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9625 sizeof(u32));
9626}
9627
af585b92
GN		 9628void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9629 struct kvm_async_pf *work)
9630{
6389ee94
AK		 9631 struct x86_exception fault;
9632
7c90705b 9633 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9634 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9635
9636 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9637 (vcpu->arch.apf.send_user_only &&
9638 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9639 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9640 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9641 fault.vector = PF_VECTOR;
9642 fault.error_code_valid = true;
9643 fault.error_code = 0;
9644 fault.nested_page_fault = false;
9645 fault.address = work->arch.token;
adfe20fb 9646 fault.async_page_fault = true;
6389ee94 9647 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9648 }
af585b92
GN		 9649}
9650
9651void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9652 struct kvm_async_pf *work)
9653{
6389ee94 9654 struct x86_exception fault;
9a6e7c39 9655 u32 val;
6389ee94 9656
f2e10669 9657 if (work->wakeup_all)
7c90705b
GN		 9658 work->arch.token = ~0; /* broadcast wakeup */
9659 else
9660 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9661 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9662
9a6e7c39
WL		 9663 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9664 !apf_get_user(vcpu, &val)) {
9665 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9666 vcpu->arch.exception.pending &&
9667 vcpu->arch.exception.nr == PF_VECTOR &&
9668 !apf_put_user(vcpu, 0)) {
9669 vcpu->arch.exception.injected = false;
9670 vcpu->arch.exception.pending = false;
9671 vcpu->arch.exception.nr = 0;
9672 vcpu->arch.exception.has_error_code = false;
9673 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9674 vcpu->arch.exception.has_payload = false;
9675 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9676 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9677 fault.vector = PF_VECTOR;
9678 fault.error_code_valid = true;
9679 fault.error_code = 0;
9680 fault.nested_page_fault = false;
9681 fault.address = work->arch.token;
9682 fault.async_page_fault = true;
9683 kvm_inject_page_fault(vcpu, &fault);
9684 }
7c90705b 9685 }
e6d53e3b 9686 vcpu->arch.apf.halted = false;
a4fa1635 9687 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9688}
9689
9690bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9691{
9692 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9693 return true;
9694 else
9bc1f09f 9695 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9696}
9697
5544eb9b
PB		 9698void kvm_arch_start_assignment(struct kvm *kvm)
9699{
9700 atomic_inc(&kvm->arch.assigned_device_count);
9701}
9702EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9703
9704void kvm_arch_end_assignment(struct kvm *kvm)
9705{
9706 atomic_dec(&kvm->arch.assigned_device_count);
9707}
9708EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9709
9710bool kvm_arch_has_assigned_device(struct kvm *kvm)
9711{
9712 return atomic_read(&kvm->arch.assigned_device_count);
9713}
9714EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9715
e0f0bbc5
AW		 9716void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9717{
9718 atomic_inc(&kvm->arch.noncoherent_dma_count);
9719}
9720EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9721
9722void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9723{
9724 atomic_dec(&kvm->arch.noncoherent_dma_count);
9725}
9726EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9727
9728bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9729{
9730 return atomic_read(&kvm->arch.noncoherent_dma_count);
9731}
9732EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9733
14717e20
AW		 9734bool kvm_arch_has_irq_bypass(void)
9735{
9736 return kvm_x86_ops->update_pi_irte != NULL;
9737}
9738
87276880
FW		 9739int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9740 struct irq_bypass_producer *prod)
9741{
9742 struct kvm_kernel_irqfd *irqfd =
9743 container_of(cons, struct kvm_kernel_irqfd, consumer);
9744
14717e20 9745 irqfd->producer = prod;
87276880 9746
14717e20
AW		 9747 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9748 prod->irq, irqfd->gsi, 1);
87276880
FW		 9749}
9750
9751void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9752 struct irq_bypass_producer *prod)
9753{
9754 int ret;
9755 struct kvm_kernel_irqfd *irqfd =
9756 container_of(cons, struct kvm_kernel_irqfd, consumer);
9757
87276880
FW		 9758 WARN_ON(irqfd->producer != prod);
9759 irqfd->producer = NULL;
9760
9761 /*
9762 * When producer of consumer is unregistered, we change back to
9763 * remapped mode, so we can re-use the current implementation
bb3541f1 9764 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9765 * int this case doesn't want to receive the interrupts.
9766 */
9767 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9768 if (ret)
9769 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9770 " fails: %d\n", irqfd->consumer.token, ret);
9771}
9772
9773int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9774 uint32_t guest_irq, bool set)
9775{
9776 if (!kvm_x86_ops->update_pi_irte)
9777 return -EINVAL;
9778
9779 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9780}
9781
52004014
FW		 9782bool kvm_vector_hashing_enabled(void)
9783{
9784 return vector_hashing;
9785}
9786EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9787
229456fc 9788EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9789EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9790EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9791EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9792EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9793EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9794EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9795EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9796EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9797EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9798EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9799EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9800EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9801EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9802EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9803EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9804EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9805EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9806EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git