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b99bd4ef | 1 | /* tc-arm.c -- Assemble for the ARM |
f17c130b | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, |
4a58c4bd | 3 | 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
b99bd4ef NC |
4 | Free Software Foundation, Inc. |
5 | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) | |
6 | Modified by David Taylor (dtaylor@armltd.co.uk) | |
22d9c8c5 | 7 | Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) |
34920d91 NC |
8 | Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) |
9 | Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) | |
b99bd4ef NC |
10 | |
11 | This file is part of GAS, the GNU Assembler. | |
12 | ||
13 | GAS is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 15 | the Free Software Foundation; either version 3, or (at your option) |
b99bd4ef NC |
16 | any later version. |
17 | ||
18 | GAS is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
c19d1205 | 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
b99bd4ef NC |
21 | GNU General Public License for more details. |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with GAS; see the file COPYING. If not, write to the Free | |
699d2810 NC |
25 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
26 | 02110-1301, USA. */ | |
b99bd4ef | 27 | |
42a68e18 | 28 | #include "as.h" |
5287ad62 | 29 | #include <limits.h> |
037e8744 | 30 | #include <stdarg.h> |
c19d1205 | 31 | #define NO_RELOC 0 |
3882b010 | 32 | #include "safe-ctype.h" |
b99bd4ef NC |
33 | #include "subsegs.h" |
34 | #include "obstack.h" | |
3da1d841 | 35 | #include "libiberty.h" |
f263249b RE |
36 | #include "opcode/arm.h" |
37 | ||
b99bd4ef NC |
38 | #ifdef OBJ_ELF |
39 | #include "elf/arm.h" | |
a394c00f | 40 | #include "dw2gencfi.h" |
b99bd4ef NC |
41 | #endif |
42 | ||
f0927246 NC |
43 | #include "dwarf2dbg.h" |
44 | ||
7ed4c4c5 NC |
45 | #ifdef OBJ_ELF |
46 | /* Must be at least the size of the largest unwind opcode (currently two). */ | |
47 | #define ARM_OPCODE_CHUNK_SIZE 8 | |
48 | ||
49 | /* This structure holds the unwinding state. */ | |
50 | ||
51 | static struct | |
52 | { | |
c19d1205 ZW |
53 | symbolS * proc_start; |
54 | symbolS * table_entry; | |
55 | symbolS * personality_routine; | |
56 | int personality_index; | |
7ed4c4c5 | 57 | /* The segment containing the function. */ |
c19d1205 ZW |
58 | segT saved_seg; |
59 | subsegT saved_subseg; | |
7ed4c4c5 NC |
60 | /* Opcodes generated from this function. */ |
61 | unsigned char * opcodes; | |
c19d1205 ZW |
62 | int opcode_count; |
63 | int opcode_alloc; | |
7ed4c4c5 | 64 | /* The number of bytes pushed to the stack. */ |
c19d1205 | 65 | offsetT frame_size; |
7ed4c4c5 NC |
66 | /* We don't add stack adjustment opcodes immediately so that we can merge |
67 | multiple adjustments. We can also omit the final adjustment | |
68 | when using a frame pointer. */ | |
c19d1205 | 69 | offsetT pending_offset; |
7ed4c4c5 | 70 | /* These two fields are set by both unwind_movsp and unwind_setfp. They |
c19d1205 ZW |
71 | hold the reg+offset to use when restoring sp from a frame pointer. */ |
72 | offsetT fp_offset; | |
73 | int fp_reg; | |
7ed4c4c5 | 74 | /* Nonzero if an unwind_setfp directive has been seen. */ |
c19d1205 | 75 | unsigned fp_used:1; |
7ed4c4c5 | 76 | /* Nonzero if the last opcode restores sp from fp_reg. */ |
c19d1205 | 77 | unsigned sp_restored:1; |
7ed4c4c5 NC |
78 | } unwind; |
79 | ||
8b1ad454 NC |
80 | #endif /* OBJ_ELF */ |
81 | ||
4962c51a MS |
82 | /* Results from operand parsing worker functions. */ |
83 | ||
84 | typedef enum | |
85 | { | |
86 | PARSE_OPERAND_SUCCESS, | |
87 | PARSE_OPERAND_FAIL, | |
88 | PARSE_OPERAND_FAIL_NO_BACKTRACK | |
89 | } parse_operand_result; | |
90 | ||
33a392fb PB |
91 | enum arm_float_abi |
92 | { | |
93 | ARM_FLOAT_ABI_HARD, | |
94 | ARM_FLOAT_ABI_SOFTFP, | |
95 | ARM_FLOAT_ABI_SOFT | |
96 | }; | |
97 | ||
c19d1205 | 98 | /* Types of processor to assemble for. */ |
b99bd4ef | 99 | #ifndef CPU_DEFAULT |
8a59fff3 MGD |
100 | /* The code that was here used to select a default CPU depending on compiler |
101 | pre-defines which were only present when doing native builds, thus | |
102 | changing gas' default behaviour depending upon the build host. | |
103 | ||
104 | If you have a target that requires a default CPU option then the you | |
105 | should define CPU_DEFAULT here. */ | |
b99bd4ef NC |
106 | #endif |
107 | ||
108 | #ifndef FPU_DEFAULT | |
c820d418 MM |
109 | # ifdef TE_LINUX |
110 | # define FPU_DEFAULT FPU_ARCH_FPA | |
111 | # elif defined (TE_NetBSD) | |
112 | # ifdef OBJ_ELF | |
113 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ | |
114 | # else | |
115 | /* Legacy a.out format. */ | |
116 | # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ | |
117 | # endif | |
4e7fd91e PB |
118 | # elif defined (TE_VXWORKS) |
119 | # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ | |
c820d418 MM |
120 | # else |
121 | /* For backwards compatibility, default to FPA. */ | |
122 | # define FPU_DEFAULT FPU_ARCH_FPA | |
123 | # endif | |
124 | #endif /* ifndef FPU_DEFAULT */ | |
b99bd4ef | 125 | |
c19d1205 | 126 | #define streq(a, b) (strcmp (a, b) == 0) |
b99bd4ef | 127 | |
e74cfd16 PB |
128 | static arm_feature_set cpu_variant; |
129 | static arm_feature_set arm_arch_used; | |
130 | static arm_feature_set thumb_arch_used; | |
b99bd4ef | 131 | |
b99bd4ef | 132 | /* Flags stored in private area of BFD structure. */ |
c19d1205 ZW |
133 | static int uses_apcs_26 = FALSE; |
134 | static int atpcs = FALSE; | |
b34976b6 AM |
135 | static int support_interwork = FALSE; |
136 | static int uses_apcs_float = FALSE; | |
c19d1205 | 137 | static int pic_code = FALSE; |
845b51d6 | 138 | static int fix_v4bx = FALSE; |
278df34e NS |
139 | /* Warn on using deprecated features. */ |
140 | static int warn_on_deprecated = TRUE; | |
141 | ||
03b1477f RE |
142 | |
143 | /* Variables that we set while parsing command-line options. Once all | |
144 | options have been read we re-process these values to set the real | |
145 | assembly flags. */ | |
e74cfd16 PB |
146 | static const arm_feature_set *legacy_cpu = NULL; |
147 | static const arm_feature_set *legacy_fpu = NULL; | |
148 | ||
149 | static const arm_feature_set *mcpu_cpu_opt = NULL; | |
150 | static const arm_feature_set *mcpu_fpu_opt = NULL; | |
151 | static const arm_feature_set *march_cpu_opt = NULL; | |
152 | static const arm_feature_set *march_fpu_opt = NULL; | |
153 | static const arm_feature_set *mfpu_opt = NULL; | |
7a1d4c38 | 154 | static const arm_feature_set *object_arch = NULL; |
e74cfd16 PB |
155 | |
156 | /* Constants for known architecture features. */ | |
157 | static const arm_feature_set fpu_default = FPU_DEFAULT; | |
158 | static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; | |
159 | static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; | |
5287ad62 JB |
160 | static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; |
161 | static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; | |
e74cfd16 PB |
162 | static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; |
163 | static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; | |
164 | static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; | |
165 | static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; | |
166 | ||
167 | #ifdef CPU_DEFAULT | |
168 | static const arm_feature_set cpu_default = CPU_DEFAULT; | |
169 | #endif | |
170 | ||
171 | static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); | |
172 | static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); | |
173 | static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); | |
174 | static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); | |
175 | static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); | |
176 | static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); | |
177 | static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); | |
178 | static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); | |
179 | static const arm_feature_set arm_ext_v4t_5 = | |
180 | ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); | |
181 | static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); | |
182 | static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); | |
183 | static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); | |
184 | static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); | |
185 | static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); | |
186 | static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); | |
e74cfd16 | 187 | static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); |
b2a5fbdc | 188 | static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0); |
62b3e311 | 189 | static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); |
9e3c6df6 | 190 | static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0); |
7e806470 PB |
191 | static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0); |
192 | static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0); | |
62b3e311 PB |
193 | static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); |
194 | static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); | |
195 | static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); | |
196 | static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); | |
9e3c6df6 | 197 | static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); |
7e806470 | 198 | static const arm_feature_set arm_ext_m = |
b2a5fbdc | 199 | ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0); |
60e5ef9f | 200 | static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0); |
f4c65163 | 201 | static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0); |
b2a5fbdc | 202 | static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0); |
eea54501 | 203 | static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0); |
90ec0d68 | 204 | static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0); |
e74cfd16 PB |
205 | |
206 | static const arm_feature_set arm_arch_any = ARM_ANY; | |
207 | static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); | |
208 | static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; | |
209 | static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; | |
251665fc | 210 | static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY; |
e74cfd16 | 211 | |
2d447fca JM |
212 | static const arm_feature_set arm_cext_iwmmxt2 = |
213 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2); | |
e74cfd16 PB |
214 | static const arm_feature_set arm_cext_iwmmxt = |
215 | ARM_FEATURE (0, ARM_CEXT_IWMMXT); | |
216 | static const arm_feature_set arm_cext_xscale = | |
217 | ARM_FEATURE (0, ARM_CEXT_XSCALE); | |
218 | static const arm_feature_set arm_cext_maverick = | |
219 | ARM_FEATURE (0, ARM_CEXT_MAVERICK); | |
220 | static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); | |
221 | static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); | |
222 | static const arm_feature_set fpu_vfp_ext_v1xd = | |
223 | ARM_FEATURE (0, FPU_VFP_EXT_V1xD); | |
224 | static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); | |
225 | static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); | |
62f3b8c8 | 226 | static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD); |
5287ad62 | 227 | static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); |
b1cc4aeb PB |
228 | static const arm_feature_set fpu_vfp_ext_d32 = |
229 | ARM_FEATURE (0, FPU_VFP_EXT_D32); | |
5287ad62 JB |
230 | static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
231 | static const arm_feature_set fpu_vfp_v3_or_neon_ext = | |
232 | ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); | |
62f3b8c8 PB |
233 | static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16); |
234 | static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA); | |
235 | static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA); | |
e74cfd16 | 236 | |
33a392fb | 237 | static int mfloat_abi_opt = -1; |
e74cfd16 PB |
238 | /* Record user cpu selection for object attributes. */ |
239 | static arm_feature_set selected_cpu = ARM_ARCH_NONE; | |
ee065d83 PB |
240 | /* Must be long enough to hold any of the names in arm_cpus. */ |
241 | static char selected_cpu_name[16]; | |
8d67f500 NC |
242 | |
243 | /* Return if no cpu was selected on command-line. */ | |
244 | static bfd_boolean | |
245 | no_cpu_selected (void) | |
246 | { | |
247 | return selected_cpu.core == arm_arch_none.core | |
248 | && selected_cpu.coproc == arm_arch_none.coproc; | |
249 | } | |
250 | ||
7cc69913 | 251 | #ifdef OBJ_ELF |
deeaaff8 DJ |
252 | # ifdef EABI_DEFAULT |
253 | static int meabi_flags = EABI_DEFAULT; | |
254 | # else | |
d507cf36 | 255 | static int meabi_flags = EF_ARM_EABI_UNKNOWN; |
deeaaff8 | 256 | # endif |
e1da3f5b | 257 | |
ee3c0378 AS |
258 | static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; |
259 | ||
e1da3f5b | 260 | bfd_boolean |
5f4273c7 | 261 | arm_is_eabi (void) |
e1da3f5b PB |
262 | { |
263 | return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); | |
264 | } | |
7cc69913 | 265 | #endif |
b99bd4ef | 266 | |
b99bd4ef | 267 | #ifdef OBJ_ELF |
c19d1205 | 268 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
b99bd4ef NC |
269 | symbolS * GOT_symbol; |
270 | #endif | |
271 | ||
b99bd4ef NC |
272 | /* 0: assemble for ARM, |
273 | 1: assemble for Thumb, | |
274 | 2: assemble for Thumb even though target CPU does not support thumb | |
275 | instructions. */ | |
276 | static int thumb_mode = 0; | |
8dc2430f NC |
277 | /* A value distinct from the possible values for thumb_mode that we |
278 | can use to record whether thumb_mode has been copied into the | |
279 | tc_frag_data field of a frag. */ | |
280 | #define MODE_RECORDED (1 << 4) | |
b99bd4ef | 281 | |
e07e6e58 NC |
282 | /* Specifies the intrinsic IT insn behavior mode. */ |
283 | enum implicit_it_mode | |
284 | { | |
285 | IMPLICIT_IT_MODE_NEVER = 0x00, | |
286 | IMPLICIT_IT_MODE_ARM = 0x01, | |
287 | IMPLICIT_IT_MODE_THUMB = 0x02, | |
288 | IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB) | |
289 | }; | |
290 | static int implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
291 | ||
c19d1205 ZW |
292 | /* If unified_syntax is true, we are processing the new unified |
293 | ARM/Thumb syntax. Important differences from the old ARM mode: | |
294 | ||
295 | - Immediate operands do not require a # prefix. | |
296 | - Conditional affixes always appear at the end of the | |
297 | instruction. (For backward compatibility, those instructions | |
298 | that formerly had them in the middle, continue to accept them | |
299 | there.) | |
300 | - The IT instruction may appear, and if it does is validated | |
301 | against subsequent conditional affixes. It does not generate | |
302 | machine code. | |
303 | ||
304 | Important differences from the old Thumb mode: | |
305 | ||
306 | - Immediate operands do not require a # prefix. | |
307 | - Most of the V6T2 instructions are only available in unified mode. | |
308 | - The .N and .W suffixes are recognized and honored (it is an error | |
309 | if they cannot be honored). | |
310 | - All instructions set the flags if and only if they have an 's' affix. | |
311 | - Conditional affixes may be used. They are validated against | |
312 | preceding IT instructions. Unlike ARM mode, you cannot use a | |
313 | conditional affix except in the scope of an IT instruction. */ | |
314 | ||
315 | static bfd_boolean unified_syntax = FALSE; | |
b99bd4ef | 316 | |
5287ad62 JB |
317 | enum neon_el_type |
318 | { | |
dcbf9037 | 319 | NT_invtype, |
5287ad62 JB |
320 | NT_untyped, |
321 | NT_integer, | |
322 | NT_float, | |
323 | NT_poly, | |
324 | NT_signed, | |
dcbf9037 | 325 | NT_unsigned |
5287ad62 JB |
326 | }; |
327 | ||
328 | struct neon_type_el | |
329 | { | |
330 | enum neon_el_type type; | |
331 | unsigned size; | |
332 | }; | |
333 | ||
334 | #define NEON_MAX_TYPE_ELS 4 | |
335 | ||
336 | struct neon_type | |
337 | { | |
338 | struct neon_type_el el[NEON_MAX_TYPE_ELS]; | |
339 | unsigned elems; | |
340 | }; | |
341 | ||
e07e6e58 NC |
342 | enum it_instruction_type |
343 | { | |
344 | OUTSIDE_IT_INSN, | |
345 | INSIDE_IT_INSN, | |
346 | INSIDE_IT_LAST_INSN, | |
347 | IF_INSIDE_IT_LAST_INSN, /* Either outside or inside; | |
348 | if inside, should be the last one. */ | |
349 | NEUTRAL_IT_INSN, /* This could be either inside or outside, | |
350 | i.e. BKPT and NOP. */ | |
351 | IT_INSN /* The IT insn has been parsed. */ | |
352 | }; | |
353 | ||
ad6cec43 MGD |
354 | /* The maximum number of operands we need. */ |
355 | #define ARM_IT_MAX_OPERANDS 6 | |
356 | ||
b99bd4ef NC |
357 | struct arm_it |
358 | { | |
c19d1205 | 359 | const char * error; |
b99bd4ef | 360 | unsigned long instruction; |
c19d1205 ZW |
361 | int size; |
362 | int size_req; | |
363 | int cond; | |
037e8744 JB |
364 | /* "uncond_value" is set to the value in place of the conditional field in |
365 | unconditional versions of the instruction, or -1 if nothing is | |
366 | appropriate. */ | |
367 | int uncond_value; | |
5287ad62 | 368 | struct neon_type vectype; |
88714cb8 DG |
369 | /* This does not indicate an actual NEON instruction, only that |
370 | the mnemonic accepts neon-style type suffixes. */ | |
371 | int is_neon; | |
0110f2b8 PB |
372 | /* Set to the opcode if the instruction needs relaxation. |
373 | Zero if the instruction is not relaxed. */ | |
374 | unsigned long relax; | |
b99bd4ef NC |
375 | struct |
376 | { | |
377 | bfd_reloc_code_real_type type; | |
c19d1205 ZW |
378 | expressionS exp; |
379 | int pc_rel; | |
b99bd4ef | 380 | } reloc; |
b99bd4ef | 381 | |
e07e6e58 NC |
382 | enum it_instruction_type it_insn_type; |
383 | ||
c19d1205 ZW |
384 | struct |
385 | { | |
386 | unsigned reg; | |
ca3f61f7 | 387 | signed int imm; |
dcbf9037 | 388 | struct neon_type_el vectype; |
ca3f61f7 NC |
389 | unsigned present : 1; /* Operand present. */ |
390 | unsigned isreg : 1; /* Operand was a register. */ | |
391 | unsigned immisreg : 1; /* .imm field is a second register. */ | |
5287ad62 JB |
392 | unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ |
393 | unsigned immisalign : 1; /* Immediate is an alignment specifier. */ | |
c96612cc | 394 | unsigned immisfloat : 1; /* Immediate was parsed as a float. */ |
5287ad62 JB |
395 | /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV |
396 | instructions. This allows us to disambiguate ARM <-> vector insns. */ | |
397 | unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ | |
037e8744 | 398 | unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ |
5287ad62 | 399 | unsigned isquad : 1; /* Operand is Neon quad-precision register. */ |
037e8744 | 400 | unsigned issingle : 1; /* Operand is VFP single-precision register. */ |
ca3f61f7 NC |
401 | unsigned hasreloc : 1; /* Operand has relocation suffix. */ |
402 | unsigned writeback : 1; /* Operand has trailing ! */ | |
403 | unsigned preind : 1; /* Preindexed address. */ | |
404 | unsigned postind : 1; /* Postindexed address. */ | |
405 | unsigned negative : 1; /* Index register was negated. */ | |
406 | unsigned shifted : 1; /* Shift applied to operation. */ | |
407 | unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ | |
ad6cec43 | 408 | } operands[ARM_IT_MAX_OPERANDS]; |
b99bd4ef NC |
409 | }; |
410 | ||
c19d1205 | 411 | static struct arm_it inst; |
b99bd4ef NC |
412 | |
413 | #define NUM_FLOAT_VALS 8 | |
414 | ||
05d2d07e | 415 | const char * fp_const[] = |
b99bd4ef NC |
416 | { |
417 | "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 | |
418 | }; | |
419 | ||
c19d1205 | 420 | /* Number of littlenums required to hold an extended precision number. */ |
b99bd4ef NC |
421 | #define MAX_LITTLENUMS 6 |
422 | ||
423 | LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; | |
424 | ||
425 | #define FAIL (-1) | |
426 | #define SUCCESS (0) | |
427 | ||
428 | #define SUFF_S 1 | |
429 | #define SUFF_D 2 | |
430 | #define SUFF_E 3 | |
431 | #define SUFF_P 4 | |
432 | ||
c19d1205 ZW |
433 | #define CP_T_X 0x00008000 |
434 | #define CP_T_Y 0x00400000 | |
b99bd4ef | 435 | |
c19d1205 ZW |
436 | #define CONDS_BIT 0x00100000 |
437 | #define LOAD_BIT 0x00100000 | |
b99bd4ef NC |
438 | |
439 | #define DOUBLE_LOAD_FLAG 0x00000001 | |
440 | ||
441 | struct asm_cond | |
442 | { | |
d3ce72d0 | 443 | const char * template_name; |
c921be7d | 444 | unsigned long value; |
b99bd4ef NC |
445 | }; |
446 | ||
c19d1205 | 447 | #define COND_ALWAYS 0xE |
b99bd4ef | 448 | |
b99bd4ef NC |
449 | struct asm_psr |
450 | { | |
d3ce72d0 | 451 | const char * template_name; |
c921be7d | 452 | unsigned long field; |
b99bd4ef NC |
453 | }; |
454 | ||
62b3e311 PB |
455 | struct asm_barrier_opt |
456 | { | |
d3ce72d0 | 457 | const char * template_name; |
c921be7d | 458 | unsigned long value; |
62b3e311 PB |
459 | }; |
460 | ||
2d2255b5 | 461 | /* The bit that distinguishes CPSR and SPSR. */ |
b99bd4ef NC |
462 | #define SPSR_BIT (1 << 22) |
463 | ||
c19d1205 ZW |
464 | /* The individual PSR flag bits. */ |
465 | #define PSR_c (1 << 16) | |
466 | #define PSR_x (1 << 17) | |
467 | #define PSR_s (1 << 18) | |
468 | #define PSR_f (1 << 19) | |
b99bd4ef | 469 | |
c19d1205 | 470 | struct reloc_entry |
bfae80f2 | 471 | { |
c921be7d NC |
472 | char * name; |
473 | bfd_reloc_code_real_type reloc; | |
bfae80f2 RE |
474 | }; |
475 | ||
5287ad62 | 476 | enum vfp_reg_pos |
bfae80f2 | 477 | { |
5287ad62 JB |
478 | VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, |
479 | VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn | |
bfae80f2 RE |
480 | }; |
481 | ||
482 | enum vfp_ldstm_type | |
483 | { | |
484 | VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX | |
485 | }; | |
486 | ||
dcbf9037 JB |
487 | /* Bits for DEFINED field in neon_typed_alias. */ |
488 | #define NTA_HASTYPE 1 | |
489 | #define NTA_HASINDEX 2 | |
490 | ||
491 | struct neon_typed_alias | |
492 | { | |
c921be7d NC |
493 | unsigned char defined; |
494 | unsigned char index; | |
495 | struct neon_type_el eltype; | |
dcbf9037 JB |
496 | }; |
497 | ||
c19d1205 ZW |
498 | /* ARM register categories. This includes coprocessor numbers and various |
499 | architecture extensions' registers. */ | |
500 | enum arm_reg_type | |
bfae80f2 | 501 | { |
c19d1205 ZW |
502 | REG_TYPE_RN, |
503 | REG_TYPE_CP, | |
504 | REG_TYPE_CN, | |
505 | REG_TYPE_FN, | |
506 | REG_TYPE_VFS, | |
507 | REG_TYPE_VFD, | |
5287ad62 | 508 | REG_TYPE_NQ, |
037e8744 | 509 | REG_TYPE_VFSD, |
5287ad62 | 510 | REG_TYPE_NDQ, |
037e8744 | 511 | REG_TYPE_NSDQ, |
c19d1205 ZW |
512 | REG_TYPE_VFC, |
513 | REG_TYPE_MVF, | |
514 | REG_TYPE_MVD, | |
515 | REG_TYPE_MVFX, | |
516 | REG_TYPE_MVDX, | |
517 | REG_TYPE_MVAX, | |
518 | REG_TYPE_DSPSC, | |
519 | REG_TYPE_MMXWR, | |
520 | REG_TYPE_MMXWC, | |
521 | REG_TYPE_MMXWCG, | |
522 | REG_TYPE_XSCALE, | |
90ec0d68 | 523 | REG_TYPE_RNB |
bfae80f2 RE |
524 | }; |
525 | ||
dcbf9037 JB |
526 | /* Structure for a hash table entry for a register. |
527 | If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra | |
528 | information which states whether a vector type or index is specified (for a | |
529 | register alias created with .dn or .qn). Otherwise NEON should be NULL. */ | |
6c43fab6 RE |
530 | struct reg_entry |
531 | { | |
c921be7d | 532 | const char * name; |
90ec0d68 | 533 | unsigned int number; |
c921be7d NC |
534 | unsigned char type; |
535 | unsigned char builtin; | |
536 | struct neon_typed_alias * neon; | |
6c43fab6 RE |
537 | }; |
538 | ||
c19d1205 | 539 | /* Diagnostics used when we don't get a register of the expected type. */ |
c921be7d | 540 | const char * const reg_expected_msgs[] = |
c19d1205 ZW |
541 | { |
542 | N_("ARM register expected"), | |
543 | N_("bad or missing co-processor number"), | |
544 | N_("co-processor register expected"), | |
545 | N_("FPA register expected"), | |
546 | N_("VFP single precision register expected"), | |
5287ad62 JB |
547 | N_("VFP/Neon double precision register expected"), |
548 | N_("Neon quad precision register expected"), | |
037e8744 | 549 | N_("VFP single or double precision register expected"), |
5287ad62 | 550 | N_("Neon double or quad precision register expected"), |
037e8744 | 551 | N_("VFP single, double or Neon quad precision register expected"), |
c19d1205 ZW |
552 | N_("VFP system register expected"), |
553 | N_("Maverick MVF register expected"), | |
554 | N_("Maverick MVD register expected"), | |
555 | N_("Maverick MVFX register expected"), | |
556 | N_("Maverick MVDX register expected"), | |
557 | N_("Maverick MVAX register expected"), | |
558 | N_("Maverick DSPSC register expected"), | |
559 | N_("iWMMXt data register expected"), | |
560 | N_("iWMMXt control register expected"), | |
561 | N_("iWMMXt scalar register expected"), | |
562 | N_("XScale accumulator register expected"), | |
6c43fab6 RE |
563 | }; |
564 | ||
c19d1205 | 565 | /* Some well known registers that we refer to directly elsewhere. */ |
bd340a04 | 566 | #define REG_R12 12 |
c19d1205 ZW |
567 | #define REG_SP 13 |
568 | #define REG_LR 14 | |
569 | #define REG_PC 15 | |
404ff6b5 | 570 | |
b99bd4ef NC |
571 | /* ARM instructions take 4bytes in the object file, Thumb instructions |
572 | take 2: */ | |
c19d1205 | 573 | #define INSN_SIZE 4 |
b99bd4ef NC |
574 | |
575 | struct asm_opcode | |
576 | { | |
577 | /* Basic string to match. */ | |
d3ce72d0 | 578 | const char * template_name; |
c19d1205 ZW |
579 | |
580 | /* Parameters to instruction. */ | |
5be8be5d | 581 | unsigned int operands[8]; |
c19d1205 ZW |
582 | |
583 | /* Conditional tag - see opcode_lookup. */ | |
584 | unsigned int tag : 4; | |
b99bd4ef NC |
585 | |
586 | /* Basic instruction code. */ | |
c19d1205 | 587 | unsigned int avalue : 28; |
b99bd4ef | 588 | |
c19d1205 ZW |
589 | /* Thumb-format instruction code. */ |
590 | unsigned int tvalue; | |
b99bd4ef | 591 | |
90e4755a | 592 | /* Which architecture variant provides this instruction. */ |
c921be7d NC |
593 | const arm_feature_set * avariant; |
594 | const arm_feature_set * tvariant; | |
c19d1205 ZW |
595 | |
596 | /* Function to call to encode instruction in ARM format. */ | |
597 | void (* aencode) (void); | |
b99bd4ef | 598 | |
c19d1205 ZW |
599 | /* Function to call to encode instruction in Thumb format. */ |
600 | void (* tencode) (void); | |
b99bd4ef NC |
601 | }; |
602 | ||
a737bd4d NC |
603 | /* Defines for various bits that we will want to toggle. */ |
604 | #define INST_IMMEDIATE 0x02000000 | |
605 | #define OFFSET_REG 0x02000000 | |
c19d1205 | 606 | #define HWOFFSET_IMM 0x00400000 |
a737bd4d NC |
607 | #define SHIFT_BY_REG 0x00000010 |
608 | #define PRE_INDEX 0x01000000 | |
609 | #define INDEX_UP 0x00800000 | |
610 | #define WRITE_BACK 0x00200000 | |
611 | #define LDM_TYPE_2_OR_3 0x00400000 | |
a028a6f5 | 612 | #define CPSI_MMOD 0x00020000 |
90e4755a | 613 | |
a737bd4d NC |
614 | #define LITERAL_MASK 0xf000f000 |
615 | #define OPCODE_MASK 0xfe1fffff | |
616 | #define V4_STR_BIT 0x00000020 | |
90e4755a | 617 | |
efd81785 PB |
618 | #define T2_SUBS_PC_LR 0xf3de8f00 |
619 | ||
a737bd4d | 620 | #define DATA_OP_SHIFT 21 |
90e4755a | 621 | |
ef8d22e6 PB |
622 | #define T2_OPCODE_MASK 0xfe1fffff |
623 | #define T2_DATA_OP_SHIFT 21 | |
624 | ||
a737bd4d NC |
625 | /* Codes to distinguish the arithmetic instructions. */ |
626 | #define OPCODE_AND 0 | |
627 | #define OPCODE_EOR 1 | |
628 | #define OPCODE_SUB 2 | |
629 | #define OPCODE_RSB 3 | |
630 | #define OPCODE_ADD 4 | |
631 | #define OPCODE_ADC 5 | |
632 | #define OPCODE_SBC 6 | |
633 | #define OPCODE_RSC 7 | |
634 | #define OPCODE_TST 8 | |
635 | #define OPCODE_TEQ 9 | |
636 | #define OPCODE_CMP 10 | |
637 | #define OPCODE_CMN 11 | |
638 | #define OPCODE_ORR 12 | |
639 | #define OPCODE_MOV 13 | |
640 | #define OPCODE_BIC 14 | |
641 | #define OPCODE_MVN 15 | |
90e4755a | 642 | |
ef8d22e6 PB |
643 | #define T2_OPCODE_AND 0 |
644 | #define T2_OPCODE_BIC 1 | |
645 | #define T2_OPCODE_ORR 2 | |
646 | #define T2_OPCODE_ORN 3 | |
647 | #define T2_OPCODE_EOR 4 | |
648 | #define T2_OPCODE_ADD 8 | |
649 | #define T2_OPCODE_ADC 10 | |
650 | #define T2_OPCODE_SBC 11 | |
651 | #define T2_OPCODE_SUB 13 | |
652 | #define T2_OPCODE_RSB 14 | |
653 | ||
a737bd4d NC |
654 | #define T_OPCODE_MUL 0x4340 |
655 | #define T_OPCODE_TST 0x4200 | |
656 | #define T_OPCODE_CMN 0x42c0 | |
657 | #define T_OPCODE_NEG 0x4240 | |
658 | #define T_OPCODE_MVN 0x43c0 | |
90e4755a | 659 | |
a737bd4d NC |
660 | #define T_OPCODE_ADD_R3 0x1800 |
661 | #define T_OPCODE_SUB_R3 0x1a00 | |
662 | #define T_OPCODE_ADD_HI 0x4400 | |
663 | #define T_OPCODE_ADD_ST 0xb000 | |
664 | #define T_OPCODE_SUB_ST 0xb080 | |
665 | #define T_OPCODE_ADD_SP 0xa800 | |
666 | #define T_OPCODE_ADD_PC 0xa000 | |
667 | #define T_OPCODE_ADD_I8 0x3000 | |
668 | #define T_OPCODE_SUB_I8 0x3800 | |
669 | #define T_OPCODE_ADD_I3 0x1c00 | |
670 | #define T_OPCODE_SUB_I3 0x1e00 | |
b99bd4ef | 671 | |
a737bd4d NC |
672 | #define T_OPCODE_ASR_R 0x4100 |
673 | #define T_OPCODE_LSL_R 0x4080 | |
c19d1205 ZW |
674 | #define T_OPCODE_LSR_R 0x40c0 |
675 | #define T_OPCODE_ROR_R 0x41c0 | |
a737bd4d NC |
676 | #define T_OPCODE_ASR_I 0x1000 |
677 | #define T_OPCODE_LSL_I 0x0000 | |
678 | #define T_OPCODE_LSR_I 0x0800 | |
b99bd4ef | 679 | |
a737bd4d NC |
680 | #define T_OPCODE_MOV_I8 0x2000 |
681 | #define T_OPCODE_CMP_I8 0x2800 | |
682 | #define T_OPCODE_CMP_LR 0x4280 | |
683 | #define T_OPCODE_MOV_HR 0x4600 | |
684 | #define T_OPCODE_CMP_HR 0x4500 | |
b99bd4ef | 685 | |
a737bd4d NC |
686 | #define T_OPCODE_LDR_PC 0x4800 |
687 | #define T_OPCODE_LDR_SP 0x9800 | |
688 | #define T_OPCODE_STR_SP 0x9000 | |
689 | #define T_OPCODE_LDR_IW 0x6800 | |
690 | #define T_OPCODE_STR_IW 0x6000 | |
691 | #define T_OPCODE_LDR_IH 0x8800 | |
692 | #define T_OPCODE_STR_IH 0x8000 | |
693 | #define T_OPCODE_LDR_IB 0x7800 | |
694 | #define T_OPCODE_STR_IB 0x7000 | |
695 | #define T_OPCODE_LDR_RW 0x5800 | |
696 | #define T_OPCODE_STR_RW 0x5000 | |
697 | #define T_OPCODE_LDR_RH 0x5a00 | |
698 | #define T_OPCODE_STR_RH 0x5200 | |
699 | #define T_OPCODE_LDR_RB 0x5c00 | |
700 | #define T_OPCODE_STR_RB 0x5400 | |
c9b604bd | 701 | |
a737bd4d NC |
702 | #define T_OPCODE_PUSH 0xb400 |
703 | #define T_OPCODE_POP 0xbc00 | |
b99bd4ef | 704 | |
2fc8bdac | 705 | #define T_OPCODE_BRANCH 0xe000 |
b99bd4ef | 706 | |
a737bd4d | 707 | #define THUMB_SIZE 2 /* Size of thumb instruction. */ |
a737bd4d | 708 | #define THUMB_PP_PC_LR 0x0100 |
c19d1205 | 709 | #define THUMB_LOAD_BIT 0x0800 |
53365c0d | 710 | #define THUMB2_LOAD_BIT 0x00100000 |
c19d1205 ZW |
711 | |
712 | #define BAD_ARGS _("bad arguments to instruction") | |
fdfde340 | 713 | #define BAD_SP _("r13 not allowed here") |
c19d1205 ZW |
714 | #define BAD_PC _("r15 not allowed here") |
715 | #define BAD_COND _("instruction cannot be conditional") | |
716 | #define BAD_OVERLAP _("registers may not be the same") | |
717 | #define BAD_HIREG _("lo register required") | |
718 | #define BAD_THUMB32 _("instruction not supported in Thumb16 mode") | |
01cfc07f | 719 | #define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); |
dfa9f0d5 PB |
720 | #define BAD_BRANCH _("branch must be last instruction in IT block") |
721 | #define BAD_NOT_IT _("instruction not allowed in IT block") | |
037e8744 | 722 | #define BAD_FPU _("selected FPU does not support instruction") |
e07e6e58 NC |
723 | #define BAD_OUT_IT _("thumb conditional instruction should be in IT block") |
724 | #define BAD_IT_COND _("incorrect condition in IT block") | |
725 | #define BAD_IT_IT _("IT falling in the range of a previous IT block") | |
921e5f0a | 726 | #define MISSING_FNSTART _("missing .fnstart before unwinding directive") |
5be8be5d DG |
727 | #define BAD_PC_ADDRESSING \ |
728 | _("cannot use register index with PC-relative addressing") | |
729 | #define BAD_PC_WRITEBACK \ | |
730 | _("cannot use writeback with PC-relative addressing") | |
08f10d51 | 731 | #define BAD_RANGE _("branch out of range") |
c19d1205 | 732 | |
c921be7d NC |
733 | static struct hash_control * arm_ops_hsh; |
734 | static struct hash_control * arm_cond_hsh; | |
735 | static struct hash_control * arm_shift_hsh; | |
736 | static struct hash_control * arm_psr_hsh; | |
737 | static struct hash_control * arm_v7m_psr_hsh; | |
738 | static struct hash_control * arm_reg_hsh; | |
739 | static struct hash_control * arm_reloc_hsh; | |
740 | static struct hash_control * arm_barrier_opt_hsh; | |
b99bd4ef | 741 | |
b99bd4ef NC |
742 | /* Stuff needed to resolve the label ambiguity |
743 | As: | |
744 | ... | |
745 | label: <insn> | |
746 | may differ from: | |
747 | ... | |
748 | label: | |
5f4273c7 | 749 | <insn> */ |
b99bd4ef NC |
750 | |
751 | symbolS * last_label_seen; | |
b34976b6 | 752 | static int label_is_thumb_function_name = FALSE; |
e07e6e58 | 753 | |
3d0c9500 NC |
754 | /* Literal pool structure. Held on a per-section |
755 | and per-sub-section basis. */ | |
a737bd4d | 756 | |
c19d1205 | 757 | #define MAX_LITERAL_POOL_SIZE 1024 |
3d0c9500 | 758 | typedef struct literal_pool |
b99bd4ef | 759 | { |
c921be7d NC |
760 | expressionS literals [MAX_LITERAL_POOL_SIZE]; |
761 | unsigned int next_free_entry; | |
762 | unsigned int id; | |
763 | symbolS * symbol; | |
764 | segT section; | |
765 | subsegT sub_section; | |
a8040cf2 NC |
766 | #ifdef OBJ_ELF |
767 | struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE]; | |
768 | #endif | |
c921be7d | 769 | struct literal_pool * next; |
3d0c9500 | 770 | } literal_pool; |
b99bd4ef | 771 | |
3d0c9500 NC |
772 | /* Pointer to a linked list of literal pools. */ |
773 | literal_pool * list_of_pools = NULL; | |
e27ec89e | 774 | |
e07e6e58 NC |
775 | #ifdef OBJ_ELF |
776 | # define now_it seg_info (now_seg)->tc_segment_info_data.current_it | |
777 | #else | |
778 | static struct current_it now_it; | |
779 | #endif | |
780 | ||
781 | static inline int | |
782 | now_it_compatible (int cond) | |
783 | { | |
784 | return (cond & ~1) == (now_it.cc & ~1); | |
785 | } | |
786 | ||
787 | static inline int | |
788 | conditional_insn (void) | |
789 | { | |
790 | return inst.cond != COND_ALWAYS; | |
791 | } | |
792 | ||
793 | static int in_it_block (void); | |
794 | ||
795 | static int handle_it_state (void); | |
796 | ||
797 | static void force_automatic_it_block_close (void); | |
798 | ||
c921be7d NC |
799 | static void it_fsm_post_encode (void); |
800 | ||
e07e6e58 NC |
801 | #define set_it_insn_type(type) \ |
802 | do \ | |
803 | { \ | |
804 | inst.it_insn_type = type; \ | |
805 | if (handle_it_state () == FAIL) \ | |
806 | return; \ | |
807 | } \ | |
808 | while (0) | |
809 | ||
c921be7d NC |
810 | #define set_it_insn_type_nonvoid(type, failret) \ |
811 | do \ | |
812 | { \ | |
813 | inst.it_insn_type = type; \ | |
814 | if (handle_it_state () == FAIL) \ | |
815 | return failret; \ | |
816 | } \ | |
817 | while(0) | |
818 | ||
e07e6e58 NC |
819 | #define set_it_insn_type_last() \ |
820 | do \ | |
821 | { \ | |
822 | if (inst.cond == COND_ALWAYS) \ | |
823 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \ | |
824 | else \ | |
825 | set_it_insn_type (INSIDE_IT_LAST_INSN); \ | |
826 | } \ | |
827 | while (0) | |
828 | ||
c19d1205 | 829 | /* Pure syntax. */ |
b99bd4ef | 830 | |
c19d1205 ZW |
831 | /* This array holds the chars that always start a comment. If the |
832 | pre-processor is disabled, these aren't very useful. */ | |
833 | const char comment_chars[] = "@"; | |
3d0c9500 | 834 | |
c19d1205 ZW |
835 | /* This array holds the chars that only start a comment at the beginning of |
836 | a line. If the line seems to have the form '# 123 filename' | |
837 | .line and .file directives will appear in the pre-processed output. */ | |
838 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
839 | first line of the input file. This is because the compiler outputs | |
840 | #NO_APP at the beginning of its output. */ | |
841 | /* Also note that comments like this one will always work. */ | |
842 | const char line_comment_chars[] = "#"; | |
3d0c9500 | 843 | |
c19d1205 | 844 | const char line_separator_chars[] = ";"; |
b99bd4ef | 845 | |
c19d1205 ZW |
846 | /* Chars that can be used to separate mant |
847 | from exp in floating point numbers. */ | |
848 | const char EXP_CHARS[] = "eE"; | |
3d0c9500 | 849 | |
c19d1205 ZW |
850 | /* Chars that mean this number is a floating point constant. */ |
851 | /* As in 0f12.456 */ | |
852 | /* or 0d1.2345e12 */ | |
b99bd4ef | 853 | |
c19d1205 | 854 | const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; |
3d0c9500 | 855 | |
c19d1205 ZW |
856 | /* Prefix characters that indicate the start of an immediate |
857 | value. */ | |
858 | #define is_immediate_prefix(C) ((C) == '#' || (C) == '$') | |
3d0c9500 | 859 | |
c19d1205 ZW |
860 | /* Separator character handling. */ |
861 | ||
862 | #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) | |
863 | ||
864 | static inline int | |
865 | skip_past_char (char ** str, char c) | |
866 | { | |
867 | if (**str == c) | |
868 | { | |
869 | (*str)++; | |
870 | return SUCCESS; | |
3d0c9500 | 871 | } |
c19d1205 ZW |
872 | else |
873 | return FAIL; | |
874 | } | |
c921be7d | 875 | |
c19d1205 | 876 | #define skip_past_comma(str) skip_past_char (str, ',') |
3d0c9500 | 877 | |
c19d1205 ZW |
878 | /* Arithmetic expressions (possibly involving symbols). */ |
879 | ||
880 | /* Return TRUE if anything in the expression is a bignum. */ | |
881 | ||
882 | static int | |
883 | walk_no_bignums (symbolS * sp) | |
884 | { | |
885 | if (symbol_get_value_expression (sp)->X_op == O_big) | |
886 | return 1; | |
887 | ||
888 | if (symbol_get_value_expression (sp)->X_add_symbol) | |
3d0c9500 | 889 | { |
c19d1205 ZW |
890 | return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) |
891 | || (symbol_get_value_expression (sp)->X_op_symbol | |
892 | && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); | |
3d0c9500 NC |
893 | } |
894 | ||
c19d1205 | 895 | return 0; |
3d0c9500 NC |
896 | } |
897 | ||
c19d1205 ZW |
898 | static int in_my_get_expression = 0; |
899 | ||
900 | /* Third argument to my_get_expression. */ | |
901 | #define GE_NO_PREFIX 0 | |
902 | #define GE_IMM_PREFIX 1 | |
903 | #define GE_OPT_PREFIX 2 | |
5287ad62 JB |
904 | /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) |
905 | immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ | |
906 | #define GE_OPT_PREFIX_BIG 3 | |
a737bd4d | 907 | |
b99bd4ef | 908 | static int |
c19d1205 | 909 | my_get_expression (expressionS * ep, char ** str, int prefix_mode) |
b99bd4ef | 910 | { |
c19d1205 ZW |
911 | char * save_in; |
912 | segT seg; | |
b99bd4ef | 913 | |
c19d1205 ZW |
914 | /* In unified syntax, all prefixes are optional. */ |
915 | if (unified_syntax) | |
5287ad62 JB |
916 | prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode |
917 | : GE_OPT_PREFIX; | |
b99bd4ef | 918 | |
c19d1205 | 919 | switch (prefix_mode) |
b99bd4ef | 920 | { |
c19d1205 ZW |
921 | case GE_NO_PREFIX: break; |
922 | case GE_IMM_PREFIX: | |
923 | if (!is_immediate_prefix (**str)) | |
924 | { | |
925 | inst.error = _("immediate expression requires a # prefix"); | |
926 | return FAIL; | |
927 | } | |
928 | (*str)++; | |
929 | break; | |
930 | case GE_OPT_PREFIX: | |
5287ad62 | 931 | case GE_OPT_PREFIX_BIG: |
c19d1205 ZW |
932 | if (is_immediate_prefix (**str)) |
933 | (*str)++; | |
934 | break; | |
935 | default: abort (); | |
936 | } | |
b99bd4ef | 937 | |
c19d1205 | 938 | memset (ep, 0, sizeof (expressionS)); |
b99bd4ef | 939 | |
c19d1205 ZW |
940 | save_in = input_line_pointer; |
941 | input_line_pointer = *str; | |
942 | in_my_get_expression = 1; | |
943 | seg = expression (ep); | |
944 | in_my_get_expression = 0; | |
945 | ||
f86adc07 | 946 | if (ep->X_op == O_illegal || ep->X_op == O_absent) |
b99bd4ef | 947 | { |
f86adc07 | 948 | /* We found a bad or missing expression in md_operand(). */ |
c19d1205 ZW |
949 | *str = input_line_pointer; |
950 | input_line_pointer = save_in; | |
951 | if (inst.error == NULL) | |
f86adc07 NS |
952 | inst.error = (ep->X_op == O_absent |
953 | ? _("missing expression") :_("bad expression")); | |
c19d1205 ZW |
954 | return 1; |
955 | } | |
b99bd4ef | 956 | |
c19d1205 ZW |
957 | #ifdef OBJ_AOUT |
958 | if (seg != absolute_section | |
959 | && seg != text_section | |
960 | && seg != data_section | |
961 | && seg != bss_section | |
962 | && seg != undefined_section) | |
963 | { | |
964 | inst.error = _("bad segment"); | |
965 | *str = input_line_pointer; | |
966 | input_line_pointer = save_in; | |
967 | return 1; | |
b99bd4ef | 968 | } |
87975d2a AM |
969 | #else |
970 | (void) seg; | |
c19d1205 | 971 | #endif |
b99bd4ef | 972 | |
c19d1205 ZW |
973 | /* Get rid of any bignums now, so that we don't generate an error for which |
974 | we can't establish a line number later on. Big numbers are never valid | |
975 | in instructions, which is where this routine is always called. */ | |
5287ad62 JB |
976 | if (prefix_mode != GE_OPT_PREFIX_BIG |
977 | && (ep->X_op == O_big | |
978 | || (ep->X_add_symbol | |
979 | && (walk_no_bignums (ep->X_add_symbol) | |
980 | || (ep->X_op_symbol | |
981 | && walk_no_bignums (ep->X_op_symbol)))))) | |
c19d1205 ZW |
982 | { |
983 | inst.error = _("invalid constant"); | |
984 | *str = input_line_pointer; | |
985 | input_line_pointer = save_in; | |
986 | return 1; | |
987 | } | |
b99bd4ef | 988 | |
c19d1205 ZW |
989 | *str = input_line_pointer; |
990 | input_line_pointer = save_in; | |
991 | return 0; | |
b99bd4ef NC |
992 | } |
993 | ||
c19d1205 ZW |
994 | /* Turn a string in input_line_pointer into a floating point constant |
995 | of type TYPE, and store the appropriate bytes in *LITP. The number | |
996 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
997 | returned, or NULL on OK. | |
b99bd4ef | 998 | |
c19d1205 ZW |
999 | Note that fp constants aren't represent in the normal way on the ARM. |
1000 | In big endian mode, things are as expected. However, in little endian | |
1001 | mode fp constants are big-endian word-wise, and little-endian byte-wise | |
1002 | within the words. For example, (double) 1.1 in big endian mode is | |
1003 | the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is | |
1004 | the byte sequence 99 99 f1 3f 9a 99 99 99. | |
b99bd4ef | 1005 | |
c19d1205 | 1006 | ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ |
b99bd4ef | 1007 | |
c19d1205 ZW |
1008 | char * |
1009 | md_atof (int type, char * litP, int * sizeP) | |
1010 | { | |
1011 | int prec; | |
1012 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
1013 | char *t; | |
1014 | int i; | |
b99bd4ef | 1015 | |
c19d1205 ZW |
1016 | switch (type) |
1017 | { | |
1018 | case 'f': | |
1019 | case 'F': | |
1020 | case 's': | |
1021 | case 'S': | |
1022 | prec = 2; | |
1023 | break; | |
b99bd4ef | 1024 | |
c19d1205 ZW |
1025 | case 'd': |
1026 | case 'D': | |
1027 | case 'r': | |
1028 | case 'R': | |
1029 | prec = 4; | |
1030 | break; | |
b99bd4ef | 1031 | |
c19d1205 ZW |
1032 | case 'x': |
1033 | case 'X': | |
499ac353 | 1034 | prec = 5; |
c19d1205 | 1035 | break; |
b99bd4ef | 1036 | |
c19d1205 ZW |
1037 | case 'p': |
1038 | case 'P': | |
499ac353 | 1039 | prec = 5; |
c19d1205 | 1040 | break; |
a737bd4d | 1041 | |
c19d1205 ZW |
1042 | default: |
1043 | *sizeP = 0; | |
499ac353 | 1044 | return _("Unrecognized or unsupported floating point constant"); |
c19d1205 | 1045 | } |
b99bd4ef | 1046 | |
c19d1205 ZW |
1047 | t = atof_ieee (input_line_pointer, type, words); |
1048 | if (t) | |
1049 | input_line_pointer = t; | |
499ac353 | 1050 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
b99bd4ef | 1051 | |
c19d1205 ZW |
1052 | if (target_big_endian) |
1053 | { | |
1054 | for (i = 0; i < prec; i++) | |
1055 | { | |
499ac353 NC |
1056 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1057 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1058 | } |
1059 | } | |
1060 | else | |
1061 | { | |
e74cfd16 | 1062 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) |
c19d1205 ZW |
1063 | for (i = prec - 1; i >= 0; i--) |
1064 | { | |
499ac353 NC |
1065 | md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); |
1066 | litP += sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1067 | } |
1068 | else | |
1069 | /* For a 4 byte float the order of elements in `words' is 1 0. | |
1070 | For an 8 byte float the order is 1 0 3 2. */ | |
1071 | for (i = 0; i < prec; i += 2) | |
1072 | { | |
499ac353 NC |
1073 | md_number_to_chars (litP, (valueT) words[i + 1], |
1074 | sizeof (LITTLENUM_TYPE)); | |
1075 | md_number_to_chars (litP + sizeof (LITTLENUM_TYPE), | |
1076 | (valueT) words[i], sizeof (LITTLENUM_TYPE)); | |
1077 | litP += 2 * sizeof (LITTLENUM_TYPE); | |
c19d1205 ZW |
1078 | } |
1079 | } | |
b99bd4ef | 1080 | |
499ac353 | 1081 | return NULL; |
c19d1205 | 1082 | } |
b99bd4ef | 1083 | |
c19d1205 ZW |
1084 | /* We handle all bad expressions here, so that we can report the faulty |
1085 | instruction in the error message. */ | |
1086 | void | |
91d6fa6a | 1087 | md_operand (expressionS * exp) |
c19d1205 ZW |
1088 | { |
1089 | if (in_my_get_expression) | |
91d6fa6a | 1090 | exp->X_op = O_illegal; |
b99bd4ef NC |
1091 | } |
1092 | ||
c19d1205 | 1093 | /* Immediate values. */ |
b99bd4ef | 1094 | |
c19d1205 ZW |
1095 | /* Generic immediate-value read function for use in directives. |
1096 | Accepts anything that 'expression' can fold to a constant. | |
1097 | *val receives the number. */ | |
1098 | #ifdef OBJ_ELF | |
1099 | static int | |
1100 | immediate_for_directive (int *val) | |
b99bd4ef | 1101 | { |
c19d1205 ZW |
1102 | expressionS exp; |
1103 | exp.X_op = O_illegal; | |
b99bd4ef | 1104 | |
c19d1205 ZW |
1105 | if (is_immediate_prefix (*input_line_pointer)) |
1106 | { | |
1107 | input_line_pointer++; | |
1108 | expression (&exp); | |
1109 | } | |
b99bd4ef | 1110 | |
c19d1205 ZW |
1111 | if (exp.X_op != O_constant) |
1112 | { | |
1113 | as_bad (_("expected #constant")); | |
1114 | ignore_rest_of_line (); | |
1115 | return FAIL; | |
1116 | } | |
1117 | *val = exp.X_add_number; | |
1118 | return SUCCESS; | |
b99bd4ef | 1119 | } |
c19d1205 | 1120 | #endif |
b99bd4ef | 1121 | |
c19d1205 | 1122 | /* Register parsing. */ |
b99bd4ef | 1123 | |
c19d1205 ZW |
1124 | /* Generic register parser. CCP points to what should be the |
1125 | beginning of a register name. If it is indeed a valid register | |
1126 | name, advance CCP over it and return the reg_entry structure; | |
1127 | otherwise return NULL. Does not issue diagnostics. */ | |
1128 | ||
1129 | static struct reg_entry * | |
1130 | arm_reg_parse_multi (char **ccp) | |
b99bd4ef | 1131 | { |
c19d1205 ZW |
1132 | char *start = *ccp; |
1133 | char *p; | |
1134 | struct reg_entry *reg; | |
b99bd4ef | 1135 | |
c19d1205 ZW |
1136 | #ifdef REGISTER_PREFIX |
1137 | if (*start != REGISTER_PREFIX) | |
01cfc07f | 1138 | return NULL; |
c19d1205 ZW |
1139 | start++; |
1140 | #endif | |
1141 | #ifdef OPTIONAL_REGISTER_PREFIX | |
1142 | if (*start == OPTIONAL_REGISTER_PREFIX) | |
1143 | start++; | |
1144 | #endif | |
b99bd4ef | 1145 | |
c19d1205 ZW |
1146 | p = start; |
1147 | if (!ISALPHA (*p) || !is_name_beginner (*p)) | |
1148 | return NULL; | |
b99bd4ef | 1149 | |
c19d1205 ZW |
1150 | do |
1151 | p++; | |
1152 | while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); | |
1153 | ||
1154 | reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); | |
1155 | ||
1156 | if (!reg) | |
1157 | return NULL; | |
1158 | ||
1159 | *ccp = p; | |
1160 | return reg; | |
b99bd4ef NC |
1161 | } |
1162 | ||
1163 | static int | |
dcbf9037 JB |
1164 | arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, |
1165 | enum arm_reg_type type) | |
b99bd4ef | 1166 | { |
c19d1205 ZW |
1167 | /* Alternative syntaxes are accepted for a few register classes. */ |
1168 | switch (type) | |
1169 | { | |
1170 | case REG_TYPE_MVF: | |
1171 | case REG_TYPE_MVD: | |
1172 | case REG_TYPE_MVFX: | |
1173 | case REG_TYPE_MVDX: | |
1174 | /* Generic coprocessor register names are allowed for these. */ | |
79134647 | 1175 | if (reg && reg->type == REG_TYPE_CN) |
c19d1205 ZW |
1176 | return reg->number; |
1177 | break; | |
69b97547 | 1178 | |
c19d1205 ZW |
1179 | case REG_TYPE_CP: |
1180 | /* For backward compatibility, a bare number is valid here. */ | |
1181 | { | |
1182 | unsigned long processor = strtoul (start, ccp, 10); | |
1183 | if (*ccp != start && processor <= 15) | |
1184 | return processor; | |
1185 | } | |
6057a28f | 1186 | |
c19d1205 ZW |
1187 | case REG_TYPE_MMXWC: |
1188 | /* WC includes WCG. ??? I'm not sure this is true for all | |
1189 | instructions that take WC registers. */ | |
79134647 | 1190 | if (reg && reg->type == REG_TYPE_MMXWCG) |
c19d1205 | 1191 | return reg->number; |
6057a28f | 1192 | break; |
c19d1205 | 1193 | |
6057a28f | 1194 | default: |
c19d1205 | 1195 | break; |
6057a28f NC |
1196 | } |
1197 | ||
dcbf9037 JB |
1198 | return FAIL; |
1199 | } | |
1200 | ||
1201 | /* As arm_reg_parse_multi, but the register must be of type TYPE, and the | |
1202 | return value is the register number or FAIL. */ | |
1203 | ||
1204 | static int | |
1205 | arm_reg_parse (char **ccp, enum arm_reg_type type) | |
1206 | { | |
1207 | char *start = *ccp; | |
1208 | struct reg_entry *reg = arm_reg_parse_multi (ccp); | |
1209 | int ret; | |
1210 | ||
1211 | /* Do not allow a scalar (reg+index) to parse as a register. */ | |
1212 | if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) | |
1213 | return FAIL; | |
1214 | ||
1215 | if (reg && reg->type == type) | |
1216 | return reg->number; | |
1217 | ||
1218 | if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) | |
1219 | return ret; | |
1220 | ||
c19d1205 ZW |
1221 | *ccp = start; |
1222 | return FAIL; | |
1223 | } | |
69b97547 | 1224 | |
dcbf9037 JB |
1225 | /* Parse a Neon type specifier. *STR should point at the leading '.' |
1226 | character. Does no verification at this stage that the type fits the opcode | |
1227 | properly. E.g., | |
1228 | ||
1229 | .i32.i32.s16 | |
1230 | .s32.f32 | |
1231 | .u16 | |
1232 | ||
1233 | Can all be legally parsed by this function. | |
1234 | ||
1235 | Fills in neon_type struct pointer with parsed information, and updates STR | |
1236 | to point after the parsed type specifier. Returns SUCCESS if this was a legal | |
1237 | type, FAIL if not. */ | |
1238 | ||
1239 | static int | |
1240 | parse_neon_type (struct neon_type *type, char **str) | |
1241 | { | |
1242 | char *ptr = *str; | |
1243 | ||
1244 | if (type) | |
1245 | type->elems = 0; | |
1246 | ||
1247 | while (type->elems < NEON_MAX_TYPE_ELS) | |
1248 | { | |
1249 | enum neon_el_type thistype = NT_untyped; | |
1250 | unsigned thissize = -1u; | |
1251 | ||
1252 | if (*ptr != '.') | |
1253 | break; | |
1254 | ||
1255 | ptr++; | |
1256 | ||
1257 | /* Just a size without an explicit type. */ | |
1258 | if (ISDIGIT (*ptr)) | |
1259 | goto parsesize; | |
1260 | ||
1261 | switch (TOLOWER (*ptr)) | |
1262 | { | |
1263 | case 'i': thistype = NT_integer; break; | |
1264 | case 'f': thistype = NT_float; break; | |
1265 | case 'p': thistype = NT_poly; break; | |
1266 | case 's': thistype = NT_signed; break; | |
1267 | case 'u': thistype = NT_unsigned; break; | |
037e8744 JB |
1268 | case 'd': |
1269 | thistype = NT_float; | |
1270 | thissize = 64; | |
1271 | ptr++; | |
1272 | goto done; | |
dcbf9037 JB |
1273 | default: |
1274 | as_bad (_("unexpected character `%c' in type specifier"), *ptr); | |
1275 | return FAIL; | |
1276 | } | |
1277 | ||
1278 | ptr++; | |
1279 | ||
1280 | /* .f is an abbreviation for .f32. */ | |
1281 | if (thistype == NT_float && !ISDIGIT (*ptr)) | |
1282 | thissize = 32; | |
1283 | else | |
1284 | { | |
1285 | parsesize: | |
1286 | thissize = strtoul (ptr, &ptr, 10); | |
1287 | ||
1288 | if (thissize != 8 && thissize != 16 && thissize != 32 | |
1289 | && thissize != 64) | |
1290 | { | |
1291 | as_bad (_("bad size %d in type specifier"), thissize); | |
1292 | return FAIL; | |
1293 | } | |
1294 | } | |
1295 | ||
037e8744 | 1296 | done: |
dcbf9037 JB |
1297 | if (type) |
1298 | { | |
1299 | type->el[type->elems].type = thistype; | |
1300 | type->el[type->elems].size = thissize; | |
1301 | type->elems++; | |
1302 | } | |
1303 | } | |
1304 | ||
1305 | /* Empty/missing type is not a successful parse. */ | |
1306 | if (type->elems == 0) | |
1307 | return FAIL; | |
1308 | ||
1309 | *str = ptr; | |
1310 | ||
1311 | return SUCCESS; | |
1312 | } | |
1313 | ||
1314 | /* Errors may be set multiple times during parsing or bit encoding | |
1315 | (particularly in the Neon bits), but usually the earliest error which is set | |
1316 | will be the most meaningful. Avoid overwriting it with later (cascading) | |
1317 | errors by calling this function. */ | |
1318 | ||
1319 | static void | |
1320 | first_error (const char *err) | |
1321 | { | |
1322 | if (!inst.error) | |
1323 | inst.error = err; | |
1324 | } | |
1325 | ||
1326 | /* Parse a single type, e.g. ".s32", leading period included. */ | |
1327 | static int | |
1328 | parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) | |
1329 | { | |
1330 | char *str = *ccp; | |
1331 | struct neon_type optype; | |
1332 | ||
1333 | if (*str == '.') | |
1334 | { | |
1335 | if (parse_neon_type (&optype, &str) == SUCCESS) | |
1336 | { | |
1337 | if (optype.elems == 1) | |
1338 | *vectype = optype.el[0]; | |
1339 | else | |
1340 | { | |
1341 | first_error (_("only one type should be specified for operand")); | |
1342 | return FAIL; | |
1343 | } | |
1344 | } | |
1345 | else | |
1346 | { | |
1347 | first_error (_("vector type expected")); | |
1348 | return FAIL; | |
1349 | } | |
1350 | } | |
1351 | else | |
1352 | return FAIL; | |
5f4273c7 | 1353 | |
dcbf9037 | 1354 | *ccp = str; |
5f4273c7 | 1355 | |
dcbf9037 JB |
1356 | return SUCCESS; |
1357 | } | |
1358 | ||
1359 | /* Special meanings for indices (which have a range of 0-7), which will fit into | |
1360 | a 4-bit integer. */ | |
1361 | ||
1362 | #define NEON_ALL_LANES 15 | |
1363 | #define NEON_INTERLEAVE_LANES 14 | |
1364 | ||
1365 | /* Parse either a register or a scalar, with an optional type. Return the | |
1366 | register number, and optionally fill in the actual type of the register | |
1367 | when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and | |
1368 | type/index information in *TYPEINFO. */ | |
1369 | ||
1370 | static int | |
1371 | parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, | |
1372 | enum arm_reg_type *rtype, | |
1373 | struct neon_typed_alias *typeinfo) | |
1374 | { | |
1375 | char *str = *ccp; | |
1376 | struct reg_entry *reg = arm_reg_parse_multi (&str); | |
1377 | struct neon_typed_alias atype; | |
1378 | struct neon_type_el parsetype; | |
1379 | ||
1380 | atype.defined = 0; | |
1381 | atype.index = -1; | |
1382 | atype.eltype.type = NT_invtype; | |
1383 | atype.eltype.size = -1; | |
1384 | ||
1385 | /* Try alternate syntax for some types of register. Note these are mutually | |
1386 | exclusive with the Neon syntax extensions. */ | |
1387 | if (reg == NULL) | |
1388 | { | |
1389 | int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); | |
1390 | if (altreg != FAIL) | |
1391 | *ccp = str; | |
1392 | if (typeinfo) | |
1393 | *typeinfo = atype; | |
1394 | return altreg; | |
1395 | } | |
1396 | ||
037e8744 JB |
1397 | /* Undo polymorphism when a set of register types may be accepted. */ |
1398 | if ((type == REG_TYPE_NDQ | |
1399 | && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) | |
1400 | || (type == REG_TYPE_VFSD | |
1401 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) | |
1402 | || (type == REG_TYPE_NSDQ | |
1403 | && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD | |
f512f76f NC |
1404 | || reg->type == REG_TYPE_NQ)) |
1405 | || (type == REG_TYPE_MMXWC | |
1406 | && (reg->type == REG_TYPE_MMXWCG))) | |
21d799b5 | 1407 | type = (enum arm_reg_type) reg->type; |
dcbf9037 JB |
1408 | |
1409 | if (type != reg->type) | |
1410 | return FAIL; | |
1411 | ||
1412 | if (reg->neon) | |
1413 | atype = *reg->neon; | |
5f4273c7 | 1414 | |
dcbf9037 JB |
1415 | if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) |
1416 | { | |
1417 | if ((atype.defined & NTA_HASTYPE) != 0) | |
1418 | { | |
1419 | first_error (_("can't redefine type for operand")); | |
1420 | return FAIL; | |
1421 | } | |
1422 | atype.defined |= NTA_HASTYPE; | |
1423 | atype.eltype = parsetype; | |
1424 | } | |
5f4273c7 | 1425 | |
dcbf9037 JB |
1426 | if (skip_past_char (&str, '[') == SUCCESS) |
1427 | { | |
1428 | if (type != REG_TYPE_VFD) | |
1429 | { | |
1430 | first_error (_("only D registers may be indexed")); | |
1431 | return FAIL; | |
1432 | } | |
5f4273c7 | 1433 | |
dcbf9037 JB |
1434 | if ((atype.defined & NTA_HASINDEX) != 0) |
1435 | { | |
1436 | first_error (_("can't change index for operand")); | |
1437 | return FAIL; | |
1438 | } | |
1439 | ||
1440 | atype.defined |= NTA_HASINDEX; | |
1441 | ||
1442 | if (skip_past_char (&str, ']') == SUCCESS) | |
1443 | atype.index = NEON_ALL_LANES; | |
1444 | else | |
1445 | { | |
1446 | expressionS exp; | |
1447 | ||
1448 | my_get_expression (&exp, &str, GE_NO_PREFIX); | |
1449 | ||
1450 | if (exp.X_op != O_constant) | |
1451 | { | |
1452 | first_error (_("constant expression required")); | |
1453 | return FAIL; | |
1454 | } | |
1455 | ||
1456 | if (skip_past_char (&str, ']') == FAIL) | |
1457 | return FAIL; | |
1458 | ||
1459 | atype.index = exp.X_add_number; | |
1460 | } | |
1461 | } | |
5f4273c7 | 1462 | |
dcbf9037 JB |
1463 | if (typeinfo) |
1464 | *typeinfo = atype; | |
5f4273c7 | 1465 | |
dcbf9037 JB |
1466 | if (rtype) |
1467 | *rtype = type; | |
5f4273c7 | 1468 | |
dcbf9037 | 1469 | *ccp = str; |
5f4273c7 | 1470 | |
dcbf9037 JB |
1471 | return reg->number; |
1472 | } | |
1473 | ||
1474 | /* Like arm_reg_parse, but allow allow the following extra features: | |
1475 | - If RTYPE is non-zero, return the (possibly restricted) type of the | |
1476 | register (e.g. Neon double or quad reg when either has been requested). | |
1477 | - If this is a Neon vector type with additional type information, fill | |
1478 | in the struct pointed to by VECTYPE (if non-NULL). | |
5f4273c7 | 1479 | This function will fault on encountering a scalar. */ |
dcbf9037 JB |
1480 | |
1481 | static int | |
1482 | arm_typed_reg_parse (char **ccp, enum arm_reg_type type, | |
1483 | enum arm_reg_type *rtype, struct neon_type_el *vectype) | |
1484 | { | |
1485 | struct neon_typed_alias atype; | |
1486 | char *str = *ccp; | |
1487 | int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); | |
1488 | ||
1489 | if (reg == FAIL) | |
1490 | return FAIL; | |
1491 | ||
0855e32b NS |
1492 | /* Do not allow regname(... to parse as a register. */ |
1493 | if (*str == '(') | |
1494 | return FAIL; | |
1495 | ||
dcbf9037 JB |
1496 | /* Do not allow a scalar (reg+index) to parse as a register. */ |
1497 | if ((atype.defined & NTA_HASINDEX) != 0) | |
1498 | { | |
1499 | first_error (_("register operand expected, but got scalar")); | |
1500 | return FAIL; | |
1501 | } | |
1502 | ||
1503 | if (vectype) | |
1504 | *vectype = atype.eltype; | |
1505 | ||
1506 | *ccp = str; | |
1507 | ||
1508 | return reg; | |
1509 | } | |
1510 | ||
1511 | #define NEON_SCALAR_REG(X) ((X) >> 4) | |
1512 | #define NEON_SCALAR_INDEX(X) ((X) & 15) | |
1513 | ||
5287ad62 JB |
1514 | /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't |
1515 | have enough information to be able to do a good job bounds-checking. So, we | |
1516 | just do easy checks here, and do further checks later. */ | |
1517 | ||
1518 | static int | |
dcbf9037 | 1519 | parse_scalar (char **ccp, int elsize, struct neon_type_el *type) |
5287ad62 | 1520 | { |
dcbf9037 | 1521 | int reg; |
5287ad62 | 1522 | char *str = *ccp; |
dcbf9037 | 1523 | struct neon_typed_alias atype; |
5f4273c7 | 1524 | |
dcbf9037 | 1525 | reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); |
5f4273c7 | 1526 | |
dcbf9037 | 1527 | if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) |
5287ad62 | 1528 | return FAIL; |
5f4273c7 | 1529 | |
dcbf9037 | 1530 | if (atype.index == NEON_ALL_LANES) |
5287ad62 | 1531 | { |
dcbf9037 | 1532 | first_error (_("scalar must have an index")); |
5287ad62 JB |
1533 | return FAIL; |
1534 | } | |
dcbf9037 | 1535 | else if (atype.index >= 64 / elsize) |
5287ad62 | 1536 | { |
dcbf9037 | 1537 | first_error (_("scalar index out of range")); |
5287ad62 JB |
1538 | return FAIL; |
1539 | } | |
5f4273c7 | 1540 | |
dcbf9037 JB |
1541 | if (type) |
1542 | *type = atype.eltype; | |
5f4273c7 | 1543 | |
5287ad62 | 1544 | *ccp = str; |
5f4273c7 | 1545 | |
dcbf9037 | 1546 | return reg * 16 + atype.index; |
5287ad62 JB |
1547 | } |
1548 | ||
c19d1205 | 1549 | /* Parse an ARM register list. Returns the bitmask, or FAIL. */ |
e07e6e58 | 1550 | |
c19d1205 ZW |
1551 | static long |
1552 | parse_reg_list (char ** strp) | |
1553 | { | |
1554 | char * str = * strp; | |
1555 | long range = 0; | |
1556 | int another_range; | |
a737bd4d | 1557 | |
c19d1205 ZW |
1558 | /* We come back here if we get ranges concatenated by '+' or '|'. */ |
1559 | do | |
6057a28f | 1560 | { |
c19d1205 | 1561 | another_range = 0; |
a737bd4d | 1562 | |
c19d1205 ZW |
1563 | if (*str == '{') |
1564 | { | |
1565 | int in_range = 0; | |
1566 | int cur_reg = -1; | |
a737bd4d | 1567 | |
c19d1205 ZW |
1568 | str++; |
1569 | do | |
1570 | { | |
1571 | int reg; | |
6057a28f | 1572 | |
dcbf9037 | 1573 | if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) |
c19d1205 | 1574 | { |
dcbf9037 | 1575 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 ZW |
1576 | return FAIL; |
1577 | } | |
a737bd4d | 1578 | |
c19d1205 ZW |
1579 | if (in_range) |
1580 | { | |
1581 | int i; | |
a737bd4d | 1582 | |
c19d1205 ZW |
1583 | if (reg <= cur_reg) |
1584 | { | |
dcbf9037 | 1585 | first_error (_("bad range in register list")); |
c19d1205 ZW |
1586 | return FAIL; |
1587 | } | |
40a18ebd | 1588 | |
c19d1205 ZW |
1589 | for (i = cur_reg + 1; i < reg; i++) |
1590 | { | |
1591 | if (range & (1 << i)) | |
1592 | as_tsktsk | |
1593 | (_("Warning: duplicated register (r%d) in register list"), | |
1594 | i); | |
1595 | else | |
1596 | range |= 1 << i; | |
1597 | } | |
1598 | in_range = 0; | |
1599 | } | |
a737bd4d | 1600 | |
c19d1205 ZW |
1601 | if (range & (1 << reg)) |
1602 | as_tsktsk (_("Warning: duplicated register (r%d) in register list"), | |
1603 | reg); | |
1604 | else if (reg <= cur_reg) | |
1605 | as_tsktsk (_("Warning: register range not in ascending order")); | |
a737bd4d | 1606 | |
c19d1205 ZW |
1607 | range |= 1 << reg; |
1608 | cur_reg = reg; | |
1609 | } | |
1610 | while (skip_past_comma (&str) != FAIL | |
1611 | || (in_range = 1, *str++ == '-')); | |
1612 | str--; | |
a737bd4d | 1613 | |
c19d1205 ZW |
1614 | if (*str++ != '}') |
1615 | { | |
dcbf9037 | 1616 | first_error (_("missing `}'")); |
c19d1205 ZW |
1617 | return FAIL; |
1618 | } | |
1619 | } | |
1620 | else | |
1621 | { | |
91d6fa6a | 1622 | expressionS exp; |
40a18ebd | 1623 | |
91d6fa6a | 1624 | if (my_get_expression (&exp, &str, GE_NO_PREFIX)) |
c19d1205 | 1625 | return FAIL; |
40a18ebd | 1626 | |
91d6fa6a | 1627 | if (exp.X_op == O_constant) |
c19d1205 | 1628 | { |
91d6fa6a NC |
1629 | if (exp.X_add_number |
1630 | != (exp.X_add_number & 0x0000ffff)) | |
c19d1205 ZW |
1631 | { |
1632 | inst.error = _("invalid register mask"); | |
1633 | return FAIL; | |
1634 | } | |
a737bd4d | 1635 | |
91d6fa6a | 1636 | if ((range & exp.X_add_number) != 0) |
c19d1205 | 1637 | { |
91d6fa6a | 1638 | int regno = range & exp.X_add_number; |
a737bd4d | 1639 | |
c19d1205 ZW |
1640 | regno &= -regno; |
1641 | regno = (1 << regno) - 1; | |
1642 | as_tsktsk | |
1643 | (_("Warning: duplicated register (r%d) in register list"), | |
1644 | regno); | |
1645 | } | |
a737bd4d | 1646 | |
91d6fa6a | 1647 | range |= exp.X_add_number; |
c19d1205 ZW |
1648 | } |
1649 | else | |
1650 | { | |
1651 | if (inst.reloc.type != 0) | |
1652 | { | |
1653 | inst.error = _("expression too complex"); | |
1654 | return FAIL; | |
1655 | } | |
a737bd4d | 1656 | |
91d6fa6a | 1657 | memcpy (&inst.reloc.exp, &exp, sizeof (expressionS)); |
c19d1205 ZW |
1658 | inst.reloc.type = BFD_RELOC_ARM_MULTI; |
1659 | inst.reloc.pc_rel = 0; | |
1660 | } | |
1661 | } | |
a737bd4d | 1662 | |
c19d1205 ZW |
1663 | if (*str == '|' || *str == '+') |
1664 | { | |
1665 | str++; | |
1666 | another_range = 1; | |
1667 | } | |
a737bd4d | 1668 | } |
c19d1205 | 1669 | while (another_range); |
a737bd4d | 1670 | |
c19d1205 ZW |
1671 | *strp = str; |
1672 | return range; | |
a737bd4d NC |
1673 | } |
1674 | ||
5287ad62 JB |
1675 | /* Types of registers in a list. */ |
1676 | ||
1677 | enum reg_list_els | |
1678 | { | |
1679 | REGLIST_VFP_S, | |
1680 | REGLIST_VFP_D, | |
1681 | REGLIST_NEON_D | |
1682 | }; | |
1683 | ||
c19d1205 ZW |
1684 | /* Parse a VFP register list. If the string is invalid return FAIL. |
1685 | Otherwise return the number of registers, and set PBASE to the first | |
5287ad62 JB |
1686 | register. Parses registers of type ETYPE. |
1687 | If REGLIST_NEON_D is used, several syntax enhancements are enabled: | |
1688 | - Q registers can be used to specify pairs of D registers | |
1689 | - { } can be omitted from around a singleton register list | |
1690 | FIXME: This is not implemented, as it would require backtracking in | |
1691 | some cases, e.g.: | |
1692 | vtbl.8 d3,d4,d5 | |
1693 | This could be done (the meaning isn't really ambiguous), but doesn't | |
1694 | fit in well with the current parsing framework. | |
dcbf9037 JB |
1695 | - 32 D registers may be used (also true for VFPv3). |
1696 | FIXME: Types are ignored in these register lists, which is probably a | |
1697 | bug. */ | |
6057a28f | 1698 | |
c19d1205 | 1699 | static int |
037e8744 | 1700 | parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) |
6057a28f | 1701 | { |
037e8744 | 1702 | char *str = *ccp; |
c19d1205 ZW |
1703 | int base_reg; |
1704 | int new_base; | |
21d799b5 | 1705 | enum arm_reg_type regtype = (enum arm_reg_type) 0; |
5287ad62 | 1706 | int max_regs = 0; |
c19d1205 ZW |
1707 | int count = 0; |
1708 | int warned = 0; | |
1709 | unsigned long mask = 0; | |
a737bd4d | 1710 | int i; |
6057a28f | 1711 | |
037e8744 | 1712 | if (*str != '{') |
5287ad62 JB |
1713 | { |
1714 | inst.error = _("expecting {"); | |
1715 | return FAIL; | |
1716 | } | |
6057a28f | 1717 | |
037e8744 | 1718 | str++; |
6057a28f | 1719 | |
5287ad62 | 1720 | switch (etype) |
c19d1205 | 1721 | { |
5287ad62 | 1722 | case REGLIST_VFP_S: |
c19d1205 ZW |
1723 | regtype = REG_TYPE_VFS; |
1724 | max_regs = 32; | |
5287ad62 | 1725 | break; |
5f4273c7 | 1726 | |
5287ad62 JB |
1727 | case REGLIST_VFP_D: |
1728 | regtype = REG_TYPE_VFD; | |
b7fc2769 | 1729 | break; |
5f4273c7 | 1730 | |
b7fc2769 JB |
1731 | case REGLIST_NEON_D: |
1732 | regtype = REG_TYPE_NDQ; | |
1733 | break; | |
1734 | } | |
1735 | ||
1736 | if (etype != REGLIST_VFP_S) | |
1737 | { | |
b1cc4aeb PB |
1738 | /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */ |
1739 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) | |
5287ad62 JB |
1740 | { |
1741 | max_regs = 32; | |
1742 | if (thumb_mode) | |
1743 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 1744 | fpu_vfp_ext_d32); |
5287ad62 JB |
1745 | else |
1746 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 1747 | fpu_vfp_ext_d32); |
5287ad62 JB |
1748 | } |
1749 | else | |
1750 | max_regs = 16; | |
c19d1205 | 1751 | } |
6057a28f | 1752 | |
c19d1205 | 1753 | base_reg = max_regs; |
a737bd4d | 1754 | |
c19d1205 ZW |
1755 | do |
1756 | { | |
5287ad62 | 1757 | int setmask = 1, addregs = 1; |
dcbf9037 | 1758 | |
037e8744 | 1759 | new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); |
dcbf9037 | 1760 | |
c19d1205 | 1761 | if (new_base == FAIL) |
a737bd4d | 1762 | { |
dcbf9037 | 1763 | first_error (_(reg_expected_msgs[regtype])); |
c19d1205 ZW |
1764 | return FAIL; |
1765 | } | |
5f4273c7 | 1766 | |
b7fc2769 JB |
1767 | if (new_base >= max_regs) |
1768 | { | |
1769 | first_error (_("register out of range in list")); | |
1770 | return FAIL; | |
1771 | } | |
5f4273c7 | 1772 | |
5287ad62 JB |
1773 | /* Note: a value of 2 * n is returned for the register Q<n>. */ |
1774 | if (regtype == REG_TYPE_NQ) | |
1775 | { | |
1776 | setmask = 3; | |
1777 | addregs = 2; | |
1778 | } | |
1779 | ||
c19d1205 ZW |
1780 | if (new_base < base_reg) |
1781 | base_reg = new_base; | |
a737bd4d | 1782 | |
5287ad62 | 1783 | if (mask & (setmask << new_base)) |
c19d1205 | 1784 | { |
dcbf9037 | 1785 | first_error (_("invalid register list")); |
c19d1205 | 1786 | return FAIL; |
a737bd4d | 1787 | } |
a737bd4d | 1788 | |
c19d1205 ZW |
1789 | if ((mask >> new_base) != 0 && ! warned) |
1790 | { | |
1791 | as_tsktsk (_("register list not in ascending order")); | |
1792 | warned = 1; | |
1793 | } | |
0bbf2aa4 | 1794 | |
5287ad62 JB |
1795 | mask |= setmask << new_base; |
1796 | count += addregs; | |
0bbf2aa4 | 1797 | |
037e8744 | 1798 | if (*str == '-') /* We have the start of a range expression */ |
c19d1205 ZW |
1799 | { |
1800 | int high_range; | |
0bbf2aa4 | 1801 | |
037e8744 | 1802 | str++; |
0bbf2aa4 | 1803 | |
037e8744 | 1804 | if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) |
dcbf9037 | 1805 | == FAIL) |
c19d1205 ZW |
1806 | { |
1807 | inst.error = gettext (reg_expected_msgs[regtype]); | |
1808 | return FAIL; | |
1809 | } | |
0bbf2aa4 | 1810 | |
b7fc2769 JB |
1811 | if (high_range >= max_regs) |
1812 | { | |
1813 | first_error (_("register out of range in list")); | |
1814 | return FAIL; | |
1815 | } | |
1816 | ||
5287ad62 JB |
1817 | if (regtype == REG_TYPE_NQ) |
1818 | high_range = high_range + 1; | |
1819 | ||
c19d1205 ZW |
1820 | if (high_range <= new_base) |
1821 | { | |
1822 | inst.error = _("register range not in ascending order"); | |
1823 | return FAIL; | |
1824 | } | |
0bbf2aa4 | 1825 | |
5287ad62 | 1826 | for (new_base += addregs; new_base <= high_range; new_base += addregs) |
0bbf2aa4 | 1827 | { |
5287ad62 | 1828 | if (mask & (setmask << new_base)) |
0bbf2aa4 | 1829 | { |
c19d1205 ZW |
1830 | inst.error = _("invalid register list"); |
1831 | return FAIL; | |
0bbf2aa4 | 1832 | } |
c19d1205 | 1833 | |
5287ad62 JB |
1834 | mask |= setmask << new_base; |
1835 | count += addregs; | |
0bbf2aa4 | 1836 | } |
0bbf2aa4 | 1837 | } |
0bbf2aa4 | 1838 | } |
037e8744 | 1839 | while (skip_past_comma (&str) != FAIL); |
0bbf2aa4 | 1840 | |
037e8744 | 1841 | str++; |
0bbf2aa4 | 1842 | |
c19d1205 ZW |
1843 | /* Sanity check -- should have raised a parse error above. */ |
1844 | if (count == 0 || count > max_regs) | |
1845 | abort (); | |
1846 | ||
1847 | *pbase = base_reg; | |
1848 | ||
1849 | /* Final test -- the registers must be consecutive. */ | |
1850 | mask >>= base_reg; | |
1851 | for (i = 0; i < count; i++) | |
1852 | { | |
1853 | if ((mask & (1u << i)) == 0) | |
1854 | { | |
1855 | inst.error = _("non-contiguous register range"); | |
1856 | return FAIL; | |
1857 | } | |
1858 | } | |
1859 | ||
037e8744 JB |
1860 | *ccp = str; |
1861 | ||
c19d1205 | 1862 | return count; |
b99bd4ef NC |
1863 | } |
1864 | ||
dcbf9037 JB |
1865 | /* True if two alias types are the same. */ |
1866 | ||
c921be7d | 1867 | static bfd_boolean |
dcbf9037 JB |
1868 | neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) |
1869 | { | |
1870 | if (!a && !b) | |
c921be7d | 1871 | return TRUE; |
5f4273c7 | 1872 | |
dcbf9037 | 1873 | if (!a || !b) |
c921be7d | 1874 | return FALSE; |
dcbf9037 JB |
1875 | |
1876 | if (a->defined != b->defined) | |
c921be7d | 1877 | return FALSE; |
5f4273c7 | 1878 | |
dcbf9037 JB |
1879 | if ((a->defined & NTA_HASTYPE) != 0 |
1880 | && (a->eltype.type != b->eltype.type | |
1881 | || a->eltype.size != b->eltype.size)) | |
c921be7d | 1882 | return FALSE; |
dcbf9037 JB |
1883 | |
1884 | if ((a->defined & NTA_HASINDEX) != 0 | |
1885 | && (a->index != b->index)) | |
c921be7d | 1886 | return FALSE; |
5f4273c7 | 1887 | |
c921be7d | 1888 | return TRUE; |
dcbf9037 JB |
1889 | } |
1890 | ||
5287ad62 JB |
1891 | /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. |
1892 | The base register is put in *PBASE. | |
dcbf9037 | 1893 | The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of |
5287ad62 JB |
1894 | the return value. |
1895 | The register stride (minus one) is put in bit 4 of the return value. | |
dcbf9037 JB |
1896 | Bits [6:5] encode the list length (minus one). |
1897 | The type of the list elements is put in *ELTYPE, if non-NULL. */ | |
5287ad62 | 1898 | |
5287ad62 | 1899 | #define NEON_LANE(X) ((X) & 0xf) |
dcbf9037 | 1900 | #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) |
5287ad62 JB |
1901 | #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) |
1902 | ||
1903 | static int | |
dcbf9037 JB |
1904 | parse_neon_el_struct_list (char **str, unsigned *pbase, |
1905 | struct neon_type_el *eltype) | |
5287ad62 JB |
1906 | { |
1907 | char *ptr = *str; | |
1908 | int base_reg = -1; | |
1909 | int reg_incr = -1; | |
1910 | int count = 0; | |
1911 | int lane = -1; | |
1912 | int leading_brace = 0; | |
1913 | enum arm_reg_type rtype = REG_TYPE_NDQ; | |
20203fb9 NC |
1914 | const char *const incr_error = _("register stride must be 1 or 2"); |
1915 | const char *const type_error = _("mismatched element/structure types in list"); | |
dcbf9037 | 1916 | struct neon_typed_alias firsttype; |
5f4273c7 | 1917 | |
5287ad62 JB |
1918 | if (skip_past_char (&ptr, '{') == SUCCESS) |
1919 | leading_brace = 1; | |
5f4273c7 | 1920 | |
5287ad62 JB |
1921 | do |
1922 | { | |
dcbf9037 JB |
1923 | struct neon_typed_alias atype; |
1924 | int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); | |
1925 | ||
5287ad62 JB |
1926 | if (getreg == FAIL) |
1927 | { | |
dcbf9037 | 1928 | first_error (_(reg_expected_msgs[rtype])); |
5287ad62 JB |
1929 | return FAIL; |
1930 | } | |
5f4273c7 | 1931 | |
5287ad62 JB |
1932 | if (base_reg == -1) |
1933 | { | |
1934 | base_reg = getreg; | |
1935 | if (rtype == REG_TYPE_NQ) | |
1936 | { | |
1937 | reg_incr = 1; | |
5287ad62 | 1938 | } |
dcbf9037 | 1939 | firsttype = atype; |
5287ad62 JB |
1940 | } |
1941 | else if (reg_incr == -1) | |
1942 | { | |
1943 | reg_incr = getreg - base_reg; | |
1944 | if (reg_incr < 1 || reg_incr > 2) | |
1945 | { | |
dcbf9037 | 1946 | first_error (_(incr_error)); |
5287ad62 JB |
1947 | return FAIL; |
1948 | } | |
1949 | } | |
1950 | else if (getreg != base_reg + reg_incr * count) | |
1951 | { | |
dcbf9037 JB |
1952 | first_error (_(incr_error)); |
1953 | return FAIL; | |
1954 | } | |
1955 | ||
c921be7d | 1956 | if (! neon_alias_types_same (&atype, &firsttype)) |
dcbf9037 JB |
1957 | { |
1958 | first_error (_(type_error)); | |
5287ad62 JB |
1959 | return FAIL; |
1960 | } | |
5f4273c7 | 1961 | |
5287ad62 JB |
1962 | /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list |
1963 | modes. */ | |
1964 | if (ptr[0] == '-') | |
1965 | { | |
dcbf9037 | 1966 | struct neon_typed_alias htype; |
5287ad62 JB |
1967 | int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; |
1968 | if (lane == -1) | |
1969 | lane = NEON_INTERLEAVE_LANES; | |
1970 | else if (lane != NEON_INTERLEAVE_LANES) | |
1971 | { | |
dcbf9037 | 1972 | first_error (_(type_error)); |
5287ad62 JB |
1973 | return FAIL; |
1974 | } | |
1975 | if (reg_incr == -1) | |
1976 | reg_incr = 1; | |
1977 | else if (reg_incr != 1) | |
1978 | { | |
dcbf9037 | 1979 | first_error (_("don't use Rn-Rm syntax with non-unit stride")); |
5287ad62 JB |
1980 | return FAIL; |
1981 | } | |
1982 | ptr++; | |
dcbf9037 | 1983 | hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); |
5287ad62 JB |
1984 | if (hireg == FAIL) |
1985 | { | |
dcbf9037 JB |
1986 | first_error (_(reg_expected_msgs[rtype])); |
1987 | return FAIL; | |
1988 | } | |
c921be7d | 1989 | if (! neon_alias_types_same (&htype, &firsttype)) |
dcbf9037 JB |
1990 | { |
1991 | first_error (_(type_error)); | |
5287ad62 JB |
1992 | return FAIL; |
1993 | } | |
1994 | count += hireg + dregs - getreg; | |
1995 | continue; | |
1996 | } | |
5f4273c7 | 1997 | |
5287ad62 JB |
1998 | /* If we're using Q registers, we can't use [] or [n] syntax. */ |
1999 | if (rtype == REG_TYPE_NQ) | |
2000 | { | |
2001 | count += 2; | |
2002 | continue; | |
2003 | } | |
5f4273c7 | 2004 | |
dcbf9037 | 2005 | if ((atype.defined & NTA_HASINDEX) != 0) |
5287ad62 | 2006 | { |
dcbf9037 JB |
2007 | if (lane == -1) |
2008 | lane = atype.index; | |
2009 | else if (lane != atype.index) | |
5287ad62 | 2010 | { |
dcbf9037 JB |
2011 | first_error (_(type_error)); |
2012 | return FAIL; | |
5287ad62 JB |
2013 | } |
2014 | } | |
2015 | else if (lane == -1) | |
2016 | lane = NEON_INTERLEAVE_LANES; | |
2017 | else if (lane != NEON_INTERLEAVE_LANES) | |
2018 | { | |
dcbf9037 | 2019 | first_error (_(type_error)); |
5287ad62 JB |
2020 | return FAIL; |
2021 | } | |
2022 | count++; | |
2023 | } | |
2024 | while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); | |
5f4273c7 | 2025 | |
5287ad62 JB |
2026 | /* No lane set by [x]. We must be interleaving structures. */ |
2027 | if (lane == -1) | |
2028 | lane = NEON_INTERLEAVE_LANES; | |
5f4273c7 | 2029 | |
5287ad62 JB |
2030 | /* Sanity check. */ |
2031 | if (lane == -1 || base_reg == -1 || count < 1 || count > 4 | |
2032 | || (count > 1 && reg_incr == -1)) | |
2033 | { | |
dcbf9037 | 2034 | first_error (_("error parsing element/structure list")); |
5287ad62 JB |
2035 | return FAIL; |
2036 | } | |
2037 | ||
2038 | if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) | |
2039 | { | |
dcbf9037 | 2040 | first_error (_("expected }")); |
5287ad62 JB |
2041 | return FAIL; |
2042 | } | |
5f4273c7 | 2043 | |
5287ad62 JB |
2044 | if (reg_incr == -1) |
2045 | reg_incr = 1; | |
2046 | ||
dcbf9037 JB |
2047 | if (eltype) |
2048 | *eltype = firsttype.eltype; | |
2049 | ||
5287ad62 JB |
2050 | *pbase = base_reg; |
2051 | *str = ptr; | |
5f4273c7 | 2052 | |
5287ad62 JB |
2053 | return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); |
2054 | } | |
2055 | ||
c19d1205 ZW |
2056 | /* Parse an explicit relocation suffix on an expression. This is |
2057 | either nothing, or a word in parentheses. Note that if !OBJ_ELF, | |
2058 | arm_reloc_hsh contains no entries, so this function can only | |
2059 | succeed if there is no () after the word. Returns -1 on error, | |
2060 | BFD_RELOC_UNUSED if there wasn't any suffix. */ | |
3da1d841 | 2061 | |
c19d1205 ZW |
2062 | static int |
2063 | parse_reloc (char **str) | |
b99bd4ef | 2064 | { |
c19d1205 ZW |
2065 | struct reloc_entry *r; |
2066 | char *p, *q; | |
b99bd4ef | 2067 | |
c19d1205 ZW |
2068 | if (**str != '(') |
2069 | return BFD_RELOC_UNUSED; | |
b99bd4ef | 2070 | |
c19d1205 ZW |
2071 | p = *str + 1; |
2072 | q = p; | |
2073 | ||
2074 | while (*q && *q != ')' && *q != ',') | |
2075 | q++; | |
2076 | if (*q != ')') | |
2077 | return -1; | |
2078 | ||
21d799b5 NC |
2079 | if ((r = (struct reloc_entry *) |
2080 | hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) | |
c19d1205 ZW |
2081 | return -1; |
2082 | ||
2083 | *str = q + 1; | |
2084 | return r->reloc; | |
b99bd4ef NC |
2085 | } |
2086 | ||
c19d1205 ZW |
2087 | /* Directives: register aliases. */ |
2088 | ||
dcbf9037 | 2089 | static struct reg_entry * |
90ec0d68 | 2090 | insert_reg_alias (char *str, unsigned number, int type) |
b99bd4ef | 2091 | { |
d3ce72d0 | 2092 | struct reg_entry *new_reg; |
c19d1205 | 2093 | const char *name; |
b99bd4ef | 2094 | |
d3ce72d0 | 2095 | if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0) |
c19d1205 | 2096 | { |
d3ce72d0 | 2097 | if (new_reg->builtin) |
c19d1205 | 2098 | as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); |
b99bd4ef | 2099 | |
c19d1205 ZW |
2100 | /* Only warn about a redefinition if it's not defined as the |
2101 | same register. */ | |
d3ce72d0 | 2102 | else if (new_reg->number != number || new_reg->type != type) |
c19d1205 | 2103 | as_warn (_("ignoring redefinition of register alias '%s'"), str); |
69b97547 | 2104 | |
d929913e | 2105 | return NULL; |
c19d1205 | 2106 | } |
b99bd4ef | 2107 | |
c19d1205 | 2108 | name = xstrdup (str); |
d3ce72d0 | 2109 | new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry)); |
b99bd4ef | 2110 | |
d3ce72d0 NC |
2111 | new_reg->name = name; |
2112 | new_reg->number = number; | |
2113 | new_reg->type = type; | |
2114 | new_reg->builtin = FALSE; | |
2115 | new_reg->neon = NULL; | |
b99bd4ef | 2116 | |
d3ce72d0 | 2117 | if (hash_insert (arm_reg_hsh, name, (void *) new_reg)) |
c19d1205 | 2118 | abort (); |
5f4273c7 | 2119 | |
d3ce72d0 | 2120 | return new_reg; |
dcbf9037 JB |
2121 | } |
2122 | ||
2123 | static void | |
2124 | insert_neon_reg_alias (char *str, int number, int type, | |
2125 | struct neon_typed_alias *atype) | |
2126 | { | |
2127 | struct reg_entry *reg = insert_reg_alias (str, number, type); | |
5f4273c7 | 2128 | |
dcbf9037 JB |
2129 | if (!reg) |
2130 | { | |
2131 | first_error (_("attempt to redefine typed alias")); | |
2132 | return; | |
2133 | } | |
5f4273c7 | 2134 | |
dcbf9037 JB |
2135 | if (atype) |
2136 | { | |
21d799b5 NC |
2137 | reg->neon = (struct neon_typed_alias *) |
2138 | xmalloc (sizeof (struct neon_typed_alias)); | |
dcbf9037 JB |
2139 | *reg->neon = *atype; |
2140 | } | |
c19d1205 | 2141 | } |
b99bd4ef | 2142 | |
c19d1205 | 2143 | /* Look for the .req directive. This is of the form: |
b99bd4ef | 2144 | |
c19d1205 | 2145 | new_register_name .req existing_register_name |
b99bd4ef | 2146 | |
c19d1205 | 2147 | If we find one, or if it looks sufficiently like one that we want to |
d929913e | 2148 | handle any error here, return TRUE. Otherwise return FALSE. */ |
b99bd4ef | 2149 | |
d929913e | 2150 | static bfd_boolean |
c19d1205 ZW |
2151 | create_register_alias (char * newname, char *p) |
2152 | { | |
2153 | struct reg_entry *old; | |
2154 | char *oldname, *nbuf; | |
2155 | size_t nlen; | |
b99bd4ef | 2156 | |
c19d1205 ZW |
2157 | /* The input scrubber ensures that whitespace after the mnemonic is |
2158 | collapsed to single spaces. */ | |
2159 | oldname = p; | |
2160 | if (strncmp (oldname, " .req ", 6) != 0) | |
d929913e | 2161 | return FALSE; |
b99bd4ef | 2162 | |
c19d1205 ZW |
2163 | oldname += 6; |
2164 | if (*oldname == '\0') | |
d929913e | 2165 | return FALSE; |
b99bd4ef | 2166 | |
21d799b5 | 2167 | old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname); |
c19d1205 | 2168 | if (!old) |
b99bd4ef | 2169 | { |
c19d1205 | 2170 | as_warn (_("unknown register '%s' -- .req ignored"), oldname); |
d929913e | 2171 | return TRUE; |
b99bd4ef NC |
2172 | } |
2173 | ||
c19d1205 ZW |
2174 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2175 | the desired alias name, and p points to its end. If not, then | |
2176 | the desired alias name is in the global original_case_string. */ | |
2177 | #ifdef TC_CASE_SENSITIVE | |
2178 | nlen = p - newname; | |
2179 | #else | |
2180 | newname = original_case_string; | |
2181 | nlen = strlen (newname); | |
2182 | #endif | |
b99bd4ef | 2183 | |
21d799b5 | 2184 | nbuf = (char *) alloca (nlen + 1); |
c19d1205 ZW |
2185 | memcpy (nbuf, newname, nlen); |
2186 | nbuf[nlen] = '\0'; | |
b99bd4ef | 2187 | |
c19d1205 ZW |
2188 | /* Create aliases under the new name as stated; an all-lowercase |
2189 | version of the new name; and an all-uppercase version of the new | |
2190 | name. */ | |
d929913e NC |
2191 | if (insert_reg_alias (nbuf, old->number, old->type) != NULL) |
2192 | { | |
2193 | for (p = nbuf; *p; p++) | |
2194 | *p = TOUPPER (*p); | |
c19d1205 | 2195 | |
d929913e NC |
2196 | if (strncmp (nbuf, newname, nlen)) |
2197 | { | |
2198 | /* If this attempt to create an additional alias fails, do not bother | |
2199 | trying to create the all-lower case alias. We will fail and issue | |
2200 | a second, duplicate error message. This situation arises when the | |
2201 | programmer does something like: | |
2202 | foo .req r0 | |
2203 | Foo .req r1 | |
2204 | The second .req creates the "Foo" alias but then fails to create | |
5f4273c7 | 2205 | the artificial FOO alias because it has already been created by the |
d929913e NC |
2206 | first .req. */ |
2207 | if (insert_reg_alias (nbuf, old->number, old->type) == NULL) | |
2208 | return TRUE; | |
2209 | } | |
c19d1205 | 2210 | |
d929913e NC |
2211 | for (p = nbuf; *p; p++) |
2212 | *p = TOLOWER (*p); | |
c19d1205 | 2213 | |
d929913e NC |
2214 | if (strncmp (nbuf, newname, nlen)) |
2215 | insert_reg_alias (nbuf, old->number, old->type); | |
2216 | } | |
c19d1205 | 2217 | |
d929913e | 2218 | return TRUE; |
b99bd4ef NC |
2219 | } |
2220 | ||
dcbf9037 JB |
2221 | /* Create a Neon typed/indexed register alias using directives, e.g.: |
2222 | X .dn d5.s32[1] | |
2223 | Y .qn 6.s16 | |
2224 | Z .dn d7 | |
2225 | T .dn Z[0] | |
2226 | These typed registers can be used instead of the types specified after the | |
2227 | Neon mnemonic, so long as all operands given have types. Types can also be | |
2228 | specified directly, e.g.: | |
5f4273c7 | 2229 | vadd d0.s32, d1.s32, d2.s32 */ |
dcbf9037 | 2230 | |
c921be7d | 2231 | static bfd_boolean |
dcbf9037 JB |
2232 | create_neon_reg_alias (char *newname, char *p) |
2233 | { | |
2234 | enum arm_reg_type basetype; | |
2235 | struct reg_entry *basereg; | |
2236 | struct reg_entry mybasereg; | |
2237 | struct neon_type ntype; | |
2238 | struct neon_typed_alias typeinfo; | |
12d6b0b7 | 2239 | char *namebuf, *nameend ATTRIBUTE_UNUSED; |
dcbf9037 | 2240 | int namelen; |
5f4273c7 | 2241 | |
dcbf9037 JB |
2242 | typeinfo.defined = 0; |
2243 | typeinfo.eltype.type = NT_invtype; | |
2244 | typeinfo.eltype.size = -1; | |
2245 | typeinfo.index = -1; | |
5f4273c7 | 2246 | |
dcbf9037 | 2247 | nameend = p; |
5f4273c7 | 2248 | |
dcbf9037 JB |
2249 | if (strncmp (p, " .dn ", 5) == 0) |
2250 | basetype = REG_TYPE_VFD; | |
2251 | else if (strncmp (p, " .qn ", 5) == 0) | |
2252 | basetype = REG_TYPE_NQ; | |
2253 | else | |
c921be7d | 2254 | return FALSE; |
5f4273c7 | 2255 | |
dcbf9037 | 2256 | p += 5; |
5f4273c7 | 2257 | |
dcbf9037 | 2258 | if (*p == '\0') |
c921be7d | 2259 | return FALSE; |
5f4273c7 | 2260 | |
dcbf9037 JB |
2261 | basereg = arm_reg_parse_multi (&p); |
2262 | ||
2263 | if (basereg && basereg->type != basetype) | |
2264 | { | |
2265 | as_bad (_("bad type for register")); | |
c921be7d | 2266 | return FALSE; |
dcbf9037 JB |
2267 | } |
2268 | ||
2269 | if (basereg == NULL) | |
2270 | { | |
2271 | expressionS exp; | |
2272 | /* Try parsing as an integer. */ | |
2273 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
2274 | if (exp.X_op != O_constant) | |
2275 | { | |
2276 | as_bad (_("expression must be constant")); | |
c921be7d | 2277 | return FALSE; |
dcbf9037 JB |
2278 | } |
2279 | basereg = &mybasereg; | |
2280 | basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 | |
2281 | : exp.X_add_number; | |
2282 | basereg->neon = 0; | |
2283 | } | |
2284 | ||
2285 | if (basereg->neon) | |
2286 | typeinfo = *basereg->neon; | |
2287 | ||
2288 | if (parse_neon_type (&ntype, &p) == SUCCESS) | |
2289 | { | |
2290 | /* We got a type. */ | |
2291 | if (typeinfo.defined & NTA_HASTYPE) | |
2292 | { | |
2293 | as_bad (_("can't redefine the type of a register alias")); | |
c921be7d | 2294 | return FALSE; |
dcbf9037 | 2295 | } |
5f4273c7 | 2296 | |
dcbf9037 JB |
2297 | typeinfo.defined |= NTA_HASTYPE; |
2298 | if (ntype.elems != 1) | |
2299 | { | |
2300 | as_bad (_("you must specify a single type only")); | |
c921be7d | 2301 | return FALSE; |
dcbf9037 JB |
2302 | } |
2303 | typeinfo.eltype = ntype.el[0]; | |
2304 | } | |
5f4273c7 | 2305 | |
dcbf9037 JB |
2306 | if (skip_past_char (&p, '[') == SUCCESS) |
2307 | { | |
2308 | expressionS exp; | |
2309 | /* We got a scalar index. */ | |
5f4273c7 | 2310 | |
dcbf9037 JB |
2311 | if (typeinfo.defined & NTA_HASINDEX) |
2312 | { | |
2313 | as_bad (_("can't redefine the index of a scalar alias")); | |
c921be7d | 2314 | return FALSE; |
dcbf9037 | 2315 | } |
5f4273c7 | 2316 | |
dcbf9037 | 2317 | my_get_expression (&exp, &p, GE_NO_PREFIX); |
5f4273c7 | 2318 | |
dcbf9037 JB |
2319 | if (exp.X_op != O_constant) |
2320 | { | |
2321 | as_bad (_("scalar index must be constant")); | |
c921be7d | 2322 | return FALSE; |
dcbf9037 | 2323 | } |
5f4273c7 | 2324 | |
dcbf9037 JB |
2325 | typeinfo.defined |= NTA_HASINDEX; |
2326 | typeinfo.index = exp.X_add_number; | |
5f4273c7 | 2327 | |
dcbf9037 JB |
2328 | if (skip_past_char (&p, ']') == FAIL) |
2329 | { | |
2330 | as_bad (_("expecting ]")); | |
c921be7d | 2331 | return FALSE; |
dcbf9037 JB |
2332 | } |
2333 | } | |
2334 | ||
15735687 NS |
2335 | /* If TC_CASE_SENSITIVE is defined, then newname already points to |
2336 | the desired alias name, and p points to its end. If not, then | |
2337 | the desired alias name is in the global original_case_string. */ | |
2338 | #ifdef TC_CASE_SENSITIVE | |
dcbf9037 | 2339 | namelen = nameend - newname; |
15735687 NS |
2340 | #else |
2341 | newname = original_case_string; | |
2342 | namelen = strlen (newname); | |
2343 | #endif | |
2344 | ||
21d799b5 | 2345 | namebuf = (char *) alloca (namelen + 1); |
dcbf9037 JB |
2346 | strncpy (namebuf, newname, namelen); |
2347 | namebuf[namelen] = '\0'; | |
5f4273c7 | 2348 | |
dcbf9037 JB |
2349 | insert_neon_reg_alias (namebuf, basereg->number, basetype, |
2350 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2351 | |
dcbf9037 JB |
2352 | /* Insert name in all uppercase. */ |
2353 | for (p = namebuf; *p; p++) | |
2354 | *p = TOUPPER (*p); | |
5f4273c7 | 2355 | |
dcbf9037 JB |
2356 | if (strncmp (namebuf, newname, namelen)) |
2357 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2358 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2359 | |
dcbf9037 JB |
2360 | /* Insert name in all lowercase. */ |
2361 | for (p = namebuf; *p; p++) | |
2362 | *p = TOLOWER (*p); | |
5f4273c7 | 2363 | |
dcbf9037 JB |
2364 | if (strncmp (namebuf, newname, namelen)) |
2365 | insert_neon_reg_alias (namebuf, basereg->number, basetype, | |
2366 | typeinfo.defined != 0 ? &typeinfo : NULL); | |
5f4273c7 | 2367 | |
c921be7d | 2368 | return TRUE; |
dcbf9037 JB |
2369 | } |
2370 | ||
c19d1205 ZW |
2371 | /* Should never be called, as .req goes between the alias and the |
2372 | register name, not at the beginning of the line. */ | |
c921be7d | 2373 | |
b99bd4ef | 2374 | static void |
c19d1205 | 2375 | s_req (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2376 | { |
c19d1205 ZW |
2377 | as_bad (_("invalid syntax for .req directive")); |
2378 | } | |
b99bd4ef | 2379 | |
dcbf9037 JB |
2380 | static void |
2381 | s_dn (int a ATTRIBUTE_UNUSED) | |
2382 | { | |
2383 | as_bad (_("invalid syntax for .dn directive")); | |
2384 | } | |
2385 | ||
2386 | static void | |
2387 | s_qn (int a ATTRIBUTE_UNUSED) | |
2388 | { | |
2389 | as_bad (_("invalid syntax for .qn directive")); | |
2390 | } | |
2391 | ||
c19d1205 ZW |
2392 | /* The .unreq directive deletes an alias which was previously defined |
2393 | by .req. For example: | |
b99bd4ef | 2394 | |
c19d1205 ZW |
2395 | my_alias .req r11 |
2396 | .unreq my_alias */ | |
b99bd4ef NC |
2397 | |
2398 | static void | |
c19d1205 | 2399 | s_unreq (int a ATTRIBUTE_UNUSED) |
b99bd4ef | 2400 | { |
c19d1205 ZW |
2401 | char * name; |
2402 | char saved_char; | |
b99bd4ef | 2403 | |
c19d1205 ZW |
2404 | name = input_line_pointer; |
2405 | ||
2406 | while (*input_line_pointer != 0 | |
2407 | && *input_line_pointer != ' ' | |
2408 | && *input_line_pointer != '\n') | |
2409 | ++input_line_pointer; | |
2410 | ||
2411 | saved_char = *input_line_pointer; | |
2412 | *input_line_pointer = 0; | |
2413 | ||
2414 | if (!*name) | |
2415 | as_bad (_("invalid syntax for .unreq directive")); | |
2416 | else | |
2417 | { | |
21d799b5 NC |
2418 | struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh, |
2419 | name); | |
c19d1205 ZW |
2420 | |
2421 | if (!reg) | |
2422 | as_bad (_("unknown register alias '%s'"), name); | |
2423 | else if (reg->builtin) | |
a1727c1a | 2424 | as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"), |
c19d1205 ZW |
2425 | name); |
2426 | else | |
2427 | { | |
d929913e NC |
2428 | char * p; |
2429 | char * nbuf; | |
2430 | ||
db0bc284 | 2431 | hash_delete (arm_reg_hsh, name, FALSE); |
c19d1205 | 2432 | free ((char *) reg->name); |
dcbf9037 JB |
2433 | if (reg->neon) |
2434 | free (reg->neon); | |
c19d1205 | 2435 | free (reg); |
d929913e NC |
2436 | |
2437 | /* Also locate the all upper case and all lower case versions. | |
2438 | Do not complain if we cannot find one or the other as it | |
2439 | was probably deleted above. */ | |
5f4273c7 | 2440 | |
d929913e NC |
2441 | nbuf = strdup (name); |
2442 | for (p = nbuf; *p; p++) | |
2443 | *p = TOUPPER (*p); | |
21d799b5 | 2444 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2445 | if (reg) |
2446 | { | |
db0bc284 | 2447 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2448 | free ((char *) reg->name); |
2449 | if (reg->neon) | |
2450 | free (reg->neon); | |
2451 | free (reg); | |
2452 | } | |
2453 | ||
2454 | for (p = nbuf; *p; p++) | |
2455 | *p = TOLOWER (*p); | |
21d799b5 | 2456 | reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf); |
d929913e NC |
2457 | if (reg) |
2458 | { | |
db0bc284 | 2459 | hash_delete (arm_reg_hsh, nbuf, FALSE); |
d929913e NC |
2460 | free ((char *) reg->name); |
2461 | if (reg->neon) | |
2462 | free (reg->neon); | |
2463 | free (reg); | |
2464 | } | |
2465 | ||
2466 | free (nbuf); | |
c19d1205 ZW |
2467 | } |
2468 | } | |
b99bd4ef | 2469 | |
c19d1205 | 2470 | *input_line_pointer = saved_char; |
b99bd4ef NC |
2471 | demand_empty_rest_of_line (); |
2472 | } | |
2473 | ||
c19d1205 ZW |
2474 | /* Directives: Instruction set selection. */ |
2475 | ||
2476 | #ifdef OBJ_ELF | |
2477 | /* This code is to handle mapping symbols as defined in the ARM ELF spec. | |
2478 | (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). | |
2479 | Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), | |
2480 | and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ | |
2481 | ||
cd000bff DJ |
2482 | /* Create a new mapping symbol for the transition to STATE. */ |
2483 | ||
2484 | static void | |
2485 | make_mapping_symbol (enum mstate state, valueT value, fragS *frag) | |
b99bd4ef | 2486 | { |
a737bd4d | 2487 | symbolS * symbolP; |
c19d1205 ZW |
2488 | const char * symname; |
2489 | int type; | |
b99bd4ef | 2490 | |
c19d1205 | 2491 | switch (state) |
b99bd4ef | 2492 | { |
c19d1205 ZW |
2493 | case MAP_DATA: |
2494 | symname = "$d"; | |
2495 | type = BSF_NO_FLAGS; | |
2496 | break; | |
2497 | case MAP_ARM: | |
2498 | symname = "$a"; | |
2499 | type = BSF_NO_FLAGS; | |
2500 | break; | |
2501 | case MAP_THUMB: | |
2502 | symname = "$t"; | |
2503 | type = BSF_NO_FLAGS; | |
2504 | break; | |
c19d1205 ZW |
2505 | default: |
2506 | abort (); | |
2507 | } | |
2508 | ||
cd000bff | 2509 | symbolP = symbol_new (symname, now_seg, value, frag); |
c19d1205 ZW |
2510 | symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; |
2511 | ||
2512 | switch (state) | |
2513 | { | |
2514 | case MAP_ARM: | |
2515 | THUMB_SET_FUNC (symbolP, 0); | |
2516 | ARM_SET_THUMB (symbolP, 0); | |
2517 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2518 | break; | |
2519 | ||
2520 | case MAP_THUMB: | |
2521 | THUMB_SET_FUNC (symbolP, 1); | |
2522 | ARM_SET_THUMB (symbolP, 1); | |
2523 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2524 | break; | |
2525 | ||
2526 | case MAP_DATA: | |
2527 | default: | |
cd000bff DJ |
2528 | break; |
2529 | } | |
2530 | ||
2531 | /* Save the mapping symbols for future reference. Also check that | |
2532 | we do not place two mapping symbols at the same offset within a | |
2533 | frag. We'll handle overlap between frags in | |
2de7820f JZ |
2534 | check_mapping_symbols. |
2535 | ||
2536 | If .fill or other data filling directive generates zero sized data, | |
2537 | the mapping symbol for the following code will have the same value | |
2538 | as the one generated for the data filling directive. In this case, | |
2539 | we replace the old symbol with the new one at the same address. */ | |
cd000bff DJ |
2540 | if (value == 0) |
2541 | { | |
2de7820f JZ |
2542 | if (frag->tc_frag_data.first_map != NULL) |
2543 | { | |
2544 | know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0); | |
2545 | symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP); | |
2546 | } | |
cd000bff DJ |
2547 | frag->tc_frag_data.first_map = symbolP; |
2548 | } | |
2549 | if (frag->tc_frag_data.last_map != NULL) | |
0f020cef JZ |
2550 | { |
2551 | know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP)); | |
0f020cef JZ |
2552 | if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP)) |
2553 | symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP); | |
2554 | } | |
cd000bff DJ |
2555 | frag->tc_frag_data.last_map = symbolP; |
2556 | } | |
2557 | ||
2558 | /* We must sometimes convert a region marked as code to data during | |
2559 | code alignment, if an odd number of bytes have to be padded. The | |
2560 | code mapping symbol is pushed to an aligned address. */ | |
2561 | ||
2562 | static void | |
2563 | insert_data_mapping_symbol (enum mstate state, | |
2564 | valueT value, fragS *frag, offsetT bytes) | |
2565 | { | |
2566 | /* If there was already a mapping symbol, remove it. */ | |
2567 | if (frag->tc_frag_data.last_map != NULL | |
2568 | && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value) | |
2569 | { | |
2570 | symbolS *symp = frag->tc_frag_data.last_map; | |
2571 | ||
2572 | if (value == 0) | |
2573 | { | |
2574 | know (frag->tc_frag_data.first_map == symp); | |
2575 | frag->tc_frag_data.first_map = NULL; | |
2576 | } | |
2577 | frag->tc_frag_data.last_map = NULL; | |
2578 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
c19d1205 | 2579 | } |
cd000bff DJ |
2580 | |
2581 | make_mapping_symbol (MAP_DATA, value, frag); | |
2582 | make_mapping_symbol (state, value + bytes, frag); | |
2583 | } | |
2584 | ||
2585 | static void mapping_state_2 (enum mstate state, int max_chars); | |
2586 | ||
2587 | /* Set the mapping state to STATE. Only call this when about to | |
2588 | emit some STATE bytes to the file. */ | |
2589 | ||
2590 | void | |
2591 | mapping_state (enum mstate state) | |
2592 | { | |
940b5ce0 DJ |
2593 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2594 | ||
cd000bff DJ |
2595 | #define TRANSITION(from, to) (mapstate == (from) && state == (to)) |
2596 | ||
2597 | if (mapstate == state) | |
2598 | /* The mapping symbol has already been emitted. | |
2599 | There is nothing else to do. */ | |
2600 | return; | |
49c62a33 NC |
2601 | |
2602 | if (state == MAP_ARM || state == MAP_THUMB) | |
2603 | /* PR gas/12931 | |
2604 | All ARM instructions require 4-byte alignment. | |
2605 | (Almost) all Thumb instructions require 2-byte alignment. | |
2606 | ||
2607 | When emitting instructions into any section, mark the section | |
2608 | appropriately. | |
2609 | ||
2610 | Some Thumb instructions are alignment-sensitive modulo 4 bytes, | |
2611 | but themselves require 2-byte alignment; this applies to some | |
2612 | PC- relative forms. However, these cases will invovle implicit | |
2613 | literal pool generation or an explicit .align >=2, both of | |
2614 | which will cause the section to me marked with sufficient | |
2615 | alignment. Thus, we don't handle those cases here. */ | |
2616 | record_alignment (now_seg, state == MAP_ARM ? 2 : 1); | |
2617 | ||
2618 | if (TRANSITION (MAP_UNDEFINED, MAP_DATA)) | |
cd000bff DJ |
2619 | /* This case will be evaluated later in the next else. */ |
2620 | return; | |
2621 | else if (TRANSITION (MAP_UNDEFINED, MAP_ARM) | |
2622 | || TRANSITION (MAP_UNDEFINED, MAP_THUMB)) | |
2623 | { | |
2624 | /* Only add the symbol if the offset is > 0: | |
2625 | if we're at the first frag, check it's size > 0; | |
2626 | if we're not at the first frag, then for sure | |
2627 | the offset is > 0. */ | |
2628 | struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; | |
2629 | const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0); | |
2630 | ||
2631 | if (add_symbol) | |
2632 | make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); | |
2633 | } | |
2634 | ||
2635 | mapping_state_2 (state, 0); | |
2636 | #undef TRANSITION | |
2637 | } | |
2638 | ||
2639 | /* Same as mapping_state, but MAX_CHARS bytes have already been | |
2640 | allocated. Put the mapping symbol that far back. */ | |
2641 | ||
2642 | static void | |
2643 | mapping_state_2 (enum mstate state, int max_chars) | |
2644 | { | |
940b5ce0 DJ |
2645 | enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate; |
2646 | ||
2647 | if (!SEG_NORMAL (now_seg)) | |
2648 | return; | |
2649 | ||
cd000bff DJ |
2650 | if (mapstate == state) |
2651 | /* The mapping symbol has already been emitted. | |
2652 | There is nothing else to do. */ | |
2653 | return; | |
2654 | ||
cd000bff DJ |
2655 | seg_info (now_seg)->tc_segment_info_data.mapstate = state; |
2656 | make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now); | |
c19d1205 ZW |
2657 | } |
2658 | #else | |
d3106081 NS |
2659 | #define mapping_state(x) ((void)0) |
2660 | #define mapping_state_2(x, y) ((void)0) | |
c19d1205 ZW |
2661 | #endif |
2662 | ||
2663 | /* Find the real, Thumb encoded start of a Thumb function. */ | |
2664 | ||
4343666d | 2665 | #ifdef OBJ_COFF |
c19d1205 ZW |
2666 | static symbolS * |
2667 | find_real_start (symbolS * symbolP) | |
2668 | { | |
2669 | char * real_start; | |
2670 | const char * name = S_GET_NAME (symbolP); | |
2671 | symbolS * new_target; | |
2672 | ||
2673 | /* This definition must agree with the one in gcc/config/arm/thumb.c. */ | |
2674 | #define STUB_NAME ".real_start_of" | |
2675 | ||
2676 | if (name == NULL) | |
2677 | abort (); | |
2678 | ||
37f6032b ZW |
2679 | /* The compiler may generate BL instructions to local labels because |
2680 | it needs to perform a branch to a far away location. These labels | |
2681 | do not have a corresponding ".real_start_of" label. We check | |
2682 | both for S_IS_LOCAL and for a leading dot, to give a way to bypass | |
2683 | the ".real_start_of" convention for nonlocal branches. */ | |
2684 | if (S_IS_LOCAL (symbolP) || name[0] == '.') | |
c19d1205 ZW |
2685 | return symbolP; |
2686 | ||
37f6032b | 2687 | real_start = ACONCAT ((STUB_NAME, name, NULL)); |
c19d1205 ZW |
2688 | new_target = symbol_find (real_start); |
2689 | ||
2690 | if (new_target == NULL) | |
2691 | { | |
bd3ba5d1 | 2692 | as_warn (_("Failed to find real start of function: %s\n"), name); |
c19d1205 ZW |
2693 | new_target = symbolP; |
2694 | } | |
2695 | ||
c19d1205 ZW |
2696 | return new_target; |
2697 | } | |
4343666d | 2698 | #endif |
c19d1205 ZW |
2699 | |
2700 | static void | |
2701 | opcode_select (int width) | |
2702 | { | |
2703 | switch (width) | |
2704 | { | |
2705 | case 16: | |
2706 | if (! thumb_mode) | |
2707 | { | |
e74cfd16 | 2708 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
c19d1205 ZW |
2709 | as_bad (_("selected processor does not support THUMB opcodes")); |
2710 | ||
2711 | thumb_mode = 1; | |
2712 | /* No need to force the alignment, since we will have been | |
2713 | coming from ARM mode, which is word-aligned. */ | |
2714 | record_alignment (now_seg, 1); | |
2715 | } | |
c19d1205 ZW |
2716 | break; |
2717 | ||
2718 | case 32: | |
2719 | if (thumb_mode) | |
2720 | { | |
e74cfd16 | 2721 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 ZW |
2722 | as_bad (_("selected processor does not support ARM opcodes")); |
2723 | ||
2724 | thumb_mode = 0; | |
2725 | ||
2726 | if (!need_pass_2) | |
2727 | frag_align (2, 0, 0); | |
2728 | ||
2729 | record_alignment (now_seg, 1); | |
2730 | } | |
c19d1205 ZW |
2731 | break; |
2732 | ||
2733 | default: | |
2734 | as_bad (_("invalid instruction size selected (%d)"), width); | |
2735 | } | |
2736 | } | |
2737 | ||
2738 | static void | |
2739 | s_arm (int ignore ATTRIBUTE_UNUSED) | |
2740 | { | |
2741 | opcode_select (32); | |
2742 | demand_empty_rest_of_line (); | |
2743 | } | |
2744 | ||
2745 | static void | |
2746 | s_thumb (int ignore ATTRIBUTE_UNUSED) | |
2747 | { | |
2748 | opcode_select (16); | |
2749 | demand_empty_rest_of_line (); | |
2750 | } | |
2751 | ||
2752 | static void | |
2753 | s_code (int unused ATTRIBUTE_UNUSED) | |
2754 | { | |
2755 | int temp; | |
2756 | ||
2757 | temp = get_absolute_expression (); | |
2758 | switch (temp) | |
2759 | { | |
2760 | case 16: | |
2761 | case 32: | |
2762 | opcode_select (temp); | |
2763 | break; | |
2764 | ||
2765 | default: | |
2766 | as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); | |
2767 | } | |
2768 | } | |
2769 | ||
2770 | static void | |
2771 | s_force_thumb (int ignore ATTRIBUTE_UNUSED) | |
2772 | { | |
2773 | /* If we are not already in thumb mode go into it, EVEN if | |
2774 | the target processor does not support thumb instructions. | |
2775 | This is used by gcc/config/arm/lib1funcs.asm for example | |
2776 | to compile interworking support functions even if the | |
2777 | target processor should not support interworking. */ | |
2778 | if (! thumb_mode) | |
2779 | { | |
2780 | thumb_mode = 2; | |
2781 | record_alignment (now_seg, 1); | |
2782 | } | |
2783 | ||
2784 | demand_empty_rest_of_line (); | |
2785 | } | |
2786 | ||
2787 | static void | |
2788 | s_thumb_func (int ignore ATTRIBUTE_UNUSED) | |
2789 | { | |
2790 | s_thumb (0); | |
2791 | ||
2792 | /* The following label is the name/address of the start of a Thumb function. | |
2793 | We need to know this for the interworking support. */ | |
2794 | label_is_thumb_function_name = TRUE; | |
2795 | } | |
2796 | ||
2797 | /* Perform a .set directive, but also mark the alias as | |
2798 | being a thumb function. */ | |
2799 | ||
2800 | static void | |
2801 | s_thumb_set (int equiv) | |
2802 | { | |
2803 | /* XXX the following is a duplicate of the code for s_set() in read.c | |
2804 | We cannot just call that code as we need to get at the symbol that | |
2805 | is created. */ | |
2806 | char * name; | |
2807 | char delim; | |
2808 | char * end_name; | |
2809 | symbolS * symbolP; | |
2810 | ||
2811 | /* Especial apologies for the random logic: | |
2812 | This just grew, and could be parsed much more simply! | |
2813 | Dean - in haste. */ | |
2814 | name = input_line_pointer; | |
2815 | delim = get_symbol_end (); | |
2816 | end_name = input_line_pointer; | |
2817 | *end_name = delim; | |
2818 | ||
2819 | if (*input_line_pointer != ',') | |
2820 | { | |
2821 | *end_name = 0; | |
2822 | as_bad (_("expected comma after name \"%s\""), name); | |
b99bd4ef NC |
2823 | *end_name = delim; |
2824 | ignore_rest_of_line (); | |
2825 | return; | |
2826 | } | |
2827 | ||
2828 | input_line_pointer++; | |
2829 | *end_name = 0; | |
2830 | ||
2831 | if (name[0] == '.' && name[1] == '\0') | |
2832 | { | |
2833 | /* XXX - this should not happen to .thumb_set. */ | |
2834 | abort (); | |
2835 | } | |
2836 | ||
2837 | if ((symbolP = symbol_find (name)) == NULL | |
2838 | && (symbolP = md_undefined_symbol (name)) == NULL) | |
2839 | { | |
2840 | #ifndef NO_LISTING | |
2841 | /* When doing symbol listings, play games with dummy fragments living | |
2842 | outside the normal fragment chain to record the file and line info | |
c19d1205 | 2843 | for this symbol. */ |
b99bd4ef NC |
2844 | if (listing & LISTING_SYMBOLS) |
2845 | { | |
2846 | extern struct list_info_struct * listing_tail; | |
21d799b5 | 2847 | fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS)); |
b99bd4ef NC |
2848 | |
2849 | memset (dummy_frag, 0, sizeof (fragS)); | |
2850 | dummy_frag->fr_type = rs_fill; | |
2851 | dummy_frag->line = listing_tail; | |
2852 | symbolP = symbol_new (name, undefined_section, 0, dummy_frag); | |
2853 | dummy_frag->fr_symbol = symbolP; | |
2854 | } | |
2855 | else | |
2856 | #endif | |
2857 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); | |
2858 | ||
2859 | #ifdef OBJ_COFF | |
2860 | /* "set" symbols are local unless otherwise specified. */ | |
2861 | SF_SET_LOCAL (symbolP); | |
2862 | #endif /* OBJ_COFF */ | |
2863 | } /* Make a new symbol. */ | |
2864 | ||
2865 | symbol_table_insert (symbolP); | |
2866 | ||
2867 | * end_name = delim; | |
2868 | ||
2869 | if (equiv | |
2870 | && S_IS_DEFINED (symbolP) | |
2871 | && S_GET_SEGMENT (symbolP) != reg_section) | |
2872 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); | |
2873 | ||
2874 | pseudo_set (symbolP); | |
2875 | ||
2876 | demand_empty_rest_of_line (); | |
2877 | ||
c19d1205 | 2878 | /* XXX Now we come to the Thumb specific bit of code. */ |
b99bd4ef NC |
2879 | |
2880 | THUMB_SET_FUNC (symbolP, 1); | |
2881 | ARM_SET_THUMB (symbolP, 1); | |
2882 | #if defined OBJ_ELF || defined OBJ_COFF | |
2883 | ARM_SET_INTERWORK (symbolP, support_interwork); | |
2884 | #endif | |
2885 | } | |
2886 | ||
c19d1205 | 2887 | /* Directives: Mode selection. */ |
b99bd4ef | 2888 | |
c19d1205 ZW |
2889 | /* .syntax [unified|divided] - choose the new unified syntax |
2890 | (same for Arm and Thumb encoding, modulo slight differences in what | |
2891 | can be represented) or the old divergent syntax for each mode. */ | |
b99bd4ef | 2892 | static void |
c19d1205 | 2893 | s_syntax (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2894 | { |
c19d1205 ZW |
2895 | char *name, delim; |
2896 | ||
2897 | name = input_line_pointer; | |
2898 | delim = get_symbol_end (); | |
2899 | ||
2900 | if (!strcasecmp (name, "unified")) | |
2901 | unified_syntax = TRUE; | |
2902 | else if (!strcasecmp (name, "divided")) | |
2903 | unified_syntax = FALSE; | |
2904 | else | |
2905 | { | |
2906 | as_bad (_("unrecognized syntax mode \"%s\""), name); | |
2907 | return; | |
2908 | } | |
2909 | *input_line_pointer = delim; | |
b99bd4ef NC |
2910 | demand_empty_rest_of_line (); |
2911 | } | |
2912 | ||
c19d1205 ZW |
2913 | /* Directives: sectioning and alignment. */ |
2914 | ||
2915 | /* Same as s_align_ptwo but align 0 => align 2. */ | |
2916 | ||
b99bd4ef | 2917 | static void |
c19d1205 | 2918 | s_align (int unused ATTRIBUTE_UNUSED) |
b99bd4ef | 2919 | { |
a737bd4d | 2920 | int temp; |
dce323d1 | 2921 | bfd_boolean fill_p; |
c19d1205 ZW |
2922 | long temp_fill; |
2923 | long max_alignment = 15; | |
b99bd4ef NC |
2924 | |
2925 | temp = get_absolute_expression (); | |
c19d1205 ZW |
2926 | if (temp > max_alignment) |
2927 | as_bad (_("alignment too large: %d assumed"), temp = max_alignment); | |
2928 | else if (temp < 0) | |
b99bd4ef | 2929 | { |
c19d1205 ZW |
2930 | as_bad (_("alignment negative. 0 assumed.")); |
2931 | temp = 0; | |
2932 | } | |
b99bd4ef | 2933 | |
c19d1205 ZW |
2934 | if (*input_line_pointer == ',') |
2935 | { | |
2936 | input_line_pointer++; | |
2937 | temp_fill = get_absolute_expression (); | |
dce323d1 | 2938 | fill_p = TRUE; |
b99bd4ef | 2939 | } |
c19d1205 | 2940 | else |
dce323d1 PB |
2941 | { |
2942 | fill_p = FALSE; | |
2943 | temp_fill = 0; | |
2944 | } | |
b99bd4ef | 2945 | |
c19d1205 ZW |
2946 | if (!temp) |
2947 | temp = 2; | |
b99bd4ef | 2948 | |
c19d1205 ZW |
2949 | /* Only make a frag if we HAVE to. */ |
2950 | if (temp && !need_pass_2) | |
dce323d1 PB |
2951 | { |
2952 | if (!fill_p && subseg_text_p (now_seg)) | |
2953 | frag_align_code (temp, 0); | |
2954 | else | |
2955 | frag_align (temp, (int) temp_fill, 0); | |
2956 | } | |
c19d1205 ZW |
2957 | demand_empty_rest_of_line (); |
2958 | ||
2959 | record_alignment (now_seg, temp); | |
b99bd4ef NC |
2960 | } |
2961 | ||
c19d1205 ZW |
2962 | static void |
2963 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
b99bd4ef | 2964 | { |
c19d1205 ZW |
2965 | /* We don't support putting frags in the BSS segment, we fake it by |
2966 | marking in_bss, then looking at s_skip for clues. */ | |
2967 | subseg_set (bss_section, 0); | |
2968 | demand_empty_rest_of_line (); | |
cd000bff DJ |
2969 | |
2970 | #ifdef md_elf_section_change_hook | |
2971 | md_elf_section_change_hook (); | |
2972 | #endif | |
c19d1205 | 2973 | } |
b99bd4ef | 2974 | |
c19d1205 ZW |
2975 | static void |
2976 | s_even (int ignore ATTRIBUTE_UNUSED) | |
2977 | { | |
2978 | /* Never make frag if expect extra pass. */ | |
2979 | if (!need_pass_2) | |
2980 | frag_align (1, 0, 0); | |
b99bd4ef | 2981 | |
c19d1205 | 2982 | record_alignment (now_seg, 1); |
b99bd4ef | 2983 | |
c19d1205 | 2984 | demand_empty_rest_of_line (); |
b99bd4ef NC |
2985 | } |
2986 | ||
c19d1205 | 2987 | /* Directives: Literal pools. */ |
a737bd4d | 2988 | |
c19d1205 ZW |
2989 | static literal_pool * |
2990 | find_literal_pool (void) | |
a737bd4d | 2991 | { |
c19d1205 | 2992 | literal_pool * pool; |
a737bd4d | 2993 | |
c19d1205 | 2994 | for (pool = list_of_pools; pool != NULL; pool = pool->next) |
a737bd4d | 2995 | { |
c19d1205 ZW |
2996 | if (pool->section == now_seg |
2997 | && pool->sub_section == now_subseg) | |
2998 | break; | |
a737bd4d NC |
2999 | } |
3000 | ||
c19d1205 | 3001 | return pool; |
a737bd4d NC |
3002 | } |
3003 | ||
c19d1205 ZW |
3004 | static literal_pool * |
3005 | find_or_make_literal_pool (void) | |
a737bd4d | 3006 | { |
c19d1205 ZW |
3007 | /* Next literal pool ID number. */ |
3008 | static unsigned int latest_pool_num = 1; | |
3009 | literal_pool * pool; | |
a737bd4d | 3010 | |
c19d1205 | 3011 | pool = find_literal_pool (); |
a737bd4d | 3012 | |
c19d1205 | 3013 | if (pool == NULL) |
a737bd4d | 3014 | { |
c19d1205 | 3015 | /* Create a new pool. */ |
21d799b5 | 3016 | pool = (literal_pool *) xmalloc (sizeof (* pool)); |
c19d1205 ZW |
3017 | if (! pool) |
3018 | return NULL; | |
a737bd4d | 3019 | |
c19d1205 ZW |
3020 | pool->next_free_entry = 0; |
3021 | pool->section = now_seg; | |
3022 | pool->sub_section = now_subseg; | |
3023 | pool->next = list_of_pools; | |
3024 | pool->symbol = NULL; | |
3025 | ||
3026 | /* Add it to the list. */ | |
3027 | list_of_pools = pool; | |
a737bd4d | 3028 | } |
a737bd4d | 3029 | |
c19d1205 ZW |
3030 | /* New pools, and emptied pools, will have a NULL symbol. */ |
3031 | if (pool->symbol == NULL) | |
a737bd4d | 3032 | { |
c19d1205 ZW |
3033 | pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, |
3034 | (valueT) 0, &zero_address_frag); | |
3035 | pool->id = latest_pool_num ++; | |
a737bd4d NC |
3036 | } |
3037 | ||
c19d1205 ZW |
3038 | /* Done. */ |
3039 | return pool; | |
a737bd4d NC |
3040 | } |
3041 | ||
c19d1205 | 3042 | /* Add the literal in the global 'inst' |
5f4273c7 | 3043 | structure to the relevant literal pool. */ |
b99bd4ef NC |
3044 | |
3045 | static int | |
c19d1205 | 3046 | add_to_lit_pool (void) |
b99bd4ef | 3047 | { |
c19d1205 ZW |
3048 | literal_pool * pool; |
3049 | unsigned int entry; | |
b99bd4ef | 3050 | |
c19d1205 ZW |
3051 | pool = find_or_make_literal_pool (); |
3052 | ||
3053 | /* Check if this literal value is already in the pool. */ | |
3054 | for (entry = 0; entry < pool->next_free_entry; entry ++) | |
b99bd4ef | 3055 | { |
c19d1205 ZW |
3056 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) |
3057 | && (inst.reloc.exp.X_op == O_constant) | |
3058 | && (pool->literals[entry].X_add_number | |
3059 | == inst.reloc.exp.X_add_number) | |
3060 | && (pool->literals[entry].X_unsigned | |
3061 | == inst.reloc.exp.X_unsigned)) | |
3062 | break; | |
3063 | ||
3064 | if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) | |
3065 | && (inst.reloc.exp.X_op == O_symbol) | |
3066 | && (pool->literals[entry].X_add_number | |
3067 | == inst.reloc.exp.X_add_number) | |
3068 | && (pool->literals[entry].X_add_symbol | |
3069 | == inst.reloc.exp.X_add_symbol) | |
3070 | && (pool->literals[entry].X_op_symbol | |
3071 | == inst.reloc.exp.X_op_symbol)) | |
3072 | break; | |
b99bd4ef NC |
3073 | } |
3074 | ||
c19d1205 ZW |
3075 | /* Do we need to create a new entry? */ |
3076 | if (entry == pool->next_free_entry) | |
3077 | { | |
3078 | if (entry >= MAX_LITERAL_POOL_SIZE) | |
3079 | { | |
3080 | inst.error = _("literal pool overflow"); | |
3081 | return FAIL; | |
3082 | } | |
3083 | ||
3084 | pool->literals[entry] = inst.reloc.exp; | |
a8040cf2 NC |
3085 | #ifdef OBJ_ELF |
3086 | /* PR ld/12974: Record the location of the first source line to reference | |
3087 | this entry in the literal pool. If it turns out during linking that the | |
3088 | symbol does not exist we will be able to give an accurate line number for | |
3089 | the (first use of the) missing reference. */ | |
3090 | if (debug_type == DEBUG_DWARF2) | |
3091 | dwarf2_where (pool->locs + entry); | |
3092 | #endif | |
c19d1205 ZW |
3093 | pool->next_free_entry += 1; |
3094 | } | |
b99bd4ef | 3095 | |
c19d1205 ZW |
3096 | inst.reloc.exp.X_op = O_symbol; |
3097 | inst.reloc.exp.X_add_number = ((int) entry) * 4; | |
3098 | inst.reloc.exp.X_add_symbol = pool->symbol; | |
b99bd4ef | 3099 | |
c19d1205 | 3100 | return SUCCESS; |
b99bd4ef NC |
3101 | } |
3102 | ||
c19d1205 ZW |
3103 | /* Can't use symbol_new here, so have to create a symbol and then at |
3104 | a later date assign it a value. Thats what these functions do. */ | |
e16bb312 | 3105 | |
c19d1205 ZW |
3106 | static void |
3107 | symbol_locate (symbolS * symbolP, | |
3108 | const char * name, /* It is copied, the caller can modify. */ | |
3109 | segT segment, /* Segment identifier (SEG_<something>). */ | |
3110 | valueT valu, /* Symbol value. */ | |
3111 | fragS * frag) /* Associated fragment. */ | |
3112 | { | |
3113 | unsigned int name_length; | |
3114 | char * preserved_copy_of_name; | |
e16bb312 | 3115 | |
c19d1205 ZW |
3116 | name_length = strlen (name) + 1; /* +1 for \0. */ |
3117 | obstack_grow (¬es, name, name_length); | |
21d799b5 | 3118 | preserved_copy_of_name = (char *) obstack_finish (¬es); |
e16bb312 | 3119 | |
c19d1205 ZW |
3120 | #ifdef tc_canonicalize_symbol_name |
3121 | preserved_copy_of_name = | |
3122 | tc_canonicalize_symbol_name (preserved_copy_of_name); | |
3123 | #endif | |
b99bd4ef | 3124 | |
c19d1205 | 3125 | S_SET_NAME (symbolP, preserved_copy_of_name); |
b99bd4ef | 3126 | |
c19d1205 ZW |
3127 | S_SET_SEGMENT (symbolP, segment); |
3128 | S_SET_VALUE (symbolP, valu); | |
3129 | symbol_clear_list_pointers (symbolP); | |
b99bd4ef | 3130 | |
c19d1205 | 3131 | symbol_set_frag (symbolP, frag); |
b99bd4ef | 3132 | |
c19d1205 ZW |
3133 | /* Link to end of symbol chain. */ |
3134 | { | |
3135 | extern int symbol_table_frozen; | |
b99bd4ef | 3136 | |
c19d1205 ZW |
3137 | if (symbol_table_frozen) |
3138 | abort (); | |
3139 | } | |
b99bd4ef | 3140 | |
c19d1205 | 3141 | symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); |
b99bd4ef | 3142 | |
c19d1205 | 3143 | obj_symbol_new_hook (symbolP); |
b99bd4ef | 3144 | |
c19d1205 ZW |
3145 | #ifdef tc_symbol_new_hook |
3146 | tc_symbol_new_hook (symbolP); | |
3147 | #endif | |
3148 | ||
3149 | #ifdef DEBUG_SYMS | |
3150 | verify_symbol_chain (symbol_rootP, symbol_lastP); | |
3151 | #endif /* DEBUG_SYMS */ | |
b99bd4ef NC |
3152 | } |
3153 | ||
b99bd4ef | 3154 | |
c19d1205 ZW |
3155 | static void |
3156 | s_ltorg (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 3157 | { |
c19d1205 ZW |
3158 | unsigned int entry; |
3159 | literal_pool * pool; | |
3160 | char sym_name[20]; | |
b99bd4ef | 3161 | |
c19d1205 ZW |
3162 | pool = find_literal_pool (); |
3163 | if (pool == NULL | |
3164 | || pool->symbol == NULL | |
3165 | || pool->next_free_entry == 0) | |
3166 | return; | |
b99bd4ef | 3167 | |
c19d1205 | 3168 | mapping_state (MAP_DATA); |
b99bd4ef | 3169 | |
c19d1205 ZW |
3170 | /* Align pool as you have word accesses. |
3171 | Only make a frag if we have to. */ | |
3172 | if (!need_pass_2) | |
3173 | frag_align (2, 0, 0); | |
b99bd4ef | 3174 | |
c19d1205 | 3175 | record_alignment (now_seg, 2); |
b99bd4ef | 3176 | |
c19d1205 | 3177 | sprintf (sym_name, "$$lit_\002%x", pool->id); |
b99bd4ef | 3178 | |
c19d1205 ZW |
3179 | symbol_locate (pool->symbol, sym_name, now_seg, |
3180 | (valueT) frag_now_fix (), frag_now); | |
3181 | symbol_table_insert (pool->symbol); | |
b99bd4ef | 3182 | |
c19d1205 | 3183 | ARM_SET_THUMB (pool->symbol, thumb_mode); |
b99bd4ef | 3184 | |
c19d1205 ZW |
3185 | #if defined OBJ_COFF || defined OBJ_ELF |
3186 | ARM_SET_INTERWORK (pool->symbol, support_interwork); | |
3187 | #endif | |
6c43fab6 | 3188 | |
c19d1205 | 3189 | for (entry = 0; entry < pool->next_free_entry; entry ++) |
a8040cf2 NC |
3190 | { |
3191 | #ifdef OBJ_ELF | |
3192 | if (debug_type == DEBUG_DWARF2) | |
3193 | dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry); | |
3194 | #endif | |
3195 | /* First output the expression in the instruction to the pool. */ | |
3196 | emit_expr (&(pool->literals[entry]), 4); /* .word */ | |
3197 | } | |
b99bd4ef | 3198 | |
c19d1205 ZW |
3199 | /* Mark the pool as empty. */ |
3200 | pool->next_free_entry = 0; | |
3201 | pool->symbol = NULL; | |
b99bd4ef NC |
3202 | } |
3203 | ||
c19d1205 ZW |
3204 | #ifdef OBJ_ELF |
3205 | /* Forward declarations for functions below, in the MD interface | |
3206 | section. */ | |
3207 | static void fix_new_arm (fragS *, int, short, expressionS *, int, int); | |
3208 | static valueT create_unwind_entry (int); | |
3209 | static void start_unwind_section (const segT, int); | |
3210 | static void add_unwind_opcode (valueT, int); | |
3211 | static void flush_pending_unwind (void); | |
b99bd4ef | 3212 | |
c19d1205 | 3213 | /* Directives: Data. */ |
b99bd4ef | 3214 | |
c19d1205 ZW |
3215 | static void |
3216 | s_arm_elf_cons (int nbytes) | |
3217 | { | |
3218 | expressionS exp; | |
b99bd4ef | 3219 | |
c19d1205 ZW |
3220 | #ifdef md_flush_pending_output |
3221 | md_flush_pending_output (); | |
3222 | #endif | |
b99bd4ef | 3223 | |
c19d1205 | 3224 | if (is_it_end_of_statement ()) |
b99bd4ef | 3225 | { |
c19d1205 ZW |
3226 | demand_empty_rest_of_line (); |
3227 | return; | |
b99bd4ef NC |
3228 | } |
3229 | ||
c19d1205 ZW |
3230 | #ifdef md_cons_align |
3231 | md_cons_align (nbytes); | |
3232 | #endif | |
b99bd4ef | 3233 | |
c19d1205 ZW |
3234 | mapping_state (MAP_DATA); |
3235 | do | |
b99bd4ef | 3236 | { |
c19d1205 ZW |
3237 | int reloc; |
3238 | char *base = input_line_pointer; | |
b99bd4ef | 3239 | |
c19d1205 | 3240 | expression (& exp); |
b99bd4ef | 3241 | |
c19d1205 ZW |
3242 | if (exp.X_op != O_symbol) |
3243 | emit_expr (&exp, (unsigned int) nbytes); | |
3244 | else | |
3245 | { | |
3246 | char *before_reloc = input_line_pointer; | |
3247 | reloc = parse_reloc (&input_line_pointer); | |
3248 | if (reloc == -1) | |
3249 | { | |
3250 | as_bad (_("unrecognized relocation suffix")); | |
3251 | ignore_rest_of_line (); | |
3252 | return; | |
3253 | } | |
3254 | else if (reloc == BFD_RELOC_UNUSED) | |
3255 | emit_expr (&exp, (unsigned int) nbytes); | |
3256 | else | |
3257 | { | |
21d799b5 NC |
3258 | reloc_howto_type *howto = (reloc_howto_type *) |
3259 | bfd_reloc_type_lookup (stdoutput, | |
3260 | (bfd_reloc_code_real_type) reloc); | |
c19d1205 | 3261 | int size = bfd_get_reloc_size (howto); |
b99bd4ef | 3262 | |
2fc8bdac ZW |
3263 | if (reloc == BFD_RELOC_ARM_PLT32) |
3264 | { | |
3265 | as_bad (_("(plt) is only valid on branch targets")); | |
3266 | reloc = BFD_RELOC_UNUSED; | |
3267 | size = 0; | |
3268 | } | |
3269 | ||
c19d1205 | 3270 | if (size > nbytes) |
2fc8bdac | 3271 | as_bad (_("%s relocations do not fit in %d bytes"), |
c19d1205 ZW |
3272 | howto->name, nbytes); |
3273 | else | |
3274 | { | |
3275 | /* We've parsed an expression stopping at O_symbol. | |
3276 | But there may be more expression left now that we | |
3277 | have parsed the relocation marker. Parse it again. | |
3278 | XXX Surely there is a cleaner way to do this. */ | |
3279 | char *p = input_line_pointer; | |
3280 | int offset; | |
21d799b5 | 3281 | char *save_buf = (char *) alloca (input_line_pointer - base); |
c19d1205 ZW |
3282 | memcpy (save_buf, base, input_line_pointer - base); |
3283 | memmove (base + (input_line_pointer - before_reloc), | |
3284 | base, before_reloc - base); | |
3285 | ||
3286 | input_line_pointer = base + (input_line_pointer-before_reloc); | |
3287 | expression (&exp); | |
3288 | memcpy (base, save_buf, p - base); | |
3289 | ||
3290 | offset = nbytes - size; | |
3291 | p = frag_more ((int) nbytes); | |
3292 | fix_new_exp (frag_now, p - frag_now->fr_literal + offset, | |
21d799b5 | 3293 | size, &exp, 0, (enum bfd_reloc_code_real) reloc); |
c19d1205 ZW |
3294 | } |
3295 | } | |
3296 | } | |
b99bd4ef | 3297 | } |
c19d1205 | 3298 | while (*input_line_pointer++ == ','); |
b99bd4ef | 3299 | |
c19d1205 ZW |
3300 | /* Put terminator back into stream. */ |
3301 | input_line_pointer --; | |
3302 | demand_empty_rest_of_line (); | |
b99bd4ef NC |
3303 | } |
3304 | ||
c921be7d NC |
3305 | /* Emit an expression containing a 32-bit thumb instruction. |
3306 | Implementation based on put_thumb32_insn. */ | |
3307 | ||
3308 | static void | |
3309 | emit_thumb32_expr (expressionS * exp) | |
3310 | { | |
3311 | expressionS exp_high = *exp; | |
3312 | ||
3313 | exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16; | |
3314 | emit_expr (& exp_high, (unsigned int) THUMB_SIZE); | |
3315 | exp->X_add_number &= 0xffff; | |
3316 | emit_expr (exp, (unsigned int) THUMB_SIZE); | |
3317 | } | |
3318 | ||
3319 | /* Guess the instruction size based on the opcode. */ | |
3320 | ||
3321 | static int | |
3322 | thumb_insn_size (int opcode) | |
3323 | { | |
3324 | if ((unsigned int) opcode < 0xe800u) | |
3325 | return 2; | |
3326 | else if ((unsigned int) opcode >= 0xe8000000u) | |
3327 | return 4; | |
3328 | else | |
3329 | return 0; | |
3330 | } | |
3331 | ||
3332 | static bfd_boolean | |
3333 | emit_insn (expressionS *exp, int nbytes) | |
3334 | { | |
3335 | int size = 0; | |
3336 | ||
3337 | if (exp->X_op == O_constant) | |
3338 | { | |
3339 | size = nbytes; | |
3340 | ||
3341 | if (size == 0) | |
3342 | size = thumb_insn_size (exp->X_add_number); | |
3343 | ||
3344 | if (size != 0) | |
3345 | { | |
3346 | if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu) | |
3347 | { | |
3348 | as_bad (_(".inst.n operand too big. "\ | |
3349 | "Use .inst.w instead")); | |
3350 | size = 0; | |
3351 | } | |
3352 | else | |
3353 | { | |
3354 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
3355 | set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0); | |
3356 | else | |
3357 | set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0); | |
3358 | ||
3359 | if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian) | |
3360 | emit_thumb32_expr (exp); | |
3361 | else | |
3362 | emit_expr (exp, (unsigned int) size); | |
3363 | ||
3364 | it_fsm_post_encode (); | |
3365 | } | |
3366 | } | |
3367 | else | |
3368 | as_bad (_("cannot determine Thumb instruction size. " \ | |
3369 | "Use .inst.n/.inst.w instead")); | |
3370 | } | |
3371 | else | |
3372 | as_bad (_("constant expression required")); | |
3373 | ||
3374 | return (size != 0); | |
3375 | } | |
3376 | ||
3377 | /* Like s_arm_elf_cons but do not use md_cons_align and | |
3378 | set the mapping state to MAP_ARM/MAP_THUMB. */ | |
3379 | ||
3380 | static void | |
3381 | s_arm_elf_inst (int nbytes) | |
3382 | { | |
3383 | if (is_it_end_of_statement ()) | |
3384 | { | |
3385 | demand_empty_rest_of_line (); | |
3386 | return; | |
3387 | } | |
3388 | ||
3389 | /* Calling mapping_state () here will not change ARM/THUMB, | |
3390 | but will ensure not to be in DATA state. */ | |
3391 | ||
3392 | if (thumb_mode) | |
3393 | mapping_state (MAP_THUMB); | |
3394 | else | |
3395 | { | |
3396 | if (nbytes != 0) | |
3397 | { | |
3398 | as_bad (_("width suffixes are invalid in ARM mode")); | |
3399 | ignore_rest_of_line (); | |
3400 | return; | |
3401 | } | |
3402 | ||
3403 | nbytes = 4; | |
3404 | ||
3405 | mapping_state (MAP_ARM); | |
3406 | } | |
3407 | ||
3408 | do | |
3409 | { | |
3410 | expressionS exp; | |
3411 | ||
3412 | expression (& exp); | |
3413 | ||
3414 | if (! emit_insn (& exp, nbytes)) | |
3415 | { | |
3416 | ignore_rest_of_line (); | |
3417 | return; | |
3418 | } | |
3419 | } | |
3420 | while (*input_line_pointer++ == ','); | |
3421 | ||
3422 | /* Put terminator back into stream. */ | |
3423 | input_line_pointer --; | |
3424 | demand_empty_rest_of_line (); | |
3425 | } | |
b99bd4ef | 3426 | |
c19d1205 | 3427 | /* Parse a .rel31 directive. */ |
b99bd4ef | 3428 | |
c19d1205 ZW |
3429 | static void |
3430 | s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) | |
3431 | { | |
3432 | expressionS exp; | |
3433 | char *p; | |
3434 | valueT highbit; | |
b99bd4ef | 3435 | |
c19d1205 ZW |
3436 | highbit = 0; |
3437 | if (*input_line_pointer == '1') | |
3438 | highbit = 0x80000000; | |
3439 | else if (*input_line_pointer != '0') | |
3440 | as_bad (_("expected 0 or 1")); | |
b99bd4ef | 3441 | |
c19d1205 ZW |
3442 | input_line_pointer++; |
3443 | if (*input_line_pointer != ',') | |
3444 | as_bad (_("missing comma")); | |
3445 | input_line_pointer++; | |
b99bd4ef | 3446 | |
c19d1205 ZW |
3447 | #ifdef md_flush_pending_output |
3448 | md_flush_pending_output (); | |
3449 | #endif | |
b99bd4ef | 3450 | |
c19d1205 ZW |
3451 | #ifdef md_cons_align |
3452 | md_cons_align (4); | |
3453 | #endif | |
b99bd4ef | 3454 | |
c19d1205 | 3455 | mapping_state (MAP_DATA); |
b99bd4ef | 3456 | |
c19d1205 | 3457 | expression (&exp); |
b99bd4ef | 3458 | |
c19d1205 ZW |
3459 | p = frag_more (4); |
3460 | md_number_to_chars (p, highbit, 4); | |
3461 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, | |
3462 | BFD_RELOC_ARM_PREL31); | |
b99bd4ef | 3463 | |
c19d1205 | 3464 | demand_empty_rest_of_line (); |
b99bd4ef NC |
3465 | } |
3466 | ||
c19d1205 | 3467 | /* Directives: AEABI stack-unwind tables. */ |
b99bd4ef | 3468 | |
c19d1205 | 3469 | /* Parse an unwind_fnstart directive. Simply records the current location. */ |
b99bd4ef | 3470 | |
c19d1205 ZW |
3471 | static void |
3472 | s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) | |
3473 | { | |
3474 | demand_empty_rest_of_line (); | |
921e5f0a PB |
3475 | if (unwind.proc_start) |
3476 | { | |
c921be7d | 3477 | as_bad (_("duplicate .fnstart directive")); |
921e5f0a PB |
3478 | return; |
3479 | } | |
3480 | ||
c19d1205 ZW |
3481 | /* Mark the start of the function. */ |
3482 | unwind.proc_start = expr_build_dot (); | |
b99bd4ef | 3483 | |
c19d1205 ZW |
3484 | /* Reset the rest of the unwind info. */ |
3485 | unwind.opcode_count = 0; | |
3486 | unwind.table_entry = NULL; | |
3487 | unwind.personality_routine = NULL; | |
3488 | unwind.personality_index = -1; | |
3489 | unwind.frame_size = 0; | |
3490 | unwind.fp_offset = 0; | |
fdfde340 | 3491 | unwind.fp_reg = REG_SP; |
c19d1205 ZW |
3492 | unwind.fp_used = 0; |
3493 | unwind.sp_restored = 0; | |
3494 | } | |
b99bd4ef | 3495 | |
b99bd4ef | 3496 | |
c19d1205 ZW |
3497 | /* Parse a handlerdata directive. Creates the exception handling table entry |
3498 | for the function. */ | |
b99bd4ef | 3499 | |
c19d1205 ZW |
3500 | static void |
3501 | s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) | |
3502 | { | |
3503 | demand_empty_rest_of_line (); | |
921e5f0a | 3504 | if (!unwind.proc_start) |
c921be7d | 3505 | as_bad (MISSING_FNSTART); |
921e5f0a | 3506 | |
c19d1205 | 3507 | if (unwind.table_entry) |
6decc662 | 3508 | as_bad (_("duplicate .handlerdata directive")); |
f02232aa | 3509 | |
c19d1205 ZW |
3510 | create_unwind_entry (1); |
3511 | } | |
a737bd4d | 3512 | |
c19d1205 | 3513 | /* Parse an unwind_fnend directive. Generates the index table entry. */ |
b99bd4ef | 3514 | |
c19d1205 ZW |
3515 | static void |
3516 | s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) | |
3517 | { | |
3518 | long where; | |
3519 | char *ptr; | |
3520 | valueT val; | |
940b5ce0 | 3521 | unsigned int marked_pr_dependency; |
f02232aa | 3522 | |
c19d1205 | 3523 | demand_empty_rest_of_line (); |
f02232aa | 3524 | |
921e5f0a PB |
3525 | if (!unwind.proc_start) |
3526 | { | |
c921be7d | 3527 | as_bad (_(".fnend directive without .fnstart")); |
921e5f0a PB |
3528 | return; |
3529 | } | |
3530 | ||
c19d1205 ZW |
3531 | /* Add eh table entry. */ |
3532 | if (unwind.table_entry == NULL) | |
3533 | val = create_unwind_entry (0); | |
3534 | else | |
3535 | val = 0; | |
f02232aa | 3536 | |
c19d1205 ZW |
3537 | /* Add index table entry. This is two words. */ |
3538 | start_unwind_section (unwind.saved_seg, 1); | |
3539 | frag_align (2, 0, 0); | |
3540 | record_alignment (now_seg, 2); | |
b99bd4ef | 3541 | |
c19d1205 ZW |
3542 | ptr = frag_more (8); |
3543 | where = frag_now_fix () - 8; | |
f02232aa | 3544 | |
c19d1205 ZW |
3545 | /* Self relative offset of the function start. */ |
3546 | fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, | |
3547 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3548 | |
c19d1205 ZW |
3549 | /* Indicate dependency on EHABI-defined personality routines to the |
3550 | linker, if it hasn't been done already. */ | |
940b5ce0 DJ |
3551 | marked_pr_dependency |
3552 | = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency; | |
c19d1205 ZW |
3553 | if (unwind.personality_index >= 0 && unwind.personality_index < 3 |
3554 | && !(marked_pr_dependency & (1 << unwind.personality_index))) | |
3555 | { | |
5f4273c7 NC |
3556 | static const char *const name[] = |
3557 | { | |
3558 | "__aeabi_unwind_cpp_pr0", | |
3559 | "__aeabi_unwind_cpp_pr1", | |
3560 | "__aeabi_unwind_cpp_pr2" | |
3561 | }; | |
c19d1205 ZW |
3562 | symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); |
3563 | fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); | |
c19d1205 | 3564 | seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency |
940b5ce0 | 3565 | |= 1 << unwind.personality_index; |
c19d1205 | 3566 | } |
f02232aa | 3567 | |
c19d1205 ZW |
3568 | if (val) |
3569 | /* Inline exception table entry. */ | |
3570 | md_number_to_chars (ptr + 4, val, 4); | |
3571 | else | |
3572 | /* Self relative offset of the table entry. */ | |
3573 | fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, | |
3574 | BFD_RELOC_ARM_PREL31); | |
f02232aa | 3575 | |
c19d1205 ZW |
3576 | /* Restore the original section. */ |
3577 | subseg_set (unwind.saved_seg, unwind.saved_subseg); | |
921e5f0a PB |
3578 | |
3579 | unwind.proc_start = NULL; | |
c19d1205 | 3580 | } |
f02232aa | 3581 | |
f02232aa | 3582 | |
c19d1205 | 3583 | /* Parse an unwind_cantunwind directive. */ |
b99bd4ef | 3584 | |
c19d1205 ZW |
3585 | static void |
3586 | s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) | |
3587 | { | |
3588 | demand_empty_rest_of_line (); | |
921e5f0a | 3589 | if (!unwind.proc_start) |
c921be7d | 3590 | as_bad (MISSING_FNSTART); |
921e5f0a | 3591 | |
c19d1205 ZW |
3592 | if (unwind.personality_routine || unwind.personality_index != -1) |
3593 | as_bad (_("personality routine specified for cantunwind frame")); | |
b99bd4ef | 3594 | |
c19d1205 ZW |
3595 | unwind.personality_index = -2; |
3596 | } | |
b99bd4ef | 3597 | |
b99bd4ef | 3598 | |
c19d1205 | 3599 | /* Parse a personalityindex directive. */ |
b99bd4ef | 3600 | |
c19d1205 ZW |
3601 | static void |
3602 | s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) | |
3603 | { | |
3604 | expressionS exp; | |
b99bd4ef | 3605 | |
921e5f0a | 3606 | if (!unwind.proc_start) |
c921be7d | 3607 | as_bad (MISSING_FNSTART); |
921e5f0a | 3608 | |
c19d1205 ZW |
3609 | if (unwind.personality_routine || unwind.personality_index != -1) |
3610 | as_bad (_("duplicate .personalityindex directive")); | |
b99bd4ef | 3611 | |
c19d1205 | 3612 | expression (&exp); |
b99bd4ef | 3613 | |
c19d1205 ZW |
3614 | if (exp.X_op != O_constant |
3615 | || exp.X_add_number < 0 || exp.X_add_number > 15) | |
b99bd4ef | 3616 | { |
c19d1205 ZW |
3617 | as_bad (_("bad personality routine number")); |
3618 | ignore_rest_of_line (); | |
3619 | return; | |
b99bd4ef NC |
3620 | } |
3621 | ||
c19d1205 | 3622 | unwind.personality_index = exp.X_add_number; |
b99bd4ef | 3623 | |
c19d1205 ZW |
3624 | demand_empty_rest_of_line (); |
3625 | } | |
e16bb312 | 3626 | |
e16bb312 | 3627 | |
c19d1205 | 3628 | /* Parse a personality directive. */ |
e16bb312 | 3629 | |
c19d1205 ZW |
3630 | static void |
3631 | s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) | |
3632 | { | |
3633 | char *name, *p, c; | |
a737bd4d | 3634 | |
921e5f0a | 3635 | if (!unwind.proc_start) |
c921be7d | 3636 | as_bad (MISSING_FNSTART); |
921e5f0a | 3637 | |
c19d1205 ZW |
3638 | if (unwind.personality_routine || unwind.personality_index != -1) |
3639 | as_bad (_("duplicate .personality directive")); | |
a737bd4d | 3640 | |
c19d1205 ZW |
3641 | name = input_line_pointer; |
3642 | c = get_symbol_end (); | |
3643 | p = input_line_pointer; | |
3644 | unwind.personality_routine = symbol_find_or_make (name); | |
3645 | *p = c; | |
3646 | demand_empty_rest_of_line (); | |
3647 | } | |
e16bb312 | 3648 | |
e16bb312 | 3649 | |
c19d1205 | 3650 | /* Parse a directive saving core registers. */ |
e16bb312 | 3651 | |
c19d1205 ZW |
3652 | static void |
3653 | s_arm_unwind_save_core (void) | |
e16bb312 | 3654 | { |
c19d1205 ZW |
3655 | valueT op; |
3656 | long range; | |
3657 | int n; | |
e16bb312 | 3658 | |
c19d1205 ZW |
3659 | range = parse_reg_list (&input_line_pointer); |
3660 | if (range == FAIL) | |
e16bb312 | 3661 | { |
c19d1205 ZW |
3662 | as_bad (_("expected register list")); |
3663 | ignore_rest_of_line (); | |
3664 | return; | |
3665 | } | |
e16bb312 | 3666 | |
c19d1205 | 3667 | demand_empty_rest_of_line (); |
e16bb312 | 3668 | |
c19d1205 ZW |
3669 | /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} |
3670 | into .unwind_save {..., sp...}. We aren't bothered about the value of | |
3671 | ip because it is clobbered by calls. */ | |
3672 | if (unwind.sp_restored && unwind.fp_reg == 12 | |
3673 | && (range & 0x3000) == 0x1000) | |
3674 | { | |
3675 | unwind.opcode_count--; | |
3676 | unwind.sp_restored = 0; | |
3677 | range = (range | 0x2000) & ~0x1000; | |
3678 | unwind.pending_offset = 0; | |
3679 | } | |
e16bb312 | 3680 | |
01ae4198 DJ |
3681 | /* Pop r4-r15. */ |
3682 | if (range & 0xfff0) | |
c19d1205 | 3683 | { |
01ae4198 DJ |
3684 | /* See if we can use the short opcodes. These pop a block of up to 8 |
3685 | registers starting with r4, plus maybe r14. */ | |
3686 | for (n = 0; n < 8; n++) | |
3687 | { | |
3688 | /* Break at the first non-saved register. */ | |
3689 | if ((range & (1 << (n + 4))) == 0) | |
3690 | break; | |
3691 | } | |
3692 | /* See if there are any other bits set. */ | |
3693 | if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) | |
3694 | { | |
3695 | /* Use the long form. */ | |
3696 | op = 0x8000 | ((range >> 4) & 0xfff); | |
3697 | add_unwind_opcode (op, 2); | |
3698 | } | |
0dd132b6 | 3699 | else |
01ae4198 DJ |
3700 | { |
3701 | /* Use the short form. */ | |
3702 | if (range & 0x4000) | |
3703 | op = 0xa8; /* Pop r14. */ | |
3704 | else | |
3705 | op = 0xa0; /* Do not pop r14. */ | |
3706 | op |= (n - 1); | |
3707 | add_unwind_opcode (op, 1); | |
3708 | } | |
c19d1205 | 3709 | } |
0dd132b6 | 3710 | |
c19d1205 ZW |
3711 | /* Pop r0-r3. */ |
3712 | if (range & 0xf) | |
3713 | { | |
3714 | op = 0xb100 | (range & 0xf); | |
3715 | add_unwind_opcode (op, 2); | |
0dd132b6 NC |
3716 | } |
3717 | ||
c19d1205 ZW |
3718 | /* Record the number of bytes pushed. */ |
3719 | for (n = 0; n < 16; n++) | |
3720 | { | |
3721 | if (range & (1 << n)) | |
3722 | unwind.frame_size += 4; | |
3723 | } | |
0dd132b6 NC |
3724 | } |
3725 | ||
c19d1205 ZW |
3726 | |
3727 | /* Parse a directive saving FPA registers. */ | |
b99bd4ef NC |
3728 | |
3729 | static void | |
c19d1205 | 3730 | s_arm_unwind_save_fpa (int reg) |
b99bd4ef | 3731 | { |
c19d1205 ZW |
3732 | expressionS exp; |
3733 | int num_regs; | |
3734 | valueT op; | |
b99bd4ef | 3735 | |
c19d1205 ZW |
3736 | /* Get Number of registers to transfer. */ |
3737 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
3738 | expression (&exp); | |
3739 | else | |
3740 | exp.X_op = O_illegal; | |
b99bd4ef | 3741 | |
c19d1205 | 3742 | if (exp.X_op != O_constant) |
b99bd4ef | 3743 | { |
c19d1205 ZW |
3744 | as_bad (_("expected , <constant>")); |
3745 | ignore_rest_of_line (); | |
b99bd4ef NC |
3746 | return; |
3747 | } | |
3748 | ||
c19d1205 ZW |
3749 | num_regs = exp.X_add_number; |
3750 | ||
3751 | if (num_regs < 1 || num_regs > 4) | |
b99bd4ef | 3752 | { |
c19d1205 ZW |
3753 | as_bad (_("number of registers must be in the range [1:4]")); |
3754 | ignore_rest_of_line (); | |
b99bd4ef NC |
3755 | return; |
3756 | } | |
3757 | ||
c19d1205 | 3758 | demand_empty_rest_of_line (); |
b99bd4ef | 3759 | |
c19d1205 ZW |
3760 | if (reg == 4) |
3761 | { | |
3762 | /* Short form. */ | |
3763 | op = 0xb4 | (num_regs - 1); | |
3764 | add_unwind_opcode (op, 1); | |
3765 | } | |
b99bd4ef NC |
3766 | else |
3767 | { | |
c19d1205 ZW |
3768 | /* Long form. */ |
3769 | op = 0xc800 | (reg << 4) | (num_regs - 1); | |
3770 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3771 | } |
c19d1205 | 3772 | unwind.frame_size += num_regs * 12; |
b99bd4ef NC |
3773 | } |
3774 | ||
c19d1205 | 3775 | |
fa073d69 MS |
3776 | /* Parse a directive saving VFP registers for ARMv6 and above. */ |
3777 | ||
3778 | static void | |
3779 | s_arm_unwind_save_vfp_armv6 (void) | |
3780 | { | |
3781 | int count; | |
3782 | unsigned int start; | |
3783 | valueT op; | |
3784 | int num_vfpv3_regs = 0; | |
3785 | int num_regs_below_16; | |
3786 | ||
3787 | count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); | |
3788 | if (count == FAIL) | |
3789 | { | |
3790 | as_bad (_("expected register list")); | |
3791 | ignore_rest_of_line (); | |
3792 | return; | |
3793 | } | |
3794 | ||
3795 | demand_empty_rest_of_line (); | |
3796 | ||
3797 | /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather | |
3798 | than FSTMX/FLDMX-style ones). */ | |
3799 | ||
3800 | /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ | |
3801 | if (start >= 16) | |
3802 | num_vfpv3_regs = count; | |
3803 | else if (start + count > 16) | |
3804 | num_vfpv3_regs = start + count - 16; | |
3805 | ||
3806 | if (num_vfpv3_regs > 0) | |
3807 | { | |
3808 | int start_offset = start > 16 ? start - 16 : 0; | |
3809 | op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); | |
3810 | add_unwind_opcode (op, 2); | |
3811 | } | |
3812 | ||
3813 | /* Generate opcode for registers numbered in the range 0 .. 15. */ | |
3814 | num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; | |
9c2799c2 | 3815 | gas_assert (num_regs_below_16 + num_vfpv3_regs == count); |
fa073d69 MS |
3816 | if (num_regs_below_16 > 0) |
3817 | { | |
3818 | op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); | |
3819 | add_unwind_opcode (op, 2); | |
3820 | } | |
3821 | ||
3822 | unwind.frame_size += count * 8; | |
3823 | } | |
3824 | ||
3825 | ||
3826 | /* Parse a directive saving VFP registers for pre-ARMv6. */ | |
b99bd4ef NC |
3827 | |
3828 | static void | |
c19d1205 | 3829 | s_arm_unwind_save_vfp (void) |
b99bd4ef | 3830 | { |
c19d1205 | 3831 | int count; |
ca3f61f7 | 3832 | unsigned int reg; |
c19d1205 | 3833 | valueT op; |
b99bd4ef | 3834 | |
5287ad62 | 3835 | count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); |
c19d1205 | 3836 | if (count == FAIL) |
b99bd4ef | 3837 | { |
c19d1205 ZW |
3838 | as_bad (_("expected register list")); |
3839 | ignore_rest_of_line (); | |
b99bd4ef NC |
3840 | return; |
3841 | } | |
3842 | ||
c19d1205 | 3843 | demand_empty_rest_of_line (); |
b99bd4ef | 3844 | |
c19d1205 | 3845 | if (reg == 8) |
b99bd4ef | 3846 | { |
c19d1205 ZW |
3847 | /* Short form. */ |
3848 | op = 0xb8 | (count - 1); | |
3849 | add_unwind_opcode (op, 1); | |
b99bd4ef | 3850 | } |
c19d1205 | 3851 | else |
b99bd4ef | 3852 | { |
c19d1205 ZW |
3853 | /* Long form. */ |
3854 | op = 0xb300 | (reg << 4) | (count - 1); | |
3855 | add_unwind_opcode (op, 2); | |
b99bd4ef | 3856 | } |
c19d1205 ZW |
3857 | unwind.frame_size += count * 8 + 4; |
3858 | } | |
b99bd4ef | 3859 | |
b99bd4ef | 3860 | |
c19d1205 ZW |
3861 | /* Parse a directive saving iWMMXt data registers. */ |
3862 | ||
3863 | static void | |
3864 | s_arm_unwind_save_mmxwr (void) | |
3865 | { | |
3866 | int reg; | |
3867 | int hi_reg; | |
3868 | int i; | |
3869 | unsigned mask = 0; | |
3870 | valueT op; | |
b99bd4ef | 3871 | |
c19d1205 ZW |
3872 | if (*input_line_pointer == '{') |
3873 | input_line_pointer++; | |
b99bd4ef | 3874 | |
c19d1205 | 3875 | do |
b99bd4ef | 3876 | { |
dcbf9037 | 3877 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
b99bd4ef | 3878 | |
c19d1205 | 3879 | if (reg == FAIL) |
b99bd4ef | 3880 | { |
9b7132d3 | 3881 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 | 3882 | goto error; |
b99bd4ef NC |
3883 | } |
3884 | ||
c19d1205 ZW |
3885 | if (mask >> reg) |
3886 | as_tsktsk (_("register list not in ascending order")); | |
3887 | mask |= 1 << reg; | |
b99bd4ef | 3888 | |
c19d1205 ZW |
3889 | if (*input_line_pointer == '-') |
3890 | { | |
3891 | input_line_pointer++; | |
dcbf9037 | 3892 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); |
c19d1205 ZW |
3893 | if (hi_reg == FAIL) |
3894 | { | |
9b7132d3 | 3895 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); |
c19d1205 ZW |
3896 | goto error; |
3897 | } | |
3898 | else if (reg >= hi_reg) | |
3899 | { | |
3900 | as_bad (_("bad register range")); | |
3901 | goto error; | |
3902 | } | |
3903 | for (; reg < hi_reg; reg++) | |
3904 | mask |= 1 << reg; | |
3905 | } | |
3906 | } | |
3907 | while (skip_past_comma (&input_line_pointer) != FAIL); | |
b99bd4ef | 3908 | |
c19d1205 ZW |
3909 | if (*input_line_pointer == '}') |
3910 | input_line_pointer++; | |
b99bd4ef | 3911 | |
c19d1205 | 3912 | demand_empty_rest_of_line (); |
b99bd4ef | 3913 | |
708587a4 | 3914 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
3915 | the list. */ |
3916 | flush_pending_unwind (); | |
b99bd4ef | 3917 | |
c19d1205 | 3918 | for (i = 0; i < 16; i++) |
b99bd4ef | 3919 | { |
c19d1205 ZW |
3920 | if (mask & (1 << i)) |
3921 | unwind.frame_size += 8; | |
b99bd4ef NC |
3922 | } |
3923 | ||
c19d1205 ZW |
3924 | /* Attempt to combine with a previous opcode. We do this because gcc |
3925 | likes to output separate unwind directives for a single block of | |
3926 | registers. */ | |
3927 | if (unwind.opcode_count > 0) | |
b99bd4ef | 3928 | { |
c19d1205 ZW |
3929 | i = unwind.opcodes[unwind.opcode_count - 1]; |
3930 | if ((i & 0xf8) == 0xc0) | |
3931 | { | |
3932 | i &= 7; | |
3933 | /* Only merge if the blocks are contiguous. */ | |
3934 | if (i < 6) | |
3935 | { | |
3936 | if ((mask & 0xfe00) == (1 << 9)) | |
3937 | { | |
3938 | mask |= ((1 << (i + 11)) - 1) & 0xfc00; | |
3939 | unwind.opcode_count--; | |
3940 | } | |
3941 | } | |
3942 | else if (i == 6 && unwind.opcode_count >= 2) | |
3943 | { | |
3944 | i = unwind.opcodes[unwind.opcode_count - 2]; | |
3945 | reg = i >> 4; | |
3946 | i &= 0xf; | |
b99bd4ef | 3947 | |
c19d1205 ZW |
3948 | op = 0xffff << (reg - 1); |
3949 | if (reg > 0 | |
87a1fd79 | 3950 | && ((mask & op) == (1u << (reg - 1)))) |
c19d1205 ZW |
3951 | { |
3952 | op = (1 << (reg + i + 1)) - 1; | |
3953 | op &= ~((1 << reg) - 1); | |
3954 | mask |= op; | |
3955 | unwind.opcode_count -= 2; | |
3956 | } | |
3957 | } | |
3958 | } | |
b99bd4ef NC |
3959 | } |
3960 | ||
c19d1205 ZW |
3961 | hi_reg = 15; |
3962 | /* We want to generate opcodes in the order the registers have been | |
3963 | saved, ie. descending order. */ | |
3964 | for (reg = 15; reg >= -1; reg--) | |
b99bd4ef | 3965 | { |
c19d1205 ZW |
3966 | /* Save registers in blocks. */ |
3967 | if (reg < 0 | |
3968 | || !(mask & (1 << reg))) | |
3969 | { | |
3970 | /* We found an unsaved reg. Generate opcodes to save the | |
5f4273c7 | 3971 | preceding block. */ |
c19d1205 ZW |
3972 | if (reg != hi_reg) |
3973 | { | |
3974 | if (reg == 9) | |
3975 | { | |
3976 | /* Short form. */ | |
3977 | op = 0xc0 | (hi_reg - 10); | |
3978 | add_unwind_opcode (op, 1); | |
3979 | } | |
3980 | else | |
3981 | { | |
3982 | /* Long form. */ | |
3983 | op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); | |
3984 | add_unwind_opcode (op, 2); | |
3985 | } | |
3986 | } | |
3987 | hi_reg = reg - 1; | |
3988 | } | |
b99bd4ef NC |
3989 | } |
3990 | ||
c19d1205 ZW |
3991 | return; |
3992 | error: | |
3993 | ignore_rest_of_line (); | |
b99bd4ef NC |
3994 | } |
3995 | ||
3996 | static void | |
c19d1205 | 3997 | s_arm_unwind_save_mmxwcg (void) |
b99bd4ef | 3998 | { |
c19d1205 ZW |
3999 | int reg; |
4000 | int hi_reg; | |
4001 | unsigned mask = 0; | |
4002 | valueT op; | |
b99bd4ef | 4003 | |
c19d1205 ZW |
4004 | if (*input_line_pointer == '{') |
4005 | input_line_pointer++; | |
b99bd4ef | 4006 | |
c19d1205 | 4007 | do |
b99bd4ef | 4008 | { |
dcbf9037 | 4009 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
b99bd4ef | 4010 | |
c19d1205 ZW |
4011 | if (reg == FAIL) |
4012 | { | |
9b7132d3 | 4013 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4014 | goto error; |
4015 | } | |
b99bd4ef | 4016 | |
c19d1205 ZW |
4017 | reg -= 8; |
4018 | if (mask >> reg) | |
4019 | as_tsktsk (_("register list not in ascending order")); | |
4020 | mask |= 1 << reg; | |
b99bd4ef | 4021 | |
c19d1205 ZW |
4022 | if (*input_line_pointer == '-') |
4023 | { | |
4024 | input_line_pointer++; | |
dcbf9037 | 4025 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); |
c19d1205 ZW |
4026 | if (hi_reg == FAIL) |
4027 | { | |
9b7132d3 | 4028 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); |
c19d1205 ZW |
4029 | goto error; |
4030 | } | |
4031 | else if (reg >= hi_reg) | |
4032 | { | |
4033 | as_bad (_("bad register range")); | |
4034 | goto error; | |
4035 | } | |
4036 | for (; reg < hi_reg; reg++) | |
4037 | mask |= 1 << reg; | |
4038 | } | |
b99bd4ef | 4039 | } |
c19d1205 | 4040 | while (skip_past_comma (&input_line_pointer) != FAIL); |
b99bd4ef | 4041 | |
c19d1205 ZW |
4042 | if (*input_line_pointer == '}') |
4043 | input_line_pointer++; | |
b99bd4ef | 4044 | |
c19d1205 ZW |
4045 | demand_empty_rest_of_line (); |
4046 | ||
708587a4 | 4047 | /* Generate any deferred opcodes because we're going to be looking at |
c19d1205 ZW |
4048 | the list. */ |
4049 | flush_pending_unwind (); | |
b99bd4ef | 4050 | |
c19d1205 | 4051 | for (reg = 0; reg < 16; reg++) |
b99bd4ef | 4052 | { |
c19d1205 ZW |
4053 | if (mask & (1 << reg)) |
4054 | unwind.frame_size += 4; | |
b99bd4ef | 4055 | } |
c19d1205 ZW |
4056 | op = 0xc700 | mask; |
4057 | add_unwind_opcode (op, 2); | |
4058 | return; | |
4059 | error: | |
4060 | ignore_rest_of_line (); | |
b99bd4ef NC |
4061 | } |
4062 | ||
c19d1205 | 4063 | |
fa073d69 MS |
4064 | /* Parse an unwind_save directive. |
4065 | If the argument is non-zero, this is a .vsave directive. */ | |
c19d1205 | 4066 | |
b99bd4ef | 4067 | static void |
fa073d69 | 4068 | s_arm_unwind_save (int arch_v6) |
b99bd4ef | 4069 | { |
c19d1205 ZW |
4070 | char *peek; |
4071 | struct reg_entry *reg; | |
4072 | bfd_boolean had_brace = FALSE; | |
b99bd4ef | 4073 | |
921e5f0a | 4074 | if (!unwind.proc_start) |
c921be7d | 4075 | as_bad (MISSING_FNSTART); |
921e5f0a | 4076 | |
c19d1205 ZW |
4077 | /* Figure out what sort of save we have. */ |
4078 | peek = input_line_pointer; | |
b99bd4ef | 4079 | |
c19d1205 | 4080 | if (*peek == '{') |
b99bd4ef | 4081 | { |
c19d1205 ZW |
4082 | had_brace = TRUE; |
4083 | peek++; | |
b99bd4ef NC |
4084 | } |
4085 | ||
c19d1205 | 4086 | reg = arm_reg_parse_multi (&peek); |
b99bd4ef | 4087 | |
c19d1205 | 4088 | if (!reg) |
b99bd4ef | 4089 | { |
c19d1205 ZW |
4090 | as_bad (_("register expected")); |
4091 | ignore_rest_of_line (); | |
b99bd4ef NC |
4092 | return; |
4093 | } | |
4094 | ||
c19d1205 | 4095 | switch (reg->type) |
b99bd4ef | 4096 | { |
c19d1205 ZW |
4097 | case REG_TYPE_FN: |
4098 | if (had_brace) | |
4099 | { | |
4100 | as_bad (_("FPA .unwind_save does not take a register list")); | |
4101 | ignore_rest_of_line (); | |
4102 | return; | |
4103 | } | |
93ac2687 | 4104 | input_line_pointer = peek; |
c19d1205 | 4105 | s_arm_unwind_save_fpa (reg->number); |
b99bd4ef | 4106 | return; |
c19d1205 ZW |
4107 | |
4108 | case REG_TYPE_RN: s_arm_unwind_save_core (); return; | |
fa073d69 MS |
4109 | case REG_TYPE_VFD: |
4110 | if (arch_v6) | |
4111 | s_arm_unwind_save_vfp_armv6 (); | |
4112 | else | |
4113 | s_arm_unwind_save_vfp (); | |
4114 | return; | |
c19d1205 ZW |
4115 | case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; |
4116 | case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; | |
4117 | ||
4118 | default: | |
4119 | as_bad (_(".unwind_save does not support this kind of register")); | |
4120 | ignore_rest_of_line (); | |
b99bd4ef | 4121 | } |
c19d1205 | 4122 | } |
b99bd4ef | 4123 | |
b99bd4ef | 4124 | |
c19d1205 ZW |
4125 | /* Parse an unwind_movsp directive. */ |
4126 | ||
4127 | static void | |
4128 | s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) | |
4129 | { | |
4130 | int reg; | |
4131 | valueT op; | |
4fa3602b | 4132 | int offset; |
c19d1205 | 4133 | |
921e5f0a | 4134 | if (!unwind.proc_start) |
c921be7d | 4135 | as_bad (MISSING_FNSTART); |
921e5f0a | 4136 | |
dcbf9037 | 4137 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 | 4138 | if (reg == FAIL) |
b99bd4ef | 4139 | { |
9b7132d3 | 4140 | as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); |
c19d1205 | 4141 | ignore_rest_of_line (); |
b99bd4ef NC |
4142 | return; |
4143 | } | |
4fa3602b PB |
4144 | |
4145 | /* Optional constant. */ | |
4146 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4147 | { | |
4148 | if (immediate_for_directive (&offset) == FAIL) | |
4149 | return; | |
4150 | } | |
4151 | else | |
4152 | offset = 0; | |
4153 | ||
c19d1205 | 4154 | demand_empty_rest_of_line (); |
b99bd4ef | 4155 | |
c19d1205 | 4156 | if (reg == REG_SP || reg == REG_PC) |
b99bd4ef | 4157 | { |
c19d1205 | 4158 | as_bad (_("SP and PC not permitted in .unwind_movsp directive")); |
b99bd4ef NC |
4159 | return; |
4160 | } | |
4161 | ||
c19d1205 ZW |
4162 | if (unwind.fp_reg != REG_SP) |
4163 | as_bad (_("unexpected .unwind_movsp directive")); | |
b99bd4ef | 4164 | |
c19d1205 ZW |
4165 | /* Generate opcode to restore the value. */ |
4166 | op = 0x90 | reg; | |
4167 | add_unwind_opcode (op, 1); | |
4168 | ||
4169 | /* Record the information for later. */ | |
4170 | unwind.fp_reg = reg; | |
4fa3602b | 4171 | unwind.fp_offset = unwind.frame_size - offset; |
c19d1205 | 4172 | unwind.sp_restored = 1; |
b05fe5cf ZW |
4173 | } |
4174 | ||
c19d1205 ZW |
4175 | /* Parse an unwind_pad directive. */ |
4176 | ||
b05fe5cf | 4177 | static void |
c19d1205 | 4178 | s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) |
b05fe5cf | 4179 | { |
c19d1205 | 4180 | int offset; |
b05fe5cf | 4181 | |
921e5f0a | 4182 | if (!unwind.proc_start) |
c921be7d | 4183 | as_bad (MISSING_FNSTART); |
921e5f0a | 4184 | |
c19d1205 ZW |
4185 | if (immediate_for_directive (&offset) == FAIL) |
4186 | return; | |
b99bd4ef | 4187 | |
c19d1205 ZW |
4188 | if (offset & 3) |
4189 | { | |
4190 | as_bad (_("stack increment must be multiple of 4")); | |
4191 | ignore_rest_of_line (); | |
4192 | return; | |
4193 | } | |
b99bd4ef | 4194 | |
c19d1205 ZW |
4195 | /* Don't generate any opcodes, just record the details for later. */ |
4196 | unwind.frame_size += offset; | |
4197 | unwind.pending_offset += offset; | |
4198 | ||
4199 | demand_empty_rest_of_line (); | |
4200 | } | |
4201 | ||
4202 | /* Parse an unwind_setfp directive. */ | |
4203 | ||
4204 | static void | |
4205 | s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) | |
b99bd4ef | 4206 | { |
c19d1205 ZW |
4207 | int sp_reg; |
4208 | int fp_reg; | |
4209 | int offset; | |
4210 | ||
921e5f0a | 4211 | if (!unwind.proc_start) |
c921be7d | 4212 | as_bad (MISSING_FNSTART); |
921e5f0a | 4213 | |
dcbf9037 | 4214 | fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
c19d1205 ZW |
4215 | if (skip_past_comma (&input_line_pointer) == FAIL) |
4216 | sp_reg = FAIL; | |
4217 | else | |
dcbf9037 | 4218 | sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); |
b99bd4ef | 4219 | |
c19d1205 ZW |
4220 | if (fp_reg == FAIL || sp_reg == FAIL) |
4221 | { | |
4222 | as_bad (_("expected <reg>, <reg>")); | |
4223 | ignore_rest_of_line (); | |
4224 | return; | |
4225 | } | |
b99bd4ef | 4226 | |
c19d1205 ZW |
4227 | /* Optional constant. */ |
4228 | if (skip_past_comma (&input_line_pointer) != FAIL) | |
4229 | { | |
4230 | if (immediate_for_directive (&offset) == FAIL) | |
4231 | return; | |
4232 | } | |
4233 | else | |
4234 | offset = 0; | |
a737bd4d | 4235 | |
c19d1205 | 4236 | demand_empty_rest_of_line (); |
a737bd4d | 4237 | |
fdfde340 | 4238 | if (sp_reg != REG_SP && sp_reg != unwind.fp_reg) |
a737bd4d | 4239 | { |
c19d1205 ZW |
4240 | as_bad (_("register must be either sp or set by a previous" |
4241 | "unwind_movsp directive")); | |
4242 | return; | |
a737bd4d NC |
4243 | } |
4244 | ||
c19d1205 ZW |
4245 | /* Don't generate any opcodes, just record the information for later. */ |
4246 | unwind.fp_reg = fp_reg; | |
4247 | unwind.fp_used = 1; | |
fdfde340 | 4248 | if (sp_reg == REG_SP) |
c19d1205 ZW |
4249 | unwind.fp_offset = unwind.frame_size - offset; |
4250 | else | |
4251 | unwind.fp_offset -= offset; | |
a737bd4d NC |
4252 | } |
4253 | ||
c19d1205 ZW |
4254 | /* Parse an unwind_raw directive. */ |
4255 | ||
4256 | static void | |
4257 | s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) | |
a737bd4d | 4258 | { |
c19d1205 | 4259 | expressionS exp; |
708587a4 | 4260 | /* This is an arbitrary limit. */ |
c19d1205 ZW |
4261 | unsigned char op[16]; |
4262 | int count; | |
a737bd4d | 4263 | |
921e5f0a | 4264 | if (!unwind.proc_start) |
c921be7d | 4265 | as_bad (MISSING_FNSTART); |
921e5f0a | 4266 | |
c19d1205 ZW |
4267 | expression (&exp); |
4268 | if (exp.X_op == O_constant | |
4269 | && skip_past_comma (&input_line_pointer) != FAIL) | |
a737bd4d | 4270 | { |
c19d1205 ZW |
4271 | unwind.frame_size += exp.X_add_number; |
4272 | expression (&exp); | |
4273 | } | |
4274 | else | |
4275 | exp.X_op = O_illegal; | |
a737bd4d | 4276 | |
c19d1205 ZW |
4277 | if (exp.X_op != O_constant) |
4278 | { | |
4279 | as_bad (_("expected <offset>, <opcode>")); | |
4280 | ignore_rest_of_line (); | |
4281 | return; | |
4282 | } | |
a737bd4d | 4283 | |
c19d1205 | 4284 | count = 0; |
a737bd4d | 4285 | |
c19d1205 ZW |
4286 | /* Parse the opcode. */ |
4287 | for (;;) | |
4288 | { | |
4289 | if (count >= 16) | |
4290 | { | |
4291 | as_bad (_("unwind opcode too long")); | |
4292 | ignore_rest_of_line (); | |
a737bd4d | 4293 | } |
c19d1205 | 4294 | if (exp.X_op != O_constant || exp.X_add_number & ~0xff) |
a737bd4d | 4295 | { |
c19d1205 ZW |
4296 | as_bad (_("invalid unwind opcode")); |
4297 | ignore_rest_of_line (); | |
4298 | return; | |
a737bd4d | 4299 | } |
c19d1205 | 4300 | op[count++] = exp.X_add_number; |
a737bd4d | 4301 | |
c19d1205 ZW |
4302 | /* Parse the next byte. */ |
4303 | if (skip_past_comma (&input_line_pointer) == FAIL) | |
4304 | break; | |
a737bd4d | 4305 | |
c19d1205 ZW |
4306 | expression (&exp); |
4307 | } | |
b99bd4ef | 4308 | |
c19d1205 ZW |
4309 | /* Add the opcode bytes in reverse order. */ |
4310 | while (count--) | |
4311 | add_unwind_opcode (op[count], 1); | |
b99bd4ef | 4312 | |
c19d1205 | 4313 | demand_empty_rest_of_line (); |
b99bd4ef | 4314 | } |
ee065d83 PB |
4315 | |
4316 | ||
4317 | /* Parse a .eabi_attribute directive. */ | |
4318 | ||
4319 | static void | |
4320 | s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) | |
4321 | { | |
ee3c0378 AS |
4322 | int tag = s_vendor_attribute (OBJ_ATTR_PROC); |
4323 | ||
4324 | if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) | |
4325 | attributes_set_explicitly[tag] = 1; | |
ee065d83 PB |
4326 | } |
4327 | ||
0855e32b NS |
4328 | /* Emit a tls fix for the symbol. */ |
4329 | ||
4330 | static void | |
4331 | s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED) | |
4332 | { | |
4333 | char *p; | |
4334 | expressionS exp; | |
4335 | #ifdef md_flush_pending_output | |
4336 | md_flush_pending_output (); | |
4337 | #endif | |
4338 | ||
4339 | #ifdef md_cons_align | |
4340 | md_cons_align (4); | |
4341 | #endif | |
4342 | ||
4343 | /* Since we're just labelling the code, there's no need to define a | |
4344 | mapping symbol. */ | |
4345 | expression (&exp); | |
4346 | p = obstack_next_free (&frchain_now->frch_obstack); | |
4347 | fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0, | |
4348 | thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
4349 | : BFD_RELOC_ARM_TLS_DESCSEQ); | |
4350 | } | |
cdf9ccec | 4351 | #endif /* OBJ_ELF */ |
0855e32b | 4352 | |
ee065d83 | 4353 | static void s_arm_arch (int); |
7a1d4c38 | 4354 | static void s_arm_object_arch (int); |
ee065d83 PB |
4355 | static void s_arm_cpu (int); |
4356 | static void s_arm_fpu (int); | |
69133863 | 4357 | static void s_arm_arch_extension (int); |
b99bd4ef | 4358 | |
f0927246 NC |
4359 | #ifdef TE_PE |
4360 | ||
4361 | static void | |
5f4273c7 | 4362 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
f0927246 NC |
4363 | { |
4364 | expressionS exp; | |
4365 | ||
4366 | do | |
4367 | { | |
4368 | expression (&exp); | |
4369 | if (exp.X_op == O_symbol) | |
4370 | exp.X_op = O_secrel; | |
4371 | ||
4372 | emit_expr (&exp, 4); | |
4373 | } | |
4374 | while (*input_line_pointer++ == ','); | |
4375 | ||
4376 | input_line_pointer--; | |
4377 | demand_empty_rest_of_line (); | |
4378 | } | |
4379 | #endif /* TE_PE */ | |
4380 | ||
c19d1205 ZW |
4381 | /* This table describes all the machine specific pseudo-ops the assembler |
4382 | has to support. The fields are: | |
4383 | pseudo-op name without dot | |
4384 | function to call to execute this pseudo-op | |
4385 | Integer arg to pass to the function. */ | |
b99bd4ef | 4386 | |
c19d1205 | 4387 | const pseudo_typeS md_pseudo_table[] = |
b99bd4ef | 4388 | { |
c19d1205 ZW |
4389 | /* Never called because '.req' does not start a line. */ |
4390 | { "req", s_req, 0 }, | |
dcbf9037 JB |
4391 | /* Following two are likewise never called. */ |
4392 | { "dn", s_dn, 0 }, | |
4393 | { "qn", s_qn, 0 }, | |
c19d1205 ZW |
4394 | { "unreq", s_unreq, 0 }, |
4395 | { "bss", s_bss, 0 }, | |
4396 | { "align", s_align, 0 }, | |
4397 | { "arm", s_arm, 0 }, | |
4398 | { "thumb", s_thumb, 0 }, | |
4399 | { "code", s_code, 0 }, | |
4400 | { "force_thumb", s_force_thumb, 0 }, | |
4401 | { "thumb_func", s_thumb_func, 0 }, | |
4402 | { "thumb_set", s_thumb_set, 0 }, | |
4403 | { "even", s_even, 0 }, | |
4404 | { "ltorg", s_ltorg, 0 }, | |
4405 | { "pool", s_ltorg, 0 }, | |
4406 | { "syntax", s_syntax, 0 }, | |
8463be01 PB |
4407 | { "cpu", s_arm_cpu, 0 }, |
4408 | { "arch", s_arm_arch, 0 }, | |
7a1d4c38 | 4409 | { "object_arch", s_arm_object_arch, 0 }, |
8463be01 | 4410 | { "fpu", s_arm_fpu, 0 }, |
69133863 | 4411 | { "arch_extension", s_arm_arch_extension, 0 }, |
c19d1205 | 4412 | #ifdef OBJ_ELF |
c921be7d NC |
4413 | { "word", s_arm_elf_cons, 4 }, |
4414 | { "long", s_arm_elf_cons, 4 }, | |
4415 | { "inst.n", s_arm_elf_inst, 2 }, | |
4416 | { "inst.w", s_arm_elf_inst, 4 }, | |
4417 | { "inst", s_arm_elf_inst, 0 }, | |
4418 | { "rel31", s_arm_rel31, 0 }, | |
c19d1205 ZW |
4419 | { "fnstart", s_arm_unwind_fnstart, 0 }, |
4420 | { "fnend", s_arm_unwind_fnend, 0 }, | |
4421 | { "cantunwind", s_arm_unwind_cantunwind, 0 }, | |
4422 | { "personality", s_arm_unwind_personality, 0 }, | |
4423 | { "personalityindex", s_arm_unwind_personalityindex, 0 }, | |
4424 | { "handlerdata", s_arm_unwind_handlerdata, 0 }, | |
4425 | { "save", s_arm_unwind_save, 0 }, | |
fa073d69 | 4426 | { "vsave", s_arm_unwind_save, 1 }, |
c19d1205 ZW |
4427 | { "movsp", s_arm_unwind_movsp, 0 }, |
4428 | { "pad", s_arm_unwind_pad, 0 }, | |
4429 | { "setfp", s_arm_unwind_setfp, 0 }, | |
4430 | { "unwind_raw", s_arm_unwind_raw, 0 }, | |
ee065d83 | 4431 | { "eabi_attribute", s_arm_eabi_attribute, 0 }, |
0855e32b | 4432 | { "tlsdescseq", s_arm_tls_descseq, 0 }, |
c19d1205 ZW |
4433 | #else |
4434 | { "word", cons, 4}, | |
f0927246 NC |
4435 | |
4436 | /* These are used for dwarf. */ | |
4437 | {"2byte", cons, 2}, | |
4438 | {"4byte", cons, 4}, | |
4439 | {"8byte", cons, 8}, | |
4440 | /* These are used for dwarf2. */ | |
4441 | { "file", (void (*) (int)) dwarf2_directive_file, 0 }, | |
4442 | { "loc", dwarf2_directive_loc, 0 }, | |
4443 | { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, | |
c19d1205 ZW |
4444 | #endif |
4445 | { "extend", float_cons, 'x' }, | |
4446 | { "ldouble", float_cons, 'x' }, | |
4447 | { "packed", float_cons, 'p' }, | |
f0927246 NC |
4448 | #ifdef TE_PE |
4449 | {"secrel32", pe_directive_secrel, 0}, | |
4450 | #endif | |
c19d1205 ZW |
4451 | { 0, 0, 0 } |
4452 | }; | |
4453 | \f | |
4454 | /* Parser functions used exclusively in instruction operands. */ | |
b99bd4ef | 4455 | |
c19d1205 ZW |
4456 | /* Generic immediate-value read function for use in insn parsing. |
4457 | STR points to the beginning of the immediate (the leading #); | |
4458 | VAL receives the value; if the value is outside [MIN, MAX] | |
4459 | issue an error. PREFIX_OPT is true if the immediate prefix is | |
4460 | optional. */ | |
b99bd4ef | 4461 | |
c19d1205 ZW |
4462 | static int |
4463 | parse_immediate (char **str, int *val, int min, int max, | |
4464 | bfd_boolean prefix_opt) | |
4465 | { | |
4466 | expressionS exp; | |
4467 | my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); | |
4468 | if (exp.X_op != O_constant) | |
b99bd4ef | 4469 | { |
c19d1205 ZW |
4470 | inst.error = _("constant expression required"); |
4471 | return FAIL; | |
4472 | } | |
b99bd4ef | 4473 | |
c19d1205 ZW |
4474 | if (exp.X_add_number < min || exp.X_add_number > max) |
4475 | { | |
4476 | inst.error = _("immediate value out of range"); | |
4477 | return FAIL; | |
4478 | } | |
b99bd4ef | 4479 | |
c19d1205 ZW |
4480 | *val = exp.X_add_number; |
4481 | return SUCCESS; | |
4482 | } | |
b99bd4ef | 4483 | |
5287ad62 | 4484 | /* Less-generic immediate-value read function with the possibility of loading a |
036dc3f7 | 4485 | big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate |
5287ad62 JB |
4486 | instructions. Puts the result directly in inst.operands[i]. */ |
4487 | ||
4488 | static int | |
4489 | parse_big_immediate (char **str, int i) | |
4490 | { | |
4491 | expressionS exp; | |
4492 | char *ptr = *str; | |
4493 | ||
4494 | my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); | |
4495 | ||
4496 | if (exp.X_op == O_constant) | |
036dc3f7 PB |
4497 | { |
4498 | inst.operands[i].imm = exp.X_add_number & 0xffffffff; | |
4499 | /* If we're on a 64-bit host, then a 64-bit number can be returned using | |
4500 | O_constant. We have to be careful not to break compilation for | |
4501 | 32-bit X_add_number, though. */ | |
58ad575f | 4502 | if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0) |
036dc3f7 PB |
4503 | { |
4504 | /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ | |
4505 | inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; | |
4506 | inst.operands[i].regisimm = 1; | |
4507 | } | |
4508 | } | |
5287ad62 | 4509 | else if (exp.X_op == O_big |
95b75c01 | 4510 | && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32) |
5287ad62 JB |
4511 | { |
4512 | unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; | |
95b75c01 | 4513 | |
5287ad62 JB |
4514 | /* Bignums have their least significant bits in |
4515 | generic_bignum[0]. Make sure we put 32 bits in imm and | |
4516 | 32 bits in reg, in a (hopefully) portable way. */ | |
9c2799c2 | 4517 | gas_assert (parts != 0); |
95b75c01 NC |
4518 | |
4519 | /* Make sure that the number is not too big. | |
4520 | PR 11972: Bignums can now be sign-extended to the | |
4521 | size of a .octa so check that the out of range bits | |
4522 | are all zero or all one. */ | |
4523 | if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64) | |
4524 | { | |
4525 | LITTLENUM_TYPE m = -1; | |
4526 | ||
4527 | if (generic_bignum[parts * 2] != 0 | |
4528 | && generic_bignum[parts * 2] != m) | |
4529 | return FAIL; | |
4530 | ||
4531 | for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++) | |
4532 | if (generic_bignum[j] != generic_bignum[j-1]) | |
4533 | return FAIL; | |
4534 | } | |
4535 | ||
5287ad62 JB |
4536 | inst.operands[i].imm = 0; |
4537 | for (j = 0; j < parts; j++, idx++) | |
4538 | inst.operands[i].imm |= generic_bignum[idx] | |
4539 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4540 | inst.operands[i].reg = 0; | |
4541 | for (j = 0; j < parts; j++, idx++) | |
4542 | inst.operands[i].reg |= generic_bignum[idx] | |
4543 | << (LITTLENUM_NUMBER_OF_BITS * j); | |
4544 | inst.operands[i].regisimm = 1; | |
4545 | } | |
4546 | else | |
4547 | return FAIL; | |
5f4273c7 | 4548 | |
5287ad62 JB |
4549 | *str = ptr; |
4550 | ||
4551 | return SUCCESS; | |
4552 | } | |
4553 | ||
c19d1205 ZW |
4554 | /* Returns the pseudo-register number of an FPA immediate constant, |
4555 | or FAIL if there isn't a valid constant here. */ | |
b99bd4ef | 4556 | |
c19d1205 ZW |
4557 | static int |
4558 | parse_fpa_immediate (char ** str) | |
4559 | { | |
4560 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4561 | char * save_in; | |
4562 | expressionS exp; | |
4563 | int i; | |
4564 | int j; | |
b99bd4ef | 4565 | |
c19d1205 ZW |
4566 | /* First try and match exact strings, this is to guarantee |
4567 | that some formats will work even for cross assembly. */ | |
b99bd4ef | 4568 | |
c19d1205 ZW |
4569 | for (i = 0; fp_const[i]; i++) |
4570 | { | |
4571 | if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) | |
b99bd4ef | 4572 | { |
c19d1205 | 4573 | char *start = *str; |
b99bd4ef | 4574 | |
c19d1205 ZW |
4575 | *str += strlen (fp_const[i]); |
4576 | if (is_end_of_line[(unsigned char) **str]) | |
4577 | return i + 8; | |
4578 | *str = start; | |
4579 | } | |
4580 | } | |
b99bd4ef | 4581 | |
c19d1205 ZW |
4582 | /* Just because we didn't get a match doesn't mean that the constant |
4583 | isn't valid, just that it is in a format that we don't | |
4584 | automatically recognize. Try parsing it with the standard | |
4585 | expression routines. */ | |
b99bd4ef | 4586 | |
c19d1205 | 4587 | memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); |
b99bd4ef | 4588 | |
c19d1205 ZW |
4589 | /* Look for a raw floating point number. */ |
4590 | if ((save_in = atof_ieee (*str, 'x', words)) != NULL | |
4591 | && is_end_of_line[(unsigned char) *save_in]) | |
4592 | { | |
4593 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4594 | { | |
4595 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
b99bd4ef | 4596 | { |
c19d1205 ZW |
4597 | if (words[j] != fp_values[i][j]) |
4598 | break; | |
b99bd4ef NC |
4599 | } |
4600 | ||
c19d1205 | 4601 | if (j == MAX_LITTLENUMS) |
b99bd4ef | 4602 | { |
c19d1205 ZW |
4603 | *str = save_in; |
4604 | return i + 8; | |
b99bd4ef NC |
4605 | } |
4606 | } | |
4607 | } | |
b99bd4ef | 4608 | |
c19d1205 ZW |
4609 | /* Try and parse a more complex expression, this will probably fail |
4610 | unless the code uses a floating point prefix (eg "0f"). */ | |
4611 | save_in = input_line_pointer; | |
4612 | input_line_pointer = *str; | |
4613 | if (expression (&exp) == absolute_section | |
4614 | && exp.X_op == O_big | |
4615 | && exp.X_add_number < 0) | |
4616 | { | |
4617 | /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. | |
4618 | Ditto for 15. */ | |
4619 | if (gen_to_words (words, 5, (long) 15) == 0) | |
4620 | { | |
4621 | for (i = 0; i < NUM_FLOAT_VALS; i++) | |
4622 | { | |
4623 | for (j = 0; j < MAX_LITTLENUMS; j++) | |
4624 | { | |
4625 | if (words[j] != fp_values[i][j]) | |
4626 | break; | |
4627 | } | |
b99bd4ef | 4628 | |
c19d1205 ZW |
4629 | if (j == MAX_LITTLENUMS) |
4630 | { | |
4631 | *str = input_line_pointer; | |
4632 | input_line_pointer = save_in; | |
4633 | return i + 8; | |
4634 | } | |
4635 | } | |
4636 | } | |
b99bd4ef NC |
4637 | } |
4638 | ||
c19d1205 ZW |
4639 | *str = input_line_pointer; |
4640 | input_line_pointer = save_in; | |
4641 | inst.error = _("invalid FPA immediate expression"); | |
4642 | return FAIL; | |
b99bd4ef NC |
4643 | } |
4644 | ||
136da414 JB |
4645 | /* Returns 1 if a number has "quarter-precision" float format |
4646 | 0baBbbbbbc defgh000 00000000 00000000. */ | |
4647 | ||
4648 | static int | |
4649 | is_quarter_float (unsigned imm) | |
4650 | { | |
4651 | int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; | |
4652 | return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; | |
4653 | } | |
4654 | ||
4655 | /* Parse an 8-bit "quarter-precision" floating point number of the form: | |
4656 | 0baBbbbbbc defgh000 00000000 00000000. | |
c96612cc JB |
4657 | The zero and minus-zero cases need special handling, since they can't be |
4658 | encoded in the "quarter-precision" float format, but can nonetheless be | |
4659 | loaded as integer constants. */ | |
136da414 JB |
4660 | |
4661 | static unsigned | |
4662 | parse_qfloat_immediate (char **ccp, int *immed) | |
4663 | { | |
4664 | char *str = *ccp; | |
c96612cc | 4665 | char *fpnum; |
136da414 | 4666 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
c96612cc | 4667 | int found_fpchar = 0; |
5f4273c7 | 4668 | |
136da414 | 4669 | skip_past_char (&str, '#'); |
5f4273c7 | 4670 | |
c96612cc JB |
4671 | /* We must not accidentally parse an integer as a floating-point number. Make |
4672 | sure that the value we parse is not an integer by checking for special | |
4673 | characters '.' or 'e'. | |
4674 | FIXME: This is a horrible hack, but doing better is tricky because type | |
4675 | information isn't in a very usable state at parse time. */ | |
4676 | fpnum = str; | |
4677 | skip_whitespace (fpnum); | |
4678 | ||
4679 | if (strncmp (fpnum, "0x", 2) == 0) | |
4680 | return FAIL; | |
4681 | else | |
4682 | { | |
4683 | for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) | |
4684 | if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') | |
4685 | { | |
4686 | found_fpchar = 1; | |
4687 | break; | |
4688 | } | |
4689 | ||
4690 | if (!found_fpchar) | |
4691 | return FAIL; | |
4692 | } | |
5f4273c7 | 4693 | |
136da414 JB |
4694 | if ((str = atof_ieee (str, 's', words)) != NULL) |
4695 | { | |
4696 | unsigned fpword = 0; | |
4697 | int i; | |
5f4273c7 | 4698 | |
136da414 JB |
4699 | /* Our FP word must be 32 bits (single-precision FP). */ |
4700 | for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) | |
4701 | { | |
4702 | fpword <<= LITTLENUM_NUMBER_OF_BITS; | |
4703 | fpword |= words[i]; | |
4704 | } | |
5f4273c7 | 4705 | |
c96612cc | 4706 | if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) |
136da414 JB |
4707 | *immed = fpword; |
4708 | else | |
4709 | return FAIL; | |
4710 | ||
4711 | *ccp = str; | |
5f4273c7 | 4712 | |
136da414 JB |
4713 | return SUCCESS; |
4714 | } | |
5f4273c7 | 4715 | |
136da414 JB |
4716 | return FAIL; |
4717 | } | |
4718 | ||
c19d1205 ZW |
4719 | /* Shift operands. */ |
4720 | enum shift_kind | |
b99bd4ef | 4721 | { |
c19d1205 ZW |
4722 | SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX |
4723 | }; | |
b99bd4ef | 4724 | |
c19d1205 ZW |
4725 | struct asm_shift_name |
4726 | { | |
4727 | const char *name; | |
4728 | enum shift_kind kind; | |
4729 | }; | |
b99bd4ef | 4730 | |
c19d1205 ZW |
4731 | /* Third argument to parse_shift. */ |
4732 | enum parse_shift_mode | |
4733 | { | |
4734 | NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ | |
4735 | SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ | |
4736 | SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ | |
4737 | SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ | |
4738 | SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ | |
4739 | }; | |
b99bd4ef | 4740 | |
c19d1205 ZW |
4741 | /* Parse a <shift> specifier on an ARM data processing instruction. |
4742 | This has three forms: | |
b99bd4ef | 4743 | |
c19d1205 ZW |
4744 | (LSL|LSR|ASL|ASR|ROR) Rs |
4745 | (LSL|LSR|ASL|ASR|ROR) #imm | |
4746 | RRX | |
b99bd4ef | 4747 | |
c19d1205 ZW |
4748 | Note that ASL is assimilated to LSL in the instruction encoding, and |
4749 | RRX to ROR #0 (which cannot be written as such). */ | |
b99bd4ef | 4750 | |
c19d1205 ZW |
4751 | static int |
4752 | parse_shift (char **str, int i, enum parse_shift_mode mode) | |
b99bd4ef | 4753 | { |
c19d1205 ZW |
4754 | const struct asm_shift_name *shift_name; |
4755 | enum shift_kind shift; | |
4756 | char *s = *str; | |
4757 | char *p = s; | |
4758 | int reg; | |
b99bd4ef | 4759 | |
c19d1205 ZW |
4760 | for (p = *str; ISALPHA (*p); p++) |
4761 | ; | |
b99bd4ef | 4762 | |
c19d1205 | 4763 | if (p == *str) |
b99bd4ef | 4764 | { |
c19d1205 ZW |
4765 | inst.error = _("shift expression expected"); |
4766 | return FAIL; | |
b99bd4ef NC |
4767 | } |
4768 | ||
21d799b5 NC |
4769 | shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str, |
4770 | p - *str); | |
c19d1205 ZW |
4771 | |
4772 | if (shift_name == NULL) | |
b99bd4ef | 4773 | { |
c19d1205 ZW |
4774 | inst.error = _("shift expression expected"); |
4775 | return FAIL; | |
b99bd4ef NC |
4776 | } |
4777 | ||
c19d1205 | 4778 | shift = shift_name->kind; |
b99bd4ef | 4779 | |
c19d1205 ZW |
4780 | switch (mode) |
4781 | { | |
4782 | case NO_SHIFT_RESTRICT: | |
4783 | case SHIFT_IMMEDIATE: break; | |
b99bd4ef | 4784 | |
c19d1205 ZW |
4785 | case SHIFT_LSL_OR_ASR_IMMEDIATE: |
4786 | if (shift != SHIFT_LSL && shift != SHIFT_ASR) | |
4787 | { | |
4788 | inst.error = _("'LSL' or 'ASR' required"); | |
4789 | return FAIL; | |
4790 | } | |
4791 | break; | |
b99bd4ef | 4792 | |
c19d1205 ZW |
4793 | case SHIFT_LSL_IMMEDIATE: |
4794 | if (shift != SHIFT_LSL) | |
4795 | { | |
4796 | inst.error = _("'LSL' required"); | |
4797 | return FAIL; | |
4798 | } | |
4799 | break; | |
b99bd4ef | 4800 | |
c19d1205 ZW |
4801 | case SHIFT_ASR_IMMEDIATE: |
4802 | if (shift != SHIFT_ASR) | |
4803 | { | |
4804 | inst.error = _("'ASR' required"); | |
4805 | return FAIL; | |
4806 | } | |
4807 | break; | |
b99bd4ef | 4808 | |
c19d1205 ZW |
4809 | default: abort (); |
4810 | } | |
b99bd4ef | 4811 | |
c19d1205 ZW |
4812 | if (shift != SHIFT_RRX) |
4813 | { | |
4814 | /* Whitespace can appear here if the next thing is a bare digit. */ | |
4815 | skip_whitespace (p); | |
b99bd4ef | 4816 | |
c19d1205 | 4817 | if (mode == NO_SHIFT_RESTRICT |
dcbf9037 | 4818 | && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4819 | { |
4820 | inst.operands[i].imm = reg; | |
4821 | inst.operands[i].immisreg = 1; | |
4822 | } | |
4823 | else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4824 | return FAIL; | |
4825 | } | |
4826 | inst.operands[i].shift_kind = shift; | |
4827 | inst.operands[i].shifted = 1; | |
4828 | *str = p; | |
4829 | return SUCCESS; | |
b99bd4ef NC |
4830 | } |
4831 | ||
c19d1205 | 4832 | /* Parse a <shifter_operand> for an ARM data processing instruction: |
b99bd4ef | 4833 | |
c19d1205 ZW |
4834 | #<immediate> |
4835 | #<immediate>, <rotate> | |
4836 | <Rm> | |
4837 | <Rm>, <shift> | |
b99bd4ef | 4838 | |
c19d1205 ZW |
4839 | where <shift> is defined by parse_shift above, and <rotate> is a |
4840 | multiple of 2 between 0 and 30. Validation of immediate operands | |
55cf6793 | 4841 | is deferred to md_apply_fix. */ |
b99bd4ef | 4842 | |
c19d1205 ZW |
4843 | static int |
4844 | parse_shifter_operand (char **str, int i) | |
4845 | { | |
4846 | int value; | |
91d6fa6a | 4847 | expressionS exp; |
b99bd4ef | 4848 | |
dcbf9037 | 4849 | if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) |
c19d1205 ZW |
4850 | { |
4851 | inst.operands[i].reg = value; | |
4852 | inst.operands[i].isreg = 1; | |
b99bd4ef | 4853 | |
c19d1205 ZW |
4854 | /* parse_shift will override this if appropriate */ |
4855 | inst.reloc.exp.X_op = O_constant; | |
4856 | inst.reloc.exp.X_add_number = 0; | |
b99bd4ef | 4857 | |
c19d1205 ZW |
4858 | if (skip_past_comma (str) == FAIL) |
4859 | return SUCCESS; | |
b99bd4ef | 4860 | |
c19d1205 ZW |
4861 | /* Shift operation on register. */ |
4862 | return parse_shift (str, i, NO_SHIFT_RESTRICT); | |
b99bd4ef NC |
4863 | } |
4864 | ||
c19d1205 ZW |
4865 | if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) |
4866 | return FAIL; | |
b99bd4ef | 4867 | |
c19d1205 | 4868 | if (skip_past_comma (str) == SUCCESS) |
b99bd4ef | 4869 | { |
c19d1205 | 4870 | /* #x, y -- ie explicit rotation by Y. */ |
91d6fa6a | 4871 | if (my_get_expression (&exp, str, GE_NO_PREFIX)) |
c19d1205 | 4872 | return FAIL; |
b99bd4ef | 4873 | |
91d6fa6a | 4874 | if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant) |
c19d1205 ZW |
4875 | { |
4876 | inst.error = _("constant expression expected"); | |
4877 | return FAIL; | |
4878 | } | |
b99bd4ef | 4879 | |
91d6fa6a | 4880 | value = exp.X_add_number; |
c19d1205 ZW |
4881 | if (value < 0 || value > 30 || value % 2 != 0) |
4882 | { | |
4883 | inst.error = _("invalid rotation"); | |
4884 | return FAIL; | |
4885 | } | |
4886 | if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) | |
4887 | { | |
4888 | inst.error = _("invalid constant"); | |
4889 | return FAIL; | |
4890 | } | |
09d92015 | 4891 | |
a415b1cd JB |
4892 | /* Encode as specified. */ |
4893 | inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7; | |
4894 | return SUCCESS; | |
09d92015 MM |
4895 | } |
4896 | ||
c19d1205 ZW |
4897 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; |
4898 | inst.reloc.pc_rel = 0; | |
4899 | return SUCCESS; | |
09d92015 MM |
4900 | } |
4901 | ||
4962c51a MS |
4902 | /* Group relocation information. Each entry in the table contains the |
4903 | textual name of the relocation as may appear in assembler source | |
4904 | and must end with a colon. | |
4905 | Along with this textual name are the relocation codes to be used if | |
4906 | the corresponding instruction is an ALU instruction (ADD or SUB only), | |
4907 | an LDR, an LDRS, or an LDC. */ | |
4908 | ||
4909 | struct group_reloc_table_entry | |
4910 | { | |
4911 | const char *name; | |
4912 | int alu_code; | |
4913 | int ldr_code; | |
4914 | int ldrs_code; | |
4915 | int ldc_code; | |
4916 | }; | |
4917 | ||
4918 | typedef enum | |
4919 | { | |
4920 | /* Varieties of non-ALU group relocation. */ | |
4921 | ||
4922 | GROUP_LDR, | |
4923 | GROUP_LDRS, | |
4924 | GROUP_LDC | |
4925 | } group_reloc_type; | |
4926 | ||
4927 | static struct group_reloc_table_entry group_reloc_table[] = | |
4928 | { /* Program counter relative: */ | |
4929 | { "pc_g0_nc", | |
4930 | BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ | |
4931 | 0, /* LDR */ | |
4932 | 0, /* LDRS */ | |
4933 | 0 }, /* LDC */ | |
4934 | { "pc_g0", | |
4935 | BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ | |
4936 | BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ | |
4937 | BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ | |
4938 | BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ | |
4939 | { "pc_g1_nc", | |
4940 | BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ | |
4941 | 0, /* LDR */ | |
4942 | 0, /* LDRS */ | |
4943 | 0 }, /* LDC */ | |
4944 | { "pc_g1", | |
4945 | BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ | |
4946 | BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ | |
4947 | BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ | |
4948 | BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ | |
4949 | { "pc_g2", | |
4950 | BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ | |
4951 | BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ | |
4952 | BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ | |
4953 | BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ | |
4954 | /* Section base relative */ | |
4955 | { "sb_g0_nc", | |
4956 | BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ | |
4957 | 0, /* LDR */ | |
4958 | 0, /* LDRS */ | |
4959 | 0 }, /* LDC */ | |
4960 | { "sb_g0", | |
4961 | BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ | |
4962 | BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ | |
4963 | BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ | |
4964 | BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ | |
4965 | { "sb_g1_nc", | |
4966 | BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ | |
4967 | 0, /* LDR */ | |
4968 | 0, /* LDRS */ | |
4969 | 0 }, /* LDC */ | |
4970 | { "sb_g1", | |
4971 | BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ | |
4972 | BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ | |
4973 | BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ | |
4974 | BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ | |
4975 | { "sb_g2", | |
4976 | BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ | |
4977 | BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ | |
4978 | BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ | |
4979 | BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ | |
4980 | ||
4981 | /* Given the address of a pointer pointing to the textual name of a group | |
4982 | relocation as may appear in assembler source, attempt to find its details | |
4983 | in group_reloc_table. The pointer will be updated to the character after | |
4984 | the trailing colon. On failure, FAIL will be returned; SUCCESS | |
4985 | otherwise. On success, *entry will be updated to point at the relevant | |
4986 | group_reloc_table entry. */ | |
4987 | ||
4988 | static int | |
4989 | find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) | |
4990 | { | |
4991 | unsigned int i; | |
4992 | for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) | |
4993 | { | |
4994 | int length = strlen (group_reloc_table[i].name); | |
4995 | ||
5f4273c7 NC |
4996 | if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 |
4997 | && (*str)[length] == ':') | |
4962c51a MS |
4998 | { |
4999 | *out = &group_reloc_table[i]; | |
5000 | *str += (length + 1); | |
5001 | return SUCCESS; | |
5002 | } | |
5003 | } | |
5004 | ||
5005 | return FAIL; | |
5006 | } | |
5007 | ||
5008 | /* Parse a <shifter_operand> for an ARM data processing instruction | |
5009 | (as for parse_shifter_operand) where group relocations are allowed: | |
5010 | ||
5011 | #<immediate> | |
5012 | #<immediate>, <rotate> | |
5013 | #:<group_reloc>:<expression> | |
5014 | <Rm> | |
5015 | <Rm>, <shift> | |
5016 | ||
5017 | where <group_reloc> is one of the strings defined in group_reloc_table. | |
5018 | The hashes are optional. | |
5019 | ||
5020 | Everything else is as for parse_shifter_operand. */ | |
5021 | ||
5022 | static parse_operand_result | |
5023 | parse_shifter_operand_group_reloc (char **str, int i) | |
5024 | { | |
5025 | /* Determine if we have the sequence of characters #: or just : | |
5026 | coming next. If we do, then we check for a group relocation. | |
5027 | If we don't, punt the whole lot to parse_shifter_operand. */ | |
5028 | ||
5029 | if (((*str)[0] == '#' && (*str)[1] == ':') | |
5030 | || (*str)[0] == ':') | |
5031 | { | |
5032 | struct group_reloc_table_entry *entry; | |
5033 | ||
5034 | if ((*str)[0] == '#') | |
5035 | (*str) += 2; | |
5036 | else | |
5037 | (*str)++; | |
5038 | ||
5039 | /* Try to parse a group relocation. Anything else is an error. */ | |
5040 | if (find_group_reloc_table_entry (str, &entry) == FAIL) | |
5041 | { | |
5042 | inst.error = _("unknown group relocation"); | |
5043 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5044 | } | |
5045 | ||
5046 | /* We now have the group relocation table entry corresponding to | |
5047 | the name in the assembler source. Next, we parse the expression. */ | |
5048 | if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) | |
5049 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5050 | ||
5051 | /* Record the relocation type (always the ALU variant here). */ | |
21d799b5 | 5052 | inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code; |
9c2799c2 | 5053 | gas_assert (inst.reloc.type != 0); |
4962c51a MS |
5054 | |
5055 | return PARSE_OPERAND_SUCCESS; | |
5056 | } | |
5057 | else | |
5058 | return parse_shifter_operand (str, i) == SUCCESS | |
5059 | ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; | |
5060 | ||
5061 | /* Never reached. */ | |
5062 | } | |
5063 | ||
8e560766 MGD |
5064 | /* Parse a Neon alignment expression. Information is written to |
5065 | inst.operands[i]. We assume the initial ':' has been skipped. | |
5066 | ||
5067 | align .imm = align << 8, .immisalign=1, .preind=0 */ | |
5068 | static parse_operand_result | |
5069 | parse_neon_alignment (char **str, int i) | |
5070 | { | |
5071 | char *p = *str; | |
5072 | expressionS exp; | |
5073 | ||
5074 | my_get_expression (&exp, &p, GE_NO_PREFIX); | |
5075 | ||
5076 | if (exp.X_op != O_constant) | |
5077 | { | |
5078 | inst.error = _("alignment must be constant"); | |
5079 | return PARSE_OPERAND_FAIL; | |
5080 | } | |
5081 | ||
5082 | inst.operands[i].imm = exp.X_add_number << 8; | |
5083 | inst.operands[i].immisalign = 1; | |
5084 | /* Alignments are not pre-indexes. */ | |
5085 | inst.operands[i].preind = 0; | |
5086 | ||
5087 | *str = p; | |
5088 | return PARSE_OPERAND_SUCCESS; | |
5089 | } | |
5090 | ||
c19d1205 ZW |
5091 | /* Parse all forms of an ARM address expression. Information is written |
5092 | to inst.operands[i] and/or inst.reloc. | |
09d92015 | 5093 | |
c19d1205 | 5094 | Preindexed addressing (.preind=1): |
09d92015 | 5095 | |
c19d1205 ZW |
5096 | [Rn, #offset] .reg=Rn .reloc.exp=offset |
5097 | [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5098 | [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5099 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5100 | |
c19d1205 | 5101 | These three may have a trailing ! which causes .writeback to be set also. |
09d92015 | 5102 | |
c19d1205 | 5103 | Postindexed addressing (.postind=1, .writeback=1): |
09d92015 | 5104 | |
c19d1205 ZW |
5105 | [Rn], #offset .reg=Rn .reloc.exp=offset |
5106 | [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5107 | [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 | |
5108 | .shift_kind=shift .reloc.exp=shift_imm | |
09d92015 | 5109 | |
c19d1205 | 5110 | Unindexed addressing (.preind=0, .postind=0): |
09d92015 | 5111 | |
c19d1205 | 5112 | [Rn], {option} .reg=Rn .imm=option .immisreg=0 |
09d92015 | 5113 | |
c19d1205 | 5114 | Other: |
09d92015 | 5115 | |
c19d1205 ZW |
5116 | [Rn]{!} shorthand for [Rn,#0]{!} |
5117 | =immediate .isreg=0 .reloc.exp=immediate | |
5118 | label .reg=PC .reloc.pc_rel=1 .reloc.exp=label | |
09d92015 | 5119 | |
c19d1205 ZW |
5120 | It is the caller's responsibility to check for addressing modes not |
5121 | supported by the instruction, and to set inst.reloc.type. */ | |
5122 | ||
4962c51a MS |
5123 | static parse_operand_result |
5124 | parse_address_main (char **str, int i, int group_relocations, | |
5125 | group_reloc_type group_type) | |
09d92015 | 5126 | { |
c19d1205 ZW |
5127 | char *p = *str; |
5128 | int reg; | |
09d92015 | 5129 | |
c19d1205 | 5130 | if (skip_past_char (&p, '[') == FAIL) |
09d92015 | 5131 | { |
c19d1205 ZW |
5132 | if (skip_past_char (&p, '=') == FAIL) |
5133 | { | |
974da60d | 5134 | /* Bare address - translate to PC-relative offset. */ |
c19d1205 ZW |
5135 | inst.reloc.pc_rel = 1; |
5136 | inst.operands[i].reg = REG_PC; | |
5137 | inst.operands[i].isreg = 1; | |
5138 | inst.operands[i].preind = 1; | |
5139 | } | |
974da60d | 5140 | /* Otherwise a load-constant pseudo op, no special treatment needed here. */ |
09d92015 | 5141 | |
c19d1205 | 5142 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) |
4962c51a | 5143 | return PARSE_OPERAND_FAIL; |
09d92015 | 5144 | |
c19d1205 | 5145 | *str = p; |
4962c51a | 5146 | return PARSE_OPERAND_SUCCESS; |
09d92015 MM |
5147 | } |
5148 | ||
dcbf9037 | 5149 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
09d92015 | 5150 | { |
c19d1205 | 5151 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
4962c51a | 5152 | return PARSE_OPERAND_FAIL; |
09d92015 | 5153 | } |
c19d1205 ZW |
5154 | inst.operands[i].reg = reg; |
5155 | inst.operands[i].isreg = 1; | |
09d92015 | 5156 | |
c19d1205 | 5157 | if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5158 | { |
c19d1205 | 5159 | inst.operands[i].preind = 1; |
09d92015 | 5160 | |
c19d1205 ZW |
5161 | if (*p == '+') p++; |
5162 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
5163 | ||
dcbf9037 | 5164 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
09d92015 | 5165 | { |
c19d1205 ZW |
5166 | inst.operands[i].imm = reg; |
5167 | inst.operands[i].immisreg = 1; | |
5168 | ||
5169 | if (skip_past_comma (&p) == SUCCESS) | |
5170 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5171 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5172 | } |
5287ad62 | 5173 | else if (skip_past_char (&p, ':') == SUCCESS) |
8e560766 MGD |
5174 | { |
5175 | /* FIXME: '@' should be used here, but it's filtered out by generic | |
5176 | code before we get to see it here. This may be subject to | |
5177 | change. */ | |
5178 | parse_operand_result result = parse_neon_alignment (&p, i); | |
5179 | ||
5180 | if (result != PARSE_OPERAND_SUCCESS) | |
5181 | return result; | |
5182 | } | |
c19d1205 ZW |
5183 | else |
5184 | { | |
5185 | if (inst.operands[i].negative) | |
5186 | { | |
5187 | inst.operands[i].negative = 0; | |
5188 | p--; | |
5189 | } | |
4962c51a | 5190 | |
5f4273c7 NC |
5191 | if (group_relocations |
5192 | && ((*p == '#' && *(p + 1) == ':') || *p == ':')) | |
4962c51a MS |
5193 | { |
5194 | struct group_reloc_table_entry *entry; | |
5195 | ||
5196 | /* Skip over the #: or : sequence. */ | |
5197 | if (*p == '#') | |
5198 | p += 2; | |
5199 | else | |
5200 | p++; | |
5201 | ||
5202 | /* Try to parse a group relocation. Anything else is an | |
5203 | error. */ | |
5204 | if (find_group_reloc_table_entry (&p, &entry) == FAIL) | |
5205 | { | |
5206 | inst.error = _("unknown group relocation"); | |
5207 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5208 | } | |
5209 | ||
5210 | /* We now have the group relocation table entry corresponding to | |
5211 | the name in the assembler source. Next, we parse the | |
5212 | expression. */ | |
5213 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5214 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5215 | ||
5216 | /* Record the relocation type. */ | |
5217 | switch (group_type) | |
5218 | { | |
5219 | case GROUP_LDR: | |
21d799b5 | 5220 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code; |
4962c51a MS |
5221 | break; |
5222 | ||
5223 | case GROUP_LDRS: | |
21d799b5 | 5224 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code; |
4962c51a MS |
5225 | break; |
5226 | ||
5227 | case GROUP_LDC: | |
21d799b5 | 5228 | inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code; |
4962c51a MS |
5229 | break; |
5230 | ||
5231 | default: | |
9c2799c2 | 5232 | gas_assert (0); |
4962c51a MS |
5233 | } |
5234 | ||
5235 | if (inst.reloc.type == 0) | |
5236 | { | |
5237 | inst.error = _("this group relocation is not allowed on this instruction"); | |
5238 | return PARSE_OPERAND_FAIL_NO_BACKTRACK; | |
5239 | } | |
5240 | } | |
5241 | else | |
26d97720 NS |
5242 | { |
5243 | char *q = p; | |
5244 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
5245 | return PARSE_OPERAND_FAIL; | |
5246 | /* If the offset is 0, find out if it's a +0 or -0. */ | |
5247 | if (inst.reloc.exp.X_op == O_constant | |
5248 | && inst.reloc.exp.X_add_number == 0) | |
5249 | { | |
5250 | skip_whitespace (q); | |
5251 | if (*q == '#') | |
5252 | { | |
5253 | q++; | |
5254 | skip_whitespace (q); | |
5255 | } | |
5256 | if (*q == '-') | |
5257 | inst.operands[i].negative = 1; | |
5258 | } | |
5259 | } | |
09d92015 MM |
5260 | } |
5261 | } | |
8e560766 MGD |
5262 | else if (skip_past_char (&p, ':') == SUCCESS) |
5263 | { | |
5264 | /* FIXME: '@' should be used here, but it's filtered out by generic code | |
5265 | before we get to see it here. This may be subject to change. */ | |
5266 | parse_operand_result result = parse_neon_alignment (&p, i); | |
5267 | ||
5268 | if (result != PARSE_OPERAND_SUCCESS) | |
5269 | return result; | |
5270 | } | |
09d92015 | 5271 | |
c19d1205 | 5272 | if (skip_past_char (&p, ']') == FAIL) |
09d92015 | 5273 | { |
c19d1205 | 5274 | inst.error = _("']' expected"); |
4962c51a | 5275 | return PARSE_OPERAND_FAIL; |
09d92015 MM |
5276 | } |
5277 | ||
c19d1205 ZW |
5278 | if (skip_past_char (&p, '!') == SUCCESS) |
5279 | inst.operands[i].writeback = 1; | |
09d92015 | 5280 | |
c19d1205 | 5281 | else if (skip_past_comma (&p) == SUCCESS) |
09d92015 | 5282 | { |
c19d1205 ZW |
5283 | if (skip_past_char (&p, '{') == SUCCESS) |
5284 | { | |
5285 | /* [Rn], {expr} - unindexed, with option */ | |
5286 | if (parse_immediate (&p, &inst.operands[i].imm, | |
ca3f61f7 | 5287 | 0, 255, TRUE) == FAIL) |
4962c51a | 5288 | return PARSE_OPERAND_FAIL; |
09d92015 | 5289 | |
c19d1205 ZW |
5290 | if (skip_past_char (&p, '}') == FAIL) |
5291 | { | |
5292 | inst.error = _("'}' expected at end of 'option' field"); | |
4962c51a | 5293 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5294 | } |
5295 | if (inst.operands[i].preind) | |
5296 | { | |
5297 | inst.error = _("cannot combine index with option"); | |
4962c51a | 5298 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5299 | } |
5300 | *str = p; | |
4962c51a | 5301 | return PARSE_OPERAND_SUCCESS; |
09d92015 | 5302 | } |
c19d1205 ZW |
5303 | else |
5304 | { | |
5305 | inst.operands[i].postind = 1; | |
5306 | inst.operands[i].writeback = 1; | |
09d92015 | 5307 | |
c19d1205 ZW |
5308 | if (inst.operands[i].preind) |
5309 | { | |
5310 | inst.error = _("cannot combine pre- and post-indexing"); | |
4962c51a | 5311 | return PARSE_OPERAND_FAIL; |
c19d1205 | 5312 | } |
09d92015 | 5313 | |
c19d1205 ZW |
5314 | if (*p == '+') p++; |
5315 | else if (*p == '-') p++, inst.operands[i].negative = 1; | |
a737bd4d | 5316 | |
dcbf9037 | 5317 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) |
c19d1205 | 5318 | { |
5287ad62 JB |
5319 | /* We might be using the immediate for alignment already. If we |
5320 | are, OR the register number into the low-order bits. */ | |
5321 | if (inst.operands[i].immisalign) | |
5322 | inst.operands[i].imm |= reg; | |
5323 | else | |
5324 | inst.operands[i].imm = reg; | |
c19d1205 | 5325 | inst.operands[i].immisreg = 1; |
a737bd4d | 5326 | |
c19d1205 ZW |
5327 | if (skip_past_comma (&p) == SUCCESS) |
5328 | if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) | |
4962c51a | 5329 | return PARSE_OPERAND_FAIL; |
c19d1205 ZW |
5330 | } |
5331 | else | |
5332 | { | |
26d97720 | 5333 | char *q = p; |
c19d1205 ZW |
5334 | if (inst.operands[i].negative) |
5335 | { | |
5336 | inst.operands[i].negative = 0; | |
5337 | p--; | |
5338 | } | |
5339 | if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) | |
4962c51a | 5340 | return PARSE_OPERAND_FAIL; |
26d97720 NS |
5341 | /* If the offset is 0, find out if it's a +0 or -0. */ |
5342 | if (inst.reloc.exp.X_op == O_constant | |
5343 | && inst.reloc.exp.X_add_number == 0) | |
5344 | { | |
5345 | skip_whitespace (q); | |
5346 | if (*q == '#') | |
5347 | { | |
5348 | q++; | |
5349 | skip_whitespace (q); | |
5350 | } | |
5351 | if (*q == '-') | |
5352 | inst.operands[i].negative = 1; | |
5353 | } | |
c19d1205 ZW |
5354 | } |
5355 | } | |
a737bd4d NC |
5356 | } |
5357 | ||
c19d1205 ZW |
5358 | /* If at this point neither .preind nor .postind is set, we have a |
5359 | bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ | |
5360 | if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) | |
5361 | { | |
5362 | inst.operands[i].preind = 1; | |
5363 | inst.reloc.exp.X_op = O_constant; | |
5364 | inst.reloc.exp.X_add_number = 0; | |
5365 | } | |
5366 | *str = p; | |
4962c51a MS |
5367 | return PARSE_OPERAND_SUCCESS; |
5368 | } | |
5369 | ||
5370 | static int | |
5371 | parse_address (char **str, int i) | |
5372 | { | |
21d799b5 | 5373 | return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS |
4962c51a MS |
5374 | ? SUCCESS : FAIL; |
5375 | } | |
5376 | ||
5377 | static parse_operand_result | |
5378 | parse_address_group_reloc (char **str, int i, group_reloc_type type) | |
5379 | { | |
5380 | return parse_address_main (str, i, 1, type); | |
a737bd4d NC |
5381 | } |
5382 | ||
b6895b4f PB |
5383 | /* Parse an operand for a MOVW or MOVT instruction. */ |
5384 | static int | |
5385 | parse_half (char **str) | |
5386 | { | |
5387 | char * p; | |
5f4273c7 | 5388 | |
b6895b4f PB |
5389 | p = *str; |
5390 | skip_past_char (&p, '#'); | |
5f4273c7 | 5391 | if (strncasecmp (p, ":lower16:", 9) == 0) |
b6895b4f PB |
5392 | inst.reloc.type = BFD_RELOC_ARM_MOVW; |
5393 | else if (strncasecmp (p, ":upper16:", 9) == 0) | |
5394 | inst.reloc.type = BFD_RELOC_ARM_MOVT; | |
5395 | ||
5396 | if (inst.reloc.type != BFD_RELOC_UNUSED) | |
5397 | { | |
5398 | p += 9; | |
5f4273c7 | 5399 | skip_whitespace (p); |
b6895b4f PB |
5400 | } |
5401 | ||
5402 | if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) | |
5403 | return FAIL; | |
5404 | ||
5405 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
5406 | { | |
5407 | if (inst.reloc.exp.X_op != O_constant) | |
5408 | { | |
5409 | inst.error = _("constant expression expected"); | |
5410 | return FAIL; | |
5411 | } | |
5412 | if (inst.reloc.exp.X_add_number < 0 | |
5413 | || inst.reloc.exp.X_add_number > 0xffff) | |
5414 | { | |
5415 | inst.error = _("immediate value out of range"); | |
5416 | return FAIL; | |
5417 | } | |
5418 | } | |
5419 | *str = p; | |
5420 | return SUCCESS; | |
5421 | } | |
5422 | ||
c19d1205 | 5423 | /* Miscellaneous. */ |
a737bd4d | 5424 | |
c19d1205 ZW |
5425 | /* Parse a PSR flag operand. The value returned is FAIL on syntax error, |
5426 | or a bitmask suitable to be or-ed into the ARM msr instruction. */ | |
5427 | static int | |
d2cd1205 | 5428 | parse_psr (char **str, bfd_boolean lhs) |
09d92015 | 5429 | { |
c19d1205 ZW |
5430 | char *p; |
5431 | unsigned long psr_field; | |
62b3e311 PB |
5432 | const struct asm_psr *psr; |
5433 | char *start; | |
d2cd1205 | 5434 | bfd_boolean is_apsr = FALSE; |
ac7f631b | 5435 | bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m); |
09d92015 | 5436 | |
a4482bb6 NC |
5437 | /* PR gas/12698: If the user has specified -march=all then m_profile will |
5438 | be TRUE, but we want to ignore it in this case as we are building for any | |
5439 | CPU type, including non-m variants. */ | |
5440 | if (selected_cpu.core == arm_arch_any.core) | |
5441 | m_profile = FALSE; | |
5442 | ||
c19d1205 ZW |
5443 | /* CPSR's and SPSR's can now be lowercase. This is just a convenience |
5444 | feature for ease of use and backwards compatibility. */ | |
5445 | p = *str; | |
62b3e311 | 5446 | if (strncasecmp (p, "SPSR", 4) == 0) |
d2cd1205 JB |
5447 | { |
5448 | if (m_profile) | |
5449 | goto unsupported_psr; | |
5450 | ||
5451 | psr_field = SPSR_BIT; | |
5452 | } | |
5453 | else if (strncasecmp (p, "CPSR", 4) == 0) | |
5454 | { | |
5455 | if (m_profile) | |
5456 | goto unsupported_psr; | |
5457 | ||
5458 | psr_field = 0; | |
5459 | } | |
5460 | else if (strncasecmp (p, "APSR", 4) == 0) | |
5461 | { | |
5462 | /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A | |
5463 | and ARMv7-R architecture CPUs. */ | |
5464 | is_apsr = TRUE; | |
5465 | psr_field = 0; | |
5466 | } | |
5467 | else if (m_profile) | |
62b3e311 PB |
5468 | { |
5469 | start = p; | |
5470 | do | |
5471 | p++; | |
5472 | while (ISALNUM (*p) || *p == '_'); | |
5473 | ||
d2cd1205 JB |
5474 | if (strncasecmp (start, "iapsr", 5) == 0 |
5475 | || strncasecmp (start, "eapsr", 5) == 0 | |
5476 | || strncasecmp (start, "xpsr", 4) == 0 | |
5477 | || strncasecmp (start, "psr", 3) == 0) | |
5478 | p = start + strcspn (start, "rR") + 1; | |
5479 | ||
21d799b5 NC |
5480 | psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start, |
5481 | p - start); | |
d2cd1205 | 5482 | |
62b3e311 PB |
5483 | if (!psr) |
5484 | return FAIL; | |
09d92015 | 5485 | |
d2cd1205 JB |
5486 | /* If APSR is being written, a bitfield may be specified. Note that |
5487 | APSR itself is handled above. */ | |
5488 | if (psr->field <= 3) | |
5489 | { | |
5490 | psr_field = psr->field; | |
5491 | is_apsr = TRUE; | |
5492 | goto check_suffix; | |
5493 | } | |
5494 | ||
62b3e311 | 5495 | *str = p; |
d2cd1205 JB |
5496 | /* M-profile MSR instructions have the mask field set to "10", except |
5497 | *PSR variants which modify APSR, which may use a different mask (and | |
5498 | have been handled already). Do that by setting the PSR_f field | |
5499 | here. */ | |
5500 | return psr->field | (lhs ? PSR_f : 0); | |
62b3e311 | 5501 | } |
d2cd1205 JB |
5502 | else |
5503 | goto unsupported_psr; | |
09d92015 | 5504 | |
62b3e311 | 5505 | p += 4; |
d2cd1205 | 5506 | check_suffix: |
c19d1205 ZW |
5507 | if (*p == '_') |
5508 | { | |
5509 | /* A suffix follows. */ | |
c19d1205 ZW |
5510 | p++; |
5511 | start = p; | |
a737bd4d | 5512 | |
c19d1205 ZW |
5513 | do |
5514 | p++; | |
5515 | while (ISALNUM (*p) || *p == '_'); | |
a737bd4d | 5516 | |
d2cd1205 JB |
5517 | if (is_apsr) |
5518 | { | |
5519 | /* APSR uses a notation for bits, rather than fields. */ | |
5520 | unsigned int nzcvq_bits = 0; | |
5521 | unsigned int g_bit = 0; | |
5522 | char *bit; | |
5523 | ||
5524 | for (bit = start; bit != p; bit++) | |
5525 | { | |
5526 | switch (TOLOWER (*bit)) | |
5527 | { | |
5528 | case 'n': | |
5529 | nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01; | |
5530 | break; | |
5531 | ||
5532 | case 'z': | |
5533 | nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02; | |
5534 | break; | |
5535 | ||
5536 | case 'c': | |
5537 | nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04; | |
5538 | break; | |
5539 | ||
5540 | case 'v': | |
5541 | nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08; | |
5542 | break; | |
5543 | ||
5544 | case 'q': | |
5545 | nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10; | |
5546 | break; | |
5547 | ||
5548 | case 'g': | |
5549 | g_bit |= (g_bit & 0x1) ? 0x2 : 0x1; | |
5550 | break; | |
5551 | ||
5552 | default: | |
5553 | inst.error = _("unexpected bit specified after APSR"); | |
5554 | return FAIL; | |
5555 | } | |
5556 | } | |
5557 | ||
5558 | if (nzcvq_bits == 0x1f) | |
5559 | psr_field |= PSR_f; | |
5560 | ||
5561 | if (g_bit == 0x1) | |
5562 | { | |
5563 | if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)) | |
5564 | { | |
5565 | inst.error = _("selected processor does not " | |
5566 | "support DSP extension"); | |
5567 | return FAIL; | |
5568 | } | |
5569 | ||
5570 | psr_field |= PSR_s; | |
5571 | } | |
5572 | ||
5573 | if ((nzcvq_bits & 0x20) != 0 | |
5574 | || (nzcvq_bits != 0x1f && nzcvq_bits != 0) | |
5575 | || (g_bit & 0x2) != 0) | |
5576 | { | |
5577 | inst.error = _("bad bitmask specified after APSR"); | |
5578 | return FAIL; | |
5579 | } | |
5580 | } | |
5581 | else | |
5582 | { | |
5583 | psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start, | |
5584 | p - start); | |
5585 | if (!psr) | |
5586 | goto error; | |
a737bd4d | 5587 | |
d2cd1205 JB |
5588 | psr_field |= psr->field; |
5589 | } | |
a737bd4d | 5590 | } |
c19d1205 | 5591 | else |
a737bd4d | 5592 | { |
c19d1205 ZW |
5593 | if (ISALNUM (*p)) |
5594 | goto error; /* Garbage after "[CS]PSR". */ | |
5595 | ||
d2cd1205 JB |
5596 | /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This |
5597 | is deprecated, but allow it anyway. */ | |
5598 | if (is_apsr && lhs) | |
5599 | { | |
5600 | psr_field |= PSR_f; | |
5601 | as_tsktsk (_("writing to APSR without specifying a bitmask is " | |
5602 | "deprecated")); | |
5603 | } | |
5604 | else if (!m_profile) | |
5605 | /* These bits are never right for M-profile devices: don't set them | |
5606 | (only code paths which read/write APSR reach here). */ | |
5607 | psr_field |= (PSR_c | PSR_f); | |
a737bd4d | 5608 | } |
c19d1205 ZW |
5609 | *str = p; |
5610 | return psr_field; | |
a737bd4d | 5611 | |
d2cd1205 JB |
5612 | unsupported_psr: |
5613 | inst.error = _("selected processor does not support requested special " | |
5614 | "purpose register"); | |
5615 | return FAIL; | |
5616 | ||
c19d1205 ZW |
5617 | error: |
5618 | inst.error = _("flag for {c}psr instruction expected"); | |
5619 | return FAIL; | |
a737bd4d NC |
5620 | } |
5621 | ||
c19d1205 ZW |
5622 | /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a |
5623 | value suitable for splatting into the AIF field of the instruction. */ | |
a737bd4d | 5624 | |
c19d1205 ZW |
5625 | static int |
5626 | parse_cps_flags (char **str) | |
a737bd4d | 5627 | { |
c19d1205 ZW |
5628 | int val = 0; |
5629 | int saw_a_flag = 0; | |
5630 | char *s = *str; | |
a737bd4d | 5631 | |
c19d1205 ZW |
5632 | for (;;) |
5633 | switch (*s++) | |
5634 | { | |
5635 | case '\0': case ',': | |
5636 | goto done; | |
a737bd4d | 5637 | |
c19d1205 ZW |
5638 | case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; |
5639 | case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; | |
5640 | case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; | |
a737bd4d | 5641 | |
c19d1205 ZW |
5642 | default: |
5643 | inst.error = _("unrecognized CPS flag"); | |
5644 | return FAIL; | |
5645 | } | |
a737bd4d | 5646 | |
c19d1205 ZW |
5647 | done: |
5648 | if (saw_a_flag == 0) | |
a737bd4d | 5649 | { |
c19d1205 ZW |
5650 | inst.error = _("missing CPS flags"); |
5651 | return FAIL; | |
a737bd4d | 5652 | } |
a737bd4d | 5653 | |
c19d1205 ZW |
5654 | *str = s - 1; |
5655 | return val; | |
a737bd4d NC |
5656 | } |
5657 | ||
c19d1205 ZW |
5658 | /* Parse an endian specifier ("BE" or "LE", case insensitive); |
5659 | returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ | |
a737bd4d NC |
5660 | |
5661 | static int | |
c19d1205 | 5662 | parse_endian_specifier (char **str) |
a737bd4d | 5663 | { |
c19d1205 ZW |
5664 | int little_endian; |
5665 | char *s = *str; | |
a737bd4d | 5666 | |
c19d1205 ZW |
5667 | if (strncasecmp (s, "BE", 2)) |
5668 | little_endian = 0; | |
5669 | else if (strncasecmp (s, "LE", 2)) | |
5670 | little_endian = 1; | |
5671 | else | |
a737bd4d | 5672 | { |
c19d1205 | 5673 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5674 | return FAIL; |
5675 | } | |
5676 | ||
c19d1205 | 5677 | if (ISALNUM (s[2]) || s[2] == '_') |
a737bd4d | 5678 | { |
c19d1205 | 5679 | inst.error = _("valid endian specifiers are be or le"); |
a737bd4d NC |
5680 | return FAIL; |
5681 | } | |
5682 | ||
c19d1205 ZW |
5683 | *str = s + 2; |
5684 | return little_endian; | |
5685 | } | |
a737bd4d | 5686 | |
c19d1205 ZW |
5687 | /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a |
5688 | value suitable for poking into the rotate field of an sxt or sxta | |
5689 | instruction, or FAIL on error. */ | |
5690 | ||
5691 | static int | |
5692 | parse_ror (char **str) | |
5693 | { | |
5694 | int rot; | |
5695 | char *s = *str; | |
5696 | ||
5697 | if (strncasecmp (s, "ROR", 3) == 0) | |
5698 | s += 3; | |
5699 | else | |
a737bd4d | 5700 | { |
c19d1205 | 5701 | inst.error = _("missing rotation field after comma"); |
a737bd4d NC |
5702 | return FAIL; |
5703 | } | |
c19d1205 ZW |
5704 | |
5705 | if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) | |
5706 | return FAIL; | |
5707 | ||
5708 | switch (rot) | |
a737bd4d | 5709 | { |
c19d1205 ZW |
5710 | case 0: *str = s; return 0x0; |
5711 | case 8: *str = s; return 0x1; | |
5712 | case 16: *str = s; return 0x2; | |
5713 | case 24: *str = s; return 0x3; | |
5714 | ||
5715 | default: | |
5716 | inst.error = _("rotation can only be 0, 8, 16, or 24"); | |
a737bd4d NC |
5717 | return FAIL; |
5718 | } | |
c19d1205 | 5719 | } |
a737bd4d | 5720 | |
c19d1205 ZW |
5721 | /* Parse a conditional code (from conds[] below). The value returned is in the |
5722 | range 0 .. 14, or FAIL. */ | |
5723 | static int | |
5724 | parse_cond (char **str) | |
5725 | { | |
c462b453 | 5726 | char *q; |
c19d1205 | 5727 | const struct asm_cond *c; |
c462b453 PB |
5728 | int n; |
5729 | /* Condition codes are always 2 characters, so matching up to | |
5730 | 3 characters is sufficient. */ | |
5731 | char cond[3]; | |
a737bd4d | 5732 | |
c462b453 PB |
5733 | q = *str; |
5734 | n = 0; | |
5735 | while (ISALPHA (*q) && n < 3) | |
5736 | { | |
e07e6e58 | 5737 | cond[n] = TOLOWER (*q); |
c462b453 PB |
5738 | q++; |
5739 | n++; | |
5740 | } | |
a737bd4d | 5741 | |
21d799b5 | 5742 | c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n); |
c19d1205 | 5743 | if (!c) |
a737bd4d | 5744 | { |
c19d1205 | 5745 | inst.error = _("condition required"); |
a737bd4d NC |
5746 | return FAIL; |
5747 | } | |
5748 | ||
c19d1205 ZW |
5749 | *str = q; |
5750 | return c->value; | |
5751 | } | |
5752 | ||
62b3e311 PB |
5753 | /* Parse an option for a barrier instruction. Returns the encoding for the |
5754 | option, or FAIL. */ | |
5755 | static int | |
5756 | parse_barrier (char **str) | |
5757 | { | |
5758 | char *p, *q; | |
5759 | const struct asm_barrier_opt *o; | |
5760 | ||
5761 | p = q = *str; | |
5762 | while (ISALPHA (*q)) | |
5763 | q++; | |
5764 | ||
21d799b5 NC |
5765 | o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p, |
5766 | q - p); | |
62b3e311 PB |
5767 | if (!o) |
5768 | return FAIL; | |
5769 | ||
5770 | *str = q; | |
5771 | return o->value; | |
5772 | } | |
5773 | ||
92e90b6e PB |
5774 | /* Parse the operands of a table branch instruction. Similar to a memory |
5775 | operand. */ | |
5776 | static int | |
5777 | parse_tb (char **str) | |
5778 | { | |
5779 | char * p = *str; | |
5780 | int reg; | |
5781 | ||
5782 | if (skip_past_char (&p, '[') == FAIL) | |
ab1eb5fe PB |
5783 | { |
5784 | inst.error = _("'[' expected"); | |
5785 | return FAIL; | |
5786 | } | |
92e90b6e | 5787 | |
dcbf9037 | 5788 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5789 | { |
5790 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5791 | return FAIL; | |
5792 | } | |
5793 | inst.operands[0].reg = reg; | |
5794 | ||
5795 | if (skip_past_comma (&p) == FAIL) | |
ab1eb5fe PB |
5796 | { |
5797 | inst.error = _("',' expected"); | |
5798 | return FAIL; | |
5799 | } | |
5f4273c7 | 5800 | |
dcbf9037 | 5801 | if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
92e90b6e PB |
5802 | { |
5803 | inst.error = _(reg_expected_msgs[REG_TYPE_RN]); | |
5804 | return FAIL; | |
5805 | } | |
5806 | inst.operands[0].imm = reg; | |
5807 | ||
5808 | if (skip_past_comma (&p) == SUCCESS) | |
5809 | { | |
5810 | if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) | |
5811 | return FAIL; | |
5812 | if (inst.reloc.exp.X_add_number != 1) | |
5813 | { | |
5814 | inst.error = _("invalid shift"); | |
5815 | return FAIL; | |
5816 | } | |
5817 | inst.operands[0].shifted = 1; | |
5818 | } | |
5819 | ||
5820 | if (skip_past_char (&p, ']') == FAIL) | |
5821 | { | |
5822 | inst.error = _("']' expected"); | |
5823 | return FAIL; | |
5824 | } | |
5825 | *str = p; | |
5826 | return SUCCESS; | |
5827 | } | |
5828 | ||
5287ad62 JB |
5829 | /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more |
5830 | information on the types the operands can take and how they are encoded. | |
037e8744 JB |
5831 | Up to four operands may be read; this function handles setting the |
5832 | ".present" field for each read operand itself. | |
5287ad62 JB |
5833 | Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, |
5834 | else returns FAIL. */ | |
5835 | ||
5836 | static int | |
5837 | parse_neon_mov (char **str, int *which_operand) | |
5838 | { | |
5839 | int i = *which_operand, val; | |
5840 | enum arm_reg_type rtype; | |
5841 | char *ptr = *str; | |
dcbf9037 | 5842 | struct neon_type_el optype; |
5f4273c7 | 5843 | |
dcbf9037 | 5844 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5845 | { |
5846 | /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ | |
5847 | inst.operands[i].reg = val; | |
5848 | inst.operands[i].isscalar = 1; | |
dcbf9037 | 5849 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5850 | inst.operands[i++].present = 1; |
5851 | ||
5852 | if (skip_past_comma (&ptr) == FAIL) | |
5853 | goto wanted_comma; | |
5f4273c7 | 5854 | |
dcbf9037 | 5855 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5287ad62 | 5856 | goto wanted_arm; |
5f4273c7 | 5857 | |
5287ad62 JB |
5858 | inst.operands[i].reg = val; |
5859 | inst.operands[i].isreg = 1; | |
5860 | inst.operands[i].present = 1; | |
5861 | } | |
037e8744 | 5862 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) |
dcbf9037 | 5863 | != FAIL) |
5287ad62 JB |
5864 | { |
5865 | /* Cases 0, 1, 2, 3, 5 (D only). */ | |
5866 | if (skip_past_comma (&ptr) == FAIL) | |
5867 | goto wanted_comma; | |
5f4273c7 | 5868 | |
5287ad62 JB |
5869 | inst.operands[i].reg = val; |
5870 | inst.operands[i].isreg = 1; | |
5871 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5872 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5873 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5874 | inst.operands[i].vectype = optype; |
5287ad62 JB |
5875 | inst.operands[i++].present = 1; |
5876 | ||
dcbf9037 | 5877 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 | 5878 | { |
037e8744 JB |
5879 | /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. |
5880 | Case 13: VMOV <Sd>, <Rm> */ | |
5287ad62 JB |
5881 | inst.operands[i].reg = val; |
5882 | inst.operands[i].isreg = 1; | |
037e8744 | 5883 | inst.operands[i].present = 1; |
5287ad62 JB |
5884 | |
5885 | if (rtype == REG_TYPE_NQ) | |
5886 | { | |
dcbf9037 | 5887 | first_error (_("can't use Neon quad register here")); |
5287ad62 JB |
5888 | return FAIL; |
5889 | } | |
037e8744 JB |
5890 | else if (rtype != REG_TYPE_VFS) |
5891 | { | |
5892 | i++; | |
5893 | if (skip_past_comma (&ptr) == FAIL) | |
5894 | goto wanted_comma; | |
5895 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5896 | goto wanted_arm; | |
5897 | inst.operands[i].reg = val; | |
5898 | inst.operands[i].isreg = 1; | |
5899 | inst.operands[i].present = 1; | |
5900 | } | |
5287ad62 | 5901 | } |
037e8744 JB |
5902 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, |
5903 | &optype)) != FAIL) | |
5287ad62 JB |
5904 | { |
5905 | /* Case 0: VMOV<c><q> <Qd>, <Qm> | |
037e8744 JB |
5906 | Case 1: VMOV<c><q> <Dd>, <Dm> |
5907 | Case 8: VMOV.F32 <Sd>, <Sm> | |
5908 | Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ | |
5287ad62 JB |
5909 | |
5910 | inst.operands[i].reg = val; | |
5911 | inst.operands[i].isreg = 1; | |
5912 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); | |
037e8744 JB |
5913 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); |
5914 | inst.operands[i].isvec = 1; | |
dcbf9037 | 5915 | inst.operands[i].vectype = optype; |
5287ad62 | 5916 | inst.operands[i].present = 1; |
5f4273c7 | 5917 | |
037e8744 JB |
5918 | if (skip_past_comma (&ptr) == SUCCESS) |
5919 | { | |
5920 | /* Case 15. */ | |
5921 | i++; | |
5922 | ||
5923 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) | |
5924 | goto wanted_arm; | |
5925 | ||
5926 | inst.operands[i].reg = val; | |
5927 | inst.operands[i].isreg = 1; | |
5928 | inst.operands[i++].present = 1; | |
5f4273c7 | 5929 | |
037e8744 JB |
5930 | if (skip_past_comma (&ptr) == FAIL) |
5931 | goto wanted_comma; | |
5f4273c7 | 5932 | |
037e8744 JB |
5933 | if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) |
5934 | goto wanted_arm; | |
5f4273c7 | 5935 | |
037e8744 JB |
5936 | inst.operands[i].reg = val; |
5937 | inst.operands[i].isreg = 1; | |
1b11b49f | 5938 | inst.operands[i].present = 1; |
037e8744 | 5939 | } |
5287ad62 | 5940 | } |
4641781c PB |
5941 | else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) |
5942 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> | |
5943 | Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> | |
5944 | Case 10: VMOV.F32 <Sd>, #<imm> | |
5945 | Case 11: VMOV.F64 <Dd>, #<imm> */ | |
5946 | inst.operands[i].immisfloat = 1; | |
5947 | else if (parse_big_immediate (&ptr, i) == SUCCESS) | |
5948 | /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> | |
5949 | Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ | |
5950 | ; | |
5287ad62 JB |
5951 | else |
5952 | { | |
dcbf9037 | 5953 | first_error (_("expected <Rm> or <Dm> or <Qm> operand")); |
5287ad62 JB |
5954 | return FAIL; |
5955 | } | |
5956 | } | |
dcbf9037 | 5957 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5958 | { |
5959 | /* Cases 6, 7. */ | |
5960 | inst.operands[i].reg = val; | |
5961 | inst.operands[i].isreg = 1; | |
5962 | inst.operands[i++].present = 1; | |
5f4273c7 | 5963 | |
5287ad62 JB |
5964 | if (skip_past_comma (&ptr) == FAIL) |
5965 | goto wanted_comma; | |
5f4273c7 | 5966 | |
dcbf9037 | 5967 | if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) |
5287ad62 JB |
5968 | { |
5969 | /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ | |
5970 | inst.operands[i].reg = val; | |
5971 | inst.operands[i].isscalar = 1; | |
5972 | inst.operands[i].present = 1; | |
dcbf9037 | 5973 | inst.operands[i].vectype = optype; |
5287ad62 | 5974 | } |
dcbf9037 | 5975 | else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) |
5287ad62 JB |
5976 | { |
5977 | /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ | |
5978 | inst.operands[i].reg = val; | |
5979 | inst.operands[i].isreg = 1; | |
5980 | inst.operands[i++].present = 1; | |
5f4273c7 | 5981 | |
5287ad62 JB |
5982 | if (skip_past_comma (&ptr) == FAIL) |
5983 | goto wanted_comma; | |
5f4273c7 | 5984 | |
037e8744 | 5985 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) |
dcbf9037 | 5986 | == FAIL) |
5287ad62 | 5987 | { |
037e8744 | 5988 | first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); |
5287ad62 JB |
5989 | return FAIL; |
5990 | } | |
5991 | ||
5992 | inst.operands[i].reg = val; | |
5993 | inst.operands[i].isreg = 1; | |
037e8744 JB |
5994 | inst.operands[i].isvec = 1; |
5995 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); | |
dcbf9037 | 5996 | inst.operands[i].vectype = optype; |
5287ad62 | 5997 | inst.operands[i].present = 1; |
5f4273c7 | 5998 | |
037e8744 JB |
5999 | if (rtype == REG_TYPE_VFS) |
6000 | { | |
6001 | /* Case 14. */ | |
6002 | i++; | |
6003 | if (skip_past_comma (&ptr) == FAIL) | |
6004 | goto wanted_comma; | |
6005 | if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, | |
6006 | &optype)) == FAIL) | |
6007 | { | |
6008 | first_error (_(reg_expected_msgs[REG_TYPE_VFS])); | |
6009 | return FAIL; | |
6010 | } | |
6011 | inst.operands[i].reg = val; | |
6012 | inst.operands[i].isreg = 1; | |
6013 | inst.operands[i].isvec = 1; | |
6014 | inst.operands[i].issingle = 1; | |
6015 | inst.operands[i].vectype = optype; | |
6016 | inst.operands[i].present = 1; | |
6017 | } | |
6018 | } | |
6019 | else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) | |
6020 | != FAIL) | |
6021 | { | |
6022 | /* Case 13. */ | |
6023 | inst.operands[i].reg = val; | |
6024 | inst.operands[i].isreg = 1; | |
6025 | inst.operands[i].isvec = 1; | |
6026 | inst.operands[i].issingle = 1; | |
6027 | inst.operands[i].vectype = optype; | |
1b11b49f | 6028 | inst.operands[i].present = 1; |
5287ad62 JB |
6029 | } |
6030 | } | |
6031 | else | |
6032 | { | |
dcbf9037 | 6033 | first_error (_("parse error")); |
5287ad62 JB |
6034 | return FAIL; |
6035 | } | |
6036 | ||
6037 | /* Successfully parsed the operands. Update args. */ | |
6038 | *which_operand = i; | |
6039 | *str = ptr; | |
6040 | return SUCCESS; | |
6041 | ||
5f4273c7 | 6042 | wanted_comma: |
dcbf9037 | 6043 | first_error (_("expected comma")); |
5287ad62 | 6044 | return FAIL; |
5f4273c7 NC |
6045 | |
6046 | wanted_arm: | |
dcbf9037 | 6047 | first_error (_(reg_expected_msgs[REG_TYPE_RN])); |
5287ad62 | 6048 | return FAIL; |
5287ad62 JB |
6049 | } |
6050 | ||
5be8be5d DG |
6051 | /* Use this macro when the operand constraints are different |
6052 | for ARM and THUMB (e.g. ldrd). */ | |
6053 | #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \ | |
6054 | ((arm_operand) | ((thumb_operand) << 16)) | |
6055 | ||
c19d1205 ZW |
6056 | /* Matcher codes for parse_operands. */ |
6057 | enum operand_parse_code | |
6058 | { | |
6059 | OP_stop, /* end of line */ | |
6060 | ||
6061 | OP_RR, /* ARM register */ | |
6062 | OP_RRnpc, /* ARM register, not r15 */ | |
5be8be5d | 6063 | OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */ |
c19d1205 | 6064 | OP_RRnpcb, /* ARM register, not r15, in square brackets */ |
55881a11 MGD |
6065 | OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback, |
6066 | optional trailing ! */ | |
c19d1205 ZW |
6067 | OP_RRw, /* ARM register, not r15, optional trailing ! */ |
6068 | OP_RCP, /* Coprocessor number */ | |
6069 | OP_RCN, /* Coprocessor register */ | |
6070 | OP_RF, /* FPA register */ | |
6071 | OP_RVS, /* VFP single precision register */ | |
5287ad62 JB |
6072 | OP_RVD, /* VFP double precision register (0..15) */ |
6073 | OP_RND, /* Neon double precision register (0..31) */ | |
6074 | OP_RNQ, /* Neon quad precision register */ | |
037e8744 | 6075 | OP_RVSD, /* VFP single or double precision register */ |
5287ad62 | 6076 | OP_RNDQ, /* Neon double or quad precision register */ |
037e8744 | 6077 | OP_RNSDQ, /* Neon single, double or quad precision register */ |
5287ad62 | 6078 | OP_RNSC, /* Neon scalar D[X] */ |
c19d1205 ZW |
6079 | OP_RVC, /* VFP control register */ |
6080 | OP_RMF, /* Maverick F register */ | |
6081 | OP_RMD, /* Maverick D register */ | |
6082 | OP_RMFX, /* Maverick FX register */ | |
6083 | OP_RMDX, /* Maverick DX register */ | |
6084 | OP_RMAX, /* Maverick AX register */ | |
6085 | OP_RMDS, /* Maverick DSPSC register */ | |
6086 | OP_RIWR, /* iWMMXt wR register */ | |
6087 | OP_RIWC, /* iWMMXt wC register */ | |
6088 | OP_RIWG, /* iWMMXt wCG register */ | |
6089 | OP_RXA, /* XScale accumulator register */ | |
6090 | ||
6091 | OP_REGLST, /* ARM register list */ | |
6092 | OP_VRSLST, /* VFP single-precision register list */ | |
6093 | OP_VRDLST, /* VFP double-precision register list */ | |
037e8744 | 6094 | OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ |
5287ad62 JB |
6095 | OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ |
6096 | OP_NSTRLST, /* Neon element/structure list */ | |
6097 | ||
5287ad62 | 6098 | OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ |
037e8744 | 6099 | OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ |
5287ad62 | 6100 | OP_RR_RNSC, /* ARM reg or Neon scalar. */ |
037e8744 | 6101 | OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ |
5287ad62 JB |
6102 | OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ |
6103 | OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ | |
6104 | OP_VMOV, /* Neon VMOV operands. */ | |
4316f0d2 | 6105 | OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */ |
5287ad62 | 6106 | OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ |
2d447fca | 6107 | OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ |
5287ad62 JB |
6108 | |
6109 | OP_I0, /* immediate zero */ | |
c19d1205 ZW |
6110 | OP_I7, /* immediate value 0 .. 7 */ |
6111 | OP_I15, /* 0 .. 15 */ | |
6112 | OP_I16, /* 1 .. 16 */ | |
5287ad62 | 6113 | OP_I16z, /* 0 .. 16 */ |
c19d1205 ZW |
6114 | OP_I31, /* 0 .. 31 */ |
6115 | OP_I31w, /* 0 .. 31, optional trailing ! */ | |
6116 | OP_I32, /* 1 .. 32 */ | |
5287ad62 JB |
6117 | OP_I32z, /* 0 .. 32 */ |
6118 | OP_I63, /* 0 .. 63 */ | |
c19d1205 | 6119 | OP_I63s, /* -64 .. 63 */ |
5287ad62 JB |
6120 | OP_I64, /* 1 .. 64 */ |
6121 | OP_I64z, /* 0 .. 64 */ | |
c19d1205 | 6122 | OP_I255, /* 0 .. 255 */ |
c19d1205 ZW |
6123 | |
6124 | OP_I4b, /* immediate, prefix optional, 1 .. 4 */ | |
6125 | OP_I7b, /* 0 .. 7 */ | |
6126 | OP_I15b, /* 0 .. 15 */ | |
6127 | OP_I31b, /* 0 .. 31 */ | |
6128 | ||
6129 | OP_SH, /* shifter operand */ | |
4962c51a | 6130 | OP_SHG, /* shifter operand with possible group relocation */ |
c19d1205 | 6131 | OP_ADDR, /* Memory address expression (any mode) */ |
4962c51a MS |
6132 | OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ |
6133 | OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ | |
6134 | OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ | |
c19d1205 ZW |
6135 | OP_EXP, /* arbitrary expression */ |
6136 | OP_EXPi, /* same, with optional immediate prefix */ | |
6137 | OP_EXPr, /* same, with optional relocation suffix */ | |
b6895b4f | 6138 | OP_HALF, /* 0 .. 65535 or low/high reloc. */ |
c19d1205 ZW |
6139 | |
6140 | OP_CPSF, /* CPS flags */ | |
6141 | OP_ENDI, /* Endianness specifier */ | |
d2cd1205 JB |
6142 | OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */ |
6143 | OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */ | |
c19d1205 | 6144 | OP_COND, /* conditional code */ |
92e90b6e | 6145 | OP_TB, /* Table branch. */ |
c19d1205 | 6146 | |
037e8744 JB |
6147 | OP_APSR_RR, /* ARM register or "APSR_nzcv". */ |
6148 | ||
c19d1205 ZW |
6149 | OP_RRnpc_I0, /* ARM register or literal 0 */ |
6150 | OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ | |
6151 | OP_RR_EXi, /* ARM register or expression with imm prefix */ | |
6152 | OP_RF_IF, /* FPA register or immediate */ | |
6153 | OP_RIWR_RIWC, /* iWMMXt R or C reg */ | |
41adaa5c | 6154 | OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ |
c19d1205 ZW |
6155 | |
6156 | /* Optional operands. */ | |
6157 | OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ | |
6158 | OP_oI31b, /* 0 .. 31 */ | |
5287ad62 | 6159 | OP_oI32b, /* 1 .. 32 */ |
5f1af56b | 6160 | OP_oI32z, /* 0 .. 32 */ |
c19d1205 ZW |
6161 | OP_oIffffb, /* 0 .. 65535 */ |
6162 | OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ | |
6163 | ||
6164 | OP_oRR, /* ARM register */ | |
6165 | OP_oRRnpc, /* ARM register, not the PC */ | |
5be8be5d | 6166 | OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */ |
b6702015 | 6167 | OP_oRRw, /* ARM register, not r15, optional trailing ! */ |
5287ad62 JB |
6168 | OP_oRND, /* Optional Neon double precision register */ |
6169 | OP_oRNQ, /* Optional Neon quad precision register */ | |
6170 | OP_oRNDQ, /* Optional Neon double or quad precision register */ | |
037e8744 | 6171 | OP_oRNSDQ, /* Optional single, double or quad precision vector register */ |
c19d1205 ZW |
6172 | OP_oSHll, /* LSL immediate */ |
6173 | OP_oSHar, /* ASR immediate */ | |
6174 | OP_oSHllar, /* LSL or ASR immediate */ | |
6175 | OP_oROR, /* ROR 0/8/16/24 */ | |
52e7f43d | 6176 | OP_oBARRIER_I15, /* Option argument for a barrier instruction. */ |
c19d1205 | 6177 | |
5be8be5d DG |
6178 | /* Some pre-defined mixed (ARM/THUMB) operands. */ |
6179 | OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp), | |
6180 | OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp), | |
6181 | OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp), | |
6182 | ||
c19d1205 ZW |
6183 | OP_FIRST_OPTIONAL = OP_oI7b |
6184 | }; | |
a737bd4d | 6185 | |
c19d1205 ZW |
6186 | /* Generic instruction operand parser. This does no encoding and no |
6187 | semantic validation; it merely squirrels values away in the inst | |
6188 | structure. Returns SUCCESS or FAIL depending on whether the | |
6189 | specified grammar matched. */ | |
6190 | static int | |
5be8be5d | 6191 | parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) |
c19d1205 | 6192 | { |
5be8be5d | 6193 | unsigned const int *upat = pattern; |
c19d1205 ZW |
6194 | char *backtrack_pos = 0; |
6195 | const char *backtrack_error = 0; | |
6196 | int i, val, backtrack_index = 0; | |
5287ad62 | 6197 | enum arm_reg_type rtype; |
4962c51a | 6198 | parse_operand_result result; |
5be8be5d | 6199 | unsigned int op_parse_code; |
c19d1205 | 6200 | |
e07e6e58 NC |
6201 | #define po_char_or_fail(chr) \ |
6202 | do \ | |
6203 | { \ | |
6204 | if (skip_past_char (&str, chr) == FAIL) \ | |
6205 | goto bad_args; \ | |
6206 | } \ | |
6207 | while (0) | |
c19d1205 | 6208 | |
e07e6e58 NC |
6209 | #define po_reg_or_fail(regtype) \ |
6210 | do \ | |
dcbf9037 | 6211 | { \ |
e07e6e58 NC |
6212 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ |
6213 | & inst.operands[i].vectype); \ | |
6214 | if (val == FAIL) \ | |
6215 | { \ | |
6216 | first_error (_(reg_expected_msgs[regtype])); \ | |
6217 | goto failure; \ | |
6218 | } \ | |
6219 | inst.operands[i].reg = val; \ | |
6220 | inst.operands[i].isreg = 1; \ | |
6221 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6222 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6223 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
6224 | || rtype == REG_TYPE_VFD \ | |
6225 | || rtype == REG_TYPE_NQ); \ | |
dcbf9037 | 6226 | } \ |
e07e6e58 NC |
6227 | while (0) |
6228 | ||
6229 | #define po_reg_or_goto(regtype, label) \ | |
6230 | do \ | |
6231 | { \ | |
6232 | val = arm_typed_reg_parse (& str, regtype, & rtype, \ | |
6233 | & inst.operands[i].vectype); \ | |
6234 | if (val == FAIL) \ | |
6235 | goto label; \ | |
dcbf9037 | 6236 | \ |
e07e6e58 NC |
6237 | inst.operands[i].reg = val; \ |
6238 | inst.operands[i].isreg = 1; \ | |
6239 | inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ | |
6240 | inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ | |
6241 | inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ | |
6242 | || rtype == REG_TYPE_VFD \ | |
6243 | || rtype == REG_TYPE_NQ); \ | |
6244 | } \ | |
6245 | while (0) | |
6246 | ||
6247 | #define po_imm_or_fail(min, max, popt) \ | |
6248 | do \ | |
6249 | { \ | |
6250 | if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ | |
6251 | goto failure; \ | |
6252 | inst.operands[i].imm = val; \ | |
6253 | } \ | |
6254 | while (0) | |
6255 | ||
6256 | #define po_scalar_or_goto(elsz, label) \ | |
6257 | do \ | |
6258 | { \ | |
6259 | val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \ | |
6260 | if (val == FAIL) \ | |
6261 | goto label; \ | |
6262 | inst.operands[i].reg = val; \ | |
6263 | inst.operands[i].isscalar = 1; \ | |
6264 | } \ | |
6265 | while (0) | |
6266 | ||
6267 | #define po_misc_or_fail(expr) \ | |
6268 | do \ | |
6269 | { \ | |
6270 | if (expr) \ | |
6271 | goto failure; \ | |
6272 | } \ | |
6273 | while (0) | |
6274 | ||
6275 | #define po_misc_or_fail_no_backtrack(expr) \ | |
6276 | do \ | |
6277 | { \ | |
6278 | result = expr; \ | |
6279 | if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \ | |
6280 | backtrack_pos = 0; \ | |
6281 | if (result != PARSE_OPERAND_SUCCESS) \ | |
6282 | goto failure; \ | |
6283 | } \ | |
6284 | while (0) | |
4962c51a | 6285 | |
52e7f43d RE |
6286 | #define po_barrier_or_imm(str) \ |
6287 | do \ | |
6288 | { \ | |
6289 | val = parse_barrier (&str); \ | |
6290 | if (val == FAIL) \ | |
6291 | { \ | |
6292 | if (ISALPHA (*str)) \ | |
6293 | goto failure; \ | |
6294 | else \ | |
6295 | goto immediate; \ | |
6296 | } \ | |
6297 | else \ | |
6298 | { \ | |
6299 | if ((inst.instruction & 0xf0) == 0x60 \ | |
6300 | && val != 0xf) \ | |
6301 | { \ | |
6302 | /* ISB can only take SY as an option. */ \ | |
6303 | inst.error = _("invalid barrier type"); \ | |
6304 | goto failure; \ | |
6305 | } \ | |
6306 | } \ | |
6307 | } \ | |
6308 | while (0) | |
6309 | ||
c19d1205 ZW |
6310 | skip_whitespace (str); |
6311 | ||
6312 | for (i = 0; upat[i] != OP_stop; i++) | |
6313 | { | |
5be8be5d DG |
6314 | op_parse_code = upat[i]; |
6315 | if (op_parse_code >= 1<<16) | |
6316 | op_parse_code = thumb ? (op_parse_code >> 16) | |
6317 | : (op_parse_code & ((1<<16)-1)); | |
6318 | ||
6319 | if (op_parse_code >= OP_FIRST_OPTIONAL) | |
c19d1205 ZW |
6320 | { |
6321 | /* Remember where we are in case we need to backtrack. */ | |
9c2799c2 | 6322 | gas_assert (!backtrack_pos); |
c19d1205 ZW |
6323 | backtrack_pos = str; |
6324 | backtrack_error = inst.error; | |
6325 | backtrack_index = i; | |
6326 | } | |
6327 | ||
b6702015 | 6328 | if (i > 0 && (i > 1 || inst.operands[0].present)) |
c19d1205 ZW |
6329 | po_char_or_fail (','); |
6330 | ||
5be8be5d | 6331 | switch (op_parse_code) |
c19d1205 ZW |
6332 | { |
6333 | /* Registers */ | |
6334 | case OP_oRRnpc: | |
5be8be5d | 6335 | case OP_oRRnpcsp: |
c19d1205 | 6336 | case OP_RRnpc: |
5be8be5d | 6337 | case OP_RRnpcsp: |
c19d1205 ZW |
6338 | case OP_oRR: |
6339 | case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; | |
6340 | case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; | |
6341 | case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; | |
6342 | case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; | |
6343 | case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; | |
6344 | case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; | |
5287ad62 JB |
6345 | case OP_oRND: |
6346 | case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; | |
cd2cf30b PB |
6347 | case OP_RVC: |
6348 | po_reg_or_goto (REG_TYPE_VFC, coproc_reg); | |
6349 | break; | |
6350 | /* Also accept generic coprocessor regs for unknown registers. */ | |
6351 | coproc_reg: | |
6352 | po_reg_or_fail (REG_TYPE_CN); | |
6353 | break; | |
c19d1205 ZW |
6354 | case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; |
6355 | case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; | |
6356 | case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; | |
6357 | case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; | |
6358 | case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; | |
6359 | case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; | |
6360 | case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; | |
6361 | case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; | |
6362 | case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; | |
6363 | case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; | |
5287ad62 JB |
6364 | case OP_oRNQ: |
6365 | case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; | |
6366 | case OP_oRNDQ: | |
6367 | case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; | |
037e8744 JB |
6368 | case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; |
6369 | case OP_oRNSDQ: | |
6370 | case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; | |
5287ad62 JB |
6371 | |
6372 | /* Neon scalar. Using an element size of 8 means that some invalid | |
6373 | scalars are accepted here, so deal with those in later code. */ | |
6374 | case OP_RNSC: po_scalar_or_goto (8, failure); break; | |
6375 | ||
5287ad62 JB |
6376 | case OP_RNDQ_I0: |
6377 | { | |
6378 | po_reg_or_goto (REG_TYPE_NDQ, try_imm0); | |
6379 | break; | |
6380 | try_imm0: | |
6381 | po_imm_or_fail (0, 0, TRUE); | |
6382 | } | |
6383 | break; | |
6384 | ||
037e8744 JB |
6385 | case OP_RVSD_I0: |
6386 | po_reg_or_goto (REG_TYPE_VFSD, try_imm0); | |
6387 | break; | |
6388 | ||
5287ad62 JB |
6389 | case OP_RR_RNSC: |
6390 | { | |
6391 | po_scalar_or_goto (8, try_rr); | |
6392 | break; | |
6393 | try_rr: | |
6394 | po_reg_or_fail (REG_TYPE_RN); | |
6395 | } | |
6396 | break; | |
6397 | ||
037e8744 JB |
6398 | case OP_RNSDQ_RNSC: |
6399 | { | |
6400 | po_scalar_or_goto (8, try_nsdq); | |
6401 | break; | |
6402 | try_nsdq: | |
6403 | po_reg_or_fail (REG_TYPE_NSDQ); | |
6404 | } | |
6405 | break; | |
6406 | ||
5287ad62 JB |
6407 | case OP_RNDQ_RNSC: |
6408 | { | |
6409 | po_scalar_or_goto (8, try_ndq); | |
6410 | break; | |
6411 | try_ndq: | |
6412 | po_reg_or_fail (REG_TYPE_NDQ); | |
6413 | } | |
6414 | break; | |
6415 | ||
6416 | case OP_RND_RNSC: | |
6417 | { | |
6418 | po_scalar_or_goto (8, try_vfd); | |
6419 | break; | |
6420 | try_vfd: | |
6421 | po_reg_or_fail (REG_TYPE_VFD); | |
6422 | } | |
6423 | break; | |
6424 | ||
6425 | case OP_VMOV: | |
6426 | /* WARNING: parse_neon_mov can move the operand counter, i. If we're | |
6427 | not careful then bad things might happen. */ | |
6428 | po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); | |
6429 | break; | |
6430 | ||
4316f0d2 | 6431 | case OP_RNDQ_Ibig: |
5287ad62 | 6432 | { |
4316f0d2 | 6433 | po_reg_or_goto (REG_TYPE_NDQ, try_immbig); |
5287ad62 | 6434 | break; |
4316f0d2 | 6435 | try_immbig: |
5287ad62 JB |
6436 | /* There's a possibility of getting a 64-bit immediate here, so |
6437 | we need special handling. */ | |
6438 | if (parse_big_immediate (&str, i) == FAIL) | |
6439 | { | |
6440 | inst.error = _("immediate value is out of range"); | |
6441 | goto failure; | |
6442 | } | |
6443 | } | |
6444 | break; | |
6445 | ||
6446 | case OP_RNDQ_I63b: | |
6447 | { | |
6448 | po_reg_or_goto (REG_TYPE_NDQ, try_shimm); | |
6449 | break; | |
6450 | try_shimm: | |
6451 | po_imm_or_fail (0, 63, TRUE); | |
6452 | } | |
6453 | break; | |
c19d1205 ZW |
6454 | |
6455 | case OP_RRnpcb: | |
6456 | po_char_or_fail ('['); | |
6457 | po_reg_or_fail (REG_TYPE_RN); | |
6458 | po_char_or_fail (']'); | |
6459 | break; | |
a737bd4d | 6460 | |
55881a11 | 6461 | case OP_RRnpctw: |
c19d1205 | 6462 | case OP_RRw: |
b6702015 | 6463 | case OP_oRRw: |
c19d1205 ZW |
6464 | po_reg_or_fail (REG_TYPE_RN); |
6465 | if (skip_past_char (&str, '!') == SUCCESS) | |
6466 | inst.operands[i].writeback = 1; | |
6467 | break; | |
6468 | ||
6469 | /* Immediates */ | |
6470 | case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; | |
6471 | case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; | |
6472 | case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; | |
5287ad62 | 6473 | case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; |
c19d1205 ZW |
6474 | case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; |
6475 | case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; | |
5287ad62 | 6476 | case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; |
c19d1205 | 6477 | case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; |
5287ad62 JB |
6478 | case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; |
6479 | case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; | |
6480 | case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; | |
c19d1205 | 6481 | case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; |
c19d1205 ZW |
6482 | |
6483 | case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; | |
6484 | case OP_oI7b: | |
6485 | case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; | |
6486 | case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; | |
6487 | case OP_oI31b: | |
6488 | case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; | |
5287ad62 | 6489 | case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; |
5f1af56b | 6490 | case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break; |
c19d1205 ZW |
6491 | case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; |
6492 | ||
6493 | /* Immediate variants */ | |
6494 | case OP_oI255c: | |
6495 | po_char_or_fail ('{'); | |
6496 | po_imm_or_fail (0, 255, TRUE); | |
6497 | po_char_or_fail ('}'); | |
6498 | break; | |
6499 | ||
6500 | case OP_I31w: | |
6501 | /* The expression parser chokes on a trailing !, so we have | |
6502 | to find it first and zap it. */ | |
6503 | { | |
6504 | char *s = str; | |
6505 | while (*s && *s != ',') | |
6506 | s++; | |
6507 | if (s[-1] == '!') | |
6508 | { | |
6509 | s[-1] = '\0'; | |
6510 | inst.operands[i].writeback = 1; | |
6511 | } | |
6512 | po_imm_or_fail (0, 31, TRUE); | |
6513 | if (str == s - 1) | |
6514 | str = s; | |
6515 | } | |
6516 | break; | |
6517 | ||
6518 | /* Expressions */ | |
6519 | case OP_EXPi: EXPi: | |
6520 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6521 | GE_OPT_PREFIX)); | |
6522 | break; | |
6523 | ||
6524 | case OP_EXP: | |
6525 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6526 | GE_NO_PREFIX)); | |
6527 | break; | |
6528 | ||
6529 | case OP_EXPr: EXPr: | |
6530 | po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, | |
6531 | GE_NO_PREFIX)); | |
6532 | if (inst.reloc.exp.X_op == O_symbol) | |
a737bd4d | 6533 | { |
c19d1205 ZW |
6534 | val = parse_reloc (&str); |
6535 | if (val == -1) | |
6536 | { | |
6537 | inst.error = _("unrecognized relocation suffix"); | |
6538 | goto failure; | |
6539 | } | |
6540 | else if (val != BFD_RELOC_UNUSED) | |
6541 | { | |
6542 | inst.operands[i].imm = val; | |
6543 | inst.operands[i].hasreloc = 1; | |
6544 | } | |
a737bd4d | 6545 | } |
c19d1205 | 6546 | break; |
a737bd4d | 6547 | |
b6895b4f PB |
6548 | /* Operand for MOVW or MOVT. */ |
6549 | case OP_HALF: | |
6550 | po_misc_or_fail (parse_half (&str)); | |
6551 | break; | |
6552 | ||
e07e6e58 | 6553 | /* Register or expression. */ |
c19d1205 ZW |
6554 | case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; |
6555 | case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; | |
a737bd4d | 6556 | |
e07e6e58 | 6557 | /* Register or immediate. */ |
c19d1205 ZW |
6558 | case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; |
6559 | I0: po_imm_or_fail (0, 0, FALSE); break; | |
a737bd4d | 6560 | |
c19d1205 ZW |
6561 | case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; |
6562 | IF: | |
6563 | if (!is_immediate_prefix (*str)) | |
6564 | goto bad_args; | |
6565 | str++; | |
6566 | val = parse_fpa_immediate (&str); | |
6567 | if (val == FAIL) | |
6568 | goto failure; | |
6569 | /* FPA immediates are encoded as registers 8-15. | |
6570 | parse_fpa_immediate has already applied the offset. */ | |
6571 | inst.operands[i].reg = val; | |
6572 | inst.operands[i].isreg = 1; | |
6573 | break; | |
09d92015 | 6574 | |
2d447fca JM |
6575 | case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; |
6576 | I32z: po_imm_or_fail (0, 32, FALSE); break; | |
6577 | ||
e07e6e58 | 6578 | /* Two kinds of register. */ |
c19d1205 ZW |
6579 | case OP_RIWR_RIWC: |
6580 | { | |
6581 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
97f87066 JM |
6582 | if (!rege |
6583 | || (rege->type != REG_TYPE_MMXWR | |
6584 | && rege->type != REG_TYPE_MMXWC | |
6585 | && rege->type != REG_TYPE_MMXWCG)) | |
c19d1205 ZW |
6586 | { |
6587 | inst.error = _("iWMMXt data or control register expected"); | |
6588 | goto failure; | |
6589 | } | |
6590 | inst.operands[i].reg = rege->number; | |
6591 | inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); | |
6592 | } | |
6593 | break; | |
09d92015 | 6594 | |
41adaa5c JM |
6595 | case OP_RIWC_RIWG: |
6596 | { | |
6597 | struct reg_entry *rege = arm_reg_parse_multi (&str); | |
6598 | if (!rege | |
6599 | || (rege->type != REG_TYPE_MMXWC | |
6600 | && rege->type != REG_TYPE_MMXWCG)) | |
6601 | { | |
6602 | inst.error = _("iWMMXt control register expected"); | |
6603 | goto failure; | |
6604 | } | |
6605 | inst.operands[i].reg = rege->number; | |
6606 | inst.operands[i].isreg = 1; | |
6607 | } | |
6608 | break; | |
6609 | ||
c19d1205 ZW |
6610 | /* Misc */ |
6611 | case OP_CPSF: val = parse_cps_flags (&str); break; | |
6612 | case OP_ENDI: val = parse_endian_specifier (&str); break; | |
6613 | case OP_oROR: val = parse_ror (&str); break; | |
c19d1205 | 6614 | case OP_COND: val = parse_cond (&str); break; |
52e7f43d RE |
6615 | case OP_oBARRIER_I15: |
6616 | po_barrier_or_imm (str); break; | |
6617 | immediate: | |
6618 | if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL) | |
6619 | goto failure; | |
6620 | break; | |
c19d1205 | 6621 | |
d2cd1205 JB |
6622 | case OP_wPSR: |
6623 | case OP_rPSR: | |
90ec0d68 MGD |
6624 | po_reg_or_goto (REG_TYPE_RNB, try_psr); |
6625 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt)) | |
6626 | { | |
6627 | inst.error = _("Banked registers are not available with this " | |
6628 | "architecture."); | |
6629 | goto failure; | |
6630 | } | |
6631 | break; | |
d2cd1205 JB |
6632 | try_psr: |
6633 | val = parse_psr (&str, op_parse_code == OP_wPSR); | |
6634 | break; | |
037e8744 JB |
6635 | |
6636 | case OP_APSR_RR: | |
6637 | po_reg_or_goto (REG_TYPE_RN, try_apsr); | |
6638 | break; | |
6639 | try_apsr: | |
6640 | /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS | |
6641 | instruction). */ | |
6642 | if (strncasecmp (str, "APSR_", 5) == 0) | |
6643 | { | |
6644 | unsigned found = 0; | |
6645 | str += 5; | |
6646 | while (found < 15) | |
6647 | switch (*str++) | |
6648 | { | |
6649 | case 'c': found = (found & 1) ? 16 : found | 1; break; | |
6650 | case 'n': found = (found & 2) ? 16 : found | 2; break; | |
6651 | case 'z': found = (found & 4) ? 16 : found | 4; break; | |
6652 | case 'v': found = (found & 8) ? 16 : found | 8; break; | |
6653 | default: found = 16; | |
6654 | } | |
6655 | if (found != 15) | |
6656 | goto failure; | |
6657 | inst.operands[i].isvec = 1; | |
f7c21dc7 NC |
6658 | /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */ |
6659 | inst.operands[i].reg = REG_PC; | |
037e8744 JB |
6660 | } |
6661 | else | |
6662 | goto failure; | |
6663 | break; | |
6664 | ||
92e90b6e PB |
6665 | case OP_TB: |
6666 | po_misc_or_fail (parse_tb (&str)); | |
6667 | break; | |
6668 | ||
e07e6e58 | 6669 | /* Register lists. */ |
c19d1205 ZW |
6670 | case OP_REGLST: |
6671 | val = parse_reg_list (&str); | |
6672 | if (*str == '^') | |
6673 | { | |
6674 | inst.operands[1].writeback = 1; | |
6675 | str++; | |
6676 | } | |
6677 | break; | |
09d92015 | 6678 | |
c19d1205 | 6679 | case OP_VRSLST: |
5287ad62 | 6680 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); |
c19d1205 | 6681 | break; |
09d92015 | 6682 | |
c19d1205 | 6683 | case OP_VRDLST: |
5287ad62 | 6684 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); |
c19d1205 | 6685 | break; |
a737bd4d | 6686 | |
037e8744 JB |
6687 | case OP_VRSDLST: |
6688 | /* Allow Q registers too. */ | |
6689 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6690 | REGLIST_NEON_D); | |
6691 | if (val == FAIL) | |
6692 | { | |
6693 | inst.error = NULL; | |
6694 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6695 | REGLIST_VFP_S); | |
6696 | inst.operands[i].issingle = 1; | |
6697 | } | |
6698 | break; | |
6699 | ||
5287ad62 JB |
6700 | case OP_NRDLST: |
6701 | val = parse_vfp_reg_list (&str, &inst.operands[i].reg, | |
6702 | REGLIST_NEON_D); | |
6703 | break; | |
6704 | ||
6705 | case OP_NSTRLST: | |
dcbf9037 JB |
6706 | val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, |
6707 | &inst.operands[i].vectype); | |
5287ad62 JB |
6708 | break; |
6709 | ||
c19d1205 ZW |
6710 | /* Addressing modes */ |
6711 | case OP_ADDR: | |
6712 | po_misc_or_fail (parse_address (&str, i)); | |
6713 | break; | |
09d92015 | 6714 | |
4962c51a MS |
6715 | case OP_ADDRGLDR: |
6716 | po_misc_or_fail_no_backtrack ( | |
6717 | parse_address_group_reloc (&str, i, GROUP_LDR)); | |
6718 | break; | |
6719 | ||
6720 | case OP_ADDRGLDRS: | |
6721 | po_misc_or_fail_no_backtrack ( | |
6722 | parse_address_group_reloc (&str, i, GROUP_LDRS)); | |
6723 | break; | |
6724 | ||
6725 | case OP_ADDRGLDC: | |
6726 | po_misc_or_fail_no_backtrack ( | |
6727 | parse_address_group_reloc (&str, i, GROUP_LDC)); | |
6728 | break; | |
6729 | ||
c19d1205 ZW |
6730 | case OP_SH: |
6731 | po_misc_or_fail (parse_shifter_operand (&str, i)); | |
6732 | break; | |
09d92015 | 6733 | |
4962c51a MS |
6734 | case OP_SHG: |
6735 | po_misc_or_fail_no_backtrack ( | |
6736 | parse_shifter_operand_group_reloc (&str, i)); | |
6737 | break; | |
6738 | ||
c19d1205 ZW |
6739 | case OP_oSHll: |
6740 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); | |
6741 | break; | |
09d92015 | 6742 | |
c19d1205 ZW |
6743 | case OP_oSHar: |
6744 | po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); | |
6745 | break; | |
09d92015 | 6746 | |
c19d1205 ZW |
6747 | case OP_oSHllar: |
6748 | po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); | |
6749 | break; | |
09d92015 | 6750 | |
c19d1205 | 6751 | default: |
5be8be5d | 6752 | as_fatal (_("unhandled operand code %d"), op_parse_code); |
c19d1205 | 6753 | } |
09d92015 | 6754 | |
c19d1205 ZW |
6755 | /* Various value-based sanity checks and shared operations. We |
6756 | do not signal immediate failures for the register constraints; | |
6757 | this allows a syntax error to take precedence. */ | |
5be8be5d | 6758 | switch (op_parse_code) |
c19d1205 ZW |
6759 | { |
6760 | case OP_oRRnpc: | |
6761 | case OP_RRnpc: | |
6762 | case OP_RRnpcb: | |
6763 | case OP_RRw: | |
b6702015 | 6764 | case OP_oRRw: |
c19d1205 ZW |
6765 | case OP_RRnpc_I0: |
6766 | if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) | |
6767 | inst.error = BAD_PC; | |
6768 | break; | |
09d92015 | 6769 | |
5be8be5d DG |
6770 | case OP_oRRnpcsp: |
6771 | case OP_RRnpcsp: | |
6772 | if (inst.operands[i].isreg) | |
6773 | { | |
6774 | if (inst.operands[i].reg == REG_PC) | |
6775 | inst.error = BAD_PC; | |
6776 | else if (inst.operands[i].reg == REG_SP) | |
6777 | inst.error = BAD_SP; | |
6778 | } | |
6779 | break; | |
6780 | ||
55881a11 MGD |
6781 | case OP_RRnpctw: |
6782 | if (inst.operands[i].isreg | |
6783 | && inst.operands[i].reg == REG_PC | |
6784 | && (inst.operands[i].writeback || thumb)) | |
6785 | inst.error = BAD_PC; | |
6786 | break; | |
6787 | ||
c19d1205 ZW |
6788 | case OP_CPSF: |
6789 | case OP_ENDI: | |
6790 | case OP_oROR: | |
d2cd1205 JB |
6791 | case OP_wPSR: |
6792 | case OP_rPSR: | |
c19d1205 | 6793 | case OP_COND: |
52e7f43d | 6794 | case OP_oBARRIER_I15: |
c19d1205 ZW |
6795 | case OP_REGLST: |
6796 | case OP_VRSLST: | |
6797 | case OP_VRDLST: | |
037e8744 | 6798 | case OP_VRSDLST: |
5287ad62 JB |
6799 | case OP_NRDLST: |
6800 | case OP_NSTRLST: | |
c19d1205 ZW |
6801 | if (val == FAIL) |
6802 | goto failure; | |
6803 | inst.operands[i].imm = val; | |
6804 | break; | |
a737bd4d | 6805 | |
c19d1205 ZW |
6806 | default: |
6807 | break; | |
6808 | } | |
09d92015 | 6809 | |
c19d1205 ZW |
6810 | /* If we get here, this operand was successfully parsed. */ |
6811 | inst.operands[i].present = 1; | |
6812 | continue; | |
09d92015 | 6813 | |
c19d1205 | 6814 | bad_args: |
09d92015 | 6815 | inst.error = BAD_ARGS; |
c19d1205 ZW |
6816 | |
6817 | failure: | |
6818 | if (!backtrack_pos) | |
d252fdde PB |
6819 | { |
6820 | /* The parse routine should already have set inst.error, but set a | |
5f4273c7 | 6821 | default here just in case. */ |
d252fdde PB |
6822 | if (!inst.error) |
6823 | inst.error = _("syntax error"); | |
6824 | return FAIL; | |
6825 | } | |
c19d1205 ZW |
6826 | |
6827 | /* Do not backtrack over a trailing optional argument that | |
6828 | absorbed some text. We will only fail again, with the | |
6829 | 'garbage following instruction' error message, which is | |
6830 | probably less helpful than the current one. */ | |
6831 | if (backtrack_index == i && backtrack_pos != str | |
6832 | && upat[i+1] == OP_stop) | |
d252fdde PB |
6833 | { |
6834 | if (!inst.error) | |
6835 | inst.error = _("syntax error"); | |
6836 | return FAIL; | |
6837 | } | |
c19d1205 ZW |
6838 | |
6839 | /* Try again, skipping the optional argument at backtrack_pos. */ | |
6840 | str = backtrack_pos; | |
6841 | inst.error = backtrack_error; | |
6842 | inst.operands[backtrack_index].present = 0; | |
6843 | i = backtrack_index; | |
6844 | backtrack_pos = 0; | |
09d92015 | 6845 | } |
09d92015 | 6846 | |
c19d1205 ZW |
6847 | /* Check that we have parsed all the arguments. */ |
6848 | if (*str != '\0' && !inst.error) | |
6849 | inst.error = _("garbage following instruction"); | |
09d92015 | 6850 | |
c19d1205 | 6851 | return inst.error ? FAIL : SUCCESS; |
09d92015 MM |
6852 | } |
6853 | ||
c19d1205 ZW |
6854 | #undef po_char_or_fail |
6855 | #undef po_reg_or_fail | |
6856 | #undef po_reg_or_goto | |
6857 | #undef po_imm_or_fail | |
5287ad62 | 6858 | #undef po_scalar_or_fail |
52e7f43d | 6859 | #undef po_barrier_or_imm |
e07e6e58 | 6860 | |
c19d1205 | 6861 | /* Shorthand macro for instruction encoding functions issuing errors. */ |
e07e6e58 NC |
6862 | #define constraint(expr, err) \ |
6863 | do \ | |
c19d1205 | 6864 | { \ |
e07e6e58 NC |
6865 | if (expr) \ |
6866 | { \ | |
6867 | inst.error = err; \ | |
6868 | return; \ | |
6869 | } \ | |
c19d1205 | 6870 | } \ |
e07e6e58 | 6871 | while (0) |
c19d1205 | 6872 | |
fdfde340 JM |
6873 | /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2 |
6874 | instructions are unpredictable if these registers are used. This | |
6875 | is the BadReg predicate in ARM's Thumb-2 documentation. */ | |
6876 | #define reject_bad_reg(reg) \ | |
6877 | do \ | |
6878 | if (reg == REG_SP || reg == REG_PC) \ | |
6879 | { \ | |
6880 | inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \ | |
6881 | return; \ | |
6882 | } \ | |
6883 | while (0) | |
6884 | ||
94206790 MM |
6885 | /* If REG is R13 (the stack pointer), warn that its use is |
6886 | deprecated. */ | |
6887 | #define warn_deprecated_sp(reg) \ | |
6888 | do \ | |
6889 | if (warn_on_deprecated && reg == REG_SP) \ | |
6890 | as_warn (_("use of r13 is deprecated")); \ | |
6891 | while (0) | |
6892 | ||
c19d1205 ZW |
6893 | /* Functions for operand encoding. ARM, then Thumb. */ |
6894 | ||
6895 | #define rotate_left(v, n) (v << n | v >> (32 - n)) | |
6896 | ||
6897 | /* If VAL can be encoded in the immediate field of an ARM instruction, | |
6898 | return the encoded form. Otherwise, return FAIL. */ | |
6899 | ||
6900 | static unsigned int | |
6901 | encode_arm_immediate (unsigned int val) | |
09d92015 | 6902 | { |
c19d1205 ZW |
6903 | unsigned int a, i; |
6904 | ||
6905 | for (i = 0; i < 32; i += 2) | |
6906 | if ((a = rotate_left (val, i)) <= 0xff) | |
6907 | return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ | |
6908 | ||
6909 | return FAIL; | |
09d92015 MM |
6910 | } |
6911 | ||
c19d1205 ZW |
6912 | /* If VAL can be encoded in the immediate field of a Thumb32 instruction, |
6913 | return the encoded form. Otherwise, return FAIL. */ | |
6914 | static unsigned int | |
6915 | encode_thumb32_immediate (unsigned int val) | |
09d92015 | 6916 | { |
c19d1205 | 6917 | unsigned int a, i; |
09d92015 | 6918 | |
9c3c69f2 | 6919 | if (val <= 0xff) |
c19d1205 | 6920 | return val; |
a737bd4d | 6921 | |
9c3c69f2 | 6922 | for (i = 1; i <= 24; i++) |
09d92015 | 6923 | { |
9c3c69f2 PB |
6924 | a = val >> i; |
6925 | if ((val & ~(0xff << i)) == 0) | |
6926 | return ((val >> i) & 0x7f) | ((32 - i) << 7); | |
09d92015 | 6927 | } |
a737bd4d | 6928 | |
c19d1205 ZW |
6929 | a = val & 0xff; |
6930 | if (val == ((a << 16) | a)) | |
6931 | return 0x100 | a; | |
6932 | if (val == ((a << 24) | (a << 16) | (a << 8) | a)) | |
6933 | return 0x300 | a; | |
09d92015 | 6934 | |
c19d1205 ZW |
6935 | a = val & 0xff00; |
6936 | if (val == ((a << 16) | a)) | |
6937 | return 0x200 | (a >> 8); | |
a737bd4d | 6938 | |
c19d1205 | 6939 | return FAIL; |
09d92015 | 6940 | } |
5287ad62 | 6941 | /* Encode a VFP SP or DP register number into inst.instruction. */ |
09d92015 MM |
6942 | |
6943 | static void | |
5287ad62 JB |
6944 | encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) |
6945 | { | |
6946 | if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) | |
6947 | && reg > 15) | |
6948 | { | |
b1cc4aeb | 6949 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32)) |
5287ad62 JB |
6950 | { |
6951 | if (thumb_mode) | |
6952 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
b1cc4aeb | 6953 | fpu_vfp_ext_d32); |
5287ad62 JB |
6954 | else |
6955 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, | |
b1cc4aeb | 6956 | fpu_vfp_ext_d32); |
5287ad62 JB |
6957 | } |
6958 | else | |
6959 | { | |
dcbf9037 | 6960 | first_error (_("D register out of range for selected VFP version")); |
5287ad62 JB |
6961 | return; |
6962 | } | |
6963 | } | |
6964 | ||
c19d1205 | 6965 | switch (pos) |
09d92015 | 6966 | { |
c19d1205 ZW |
6967 | case VFP_REG_Sd: |
6968 | inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); | |
6969 | break; | |
6970 | ||
6971 | case VFP_REG_Sn: | |
6972 | inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); | |
6973 | break; | |
6974 | ||
6975 | case VFP_REG_Sm: | |
6976 | inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); | |
6977 | break; | |
6978 | ||
5287ad62 JB |
6979 | case VFP_REG_Dd: |
6980 | inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); | |
6981 | break; | |
5f4273c7 | 6982 | |
5287ad62 JB |
6983 | case VFP_REG_Dn: |
6984 | inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); | |
6985 | break; | |
5f4273c7 | 6986 | |
5287ad62 JB |
6987 | case VFP_REG_Dm: |
6988 | inst.instruction |= (reg & 15) | ((reg >> 4) << 5); | |
6989 | break; | |
6990 | ||
c19d1205 ZW |
6991 | default: |
6992 | abort (); | |
09d92015 | 6993 | } |
09d92015 MM |
6994 | } |
6995 | ||
c19d1205 | 6996 | /* Encode a <shift> in an ARM-format instruction. The immediate, |
55cf6793 | 6997 | if any, is handled by md_apply_fix. */ |
09d92015 | 6998 | static void |
c19d1205 | 6999 | encode_arm_shift (int i) |
09d92015 | 7000 | { |
c19d1205 ZW |
7001 | if (inst.operands[i].shift_kind == SHIFT_RRX) |
7002 | inst.instruction |= SHIFT_ROR << 5; | |
7003 | else | |
09d92015 | 7004 | { |
c19d1205 ZW |
7005 | inst.instruction |= inst.operands[i].shift_kind << 5; |
7006 | if (inst.operands[i].immisreg) | |
7007 | { | |
7008 | inst.instruction |= SHIFT_BY_REG; | |
7009 | inst.instruction |= inst.operands[i].imm << 8; | |
7010 | } | |
7011 | else | |
7012 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
09d92015 | 7013 | } |
c19d1205 | 7014 | } |
09d92015 | 7015 | |
c19d1205 ZW |
7016 | static void |
7017 | encode_arm_shifter_operand (int i) | |
7018 | { | |
7019 | if (inst.operands[i].isreg) | |
09d92015 | 7020 | { |
c19d1205 ZW |
7021 | inst.instruction |= inst.operands[i].reg; |
7022 | encode_arm_shift (i); | |
09d92015 | 7023 | } |
c19d1205 | 7024 | else |
a415b1cd JB |
7025 | { |
7026 | inst.instruction |= INST_IMMEDIATE; | |
7027 | if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE) | |
7028 | inst.instruction |= inst.operands[i].imm; | |
7029 | } | |
09d92015 MM |
7030 | } |
7031 | ||
c19d1205 | 7032 | /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ |
09d92015 | 7033 | static void |
c19d1205 | 7034 | encode_arm_addr_mode_common (int i, bfd_boolean is_t) |
09d92015 | 7035 | { |
9c2799c2 | 7036 | gas_assert (inst.operands[i].isreg); |
c19d1205 | 7037 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7038 | |
c19d1205 | 7039 | if (inst.operands[i].preind) |
09d92015 | 7040 | { |
c19d1205 ZW |
7041 | if (is_t) |
7042 | { | |
7043 | inst.error = _("instruction does not accept preindexed addressing"); | |
7044 | return; | |
7045 | } | |
7046 | inst.instruction |= PRE_INDEX; | |
7047 | if (inst.operands[i].writeback) | |
7048 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7049 | |
c19d1205 ZW |
7050 | } |
7051 | else if (inst.operands[i].postind) | |
7052 | { | |
9c2799c2 | 7053 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
7054 | if (is_t) |
7055 | inst.instruction |= WRITE_BACK; | |
7056 | } | |
7057 | else /* unindexed - only for coprocessor */ | |
09d92015 | 7058 | { |
c19d1205 | 7059 | inst.error = _("instruction does not accept unindexed addressing"); |
09d92015 MM |
7060 | return; |
7061 | } | |
7062 | ||
c19d1205 ZW |
7063 | if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) |
7064 | && (((inst.instruction & 0x000f0000) >> 16) | |
7065 | == ((inst.instruction & 0x0000f000) >> 12))) | |
7066 | as_warn ((inst.instruction & LOAD_BIT) | |
7067 | ? _("destination register same as write-back base") | |
7068 | : _("source register same as write-back base")); | |
09d92015 MM |
7069 | } |
7070 | ||
c19d1205 ZW |
7071 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7072 | ARM-format mode 2 load or store instruction. If is_t is true, | |
7073 | reject forms that cannot be used with a T instruction (i.e. not | |
7074 | post-indexed). */ | |
a737bd4d | 7075 | static void |
c19d1205 | 7076 | encode_arm_addr_mode_2 (int i, bfd_boolean is_t) |
09d92015 | 7077 | { |
5be8be5d DG |
7078 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
7079 | ||
c19d1205 | 7080 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7081 | |
c19d1205 | 7082 | if (inst.operands[i].immisreg) |
09d92015 | 7083 | { |
5be8be5d DG |
7084 | constraint ((inst.operands[i].imm == REG_PC |
7085 | || (is_pc && inst.operands[i].writeback)), | |
7086 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7087 | inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ |
7088 | inst.instruction |= inst.operands[i].imm; | |
7089 | if (!inst.operands[i].negative) | |
7090 | inst.instruction |= INDEX_UP; | |
7091 | if (inst.operands[i].shifted) | |
7092 | { | |
7093 | if (inst.operands[i].shift_kind == SHIFT_RRX) | |
7094 | inst.instruction |= SHIFT_ROR << 5; | |
7095 | else | |
7096 | { | |
7097 | inst.instruction |= inst.operands[i].shift_kind << 5; | |
7098 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; | |
7099 | } | |
7100 | } | |
09d92015 | 7101 | } |
c19d1205 | 7102 | else /* immediate offset in inst.reloc */ |
09d92015 | 7103 | { |
5be8be5d DG |
7104 | if (is_pc && !inst.reloc.pc_rel) |
7105 | { | |
7106 | const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0); | |
23a10334 JZ |
7107 | |
7108 | /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt | |
7109 | cannot use PC in addressing. | |
7110 | PC cannot be used in writeback addressing, either. */ | |
7111 | constraint ((is_t || inst.operands[i].writeback), | |
5be8be5d | 7112 | BAD_PC_ADDRESSING); |
23a10334 | 7113 | |
dc5ec521 | 7114 | /* Use of PC in str is deprecated for ARMv7. */ |
23a10334 JZ |
7115 | if (warn_on_deprecated |
7116 | && !is_load | |
7117 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
7118 | as_warn (_("use of PC in this instruction is deprecated")); | |
5be8be5d DG |
7119 | } |
7120 | ||
c19d1205 | 7121 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
26d97720 NS |
7122 | { |
7123 | /* Prefer + for zero encoded value. */ | |
7124 | if (!inst.operands[i].negative) | |
7125 | inst.instruction |= INDEX_UP; | |
7126 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; | |
7127 | } | |
09d92015 | 7128 | } |
09d92015 MM |
7129 | } |
7130 | ||
c19d1205 ZW |
7131 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7132 | ARM-format mode 3 load or store instruction. Reject forms that | |
7133 | cannot be used with such instructions. If is_t is true, reject | |
7134 | forms that cannot be used with a T instruction (i.e. not | |
7135 | post-indexed). */ | |
7136 | static void | |
7137 | encode_arm_addr_mode_3 (int i, bfd_boolean is_t) | |
09d92015 | 7138 | { |
c19d1205 | 7139 | if (inst.operands[i].immisreg && inst.operands[i].shifted) |
09d92015 | 7140 | { |
c19d1205 ZW |
7141 | inst.error = _("instruction does not accept scaled register index"); |
7142 | return; | |
09d92015 | 7143 | } |
a737bd4d | 7144 | |
c19d1205 | 7145 | encode_arm_addr_mode_common (i, is_t); |
a737bd4d | 7146 | |
c19d1205 ZW |
7147 | if (inst.operands[i].immisreg) |
7148 | { | |
5be8be5d DG |
7149 | constraint ((inst.operands[i].imm == REG_PC |
7150 | || inst.operands[i].reg == REG_PC), | |
7151 | BAD_PC_ADDRESSING); | |
c19d1205 ZW |
7152 | inst.instruction |= inst.operands[i].imm; |
7153 | if (!inst.operands[i].negative) | |
7154 | inst.instruction |= INDEX_UP; | |
7155 | } | |
7156 | else /* immediate offset in inst.reloc */ | |
7157 | { | |
5be8be5d DG |
7158 | constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel |
7159 | && inst.operands[i].writeback), | |
7160 | BAD_PC_WRITEBACK); | |
c19d1205 ZW |
7161 | inst.instruction |= HWOFFSET_IMM; |
7162 | if (inst.reloc.type == BFD_RELOC_UNUSED) | |
26d97720 NS |
7163 | { |
7164 | /* Prefer + for zero encoded value. */ | |
7165 | if (!inst.operands[i].negative) | |
7166 | inst.instruction |= INDEX_UP; | |
7167 | ||
7168 | inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; | |
7169 | } | |
c19d1205 | 7170 | } |
a737bd4d NC |
7171 | } |
7172 | ||
c19d1205 ZW |
7173 | /* inst.operands[i] was set up by parse_address. Encode it into an |
7174 | ARM-format instruction. Reject all forms which cannot be encoded | |
7175 | into a coprocessor load/store instruction. If wb_ok is false, | |
7176 | reject use of writeback; if unind_ok is false, reject use of | |
7177 | unindexed addressing. If reloc_override is not 0, use it instead | |
4962c51a MS |
7178 | of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one |
7179 | (in which case it is preserved). */ | |
09d92015 | 7180 | |
c19d1205 ZW |
7181 | static int |
7182 | encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) | |
09d92015 | 7183 | { |
c19d1205 | 7184 | inst.instruction |= inst.operands[i].reg << 16; |
a737bd4d | 7185 | |
9c2799c2 | 7186 | gas_assert (!(inst.operands[i].preind && inst.operands[i].postind)); |
09d92015 | 7187 | |
c19d1205 | 7188 | if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ |
09d92015 | 7189 | { |
9c2799c2 | 7190 | gas_assert (!inst.operands[i].writeback); |
c19d1205 ZW |
7191 | if (!unind_ok) |
7192 | { | |
7193 | inst.error = _("instruction does not support unindexed addressing"); | |
7194 | return FAIL; | |
7195 | } | |
7196 | inst.instruction |= inst.operands[i].imm; | |
7197 | inst.instruction |= INDEX_UP; | |
7198 | return SUCCESS; | |
09d92015 | 7199 | } |
a737bd4d | 7200 | |
c19d1205 ZW |
7201 | if (inst.operands[i].preind) |
7202 | inst.instruction |= PRE_INDEX; | |
a737bd4d | 7203 | |
c19d1205 | 7204 | if (inst.operands[i].writeback) |
09d92015 | 7205 | { |
c19d1205 ZW |
7206 | if (inst.operands[i].reg == REG_PC) |
7207 | { | |
7208 | inst.error = _("pc may not be used with write-back"); | |
7209 | return FAIL; | |
7210 | } | |
7211 | if (!wb_ok) | |
7212 | { | |
7213 | inst.error = _("instruction does not support writeback"); | |
7214 | return FAIL; | |
7215 | } | |
7216 | inst.instruction |= WRITE_BACK; | |
09d92015 | 7217 | } |
a737bd4d | 7218 | |
c19d1205 | 7219 | if (reloc_override) |
21d799b5 | 7220 | inst.reloc.type = (bfd_reloc_code_real_type) reloc_override; |
4962c51a MS |
7221 | else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC |
7222 | || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) | |
7223 | && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) | |
7224 | { | |
7225 | if (thumb_mode) | |
7226 | inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; | |
7227 | else | |
7228 | inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; | |
7229 | } | |
7230 | ||
26d97720 NS |
7231 | /* Prefer + for zero encoded value. */ |
7232 | if (!inst.operands[i].negative) | |
7233 | inst.instruction |= INDEX_UP; | |
7234 | ||
c19d1205 ZW |
7235 | return SUCCESS; |
7236 | } | |
a737bd4d | 7237 | |
c19d1205 ZW |
7238 | /* inst.reloc.exp describes an "=expr" load pseudo-operation. |
7239 | Determine whether it can be performed with a move instruction; if | |
7240 | it can, convert inst.instruction to that move instruction and | |
c921be7d NC |
7241 | return TRUE; if it can't, convert inst.instruction to a literal-pool |
7242 | load and return FALSE. If this is not a valid thing to do in the | |
7243 | current context, set inst.error and return TRUE. | |
a737bd4d | 7244 | |
c19d1205 ZW |
7245 | inst.operands[i] describes the destination register. */ |
7246 | ||
c921be7d | 7247 | static bfd_boolean |
c19d1205 ZW |
7248 | move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) |
7249 | { | |
53365c0d PB |
7250 | unsigned long tbit; |
7251 | ||
7252 | if (thumb_p) | |
7253 | tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; | |
7254 | else | |
7255 | tbit = LOAD_BIT; | |
7256 | ||
7257 | if ((inst.instruction & tbit) == 0) | |
09d92015 | 7258 | { |
c19d1205 | 7259 | inst.error = _("invalid pseudo operation"); |
c921be7d | 7260 | return TRUE; |
09d92015 | 7261 | } |
c19d1205 | 7262 | if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) |
09d92015 MM |
7263 | { |
7264 | inst.error = _("constant expression expected"); | |
c921be7d | 7265 | return TRUE; |
09d92015 | 7266 | } |
c19d1205 | 7267 | if (inst.reloc.exp.X_op == O_constant) |
09d92015 | 7268 | { |
c19d1205 ZW |
7269 | if (thumb_p) |
7270 | { | |
53365c0d | 7271 | if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) |
c19d1205 ZW |
7272 | { |
7273 | /* This can be done with a mov(1) instruction. */ | |
7274 | inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); | |
7275 | inst.instruction |= inst.reloc.exp.X_add_number; | |
c921be7d | 7276 | return TRUE; |
c19d1205 ZW |
7277 | } |
7278 | } | |
7279 | else | |
7280 | { | |
7281 | int value = encode_arm_immediate (inst.reloc.exp.X_add_number); | |
7282 | if (value != FAIL) | |
7283 | { | |
7284 | /* This can be done with a mov instruction. */ | |
7285 | inst.instruction &= LITERAL_MASK; | |
7286 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); | |
7287 | inst.instruction |= value & 0xfff; | |
c921be7d | 7288 | return TRUE; |
c19d1205 | 7289 | } |
09d92015 | 7290 | |
c19d1205 ZW |
7291 | value = encode_arm_immediate (~inst.reloc.exp.X_add_number); |
7292 | if (value != FAIL) | |
7293 | { | |
7294 | /* This can be done with a mvn instruction. */ | |
7295 | inst.instruction &= LITERAL_MASK; | |
7296 | inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); | |
7297 | inst.instruction |= value & 0xfff; | |
c921be7d | 7298 | return TRUE; |
c19d1205 ZW |
7299 | } |
7300 | } | |
09d92015 MM |
7301 | } |
7302 | ||
c19d1205 ZW |
7303 | if (add_to_lit_pool () == FAIL) |
7304 | { | |
7305 | inst.error = _("literal pool insertion failed"); | |
c921be7d | 7306 | return TRUE; |
c19d1205 ZW |
7307 | } |
7308 | inst.operands[1].reg = REG_PC; | |
7309 | inst.operands[1].isreg = 1; | |
7310 | inst.operands[1].preind = 1; | |
7311 | inst.reloc.pc_rel = 1; | |
7312 | inst.reloc.type = (thumb_p | |
7313 | ? BFD_RELOC_ARM_THUMB_OFFSET | |
7314 | : (mode_3 | |
7315 | ? BFD_RELOC_ARM_HWLITERAL | |
7316 | : BFD_RELOC_ARM_LITERAL)); | |
c921be7d | 7317 | return FALSE; |
09d92015 MM |
7318 | } |
7319 | ||
5f4273c7 | 7320 | /* Functions for instruction encoding, sorted by sub-architecture. |
c19d1205 ZW |
7321 | First some generics; their names are taken from the conventional |
7322 | bit positions for register arguments in ARM format instructions. */ | |
09d92015 | 7323 | |
a737bd4d | 7324 | static void |
c19d1205 | 7325 | do_noargs (void) |
09d92015 | 7326 | { |
c19d1205 | 7327 | } |
a737bd4d | 7328 | |
c19d1205 ZW |
7329 | static void |
7330 | do_rd (void) | |
7331 | { | |
7332 | inst.instruction |= inst.operands[0].reg << 12; | |
7333 | } | |
a737bd4d | 7334 | |
c19d1205 ZW |
7335 | static void |
7336 | do_rd_rm (void) | |
7337 | { | |
7338 | inst.instruction |= inst.operands[0].reg << 12; | |
7339 | inst.instruction |= inst.operands[1].reg; | |
7340 | } | |
09d92015 | 7341 | |
c19d1205 ZW |
7342 | static void |
7343 | do_rd_rn (void) | |
7344 | { | |
7345 | inst.instruction |= inst.operands[0].reg << 12; | |
7346 | inst.instruction |= inst.operands[1].reg << 16; | |
7347 | } | |
a737bd4d | 7348 | |
c19d1205 ZW |
7349 | static void |
7350 | do_rn_rd (void) | |
7351 | { | |
7352 | inst.instruction |= inst.operands[0].reg << 16; | |
7353 | inst.instruction |= inst.operands[1].reg << 12; | |
7354 | } | |
09d92015 | 7355 | |
c19d1205 ZW |
7356 | static void |
7357 | do_rd_rm_rn (void) | |
7358 | { | |
9a64e435 | 7359 | unsigned Rn = inst.operands[2].reg; |
708587a4 | 7360 | /* Enforce restrictions on SWP instruction. */ |
9a64e435 | 7361 | if ((inst.instruction & 0x0fbfffff) == 0x01000090) |
56adecf4 DG |
7362 | { |
7363 | constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, | |
7364 | _("Rn must not overlap other operands")); | |
7365 | ||
7366 | /* SWP{b} is deprecated for ARMv6* and ARMv7. */ | |
7367 | if (warn_on_deprecated | |
7368 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
7369 | as_warn (_("swp{b} use is deprecated for this architecture")); | |
7370 | ||
7371 | } | |
c19d1205 ZW |
7372 | inst.instruction |= inst.operands[0].reg << 12; |
7373 | inst.instruction |= inst.operands[1].reg; | |
9a64e435 | 7374 | inst.instruction |= Rn << 16; |
c19d1205 | 7375 | } |
09d92015 | 7376 | |
c19d1205 ZW |
7377 | static void |
7378 | do_rd_rn_rm (void) | |
7379 | { | |
7380 | inst.instruction |= inst.operands[0].reg << 12; | |
7381 | inst.instruction |= inst.operands[1].reg << 16; | |
7382 | inst.instruction |= inst.operands[2].reg; | |
7383 | } | |
a737bd4d | 7384 | |
c19d1205 ZW |
7385 | static void |
7386 | do_rm_rd_rn (void) | |
7387 | { | |
5be8be5d DG |
7388 | constraint ((inst.operands[2].reg == REG_PC), BAD_PC); |
7389 | constraint (((inst.reloc.exp.X_op != O_constant | |
7390 | && inst.reloc.exp.X_op != O_illegal) | |
7391 | || inst.reloc.exp.X_add_number != 0), | |
7392 | BAD_ADDR_MODE); | |
c19d1205 ZW |
7393 | inst.instruction |= inst.operands[0].reg; |
7394 | inst.instruction |= inst.operands[1].reg << 12; | |
7395 | inst.instruction |= inst.operands[2].reg << 16; | |
7396 | } | |
09d92015 | 7397 | |
c19d1205 ZW |
7398 | static void |
7399 | do_imm0 (void) | |
7400 | { | |
7401 | inst.instruction |= inst.operands[0].imm; | |
7402 | } | |
09d92015 | 7403 | |
c19d1205 ZW |
7404 | static void |
7405 | do_rd_cpaddr (void) | |
7406 | { | |
7407 | inst.instruction |= inst.operands[0].reg << 12; | |
7408 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
09d92015 | 7409 | } |
a737bd4d | 7410 | |
c19d1205 ZW |
7411 | /* ARM instructions, in alphabetical order by function name (except |
7412 | that wrapper functions appear immediately after the function they | |
7413 | wrap). */ | |
09d92015 | 7414 | |
c19d1205 ZW |
7415 | /* This is a pseudo-op of the form "adr rd, label" to be converted |
7416 | into a relative address of the form "add rd, pc, #label-.-8". */ | |
09d92015 MM |
7417 | |
7418 | static void | |
c19d1205 | 7419 | do_adr (void) |
09d92015 | 7420 | { |
c19d1205 | 7421 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ |
a737bd4d | 7422 | |
c19d1205 ZW |
7423 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7424 | out to be negative. */ | |
7425 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
c19d1205 | 7426 | inst.reloc.pc_rel = 1; |
2fc8bdac | 7427 | inst.reloc.exp.X_add_number -= 8; |
c19d1205 | 7428 | } |
b99bd4ef | 7429 | |
c19d1205 ZW |
7430 | /* This is a pseudo-op of the form "adrl rd, label" to be converted |
7431 | into a relative address of the form: | |
7432 | add rd, pc, #low(label-.-8)" | |
7433 | add rd, rd, #high(label-.-8)" */ | |
b99bd4ef | 7434 | |
c19d1205 ZW |
7435 | static void |
7436 | do_adrl (void) | |
7437 | { | |
7438 | inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ | |
a737bd4d | 7439 | |
c19d1205 ZW |
7440 | /* Frag hacking will turn this into a sub instruction if the offset turns |
7441 | out to be negative. */ | |
7442 | inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; | |
c19d1205 ZW |
7443 | inst.reloc.pc_rel = 1; |
7444 | inst.size = INSN_SIZE * 2; | |
2fc8bdac | 7445 | inst.reloc.exp.X_add_number -= 8; |
b99bd4ef NC |
7446 | } |
7447 | ||
b99bd4ef | 7448 | static void |
c19d1205 | 7449 | do_arit (void) |
b99bd4ef | 7450 | { |
c19d1205 ZW |
7451 | if (!inst.operands[1].present) |
7452 | inst.operands[1].reg = inst.operands[0].reg; | |
7453 | inst.instruction |= inst.operands[0].reg << 12; | |
7454 | inst.instruction |= inst.operands[1].reg << 16; | |
7455 | encode_arm_shifter_operand (2); | |
7456 | } | |
b99bd4ef | 7457 | |
62b3e311 PB |
7458 | static void |
7459 | do_barrier (void) | |
7460 | { | |
7461 | if (inst.operands[0].present) | |
7462 | { | |
7463 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
7464 | && inst.operands[0].imm > 0xf |
7465 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 7466 | _("bad barrier type")); |
62b3e311 PB |
7467 | inst.instruction |= inst.operands[0].imm; |
7468 | } | |
7469 | else | |
7470 | inst.instruction |= 0xf; | |
7471 | } | |
7472 | ||
c19d1205 ZW |
7473 | static void |
7474 | do_bfc (void) | |
7475 | { | |
7476 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; | |
7477 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7478 | /* The instruction encoding stores the LSB and MSB, | |
7479 | not the LSB and width. */ | |
7480 | inst.instruction |= inst.operands[0].reg << 12; | |
7481 | inst.instruction |= inst.operands[1].imm << 7; | |
7482 | inst.instruction |= (msb - 1) << 16; | |
7483 | } | |
b99bd4ef | 7484 | |
c19d1205 ZW |
7485 | static void |
7486 | do_bfi (void) | |
7487 | { | |
7488 | unsigned int msb; | |
b99bd4ef | 7489 | |
c19d1205 ZW |
7490 | /* #0 in second position is alternative syntax for bfc, which is |
7491 | the same instruction but with REG_PC in the Rm field. */ | |
7492 | if (!inst.operands[1].isreg) | |
7493 | inst.operands[1].reg = REG_PC; | |
b99bd4ef | 7494 | |
c19d1205 ZW |
7495 | msb = inst.operands[2].imm + inst.operands[3].imm; |
7496 | constraint (msb > 32, _("bit-field extends past end of register")); | |
7497 | /* The instruction encoding stores the LSB and MSB, | |
7498 | not the LSB and width. */ | |
7499 | inst.instruction |= inst.operands[0].reg << 12; | |
7500 | inst.instruction |= inst.operands[1].reg; | |
7501 | inst.instruction |= inst.operands[2].imm << 7; | |
7502 | inst.instruction |= (msb - 1) << 16; | |
b99bd4ef NC |
7503 | } |
7504 | ||
b99bd4ef | 7505 | static void |
c19d1205 | 7506 | do_bfx (void) |
b99bd4ef | 7507 | { |
c19d1205 ZW |
7508 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
7509 | _("bit-field extends past end of register")); | |
7510 | inst.instruction |= inst.operands[0].reg << 12; | |
7511 | inst.instruction |= inst.operands[1].reg; | |
7512 | inst.instruction |= inst.operands[2].imm << 7; | |
7513 | inst.instruction |= (inst.operands[3].imm - 1) << 16; | |
7514 | } | |
09d92015 | 7515 | |
c19d1205 ZW |
7516 | /* ARM V5 breakpoint instruction (argument parse) |
7517 | BKPT <16 bit unsigned immediate> | |
7518 | Instruction is not conditional. | |
7519 | The bit pattern given in insns[] has the COND_ALWAYS condition, | |
7520 | and it is an error if the caller tried to override that. */ | |
b99bd4ef | 7521 | |
c19d1205 ZW |
7522 | static void |
7523 | do_bkpt (void) | |
7524 | { | |
7525 | /* Top 12 of 16 bits to bits 19:8. */ | |
7526 | inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; | |
09d92015 | 7527 | |
c19d1205 ZW |
7528 | /* Bottom 4 of 16 bits to bits 3:0. */ |
7529 | inst.instruction |= inst.operands[0].imm & 0xf; | |
7530 | } | |
09d92015 | 7531 | |
c19d1205 ZW |
7532 | static void |
7533 | encode_branch (int default_reloc) | |
7534 | { | |
7535 | if (inst.operands[0].hasreloc) | |
7536 | { | |
0855e32b NS |
7537 | constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32 |
7538 | && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL, | |
7539 | _("the only valid suffixes here are '(plt)' and '(tlscall)'")); | |
7540 | inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32 | |
7541 | ? BFD_RELOC_ARM_PLT32 | |
7542 | : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL; | |
c19d1205 | 7543 | } |
b99bd4ef | 7544 | else |
9ae92b05 | 7545 | inst.reloc.type = (bfd_reloc_code_real_type) default_reloc; |
2fc8bdac | 7546 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
7547 | } |
7548 | ||
b99bd4ef | 7549 | static void |
c19d1205 | 7550 | do_branch (void) |
b99bd4ef | 7551 | { |
39b41c9c PB |
7552 | #ifdef OBJ_ELF |
7553 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7554 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7555 | else | |
7556 | #endif | |
7557 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
7558 | } | |
7559 | ||
7560 | static void | |
7561 | do_bl (void) | |
7562 | { | |
7563 | #ifdef OBJ_ELF | |
7564 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
7565 | { | |
7566 | if (inst.cond == COND_ALWAYS) | |
7567 | encode_branch (BFD_RELOC_ARM_PCREL_CALL); | |
7568 | else | |
7569 | encode_branch (BFD_RELOC_ARM_PCREL_JUMP); | |
7570 | } | |
7571 | else | |
7572 | #endif | |
7573 | encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); | |
c19d1205 | 7574 | } |
b99bd4ef | 7575 | |
c19d1205 ZW |
7576 | /* ARM V5 branch-link-exchange instruction (argument parse) |
7577 | BLX <target_addr> ie BLX(1) | |
7578 | BLX{<condition>} <Rm> ie BLX(2) | |
7579 | Unfortunately, there are two different opcodes for this mnemonic. | |
7580 | So, the insns[].value is not used, and the code here zaps values | |
7581 | into inst.instruction. | |
7582 | Also, the <target_addr> can be 25 bits, hence has its own reloc. */ | |
b99bd4ef | 7583 | |
c19d1205 ZW |
7584 | static void |
7585 | do_blx (void) | |
7586 | { | |
7587 | if (inst.operands[0].isreg) | |
b99bd4ef | 7588 | { |
c19d1205 ZW |
7589 | /* Arg is a register; the opcode provided by insns[] is correct. |
7590 | It is not illegal to do "blx pc", just useless. */ | |
7591 | if (inst.operands[0].reg == REG_PC) | |
7592 | as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); | |
b99bd4ef | 7593 | |
c19d1205 ZW |
7594 | inst.instruction |= inst.operands[0].reg; |
7595 | } | |
7596 | else | |
b99bd4ef | 7597 | { |
c19d1205 | 7598 | /* Arg is an address; this instruction cannot be executed |
267bf995 RR |
7599 | conditionally, and the opcode must be adjusted. |
7600 | We retain the BFD_RELOC_ARM_PCREL_BLX till the very end | |
7601 | where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */ | |
c19d1205 | 7602 | constraint (inst.cond != COND_ALWAYS, BAD_COND); |
2fc8bdac | 7603 | inst.instruction = 0xfa000000; |
267bf995 | 7604 | encode_branch (BFD_RELOC_ARM_PCREL_BLX); |
b99bd4ef | 7605 | } |
c19d1205 ZW |
7606 | } |
7607 | ||
7608 | static void | |
7609 | do_bx (void) | |
7610 | { | |
845b51d6 PB |
7611 | bfd_boolean want_reloc; |
7612 | ||
c19d1205 ZW |
7613 | if (inst.operands[0].reg == REG_PC) |
7614 | as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); | |
b99bd4ef | 7615 | |
c19d1205 | 7616 | inst.instruction |= inst.operands[0].reg; |
845b51d6 PB |
7617 | /* Output R_ARM_V4BX relocations if is an EABI object that looks like |
7618 | it is for ARMv4t or earlier. */ | |
7619 | want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5); | |
7620 | if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5)) | |
7621 | want_reloc = TRUE; | |
7622 | ||
5ad34203 | 7623 | #ifdef OBJ_ELF |
845b51d6 | 7624 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
5ad34203 | 7625 | #endif |
584206db | 7626 | want_reloc = FALSE; |
845b51d6 PB |
7627 | |
7628 | if (want_reloc) | |
7629 | inst.reloc.type = BFD_RELOC_ARM_V4BX; | |
09d92015 MM |
7630 | } |
7631 | ||
c19d1205 ZW |
7632 | |
7633 | /* ARM v5TEJ. Jump to Jazelle code. */ | |
a737bd4d NC |
7634 | |
7635 | static void | |
c19d1205 | 7636 | do_bxj (void) |
a737bd4d | 7637 | { |
c19d1205 ZW |
7638 | if (inst.operands[0].reg == REG_PC) |
7639 | as_tsktsk (_("use of r15 in bxj is not really useful")); | |
7640 | ||
7641 | inst.instruction |= inst.operands[0].reg; | |
a737bd4d NC |
7642 | } |
7643 | ||
c19d1205 ZW |
7644 | /* Co-processor data operation: |
7645 | CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} | |
7646 | CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ | |
7647 | static void | |
7648 | do_cdp (void) | |
7649 | { | |
7650 | inst.instruction |= inst.operands[0].reg << 8; | |
7651 | inst.instruction |= inst.operands[1].imm << 20; | |
7652 | inst.instruction |= inst.operands[2].reg << 12; | |
7653 | inst.instruction |= inst.operands[3].reg << 16; | |
7654 | inst.instruction |= inst.operands[4].reg; | |
7655 | inst.instruction |= inst.operands[5].imm << 5; | |
7656 | } | |
a737bd4d NC |
7657 | |
7658 | static void | |
c19d1205 | 7659 | do_cmp (void) |
a737bd4d | 7660 | { |
c19d1205 ZW |
7661 | inst.instruction |= inst.operands[0].reg << 16; |
7662 | encode_arm_shifter_operand (1); | |
a737bd4d NC |
7663 | } |
7664 | ||
c19d1205 ZW |
7665 | /* Transfer between coprocessor and ARM registers. |
7666 | MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} | |
7667 | MRC2 | |
7668 | MCR{cond} | |
7669 | MCR2 | |
7670 | ||
7671 | No special properties. */ | |
09d92015 MM |
7672 | |
7673 | static void | |
c19d1205 | 7674 | do_co_reg (void) |
09d92015 | 7675 | { |
fdfde340 JM |
7676 | unsigned Rd; |
7677 | ||
7678 | Rd = inst.operands[2].reg; | |
7679 | if (thumb_mode) | |
7680 | { | |
7681 | if (inst.instruction == 0xee000010 | |
7682 | || inst.instruction == 0xfe000010) | |
7683 | /* MCR, MCR2 */ | |
7684 | reject_bad_reg (Rd); | |
7685 | else | |
7686 | /* MRC, MRC2 */ | |
7687 | constraint (Rd == REG_SP, BAD_SP); | |
7688 | } | |
7689 | else | |
7690 | { | |
7691 | /* MCR */ | |
7692 | if (inst.instruction == 0xe000010) | |
7693 | constraint (Rd == REG_PC, BAD_PC); | |
7694 | } | |
7695 | ||
7696 | ||
c19d1205 ZW |
7697 | inst.instruction |= inst.operands[0].reg << 8; |
7698 | inst.instruction |= inst.operands[1].imm << 21; | |
fdfde340 | 7699 | inst.instruction |= Rd << 12; |
c19d1205 ZW |
7700 | inst.instruction |= inst.operands[3].reg << 16; |
7701 | inst.instruction |= inst.operands[4].reg; | |
7702 | inst.instruction |= inst.operands[5].imm << 5; | |
7703 | } | |
09d92015 | 7704 | |
c19d1205 ZW |
7705 | /* Transfer between coprocessor register and pair of ARM registers. |
7706 | MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. | |
7707 | MCRR2 | |
7708 | MRRC{cond} | |
7709 | MRRC2 | |
b99bd4ef | 7710 | |
c19d1205 | 7711 | Two XScale instructions are special cases of these: |
09d92015 | 7712 | |
c19d1205 ZW |
7713 | MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 |
7714 | MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 | |
b99bd4ef | 7715 | |
5f4273c7 | 7716 | Result unpredictable if Rd or Rn is R15. */ |
a737bd4d | 7717 | |
c19d1205 ZW |
7718 | static void |
7719 | do_co_reg2c (void) | |
7720 | { | |
fdfde340 JM |
7721 | unsigned Rd, Rn; |
7722 | ||
7723 | Rd = inst.operands[2].reg; | |
7724 | Rn = inst.operands[3].reg; | |
7725 | ||
7726 | if (thumb_mode) | |
7727 | { | |
7728 | reject_bad_reg (Rd); | |
7729 | reject_bad_reg (Rn); | |
7730 | } | |
7731 | else | |
7732 | { | |
7733 | constraint (Rd == REG_PC, BAD_PC); | |
7734 | constraint (Rn == REG_PC, BAD_PC); | |
7735 | } | |
7736 | ||
c19d1205 ZW |
7737 | inst.instruction |= inst.operands[0].reg << 8; |
7738 | inst.instruction |= inst.operands[1].imm << 4; | |
fdfde340 JM |
7739 | inst.instruction |= Rd << 12; |
7740 | inst.instruction |= Rn << 16; | |
c19d1205 | 7741 | inst.instruction |= inst.operands[4].reg; |
b99bd4ef NC |
7742 | } |
7743 | ||
c19d1205 ZW |
7744 | static void |
7745 | do_cpsi (void) | |
7746 | { | |
7747 | inst.instruction |= inst.operands[0].imm << 6; | |
a028a6f5 PB |
7748 | if (inst.operands[1].present) |
7749 | { | |
7750 | inst.instruction |= CPSI_MMOD; | |
7751 | inst.instruction |= inst.operands[1].imm; | |
7752 | } | |
c19d1205 | 7753 | } |
b99bd4ef | 7754 | |
62b3e311 PB |
7755 | static void |
7756 | do_dbg (void) | |
7757 | { | |
7758 | inst.instruction |= inst.operands[0].imm; | |
7759 | } | |
7760 | ||
eea54501 MGD |
7761 | static void |
7762 | do_div (void) | |
7763 | { | |
7764 | unsigned Rd, Rn, Rm; | |
7765 | ||
7766 | Rd = inst.operands[0].reg; | |
7767 | Rn = (inst.operands[1].present | |
7768 | ? inst.operands[1].reg : Rd); | |
7769 | Rm = inst.operands[2].reg; | |
7770 | ||
7771 | constraint ((Rd == REG_PC), BAD_PC); | |
7772 | constraint ((Rn == REG_PC), BAD_PC); | |
7773 | constraint ((Rm == REG_PC), BAD_PC); | |
7774 | ||
7775 | inst.instruction |= Rd << 16; | |
7776 | inst.instruction |= Rn << 0; | |
7777 | inst.instruction |= Rm << 8; | |
7778 | } | |
7779 | ||
b99bd4ef | 7780 | static void |
c19d1205 | 7781 | do_it (void) |
b99bd4ef | 7782 | { |
c19d1205 | 7783 | /* There is no IT instruction in ARM mode. We |
e07e6e58 NC |
7784 | process it to do the validation as if in |
7785 | thumb mode, just in case the code gets | |
7786 | assembled for thumb using the unified syntax. */ | |
7787 | ||
c19d1205 | 7788 | inst.size = 0; |
e07e6e58 NC |
7789 | if (unified_syntax) |
7790 | { | |
7791 | set_it_insn_type (IT_INSN); | |
7792 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
7793 | now_it.cc = inst.operands[0].imm; | |
7794 | } | |
09d92015 | 7795 | } |
b99bd4ef | 7796 | |
09d92015 | 7797 | static void |
c19d1205 | 7798 | do_ldmstm (void) |
ea6ef066 | 7799 | { |
c19d1205 ZW |
7800 | int base_reg = inst.operands[0].reg; |
7801 | int range = inst.operands[1].imm; | |
ea6ef066 | 7802 | |
c19d1205 ZW |
7803 | inst.instruction |= base_reg << 16; |
7804 | inst.instruction |= range; | |
ea6ef066 | 7805 | |
c19d1205 ZW |
7806 | if (inst.operands[1].writeback) |
7807 | inst.instruction |= LDM_TYPE_2_OR_3; | |
09d92015 | 7808 | |
c19d1205 | 7809 | if (inst.operands[0].writeback) |
ea6ef066 | 7810 | { |
c19d1205 ZW |
7811 | inst.instruction |= WRITE_BACK; |
7812 | /* Check for unpredictable uses of writeback. */ | |
7813 | if (inst.instruction & LOAD_BIT) | |
09d92015 | 7814 | { |
c19d1205 ZW |
7815 | /* Not allowed in LDM type 2. */ |
7816 | if ((inst.instruction & LDM_TYPE_2_OR_3) | |
7817 | && ((range & (1 << REG_PC)) == 0)) | |
7818 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7819 | /* Only allowed if base reg not in list for other types. */ | |
7820 | else if (range & (1 << base_reg)) | |
7821 | as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); | |
7822 | } | |
7823 | else /* STM. */ | |
7824 | { | |
7825 | /* Not allowed for type 2. */ | |
7826 | if (inst.instruction & LDM_TYPE_2_OR_3) | |
7827 | as_warn (_("writeback of base register is UNPREDICTABLE")); | |
7828 | /* Only allowed if base reg not in list, or first in list. */ | |
7829 | else if ((range & (1 << base_reg)) | |
7830 | && (range & ((1 << base_reg) - 1))) | |
7831 | as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); | |
09d92015 | 7832 | } |
ea6ef066 | 7833 | } |
a737bd4d NC |
7834 | } |
7835 | ||
c19d1205 ZW |
7836 | /* ARMv5TE load-consecutive (argument parse) |
7837 | Mode is like LDRH. | |
7838 | ||
7839 | LDRccD R, mode | |
7840 | STRccD R, mode. */ | |
7841 | ||
a737bd4d | 7842 | static void |
c19d1205 | 7843 | do_ldrd (void) |
a737bd4d | 7844 | { |
c19d1205 | 7845 | constraint (inst.operands[0].reg % 2 != 0, |
c56791bb | 7846 | _("first transfer register must be even")); |
c19d1205 ZW |
7847 | constraint (inst.operands[1].present |
7848 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
c56791bb | 7849 | _("can only transfer two consecutive registers")); |
c19d1205 ZW |
7850 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); |
7851 | constraint (!inst.operands[2].isreg, _("'[' expected")); | |
a737bd4d | 7852 | |
c19d1205 ZW |
7853 | if (!inst.operands[1].present) |
7854 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
5f4273c7 | 7855 | |
c56791bb RE |
7856 | /* encode_arm_addr_mode_3 will diagnose overlap between the base |
7857 | register and the first register written; we have to diagnose | |
7858 | overlap between the base and the second register written here. */ | |
ea6ef066 | 7859 | |
c56791bb RE |
7860 | if (inst.operands[2].reg == inst.operands[1].reg |
7861 | && (inst.operands[2].writeback || inst.operands[2].postind)) | |
7862 | as_warn (_("base register written back, and overlaps " | |
7863 | "second transfer register")); | |
b05fe5cf | 7864 | |
c56791bb RE |
7865 | if (!(inst.instruction & V4_STR_BIT)) |
7866 | { | |
c19d1205 | 7867 | /* For an index-register load, the index register must not overlap the |
c56791bb RE |
7868 | destination (even if not write-back). */ |
7869 | if (inst.operands[2].immisreg | |
7870 | && ((unsigned) inst.operands[2].imm == inst.operands[0].reg | |
7871 | || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) | |
7872 | as_warn (_("index register overlaps transfer register")); | |
b05fe5cf | 7873 | } |
c19d1205 ZW |
7874 | inst.instruction |= inst.operands[0].reg << 12; |
7875 | encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); | |
b05fe5cf ZW |
7876 | } |
7877 | ||
7878 | static void | |
c19d1205 | 7879 | do_ldrex (void) |
b05fe5cf | 7880 | { |
c19d1205 ZW |
7881 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind |
7882 | || inst.operands[1].postind || inst.operands[1].writeback | |
7883 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
01cfc07f NC |
7884 | || inst.operands[1].negative |
7885 | /* This can arise if the programmer has written | |
7886 | strex rN, rM, foo | |
7887 | or if they have mistakenly used a register name as the last | |
7888 | operand, eg: | |
7889 | strex rN, rM, rX | |
7890 | It is very difficult to distinguish between these two cases | |
7891 | because "rX" might actually be a label. ie the register | |
7892 | name has been occluded by a symbol of the same name. So we | |
7893 | just generate a general 'bad addressing mode' type error | |
7894 | message and leave it up to the programmer to discover the | |
7895 | true cause and fix their mistake. */ | |
7896 | || (inst.operands[1].reg == REG_PC), | |
7897 | BAD_ADDR_MODE); | |
b05fe5cf | 7898 | |
c19d1205 ZW |
7899 | constraint (inst.reloc.exp.X_op != O_constant |
7900 | || inst.reloc.exp.X_add_number != 0, | |
7901 | _("offset must be zero in ARM encoding")); | |
b05fe5cf | 7902 | |
5be8be5d DG |
7903 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
7904 | ||
c19d1205 ZW |
7905 | inst.instruction |= inst.operands[0].reg << 12; |
7906 | inst.instruction |= inst.operands[1].reg << 16; | |
7907 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b05fe5cf ZW |
7908 | } |
7909 | ||
7910 | static void | |
c19d1205 | 7911 | do_ldrexd (void) |
b05fe5cf | 7912 | { |
c19d1205 ZW |
7913 | constraint (inst.operands[0].reg % 2 != 0, |
7914 | _("even register required")); | |
7915 | constraint (inst.operands[1].present | |
7916 | && inst.operands[1].reg != inst.operands[0].reg + 1, | |
7917 | _("can only load two consecutive registers")); | |
7918 | /* If op 1 were present and equal to PC, this function wouldn't | |
7919 | have been called in the first place. */ | |
7920 | constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); | |
b05fe5cf | 7921 | |
c19d1205 ZW |
7922 | inst.instruction |= inst.operands[0].reg << 12; |
7923 | inst.instruction |= inst.operands[2].reg << 16; | |
b05fe5cf ZW |
7924 | } |
7925 | ||
1be5fd2e NC |
7926 | /* In both ARM and thumb state 'ldr pc, #imm' with an immediate |
7927 | which is not a multiple of four is UNPREDICTABLE. */ | |
7928 | static void | |
7929 | check_ldr_r15_aligned (void) | |
7930 | { | |
7931 | constraint (!(inst.operands[1].immisreg) | |
7932 | && (inst.operands[0].reg == REG_PC | |
7933 | && inst.operands[1].reg == REG_PC | |
7934 | && (inst.reloc.exp.X_add_number & 0x3)), | |
7935 | _("ldr to register 15 must be 4-byte alligned")); | |
7936 | } | |
7937 | ||
b05fe5cf | 7938 | static void |
c19d1205 | 7939 | do_ldst (void) |
b05fe5cf | 7940 | { |
c19d1205 ZW |
7941 | inst.instruction |= inst.operands[0].reg << 12; |
7942 | if (!inst.operands[1].isreg) | |
7943 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) | |
b05fe5cf | 7944 | return; |
c19d1205 | 7945 | encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); |
1be5fd2e | 7946 | check_ldr_r15_aligned (); |
b05fe5cf ZW |
7947 | } |
7948 | ||
7949 | static void | |
c19d1205 | 7950 | do_ldstt (void) |
b05fe5cf | 7951 | { |
c19d1205 ZW |
7952 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7953 | reject [Rn,...]. */ | |
7954 | if (inst.operands[1].preind) | |
b05fe5cf | 7955 | { |
bd3ba5d1 NC |
7956 | constraint (inst.reloc.exp.X_op != O_constant |
7957 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7958 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7959 | |
c19d1205 ZW |
7960 | inst.operands[1].preind = 0; |
7961 | inst.operands[1].postind = 1; | |
7962 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7963 | } |
c19d1205 ZW |
7964 | inst.instruction |= inst.operands[0].reg << 12; |
7965 | encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); | |
7966 | } | |
b05fe5cf | 7967 | |
c19d1205 | 7968 | /* Halfword and signed-byte load/store operations. */ |
b05fe5cf | 7969 | |
c19d1205 ZW |
7970 | static void |
7971 | do_ldstv4 (void) | |
7972 | { | |
ff4a8d2b | 7973 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 ZW |
7974 | inst.instruction |= inst.operands[0].reg << 12; |
7975 | if (!inst.operands[1].isreg) | |
7976 | if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) | |
b05fe5cf | 7977 | return; |
c19d1205 | 7978 | encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); |
b05fe5cf ZW |
7979 | } |
7980 | ||
7981 | static void | |
c19d1205 | 7982 | do_ldsttv4 (void) |
b05fe5cf | 7983 | { |
c19d1205 ZW |
7984 | /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and |
7985 | reject [Rn,...]. */ | |
7986 | if (inst.operands[1].preind) | |
b05fe5cf | 7987 | { |
bd3ba5d1 NC |
7988 | constraint (inst.reloc.exp.X_op != O_constant |
7989 | || inst.reloc.exp.X_add_number != 0, | |
c19d1205 | 7990 | _("this instruction requires a post-indexed address")); |
b05fe5cf | 7991 | |
c19d1205 ZW |
7992 | inst.operands[1].preind = 0; |
7993 | inst.operands[1].postind = 1; | |
7994 | inst.operands[1].writeback = 1; | |
b05fe5cf | 7995 | } |
c19d1205 ZW |
7996 | inst.instruction |= inst.operands[0].reg << 12; |
7997 | encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); | |
7998 | } | |
b05fe5cf | 7999 | |
c19d1205 ZW |
8000 | /* Co-processor register load/store. |
8001 | Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ | |
8002 | static void | |
8003 | do_lstc (void) | |
8004 | { | |
8005 | inst.instruction |= inst.operands[0].reg << 8; | |
8006 | inst.instruction |= inst.operands[1].reg << 12; | |
8007 | encode_arm_cp_address (2, TRUE, TRUE, 0); | |
b05fe5cf ZW |
8008 | } |
8009 | ||
b05fe5cf | 8010 | static void |
c19d1205 | 8011 | do_mlas (void) |
b05fe5cf | 8012 | { |
8fb9d7b9 | 8013 | /* This restriction does not apply to mls (nor to mla in v6 or later). */ |
c19d1205 | 8014 | if (inst.operands[0].reg == inst.operands[1].reg |
8fb9d7b9 | 8015 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) |
c19d1205 | 8016 | && !(inst.instruction & 0x00400000)) |
8fb9d7b9 | 8017 | as_tsktsk (_("Rd and Rm should be different in mla")); |
b05fe5cf | 8018 | |
c19d1205 ZW |
8019 | inst.instruction |= inst.operands[0].reg << 16; |
8020 | inst.instruction |= inst.operands[1].reg; | |
8021 | inst.instruction |= inst.operands[2].reg << 8; | |
8022 | inst.instruction |= inst.operands[3].reg << 12; | |
c19d1205 | 8023 | } |
b05fe5cf | 8024 | |
c19d1205 ZW |
8025 | static void |
8026 | do_mov (void) | |
8027 | { | |
8028 | inst.instruction |= inst.operands[0].reg << 12; | |
8029 | encode_arm_shifter_operand (1); | |
8030 | } | |
b05fe5cf | 8031 | |
c19d1205 ZW |
8032 | /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ |
8033 | static void | |
8034 | do_mov16 (void) | |
8035 | { | |
b6895b4f PB |
8036 | bfd_vma imm; |
8037 | bfd_boolean top; | |
8038 | ||
8039 | top = (inst.instruction & 0x00400000) != 0; | |
8040 | constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, | |
8041 | _(":lower16: not allowed this instruction")); | |
8042 | constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, | |
8043 | _(":upper16: not allowed instruction")); | |
c19d1205 | 8044 | inst.instruction |= inst.operands[0].reg << 12; |
b6895b4f PB |
8045 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
8046 | { | |
8047 | imm = inst.reloc.exp.X_add_number; | |
8048 | /* The value is in two pieces: 0:11, 16:19. */ | |
8049 | inst.instruction |= (imm & 0x00000fff); | |
8050 | inst.instruction |= (imm & 0x0000f000) << 4; | |
8051 | } | |
b05fe5cf | 8052 | } |
b99bd4ef | 8053 | |
037e8744 JB |
8054 | static void do_vfp_nsyn_opcode (const char *); |
8055 | ||
8056 | static int | |
8057 | do_vfp_nsyn_mrs (void) | |
8058 | { | |
8059 | if (inst.operands[0].isvec) | |
8060 | { | |
8061 | if (inst.operands[1].reg != 1) | |
8062 | first_error (_("operand 1 must be FPSCR")); | |
8063 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
8064 | memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); | |
8065 | do_vfp_nsyn_opcode ("fmstat"); | |
8066 | } | |
8067 | else if (inst.operands[1].isvec) | |
8068 | do_vfp_nsyn_opcode ("fmrx"); | |
8069 | else | |
8070 | return FAIL; | |
5f4273c7 | 8071 | |
037e8744 JB |
8072 | return SUCCESS; |
8073 | } | |
8074 | ||
8075 | static int | |
8076 | do_vfp_nsyn_msr (void) | |
8077 | { | |
8078 | if (inst.operands[0].isvec) | |
8079 | do_vfp_nsyn_opcode ("fmxr"); | |
8080 | else | |
8081 | return FAIL; | |
8082 | ||
8083 | return SUCCESS; | |
8084 | } | |
8085 | ||
f7c21dc7 NC |
8086 | static void |
8087 | do_vmrs (void) | |
8088 | { | |
8089 | unsigned Rt = inst.operands[0].reg; | |
8090 | ||
8091 | if (thumb_mode && inst.operands[0].reg == REG_SP) | |
8092 | { | |
8093 | inst.error = BAD_SP; | |
8094 | return; | |
8095 | } | |
8096 | ||
8097 | /* APSR_ sets isvec. All other refs to PC are illegal. */ | |
8098 | if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC) | |
8099 | { | |
8100 | inst.error = BAD_PC; | |
8101 | return; | |
8102 | } | |
8103 | ||
8104 | if (inst.operands[1].reg != 1) | |
8105 | first_error (_("operand 1 must be FPSCR")); | |
8106 | ||
8107 | inst.instruction |= (Rt << 12); | |
8108 | } | |
8109 | ||
8110 | static void | |
8111 | do_vmsr (void) | |
8112 | { | |
8113 | unsigned Rt = inst.operands[1].reg; | |
8114 | ||
8115 | if (thumb_mode) | |
8116 | reject_bad_reg (Rt); | |
8117 | else if (Rt == REG_PC) | |
8118 | { | |
8119 | inst.error = BAD_PC; | |
8120 | return; | |
8121 | } | |
8122 | ||
8123 | if (inst.operands[0].reg != 1) | |
8124 | first_error (_("operand 0 must be FPSCR")); | |
8125 | ||
8126 | inst.instruction |= (Rt << 12); | |
8127 | } | |
8128 | ||
b99bd4ef | 8129 | static void |
c19d1205 | 8130 | do_mrs (void) |
b99bd4ef | 8131 | { |
90ec0d68 MGD |
8132 | unsigned br; |
8133 | ||
037e8744 JB |
8134 | if (do_vfp_nsyn_mrs () == SUCCESS) |
8135 | return; | |
8136 | ||
ff4a8d2b | 8137 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); |
c19d1205 | 8138 | inst.instruction |= inst.operands[0].reg << 12; |
90ec0d68 MGD |
8139 | |
8140 | if (inst.operands[1].isreg) | |
8141 | { | |
8142 | br = inst.operands[1].reg; | |
8143 | if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000)) | |
8144 | as_bad (_("bad register for mrs")); | |
8145 | } | |
8146 | else | |
8147 | { | |
8148 | /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ | |
8149 | constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) | |
8150 | != (PSR_c|PSR_f), | |
d2cd1205 | 8151 | _("'APSR', 'CPSR' or 'SPSR' expected")); |
90ec0d68 MGD |
8152 | br = (15<<16) | (inst.operands[1].imm & SPSR_BIT); |
8153 | } | |
8154 | ||
8155 | inst.instruction |= br; | |
c19d1205 | 8156 | } |
b99bd4ef | 8157 | |
c19d1205 ZW |
8158 | /* Two possible forms: |
8159 | "{C|S}PSR_<field>, Rm", | |
8160 | "{C|S}PSR_f, #expression". */ | |
b99bd4ef | 8161 | |
c19d1205 ZW |
8162 | static void |
8163 | do_msr (void) | |
8164 | { | |
037e8744 JB |
8165 | if (do_vfp_nsyn_msr () == SUCCESS) |
8166 | return; | |
8167 | ||
c19d1205 ZW |
8168 | inst.instruction |= inst.operands[0].imm; |
8169 | if (inst.operands[1].isreg) | |
8170 | inst.instruction |= inst.operands[1].reg; | |
8171 | else | |
b99bd4ef | 8172 | { |
c19d1205 ZW |
8173 | inst.instruction |= INST_IMMEDIATE; |
8174 | inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; | |
8175 | inst.reloc.pc_rel = 0; | |
b99bd4ef | 8176 | } |
b99bd4ef NC |
8177 | } |
8178 | ||
c19d1205 ZW |
8179 | static void |
8180 | do_mul (void) | |
a737bd4d | 8181 | { |
ff4a8d2b NC |
8182 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
8183 | ||
c19d1205 ZW |
8184 | if (!inst.operands[2].present) |
8185 | inst.operands[2].reg = inst.operands[0].reg; | |
8186 | inst.instruction |= inst.operands[0].reg << 16; | |
8187 | inst.instruction |= inst.operands[1].reg; | |
8188 | inst.instruction |= inst.operands[2].reg << 8; | |
a737bd4d | 8189 | |
8fb9d7b9 MS |
8190 | if (inst.operands[0].reg == inst.operands[1].reg |
8191 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) | |
8192 | as_tsktsk (_("Rd and Rm should be different in mul")); | |
a737bd4d NC |
8193 | } |
8194 | ||
c19d1205 ZW |
8195 | /* Long Multiply Parser |
8196 | UMULL RdLo, RdHi, Rm, Rs | |
8197 | SMULL RdLo, RdHi, Rm, Rs | |
8198 | UMLAL RdLo, RdHi, Rm, Rs | |
8199 | SMLAL RdLo, RdHi, Rm, Rs. */ | |
b99bd4ef NC |
8200 | |
8201 | static void | |
c19d1205 | 8202 | do_mull (void) |
b99bd4ef | 8203 | { |
c19d1205 ZW |
8204 | inst.instruction |= inst.operands[0].reg << 12; |
8205 | inst.instruction |= inst.operands[1].reg << 16; | |
8206 | inst.instruction |= inst.operands[2].reg; | |
8207 | inst.instruction |= inst.operands[3].reg << 8; | |
b99bd4ef | 8208 | |
682b27ad PB |
8209 | /* rdhi and rdlo must be different. */ |
8210 | if (inst.operands[0].reg == inst.operands[1].reg) | |
8211 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8212 | ||
8213 | /* rdhi, rdlo and rm must all be different before armv6. */ | |
8214 | if ((inst.operands[0].reg == inst.operands[2].reg | |
c19d1205 | 8215 | || inst.operands[1].reg == inst.operands[2].reg) |
682b27ad | 8216 | && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) |
c19d1205 ZW |
8217 | as_tsktsk (_("rdhi, rdlo and rm must all be different")); |
8218 | } | |
b99bd4ef | 8219 | |
c19d1205 ZW |
8220 | static void |
8221 | do_nop (void) | |
8222 | { | |
e7495e45 NS |
8223 | if (inst.operands[0].present |
8224 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k)) | |
c19d1205 ZW |
8225 | { |
8226 | /* Architectural NOP hints are CPSR sets with no bits selected. */ | |
8227 | inst.instruction &= 0xf0000000; | |
e7495e45 NS |
8228 | inst.instruction |= 0x0320f000; |
8229 | if (inst.operands[0].present) | |
8230 | inst.instruction |= inst.operands[0].imm; | |
c19d1205 | 8231 | } |
b99bd4ef NC |
8232 | } |
8233 | ||
c19d1205 ZW |
8234 | /* ARM V6 Pack Halfword Bottom Top instruction (argument parse). |
8235 | PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} | |
8236 | Condition defaults to COND_ALWAYS. | |
8237 | Error if Rd, Rn or Rm are R15. */ | |
b99bd4ef NC |
8238 | |
8239 | static void | |
c19d1205 | 8240 | do_pkhbt (void) |
b99bd4ef | 8241 | { |
c19d1205 ZW |
8242 | inst.instruction |= inst.operands[0].reg << 12; |
8243 | inst.instruction |= inst.operands[1].reg << 16; | |
8244 | inst.instruction |= inst.operands[2].reg; | |
8245 | if (inst.operands[3].present) | |
8246 | encode_arm_shift (3); | |
8247 | } | |
b99bd4ef | 8248 | |
c19d1205 | 8249 | /* ARM V6 PKHTB (Argument Parse). */ |
b99bd4ef | 8250 | |
c19d1205 ZW |
8251 | static void |
8252 | do_pkhtb (void) | |
8253 | { | |
8254 | if (!inst.operands[3].present) | |
b99bd4ef | 8255 | { |
c19d1205 ZW |
8256 | /* If the shift specifier is omitted, turn the instruction |
8257 | into pkhbt rd, rm, rn. */ | |
8258 | inst.instruction &= 0xfff00010; | |
8259 | inst.instruction |= inst.operands[0].reg << 12; | |
8260 | inst.instruction |= inst.operands[1].reg; | |
8261 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
8262 | } |
8263 | else | |
8264 | { | |
c19d1205 ZW |
8265 | inst.instruction |= inst.operands[0].reg << 12; |
8266 | inst.instruction |= inst.operands[1].reg << 16; | |
8267 | inst.instruction |= inst.operands[2].reg; | |
8268 | encode_arm_shift (3); | |
b99bd4ef NC |
8269 | } |
8270 | } | |
8271 | ||
c19d1205 | 8272 | /* ARMv5TE: Preload-Cache |
60e5ef9f | 8273 | MP Extensions: Preload for write |
c19d1205 | 8274 | |
60e5ef9f | 8275 | PLD(W) <addr_mode> |
c19d1205 ZW |
8276 | |
8277 | Syntactically, like LDR with B=1, W=0, L=1. */ | |
b99bd4ef NC |
8278 | |
8279 | static void | |
c19d1205 | 8280 | do_pld (void) |
b99bd4ef | 8281 | { |
c19d1205 ZW |
8282 | constraint (!inst.operands[0].isreg, |
8283 | _("'[' expected after PLD mnemonic")); | |
8284 | constraint (inst.operands[0].postind, | |
8285 | _("post-indexed expression used in preload instruction")); | |
8286 | constraint (inst.operands[0].writeback, | |
8287 | _("writeback used in preload instruction")); | |
8288 | constraint (!inst.operands[0].preind, | |
8289 | _("unindexed addressing used in preload instruction")); | |
c19d1205 ZW |
8290 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); |
8291 | } | |
b99bd4ef | 8292 | |
62b3e311 PB |
8293 | /* ARMv7: PLI <addr_mode> */ |
8294 | static void | |
8295 | do_pli (void) | |
8296 | { | |
8297 | constraint (!inst.operands[0].isreg, | |
8298 | _("'[' expected after PLI mnemonic")); | |
8299 | constraint (inst.operands[0].postind, | |
8300 | _("post-indexed expression used in preload instruction")); | |
8301 | constraint (inst.operands[0].writeback, | |
8302 | _("writeback used in preload instruction")); | |
8303 | constraint (!inst.operands[0].preind, | |
8304 | _("unindexed addressing used in preload instruction")); | |
8305 | encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); | |
8306 | inst.instruction &= ~PRE_INDEX; | |
8307 | } | |
8308 | ||
c19d1205 ZW |
8309 | static void |
8310 | do_push_pop (void) | |
8311 | { | |
8312 | inst.operands[1] = inst.operands[0]; | |
8313 | memset (&inst.operands[0], 0, sizeof inst.operands[0]); | |
8314 | inst.operands[0].isreg = 1; | |
8315 | inst.operands[0].writeback = 1; | |
8316 | inst.operands[0].reg = REG_SP; | |
8317 | do_ldmstm (); | |
8318 | } | |
b99bd4ef | 8319 | |
c19d1205 ZW |
8320 | /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the |
8321 | word at the specified address and the following word | |
8322 | respectively. | |
8323 | Unconditionally executed. | |
8324 | Error if Rn is R15. */ | |
b99bd4ef | 8325 | |
c19d1205 ZW |
8326 | static void |
8327 | do_rfe (void) | |
8328 | { | |
8329 | inst.instruction |= inst.operands[0].reg << 16; | |
8330 | if (inst.operands[0].writeback) | |
8331 | inst.instruction |= WRITE_BACK; | |
8332 | } | |
b99bd4ef | 8333 | |
c19d1205 | 8334 | /* ARM V6 ssat (argument parse). */ |
b99bd4ef | 8335 | |
c19d1205 ZW |
8336 | static void |
8337 | do_ssat (void) | |
8338 | { | |
8339 | inst.instruction |= inst.operands[0].reg << 12; | |
8340 | inst.instruction |= (inst.operands[1].imm - 1) << 16; | |
8341 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8342 | |
c19d1205 ZW |
8343 | if (inst.operands[3].present) |
8344 | encode_arm_shift (3); | |
b99bd4ef NC |
8345 | } |
8346 | ||
c19d1205 | 8347 | /* ARM V6 usat (argument parse). */ |
b99bd4ef NC |
8348 | |
8349 | static void | |
c19d1205 | 8350 | do_usat (void) |
b99bd4ef | 8351 | { |
c19d1205 ZW |
8352 | inst.instruction |= inst.operands[0].reg << 12; |
8353 | inst.instruction |= inst.operands[1].imm << 16; | |
8354 | inst.instruction |= inst.operands[2].reg; | |
b99bd4ef | 8355 | |
c19d1205 ZW |
8356 | if (inst.operands[3].present) |
8357 | encode_arm_shift (3); | |
b99bd4ef NC |
8358 | } |
8359 | ||
c19d1205 | 8360 | /* ARM V6 ssat16 (argument parse). */ |
09d92015 MM |
8361 | |
8362 | static void | |
c19d1205 | 8363 | do_ssat16 (void) |
09d92015 | 8364 | { |
c19d1205 ZW |
8365 | inst.instruction |= inst.operands[0].reg << 12; |
8366 | inst.instruction |= ((inst.operands[1].imm - 1) << 16); | |
8367 | inst.instruction |= inst.operands[2].reg; | |
09d92015 MM |
8368 | } |
8369 | ||
c19d1205 ZW |
8370 | static void |
8371 | do_usat16 (void) | |
a737bd4d | 8372 | { |
c19d1205 ZW |
8373 | inst.instruction |= inst.operands[0].reg << 12; |
8374 | inst.instruction |= inst.operands[1].imm << 16; | |
8375 | inst.instruction |= inst.operands[2].reg; | |
8376 | } | |
a737bd4d | 8377 | |
c19d1205 ZW |
8378 | /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while |
8379 | preserving the other bits. | |
a737bd4d | 8380 | |
c19d1205 ZW |
8381 | setend <endian_specifier>, where <endian_specifier> is either |
8382 | BE or LE. */ | |
a737bd4d | 8383 | |
c19d1205 ZW |
8384 | static void |
8385 | do_setend (void) | |
8386 | { | |
8387 | if (inst.operands[0].imm) | |
8388 | inst.instruction |= 0x200; | |
a737bd4d NC |
8389 | } |
8390 | ||
8391 | static void | |
c19d1205 | 8392 | do_shift (void) |
a737bd4d | 8393 | { |
c19d1205 ZW |
8394 | unsigned int Rm = (inst.operands[1].present |
8395 | ? inst.operands[1].reg | |
8396 | : inst.operands[0].reg); | |
a737bd4d | 8397 | |
c19d1205 ZW |
8398 | inst.instruction |= inst.operands[0].reg << 12; |
8399 | inst.instruction |= Rm; | |
8400 | if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ | |
a737bd4d | 8401 | { |
c19d1205 ZW |
8402 | inst.instruction |= inst.operands[2].reg << 8; |
8403 | inst.instruction |= SHIFT_BY_REG; | |
94342ec3 NC |
8404 | /* PR 12854: Error on extraneous shifts. */ |
8405 | constraint (inst.operands[2].shifted, | |
8406 | _("extraneous shift as part of operand to shift insn")); | |
a737bd4d NC |
8407 | } |
8408 | else | |
c19d1205 | 8409 | inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; |
a737bd4d NC |
8410 | } |
8411 | ||
09d92015 | 8412 | static void |
3eb17e6b | 8413 | do_smc (void) |
09d92015 | 8414 | { |
3eb17e6b | 8415 | inst.reloc.type = BFD_RELOC_ARM_SMC; |
c19d1205 | 8416 | inst.reloc.pc_rel = 0; |
09d92015 MM |
8417 | } |
8418 | ||
90ec0d68 MGD |
8419 | static void |
8420 | do_hvc (void) | |
8421 | { | |
8422 | inst.reloc.type = BFD_RELOC_ARM_HVC; | |
8423 | inst.reloc.pc_rel = 0; | |
8424 | } | |
8425 | ||
09d92015 | 8426 | static void |
c19d1205 | 8427 | do_swi (void) |
09d92015 | 8428 | { |
c19d1205 ZW |
8429 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
8430 | inst.reloc.pc_rel = 0; | |
09d92015 MM |
8431 | } |
8432 | ||
c19d1205 ZW |
8433 | /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) |
8434 | SMLAxy{cond} Rd,Rm,Rs,Rn | |
8435 | SMLAWy{cond} Rd,Rm,Rs,Rn | |
8436 | Error if any register is R15. */ | |
e16bb312 | 8437 | |
c19d1205 ZW |
8438 | static void |
8439 | do_smla (void) | |
e16bb312 | 8440 | { |
c19d1205 ZW |
8441 | inst.instruction |= inst.operands[0].reg << 16; |
8442 | inst.instruction |= inst.operands[1].reg; | |
8443 | inst.instruction |= inst.operands[2].reg << 8; | |
8444 | inst.instruction |= inst.operands[3].reg << 12; | |
8445 | } | |
a737bd4d | 8446 | |
c19d1205 ZW |
8447 | /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) |
8448 | SMLALxy{cond} Rdlo,Rdhi,Rm,Rs | |
8449 | Error if any register is R15. | |
8450 | Warning if Rdlo == Rdhi. */ | |
a737bd4d | 8451 | |
c19d1205 ZW |
8452 | static void |
8453 | do_smlal (void) | |
8454 | { | |
8455 | inst.instruction |= inst.operands[0].reg << 12; | |
8456 | inst.instruction |= inst.operands[1].reg << 16; | |
8457 | inst.instruction |= inst.operands[2].reg; | |
8458 | inst.instruction |= inst.operands[3].reg << 8; | |
a737bd4d | 8459 | |
c19d1205 ZW |
8460 | if (inst.operands[0].reg == inst.operands[1].reg) |
8461 | as_tsktsk (_("rdhi and rdlo must be different")); | |
8462 | } | |
a737bd4d | 8463 | |
c19d1205 ZW |
8464 | /* ARM V5E (El Segundo) signed-multiply (argument parse) |
8465 | SMULxy{cond} Rd,Rm,Rs | |
8466 | Error if any register is R15. */ | |
a737bd4d | 8467 | |
c19d1205 ZW |
8468 | static void |
8469 | do_smul (void) | |
8470 | { | |
8471 | inst.instruction |= inst.operands[0].reg << 16; | |
8472 | inst.instruction |= inst.operands[1].reg; | |
8473 | inst.instruction |= inst.operands[2].reg << 8; | |
8474 | } | |
a737bd4d | 8475 | |
b6702015 PB |
8476 | /* ARM V6 srs (argument parse). The variable fields in the encoding are |
8477 | the same for both ARM and Thumb-2. */ | |
a737bd4d | 8478 | |
c19d1205 ZW |
8479 | static void |
8480 | do_srs (void) | |
8481 | { | |
b6702015 PB |
8482 | int reg; |
8483 | ||
8484 | if (inst.operands[0].present) | |
8485 | { | |
8486 | reg = inst.operands[0].reg; | |
fdfde340 | 8487 | constraint (reg != REG_SP, _("SRS base register must be r13")); |
b6702015 PB |
8488 | } |
8489 | else | |
fdfde340 | 8490 | reg = REG_SP; |
b6702015 PB |
8491 | |
8492 | inst.instruction |= reg << 16; | |
8493 | inst.instruction |= inst.operands[1].imm; | |
8494 | if (inst.operands[0].writeback || inst.operands[1].writeback) | |
c19d1205 ZW |
8495 | inst.instruction |= WRITE_BACK; |
8496 | } | |
a737bd4d | 8497 | |
c19d1205 | 8498 | /* ARM V6 strex (argument parse). */ |
a737bd4d | 8499 | |
c19d1205 ZW |
8500 | static void |
8501 | do_strex (void) | |
8502 | { | |
8503 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
8504 | || inst.operands[2].postind || inst.operands[2].writeback | |
8505 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
01cfc07f NC |
8506 | || inst.operands[2].negative |
8507 | /* See comment in do_ldrex(). */ | |
8508 | || (inst.operands[2].reg == REG_PC), | |
8509 | BAD_ADDR_MODE); | |
a737bd4d | 8510 | |
c19d1205 ZW |
8511 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8512 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
a737bd4d | 8513 | |
c19d1205 ZW |
8514 | constraint (inst.reloc.exp.X_op != O_constant |
8515 | || inst.reloc.exp.X_add_number != 0, | |
8516 | _("offset must be zero in ARM encoding")); | |
a737bd4d | 8517 | |
c19d1205 ZW |
8518 | inst.instruction |= inst.operands[0].reg << 12; |
8519 | inst.instruction |= inst.operands[1].reg; | |
8520 | inst.instruction |= inst.operands[2].reg << 16; | |
8521 | inst.reloc.type = BFD_RELOC_UNUSED; | |
e16bb312 NC |
8522 | } |
8523 | ||
877807f8 NC |
8524 | static void |
8525 | do_t_strexbh (void) | |
8526 | { | |
8527 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
8528 | || inst.operands[2].postind || inst.operands[2].writeback | |
8529 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
8530 | || inst.operands[2].negative, | |
8531 | BAD_ADDR_MODE); | |
8532 | ||
8533 | constraint (inst.operands[0].reg == inst.operands[1].reg | |
8534 | || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); | |
8535 | ||
8536 | do_rm_rd_rn (); | |
8537 | } | |
8538 | ||
e16bb312 | 8539 | static void |
c19d1205 | 8540 | do_strexd (void) |
e16bb312 | 8541 | { |
c19d1205 ZW |
8542 | constraint (inst.operands[1].reg % 2 != 0, |
8543 | _("even register required")); | |
8544 | constraint (inst.operands[2].present | |
8545 | && inst.operands[2].reg != inst.operands[1].reg + 1, | |
8546 | _("can only store two consecutive registers")); | |
8547 | /* If op 2 were present and equal to PC, this function wouldn't | |
8548 | have been called in the first place. */ | |
8549 | constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); | |
e16bb312 | 8550 | |
c19d1205 ZW |
8551 | constraint (inst.operands[0].reg == inst.operands[1].reg |
8552 | || inst.operands[0].reg == inst.operands[1].reg + 1 | |
8553 | || inst.operands[0].reg == inst.operands[3].reg, | |
8554 | BAD_OVERLAP); | |
e16bb312 | 8555 | |
c19d1205 ZW |
8556 | inst.instruction |= inst.operands[0].reg << 12; |
8557 | inst.instruction |= inst.operands[1].reg; | |
8558 | inst.instruction |= inst.operands[3].reg << 16; | |
e16bb312 NC |
8559 | } |
8560 | ||
c19d1205 ZW |
8561 | /* ARM V6 SXTAH extracts a 16-bit value from a register, sign |
8562 | extends it to 32-bits, and adds the result to a value in another | |
8563 | register. You can specify a rotation by 0, 8, 16, or 24 bits | |
8564 | before extracting the 16-bit value. | |
8565 | SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} | |
8566 | Condition defaults to COND_ALWAYS. | |
8567 | Error if any register uses R15. */ | |
8568 | ||
e16bb312 | 8569 | static void |
c19d1205 | 8570 | do_sxtah (void) |
e16bb312 | 8571 | { |
c19d1205 ZW |
8572 | inst.instruction |= inst.operands[0].reg << 12; |
8573 | inst.instruction |= inst.operands[1].reg << 16; | |
8574 | inst.instruction |= inst.operands[2].reg; | |
8575 | inst.instruction |= inst.operands[3].imm << 10; | |
8576 | } | |
e16bb312 | 8577 | |
c19d1205 | 8578 | /* ARM V6 SXTH. |
e16bb312 | 8579 | |
c19d1205 ZW |
8580 | SXTH {<cond>} <Rd>, <Rm>{, <rotation>} |
8581 | Condition defaults to COND_ALWAYS. | |
8582 | Error if any register uses R15. */ | |
e16bb312 NC |
8583 | |
8584 | static void | |
c19d1205 | 8585 | do_sxth (void) |
e16bb312 | 8586 | { |
c19d1205 ZW |
8587 | inst.instruction |= inst.operands[0].reg << 12; |
8588 | inst.instruction |= inst.operands[1].reg; | |
8589 | inst.instruction |= inst.operands[2].imm << 10; | |
e16bb312 | 8590 | } |
c19d1205 ZW |
8591 | \f |
8592 | /* VFP instructions. In a logical order: SP variant first, monad | |
8593 | before dyad, arithmetic then move then load/store. */ | |
e16bb312 NC |
8594 | |
8595 | static void | |
c19d1205 | 8596 | do_vfp_sp_monadic (void) |
e16bb312 | 8597 | { |
5287ad62 JB |
8598 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8599 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8600 | } |
8601 | ||
8602 | static void | |
c19d1205 | 8603 | do_vfp_sp_dyadic (void) |
e16bb312 | 8604 | { |
5287ad62 JB |
8605 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8606 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); | |
8607 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); | |
e16bb312 NC |
8608 | } |
8609 | ||
8610 | static void | |
c19d1205 | 8611 | do_vfp_sp_compare_z (void) |
e16bb312 | 8612 | { |
5287ad62 | 8613 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
e16bb312 NC |
8614 | } |
8615 | ||
8616 | static void | |
c19d1205 | 8617 | do_vfp_dp_sp_cvt (void) |
e16bb312 | 8618 | { |
5287ad62 JB |
8619 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
8620 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
e16bb312 NC |
8621 | } |
8622 | ||
8623 | static void | |
c19d1205 | 8624 | do_vfp_sp_dp_cvt (void) |
e16bb312 | 8625 | { |
5287ad62 JB |
8626 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
8627 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
e16bb312 NC |
8628 | } |
8629 | ||
8630 | static void | |
c19d1205 | 8631 | do_vfp_reg_from_sp (void) |
e16bb312 | 8632 | { |
c19d1205 | 8633 | inst.instruction |= inst.operands[0].reg << 12; |
5287ad62 | 8634 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); |
e16bb312 NC |
8635 | } |
8636 | ||
8637 | static void | |
c19d1205 | 8638 | do_vfp_reg2_from_sp2 (void) |
e16bb312 | 8639 | { |
c19d1205 ZW |
8640 | constraint (inst.operands[2].imm != 2, |
8641 | _("only two consecutive VFP SP registers allowed here")); | |
8642 | inst.instruction |= inst.operands[0].reg << 12; | |
8643 | inst.instruction |= inst.operands[1].reg << 16; | |
5287ad62 | 8644 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); |
e16bb312 NC |
8645 | } |
8646 | ||
8647 | static void | |
c19d1205 | 8648 | do_vfp_sp_from_reg (void) |
e16bb312 | 8649 | { |
5287ad62 | 8650 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); |
c19d1205 | 8651 | inst.instruction |= inst.operands[1].reg << 12; |
e16bb312 NC |
8652 | } |
8653 | ||
8654 | static void | |
c19d1205 | 8655 | do_vfp_sp2_from_reg2 (void) |
e16bb312 | 8656 | { |
c19d1205 ZW |
8657 | constraint (inst.operands[0].imm != 2, |
8658 | _("only two consecutive VFP SP registers allowed here")); | |
5287ad62 | 8659 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); |
c19d1205 ZW |
8660 | inst.instruction |= inst.operands[1].reg << 12; |
8661 | inst.instruction |= inst.operands[2].reg << 16; | |
e16bb312 NC |
8662 | } |
8663 | ||
8664 | static void | |
c19d1205 | 8665 | do_vfp_sp_ldst (void) |
e16bb312 | 8666 | { |
5287ad62 | 8667 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
c19d1205 | 8668 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8669 | } |
8670 | ||
8671 | static void | |
c19d1205 | 8672 | do_vfp_dp_ldst (void) |
e16bb312 | 8673 | { |
5287ad62 | 8674 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); |
c19d1205 | 8675 | encode_arm_cp_address (1, FALSE, TRUE, 0); |
e16bb312 NC |
8676 | } |
8677 | ||
c19d1205 | 8678 | |
e16bb312 | 8679 | static void |
c19d1205 | 8680 | vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8681 | { |
c19d1205 ZW |
8682 | if (inst.operands[0].writeback) |
8683 | inst.instruction |= WRITE_BACK; | |
8684 | else | |
8685 | constraint (ldstm_type != VFP_LDSTMIA, | |
8686 | _("this addressing mode requires base-register writeback")); | |
8687 | inst.instruction |= inst.operands[0].reg << 16; | |
5287ad62 | 8688 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); |
c19d1205 | 8689 | inst.instruction |= inst.operands[1].imm; |
e16bb312 NC |
8690 | } |
8691 | ||
8692 | static void | |
c19d1205 | 8693 | vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) |
e16bb312 | 8694 | { |
c19d1205 | 8695 | int count; |
e16bb312 | 8696 | |
c19d1205 ZW |
8697 | if (inst.operands[0].writeback) |
8698 | inst.instruction |= WRITE_BACK; | |
8699 | else | |
8700 | constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, | |
8701 | _("this addressing mode requires base-register writeback")); | |
e16bb312 | 8702 | |
c19d1205 | 8703 | inst.instruction |= inst.operands[0].reg << 16; |
5287ad62 | 8704 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); |
e16bb312 | 8705 | |
c19d1205 ZW |
8706 | count = inst.operands[1].imm << 1; |
8707 | if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) | |
8708 | count += 1; | |
e16bb312 | 8709 | |
c19d1205 | 8710 | inst.instruction |= count; |
e16bb312 NC |
8711 | } |
8712 | ||
8713 | static void | |
c19d1205 | 8714 | do_vfp_sp_ldstmia (void) |
e16bb312 | 8715 | { |
c19d1205 | 8716 | vfp_sp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8717 | } |
8718 | ||
8719 | static void | |
c19d1205 | 8720 | do_vfp_sp_ldstmdb (void) |
e16bb312 | 8721 | { |
c19d1205 | 8722 | vfp_sp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8723 | } |
8724 | ||
8725 | static void | |
c19d1205 | 8726 | do_vfp_dp_ldstmia (void) |
e16bb312 | 8727 | { |
c19d1205 | 8728 | vfp_dp_ldstm (VFP_LDSTMIA); |
e16bb312 NC |
8729 | } |
8730 | ||
8731 | static void | |
c19d1205 | 8732 | do_vfp_dp_ldstmdb (void) |
e16bb312 | 8733 | { |
c19d1205 | 8734 | vfp_dp_ldstm (VFP_LDSTMDB); |
e16bb312 NC |
8735 | } |
8736 | ||
8737 | static void | |
c19d1205 | 8738 | do_vfp_xp_ldstmia (void) |
e16bb312 | 8739 | { |
c19d1205 ZW |
8740 | vfp_dp_ldstm (VFP_LDSTMIAX); |
8741 | } | |
e16bb312 | 8742 | |
c19d1205 ZW |
8743 | static void |
8744 | do_vfp_xp_ldstmdb (void) | |
8745 | { | |
8746 | vfp_dp_ldstm (VFP_LDSTMDBX); | |
e16bb312 | 8747 | } |
5287ad62 JB |
8748 | |
8749 | static void | |
8750 | do_vfp_dp_rd_rm (void) | |
8751 | { | |
8752 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8753 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); | |
8754 | } | |
8755 | ||
8756 | static void | |
8757 | do_vfp_dp_rn_rd (void) | |
8758 | { | |
8759 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); | |
8760 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8761 | } | |
8762 | ||
8763 | static void | |
8764 | do_vfp_dp_rd_rn (void) | |
8765 | { | |
8766 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8767 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8768 | } | |
8769 | ||
8770 | static void | |
8771 | do_vfp_dp_rd_rn_rm (void) | |
8772 | { | |
8773 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8774 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); | |
8775 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); | |
8776 | } | |
8777 | ||
8778 | static void | |
8779 | do_vfp_dp_rd (void) | |
8780 | { | |
8781 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8782 | } | |
8783 | ||
8784 | static void | |
8785 | do_vfp_dp_rm_rd_rn (void) | |
8786 | { | |
8787 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); | |
8788 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); | |
8789 | encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); | |
8790 | } | |
8791 | ||
8792 | /* VFPv3 instructions. */ | |
8793 | static void | |
8794 | do_vfp_sp_const (void) | |
8795 | { | |
8796 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
00249aaa PB |
8797 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8798 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8799 | } |
8800 | ||
8801 | static void | |
8802 | do_vfp_dp_const (void) | |
8803 | { | |
8804 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
00249aaa PB |
8805 | inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; |
8806 | inst.instruction |= (inst.operands[1].imm & 0x0f); | |
5287ad62 JB |
8807 | } |
8808 | ||
8809 | static void | |
8810 | vfp_conv (int srcsize) | |
8811 | { | |
5f1af56b MGD |
8812 | int immbits = srcsize - inst.operands[1].imm; |
8813 | ||
8814 | if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize)) | |
8815 | { | |
8816 | /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16. | |
8817 | i.e. immbits must be in range 0 - 16. */ | |
8818 | inst.error = _("immediate value out of range, expected range [0, 16]"); | |
8819 | return; | |
8820 | } | |
8821 | else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize)) | |
8822 | { | |
8823 | /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32. | |
8824 | i.e. immbits must be in range 0 - 31. */ | |
8825 | inst.error = _("immediate value out of range, expected range [1, 32]"); | |
8826 | return; | |
8827 | } | |
8828 | ||
5287ad62 JB |
8829 | inst.instruction |= (immbits & 1) << 5; |
8830 | inst.instruction |= (immbits >> 1); | |
8831 | } | |
8832 | ||
8833 | static void | |
8834 | do_vfp_sp_conv_16 (void) | |
8835 | { | |
8836 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8837 | vfp_conv (16); | |
8838 | } | |
8839 | ||
8840 | static void | |
8841 | do_vfp_dp_conv_16 (void) | |
8842 | { | |
8843 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8844 | vfp_conv (16); | |
8845 | } | |
8846 | ||
8847 | static void | |
8848 | do_vfp_sp_conv_32 (void) | |
8849 | { | |
8850 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
8851 | vfp_conv (32); | |
8852 | } | |
8853 | ||
8854 | static void | |
8855 | do_vfp_dp_conv_32 (void) | |
8856 | { | |
8857 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); | |
8858 | vfp_conv (32); | |
8859 | } | |
c19d1205 ZW |
8860 | \f |
8861 | /* FPA instructions. Also in a logical order. */ | |
e16bb312 | 8862 | |
c19d1205 ZW |
8863 | static void |
8864 | do_fpa_cmp (void) | |
8865 | { | |
8866 | inst.instruction |= inst.operands[0].reg << 16; | |
8867 | inst.instruction |= inst.operands[1].reg; | |
8868 | } | |
b99bd4ef NC |
8869 | |
8870 | static void | |
c19d1205 | 8871 | do_fpa_ldmstm (void) |
b99bd4ef | 8872 | { |
c19d1205 ZW |
8873 | inst.instruction |= inst.operands[0].reg << 12; |
8874 | switch (inst.operands[1].imm) | |
8875 | { | |
8876 | case 1: inst.instruction |= CP_T_X; break; | |
8877 | case 2: inst.instruction |= CP_T_Y; break; | |
8878 | case 3: inst.instruction |= CP_T_Y | CP_T_X; break; | |
8879 | case 4: break; | |
8880 | default: abort (); | |
8881 | } | |
b99bd4ef | 8882 | |
c19d1205 ZW |
8883 | if (inst.instruction & (PRE_INDEX | INDEX_UP)) |
8884 | { | |
8885 | /* The instruction specified "ea" or "fd", so we can only accept | |
8886 | [Rn]{!}. The instruction does not really support stacking or | |
8887 | unstacking, so we have to emulate these by setting appropriate | |
8888 | bits and offsets. */ | |
8889 | constraint (inst.reloc.exp.X_op != O_constant | |
8890 | || inst.reloc.exp.X_add_number != 0, | |
8891 | _("this instruction does not support indexing")); | |
b99bd4ef | 8892 | |
c19d1205 ZW |
8893 | if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) |
8894 | inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; | |
b99bd4ef | 8895 | |
c19d1205 ZW |
8896 | if (!(inst.instruction & INDEX_UP)) |
8897 | inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; | |
b99bd4ef | 8898 | |
c19d1205 ZW |
8899 | if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) |
8900 | { | |
8901 | inst.operands[2].preind = 0; | |
8902 | inst.operands[2].postind = 1; | |
8903 | } | |
8904 | } | |
b99bd4ef | 8905 | |
c19d1205 | 8906 | encode_arm_cp_address (2, TRUE, TRUE, 0); |
b99bd4ef | 8907 | } |
c19d1205 ZW |
8908 | \f |
8909 | /* iWMMXt instructions: strictly in alphabetical order. */ | |
b99bd4ef | 8910 | |
c19d1205 ZW |
8911 | static void |
8912 | do_iwmmxt_tandorc (void) | |
8913 | { | |
8914 | constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); | |
8915 | } | |
b99bd4ef | 8916 | |
c19d1205 ZW |
8917 | static void |
8918 | do_iwmmxt_textrc (void) | |
8919 | { | |
8920 | inst.instruction |= inst.operands[0].reg << 12; | |
8921 | inst.instruction |= inst.operands[1].imm; | |
8922 | } | |
b99bd4ef NC |
8923 | |
8924 | static void | |
c19d1205 | 8925 | do_iwmmxt_textrm (void) |
b99bd4ef | 8926 | { |
c19d1205 ZW |
8927 | inst.instruction |= inst.operands[0].reg << 12; |
8928 | inst.instruction |= inst.operands[1].reg << 16; | |
8929 | inst.instruction |= inst.operands[2].imm; | |
8930 | } | |
b99bd4ef | 8931 | |
c19d1205 ZW |
8932 | static void |
8933 | do_iwmmxt_tinsr (void) | |
8934 | { | |
8935 | inst.instruction |= inst.operands[0].reg << 16; | |
8936 | inst.instruction |= inst.operands[1].reg << 12; | |
8937 | inst.instruction |= inst.operands[2].imm; | |
8938 | } | |
b99bd4ef | 8939 | |
c19d1205 ZW |
8940 | static void |
8941 | do_iwmmxt_tmia (void) | |
8942 | { | |
8943 | inst.instruction |= inst.operands[0].reg << 5; | |
8944 | inst.instruction |= inst.operands[1].reg; | |
8945 | inst.instruction |= inst.operands[2].reg << 12; | |
8946 | } | |
b99bd4ef | 8947 | |
c19d1205 ZW |
8948 | static void |
8949 | do_iwmmxt_waligni (void) | |
8950 | { | |
8951 | inst.instruction |= inst.operands[0].reg << 12; | |
8952 | inst.instruction |= inst.operands[1].reg << 16; | |
8953 | inst.instruction |= inst.operands[2].reg; | |
8954 | inst.instruction |= inst.operands[3].imm << 20; | |
8955 | } | |
b99bd4ef | 8956 | |
2d447fca JM |
8957 | static void |
8958 | do_iwmmxt_wmerge (void) | |
8959 | { | |
8960 | inst.instruction |= inst.operands[0].reg << 12; | |
8961 | inst.instruction |= inst.operands[1].reg << 16; | |
8962 | inst.instruction |= inst.operands[2].reg; | |
8963 | inst.instruction |= inst.operands[3].imm << 21; | |
8964 | } | |
8965 | ||
c19d1205 ZW |
8966 | static void |
8967 | do_iwmmxt_wmov (void) | |
8968 | { | |
8969 | /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ | |
8970 | inst.instruction |= inst.operands[0].reg << 12; | |
8971 | inst.instruction |= inst.operands[1].reg << 16; | |
8972 | inst.instruction |= inst.operands[1].reg; | |
8973 | } | |
b99bd4ef | 8974 | |
c19d1205 ZW |
8975 | static void |
8976 | do_iwmmxt_wldstbh (void) | |
8977 | { | |
8f06b2d8 | 8978 | int reloc; |
c19d1205 | 8979 | inst.instruction |= inst.operands[0].reg << 12; |
8f06b2d8 PB |
8980 | if (thumb_mode) |
8981 | reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; | |
8982 | else | |
8983 | reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; | |
8984 | encode_arm_cp_address (1, TRUE, FALSE, reloc); | |
b99bd4ef NC |
8985 | } |
8986 | ||
c19d1205 ZW |
8987 | static void |
8988 | do_iwmmxt_wldstw (void) | |
8989 | { | |
8990 | /* RIWR_RIWC clears .isreg for a control register. */ | |
8991 | if (!inst.operands[0].isreg) | |
8992 | { | |
8993 | constraint (inst.cond != COND_ALWAYS, BAD_COND); | |
8994 | inst.instruction |= 0xf0000000; | |
8995 | } | |
b99bd4ef | 8996 | |
c19d1205 ZW |
8997 | inst.instruction |= inst.operands[0].reg << 12; |
8998 | encode_arm_cp_address (1, TRUE, TRUE, 0); | |
8999 | } | |
b99bd4ef NC |
9000 | |
9001 | static void | |
c19d1205 | 9002 | do_iwmmxt_wldstd (void) |
b99bd4ef | 9003 | { |
c19d1205 | 9004 | inst.instruction |= inst.operands[0].reg << 12; |
2d447fca JM |
9005 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) |
9006 | && inst.operands[1].immisreg) | |
9007 | { | |
9008 | inst.instruction &= ~0x1a000ff; | |
9009 | inst.instruction |= (0xf << 28); | |
9010 | if (inst.operands[1].preind) | |
9011 | inst.instruction |= PRE_INDEX; | |
9012 | if (!inst.operands[1].negative) | |
9013 | inst.instruction |= INDEX_UP; | |
9014 | if (inst.operands[1].writeback) | |
9015 | inst.instruction |= WRITE_BACK; | |
9016 | inst.instruction |= inst.operands[1].reg << 16; | |
9017 | inst.instruction |= inst.reloc.exp.X_add_number << 4; | |
9018 | inst.instruction |= inst.operands[1].imm; | |
9019 | } | |
9020 | else | |
9021 | encode_arm_cp_address (1, TRUE, FALSE, 0); | |
c19d1205 | 9022 | } |
b99bd4ef | 9023 | |
c19d1205 ZW |
9024 | static void |
9025 | do_iwmmxt_wshufh (void) | |
9026 | { | |
9027 | inst.instruction |= inst.operands[0].reg << 12; | |
9028 | inst.instruction |= inst.operands[1].reg << 16; | |
9029 | inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); | |
9030 | inst.instruction |= (inst.operands[2].imm & 0x0f); | |
9031 | } | |
b99bd4ef | 9032 | |
c19d1205 ZW |
9033 | static void |
9034 | do_iwmmxt_wzero (void) | |
9035 | { | |
9036 | /* WZERO reg is an alias for WANDN reg, reg, reg. */ | |
9037 | inst.instruction |= inst.operands[0].reg; | |
9038 | inst.instruction |= inst.operands[0].reg << 12; | |
9039 | inst.instruction |= inst.operands[0].reg << 16; | |
9040 | } | |
2d447fca JM |
9041 | |
9042 | static void | |
9043 | do_iwmmxt_wrwrwr_or_imm5 (void) | |
9044 | { | |
9045 | if (inst.operands[2].isreg) | |
9046 | do_rd_rn_rm (); | |
9047 | else { | |
9048 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), | |
9049 | _("immediate operand requires iWMMXt2")); | |
9050 | do_rd_rn (); | |
9051 | if (inst.operands[2].imm == 0) | |
9052 | { | |
9053 | switch ((inst.instruction >> 20) & 0xf) | |
9054 | { | |
9055 | case 4: | |
9056 | case 5: | |
9057 | case 6: | |
5f4273c7 | 9058 | case 7: |
2d447fca JM |
9059 | /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ |
9060 | inst.operands[2].imm = 16; | |
9061 | inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); | |
9062 | break; | |
9063 | case 8: | |
9064 | case 9: | |
9065 | case 10: | |
9066 | case 11: | |
9067 | /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ | |
9068 | inst.operands[2].imm = 32; | |
9069 | inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); | |
9070 | break; | |
9071 | case 12: | |
9072 | case 13: | |
9073 | case 14: | |
9074 | case 15: | |
9075 | { | |
9076 | /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ | |
9077 | unsigned long wrn; | |
9078 | wrn = (inst.instruction >> 16) & 0xf; | |
9079 | inst.instruction &= 0xff0fff0f; | |
9080 | inst.instruction |= wrn; | |
9081 | /* Bail out here; the instruction is now assembled. */ | |
9082 | return; | |
9083 | } | |
9084 | } | |
9085 | } | |
9086 | /* Map 32 -> 0, etc. */ | |
9087 | inst.operands[2].imm &= 0x1f; | |
9088 | inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); | |
9089 | } | |
9090 | } | |
c19d1205 ZW |
9091 | \f |
9092 | /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register | |
9093 | operations first, then control, shift, and load/store. */ | |
b99bd4ef | 9094 | |
c19d1205 | 9095 | /* Insns like "foo X,Y,Z". */ |
b99bd4ef | 9096 | |
c19d1205 ZW |
9097 | static void |
9098 | do_mav_triple (void) | |
9099 | { | |
9100 | inst.instruction |= inst.operands[0].reg << 16; | |
9101 | inst.instruction |= inst.operands[1].reg; | |
9102 | inst.instruction |= inst.operands[2].reg << 12; | |
9103 | } | |
b99bd4ef | 9104 | |
c19d1205 ZW |
9105 | /* Insns like "foo W,X,Y,Z". |
9106 | where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ | |
a737bd4d | 9107 | |
c19d1205 ZW |
9108 | static void |
9109 | do_mav_quad (void) | |
9110 | { | |
9111 | inst.instruction |= inst.operands[0].reg << 5; | |
9112 | inst.instruction |= inst.operands[1].reg << 12; | |
9113 | inst.instruction |= inst.operands[2].reg << 16; | |
9114 | inst.instruction |= inst.operands[3].reg; | |
a737bd4d NC |
9115 | } |
9116 | ||
c19d1205 ZW |
9117 | /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ |
9118 | static void | |
9119 | do_mav_dspsc (void) | |
a737bd4d | 9120 | { |
c19d1205 ZW |
9121 | inst.instruction |= inst.operands[1].reg << 12; |
9122 | } | |
a737bd4d | 9123 | |
c19d1205 ZW |
9124 | /* Maverick shift immediate instructions. |
9125 | cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. | |
9126 | cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ | |
a737bd4d | 9127 | |
c19d1205 ZW |
9128 | static void |
9129 | do_mav_shift (void) | |
9130 | { | |
9131 | int imm = inst.operands[2].imm; | |
a737bd4d | 9132 | |
c19d1205 ZW |
9133 | inst.instruction |= inst.operands[0].reg << 12; |
9134 | inst.instruction |= inst.operands[1].reg << 16; | |
a737bd4d | 9135 | |
c19d1205 ZW |
9136 | /* Bits 0-3 of the insn should have bits 0-3 of the immediate. |
9137 | Bits 5-7 of the insn should have bits 4-6 of the immediate. | |
9138 | Bit 4 should be 0. */ | |
9139 | imm = (imm & 0xf) | ((imm & 0x70) << 1); | |
a737bd4d | 9140 | |
c19d1205 ZW |
9141 | inst.instruction |= imm; |
9142 | } | |
9143 | \f | |
9144 | /* XScale instructions. Also sorted arithmetic before move. */ | |
a737bd4d | 9145 | |
c19d1205 ZW |
9146 | /* Xscale multiply-accumulate (argument parse) |
9147 | MIAcc acc0,Rm,Rs | |
9148 | MIAPHcc acc0,Rm,Rs | |
9149 | MIAxycc acc0,Rm,Rs. */ | |
a737bd4d | 9150 | |
c19d1205 ZW |
9151 | static void |
9152 | do_xsc_mia (void) | |
9153 | { | |
9154 | inst.instruction |= inst.operands[1].reg; | |
9155 | inst.instruction |= inst.operands[2].reg << 12; | |
9156 | } | |
a737bd4d | 9157 | |
c19d1205 | 9158 | /* Xscale move-accumulator-register (argument parse) |
a737bd4d | 9159 | |
c19d1205 | 9160 | MARcc acc0,RdLo,RdHi. */ |
b99bd4ef | 9161 | |
c19d1205 ZW |
9162 | static void |
9163 | do_xsc_mar (void) | |
9164 | { | |
9165 | inst.instruction |= inst.operands[1].reg << 12; | |
9166 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
9167 | } |
9168 | ||
c19d1205 | 9169 | /* Xscale move-register-accumulator (argument parse) |
b99bd4ef | 9170 | |
c19d1205 | 9171 | MRAcc RdLo,RdHi,acc0. */ |
b99bd4ef NC |
9172 | |
9173 | static void | |
c19d1205 | 9174 | do_xsc_mra (void) |
b99bd4ef | 9175 | { |
c19d1205 ZW |
9176 | constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); |
9177 | inst.instruction |= inst.operands[0].reg << 12; | |
9178 | inst.instruction |= inst.operands[1].reg << 16; | |
9179 | } | |
9180 | \f | |
9181 | /* Encoding functions relevant only to Thumb. */ | |
b99bd4ef | 9182 | |
c19d1205 ZW |
9183 | /* inst.operands[i] is a shifted-register operand; encode |
9184 | it into inst.instruction in the format used by Thumb32. */ | |
9185 | ||
9186 | static void | |
9187 | encode_thumb32_shifted_operand (int i) | |
9188 | { | |
9189 | unsigned int value = inst.reloc.exp.X_add_number; | |
9190 | unsigned int shift = inst.operands[i].shift_kind; | |
b99bd4ef | 9191 | |
9c3c69f2 PB |
9192 | constraint (inst.operands[i].immisreg, |
9193 | _("shift by register not allowed in thumb mode")); | |
c19d1205 ZW |
9194 | inst.instruction |= inst.operands[i].reg; |
9195 | if (shift == SHIFT_RRX) | |
9196 | inst.instruction |= SHIFT_ROR << 4; | |
9197 | else | |
b99bd4ef | 9198 | { |
c19d1205 ZW |
9199 | constraint (inst.reloc.exp.X_op != O_constant, |
9200 | _("expression too complex")); | |
9201 | ||
9202 | constraint (value > 32 | |
9203 | || (value == 32 && (shift == SHIFT_LSL | |
9204 | || shift == SHIFT_ROR)), | |
9205 | _("shift expression is too large")); | |
9206 | ||
9207 | if (value == 0) | |
9208 | shift = SHIFT_LSL; | |
9209 | else if (value == 32) | |
9210 | value = 0; | |
9211 | ||
9212 | inst.instruction |= shift << 4; | |
9213 | inst.instruction |= (value & 0x1c) << 10; | |
9214 | inst.instruction |= (value & 0x03) << 6; | |
b99bd4ef | 9215 | } |
c19d1205 | 9216 | } |
b99bd4ef | 9217 | |
b99bd4ef | 9218 | |
c19d1205 ZW |
9219 | /* inst.operands[i] was set up by parse_address. Encode it into a |
9220 | Thumb32 format load or store instruction. Reject forms that cannot | |
9221 | be used with such instructions. If is_t is true, reject forms that | |
9222 | cannot be used with a T instruction; if is_d is true, reject forms | |
5be8be5d DG |
9223 | that cannot be used with a D instruction. If it is a store insn, |
9224 | reject PC in Rn. */ | |
b99bd4ef | 9225 | |
c19d1205 ZW |
9226 | static void |
9227 | encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) | |
9228 | { | |
5be8be5d | 9229 | const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); |
c19d1205 ZW |
9230 | |
9231 | constraint (!inst.operands[i].isreg, | |
53365c0d | 9232 | _("Instruction does not support =N addresses")); |
b99bd4ef | 9233 | |
c19d1205 ZW |
9234 | inst.instruction |= inst.operands[i].reg << 16; |
9235 | if (inst.operands[i].immisreg) | |
b99bd4ef | 9236 | { |
5be8be5d | 9237 | constraint (is_pc, BAD_PC_ADDRESSING); |
c19d1205 ZW |
9238 | constraint (is_t || is_d, _("cannot use register index with this instruction")); |
9239 | constraint (inst.operands[i].negative, | |
9240 | _("Thumb does not support negative register indexing")); | |
9241 | constraint (inst.operands[i].postind, | |
9242 | _("Thumb does not support register post-indexing")); | |
9243 | constraint (inst.operands[i].writeback, | |
9244 | _("Thumb does not support register indexing with writeback")); | |
9245 | constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, | |
9246 | _("Thumb supports only LSL in shifted register indexing")); | |
b99bd4ef | 9247 | |
f40d1643 | 9248 | inst.instruction |= inst.operands[i].imm; |
c19d1205 | 9249 | if (inst.operands[i].shifted) |
b99bd4ef | 9250 | { |
c19d1205 ZW |
9251 | constraint (inst.reloc.exp.X_op != O_constant, |
9252 | _("expression too complex")); | |
9c3c69f2 PB |
9253 | constraint (inst.reloc.exp.X_add_number < 0 |
9254 | || inst.reloc.exp.X_add_number > 3, | |
c19d1205 | 9255 | _("shift out of range")); |
9c3c69f2 | 9256 | inst.instruction |= inst.reloc.exp.X_add_number << 4; |
c19d1205 ZW |
9257 | } |
9258 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9259 | } | |
9260 | else if (inst.operands[i].preind) | |
9261 | { | |
5be8be5d | 9262 | constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK); |
f40d1643 | 9263 | constraint (is_t && inst.operands[i].writeback, |
c19d1205 | 9264 | _("cannot use writeback with this instruction")); |
5be8be5d DG |
9265 | constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0) |
9266 | && !inst.reloc.pc_rel, BAD_PC_ADDRESSING); | |
c19d1205 ZW |
9267 | |
9268 | if (is_d) | |
9269 | { | |
9270 | inst.instruction |= 0x01000000; | |
9271 | if (inst.operands[i].writeback) | |
9272 | inst.instruction |= 0x00200000; | |
b99bd4ef | 9273 | } |
c19d1205 | 9274 | else |
b99bd4ef | 9275 | { |
c19d1205 ZW |
9276 | inst.instruction |= 0x00000c00; |
9277 | if (inst.operands[i].writeback) | |
9278 | inst.instruction |= 0x00000100; | |
b99bd4ef | 9279 | } |
c19d1205 | 9280 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; |
b99bd4ef | 9281 | } |
c19d1205 | 9282 | else if (inst.operands[i].postind) |
b99bd4ef | 9283 | { |
9c2799c2 | 9284 | gas_assert (inst.operands[i].writeback); |
c19d1205 ZW |
9285 | constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); |
9286 | constraint (is_t, _("cannot use post-indexing with this instruction")); | |
9287 | ||
9288 | if (is_d) | |
9289 | inst.instruction |= 0x00200000; | |
9290 | else | |
9291 | inst.instruction |= 0x00000900; | |
9292 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
9293 | } | |
9294 | else /* unindexed - only for coprocessor */ | |
9295 | inst.error = _("instruction does not accept unindexed addressing"); | |
9296 | } | |
9297 | ||
9298 | /* Table of Thumb instructions which exist in both 16- and 32-bit | |
9299 | encodings (the latter only in post-V6T2 cores). The index is the | |
9300 | value used in the insns table below. When there is more than one | |
9301 | possible 16-bit encoding for the instruction, this table always | |
0110f2b8 PB |
9302 | holds variant (1). |
9303 | Also contains several pseudo-instructions used during relaxation. */ | |
c19d1205 | 9304 | #define T16_32_TAB \ |
21d799b5 NC |
9305 | X(_adc, 4140, eb400000), \ |
9306 | X(_adcs, 4140, eb500000), \ | |
9307 | X(_add, 1c00, eb000000), \ | |
9308 | X(_adds, 1c00, eb100000), \ | |
9309 | X(_addi, 0000, f1000000), \ | |
9310 | X(_addis, 0000, f1100000), \ | |
9311 | X(_add_pc,000f, f20f0000), \ | |
9312 | X(_add_sp,000d, f10d0000), \ | |
9313 | X(_adr, 000f, f20f0000), \ | |
9314 | X(_and, 4000, ea000000), \ | |
9315 | X(_ands, 4000, ea100000), \ | |
9316 | X(_asr, 1000, fa40f000), \ | |
9317 | X(_asrs, 1000, fa50f000), \ | |
9318 | X(_b, e000, f000b000), \ | |
9319 | X(_bcond, d000, f0008000), \ | |
9320 | X(_bic, 4380, ea200000), \ | |
9321 | X(_bics, 4380, ea300000), \ | |
9322 | X(_cmn, 42c0, eb100f00), \ | |
9323 | X(_cmp, 2800, ebb00f00), \ | |
9324 | X(_cpsie, b660, f3af8400), \ | |
9325 | X(_cpsid, b670, f3af8600), \ | |
9326 | X(_cpy, 4600, ea4f0000), \ | |
9327 | X(_dec_sp,80dd, f1ad0d00), \ | |
9328 | X(_eor, 4040, ea800000), \ | |
9329 | X(_eors, 4040, ea900000), \ | |
9330 | X(_inc_sp,00dd, f10d0d00), \ | |
9331 | X(_ldmia, c800, e8900000), \ | |
9332 | X(_ldr, 6800, f8500000), \ | |
9333 | X(_ldrb, 7800, f8100000), \ | |
9334 | X(_ldrh, 8800, f8300000), \ | |
9335 | X(_ldrsb, 5600, f9100000), \ | |
9336 | X(_ldrsh, 5e00, f9300000), \ | |
9337 | X(_ldr_pc,4800, f85f0000), \ | |
9338 | X(_ldr_pc2,4800, f85f0000), \ | |
9339 | X(_ldr_sp,9800, f85d0000), \ | |
9340 | X(_lsl, 0000, fa00f000), \ | |
9341 | X(_lsls, 0000, fa10f000), \ | |
9342 | X(_lsr, 0800, fa20f000), \ | |
9343 | X(_lsrs, 0800, fa30f000), \ | |
9344 | X(_mov, 2000, ea4f0000), \ | |
9345 | X(_movs, 2000, ea5f0000), \ | |
9346 | X(_mul, 4340, fb00f000), \ | |
9347 | X(_muls, 4340, ffffffff), /* no 32b muls */ \ | |
9348 | X(_mvn, 43c0, ea6f0000), \ | |
9349 | X(_mvns, 43c0, ea7f0000), \ | |
9350 | X(_neg, 4240, f1c00000), /* rsb #0 */ \ | |
9351 | X(_negs, 4240, f1d00000), /* rsbs #0 */ \ | |
9352 | X(_orr, 4300, ea400000), \ | |
9353 | X(_orrs, 4300, ea500000), \ | |
9354 | X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \ | |
9355 | X(_push, b400, e92d0000), /* stmdb sp!,... */ \ | |
9356 | X(_rev, ba00, fa90f080), \ | |
9357 | X(_rev16, ba40, fa90f090), \ | |
9358 | X(_revsh, bac0, fa90f0b0), \ | |
9359 | X(_ror, 41c0, fa60f000), \ | |
9360 | X(_rors, 41c0, fa70f000), \ | |
9361 | X(_sbc, 4180, eb600000), \ | |
9362 | X(_sbcs, 4180, eb700000), \ | |
9363 | X(_stmia, c000, e8800000), \ | |
9364 | X(_str, 6000, f8400000), \ | |
9365 | X(_strb, 7000, f8000000), \ | |
9366 | X(_strh, 8000, f8200000), \ | |
9367 | X(_str_sp,9000, f84d0000), \ | |
9368 | X(_sub, 1e00, eba00000), \ | |
9369 | X(_subs, 1e00, ebb00000), \ | |
9370 | X(_subi, 8000, f1a00000), \ | |
9371 | X(_subis, 8000, f1b00000), \ | |
9372 | X(_sxtb, b240, fa4ff080), \ | |
9373 | X(_sxth, b200, fa0ff080), \ | |
9374 | X(_tst, 4200, ea100f00), \ | |
9375 | X(_uxtb, b2c0, fa5ff080), \ | |
9376 | X(_uxth, b280, fa1ff080), \ | |
9377 | X(_nop, bf00, f3af8000), \ | |
9378 | X(_yield, bf10, f3af8001), \ | |
9379 | X(_wfe, bf20, f3af8002), \ | |
9380 | X(_wfi, bf30, f3af8003), \ | |
9381 | X(_sev, bf40, f3af8004), | |
c19d1205 ZW |
9382 | |
9383 | /* To catch errors in encoding functions, the codes are all offset by | |
9384 | 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined | |
9385 | as 16-bit instructions. */ | |
21d799b5 | 9386 | #define X(a,b,c) T_MNEM##a |
c19d1205 ZW |
9387 | enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; |
9388 | #undef X | |
9389 | ||
9390 | #define X(a,b,c) 0x##b | |
9391 | static const unsigned short thumb_op16[] = { T16_32_TAB }; | |
9392 | #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) | |
9393 | #undef X | |
9394 | ||
9395 | #define X(a,b,c) 0x##c | |
9396 | static const unsigned int thumb_op32[] = { T16_32_TAB }; | |
c921be7d NC |
9397 | #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) |
9398 | #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) | |
c19d1205 ZW |
9399 | #undef X |
9400 | #undef T16_32_TAB | |
9401 | ||
9402 | /* Thumb instruction encoders, in alphabetical order. */ | |
9403 | ||
92e90b6e | 9404 | /* ADDW or SUBW. */ |
c921be7d | 9405 | |
92e90b6e PB |
9406 | static void |
9407 | do_t_add_sub_w (void) | |
9408 | { | |
9409 | int Rd, Rn; | |
9410 | ||
9411 | Rd = inst.operands[0].reg; | |
9412 | Rn = inst.operands[1].reg; | |
9413 | ||
539d4391 NC |
9414 | /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this |
9415 | is the SP-{plus,minus}-immediate form of the instruction. */ | |
9416 | if (Rn == REG_SP) | |
9417 | constraint (Rd == REG_PC, BAD_PC); | |
9418 | else | |
9419 | reject_bad_reg (Rd); | |
fdfde340 | 9420 | |
92e90b6e PB |
9421 | inst.instruction |= (Rn << 16) | (Rd << 8); |
9422 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9423 | } | |
9424 | ||
c19d1205 ZW |
9425 | /* Parse an add or subtract instruction. We get here with inst.instruction |
9426 | equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ | |
9427 | ||
9428 | static void | |
9429 | do_t_add_sub (void) | |
9430 | { | |
9431 | int Rd, Rs, Rn; | |
9432 | ||
9433 | Rd = inst.operands[0].reg; | |
9434 | Rs = (inst.operands[1].present | |
9435 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9436 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9437 | ||
e07e6e58 NC |
9438 | if (Rd == REG_PC) |
9439 | set_it_insn_type_last (); | |
9440 | ||
c19d1205 ZW |
9441 | if (unified_syntax) |
9442 | { | |
0110f2b8 PB |
9443 | bfd_boolean flags; |
9444 | bfd_boolean narrow; | |
9445 | int opcode; | |
9446 | ||
9447 | flags = (inst.instruction == T_MNEM_adds | |
9448 | || inst.instruction == T_MNEM_subs); | |
9449 | if (flags) | |
e07e6e58 | 9450 | narrow = !in_it_block (); |
0110f2b8 | 9451 | else |
e07e6e58 | 9452 | narrow = in_it_block (); |
c19d1205 | 9453 | if (!inst.operands[2].isreg) |
b99bd4ef | 9454 | { |
16805f35 PB |
9455 | int add; |
9456 | ||
fdfde340 JM |
9457 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); |
9458 | ||
16805f35 PB |
9459 | add = (inst.instruction == T_MNEM_add |
9460 | || inst.instruction == T_MNEM_adds); | |
0110f2b8 PB |
9461 | opcode = 0; |
9462 | if (inst.size_req != 4) | |
9463 | { | |
0110f2b8 PB |
9464 | /* Attempt to use a narrow opcode, with relaxation if |
9465 | appropriate. */ | |
9466 | if (Rd == REG_SP && Rs == REG_SP && !flags) | |
9467 | opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; | |
9468 | else if (Rd <= 7 && Rs == REG_SP && add && !flags) | |
9469 | opcode = T_MNEM_add_sp; | |
9470 | else if (Rd <= 7 && Rs == REG_PC && add && !flags) | |
9471 | opcode = T_MNEM_add_pc; | |
9472 | else if (Rd <= 7 && Rs <= 7 && narrow) | |
9473 | { | |
9474 | if (flags) | |
9475 | opcode = add ? T_MNEM_addis : T_MNEM_subis; | |
9476 | else | |
9477 | opcode = add ? T_MNEM_addi : T_MNEM_subi; | |
9478 | } | |
9479 | if (opcode) | |
9480 | { | |
9481 | inst.instruction = THUMB_OP16(opcode); | |
9482 | inst.instruction |= (Rd << 4) | Rs; | |
9483 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9484 | if (inst.size_req != 2) | |
9485 | inst.relax = opcode; | |
9486 | } | |
9487 | else | |
9488 | constraint (inst.size_req == 2, BAD_HIREG); | |
9489 | } | |
9490 | if (inst.size_req == 4 | |
9491 | || (inst.size_req != 2 && !opcode)) | |
9492 | { | |
efd81785 PB |
9493 | if (Rd == REG_PC) |
9494 | { | |
fdfde340 | 9495 | constraint (add, BAD_PC); |
efd81785 PB |
9496 | constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, |
9497 | _("only SUBS PC, LR, #const allowed")); | |
9498 | constraint (inst.reloc.exp.X_op != O_constant, | |
9499 | _("expression too complex")); | |
9500 | constraint (inst.reloc.exp.X_add_number < 0 | |
9501 | || inst.reloc.exp.X_add_number > 0xff, | |
9502 | _("immediate value out of range")); | |
9503 | inst.instruction = T2_SUBS_PC_LR | |
9504 | | inst.reloc.exp.X_add_number; | |
9505 | inst.reloc.type = BFD_RELOC_UNUSED; | |
9506 | return; | |
9507 | } | |
9508 | else if (Rs == REG_PC) | |
16805f35 PB |
9509 | { |
9510 | /* Always use addw/subw. */ | |
9511 | inst.instruction = add ? 0xf20f0000 : 0xf2af0000; | |
9512 | inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; | |
9513 | } | |
9514 | else | |
9515 | { | |
9516 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9517 | inst.instruction = (inst.instruction & 0xe1ffffff) | |
9518 | | 0x10000000; | |
9519 | if (flags) | |
9520 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9521 | else | |
9522 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; | |
9523 | } | |
dc4503c6 PB |
9524 | inst.instruction |= Rd << 8; |
9525 | inst.instruction |= Rs << 16; | |
0110f2b8 | 9526 | } |
b99bd4ef | 9527 | } |
c19d1205 ZW |
9528 | else |
9529 | { | |
5f4cb198 NC |
9530 | unsigned int value = inst.reloc.exp.X_add_number; |
9531 | unsigned int shift = inst.operands[2].shift_kind; | |
9532 | ||
c19d1205 ZW |
9533 | Rn = inst.operands[2].reg; |
9534 | /* See if we can do this with a 16-bit instruction. */ | |
9535 | if (!inst.operands[2].shifted && inst.size_req != 4) | |
9536 | { | |
e27ec89e PB |
9537 | if (Rd > 7 || Rs > 7 || Rn > 7) |
9538 | narrow = FALSE; | |
9539 | ||
9540 | if (narrow) | |
c19d1205 | 9541 | { |
e27ec89e PB |
9542 | inst.instruction = ((inst.instruction == T_MNEM_adds |
9543 | || inst.instruction == T_MNEM_add) | |
c19d1205 ZW |
9544 | ? T_OPCODE_ADD_R3 |
9545 | : T_OPCODE_SUB_R3); | |
9546 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
9547 | return; | |
9548 | } | |
b99bd4ef | 9549 | |
7e806470 | 9550 | if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) |
c19d1205 | 9551 | { |
7e806470 PB |
9552 | /* Thumb-1 cores (except v6-M) require at least one high |
9553 | register in a narrow non flag setting add. */ | |
9554 | if (Rd > 7 || Rn > 7 | |
9555 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2) | |
9556 | || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr)) | |
c19d1205 | 9557 | { |
7e806470 PB |
9558 | if (Rd == Rn) |
9559 | { | |
9560 | Rn = Rs; | |
9561 | Rs = Rd; | |
9562 | } | |
c19d1205 ZW |
9563 | inst.instruction = T_OPCODE_ADD_HI; |
9564 | inst.instruction |= (Rd & 8) << 4; | |
9565 | inst.instruction |= (Rd & 7); | |
9566 | inst.instruction |= Rn << 3; | |
9567 | return; | |
9568 | } | |
c19d1205 ZW |
9569 | } |
9570 | } | |
c921be7d | 9571 | |
fdfde340 JM |
9572 | constraint (Rd == REG_PC, BAD_PC); |
9573 | constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP); | |
9574 | constraint (Rs == REG_PC, BAD_PC); | |
9575 | reject_bad_reg (Rn); | |
9576 | ||
c19d1205 ZW |
9577 | /* If we get here, it can't be done in 16 bits. */ |
9578 | constraint (inst.operands[2].shifted && inst.operands[2].immisreg, | |
9579 | _("shift must be constant")); | |
9580 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9581 | inst.instruction |= Rd << 8; | |
9582 | inst.instruction |= Rs << 16; | |
5f4cb198 NC |
9583 | constraint (Rd == REG_SP && Rs == REG_SP && value > 3, |
9584 | _("shift value over 3 not allowed in thumb mode")); | |
9585 | constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL, | |
9586 | _("only LSL shift allowed in thumb mode")); | |
c19d1205 ZW |
9587 | encode_thumb32_shifted_operand (2); |
9588 | } | |
9589 | } | |
9590 | else | |
9591 | { | |
9592 | constraint (inst.instruction == T_MNEM_adds | |
9593 | || inst.instruction == T_MNEM_subs, | |
9594 | BAD_THUMB32); | |
b99bd4ef | 9595 | |
c19d1205 | 9596 | if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ |
b99bd4ef | 9597 | { |
c19d1205 ZW |
9598 | constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) |
9599 | || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), | |
9600 | BAD_HIREG); | |
9601 | ||
9602 | inst.instruction = (inst.instruction == T_MNEM_add | |
9603 | ? 0x0000 : 0x8000); | |
9604 | inst.instruction |= (Rd << 4) | Rs; | |
9605 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
b99bd4ef NC |
9606 | return; |
9607 | } | |
9608 | ||
c19d1205 ZW |
9609 | Rn = inst.operands[2].reg; |
9610 | constraint (inst.operands[2].shifted, _("unshifted register required")); | |
b99bd4ef | 9611 | |
c19d1205 ZW |
9612 | /* We now have Rd, Rs, and Rn set to registers. */ |
9613 | if (Rd > 7 || Rs > 7 || Rn > 7) | |
b99bd4ef | 9614 | { |
c19d1205 ZW |
9615 | /* Can't do this for SUB. */ |
9616 | constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); | |
9617 | inst.instruction = T_OPCODE_ADD_HI; | |
9618 | inst.instruction |= (Rd & 8) << 4; | |
9619 | inst.instruction |= (Rd & 7); | |
9620 | if (Rs == Rd) | |
9621 | inst.instruction |= Rn << 3; | |
9622 | else if (Rn == Rd) | |
9623 | inst.instruction |= Rs << 3; | |
9624 | else | |
9625 | constraint (1, _("dest must overlap one source register")); | |
9626 | } | |
9627 | else | |
9628 | { | |
9629 | inst.instruction = (inst.instruction == T_MNEM_add | |
9630 | ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); | |
9631 | inst.instruction |= Rd | (Rs << 3) | (Rn << 6); | |
b99bd4ef | 9632 | } |
b99bd4ef | 9633 | } |
b99bd4ef NC |
9634 | } |
9635 | ||
c19d1205 ZW |
9636 | static void |
9637 | do_t_adr (void) | |
9638 | { | |
fdfde340 JM |
9639 | unsigned Rd; |
9640 | ||
9641 | Rd = inst.operands[0].reg; | |
9642 | reject_bad_reg (Rd); | |
9643 | ||
9644 | if (unified_syntax && inst.size_req == 0 && Rd <= 7) | |
0110f2b8 PB |
9645 | { |
9646 | /* Defer to section relaxation. */ | |
9647 | inst.relax = inst.instruction; | |
9648 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 | 9649 | inst.instruction |= Rd << 4; |
0110f2b8 PB |
9650 | } |
9651 | else if (unified_syntax && inst.size_req != 2) | |
e9f89963 | 9652 | { |
0110f2b8 | 9653 | /* Generate a 32-bit opcode. */ |
e9f89963 | 9654 | inst.instruction = THUMB_OP32 (inst.instruction); |
fdfde340 | 9655 | inst.instruction |= Rd << 8; |
e9f89963 PB |
9656 | inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; |
9657 | inst.reloc.pc_rel = 1; | |
9658 | } | |
9659 | else | |
9660 | { | |
0110f2b8 | 9661 | /* Generate a 16-bit opcode. */ |
e9f89963 PB |
9662 | inst.instruction = THUMB_OP16 (inst.instruction); |
9663 | inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; | |
9664 | inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ | |
9665 | inst.reloc.pc_rel = 1; | |
b99bd4ef | 9666 | |
fdfde340 | 9667 | inst.instruction |= Rd << 4; |
e9f89963 | 9668 | } |
c19d1205 | 9669 | } |
b99bd4ef | 9670 | |
c19d1205 ZW |
9671 | /* Arithmetic instructions for which there is just one 16-bit |
9672 | instruction encoding, and it allows only two low registers. | |
9673 | For maximal compatibility with ARM syntax, we allow three register | |
9674 | operands even when Thumb-32 instructions are not available, as long | |
9675 | as the first two are identical. For instance, both "sbc r0,r1" and | |
9676 | "sbc r0,r0,r1" are allowed. */ | |
b99bd4ef | 9677 | static void |
c19d1205 | 9678 | do_t_arit3 (void) |
b99bd4ef | 9679 | { |
c19d1205 | 9680 | int Rd, Rs, Rn; |
b99bd4ef | 9681 | |
c19d1205 ZW |
9682 | Rd = inst.operands[0].reg; |
9683 | Rs = (inst.operands[1].present | |
9684 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9685 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9686 | Rn = inst.operands[2].reg; | |
b99bd4ef | 9687 | |
fdfde340 JM |
9688 | reject_bad_reg (Rd); |
9689 | reject_bad_reg (Rs); | |
9690 | if (inst.operands[2].isreg) | |
9691 | reject_bad_reg (Rn); | |
9692 | ||
c19d1205 | 9693 | if (unified_syntax) |
b99bd4ef | 9694 | { |
c19d1205 ZW |
9695 | if (!inst.operands[2].isreg) |
9696 | { | |
9697 | /* For an immediate, we always generate a 32-bit opcode; | |
9698 | section relaxation will shrink it later if possible. */ | |
9699 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9700 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9701 | inst.instruction |= Rd << 8; | |
9702 | inst.instruction |= Rs << 16; | |
9703 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
9704 | } | |
9705 | else | |
9706 | { | |
e27ec89e PB |
9707 | bfd_boolean narrow; |
9708 | ||
c19d1205 | 9709 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9710 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9711 | narrow = !in_it_block (); |
e27ec89e | 9712 | else |
e07e6e58 | 9713 | narrow = in_it_block (); |
e27ec89e PB |
9714 | |
9715 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9716 | narrow = FALSE; | |
9717 | if (inst.operands[2].shifted) | |
9718 | narrow = FALSE; | |
9719 | if (inst.size_req == 4) | |
9720 | narrow = FALSE; | |
9721 | ||
9722 | if (narrow | |
c19d1205 ZW |
9723 | && Rd == Rs) |
9724 | { | |
9725 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9726 | inst.instruction |= Rd; | |
9727 | inst.instruction |= Rn << 3; | |
9728 | return; | |
9729 | } | |
b99bd4ef | 9730 | |
c19d1205 ZW |
9731 | /* If we get here, it can't be done in 16 bits. */ |
9732 | constraint (inst.operands[2].shifted | |
9733 | && inst.operands[2].immisreg, | |
9734 | _("shift must be constant")); | |
9735 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9736 | inst.instruction |= Rd << 8; | |
9737 | inst.instruction |= Rs << 16; | |
9738 | encode_thumb32_shifted_operand (2); | |
9739 | } | |
a737bd4d | 9740 | } |
c19d1205 | 9741 | else |
b99bd4ef | 9742 | { |
c19d1205 ZW |
9743 | /* On its face this is a lie - the instruction does set the |
9744 | flags. However, the only supported mnemonic in this mode | |
9745 | says it doesn't. */ | |
9746 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9747 | |
c19d1205 ZW |
9748 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9749 | _("unshifted register required")); | |
9750 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9751 | constraint (Rd != Rs, | |
9752 | _("dest and source1 must be the same register")); | |
a737bd4d | 9753 | |
c19d1205 ZW |
9754 | inst.instruction = THUMB_OP16 (inst.instruction); |
9755 | inst.instruction |= Rd; | |
9756 | inst.instruction |= Rn << 3; | |
b99bd4ef | 9757 | } |
a737bd4d | 9758 | } |
b99bd4ef | 9759 | |
c19d1205 ZW |
9760 | /* Similarly, but for instructions where the arithmetic operation is |
9761 | commutative, so we can allow either of them to be different from | |
9762 | the destination operand in a 16-bit instruction. For instance, all | |
9763 | three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are | |
9764 | accepted. */ | |
9765 | static void | |
9766 | do_t_arit3c (void) | |
a737bd4d | 9767 | { |
c19d1205 | 9768 | int Rd, Rs, Rn; |
b99bd4ef | 9769 | |
c19d1205 ZW |
9770 | Rd = inst.operands[0].reg; |
9771 | Rs = (inst.operands[1].present | |
9772 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
9773 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
9774 | Rn = inst.operands[2].reg; | |
c921be7d | 9775 | |
fdfde340 JM |
9776 | reject_bad_reg (Rd); |
9777 | reject_bad_reg (Rs); | |
9778 | if (inst.operands[2].isreg) | |
9779 | reject_bad_reg (Rn); | |
a737bd4d | 9780 | |
c19d1205 | 9781 | if (unified_syntax) |
a737bd4d | 9782 | { |
c19d1205 | 9783 | if (!inst.operands[2].isreg) |
b99bd4ef | 9784 | { |
c19d1205 ZW |
9785 | /* For an immediate, we always generate a 32-bit opcode; |
9786 | section relaxation will shrink it later if possible. */ | |
9787 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9788 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
9789 | inst.instruction |= Rd << 8; | |
9790 | inst.instruction |= Rs << 16; | |
9791 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
b99bd4ef | 9792 | } |
c19d1205 | 9793 | else |
a737bd4d | 9794 | { |
e27ec89e PB |
9795 | bfd_boolean narrow; |
9796 | ||
c19d1205 | 9797 | /* See if we can do this with a 16-bit instruction. */ |
e27ec89e | 9798 | if (THUMB_SETS_FLAGS (inst.instruction)) |
e07e6e58 | 9799 | narrow = !in_it_block (); |
e27ec89e | 9800 | else |
e07e6e58 | 9801 | narrow = in_it_block (); |
e27ec89e PB |
9802 | |
9803 | if (Rd > 7 || Rn > 7 || Rs > 7) | |
9804 | narrow = FALSE; | |
9805 | if (inst.operands[2].shifted) | |
9806 | narrow = FALSE; | |
9807 | if (inst.size_req == 4) | |
9808 | narrow = FALSE; | |
9809 | ||
9810 | if (narrow) | |
a737bd4d | 9811 | { |
c19d1205 | 9812 | if (Rd == Rs) |
a737bd4d | 9813 | { |
c19d1205 ZW |
9814 | inst.instruction = THUMB_OP16 (inst.instruction); |
9815 | inst.instruction |= Rd; | |
9816 | inst.instruction |= Rn << 3; | |
9817 | return; | |
a737bd4d | 9818 | } |
c19d1205 | 9819 | if (Rd == Rn) |
a737bd4d | 9820 | { |
c19d1205 ZW |
9821 | inst.instruction = THUMB_OP16 (inst.instruction); |
9822 | inst.instruction |= Rd; | |
9823 | inst.instruction |= Rs << 3; | |
9824 | return; | |
a737bd4d NC |
9825 | } |
9826 | } | |
c19d1205 ZW |
9827 | |
9828 | /* If we get here, it can't be done in 16 bits. */ | |
9829 | constraint (inst.operands[2].shifted | |
9830 | && inst.operands[2].immisreg, | |
9831 | _("shift must be constant")); | |
9832 | inst.instruction = THUMB_OP32 (inst.instruction); | |
9833 | inst.instruction |= Rd << 8; | |
9834 | inst.instruction |= Rs << 16; | |
9835 | encode_thumb32_shifted_operand (2); | |
a737bd4d | 9836 | } |
b99bd4ef | 9837 | } |
c19d1205 ZW |
9838 | else |
9839 | { | |
9840 | /* On its face this is a lie - the instruction does set the | |
9841 | flags. However, the only supported mnemonic in this mode | |
9842 | says it doesn't. */ | |
9843 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
a737bd4d | 9844 | |
c19d1205 ZW |
9845 | constraint (!inst.operands[2].isreg || inst.operands[2].shifted, |
9846 | _("unshifted register required")); | |
9847 | constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); | |
9848 | ||
9849 | inst.instruction = THUMB_OP16 (inst.instruction); | |
9850 | inst.instruction |= Rd; | |
9851 | ||
9852 | if (Rd == Rs) | |
9853 | inst.instruction |= Rn << 3; | |
9854 | else if (Rd == Rn) | |
9855 | inst.instruction |= Rs << 3; | |
9856 | else | |
9857 | constraint (1, _("dest must overlap one source register")); | |
9858 | } | |
a737bd4d NC |
9859 | } |
9860 | ||
62b3e311 PB |
9861 | static void |
9862 | do_t_barrier (void) | |
9863 | { | |
9864 | if (inst.operands[0].present) | |
9865 | { | |
9866 | constraint ((inst.instruction & 0xf0) != 0x40 | |
52e7f43d RE |
9867 | && inst.operands[0].imm > 0xf |
9868 | && inst.operands[0].imm < 0x0, | |
bd3ba5d1 | 9869 | _("bad barrier type")); |
62b3e311 PB |
9870 | inst.instruction |= inst.operands[0].imm; |
9871 | } | |
9872 | else | |
9873 | inst.instruction |= 0xf; | |
9874 | } | |
9875 | ||
c19d1205 ZW |
9876 | static void |
9877 | do_t_bfc (void) | |
a737bd4d | 9878 | { |
fdfde340 | 9879 | unsigned Rd; |
c19d1205 ZW |
9880 | unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; |
9881 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9882 | /* The instruction encoding stores the LSB and MSB, | |
9883 | not the LSB and width. */ | |
fdfde340 JM |
9884 | Rd = inst.operands[0].reg; |
9885 | reject_bad_reg (Rd); | |
9886 | inst.instruction |= Rd << 8; | |
c19d1205 ZW |
9887 | inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; |
9888 | inst.instruction |= (inst.operands[1].imm & 0x03) << 6; | |
9889 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9890 | } |
9891 | ||
c19d1205 ZW |
9892 | static void |
9893 | do_t_bfi (void) | |
b99bd4ef | 9894 | { |
fdfde340 | 9895 | int Rd, Rn; |
c19d1205 | 9896 | unsigned int msb; |
b99bd4ef | 9897 | |
fdfde340 JM |
9898 | Rd = inst.operands[0].reg; |
9899 | reject_bad_reg (Rd); | |
9900 | ||
c19d1205 ZW |
9901 | /* #0 in second position is alternative syntax for bfc, which is |
9902 | the same instruction but with REG_PC in the Rm field. */ | |
9903 | if (!inst.operands[1].isreg) | |
fdfde340 JM |
9904 | Rn = REG_PC; |
9905 | else | |
9906 | { | |
9907 | Rn = inst.operands[1].reg; | |
9908 | reject_bad_reg (Rn); | |
9909 | } | |
b99bd4ef | 9910 | |
c19d1205 ZW |
9911 | msb = inst.operands[2].imm + inst.operands[3].imm; |
9912 | constraint (msb > 32, _("bit-field extends past end of register")); | |
9913 | /* The instruction encoding stores the LSB and MSB, | |
9914 | not the LSB and width. */ | |
fdfde340 JM |
9915 | inst.instruction |= Rd << 8; |
9916 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9917 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9918 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9919 | inst.instruction |= msb - 1; | |
b99bd4ef NC |
9920 | } |
9921 | ||
c19d1205 ZW |
9922 | static void |
9923 | do_t_bfx (void) | |
b99bd4ef | 9924 | { |
fdfde340 JM |
9925 | unsigned Rd, Rn; |
9926 | ||
9927 | Rd = inst.operands[0].reg; | |
9928 | Rn = inst.operands[1].reg; | |
9929 | ||
9930 | reject_bad_reg (Rd); | |
9931 | reject_bad_reg (Rn); | |
9932 | ||
c19d1205 ZW |
9933 | constraint (inst.operands[2].imm + inst.operands[3].imm > 32, |
9934 | _("bit-field extends past end of register")); | |
fdfde340 JM |
9935 | inst.instruction |= Rd << 8; |
9936 | inst.instruction |= Rn << 16; | |
c19d1205 ZW |
9937 | inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; |
9938 | inst.instruction |= (inst.operands[2].imm & 0x03) << 6; | |
9939 | inst.instruction |= inst.operands[3].imm - 1; | |
9940 | } | |
b99bd4ef | 9941 | |
c19d1205 ZW |
9942 | /* ARM V5 Thumb BLX (argument parse) |
9943 | BLX <target_addr> which is BLX(1) | |
9944 | BLX <Rm> which is BLX(2) | |
9945 | Unfortunately, there are two different opcodes for this mnemonic. | |
9946 | So, the insns[].value is not used, and the code here zaps values | |
9947 | into inst.instruction. | |
b99bd4ef | 9948 | |
c19d1205 ZW |
9949 | ??? How to take advantage of the additional two bits of displacement |
9950 | available in Thumb32 mode? Need new relocation? */ | |
b99bd4ef | 9951 | |
c19d1205 ZW |
9952 | static void |
9953 | do_t_blx (void) | |
9954 | { | |
e07e6e58 NC |
9955 | set_it_insn_type_last (); |
9956 | ||
c19d1205 | 9957 | if (inst.operands[0].isreg) |
fdfde340 JM |
9958 | { |
9959 | constraint (inst.operands[0].reg == REG_PC, BAD_PC); | |
9960 | /* We have a register, so this is BLX(2). */ | |
9961 | inst.instruction |= inst.operands[0].reg << 3; | |
9962 | } | |
b99bd4ef NC |
9963 | else |
9964 | { | |
c19d1205 | 9965 | /* No register. This must be BLX(1). */ |
2fc8bdac | 9966 | inst.instruction = 0xf000e800; |
0855e32b | 9967 | encode_branch (BFD_RELOC_THUMB_PCREL_BLX); |
b99bd4ef NC |
9968 | } |
9969 | } | |
9970 | ||
c19d1205 ZW |
9971 | static void |
9972 | do_t_branch (void) | |
b99bd4ef | 9973 | { |
0110f2b8 | 9974 | int opcode; |
dfa9f0d5 | 9975 | int cond; |
9ae92b05 | 9976 | int reloc; |
dfa9f0d5 | 9977 | |
e07e6e58 NC |
9978 | cond = inst.cond; |
9979 | set_it_insn_type (IF_INSIDE_IT_LAST_INSN); | |
9980 | ||
9981 | if (in_it_block ()) | |
dfa9f0d5 PB |
9982 | { |
9983 | /* Conditional branches inside IT blocks are encoded as unconditional | |
9984 | branches. */ | |
9985 | cond = COND_ALWAYS; | |
dfa9f0d5 PB |
9986 | } |
9987 | else | |
9988 | cond = inst.cond; | |
9989 | ||
9990 | if (cond != COND_ALWAYS) | |
0110f2b8 PB |
9991 | opcode = T_MNEM_bcond; |
9992 | else | |
9993 | opcode = inst.instruction; | |
9994 | ||
12d6b0b7 RS |
9995 | if (unified_syntax |
9996 | && (inst.size_req == 4 | |
10960bfb PB |
9997 | || (inst.size_req != 2 |
9998 | && (inst.operands[0].hasreloc | |
9999 | || inst.reloc.exp.X_op == O_constant)))) | |
c19d1205 | 10000 | { |
0110f2b8 | 10001 | inst.instruction = THUMB_OP32(opcode); |
dfa9f0d5 | 10002 | if (cond == COND_ALWAYS) |
9ae92b05 | 10003 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; |
c19d1205 ZW |
10004 | else |
10005 | { | |
9c2799c2 | 10006 | gas_assert (cond != 0xF); |
dfa9f0d5 | 10007 | inst.instruction |= cond << 22; |
9ae92b05 | 10008 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; |
c19d1205 ZW |
10009 | } |
10010 | } | |
b99bd4ef NC |
10011 | else |
10012 | { | |
0110f2b8 | 10013 | inst.instruction = THUMB_OP16(opcode); |
dfa9f0d5 | 10014 | if (cond == COND_ALWAYS) |
9ae92b05 | 10015 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH12; |
c19d1205 | 10016 | else |
b99bd4ef | 10017 | { |
dfa9f0d5 | 10018 | inst.instruction |= cond << 8; |
9ae92b05 | 10019 | reloc = BFD_RELOC_THUMB_PCREL_BRANCH9; |
b99bd4ef | 10020 | } |
0110f2b8 PB |
10021 | /* Allow section relaxation. */ |
10022 | if (unified_syntax && inst.size_req != 2) | |
10023 | inst.relax = opcode; | |
b99bd4ef | 10024 | } |
9ae92b05 | 10025 | inst.reloc.type = reloc; |
c19d1205 | 10026 | inst.reloc.pc_rel = 1; |
b99bd4ef NC |
10027 | } |
10028 | ||
10029 | static void | |
c19d1205 | 10030 | do_t_bkpt (void) |
b99bd4ef | 10031 | { |
dfa9f0d5 PB |
10032 | constraint (inst.cond != COND_ALWAYS, |
10033 | _("instruction is always unconditional")); | |
c19d1205 | 10034 | if (inst.operands[0].present) |
b99bd4ef | 10035 | { |
c19d1205 ZW |
10036 | constraint (inst.operands[0].imm > 255, |
10037 | _("immediate value out of range")); | |
10038 | inst.instruction |= inst.operands[0].imm; | |
e07e6e58 | 10039 | set_it_insn_type (NEUTRAL_IT_INSN); |
b99bd4ef | 10040 | } |
b99bd4ef NC |
10041 | } |
10042 | ||
10043 | static void | |
c19d1205 | 10044 | do_t_branch23 (void) |
b99bd4ef | 10045 | { |
e07e6e58 | 10046 | set_it_insn_type_last (); |
0855e32b NS |
10047 | encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23); |
10048 | ||
10049 | /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in | |
10050 | this file. We used to simply ignore the PLT reloc type here -- | |
10051 | the branch encoding is now needed to deal with TLSCALL relocs. | |
10052 | So if we see a PLT reloc now, put it back to how it used to be to | |
10053 | keep the preexisting behaviour. */ | |
10054 | if (inst.reloc.type == BFD_RELOC_ARM_PLT32) | |
10055 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
90e4755a | 10056 | |
4343666d | 10057 | #if defined(OBJ_COFF) |
c19d1205 ZW |
10058 | /* If the destination of the branch is a defined symbol which does not have |
10059 | the THUMB_FUNC attribute, then we must be calling a function which has | |
10060 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
10061 | function and change the branch to refer to that function instead. */ | |
10062 | if ( inst.reloc.exp.X_op == O_symbol | |
10063 | && inst.reloc.exp.X_add_symbol != NULL | |
10064 | && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) | |
10065 | && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) | |
10066 | inst.reloc.exp.X_add_symbol = | |
10067 | find_real_start (inst.reloc.exp.X_add_symbol); | |
4343666d | 10068 | #endif |
90e4755a RE |
10069 | } |
10070 | ||
10071 | static void | |
c19d1205 | 10072 | do_t_bx (void) |
90e4755a | 10073 | { |
e07e6e58 | 10074 | set_it_insn_type_last (); |
c19d1205 ZW |
10075 | inst.instruction |= inst.operands[0].reg << 3; |
10076 | /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc | |
10077 | should cause the alignment to be checked once it is known. This is | |
10078 | because BX PC only works if the instruction is word aligned. */ | |
10079 | } | |
90e4755a | 10080 | |
c19d1205 ZW |
10081 | static void |
10082 | do_t_bxj (void) | |
10083 | { | |
fdfde340 | 10084 | int Rm; |
90e4755a | 10085 | |
e07e6e58 | 10086 | set_it_insn_type_last (); |
fdfde340 JM |
10087 | Rm = inst.operands[0].reg; |
10088 | reject_bad_reg (Rm); | |
10089 | inst.instruction |= Rm << 16; | |
90e4755a RE |
10090 | } |
10091 | ||
10092 | static void | |
c19d1205 | 10093 | do_t_clz (void) |
90e4755a | 10094 | { |
fdfde340 JM |
10095 | unsigned Rd; |
10096 | unsigned Rm; | |
10097 | ||
10098 | Rd = inst.operands[0].reg; | |
10099 | Rm = inst.operands[1].reg; | |
10100 | ||
10101 | reject_bad_reg (Rd); | |
10102 | reject_bad_reg (Rm); | |
10103 | ||
10104 | inst.instruction |= Rd << 8; | |
10105 | inst.instruction |= Rm << 16; | |
10106 | inst.instruction |= Rm; | |
c19d1205 | 10107 | } |
90e4755a | 10108 | |
dfa9f0d5 PB |
10109 | static void |
10110 | do_t_cps (void) | |
10111 | { | |
e07e6e58 | 10112 | set_it_insn_type (OUTSIDE_IT_INSN); |
dfa9f0d5 PB |
10113 | inst.instruction |= inst.operands[0].imm; |
10114 | } | |
10115 | ||
c19d1205 ZW |
10116 | static void |
10117 | do_t_cpsi (void) | |
10118 | { | |
e07e6e58 | 10119 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 | 10120 | if (unified_syntax |
62b3e311 PB |
10121 | && (inst.operands[1].present || inst.size_req == 4) |
10122 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) | |
90e4755a | 10123 | { |
c19d1205 ZW |
10124 | unsigned int imod = (inst.instruction & 0x0030) >> 4; |
10125 | inst.instruction = 0xf3af8000; | |
10126 | inst.instruction |= imod << 9; | |
10127 | inst.instruction |= inst.operands[0].imm << 5; | |
10128 | if (inst.operands[1].present) | |
10129 | inst.instruction |= 0x100 | inst.operands[1].imm; | |
90e4755a | 10130 | } |
c19d1205 | 10131 | else |
90e4755a | 10132 | { |
62b3e311 PB |
10133 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) |
10134 | && (inst.operands[0].imm & 4), | |
10135 | _("selected processor does not support 'A' form " | |
10136 | "of this instruction")); | |
10137 | constraint (inst.operands[1].present || inst.size_req == 4, | |
c19d1205 ZW |
10138 | _("Thumb does not support the 2-argument " |
10139 | "form of this instruction")); | |
10140 | inst.instruction |= inst.operands[0].imm; | |
90e4755a | 10141 | } |
90e4755a RE |
10142 | } |
10143 | ||
c19d1205 ZW |
10144 | /* THUMB CPY instruction (argument parse). */ |
10145 | ||
90e4755a | 10146 | static void |
c19d1205 | 10147 | do_t_cpy (void) |
90e4755a | 10148 | { |
c19d1205 | 10149 | if (inst.size_req == 4) |
90e4755a | 10150 | { |
c19d1205 ZW |
10151 | inst.instruction = THUMB_OP32 (T_MNEM_mov); |
10152 | inst.instruction |= inst.operands[0].reg << 8; | |
10153 | inst.instruction |= inst.operands[1].reg; | |
90e4755a | 10154 | } |
c19d1205 | 10155 | else |
90e4755a | 10156 | { |
c19d1205 ZW |
10157 | inst.instruction |= (inst.operands[0].reg & 0x8) << 4; |
10158 | inst.instruction |= (inst.operands[0].reg & 0x7); | |
10159 | inst.instruction |= inst.operands[1].reg << 3; | |
90e4755a | 10160 | } |
90e4755a RE |
10161 | } |
10162 | ||
90e4755a | 10163 | static void |
25fe350b | 10164 | do_t_cbz (void) |
90e4755a | 10165 | { |
e07e6e58 | 10166 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
10167 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10168 | inst.instruction |= inst.operands[0].reg; | |
10169 | inst.reloc.pc_rel = 1; | |
10170 | inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; | |
10171 | } | |
90e4755a | 10172 | |
62b3e311 PB |
10173 | static void |
10174 | do_t_dbg (void) | |
10175 | { | |
10176 | inst.instruction |= inst.operands[0].imm; | |
10177 | } | |
10178 | ||
10179 | static void | |
10180 | do_t_div (void) | |
10181 | { | |
fdfde340 JM |
10182 | unsigned Rd, Rn, Rm; |
10183 | ||
10184 | Rd = inst.operands[0].reg; | |
10185 | Rn = (inst.operands[1].present | |
10186 | ? inst.operands[1].reg : Rd); | |
10187 | Rm = inst.operands[2].reg; | |
10188 | ||
10189 | reject_bad_reg (Rd); | |
10190 | reject_bad_reg (Rn); | |
10191 | reject_bad_reg (Rm); | |
10192 | ||
10193 | inst.instruction |= Rd << 8; | |
10194 | inst.instruction |= Rn << 16; | |
10195 | inst.instruction |= Rm; | |
62b3e311 PB |
10196 | } |
10197 | ||
c19d1205 ZW |
10198 | static void |
10199 | do_t_hint (void) | |
10200 | { | |
10201 | if (unified_syntax && inst.size_req == 4) | |
10202 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10203 | else | |
10204 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10205 | } | |
90e4755a | 10206 | |
c19d1205 ZW |
10207 | static void |
10208 | do_t_it (void) | |
10209 | { | |
10210 | unsigned int cond = inst.operands[0].imm; | |
e27ec89e | 10211 | |
e07e6e58 NC |
10212 | set_it_insn_type (IT_INSN); |
10213 | now_it.mask = (inst.instruction & 0xf) | 0x10; | |
10214 | now_it.cc = cond; | |
e27ec89e PB |
10215 | |
10216 | /* If the condition is a negative condition, invert the mask. */ | |
c19d1205 | 10217 | if ((cond & 0x1) == 0x0) |
90e4755a | 10218 | { |
c19d1205 | 10219 | unsigned int mask = inst.instruction & 0x000f; |
90e4755a | 10220 | |
c19d1205 ZW |
10221 | if ((mask & 0x7) == 0) |
10222 | /* no conversion needed */; | |
10223 | else if ((mask & 0x3) == 0) | |
e27ec89e PB |
10224 | mask ^= 0x8; |
10225 | else if ((mask & 0x1) == 0) | |
10226 | mask ^= 0xC; | |
c19d1205 | 10227 | else |
e27ec89e | 10228 | mask ^= 0xE; |
90e4755a | 10229 | |
e27ec89e PB |
10230 | inst.instruction &= 0xfff0; |
10231 | inst.instruction |= mask; | |
c19d1205 | 10232 | } |
90e4755a | 10233 | |
c19d1205 ZW |
10234 | inst.instruction |= cond << 4; |
10235 | } | |
90e4755a | 10236 | |
3c707909 PB |
10237 | /* Helper function used for both push/pop and ldm/stm. */ |
10238 | static void | |
10239 | encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) | |
10240 | { | |
10241 | bfd_boolean load; | |
10242 | ||
10243 | load = (inst.instruction & (1 << 20)) != 0; | |
10244 | ||
10245 | if (mask & (1 << 13)) | |
10246 | inst.error = _("SP not allowed in register list"); | |
1e5b0379 NC |
10247 | |
10248 | if ((mask & (1 << base)) != 0 | |
10249 | && writeback) | |
10250 | inst.error = _("having the base register in the register list when " | |
10251 | "using write back is UNPREDICTABLE"); | |
10252 | ||
3c707909 PB |
10253 | if (load) |
10254 | { | |
e07e6e58 NC |
10255 | if (mask & (1 << 15)) |
10256 | { | |
10257 | if (mask & (1 << 14)) | |
10258 | inst.error = _("LR and PC should not both be in register list"); | |
10259 | else | |
10260 | set_it_insn_type_last (); | |
10261 | } | |
3c707909 PB |
10262 | } |
10263 | else | |
10264 | { | |
10265 | if (mask & (1 << 15)) | |
10266 | inst.error = _("PC not allowed in register list"); | |
3c707909 PB |
10267 | } |
10268 | ||
10269 | if ((mask & (mask - 1)) == 0) | |
10270 | { | |
10271 | /* Single register transfers implemented as str/ldr. */ | |
10272 | if (writeback) | |
10273 | { | |
10274 | if (inst.instruction & (1 << 23)) | |
10275 | inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ | |
10276 | else | |
10277 | inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ | |
10278 | } | |
10279 | else | |
10280 | { | |
10281 | if (inst.instruction & (1 << 23)) | |
10282 | inst.instruction = 0x00800000; /* ia -> [base] */ | |
10283 | else | |
10284 | inst.instruction = 0x00000c04; /* db -> [base, #-4] */ | |
10285 | } | |
10286 | ||
10287 | inst.instruction |= 0xf8400000; | |
10288 | if (load) | |
10289 | inst.instruction |= 0x00100000; | |
10290 | ||
5f4273c7 | 10291 | mask = ffs (mask) - 1; |
3c707909 PB |
10292 | mask <<= 12; |
10293 | } | |
10294 | else if (writeback) | |
10295 | inst.instruction |= WRITE_BACK; | |
10296 | ||
10297 | inst.instruction |= mask; | |
10298 | inst.instruction |= base << 16; | |
10299 | } | |
10300 | ||
c19d1205 ZW |
10301 | static void |
10302 | do_t_ldmstm (void) | |
10303 | { | |
10304 | /* This really doesn't seem worth it. */ | |
10305 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
10306 | _("expression too complex")); | |
10307 | constraint (inst.operands[1].writeback, | |
10308 | _("Thumb load/store multiple does not support {reglist}^")); | |
90e4755a | 10309 | |
c19d1205 ZW |
10310 | if (unified_syntax) |
10311 | { | |
3c707909 PB |
10312 | bfd_boolean narrow; |
10313 | unsigned mask; | |
10314 | ||
10315 | narrow = FALSE; | |
c19d1205 ZW |
10316 | /* See if we can use a 16-bit instruction. */ |
10317 | if (inst.instruction < 0xffff /* not ldmdb/stmdb */ | |
10318 | && inst.size_req != 4 | |
3c707909 | 10319 | && !(inst.operands[1].imm & ~0xff)) |
90e4755a | 10320 | { |
3c707909 | 10321 | mask = 1 << inst.operands[0].reg; |
90e4755a | 10322 | |
eab4f823 | 10323 | if (inst.operands[0].reg <= 7) |
90e4755a | 10324 | { |
3c707909 | 10325 | if (inst.instruction == T_MNEM_stmia |
eab4f823 MGD |
10326 | ? inst.operands[0].writeback |
10327 | : (inst.operands[0].writeback | |
10328 | == !(inst.operands[1].imm & mask))) | |
10329 | { | |
10330 | if (inst.instruction == T_MNEM_stmia | |
10331 | && (inst.operands[1].imm & mask) | |
10332 | && (inst.operands[1].imm & (mask - 1))) | |
10333 | as_warn (_("value stored for r%d is UNKNOWN"), | |
10334 | inst.operands[0].reg); | |
3c707909 | 10335 | |
eab4f823 MGD |
10336 | inst.instruction = THUMB_OP16 (inst.instruction); |
10337 | inst.instruction |= inst.operands[0].reg << 8; | |
10338 | inst.instruction |= inst.operands[1].imm; | |
10339 | narrow = TRUE; | |
10340 | } | |
10341 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
10342 | { | |
10343 | /* This means 1 register in reg list one of 3 situations: | |
10344 | 1. Instruction is stmia, but without writeback. | |
10345 | 2. lmdia without writeback, but with Rn not in | |
10346 | reglist. | |
10347 | 3. ldmia with writeback, but with Rn in reglist. | |
10348 | Case 3 is UNPREDICTABLE behaviour, so we handle | |
10349 | case 1 and 2 which can be converted into a 16-bit | |
10350 | str or ldr. The SP cases are handled below. */ | |
10351 | unsigned long opcode; | |
10352 | /* First, record an error for Case 3. */ | |
10353 | if (inst.operands[1].imm & mask | |
10354 | && inst.operands[0].writeback) | |
10355 | inst.error = | |
10356 | _("having the base register in the register list when " | |
10357 | "using write back is UNPREDICTABLE"); | |
10358 | ||
10359 | opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str | |
10360 | : T_MNEM_ldr); | |
10361 | inst.instruction = THUMB_OP16 (opcode); | |
10362 | inst.instruction |= inst.operands[0].reg << 3; | |
10363 | inst.instruction |= (ffs (inst.operands[1].imm)-1); | |
10364 | narrow = TRUE; | |
10365 | } | |
90e4755a | 10366 | } |
eab4f823 | 10367 | else if (inst.operands[0] .reg == REG_SP) |
90e4755a | 10368 | { |
eab4f823 MGD |
10369 | if (inst.operands[0].writeback) |
10370 | { | |
10371 | inst.instruction = | |
10372 | THUMB_OP16 (inst.instruction == T_MNEM_stmia | |
10373 | ? T_MNEM_push : T_MNEM_pop); | |
10374 | inst.instruction |= inst.operands[1].imm; | |
10375 | narrow = TRUE; | |
10376 | } | |
10377 | else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0) | |
10378 | { | |
10379 | inst.instruction = | |
10380 | THUMB_OP16 (inst.instruction == T_MNEM_stmia | |
10381 | ? T_MNEM_str_sp : T_MNEM_ldr_sp); | |
10382 | inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8); | |
10383 | narrow = TRUE; | |
10384 | } | |
90e4755a | 10385 | } |
3c707909 PB |
10386 | } |
10387 | ||
10388 | if (!narrow) | |
10389 | { | |
c19d1205 ZW |
10390 | if (inst.instruction < 0xffff) |
10391 | inst.instruction = THUMB_OP32 (inst.instruction); | |
3c707909 | 10392 | |
5f4273c7 NC |
10393 | encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm, |
10394 | inst.operands[0].writeback); | |
90e4755a RE |
10395 | } |
10396 | } | |
c19d1205 | 10397 | else |
90e4755a | 10398 | { |
c19d1205 ZW |
10399 | constraint (inst.operands[0].reg > 7 |
10400 | || (inst.operands[1].imm & ~0xff), BAD_HIREG); | |
1198ca51 PB |
10401 | constraint (inst.instruction != T_MNEM_ldmia |
10402 | && inst.instruction != T_MNEM_stmia, | |
10403 | _("Thumb-2 instruction only valid in unified syntax")); | |
c19d1205 | 10404 | if (inst.instruction == T_MNEM_stmia) |
f03698e6 | 10405 | { |
c19d1205 ZW |
10406 | if (!inst.operands[0].writeback) |
10407 | as_warn (_("this instruction will write back the base register")); | |
10408 | if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) | |
10409 | && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) | |
1e5b0379 | 10410 | as_warn (_("value stored for r%d is UNKNOWN"), |
c19d1205 | 10411 | inst.operands[0].reg); |
f03698e6 | 10412 | } |
c19d1205 | 10413 | else |
90e4755a | 10414 | { |
c19d1205 ZW |
10415 | if (!inst.operands[0].writeback |
10416 | && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10417 | as_warn (_("this instruction will write back the base register")); | |
10418 | else if (inst.operands[0].writeback | |
10419 | && (inst.operands[1].imm & (1 << inst.operands[0].reg))) | |
10420 | as_warn (_("this instruction will not write back the base register")); | |
90e4755a RE |
10421 | } |
10422 | ||
c19d1205 ZW |
10423 | inst.instruction = THUMB_OP16 (inst.instruction); |
10424 | inst.instruction |= inst.operands[0].reg << 8; | |
10425 | inst.instruction |= inst.operands[1].imm; | |
10426 | } | |
10427 | } | |
e28cd48c | 10428 | |
c19d1205 ZW |
10429 | static void |
10430 | do_t_ldrex (void) | |
10431 | { | |
10432 | constraint (!inst.operands[1].isreg || !inst.operands[1].preind | |
10433 | || inst.operands[1].postind || inst.operands[1].writeback | |
10434 | || inst.operands[1].immisreg || inst.operands[1].shifted | |
10435 | || inst.operands[1].negative, | |
01cfc07f | 10436 | BAD_ADDR_MODE); |
e28cd48c | 10437 | |
5be8be5d DG |
10438 | constraint ((inst.operands[1].reg == REG_PC), BAD_PC); |
10439 | ||
c19d1205 ZW |
10440 | inst.instruction |= inst.operands[0].reg << 12; |
10441 | inst.instruction |= inst.operands[1].reg << 16; | |
10442 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
10443 | } | |
e28cd48c | 10444 | |
c19d1205 ZW |
10445 | static void |
10446 | do_t_ldrexd (void) | |
10447 | { | |
10448 | if (!inst.operands[1].present) | |
1cac9012 | 10449 | { |
c19d1205 ZW |
10450 | constraint (inst.operands[0].reg == REG_LR, |
10451 | _("r14 not allowed as first register " | |
10452 | "when second register is omitted")); | |
10453 | inst.operands[1].reg = inst.operands[0].reg + 1; | |
b99bd4ef | 10454 | } |
c19d1205 ZW |
10455 | constraint (inst.operands[0].reg == inst.operands[1].reg, |
10456 | BAD_OVERLAP); | |
b99bd4ef | 10457 | |
c19d1205 ZW |
10458 | inst.instruction |= inst.operands[0].reg << 12; |
10459 | inst.instruction |= inst.operands[1].reg << 8; | |
10460 | inst.instruction |= inst.operands[2].reg << 16; | |
b99bd4ef NC |
10461 | } |
10462 | ||
10463 | static void | |
c19d1205 | 10464 | do_t_ldst (void) |
b99bd4ef | 10465 | { |
0110f2b8 PB |
10466 | unsigned long opcode; |
10467 | int Rn; | |
10468 | ||
e07e6e58 NC |
10469 | if (inst.operands[0].isreg |
10470 | && !inst.operands[0].preind | |
10471 | && inst.operands[0].reg == REG_PC) | |
10472 | set_it_insn_type_last (); | |
10473 | ||
0110f2b8 | 10474 | opcode = inst.instruction; |
c19d1205 | 10475 | if (unified_syntax) |
b99bd4ef | 10476 | { |
53365c0d PB |
10477 | if (!inst.operands[1].isreg) |
10478 | { | |
10479 | if (opcode <= 0xffff) | |
10480 | inst.instruction = THUMB_OP32 (opcode); | |
10481 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10482 | return; | |
10483 | } | |
0110f2b8 PB |
10484 | if (inst.operands[1].isreg |
10485 | && !inst.operands[1].writeback | |
c19d1205 ZW |
10486 | && !inst.operands[1].shifted && !inst.operands[1].postind |
10487 | && !inst.operands[1].negative && inst.operands[0].reg <= 7 | |
0110f2b8 PB |
10488 | && opcode <= 0xffff |
10489 | && inst.size_req != 4) | |
c19d1205 | 10490 | { |
0110f2b8 PB |
10491 | /* Insn may have a 16-bit form. */ |
10492 | Rn = inst.operands[1].reg; | |
10493 | if (inst.operands[1].immisreg) | |
10494 | { | |
10495 | inst.instruction = THUMB_OP16 (opcode); | |
5f4273c7 | 10496 | /* [Rn, Rik] */ |
0110f2b8 PB |
10497 | if (Rn <= 7 && inst.operands[1].imm <= 7) |
10498 | goto op16; | |
5be8be5d DG |
10499 | else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str) |
10500 | reject_bad_reg (inst.operands[1].imm); | |
0110f2b8 PB |
10501 | } |
10502 | else if ((Rn <= 7 && opcode != T_MNEM_ldrsh | |
10503 | && opcode != T_MNEM_ldrsb) | |
10504 | || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) | |
10505 | || (Rn == REG_SP && opcode == T_MNEM_str)) | |
10506 | { | |
10507 | /* [Rn, #const] */ | |
10508 | if (Rn > 7) | |
10509 | { | |
10510 | if (Rn == REG_PC) | |
10511 | { | |
10512 | if (inst.reloc.pc_rel) | |
10513 | opcode = T_MNEM_ldr_pc2; | |
10514 | else | |
10515 | opcode = T_MNEM_ldr_pc; | |
10516 | } | |
10517 | else | |
10518 | { | |
10519 | if (opcode == T_MNEM_ldr) | |
10520 | opcode = T_MNEM_ldr_sp; | |
10521 | else | |
10522 | opcode = T_MNEM_str_sp; | |
10523 | } | |
10524 | inst.instruction = inst.operands[0].reg << 8; | |
10525 | } | |
10526 | else | |
10527 | { | |
10528 | inst.instruction = inst.operands[0].reg; | |
10529 | inst.instruction |= inst.operands[1].reg << 3; | |
10530 | } | |
10531 | inst.instruction |= THUMB_OP16 (opcode); | |
10532 | if (inst.size_req == 2) | |
10533 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10534 | else | |
10535 | inst.relax = opcode; | |
10536 | return; | |
10537 | } | |
c19d1205 | 10538 | } |
0110f2b8 | 10539 | /* Definitely a 32-bit variant. */ |
5be8be5d | 10540 | |
8d67f500 NC |
10541 | /* Warning for Erratum 752419. */ |
10542 | if (opcode == T_MNEM_ldr | |
10543 | && inst.operands[0].reg == REG_SP | |
10544 | && inst.operands[1].writeback == 1 | |
10545 | && !inst.operands[1].immisreg) | |
10546 | { | |
10547 | if (no_cpu_selected () | |
10548 | || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7) | |
10549 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a) | |
10550 | && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r))) | |
10551 | as_warn (_("This instruction may be unpredictable " | |
10552 | "if executed on M-profile cores " | |
10553 | "with interrupts enabled.")); | |
10554 | } | |
10555 | ||
5be8be5d | 10556 | /* Do some validations regarding addressing modes. */ |
1be5fd2e | 10557 | if (inst.operands[1].immisreg) |
5be8be5d DG |
10558 | reject_bad_reg (inst.operands[1].imm); |
10559 | ||
1be5fd2e NC |
10560 | constraint (inst.operands[1].writeback == 1 |
10561 | && inst.operands[0].reg == inst.operands[1].reg, | |
10562 | BAD_OVERLAP); | |
10563 | ||
0110f2b8 | 10564 | inst.instruction = THUMB_OP32 (opcode); |
c19d1205 ZW |
10565 | inst.instruction |= inst.operands[0].reg << 12; |
10566 | encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); | |
1be5fd2e | 10567 | check_ldr_r15_aligned (); |
b99bd4ef NC |
10568 | return; |
10569 | } | |
10570 | ||
c19d1205 ZW |
10571 | constraint (inst.operands[0].reg > 7, BAD_HIREG); |
10572 | ||
10573 | if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) | |
b99bd4ef | 10574 | { |
c19d1205 ZW |
10575 | /* Only [Rn,Rm] is acceptable. */ |
10576 | constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); | |
10577 | constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg | |
10578 | || inst.operands[1].postind || inst.operands[1].shifted | |
10579 | || inst.operands[1].negative, | |
10580 | _("Thumb does not support this addressing mode")); | |
10581 | inst.instruction = THUMB_OP16 (inst.instruction); | |
10582 | goto op16; | |
b99bd4ef | 10583 | } |
5f4273c7 | 10584 | |
c19d1205 ZW |
10585 | inst.instruction = THUMB_OP16 (inst.instruction); |
10586 | if (!inst.operands[1].isreg) | |
10587 | if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) | |
10588 | return; | |
b99bd4ef | 10589 | |
c19d1205 ZW |
10590 | constraint (!inst.operands[1].preind |
10591 | || inst.operands[1].shifted | |
10592 | || inst.operands[1].writeback, | |
10593 | _("Thumb does not support this addressing mode")); | |
10594 | if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) | |
90e4755a | 10595 | { |
c19d1205 ZW |
10596 | constraint (inst.instruction & 0x0600, |
10597 | _("byte or halfword not valid for base register")); | |
10598 | constraint (inst.operands[1].reg == REG_PC | |
10599 | && !(inst.instruction & THUMB_LOAD_BIT), | |
10600 | _("r15 based store not allowed")); | |
10601 | constraint (inst.operands[1].immisreg, | |
10602 | _("invalid base register for register offset")); | |
b99bd4ef | 10603 | |
c19d1205 ZW |
10604 | if (inst.operands[1].reg == REG_PC) |
10605 | inst.instruction = T_OPCODE_LDR_PC; | |
10606 | else if (inst.instruction & THUMB_LOAD_BIT) | |
10607 | inst.instruction = T_OPCODE_LDR_SP; | |
10608 | else | |
10609 | inst.instruction = T_OPCODE_STR_SP; | |
b99bd4ef | 10610 | |
c19d1205 ZW |
10611 | inst.instruction |= inst.operands[0].reg << 8; |
10612 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10613 | return; | |
10614 | } | |
90e4755a | 10615 | |
c19d1205 ZW |
10616 | constraint (inst.operands[1].reg > 7, BAD_HIREG); |
10617 | if (!inst.operands[1].immisreg) | |
10618 | { | |
10619 | /* Immediate offset. */ | |
10620 | inst.instruction |= inst.operands[0].reg; | |
10621 | inst.instruction |= inst.operands[1].reg << 3; | |
10622 | inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; | |
10623 | return; | |
10624 | } | |
90e4755a | 10625 | |
c19d1205 ZW |
10626 | /* Register offset. */ |
10627 | constraint (inst.operands[1].imm > 7, BAD_HIREG); | |
10628 | constraint (inst.operands[1].negative, | |
10629 | _("Thumb does not support this addressing mode")); | |
90e4755a | 10630 | |
c19d1205 ZW |
10631 | op16: |
10632 | switch (inst.instruction) | |
10633 | { | |
10634 | case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; | |
10635 | case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; | |
10636 | case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; | |
10637 | case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; | |
10638 | case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; | |
10639 | case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; | |
10640 | case 0x5600 /* ldrsb */: | |
10641 | case 0x5e00 /* ldrsh */: break; | |
10642 | default: abort (); | |
10643 | } | |
90e4755a | 10644 | |
c19d1205 ZW |
10645 | inst.instruction |= inst.operands[0].reg; |
10646 | inst.instruction |= inst.operands[1].reg << 3; | |
10647 | inst.instruction |= inst.operands[1].imm << 6; | |
10648 | } | |
90e4755a | 10649 | |
c19d1205 ZW |
10650 | static void |
10651 | do_t_ldstd (void) | |
10652 | { | |
10653 | if (!inst.operands[1].present) | |
b99bd4ef | 10654 | { |
c19d1205 ZW |
10655 | inst.operands[1].reg = inst.operands[0].reg + 1; |
10656 | constraint (inst.operands[0].reg == REG_LR, | |
10657 | _("r14 not allowed here")); | |
bd340a04 MGD |
10658 | constraint (inst.operands[0].reg == REG_R12, |
10659 | _("r12 not allowed here")); | |
b99bd4ef | 10660 | } |
bd340a04 MGD |
10661 | |
10662 | if (inst.operands[2].writeback | |
10663 | && (inst.operands[0].reg == inst.operands[2].reg | |
10664 | || inst.operands[1].reg == inst.operands[2].reg)) | |
10665 | as_warn (_("base register written back, and overlaps " | |
10666 | "one of transfer registers")); | |
10667 | ||
c19d1205 ZW |
10668 | inst.instruction |= inst.operands[0].reg << 12; |
10669 | inst.instruction |= inst.operands[1].reg << 8; | |
10670 | encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); | |
b99bd4ef NC |
10671 | } |
10672 | ||
c19d1205 ZW |
10673 | static void |
10674 | do_t_ldstt (void) | |
10675 | { | |
10676 | inst.instruction |= inst.operands[0].reg << 12; | |
10677 | encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); | |
10678 | } | |
a737bd4d | 10679 | |
b99bd4ef | 10680 | static void |
c19d1205 | 10681 | do_t_mla (void) |
b99bd4ef | 10682 | { |
fdfde340 | 10683 | unsigned Rd, Rn, Rm, Ra; |
c921be7d | 10684 | |
fdfde340 JM |
10685 | Rd = inst.operands[0].reg; |
10686 | Rn = inst.operands[1].reg; | |
10687 | Rm = inst.operands[2].reg; | |
10688 | Ra = inst.operands[3].reg; | |
10689 | ||
10690 | reject_bad_reg (Rd); | |
10691 | reject_bad_reg (Rn); | |
10692 | reject_bad_reg (Rm); | |
10693 | reject_bad_reg (Ra); | |
10694 | ||
10695 | inst.instruction |= Rd << 8; | |
10696 | inst.instruction |= Rn << 16; | |
10697 | inst.instruction |= Rm; | |
10698 | inst.instruction |= Ra << 12; | |
c19d1205 | 10699 | } |
b99bd4ef | 10700 | |
c19d1205 ZW |
10701 | static void |
10702 | do_t_mlal (void) | |
10703 | { | |
fdfde340 JM |
10704 | unsigned RdLo, RdHi, Rn, Rm; |
10705 | ||
10706 | RdLo = inst.operands[0].reg; | |
10707 | RdHi = inst.operands[1].reg; | |
10708 | Rn = inst.operands[2].reg; | |
10709 | Rm = inst.operands[3].reg; | |
10710 | ||
10711 | reject_bad_reg (RdLo); | |
10712 | reject_bad_reg (RdHi); | |
10713 | reject_bad_reg (Rn); | |
10714 | reject_bad_reg (Rm); | |
10715 | ||
10716 | inst.instruction |= RdLo << 12; | |
10717 | inst.instruction |= RdHi << 8; | |
10718 | inst.instruction |= Rn << 16; | |
10719 | inst.instruction |= Rm; | |
c19d1205 | 10720 | } |
b99bd4ef | 10721 | |
c19d1205 ZW |
10722 | static void |
10723 | do_t_mov_cmp (void) | |
10724 | { | |
fdfde340 JM |
10725 | unsigned Rn, Rm; |
10726 | ||
10727 | Rn = inst.operands[0].reg; | |
10728 | Rm = inst.operands[1].reg; | |
10729 | ||
e07e6e58 NC |
10730 | if (Rn == REG_PC) |
10731 | set_it_insn_type_last (); | |
10732 | ||
c19d1205 | 10733 | if (unified_syntax) |
b99bd4ef | 10734 | { |
c19d1205 ZW |
10735 | int r0off = (inst.instruction == T_MNEM_mov |
10736 | || inst.instruction == T_MNEM_movs) ? 8 : 16; | |
0110f2b8 | 10737 | unsigned long opcode; |
3d388997 PB |
10738 | bfd_boolean narrow; |
10739 | bfd_boolean low_regs; | |
10740 | ||
fdfde340 | 10741 | low_regs = (Rn <= 7 && Rm <= 7); |
0110f2b8 | 10742 | opcode = inst.instruction; |
e07e6e58 | 10743 | if (in_it_block ()) |
0110f2b8 | 10744 | narrow = opcode != T_MNEM_movs; |
3d388997 | 10745 | else |
0110f2b8 | 10746 | narrow = opcode != T_MNEM_movs || low_regs; |
3d388997 PB |
10747 | if (inst.size_req == 4 |
10748 | || inst.operands[1].shifted) | |
10749 | narrow = FALSE; | |
10750 | ||
efd81785 PB |
10751 | /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ |
10752 | if (opcode == T_MNEM_movs && inst.operands[1].isreg | |
10753 | && !inst.operands[1].shifted | |
fdfde340 JM |
10754 | && Rn == REG_PC |
10755 | && Rm == REG_LR) | |
efd81785 PB |
10756 | { |
10757 | inst.instruction = T2_SUBS_PC_LR; | |
10758 | return; | |
10759 | } | |
10760 | ||
fdfde340 JM |
10761 | if (opcode == T_MNEM_cmp) |
10762 | { | |
10763 | constraint (Rn == REG_PC, BAD_PC); | |
94206790 MM |
10764 | if (narrow) |
10765 | { | |
10766 | /* In the Thumb-2 ISA, use of R13 as Rm is deprecated, | |
10767 | but valid. */ | |
10768 | warn_deprecated_sp (Rm); | |
10769 | /* R15 was documented as a valid choice for Rm in ARMv6, | |
10770 | but as UNPREDICTABLE in ARMv7. ARM's proprietary | |
10771 | tools reject R15, so we do too. */ | |
10772 | constraint (Rm == REG_PC, BAD_PC); | |
10773 | } | |
10774 | else | |
10775 | reject_bad_reg (Rm); | |
fdfde340 JM |
10776 | } |
10777 | else if (opcode == T_MNEM_mov | |
10778 | || opcode == T_MNEM_movs) | |
10779 | { | |
10780 | if (inst.operands[1].isreg) | |
10781 | { | |
10782 | if (opcode == T_MNEM_movs) | |
10783 | { | |
10784 | reject_bad_reg (Rn); | |
10785 | reject_bad_reg (Rm); | |
10786 | } | |
76fa04a4 MGD |
10787 | else if (narrow) |
10788 | { | |
10789 | /* This is mov.n. */ | |
10790 | if ((Rn == REG_SP || Rn == REG_PC) | |
10791 | && (Rm == REG_SP || Rm == REG_PC)) | |
10792 | { | |
10793 | as_warn (_("Use of r%u as a source register is " | |
10794 | "deprecated when r%u is the destination " | |
10795 | "register."), Rm, Rn); | |
10796 | } | |
10797 | } | |
10798 | else | |
10799 | { | |
10800 | /* This is mov.w. */ | |
10801 | constraint (Rn == REG_PC, BAD_PC); | |
10802 | constraint (Rm == REG_PC, BAD_PC); | |
10803 | constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); | |
10804 | } | |
fdfde340 JM |
10805 | } |
10806 | else | |
10807 | reject_bad_reg (Rn); | |
10808 | } | |
10809 | ||
c19d1205 ZW |
10810 | if (!inst.operands[1].isreg) |
10811 | { | |
0110f2b8 | 10812 | /* Immediate operand. */ |
e07e6e58 | 10813 | if (!in_it_block () && opcode == T_MNEM_mov) |
0110f2b8 PB |
10814 | narrow = 0; |
10815 | if (low_regs && narrow) | |
10816 | { | |
10817 | inst.instruction = THUMB_OP16 (opcode); | |
fdfde340 | 10818 | inst.instruction |= Rn << 8; |
0110f2b8 PB |
10819 | if (inst.size_req == 2) |
10820 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; | |
10821 | else | |
10822 | inst.relax = opcode; | |
10823 | } | |
10824 | else | |
10825 | { | |
10826 | inst.instruction = THUMB_OP32 (inst.instruction); | |
10827 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 10828 | inst.instruction |= Rn << r0off; |
0110f2b8 PB |
10829 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
10830 | } | |
c19d1205 | 10831 | } |
728ca7c9 PB |
10832 | else if (inst.operands[1].shifted && inst.operands[1].immisreg |
10833 | && (inst.instruction == T_MNEM_mov | |
10834 | || inst.instruction == T_MNEM_movs)) | |
10835 | { | |
10836 | /* Register shifts are encoded as separate shift instructions. */ | |
10837 | bfd_boolean flags = (inst.instruction == T_MNEM_movs); | |
10838 | ||
e07e6e58 | 10839 | if (in_it_block ()) |
728ca7c9 PB |
10840 | narrow = !flags; |
10841 | else | |
10842 | narrow = flags; | |
10843 | ||
10844 | if (inst.size_req == 4) | |
10845 | narrow = FALSE; | |
10846 | ||
10847 | if (!low_regs || inst.operands[1].imm > 7) | |
10848 | narrow = FALSE; | |
10849 | ||
fdfde340 | 10850 | if (Rn != Rm) |
728ca7c9 PB |
10851 | narrow = FALSE; |
10852 | ||
10853 | switch (inst.operands[1].shift_kind) | |
10854 | { | |
10855 | case SHIFT_LSL: | |
10856 | opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); | |
10857 | break; | |
10858 | case SHIFT_ASR: | |
10859 | opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); | |
10860 | break; | |
10861 | case SHIFT_LSR: | |
10862 | opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); | |
10863 | break; | |
10864 | case SHIFT_ROR: | |
10865 | opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); | |
10866 | break; | |
10867 | default: | |
5f4273c7 | 10868 | abort (); |
728ca7c9 PB |
10869 | } |
10870 | ||
10871 | inst.instruction = opcode; | |
10872 | if (narrow) | |
10873 | { | |
fdfde340 | 10874 | inst.instruction |= Rn; |
728ca7c9 PB |
10875 | inst.instruction |= inst.operands[1].imm << 3; |
10876 | } | |
10877 | else | |
10878 | { | |
10879 | if (flags) | |
10880 | inst.instruction |= CONDS_BIT; | |
10881 | ||
fdfde340 JM |
10882 | inst.instruction |= Rn << 8; |
10883 | inst.instruction |= Rm << 16; | |
728ca7c9 PB |
10884 | inst.instruction |= inst.operands[1].imm; |
10885 | } | |
10886 | } | |
3d388997 | 10887 | else if (!narrow) |
c19d1205 | 10888 | { |
728ca7c9 PB |
10889 | /* Some mov with immediate shift have narrow variants. |
10890 | Register shifts are handled above. */ | |
10891 | if (low_regs && inst.operands[1].shifted | |
10892 | && (inst.instruction == T_MNEM_mov | |
10893 | || inst.instruction == T_MNEM_movs)) | |
10894 | { | |
e07e6e58 | 10895 | if (in_it_block ()) |
728ca7c9 PB |
10896 | narrow = (inst.instruction == T_MNEM_mov); |
10897 | else | |
10898 | narrow = (inst.instruction == T_MNEM_movs); | |
10899 | } | |
10900 | ||
10901 | if (narrow) | |
10902 | { | |
10903 | switch (inst.operands[1].shift_kind) | |
10904 | { | |
10905 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
10906 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
10907 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; | |
10908 | default: narrow = FALSE; break; | |
10909 | } | |
10910 | } | |
10911 | ||
10912 | if (narrow) | |
10913 | { | |
fdfde340 JM |
10914 | inst.instruction |= Rn; |
10915 | inst.instruction |= Rm << 3; | |
728ca7c9 PB |
10916 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
10917 | } | |
10918 | else | |
10919 | { | |
10920 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 10921 | inst.instruction |= Rn << r0off; |
728ca7c9 PB |
10922 | encode_thumb32_shifted_operand (1); |
10923 | } | |
c19d1205 ZW |
10924 | } |
10925 | else | |
10926 | switch (inst.instruction) | |
10927 | { | |
10928 | case T_MNEM_mov: | |
837b3435 | 10929 | /* In v4t or v5t a move of two lowregs produces unpredictable |
c6400f8a MGD |
10930 | results. Don't allow this. */ |
10931 | if (low_regs) | |
10932 | { | |
10933 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6), | |
10934 | "MOV Rd, Rs with two low registers is not " | |
10935 | "permitted on this architecture"); | |
10936 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, | |
10937 | arm_ext_v6); | |
10938 | } | |
10939 | ||
c19d1205 | 10940 | inst.instruction = T_OPCODE_MOV_HR; |
fdfde340 JM |
10941 | inst.instruction |= (Rn & 0x8) << 4; |
10942 | inst.instruction |= (Rn & 0x7); | |
10943 | inst.instruction |= Rm << 3; | |
c19d1205 | 10944 | break; |
b99bd4ef | 10945 | |
c19d1205 ZW |
10946 | case T_MNEM_movs: |
10947 | /* We know we have low registers at this point. | |
941a8a52 MGD |
10948 | Generate LSLS Rd, Rs, #0. */ |
10949 | inst.instruction = T_OPCODE_LSL_I; | |
fdfde340 JM |
10950 | inst.instruction |= Rn; |
10951 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10952 | break; |
10953 | ||
10954 | case T_MNEM_cmp: | |
3d388997 | 10955 | if (low_regs) |
c19d1205 ZW |
10956 | { |
10957 | inst.instruction = T_OPCODE_CMP_LR; | |
fdfde340 JM |
10958 | inst.instruction |= Rn; |
10959 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10960 | } |
10961 | else | |
10962 | { | |
10963 | inst.instruction = T_OPCODE_CMP_HR; | |
fdfde340 JM |
10964 | inst.instruction |= (Rn & 0x8) << 4; |
10965 | inst.instruction |= (Rn & 0x7); | |
10966 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
10967 | } |
10968 | break; | |
10969 | } | |
b99bd4ef NC |
10970 | return; |
10971 | } | |
10972 | ||
c19d1205 | 10973 | inst.instruction = THUMB_OP16 (inst.instruction); |
539d4391 NC |
10974 | |
10975 | /* PR 10443: Do not silently ignore shifted operands. */ | |
10976 | constraint (inst.operands[1].shifted, | |
10977 | _("shifts in CMP/MOV instructions are only supported in unified syntax")); | |
10978 | ||
c19d1205 | 10979 | if (inst.operands[1].isreg) |
b99bd4ef | 10980 | { |
fdfde340 | 10981 | if (Rn < 8 && Rm < 8) |
b99bd4ef | 10982 | { |
c19d1205 ZW |
10983 | /* A move of two lowregs is encoded as ADD Rd, Rs, #0 |
10984 | since a MOV instruction produces unpredictable results. */ | |
10985 | if (inst.instruction == T_OPCODE_MOV_I8) | |
10986 | inst.instruction = T_OPCODE_ADD_I3; | |
b99bd4ef | 10987 | else |
c19d1205 | 10988 | inst.instruction = T_OPCODE_CMP_LR; |
b99bd4ef | 10989 | |
fdfde340 JM |
10990 | inst.instruction |= Rn; |
10991 | inst.instruction |= Rm << 3; | |
b99bd4ef NC |
10992 | } |
10993 | else | |
10994 | { | |
c19d1205 ZW |
10995 | if (inst.instruction == T_OPCODE_MOV_I8) |
10996 | inst.instruction = T_OPCODE_MOV_HR; | |
10997 | else | |
10998 | inst.instruction = T_OPCODE_CMP_HR; | |
10999 | do_t_cpy (); | |
b99bd4ef NC |
11000 | } |
11001 | } | |
c19d1205 | 11002 | else |
b99bd4ef | 11003 | { |
fdfde340 | 11004 | constraint (Rn > 7, |
c19d1205 | 11005 | _("only lo regs allowed with immediate")); |
fdfde340 | 11006 | inst.instruction |= Rn << 8; |
c19d1205 ZW |
11007 | inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; |
11008 | } | |
11009 | } | |
b99bd4ef | 11010 | |
c19d1205 ZW |
11011 | static void |
11012 | do_t_mov16 (void) | |
11013 | { | |
fdfde340 | 11014 | unsigned Rd; |
b6895b4f PB |
11015 | bfd_vma imm; |
11016 | bfd_boolean top; | |
11017 | ||
11018 | top = (inst.instruction & 0x00800000) != 0; | |
11019 | if (inst.reloc.type == BFD_RELOC_ARM_MOVW) | |
11020 | { | |
11021 | constraint (top, _(":lower16: not allowed this instruction")); | |
11022 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; | |
11023 | } | |
11024 | else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) | |
11025 | { | |
11026 | constraint (!top, _(":upper16: not allowed this instruction")); | |
11027 | inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; | |
11028 | } | |
11029 | ||
fdfde340 JM |
11030 | Rd = inst.operands[0].reg; |
11031 | reject_bad_reg (Rd); | |
11032 | ||
11033 | inst.instruction |= Rd << 8; | |
b6895b4f PB |
11034 | if (inst.reloc.type == BFD_RELOC_UNUSED) |
11035 | { | |
11036 | imm = inst.reloc.exp.X_add_number; | |
11037 | inst.instruction |= (imm & 0xf000) << 4; | |
11038 | inst.instruction |= (imm & 0x0800) << 15; | |
11039 | inst.instruction |= (imm & 0x0700) << 4; | |
11040 | inst.instruction |= (imm & 0x00ff); | |
11041 | } | |
c19d1205 | 11042 | } |
b99bd4ef | 11043 | |
c19d1205 ZW |
11044 | static void |
11045 | do_t_mvn_tst (void) | |
11046 | { | |
fdfde340 | 11047 | unsigned Rn, Rm; |
c921be7d | 11048 | |
fdfde340 JM |
11049 | Rn = inst.operands[0].reg; |
11050 | Rm = inst.operands[1].reg; | |
11051 | ||
11052 | if (inst.instruction == T_MNEM_cmp | |
11053 | || inst.instruction == T_MNEM_cmn) | |
11054 | constraint (Rn == REG_PC, BAD_PC); | |
11055 | else | |
11056 | reject_bad_reg (Rn); | |
11057 | reject_bad_reg (Rm); | |
11058 | ||
c19d1205 ZW |
11059 | if (unified_syntax) |
11060 | { | |
11061 | int r0off = (inst.instruction == T_MNEM_mvn | |
11062 | || inst.instruction == T_MNEM_mvns) ? 8 : 16; | |
3d388997 PB |
11063 | bfd_boolean narrow; |
11064 | ||
11065 | if (inst.size_req == 4 | |
11066 | || inst.instruction > 0xffff | |
11067 | || inst.operands[1].shifted | |
fdfde340 | 11068 | || Rn > 7 || Rm > 7) |
3d388997 PB |
11069 | narrow = FALSE; |
11070 | else if (inst.instruction == T_MNEM_cmn) | |
11071 | narrow = TRUE; | |
11072 | else if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11073 | narrow = !in_it_block (); |
3d388997 | 11074 | else |
e07e6e58 | 11075 | narrow = in_it_block (); |
3d388997 | 11076 | |
c19d1205 | 11077 | if (!inst.operands[1].isreg) |
b99bd4ef | 11078 | { |
c19d1205 ZW |
11079 | /* For an immediate, we always generate a 32-bit opcode; |
11080 | section relaxation will shrink it later if possible. */ | |
11081 | if (inst.instruction < 0xffff) | |
11082 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11083 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
fdfde340 | 11084 | inst.instruction |= Rn << r0off; |
c19d1205 | 11085 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; |
b99bd4ef | 11086 | } |
c19d1205 | 11087 | else |
b99bd4ef | 11088 | { |
c19d1205 | 11089 | /* See if we can do this with a 16-bit instruction. */ |
3d388997 | 11090 | if (narrow) |
b99bd4ef | 11091 | { |
c19d1205 | 11092 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11093 | inst.instruction |= Rn; |
11094 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11095 | } |
c19d1205 | 11096 | else |
b99bd4ef | 11097 | { |
c19d1205 ZW |
11098 | constraint (inst.operands[1].shifted |
11099 | && inst.operands[1].immisreg, | |
11100 | _("shift must be constant")); | |
11101 | if (inst.instruction < 0xffff) | |
11102 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 | 11103 | inst.instruction |= Rn << r0off; |
c19d1205 | 11104 | encode_thumb32_shifted_operand (1); |
b99bd4ef | 11105 | } |
b99bd4ef NC |
11106 | } |
11107 | } | |
11108 | else | |
11109 | { | |
c19d1205 ZW |
11110 | constraint (inst.instruction > 0xffff |
11111 | || inst.instruction == T_MNEM_mvns, BAD_THUMB32); | |
11112 | constraint (!inst.operands[1].isreg || inst.operands[1].shifted, | |
11113 | _("unshifted register required")); | |
fdfde340 | 11114 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 11115 | BAD_HIREG); |
b99bd4ef | 11116 | |
c19d1205 | 11117 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11118 | inst.instruction |= Rn; |
11119 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11120 | } |
b99bd4ef NC |
11121 | } |
11122 | ||
b05fe5cf | 11123 | static void |
c19d1205 | 11124 | do_t_mrs (void) |
b05fe5cf | 11125 | { |
fdfde340 | 11126 | unsigned Rd; |
037e8744 JB |
11127 | |
11128 | if (do_vfp_nsyn_mrs () == SUCCESS) | |
11129 | return; | |
11130 | ||
90ec0d68 MGD |
11131 | Rd = inst.operands[0].reg; |
11132 | reject_bad_reg (Rd); | |
11133 | inst.instruction |= Rd << 8; | |
11134 | ||
11135 | if (inst.operands[1].isreg) | |
62b3e311 | 11136 | { |
90ec0d68 MGD |
11137 | unsigned br = inst.operands[1].reg; |
11138 | if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000)) | |
11139 | as_bad (_("bad register for mrs")); | |
11140 | ||
11141 | inst.instruction |= br & (0xf << 16); | |
11142 | inst.instruction |= (br & 0x300) >> 4; | |
11143 | inst.instruction |= (br & SPSR_BIT) >> 2; | |
62b3e311 PB |
11144 | } |
11145 | else | |
11146 | { | |
90ec0d68 | 11147 | int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
5f4273c7 | 11148 | |
d2cd1205 JB |
11149 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
11150 | constraint (flags != 0, _("selected processor does not support " | |
11151 | "requested special purpose register")); | |
90ec0d68 | 11152 | else |
d2cd1205 JB |
11153 | /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile |
11154 | devices). */ | |
11155 | constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), | |
11156 | _("'APSR', 'CPSR' or 'SPSR' expected")); | |
fdfde340 | 11157 | |
90ec0d68 MGD |
11158 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
11159 | inst.instruction |= inst.operands[1].imm & 0xff; | |
11160 | inst.instruction |= 0xf0000; | |
11161 | } | |
c19d1205 | 11162 | } |
b05fe5cf | 11163 | |
c19d1205 ZW |
11164 | static void |
11165 | do_t_msr (void) | |
11166 | { | |
62b3e311 | 11167 | int flags; |
fdfde340 | 11168 | unsigned Rn; |
62b3e311 | 11169 | |
037e8744 JB |
11170 | if (do_vfp_nsyn_msr () == SUCCESS) |
11171 | return; | |
11172 | ||
c19d1205 ZW |
11173 | constraint (!inst.operands[1].isreg, |
11174 | _("Thumb encoding does not support an immediate here")); | |
90ec0d68 MGD |
11175 | |
11176 | if (inst.operands[0].isreg) | |
11177 | flags = (int)(inst.operands[0].reg); | |
11178 | else | |
11179 | flags = inst.operands[0].imm; | |
11180 | ||
d2cd1205 | 11181 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)) |
62b3e311 | 11182 | { |
d2cd1205 JB |
11183 | int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); |
11184 | ||
11185 | constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
11186 | && (bits & ~(PSR_s | PSR_f)) != 0) | |
11187 | || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp) | |
11188 | && bits != PSR_f), | |
11189 | _("selected processor does not support requested special " | |
11190 | "purpose register")); | |
62b3e311 PB |
11191 | } |
11192 | else | |
d2cd1205 JB |
11193 | constraint ((flags & 0xff) != 0, _("selected processor does not support " |
11194 | "requested special purpose register")); | |
c921be7d | 11195 | |
fdfde340 JM |
11196 | Rn = inst.operands[1].reg; |
11197 | reject_bad_reg (Rn); | |
11198 | ||
62b3e311 | 11199 | inst.instruction |= (flags & SPSR_BIT) >> 2; |
90ec0d68 MGD |
11200 | inst.instruction |= (flags & 0xf0000) >> 8; |
11201 | inst.instruction |= (flags & 0x300) >> 4; | |
62b3e311 | 11202 | inst.instruction |= (flags & 0xff); |
fdfde340 | 11203 | inst.instruction |= Rn << 16; |
c19d1205 | 11204 | } |
b05fe5cf | 11205 | |
c19d1205 ZW |
11206 | static void |
11207 | do_t_mul (void) | |
11208 | { | |
17828f45 | 11209 | bfd_boolean narrow; |
fdfde340 | 11210 | unsigned Rd, Rn, Rm; |
17828f45 | 11211 | |
c19d1205 ZW |
11212 | if (!inst.operands[2].present) |
11213 | inst.operands[2].reg = inst.operands[0].reg; | |
b05fe5cf | 11214 | |
fdfde340 JM |
11215 | Rd = inst.operands[0].reg; |
11216 | Rn = inst.operands[1].reg; | |
11217 | Rm = inst.operands[2].reg; | |
11218 | ||
17828f45 | 11219 | if (unified_syntax) |
b05fe5cf | 11220 | { |
17828f45 | 11221 | if (inst.size_req == 4 |
fdfde340 JM |
11222 | || (Rd != Rn |
11223 | && Rd != Rm) | |
11224 | || Rn > 7 | |
11225 | || Rm > 7) | |
17828f45 JM |
11226 | narrow = FALSE; |
11227 | else if (inst.instruction == T_MNEM_muls) | |
e07e6e58 | 11228 | narrow = !in_it_block (); |
17828f45 | 11229 | else |
e07e6e58 | 11230 | narrow = in_it_block (); |
b05fe5cf | 11231 | } |
c19d1205 | 11232 | else |
b05fe5cf | 11233 | { |
17828f45 | 11234 | constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32); |
fdfde340 | 11235 | constraint (Rn > 7 || Rm > 7, |
c19d1205 | 11236 | BAD_HIREG); |
17828f45 JM |
11237 | narrow = TRUE; |
11238 | } | |
b05fe5cf | 11239 | |
17828f45 JM |
11240 | if (narrow) |
11241 | { | |
11242 | /* 16-bit MULS/Conditional MUL. */ | |
c19d1205 | 11243 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 | 11244 | inst.instruction |= Rd; |
b05fe5cf | 11245 | |
fdfde340 JM |
11246 | if (Rd == Rn) |
11247 | inst.instruction |= Rm << 3; | |
11248 | else if (Rd == Rm) | |
11249 | inst.instruction |= Rn << 3; | |
c19d1205 ZW |
11250 | else |
11251 | constraint (1, _("dest must overlap one source register")); | |
11252 | } | |
17828f45 JM |
11253 | else |
11254 | { | |
e07e6e58 NC |
11255 | constraint (inst.instruction != T_MNEM_mul, |
11256 | _("Thumb-2 MUL must not set flags")); | |
17828f45 JM |
11257 | /* 32-bit MUL. */ |
11258 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11259 | inst.instruction |= Rd << 8; |
11260 | inst.instruction |= Rn << 16; | |
11261 | inst.instruction |= Rm << 0; | |
11262 | ||
11263 | reject_bad_reg (Rd); | |
11264 | reject_bad_reg (Rn); | |
11265 | reject_bad_reg (Rm); | |
17828f45 | 11266 | } |
c19d1205 | 11267 | } |
b05fe5cf | 11268 | |
c19d1205 ZW |
11269 | static void |
11270 | do_t_mull (void) | |
11271 | { | |
fdfde340 | 11272 | unsigned RdLo, RdHi, Rn, Rm; |
b05fe5cf | 11273 | |
fdfde340 JM |
11274 | RdLo = inst.operands[0].reg; |
11275 | RdHi = inst.operands[1].reg; | |
11276 | Rn = inst.operands[2].reg; | |
11277 | Rm = inst.operands[3].reg; | |
11278 | ||
11279 | reject_bad_reg (RdLo); | |
11280 | reject_bad_reg (RdHi); | |
11281 | reject_bad_reg (Rn); | |
11282 | reject_bad_reg (Rm); | |
11283 | ||
11284 | inst.instruction |= RdLo << 12; | |
11285 | inst.instruction |= RdHi << 8; | |
11286 | inst.instruction |= Rn << 16; | |
11287 | inst.instruction |= Rm; | |
11288 | ||
11289 | if (RdLo == RdHi) | |
c19d1205 ZW |
11290 | as_tsktsk (_("rdhi and rdlo must be different")); |
11291 | } | |
b05fe5cf | 11292 | |
c19d1205 ZW |
11293 | static void |
11294 | do_t_nop (void) | |
11295 | { | |
e07e6e58 NC |
11296 | set_it_insn_type (NEUTRAL_IT_INSN); |
11297 | ||
c19d1205 ZW |
11298 | if (unified_syntax) |
11299 | { | |
11300 | if (inst.size_req == 4 || inst.operands[0].imm > 15) | |
b05fe5cf | 11301 | { |
c19d1205 ZW |
11302 | inst.instruction = THUMB_OP32 (inst.instruction); |
11303 | inst.instruction |= inst.operands[0].imm; | |
11304 | } | |
11305 | else | |
11306 | { | |
bc2d1808 NC |
11307 | /* PR9722: Check for Thumb2 availability before |
11308 | generating a thumb2 nop instruction. */ | |
afa62d5e | 11309 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
bc2d1808 NC |
11310 | { |
11311 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11312 | inst.instruction |= inst.operands[0].imm << 4; | |
11313 | } | |
11314 | else | |
11315 | inst.instruction = 0x46c0; | |
c19d1205 ZW |
11316 | } |
11317 | } | |
11318 | else | |
11319 | { | |
11320 | constraint (inst.operands[0].present, | |
11321 | _("Thumb does not support NOP with hints")); | |
11322 | inst.instruction = 0x46c0; | |
11323 | } | |
11324 | } | |
b05fe5cf | 11325 | |
c19d1205 ZW |
11326 | static void |
11327 | do_t_neg (void) | |
11328 | { | |
11329 | if (unified_syntax) | |
11330 | { | |
3d388997 PB |
11331 | bfd_boolean narrow; |
11332 | ||
11333 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11334 | narrow = !in_it_block (); |
3d388997 | 11335 | else |
e07e6e58 | 11336 | narrow = in_it_block (); |
3d388997 PB |
11337 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11338 | narrow = FALSE; | |
11339 | if (inst.size_req == 4) | |
11340 | narrow = FALSE; | |
11341 | ||
11342 | if (!narrow) | |
c19d1205 ZW |
11343 | { |
11344 | inst.instruction = THUMB_OP32 (inst.instruction); | |
11345 | inst.instruction |= inst.operands[0].reg << 8; | |
11346 | inst.instruction |= inst.operands[1].reg << 16; | |
b05fe5cf ZW |
11347 | } |
11348 | else | |
11349 | { | |
c19d1205 ZW |
11350 | inst.instruction = THUMB_OP16 (inst.instruction); |
11351 | inst.instruction |= inst.operands[0].reg; | |
11352 | inst.instruction |= inst.operands[1].reg << 3; | |
b05fe5cf ZW |
11353 | } |
11354 | } | |
11355 | else | |
11356 | { | |
c19d1205 ZW |
11357 | constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, |
11358 | BAD_HIREG); | |
11359 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
11360 | ||
11361 | inst.instruction = THUMB_OP16 (inst.instruction); | |
11362 | inst.instruction |= inst.operands[0].reg; | |
11363 | inst.instruction |= inst.operands[1].reg << 3; | |
11364 | } | |
11365 | } | |
11366 | ||
1c444d06 JM |
11367 | static void |
11368 | do_t_orn (void) | |
11369 | { | |
11370 | unsigned Rd, Rn; | |
11371 | ||
11372 | Rd = inst.operands[0].reg; | |
11373 | Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; | |
11374 | ||
fdfde340 JM |
11375 | reject_bad_reg (Rd); |
11376 | /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */ | |
11377 | reject_bad_reg (Rn); | |
11378 | ||
1c444d06 JM |
11379 | inst.instruction |= Rd << 8; |
11380 | inst.instruction |= Rn << 16; | |
11381 | ||
11382 | if (!inst.operands[2].isreg) | |
11383 | { | |
11384 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11385 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11386 | } | |
11387 | else | |
11388 | { | |
11389 | unsigned Rm; | |
11390 | ||
11391 | Rm = inst.operands[2].reg; | |
fdfde340 | 11392 | reject_bad_reg (Rm); |
1c444d06 JM |
11393 | |
11394 | constraint (inst.operands[2].shifted | |
11395 | && inst.operands[2].immisreg, | |
11396 | _("shift must be constant")); | |
11397 | encode_thumb32_shifted_operand (2); | |
11398 | } | |
11399 | } | |
11400 | ||
c19d1205 ZW |
11401 | static void |
11402 | do_t_pkhbt (void) | |
11403 | { | |
fdfde340 JM |
11404 | unsigned Rd, Rn, Rm; |
11405 | ||
11406 | Rd = inst.operands[0].reg; | |
11407 | Rn = inst.operands[1].reg; | |
11408 | Rm = inst.operands[2].reg; | |
11409 | ||
11410 | reject_bad_reg (Rd); | |
11411 | reject_bad_reg (Rn); | |
11412 | reject_bad_reg (Rm); | |
11413 | ||
11414 | inst.instruction |= Rd << 8; | |
11415 | inst.instruction |= Rn << 16; | |
11416 | inst.instruction |= Rm; | |
c19d1205 ZW |
11417 | if (inst.operands[3].present) |
11418 | { | |
11419 | unsigned int val = inst.reloc.exp.X_add_number; | |
11420 | constraint (inst.reloc.exp.X_op != O_constant, | |
11421 | _("expression too complex")); | |
11422 | inst.instruction |= (val & 0x1c) << 10; | |
11423 | inst.instruction |= (val & 0x03) << 6; | |
b05fe5cf | 11424 | } |
c19d1205 | 11425 | } |
b05fe5cf | 11426 | |
c19d1205 ZW |
11427 | static void |
11428 | do_t_pkhtb (void) | |
11429 | { | |
11430 | if (!inst.operands[3].present) | |
1ef52f49 NC |
11431 | { |
11432 | unsigned Rtmp; | |
11433 | ||
11434 | inst.instruction &= ~0x00000020; | |
11435 | ||
11436 | /* PR 10168. Swap the Rm and Rn registers. */ | |
11437 | Rtmp = inst.operands[1].reg; | |
11438 | inst.operands[1].reg = inst.operands[2].reg; | |
11439 | inst.operands[2].reg = Rtmp; | |
11440 | } | |
c19d1205 | 11441 | do_t_pkhbt (); |
b05fe5cf ZW |
11442 | } |
11443 | ||
c19d1205 ZW |
11444 | static void |
11445 | do_t_pld (void) | |
11446 | { | |
fdfde340 JM |
11447 | if (inst.operands[0].immisreg) |
11448 | reject_bad_reg (inst.operands[0].imm); | |
11449 | ||
c19d1205 ZW |
11450 | encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); |
11451 | } | |
b05fe5cf | 11452 | |
c19d1205 ZW |
11453 | static void |
11454 | do_t_push_pop (void) | |
b99bd4ef | 11455 | { |
e9f89963 | 11456 | unsigned mask; |
5f4273c7 | 11457 | |
c19d1205 ZW |
11458 | constraint (inst.operands[0].writeback, |
11459 | _("push/pop do not support {reglist}^")); | |
11460 | constraint (inst.reloc.type != BFD_RELOC_UNUSED, | |
11461 | _("expression too complex")); | |
b99bd4ef | 11462 | |
e9f89963 PB |
11463 | mask = inst.operands[0].imm; |
11464 | if ((mask & ~0xff) == 0) | |
3c707909 | 11465 | inst.instruction = THUMB_OP16 (inst.instruction) | mask; |
c19d1205 | 11466 | else if ((inst.instruction == T_MNEM_push |
e9f89963 | 11467 | && (mask & ~0xff) == 1 << REG_LR) |
c19d1205 | 11468 | || (inst.instruction == T_MNEM_pop |
e9f89963 | 11469 | && (mask & ~0xff) == 1 << REG_PC)) |
b99bd4ef | 11470 | { |
c19d1205 ZW |
11471 | inst.instruction = THUMB_OP16 (inst.instruction); |
11472 | inst.instruction |= THUMB_PP_PC_LR; | |
3c707909 | 11473 | inst.instruction |= mask & 0xff; |
c19d1205 ZW |
11474 | } |
11475 | else if (unified_syntax) | |
11476 | { | |
3c707909 | 11477 | inst.instruction = THUMB_OP32 (inst.instruction); |
5f4273c7 | 11478 | encode_thumb2_ldmstm (13, mask, TRUE); |
c19d1205 ZW |
11479 | } |
11480 | else | |
11481 | { | |
11482 | inst.error = _("invalid register list to push/pop instruction"); | |
11483 | return; | |
11484 | } | |
c19d1205 | 11485 | } |
b99bd4ef | 11486 | |
c19d1205 ZW |
11487 | static void |
11488 | do_t_rbit (void) | |
11489 | { | |
fdfde340 JM |
11490 | unsigned Rd, Rm; |
11491 | ||
11492 | Rd = inst.operands[0].reg; | |
11493 | Rm = inst.operands[1].reg; | |
11494 | ||
11495 | reject_bad_reg (Rd); | |
11496 | reject_bad_reg (Rm); | |
11497 | ||
11498 | inst.instruction |= Rd << 8; | |
11499 | inst.instruction |= Rm << 16; | |
11500 | inst.instruction |= Rm; | |
c19d1205 | 11501 | } |
b99bd4ef | 11502 | |
c19d1205 ZW |
11503 | static void |
11504 | do_t_rev (void) | |
11505 | { | |
fdfde340 JM |
11506 | unsigned Rd, Rm; |
11507 | ||
11508 | Rd = inst.operands[0].reg; | |
11509 | Rm = inst.operands[1].reg; | |
11510 | ||
11511 | reject_bad_reg (Rd); | |
11512 | reject_bad_reg (Rm); | |
11513 | ||
11514 | if (Rd <= 7 && Rm <= 7 | |
c19d1205 ZW |
11515 | && inst.size_req != 4) |
11516 | { | |
11517 | inst.instruction = THUMB_OP16 (inst.instruction); | |
fdfde340 JM |
11518 | inst.instruction |= Rd; |
11519 | inst.instruction |= Rm << 3; | |
c19d1205 ZW |
11520 | } |
11521 | else if (unified_syntax) | |
11522 | { | |
11523 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11524 | inst.instruction |= Rd << 8; |
11525 | inst.instruction |= Rm << 16; | |
11526 | inst.instruction |= Rm; | |
c19d1205 ZW |
11527 | } |
11528 | else | |
11529 | inst.error = BAD_HIREG; | |
11530 | } | |
b99bd4ef | 11531 | |
1c444d06 JM |
11532 | static void |
11533 | do_t_rrx (void) | |
11534 | { | |
11535 | unsigned Rd, Rm; | |
11536 | ||
11537 | Rd = inst.operands[0].reg; | |
11538 | Rm = inst.operands[1].reg; | |
11539 | ||
fdfde340 JM |
11540 | reject_bad_reg (Rd); |
11541 | reject_bad_reg (Rm); | |
c921be7d | 11542 | |
1c444d06 JM |
11543 | inst.instruction |= Rd << 8; |
11544 | inst.instruction |= Rm; | |
11545 | } | |
11546 | ||
c19d1205 ZW |
11547 | static void |
11548 | do_t_rsb (void) | |
11549 | { | |
fdfde340 | 11550 | unsigned Rd, Rs; |
b99bd4ef | 11551 | |
c19d1205 ZW |
11552 | Rd = inst.operands[0].reg; |
11553 | Rs = (inst.operands[1].present | |
11554 | ? inst.operands[1].reg /* Rd, Rs, foo */ | |
11555 | : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ | |
b99bd4ef | 11556 | |
fdfde340 JM |
11557 | reject_bad_reg (Rd); |
11558 | reject_bad_reg (Rs); | |
11559 | if (inst.operands[2].isreg) | |
11560 | reject_bad_reg (inst.operands[2].reg); | |
11561 | ||
c19d1205 ZW |
11562 | inst.instruction |= Rd << 8; |
11563 | inst.instruction |= Rs << 16; | |
11564 | if (!inst.operands[2].isreg) | |
11565 | { | |
026d3abb PB |
11566 | bfd_boolean narrow; |
11567 | ||
11568 | if ((inst.instruction & 0x00100000) != 0) | |
e07e6e58 | 11569 | narrow = !in_it_block (); |
026d3abb | 11570 | else |
e07e6e58 | 11571 | narrow = in_it_block (); |
026d3abb PB |
11572 | |
11573 | if (Rd > 7 || Rs > 7) | |
11574 | narrow = FALSE; | |
11575 | ||
11576 | if (inst.size_req == 4 || !unified_syntax) | |
11577 | narrow = FALSE; | |
11578 | ||
11579 | if (inst.reloc.exp.X_op != O_constant | |
11580 | || inst.reloc.exp.X_add_number != 0) | |
11581 | narrow = FALSE; | |
11582 | ||
11583 | /* Turn rsb #0 into 16-bit neg. We should probably do this via | |
11584 | relaxation, but it doesn't seem worth the hassle. */ | |
11585 | if (narrow) | |
11586 | { | |
11587 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11588 | inst.instruction = THUMB_OP16 (T_MNEM_negs); | |
11589 | inst.instruction |= Rs << 3; | |
11590 | inst.instruction |= Rd; | |
11591 | } | |
11592 | else | |
11593 | { | |
11594 | inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; | |
11595 | inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
11596 | } | |
c19d1205 ZW |
11597 | } |
11598 | else | |
11599 | encode_thumb32_shifted_operand (2); | |
11600 | } | |
b99bd4ef | 11601 | |
c19d1205 ZW |
11602 | static void |
11603 | do_t_setend (void) | |
11604 | { | |
e07e6e58 | 11605 | set_it_insn_type (OUTSIDE_IT_INSN); |
c19d1205 ZW |
11606 | if (inst.operands[0].imm) |
11607 | inst.instruction |= 0x8; | |
11608 | } | |
b99bd4ef | 11609 | |
c19d1205 ZW |
11610 | static void |
11611 | do_t_shift (void) | |
11612 | { | |
11613 | if (!inst.operands[1].present) | |
11614 | inst.operands[1].reg = inst.operands[0].reg; | |
11615 | ||
11616 | if (unified_syntax) | |
11617 | { | |
3d388997 PB |
11618 | bfd_boolean narrow; |
11619 | int shift_kind; | |
11620 | ||
11621 | switch (inst.instruction) | |
11622 | { | |
11623 | case T_MNEM_asr: | |
11624 | case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; | |
11625 | case T_MNEM_lsl: | |
11626 | case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; | |
11627 | case T_MNEM_lsr: | |
11628 | case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; | |
11629 | case T_MNEM_ror: | |
11630 | case T_MNEM_rors: shift_kind = SHIFT_ROR; break; | |
11631 | default: abort (); | |
11632 | } | |
11633 | ||
11634 | if (THUMB_SETS_FLAGS (inst.instruction)) | |
e07e6e58 | 11635 | narrow = !in_it_block (); |
3d388997 | 11636 | else |
e07e6e58 | 11637 | narrow = in_it_block (); |
3d388997 PB |
11638 | if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) |
11639 | narrow = FALSE; | |
11640 | if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) | |
11641 | narrow = FALSE; | |
11642 | if (inst.operands[2].isreg | |
11643 | && (inst.operands[1].reg != inst.operands[0].reg | |
11644 | || inst.operands[2].reg > 7)) | |
11645 | narrow = FALSE; | |
11646 | if (inst.size_req == 4) | |
11647 | narrow = FALSE; | |
11648 | ||
fdfde340 JM |
11649 | reject_bad_reg (inst.operands[0].reg); |
11650 | reject_bad_reg (inst.operands[1].reg); | |
c921be7d | 11651 | |
3d388997 | 11652 | if (!narrow) |
c19d1205 ZW |
11653 | { |
11654 | if (inst.operands[2].isreg) | |
b99bd4ef | 11655 | { |
fdfde340 | 11656 | reject_bad_reg (inst.operands[2].reg); |
c19d1205 ZW |
11657 | inst.instruction = THUMB_OP32 (inst.instruction); |
11658 | inst.instruction |= inst.operands[0].reg << 8; | |
11659 | inst.instruction |= inst.operands[1].reg << 16; | |
11660 | inst.instruction |= inst.operands[2].reg; | |
94342ec3 NC |
11661 | |
11662 | /* PR 12854: Error on extraneous shifts. */ | |
11663 | constraint (inst.operands[2].shifted, | |
11664 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
11665 | } |
11666 | else | |
11667 | { | |
11668 | inst.operands[1].shifted = 1; | |
3d388997 | 11669 | inst.operands[1].shift_kind = shift_kind; |
c19d1205 ZW |
11670 | inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) |
11671 | ? T_MNEM_movs : T_MNEM_mov); | |
11672 | inst.instruction |= inst.operands[0].reg << 8; | |
11673 | encode_thumb32_shifted_operand (1); | |
11674 | /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ | |
11675 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef NC |
11676 | } |
11677 | } | |
11678 | else | |
11679 | { | |
c19d1205 | 11680 | if (inst.operands[2].isreg) |
b99bd4ef | 11681 | { |
3d388997 | 11682 | switch (shift_kind) |
b99bd4ef | 11683 | { |
3d388997 PB |
11684 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; |
11685 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; | |
11686 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; | |
11687 | case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; | |
c19d1205 | 11688 | default: abort (); |
b99bd4ef | 11689 | } |
5f4273c7 | 11690 | |
c19d1205 ZW |
11691 | inst.instruction |= inst.operands[0].reg; |
11692 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
11693 | |
11694 | /* PR 12854: Error on extraneous shifts. */ | |
11695 | constraint (inst.operands[2].shifted, | |
11696 | _("extraneous shift as part of operand to shift insn")); | |
b99bd4ef NC |
11697 | } |
11698 | else | |
11699 | { | |
3d388997 | 11700 | switch (shift_kind) |
b99bd4ef | 11701 | { |
3d388997 PB |
11702 | case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; |
11703 | case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; | |
11704 | case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; | |
c19d1205 | 11705 | default: abort (); |
b99bd4ef | 11706 | } |
c19d1205 ZW |
11707 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; |
11708 | inst.instruction |= inst.operands[0].reg; | |
11709 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11710 | } |
11711 | } | |
c19d1205 ZW |
11712 | } |
11713 | else | |
11714 | { | |
11715 | constraint (inst.operands[0].reg > 7 | |
11716 | || inst.operands[1].reg > 7, BAD_HIREG); | |
11717 | constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); | |
b99bd4ef | 11718 | |
c19d1205 ZW |
11719 | if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ |
11720 | { | |
11721 | constraint (inst.operands[2].reg > 7, BAD_HIREG); | |
11722 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
11723 | _("source1 and dest must be same register")); | |
b99bd4ef | 11724 | |
c19d1205 ZW |
11725 | switch (inst.instruction) |
11726 | { | |
11727 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; | |
11728 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; | |
11729 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; | |
11730 | case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; | |
11731 | default: abort (); | |
11732 | } | |
5f4273c7 | 11733 | |
c19d1205 ZW |
11734 | inst.instruction |= inst.operands[0].reg; |
11735 | inst.instruction |= inst.operands[2].reg << 3; | |
af199b06 NC |
11736 | |
11737 | /* PR 12854: Error on extraneous shifts. */ | |
11738 | constraint (inst.operands[2].shifted, | |
11739 | _("extraneous shift as part of operand to shift insn")); | |
c19d1205 ZW |
11740 | } |
11741 | else | |
b99bd4ef | 11742 | { |
c19d1205 ZW |
11743 | switch (inst.instruction) |
11744 | { | |
11745 | case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; | |
11746 | case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; | |
11747 | case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; | |
11748 | case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; | |
11749 | default: abort (); | |
11750 | } | |
11751 | inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; | |
11752 | inst.instruction |= inst.operands[0].reg; | |
11753 | inst.instruction |= inst.operands[1].reg << 3; | |
b99bd4ef NC |
11754 | } |
11755 | } | |
b99bd4ef NC |
11756 | } |
11757 | ||
11758 | static void | |
c19d1205 | 11759 | do_t_simd (void) |
b99bd4ef | 11760 | { |
fdfde340 JM |
11761 | unsigned Rd, Rn, Rm; |
11762 | ||
11763 | Rd = inst.operands[0].reg; | |
11764 | Rn = inst.operands[1].reg; | |
11765 | Rm = inst.operands[2].reg; | |
11766 | ||
11767 | reject_bad_reg (Rd); | |
11768 | reject_bad_reg (Rn); | |
11769 | reject_bad_reg (Rm); | |
11770 | ||
11771 | inst.instruction |= Rd << 8; | |
11772 | inst.instruction |= Rn << 16; | |
11773 | inst.instruction |= Rm; | |
c19d1205 | 11774 | } |
b99bd4ef | 11775 | |
03ee1b7f NC |
11776 | static void |
11777 | do_t_simd2 (void) | |
11778 | { | |
11779 | unsigned Rd, Rn, Rm; | |
11780 | ||
11781 | Rd = inst.operands[0].reg; | |
11782 | Rm = inst.operands[1].reg; | |
11783 | Rn = inst.operands[2].reg; | |
11784 | ||
11785 | reject_bad_reg (Rd); | |
11786 | reject_bad_reg (Rn); | |
11787 | reject_bad_reg (Rm); | |
11788 | ||
11789 | inst.instruction |= Rd << 8; | |
11790 | inst.instruction |= Rn << 16; | |
11791 | inst.instruction |= Rm; | |
11792 | } | |
11793 | ||
c19d1205 | 11794 | static void |
3eb17e6b | 11795 | do_t_smc (void) |
c19d1205 ZW |
11796 | { |
11797 | unsigned int value = inst.reloc.exp.X_add_number; | |
f4c65163 MGD |
11798 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a), |
11799 | _("SMC is not permitted on this architecture")); | |
c19d1205 ZW |
11800 | constraint (inst.reloc.exp.X_op != O_constant, |
11801 | _("expression too complex")); | |
11802 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11803 | inst.instruction |= (value & 0xf000) >> 12; | |
11804 | inst.instruction |= (value & 0x0ff0); | |
11805 | inst.instruction |= (value & 0x000f) << 16; | |
11806 | } | |
b99bd4ef | 11807 | |
90ec0d68 MGD |
11808 | static void |
11809 | do_t_hvc (void) | |
11810 | { | |
11811 | unsigned int value = inst.reloc.exp.X_add_number; | |
11812 | ||
11813 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11814 | inst.instruction |= (value & 0x0fff); | |
11815 | inst.instruction |= (value & 0xf000) << 4; | |
11816 | } | |
11817 | ||
c19d1205 | 11818 | static void |
3a21c15a | 11819 | do_t_ssat_usat (int bias) |
c19d1205 | 11820 | { |
fdfde340 JM |
11821 | unsigned Rd, Rn; |
11822 | ||
11823 | Rd = inst.operands[0].reg; | |
11824 | Rn = inst.operands[2].reg; | |
11825 | ||
11826 | reject_bad_reg (Rd); | |
11827 | reject_bad_reg (Rn); | |
11828 | ||
11829 | inst.instruction |= Rd << 8; | |
3a21c15a | 11830 | inst.instruction |= inst.operands[1].imm - bias; |
fdfde340 | 11831 | inst.instruction |= Rn << 16; |
b99bd4ef | 11832 | |
c19d1205 | 11833 | if (inst.operands[3].present) |
b99bd4ef | 11834 | { |
3a21c15a NC |
11835 | offsetT shift_amount = inst.reloc.exp.X_add_number; |
11836 | ||
11837 | inst.reloc.type = BFD_RELOC_UNUSED; | |
11838 | ||
c19d1205 ZW |
11839 | constraint (inst.reloc.exp.X_op != O_constant, |
11840 | _("expression too complex")); | |
b99bd4ef | 11841 | |
3a21c15a | 11842 | if (shift_amount != 0) |
6189168b | 11843 | { |
3a21c15a NC |
11844 | constraint (shift_amount > 31, |
11845 | _("shift expression is too large")); | |
11846 | ||
c19d1205 | 11847 | if (inst.operands[3].shift_kind == SHIFT_ASR) |
3a21c15a NC |
11848 | inst.instruction |= 0x00200000; /* sh bit. */ |
11849 | ||
11850 | inst.instruction |= (shift_amount & 0x1c) << 10; | |
11851 | inst.instruction |= (shift_amount & 0x03) << 6; | |
6189168b NC |
11852 | } |
11853 | } | |
b99bd4ef | 11854 | } |
c921be7d | 11855 | |
3a21c15a NC |
11856 | static void |
11857 | do_t_ssat (void) | |
11858 | { | |
11859 | do_t_ssat_usat (1); | |
11860 | } | |
b99bd4ef | 11861 | |
0dd132b6 | 11862 | static void |
c19d1205 | 11863 | do_t_ssat16 (void) |
0dd132b6 | 11864 | { |
fdfde340 JM |
11865 | unsigned Rd, Rn; |
11866 | ||
11867 | Rd = inst.operands[0].reg; | |
11868 | Rn = inst.operands[2].reg; | |
11869 | ||
11870 | reject_bad_reg (Rd); | |
11871 | reject_bad_reg (Rn); | |
11872 | ||
11873 | inst.instruction |= Rd << 8; | |
c19d1205 | 11874 | inst.instruction |= inst.operands[1].imm - 1; |
fdfde340 | 11875 | inst.instruction |= Rn << 16; |
c19d1205 | 11876 | } |
0dd132b6 | 11877 | |
c19d1205 ZW |
11878 | static void |
11879 | do_t_strex (void) | |
11880 | { | |
11881 | constraint (!inst.operands[2].isreg || !inst.operands[2].preind | |
11882 | || inst.operands[2].postind || inst.operands[2].writeback | |
11883 | || inst.operands[2].immisreg || inst.operands[2].shifted | |
11884 | || inst.operands[2].negative, | |
01cfc07f | 11885 | BAD_ADDR_MODE); |
0dd132b6 | 11886 | |
5be8be5d DG |
11887 | constraint (inst.operands[2].reg == REG_PC, BAD_PC); |
11888 | ||
c19d1205 ZW |
11889 | inst.instruction |= inst.operands[0].reg << 8; |
11890 | inst.instruction |= inst.operands[1].reg << 12; | |
11891 | inst.instruction |= inst.operands[2].reg << 16; | |
11892 | inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; | |
0dd132b6 NC |
11893 | } |
11894 | ||
b99bd4ef | 11895 | static void |
c19d1205 | 11896 | do_t_strexd (void) |
b99bd4ef | 11897 | { |
c19d1205 ZW |
11898 | if (!inst.operands[2].present) |
11899 | inst.operands[2].reg = inst.operands[1].reg + 1; | |
b99bd4ef | 11900 | |
c19d1205 ZW |
11901 | constraint (inst.operands[0].reg == inst.operands[1].reg |
11902 | || inst.operands[0].reg == inst.operands[2].reg | |
f8a8e9d6 | 11903 | || inst.operands[0].reg == inst.operands[3].reg, |
c19d1205 | 11904 | BAD_OVERLAP); |
b99bd4ef | 11905 | |
c19d1205 ZW |
11906 | inst.instruction |= inst.operands[0].reg; |
11907 | inst.instruction |= inst.operands[1].reg << 12; | |
11908 | inst.instruction |= inst.operands[2].reg << 8; | |
11909 | inst.instruction |= inst.operands[3].reg << 16; | |
b99bd4ef NC |
11910 | } |
11911 | ||
11912 | static void | |
c19d1205 | 11913 | do_t_sxtah (void) |
b99bd4ef | 11914 | { |
fdfde340 JM |
11915 | unsigned Rd, Rn, Rm; |
11916 | ||
11917 | Rd = inst.operands[0].reg; | |
11918 | Rn = inst.operands[1].reg; | |
11919 | Rm = inst.operands[2].reg; | |
11920 | ||
11921 | reject_bad_reg (Rd); | |
11922 | reject_bad_reg (Rn); | |
11923 | reject_bad_reg (Rm); | |
11924 | ||
11925 | inst.instruction |= Rd << 8; | |
11926 | inst.instruction |= Rn << 16; | |
11927 | inst.instruction |= Rm; | |
c19d1205 ZW |
11928 | inst.instruction |= inst.operands[3].imm << 4; |
11929 | } | |
b99bd4ef | 11930 | |
c19d1205 ZW |
11931 | static void |
11932 | do_t_sxth (void) | |
11933 | { | |
fdfde340 JM |
11934 | unsigned Rd, Rm; |
11935 | ||
11936 | Rd = inst.operands[0].reg; | |
11937 | Rm = inst.operands[1].reg; | |
11938 | ||
11939 | reject_bad_reg (Rd); | |
11940 | reject_bad_reg (Rm); | |
c921be7d NC |
11941 | |
11942 | if (inst.instruction <= 0xffff | |
11943 | && inst.size_req != 4 | |
fdfde340 | 11944 | && Rd <= 7 && Rm <= 7 |
c19d1205 | 11945 | && (!inst.operands[2].present || inst.operands[2].imm == 0)) |
b99bd4ef | 11946 | { |
c19d1205 | 11947 | inst.instruction = THUMB_OP16 (inst.instruction); |
fdfde340 JM |
11948 | inst.instruction |= Rd; |
11949 | inst.instruction |= Rm << 3; | |
b99bd4ef | 11950 | } |
c19d1205 | 11951 | else if (unified_syntax) |
b99bd4ef | 11952 | { |
c19d1205 ZW |
11953 | if (inst.instruction <= 0xffff) |
11954 | inst.instruction = THUMB_OP32 (inst.instruction); | |
fdfde340 JM |
11955 | inst.instruction |= Rd << 8; |
11956 | inst.instruction |= Rm; | |
c19d1205 | 11957 | inst.instruction |= inst.operands[2].imm << 4; |
b99bd4ef | 11958 | } |
c19d1205 | 11959 | else |
b99bd4ef | 11960 | { |
c19d1205 ZW |
11961 | constraint (inst.operands[2].present && inst.operands[2].imm != 0, |
11962 | _("Thumb encoding does not support rotation")); | |
11963 | constraint (1, BAD_HIREG); | |
b99bd4ef | 11964 | } |
c19d1205 | 11965 | } |
b99bd4ef | 11966 | |
c19d1205 ZW |
11967 | static void |
11968 | do_t_swi (void) | |
11969 | { | |
b2a5fbdc MGD |
11970 | /* We have to do the following check manually as ARM_EXT_OS only applies |
11971 | to ARM_EXT_V6M. */ | |
11972 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m)) | |
11973 | { | |
ac7f631b NC |
11974 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os) |
11975 | /* This only applies to the v6m howver, not later architectures. */ | |
11976 | && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)) | |
b2a5fbdc MGD |
11977 | as_bad (_("SVC is not permitted on this architecture")); |
11978 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os); | |
11979 | } | |
11980 | ||
c19d1205 ZW |
11981 | inst.reloc.type = BFD_RELOC_ARM_SWI; |
11982 | } | |
b99bd4ef | 11983 | |
92e90b6e PB |
11984 | static void |
11985 | do_t_tb (void) | |
11986 | { | |
fdfde340 | 11987 | unsigned Rn, Rm; |
92e90b6e PB |
11988 | int half; |
11989 | ||
11990 | half = (inst.instruction & 0x10) != 0; | |
e07e6e58 | 11991 | set_it_insn_type_last (); |
dfa9f0d5 PB |
11992 | constraint (inst.operands[0].immisreg, |
11993 | _("instruction requires register index")); | |
fdfde340 JM |
11994 | |
11995 | Rn = inst.operands[0].reg; | |
11996 | Rm = inst.operands[0].imm; | |
c921be7d | 11997 | |
fdfde340 JM |
11998 | constraint (Rn == REG_SP, BAD_SP); |
11999 | reject_bad_reg (Rm); | |
12000 | ||
92e90b6e PB |
12001 | constraint (!half && inst.operands[0].shifted, |
12002 | _("instruction does not allow shifted index")); | |
fdfde340 | 12003 | inst.instruction |= (Rn << 16) | Rm; |
92e90b6e PB |
12004 | } |
12005 | ||
c19d1205 ZW |
12006 | static void |
12007 | do_t_usat (void) | |
12008 | { | |
3a21c15a | 12009 | do_t_ssat_usat (0); |
b99bd4ef NC |
12010 | } |
12011 | ||
12012 | static void | |
c19d1205 | 12013 | do_t_usat16 (void) |
b99bd4ef | 12014 | { |
fdfde340 JM |
12015 | unsigned Rd, Rn; |
12016 | ||
12017 | Rd = inst.operands[0].reg; | |
12018 | Rn = inst.operands[2].reg; | |
12019 | ||
12020 | reject_bad_reg (Rd); | |
12021 | reject_bad_reg (Rn); | |
12022 | ||
12023 | inst.instruction |= Rd << 8; | |
c19d1205 | 12024 | inst.instruction |= inst.operands[1].imm; |
fdfde340 | 12025 | inst.instruction |= Rn << 16; |
b99bd4ef | 12026 | } |
c19d1205 | 12027 | |
5287ad62 | 12028 | /* Neon instruction encoder helpers. */ |
5f4273c7 | 12029 | |
5287ad62 | 12030 | /* Encodings for the different types for various Neon opcodes. */ |
b99bd4ef | 12031 | |
5287ad62 JB |
12032 | /* An "invalid" code for the following tables. */ |
12033 | #define N_INV -1u | |
12034 | ||
12035 | struct neon_tab_entry | |
b99bd4ef | 12036 | { |
5287ad62 JB |
12037 | unsigned integer; |
12038 | unsigned float_or_poly; | |
12039 | unsigned scalar_or_imm; | |
12040 | }; | |
5f4273c7 | 12041 | |
5287ad62 JB |
12042 | /* Map overloaded Neon opcodes to their respective encodings. */ |
12043 | #define NEON_ENC_TAB \ | |
12044 | X(vabd, 0x0000700, 0x1200d00, N_INV), \ | |
12045 | X(vmax, 0x0000600, 0x0000f00, N_INV), \ | |
12046 | X(vmin, 0x0000610, 0x0200f00, N_INV), \ | |
12047 | X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ | |
12048 | X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ | |
12049 | X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ | |
12050 | X(vadd, 0x0000800, 0x0000d00, N_INV), \ | |
12051 | X(vsub, 0x1000800, 0x0200d00, N_INV), \ | |
12052 | X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ | |
12053 | X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ | |
12054 | X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ | |
12055 | /* Register variants of the following two instructions are encoded as | |
e07e6e58 | 12056 | vcge / vcgt with the operands reversed. */ \ |
92559b5b PB |
12057 | X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ |
12058 | X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ | |
62f3b8c8 PB |
12059 | X(vfma, N_INV, 0x0000c10, N_INV), \ |
12060 | X(vfms, N_INV, 0x0200c10, N_INV), \ | |
5287ad62 JB |
12061 | X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ |
12062 | X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ | |
12063 | X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ | |
12064 | X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ | |
12065 | X(vmlal, 0x0800800, N_INV, 0x0800240), \ | |
12066 | X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ | |
12067 | X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ | |
12068 | X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ | |
12069 | X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ | |
12070 | X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ | |
12071 | X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ | |
12072 | X(vshl, 0x0000400, N_INV, 0x0800510), \ | |
12073 | X(vqshl, 0x0000410, N_INV, 0x0800710), \ | |
12074 | X(vand, 0x0000110, N_INV, 0x0800030), \ | |
12075 | X(vbic, 0x0100110, N_INV, 0x0800030), \ | |
12076 | X(veor, 0x1000110, N_INV, N_INV), \ | |
12077 | X(vorn, 0x0300110, N_INV, 0x0800010), \ | |
12078 | X(vorr, 0x0200110, N_INV, 0x0800010), \ | |
12079 | X(vmvn, 0x1b00580, N_INV, 0x0800030), \ | |
12080 | X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ | |
12081 | X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ | |
12082 | X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ | |
12083 | X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ | |
12084 | X(vst1, 0x0000000, 0x0800000, N_INV), \ | |
12085 | X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ | |
12086 | X(vst2, 0x0000100, 0x0800100, N_INV), \ | |
12087 | X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ | |
12088 | X(vst3, 0x0000200, 0x0800200, N_INV), \ | |
12089 | X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ | |
12090 | X(vst4, 0x0000300, 0x0800300, N_INV), \ | |
12091 | X(vmovn, 0x1b20200, N_INV, N_INV), \ | |
12092 | X(vtrn, 0x1b20080, N_INV, N_INV), \ | |
12093 | X(vqmovn, 0x1b20200, N_INV, N_INV), \ | |
037e8744 JB |
12094 | X(vqmovun, 0x1b20240, N_INV, N_INV), \ |
12095 | X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ | |
e6655fda PB |
12096 | X(vnmla, 0xe100a40, 0xe100b40, N_INV), \ |
12097 | X(vnmls, 0xe100a00, 0xe100b00, N_INV), \ | |
62f3b8c8 PB |
12098 | X(vfnma, 0xe900a40, 0xe900b40, N_INV), \ |
12099 | X(vfnms, 0xe900a00, 0xe900b00, N_INV), \ | |
037e8744 JB |
12100 | X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ |
12101 | X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ | |
12102 | X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ | |
12103 | X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) | |
5287ad62 JB |
12104 | |
12105 | enum neon_opc | |
12106 | { | |
12107 | #define X(OPC,I,F,S) N_MNEM_##OPC | |
12108 | NEON_ENC_TAB | |
12109 | #undef X | |
12110 | }; | |
b99bd4ef | 12111 | |
5287ad62 JB |
12112 | static const struct neon_tab_entry neon_enc_tab[] = |
12113 | { | |
12114 | #define X(OPC,I,F,S) { (I), (F), (S) } | |
12115 | NEON_ENC_TAB | |
12116 | #undef X | |
12117 | }; | |
b99bd4ef | 12118 | |
88714cb8 DG |
12119 | /* Do not use these macros; instead, use NEON_ENCODE defined below. */ |
12120 | #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12121 | #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12122 | #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12123 | #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12124 | #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12125 | #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12126 | #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer) | |
12127 | #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | |
12128 | #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) | |
12129 | #define NEON_ENC_SINGLE_(X) \ | |
037e8744 | 12130 | ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) |
88714cb8 | 12131 | #define NEON_ENC_DOUBLE_(X) \ |
037e8744 | 12132 | ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) |
5287ad62 | 12133 | |
88714cb8 DG |
12134 | #define NEON_ENCODE(type, inst) \ |
12135 | do \ | |
12136 | { \ | |
12137 | inst.instruction = NEON_ENC_##type##_ (inst.instruction); \ | |
12138 | inst.is_neon = 1; \ | |
12139 | } \ | |
12140 | while (0) | |
12141 | ||
12142 | #define check_neon_suffixes \ | |
12143 | do \ | |
12144 | { \ | |
12145 | if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \ | |
12146 | { \ | |
12147 | as_bad (_("invalid neon suffix for non neon instruction")); \ | |
12148 | return; \ | |
12149 | } \ | |
12150 | } \ | |
12151 | while (0) | |
12152 | ||
037e8744 JB |
12153 | /* Define shapes for instruction operands. The following mnemonic characters |
12154 | are used in this table: | |
5287ad62 | 12155 | |
037e8744 | 12156 | F - VFP S<n> register |
5287ad62 JB |
12157 | D - Neon D<n> register |
12158 | Q - Neon Q<n> register | |
12159 | I - Immediate | |
12160 | S - Scalar | |
12161 | R - ARM register | |
12162 | L - D<n> register list | |
5f4273c7 | 12163 | |
037e8744 JB |
12164 | This table is used to generate various data: |
12165 | - enumerations of the form NS_DDR to be used as arguments to | |
12166 | neon_select_shape. | |
12167 | - a table classifying shapes into single, double, quad, mixed. | |
5f4273c7 | 12168 | - a table used to drive neon_select_shape. */ |
b99bd4ef | 12169 | |
037e8744 JB |
12170 | #define NEON_SHAPE_DEF \ |
12171 | X(3, (D, D, D), DOUBLE), \ | |
12172 | X(3, (Q, Q, Q), QUAD), \ | |
12173 | X(3, (D, D, I), DOUBLE), \ | |
12174 | X(3, (Q, Q, I), QUAD), \ | |
12175 | X(3, (D, D, S), DOUBLE), \ | |
12176 | X(3, (Q, Q, S), QUAD), \ | |
12177 | X(2, (D, D), DOUBLE), \ | |
12178 | X(2, (Q, Q), QUAD), \ | |
12179 | X(2, (D, S), DOUBLE), \ | |
12180 | X(2, (Q, S), QUAD), \ | |
12181 | X(2, (D, R), DOUBLE), \ | |
12182 | X(2, (Q, R), QUAD), \ | |
12183 | X(2, (D, I), DOUBLE), \ | |
12184 | X(2, (Q, I), QUAD), \ | |
12185 | X(3, (D, L, D), DOUBLE), \ | |
12186 | X(2, (D, Q), MIXED), \ | |
12187 | X(2, (Q, D), MIXED), \ | |
12188 | X(3, (D, Q, I), MIXED), \ | |
12189 | X(3, (Q, D, I), MIXED), \ | |
12190 | X(3, (Q, D, D), MIXED), \ | |
12191 | X(3, (D, Q, Q), MIXED), \ | |
12192 | X(3, (Q, Q, D), MIXED), \ | |
12193 | X(3, (Q, D, S), MIXED), \ | |
12194 | X(3, (D, Q, S), MIXED), \ | |
12195 | X(4, (D, D, D, I), DOUBLE), \ | |
12196 | X(4, (Q, Q, Q, I), QUAD), \ | |
12197 | X(2, (F, F), SINGLE), \ | |
12198 | X(3, (F, F, F), SINGLE), \ | |
12199 | X(2, (F, I), SINGLE), \ | |
12200 | X(2, (F, D), MIXED), \ | |
12201 | X(2, (D, F), MIXED), \ | |
12202 | X(3, (F, F, I), MIXED), \ | |
12203 | X(4, (R, R, F, F), SINGLE), \ | |
12204 | X(4, (F, F, R, R), SINGLE), \ | |
12205 | X(3, (D, R, R), DOUBLE), \ | |
12206 | X(3, (R, R, D), DOUBLE), \ | |
12207 | X(2, (S, R), SINGLE), \ | |
12208 | X(2, (R, S), SINGLE), \ | |
12209 | X(2, (F, R), SINGLE), \ | |
12210 | X(2, (R, F), SINGLE) | |
12211 | ||
12212 | #define S2(A,B) NS_##A##B | |
12213 | #define S3(A,B,C) NS_##A##B##C | |
12214 | #define S4(A,B,C,D) NS_##A##B##C##D | |
12215 | ||
12216 | #define X(N, L, C) S##N L | |
12217 | ||
5287ad62 JB |
12218 | enum neon_shape |
12219 | { | |
037e8744 JB |
12220 | NEON_SHAPE_DEF, |
12221 | NS_NULL | |
5287ad62 | 12222 | }; |
b99bd4ef | 12223 | |
037e8744 JB |
12224 | #undef X |
12225 | #undef S2 | |
12226 | #undef S3 | |
12227 | #undef S4 | |
12228 | ||
12229 | enum neon_shape_class | |
12230 | { | |
12231 | SC_SINGLE, | |
12232 | SC_DOUBLE, | |
12233 | SC_QUAD, | |
12234 | SC_MIXED | |
12235 | }; | |
12236 | ||
12237 | #define X(N, L, C) SC_##C | |
12238 | ||
12239 | static enum neon_shape_class neon_shape_class[] = | |
12240 | { | |
12241 | NEON_SHAPE_DEF | |
12242 | }; | |
12243 | ||
12244 | #undef X | |
12245 | ||
12246 | enum neon_shape_el | |
12247 | { | |
12248 | SE_F, | |
12249 | SE_D, | |
12250 | SE_Q, | |
12251 | SE_I, | |
12252 | SE_S, | |
12253 | SE_R, | |
12254 | SE_L | |
12255 | }; | |
12256 | ||
12257 | /* Register widths of above. */ | |
12258 | static unsigned neon_shape_el_size[] = | |
12259 | { | |
12260 | 32, | |
12261 | 64, | |
12262 | 128, | |
12263 | 0, | |
12264 | 32, | |
12265 | 32, | |
12266 | 0 | |
12267 | }; | |
12268 | ||
12269 | struct neon_shape_info | |
12270 | { | |
12271 | unsigned els; | |
12272 | enum neon_shape_el el[NEON_MAX_TYPE_ELS]; | |
12273 | }; | |
12274 | ||
12275 | #define S2(A,B) { SE_##A, SE_##B } | |
12276 | #define S3(A,B,C) { SE_##A, SE_##B, SE_##C } | |
12277 | #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } | |
12278 | ||
12279 | #define X(N, L, C) { N, S##N L } | |
12280 | ||
12281 | static struct neon_shape_info neon_shape_tab[] = | |
12282 | { | |
12283 | NEON_SHAPE_DEF | |
12284 | }; | |
12285 | ||
12286 | #undef X | |
12287 | #undef S2 | |
12288 | #undef S3 | |
12289 | #undef S4 | |
12290 | ||
5287ad62 JB |
12291 | /* Bit masks used in type checking given instructions. |
12292 | 'N_EQK' means the type must be the same as (or based on in some way) the key | |
12293 | type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is | |
12294 | set, various other bits can be set as well in order to modify the meaning of | |
12295 | the type constraint. */ | |
12296 | ||
12297 | enum neon_type_mask | |
12298 | { | |
8e79c3df CM |
12299 | N_S8 = 0x0000001, |
12300 | N_S16 = 0x0000002, | |
12301 | N_S32 = 0x0000004, | |
12302 | N_S64 = 0x0000008, | |
12303 | N_U8 = 0x0000010, | |
12304 | N_U16 = 0x0000020, | |
12305 | N_U32 = 0x0000040, | |
12306 | N_U64 = 0x0000080, | |
12307 | N_I8 = 0x0000100, | |
12308 | N_I16 = 0x0000200, | |
12309 | N_I32 = 0x0000400, | |
12310 | N_I64 = 0x0000800, | |
12311 | N_8 = 0x0001000, | |
12312 | N_16 = 0x0002000, | |
12313 | N_32 = 0x0004000, | |
12314 | N_64 = 0x0008000, | |
12315 | N_P8 = 0x0010000, | |
12316 | N_P16 = 0x0020000, | |
12317 | N_F16 = 0x0040000, | |
12318 | N_F32 = 0x0080000, | |
12319 | N_F64 = 0x0100000, | |
c921be7d NC |
12320 | N_KEY = 0x1000000, /* Key element (main type specifier). */ |
12321 | N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */ | |
8e79c3df | 12322 | N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
c921be7d NC |
12323 | N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */ |
12324 | N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */ | |
12325 | N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */ | |
12326 | N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */ | |
12327 | N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */ | |
12328 | N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */ | |
12329 | N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */ | |
5287ad62 | 12330 | N_UTYP = 0, |
037e8744 | 12331 | N_MAX_NONSPECIAL = N_F64 |
5287ad62 JB |
12332 | }; |
12333 | ||
dcbf9037 JB |
12334 | #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) |
12335 | ||
5287ad62 JB |
12336 | #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) |
12337 | #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) | |
12338 | #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) | |
12339 | #define N_SUF_32 (N_SU_32 | N_F32) | |
12340 | #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) | |
12341 | #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) | |
12342 | ||
12343 | /* Pass this as the first type argument to neon_check_type to ignore types | |
12344 | altogether. */ | |
12345 | #define N_IGNORE_TYPE (N_KEY | N_EQK) | |
12346 | ||
037e8744 JB |
12347 | /* Select a "shape" for the current instruction (describing register types or |
12348 | sizes) from a list of alternatives. Return NS_NULL if the current instruction | |
12349 | doesn't fit. For non-polymorphic shapes, checking is usually done as a | |
12350 | function of operand parsing, so this function doesn't need to be called. | |
12351 | Shapes should be listed in order of decreasing length. */ | |
5287ad62 JB |
12352 | |
12353 | static enum neon_shape | |
037e8744 | 12354 | neon_select_shape (enum neon_shape shape, ...) |
5287ad62 | 12355 | { |
037e8744 JB |
12356 | va_list ap; |
12357 | enum neon_shape first_shape = shape; | |
5287ad62 JB |
12358 | |
12359 | /* Fix missing optional operands. FIXME: we don't know at this point how | |
12360 | many arguments we should have, so this makes the assumption that we have | |
12361 | > 1. This is true of all current Neon opcodes, I think, but may not be | |
12362 | true in the future. */ | |
12363 | if (!inst.operands[1].present) | |
12364 | inst.operands[1] = inst.operands[0]; | |
12365 | ||
037e8744 | 12366 | va_start (ap, shape); |
5f4273c7 | 12367 | |
21d799b5 | 12368 | for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int)) |
037e8744 JB |
12369 | { |
12370 | unsigned j; | |
12371 | int matches = 1; | |
12372 | ||
12373 | for (j = 0; j < neon_shape_tab[shape].els; j++) | |
12374 | { | |
12375 | if (!inst.operands[j].present) | |
12376 | { | |
12377 | matches = 0; | |
12378 | break; | |
12379 | } | |
12380 | ||
12381 | switch (neon_shape_tab[shape].el[j]) | |
12382 | { | |
12383 | case SE_F: | |
12384 | if (!(inst.operands[j].isreg | |
12385 | && inst.operands[j].isvec | |
12386 | && inst.operands[j].issingle | |
12387 | && !inst.operands[j].isquad)) | |
12388 | matches = 0; | |
12389 | break; | |
12390 | ||
12391 | case SE_D: | |
12392 | if (!(inst.operands[j].isreg | |
12393 | && inst.operands[j].isvec | |
12394 | && !inst.operands[j].isquad | |
12395 | && !inst.operands[j].issingle)) | |
12396 | matches = 0; | |
12397 | break; | |
12398 | ||
12399 | case SE_R: | |
12400 | if (!(inst.operands[j].isreg | |
12401 | && !inst.operands[j].isvec)) | |
12402 | matches = 0; | |
12403 | break; | |
12404 | ||
12405 | case SE_Q: | |
12406 | if (!(inst.operands[j].isreg | |
12407 | && inst.operands[j].isvec | |
12408 | && inst.operands[j].isquad | |
12409 | && !inst.operands[j].issingle)) | |
12410 | matches = 0; | |
12411 | break; | |
12412 | ||
12413 | case SE_I: | |
12414 | if (!(!inst.operands[j].isreg | |
12415 | && !inst.operands[j].isscalar)) | |
12416 | matches = 0; | |
12417 | break; | |
12418 | ||
12419 | case SE_S: | |
12420 | if (!(!inst.operands[j].isreg | |
12421 | && inst.operands[j].isscalar)) | |
12422 | matches = 0; | |
12423 | break; | |
12424 | ||
12425 | case SE_L: | |
12426 | break; | |
12427 | } | |
3fde54a2 JZ |
12428 | if (!matches) |
12429 | break; | |
037e8744 | 12430 | } |
ad6cec43 MGD |
12431 | if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) |
12432 | /* We've matched all the entries in the shape table, and we don't | |
12433 | have any left over operands which have not been matched. */ | |
5287ad62 | 12434 | break; |
037e8744 | 12435 | } |
5f4273c7 | 12436 | |
037e8744 | 12437 | va_end (ap); |
5287ad62 | 12438 | |
037e8744 JB |
12439 | if (shape == NS_NULL && first_shape != NS_NULL) |
12440 | first_error (_("invalid instruction shape")); | |
5287ad62 | 12441 | |
037e8744 JB |
12442 | return shape; |
12443 | } | |
5287ad62 | 12444 | |
037e8744 JB |
12445 | /* True if SHAPE is predominantly a quadword operation (most of the time, this |
12446 | means the Q bit should be set). */ | |
12447 | ||
12448 | static int | |
12449 | neon_quad (enum neon_shape shape) | |
12450 | { | |
12451 | return neon_shape_class[shape] == SC_QUAD; | |
5287ad62 | 12452 | } |
037e8744 | 12453 | |
5287ad62 JB |
12454 | static void |
12455 | neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, | |
12456 | unsigned *g_size) | |
12457 | { | |
12458 | /* Allow modification to be made to types which are constrained to be | |
12459 | based on the key element, based on bits set alongside N_EQK. */ | |
12460 | if ((typebits & N_EQK) != 0) | |
12461 | { | |
12462 | if ((typebits & N_HLF) != 0) | |
12463 | *g_size /= 2; | |
12464 | else if ((typebits & N_DBL) != 0) | |
12465 | *g_size *= 2; | |
12466 | if ((typebits & N_SGN) != 0) | |
12467 | *g_type = NT_signed; | |
12468 | else if ((typebits & N_UNS) != 0) | |
12469 | *g_type = NT_unsigned; | |
12470 | else if ((typebits & N_INT) != 0) | |
12471 | *g_type = NT_integer; | |
12472 | else if ((typebits & N_FLT) != 0) | |
12473 | *g_type = NT_float; | |
dcbf9037 JB |
12474 | else if ((typebits & N_SIZ) != 0) |
12475 | *g_type = NT_untyped; | |
5287ad62 JB |
12476 | } |
12477 | } | |
5f4273c7 | 12478 | |
5287ad62 JB |
12479 | /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" |
12480 | operand type, i.e. the single type specified in a Neon instruction when it | |
12481 | is the only one given. */ | |
12482 | ||
12483 | static struct neon_type_el | |
12484 | neon_type_promote (struct neon_type_el *key, unsigned thisarg) | |
12485 | { | |
12486 | struct neon_type_el dest = *key; | |
5f4273c7 | 12487 | |
9c2799c2 | 12488 | gas_assert ((thisarg & N_EQK) != 0); |
5f4273c7 | 12489 | |
5287ad62 JB |
12490 | neon_modify_type_size (thisarg, &dest.type, &dest.size); |
12491 | ||
12492 | return dest; | |
12493 | } | |
12494 | ||
12495 | /* Convert Neon type and size into compact bitmask representation. */ | |
12496 | ||
12497 | static enum neon_type_mask | |
12498 | type_chk_of_el_type (enum neon_el_type type, unsigned size) | |
12499 | { | |
12500 | switch (type) | |
12501 | { | |
12502 | case NT_untyped: | |
12503 | switch (size) | |
12504 | { | |
12505 | case 8: return N_8; | |
12506 | case 16: return N_16; | |
12507 | case 32: return N_32; | |
12508 | case 64: return N_64; | |
12509 | default: ; | |
12510 | } | |
12511 | break; | |
12512 | ||
12513 | case NT_integer: | |
12514 | switch (size) | |
12515 | { | |
12516 | case 8: return N_I8; | |
12517 | case 16: return N_I16; | |
12518 | case 32: return N_I32; | |
12519 | case 64: return N_I64; | |
12520 | default: ; | |
12521 | } | |
12522 | break; | |
12523 | ||
12524 | case NT_float: | |
037e8744 JB |
12525 | switch (size) |
12526 | { | |
8e79c3df | 12527 | case 16: return N_F16; |
037e8744 JB |
12528 | case 32: return N_F32; |
12529 | case 64: return N_F64; | |
12530 | default: ; | |
12531 | } | |
5287ad62 JB |
12532 | break; |
12533 | ||
12534 | case NT_poly: | |
12535 | switch (size) | |
12536 | { | |
12537 | case 8: return N_P8; | |
12538 | case 16: return N_P16; | |
12539 | default: ; | |
12540 | } | |
12541 | break; | |
12542 | ||
12543 | case NT_signed: | |
12544 | switch (size) | |
12545 | { | |
12546 | case 8: return N_S8; | |
12547 | case 16: return N_S16; | |
12548 | case 32: return N_S32; | |
12549 | case 64: return N_S64; | |
12550 | default: ; | |
12551 | } | |
12552 | break; | |
12553 | ||
12554 | case NT_unsigned: | |
12555 | switch (size) | |
12556 | { | |
12557 | case 8: return N_U8; | |
12558 | case 16: return N_U16; | |
12559 | case 32: return N_U32; | |
12560 | case 64: return N_U64; | |
12561 | default: ; | |
12562 | } | |
12563 | break; | |
12564 | ||
12565 | default: ; | |
12566 | } | |
5f4273c7 | 12567 | |
5287ad62 JB |
12568 | return N_UTYP; |
12569 | } | |
12570 | ||
12571 | /* Convert compact Neon bitmask type representation to a type and size. Only | |
12572 | handles the case where a single bit is set in the mask. */ | |
12573 | ||
dcbf9037 | 12574 | static int |
5287ad62 JB |
12575 | el_type_of_type_chk (enum neon_el_type *type, unsigned *size, |
12576 | enum neon_type_mask mask) | |
12577 | { | |
dcbf9037 JB |
12578 | if ((mask & N_EQK) != 0) |
12579 | return FAIL; | |
12580 | ||
5287ad62 JB |
12581 | if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) |
12582 | *size = 8; | |
dcbf9037 | 12583 | else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) |
5287ad62 | 12584 | *size = 16; |
dcbf9037 | 12585 | else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) |
5287ad62 | 12586 | *size = 32; |
037e8744 | 12587 | else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) |
5287ad62 | 12588 | *size = 64; |
dcbf9037 JB |
12589 | else |
12590 | return FAIL; | |
12591 | ||
5287ad62 JB |
12592 | if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) |
12593 | *type = NT_signed; | |
dcbf9037 | 12594 | else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) |
5287ad62 | 12595 | *type = NT_unsigned; |
dcbf9037 | 12596 | else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) |
5287ad62 | 12597 | *type = NT_integer; |
dcbf9037 | 12598 | else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) |
5287ad62 | 12599 | *type = NT_untyped; |
dcbf9037 | 12600 | else if ((mask & (N_P8 | N_P16)) != 0) |
5287ad62 | 12601 | *type = NT_poly; |
037e8744 | 12602 | else if ((mask & (N_F32 | N_F64)) != 0) |
5287ad62 | 12603 | *type = NT_float; |
dcbf9037 JB |
12604 | else |
12605 | return FAIL; | |
5f4273c7 | 12606 | |
dcbf9037 | 12607 | return SUCCESS; |
5287ad62 JB |
12608 | } |
12609 | ||
12610 | /* Modify a bitmask of allowed types. This is only needed for type | |
12611 | relaxation. */ | |
12612 | ||
12613 | static unsigned | |
12614 | modify_types_allowed (unsigned allowed, unsigned mods) | |
12615 | { | |
12616 | unsigned size; | |
12617 | enum neon_el_type type; | |
12618 | unsigned destmask; | |
12619 | int i; | |
5f4273c7 | 12620 | |
5287ad62 | 12621 | destmask = 0; |
5f4273c7 | 12622 | |
5287ad62 JB |
12623 | for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) |
12624 | { | |
21d799b5 NC |
12625 | if (el_type_of_type_chk (&type, &size, |
12626 | (enum neon_type_mask) (allowed & i)) == SUCCESS) | |
dcbf9037 JB |
12627 | { |
12628 | neon_modify_type_size (mods, &type, &size); | |
12629 | destmask |= type_chk_of_el_type (type, size); | |
12630 | } | |
5287ad62 | 12631 | } |
5f4273c7 | 12632 | |
5287ad62 JB |
12633 | return destmask; |
12634 | } | |
12635 | ||
12636 | /* Check type and return type classification. | |
12637 | The manual states (paraphrase): If one datatype is given, it indicates the | |
12638 | type given in: | |
12639 | - the second operand, if there is one | |
12640 | - the operand, if there is no second operand | |
12641 | - the result, if there are no operands. | |
12642 | This isn't quite good enough though, so we use a concept of a "key" datatype | |
12643 | which is set on a per-instruction basis, which is the one which matters when | |
12644 | only one data type is written. | |
12645 | Note: this function has side-effects (e.g. filling in missing operands). All | |
037e8744 | 12646 | Neon instructions should call it before performing bit encoding. */ |
5287ad62 JB |
12647 | |
12648 | static struct neon_type_el | |
12649 | neon_check_type (unsigned els, enum neon_shape ns, ...) | |
12650 | { | |
12651 | va_list ap; | |
12652 | unsigned i, pass, key_el = 0; | |
12653 | unsigned types[NEON_MAX_TYPE_ELS]; | |
12654 | enum neon_el_type k_type = NT_invtype; | |
12655 | unsigned k_size = -1u; | |
12656 | struct neon_type_el badtype = {NT_invtype, -1}; | |
12657 | unsigned key_allowed = 0; | |
12658 | ||
12659 | /* Optional registers in Neon instructions are always (not) in operand 1. | |
12660 | Fill in the missing operand here, if it was omitted. */ | |
12661 | if (els > 1 && !inst.operands[1].present) | |
12662 | inst.operands[1] = inst.operands[0]; | |
12663 | ||
12664 | /* Suck up all the varargs. */ | |
12665 | va_start (ap, ns); | |
12666 | for (i = 0; i < els; i++) | |
12667 | { | |
12668 | unsigned thisarg = va_arg (ap, unsigned); | |
12669 | if (thisarg == N_IGNORE_TYPE) | |
12670 | { | |
12671 | va_end (ap); | |
12672 | return badtype; | |
12673 | } | |
12674 | types[i] = thisarg; | |
12675 | if ((thisarg & N_KEY) != 0) | |
12676 | key_el = i; | |
12677 | } | |
12678 | va_end (ap); | |
12679 | ||
dcbf9037 JB |
12680 | if (inst.vectype.elems > 0) |
12681 | for (i = 0; i < els; i++) | |
12682 | if (inst.operands[i].vectype.type != NT_invtype) | |
12683 | { | |
12684 | first_error (_("types specified in both the mnemonic and operands")); | |
12685 | return badtype; | |
12686 | } | |
12687 | ||
5287ad62 JB |
12688 | /* Duplicate inst.vectype elements here as necessary. |
12689 | FIXME: No idea if this is exactly the same as the ARM assembler, | |
12690 | particularly when an insn takes one register and one non-register | |
12691 | operand. */ | |
12692 | if (inst.vectype.elems == 1 && els > 1) | |
12693 | { | |
12694 | unsigned j; | |
12695 | inst.vectype.elems = els; | |
12696 | inst.vectype.el[key_el] = inst.vectype.el[0]; | |
12697 | for (j = 0; j < els; j++) | |
dcbf9037 JB |
12698 | if (j != key_el) |
12699 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12700 | types[j]); | |
12701 | } | |
12702 | else if (inst.vectype.elems == 0 && els > 0) | |
12703 | { | |
12704 | unsigned j; | |
12705 | /* No types were given after the mnemonic, so look for types specified | |
12706 | after each operand. We allow some flexibility here; as long as the | |
12707 | "key" operand has a type, we can infer the others. */ | |
12708 | for (j = 0; j < els; j++) | |
12709 | if (inst.operands[j].vectype.type != NT_invtype) | |
12710 | inst.vectype.el[j] = inst.operands[j].vectype; | |
12711 | ||
12712 | if (inst.operands[key_el].vectype.type != NT_invtype) | |
5287ad62 | 12713 | { |
dcbf9037 JB |
12714 | for (j = 0; j < els; j++) |
12715 | if (inst.operands[j].vectype.type == NT_invtype) | |
12716 | inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], | |
12717 | types[j]); | |
12718 | } | |
12719 | else | |
12720 | { | |
12721 | first_error (_("operand types can't be inferred")); | |
12722 | return badtype; | |
5287ad62 JB |
12723 | } |
12724 | } | |
12725 | else if (inst.vectype.elems != els) | |
12726 | { | |
dcbf9037 | 12727 | first_error (_("type specifier has the wrong number of parts")); |
5287ad62 JB |
12728 | return badtype; |
12729 | } | |
12730 | ||
12731 | for (pass = 0; pass < 2; pass++) | |
12732 | { | |
12733 | for (i = 0; i < els; i++) | |
12734 | { | |
12735 | unsigned thisarg = types[i]; | |
12736 | unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) | |
12737 | ? modify_types_allowed (key_allowed, thisarg) : thisarg; | |
12738 | enum neon_el_type g_type = inst.vectype.el[i].type; | |
12739 | unsigned g_size = inst.vectype.el[i].size; | |
12740 | ||
12741 | /* Decay more-specific signed & unsigned types to sign-insensitive | |
12742 | integer types if sign-specific variants are unavailable. */ | |
12743 | if ((g_type == NT_signed || g_type == NT_unsigned) | |
12744 | && (types_allowed & N_SU_ALL) == 0) | |
12745 | g_type = NT_integer; | |
12746 | ||
12747 | /* If only untyped args are allowed, decay any more specific types to | |
12748 | them. Some instructions only care about signs for some element | |
12749 | sizes, so handle that properly. */ | |
12750 | if ((g_size == 8 && (types_allowed & N_8) != 0) | |
12751 | || (g_size == 16 && (types_allowed & N_16) != 0) | |
12752 | || (g_size == 32 && (types_allowed & N_32) != 0) | |
12753 | || (g_size == 64 && (types_allowed & N_64) != 0)) | |
12754 | g_type = NT_untyped; | |
12755 | ||
12756 | if (pass == 0) | |
12757 | { | |
12758 | if ((thisarg & N_KEY) != 0) | |
12759 | { | |
12760 | k_type = g_type; | |
12761 | k_size = g_size; | |
12762 | key_allowed = thisarg & ~N_KEY; | |
12763 | } | |
12764 | } | |
12765 | else | |
12766 | { | |
037e8744 JB |
12767 | if ((thisarg & N_VFP) != 0) |
12768 | { | |
99b253c5 NC |
12769 | enum neon_shape_el regshape; |
12770 | unsigned regwidth, match; | |
12771 | ||
12772 | /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */ | |
12773 | if (ns == NS_NULL) | |
12774 | { | |
12775 | first_error (_("invalid instruction shape")); | |
12776 | return badtype; | |
12777 | } | |
12778 | regshape = neon_shape_tab[ns].el[i]; | |
12779 | regwidth = neon_shape_el_size[regshape]; | |
037e8744 JB |
12780 | |
12781 | /* In VFP mode, operands must match register widths. If we | |
12782 | have a key operand, use its width, else use the width of | |
12783 | the current operand. */ | |
12784 | if (k_size != -1u) | |
12785 | match = k_size; | |
12786 | else | |
12787 | match = g_size; | |
12788 | ||
12789 | if (regwidth != match) | |
12790 | { | |
12791 | first_error (_("operand size must match register width")); | |
12792 | return badtype; | |
12793 | } | |
12794 | } | |
5f4273c7 | 12795 | |
5287ad62 JB |
12796 | if ((thisarg & N_EQK) == 0) |
12797 | { | |
12798 | unsigned given_type = type_chk_of_el_type (g_type, g_size); | |
12799 | ||
12800 | if ((given_type & types_allowed) == 0) | |
12801 | { | |
dcbf9037 | 12802 | first_error (_("bad type in Neon instruction")); |
5287ad62 JB |
12803 | return badtype; |
12804 | } | |
12805 | } | |
12806 | else | |
12807 | { | |
12808 | enum neon_el_type mod_k_type = k_type; | |
12809 | unsigned mod_k_size = k_size; | |
12810 | neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); | |
12811 | if (g_type != mod_k_type || g_size != mod_k_size) | |
12812 | { | |
dcbf9037 | 12813 | first_error (_("inconsistent types in Neon instruction")); |
5287ad62 JB |
12814 | return badtype; |
12815 | } | |
12816 | } | |
12817 | } | |
12818 | } | |
12819 | } | |
12820 | ||
12821 | return inst.vectype.el[key_el]; | |
12822 | } | |
12823 | ||
037e8744 | 12824 | /* Neon-style VFP instruction forwarding. */ |
5287ad62 | 12825 | |
037e8744 JB |
12826 | /* Thumb VFP instructions have 0xE in the condition field. */ |
12827 | ||
12828 | static void | |
12829 | do_vfp_cond_or_thumb (void) | |
5287ad62 | 12830 | { |
88714cb8 DG |
12831 | inst.is_neon = 1; |
12832 | ||
5287ad62 | 12833 | if (thumb_mode) |
037e8744 | 12834 | inst.instruction |= 0xe0000000; |
5287ad62 | 12835 | else |
037e8744 | 12836 | inst.instruction |= inst.cond << 28; |
5287ad62 JB |
12837 | } |
12838 | ||
037e8744 JB |
12839 | /* Look up and encode a simple mnemonic, for use as a helper function for the |
12840 | Neon-style VFP syntax. This avoids duplication of bits of the insns table, | |
12841 | etc. It is assumed that operand parsing has already been done, and that the | |
12842 | operands are in the form expected by the given opcode (this isn't necessarily | |
12843 | the same as the form in which they were parsed, hence some massaging must | |
12844 | take place before this function is called). | |
12845 | Checks current arch version against that in the looked-up opcode. */ | |
5287ad62 | 12846 | |
037e8744 JB |
12847 | static void |
12848 | do_vfp_nsyn_opcode (const char *opname) | |
5287ad62 | 12849 | { |
037e8744 | 12850 | const struct asm_opcode *opcode; |
5f4273c7 | 12851 | |
21d799b5 | 12852 | opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname); |
5287ad62 | 12853 | |
037e8744 JB |
12854 | if (!opcode) |
12855 | abort (); | |
5287ad62 | 12856 | |
037e8744 JB |
12857 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, |
12858 | thumb_mode ? *opcode->tvariant : *opcode->avariant), | |
12859 | _(BAD_FPU)); | |
5287ad62 | 12860 | |
88714cb8 DG |
12861 | inst.is_neon = 1; |
12862 | ||
037e8744 JB |
12863 | if (thumb_mode) |
12864 | { | |
12865 | inst.instruction = opcode->tvalue; | |
12866 | opcode->tencode (); | |
12867 | } | |
12868 | else | |
12869 | { | |
12870 | inst.instruction = (inst.cond << 28) | opcode->avalue; | |
12871 | opcode->aencode (); | |
12872 | } | |
12873 | } | |
5287ad62 JB |
12874 | |
12875 | static void | |
037e8744 | 12876 | do_vfp_nsyn_add_sub (enum neon_shape rs) |
5287ad62 | 12877 | { |
037e8744 JB |
12878 | int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; |
12879 | ||
12880 | if (rs == NS_FFF) | |
12881 | { | |
12882 | if (is_add) | |
12883 | do_vfp_nsyn_opcode ("fadds"); | |
12884 | else | |
12885 | do_vfp_nsyn_opcode ("fsubs"); | |
12886 | } | |
12887 | else | |
12888 | { | |
12889 | if (is_add) | |
12890 | do_vfp_nsyn_opcode ("faddd"); | |
12891 | else | |
12892 | do_vfp_nsyn_opcode ("fsubd"); | |
12893 | } | |
12894 | } | |
12895 | ||
12896 | /* Check operand types to see if this is a VFP instruction, and if so call | |
12897 | PFN (). */ | |
12898 | ||
12899 | static int | |
12900 | try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) | |
12901 | { | |
12902 | enum neon_shape rs; | |
12903 | struct neon_type_el et; | |
12904 | ||
12905 | switch (args) | |
12906 | { | |
12907 | case 2: | |
12908 | rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
12909 | et = neon_check_type (2, rs, | |
12910 | N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12911 | break; | |
5f4273c7 | 12912 | |
037e8744 JB |
12913 | case 3: |
12914 | rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
12915 | et = neon_check_type (3, rs, | |
12916 | N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
12917 | break; | |
12918 | ||
12919 | default: | |
12920 | abort (); | |
12921 | } | |
12922 | ||
12923 | if (et.type != NT_invtype) | |
12924 | { | |
12925 | pfn (rs); | |
12926 | return SUCCESS; | |
12927 | } | |
037e8744 | 12928 | |
99b253c5 | 12929 | inst.error = NULL; |
037e8744 JB |
12930 | return FAIL; |
12931 | } | |
12932 | ||
12933 | static void | |
12934 | do_vfp_nsyn_mla_mls (enum neon_shape rs) | |
12935 | { | |
12936 | int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; | |
5f4273c7 | 12937 | |
037e8744 JB |
12938 | if (rs == NS_FFF) |
12939 | { | |
12940 | if (is_mla) | |
12941 | do_vfp_nsyn_opcode ("fmacs"); | |
12942 | else | |
1ee69515 | 12943 | do_vfp_nsyn_opcode ("fnmacs"); |
037e8744 JB |
12944 | } |
12945 | else | |
12946 | { | |
12947 | if (is_mla) | |
12948 | do_vfp_nsyn_opcode ("fmacd"); | |
12949 | else | |
1ee69515 | 12950 | do_vfp_nsyn_opcode ("fnmacd"); |
037e8744 JB |
12951 | } |
12952 | } | |
12953 | ||
62f3b8c8 PB |
12954 | static void |
12955 | do_vfp_nsyn_fma_fms (enum neon_shape rs) | |
12956 | { | |
12957 | int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma; | |
12958 | ||
12959 | if (rs == NS_FFF) | |
12960 | { | |
12961 | if (is_fma) | |
12962 | do_vfp_nsyn_opcode ("ffmas"); | |
12963 | else | |
12964 | do_vfp_nsyn_opcode ("ffnmas"); | |
12965 | } | |
12966 | else | |
12967 | { | |
12968 | if (is_fma) | |
12969 | do_vfp_nsyn_opcode ("ffmad"); | |
12970 | else | |
12971 | do_vfp_nsyn_opcode ("ffnmad"); | |
12972 | } | |
12973 | } | |
12974 | ||
037e8744 JB |
12975 | static void |
12976 | do_vfp_nsyn_mul (enum neon_shape rs) | |
12977 | { | |
12978 | if (rs == NS_FFF) | |
12979 | do_vfp_nsyn_opcode ("fmuls"); | |
12980 | else | |
12981 | do_vfp_nsyn_opcode ("fmuld"); | |
12982 | } | |
12983 | ||
12984 | static void | |
12985 | do_vfp_nsyn_abs_neg (enum neon_shape rs) | |
12986 | { | |
12987 | int is_neg = (inst.instruction & 0x80) != 0; | |
12988 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); | |
12989 | ||
12990 | if (rs == NS_FF) | |
12991 | { | |
12992 | if (is_neg) | |
12993 | do_vfp_nsyn_opcode ("fnegs"); | |
12994 | else | |
12995 | do_vfp_nsyn_opcode ("fabss"); | |
12996 | } | |
12997 | else | |
12998 | { | |
12999 | if (is_neg) | |
13000 | do_vfp_nsyn_opcode ("fnegd"); | |
13001 | else | |
13002 | do_vfp_nsyn_opcode ("fabsd"); | |
13003 | } | |
13004 | } | |
13005 | ||
13006 | /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision | |
13007 | insns belong to Neon, and are handled elsewhere. */ | |
13008 | ||
13009 | static void | |
13010 | do_vfp_nsyn_ldm_stm (int is_dbmode) | |
13011 | { | |
13012 | int is_ldm = (inst.instruction & (1 << 20)) != 0; | |
13013 | if (is_ldm) | |
13014 | { | |
13015 | if (is_dbmode) | |
13016 | do_vfp_nsyn_opcode ("fldmdbs"); | |
13017 | else | |
13018 | do_vfp_nsyn_opcode ("fldmias"); | |
13019 | } | |
13020 | else | |
13021 | { | |
13022 | if (is_dbmode) | |
13023 | do_vfp_nsyn_opcode ("fstmdbs"); | |
13024 | else | |
13025 | do_vfp_nsyn_opcode ("fstmias"); | |
13026 | } | |
13027 | } | |
13028 | ||
037e8744 JB |
13029 | static void |
13030 | do_vfp_nsyn_sqrt (void) | |
13031 | { | |
13032 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13033 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13034 | |
037e8744 JB |
13035 | if (rs == NS_FF) |
13036 | do_vfp_nsyn_opcode ("fsqrts"); | |
13037 | else | |
13038 | do_vfp_nsyn_opcode ("fsqrtd"); | |
13039 | } | |
13040 | ||
13041 | static void | |
13042 | do_vfp_nsyn_div (void) | |
13043 | { | |
13044 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13045 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
13046 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13047 | |
037e8744 JB |
13048 | if (rs == NS_FFF) |
13049 | do_vfp_nsyn_opcode ("fdivs"); | |
13050 | else | |
13051 | do_vfp_nsyn_opcode ("fdivd"); | |
13052 | } | |
13053 | ||
13054 | static void | |
13055 | do_vfp_nsyn_nmul (void) | |
13056 | { | |
13057 | enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); | |
13058 | neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, | |
13059 | N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13060 | |
037e8744 JB |
13061 | if (rs == NS_FFF) |
13062 | { | |
88714cb8 | 13063 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
13064 | do_vfp_sp_dyadic (); |
13065 | } | |
13066 | else | |
13067 | { | |
88714cb8 | 13068 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
13069 | do_vfp_dp_rd_rn_rm (); |
13070 | } | |
13071 | do_vfp_cond_or_thumb (); | |
13072 | } | |
13073 | ||
13074 | static void | |
13075 | do_vfp_nsyn_cmp (void) | |
13076 | { | |
13077 | if (inst.operands[1].isreg) | |
13078 | { | |
13079 | enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); | |
13080 | neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); | |
5f4273c7 | 13081 | |
037e8744 JB |
13082 | if (rs == NS_FF) |
13083 | { | |
88714cb8 | 13084 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
13085 | do_vfp_sp_monadic (); |
13086 | } | |
13087 | else | |
13088 | { | |
88714cb8 | 13089 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
13090 | do_vfp_dp_rd_rm (); |
13091 | } | |
13092 | } | |
13093 | else | |
13094 | { | |
13095 | enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); | |
13096 | neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); | |
13097 | ||
13098 | switch (inst.instruction & 0x0fffffff) | |
13099 | { | |
13100 | case N_MNEM_vcmp: | |
13101 | inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; | |
13102 | break; | |
13103 | case N_MNEM_vcmpe: | |
13104 | inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; | |
13105 | break; | |
13106 | default: | |
13107 | abort (); | |
13108 | } | |
5f4273c7 | 13109 | |
037e8744 JB |
13110 | if (rs == NS_FI) |
13111 | { | |
88714cb8 | 13112 | NEON_ENCODE (SINGLE, inst); |
037e8744 JB |
13113 | do_vfp_sp_compare_z (); |
13114 | } | |
13115 | else | |
13116 | { | |
88714cb8 | 13117 | NEON_ENCODE (DOUBLE, inst); |
037e8744 JB |
13118 | do_vfp_dp_rd (); |
13119 | } | |
13120 | } | |
13121 | do_vfp_cond_or_thumb (); | |
13122 | } | |
13123 | ||
13124 | static void | |
13125 | nsyn_insert_sp (void) | |
13126 | { | |
13127 | inst.operands[1] = inst.operands[0]; | |
13128 | memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); | |
fdfde340 | 13129 | inst.operands[0].reg = REG_SP; |
037e8744 JB |
13130 | inst.operands[0].isreg = 1; |
13131 | inst.operands[0].writeback = 1; | |
13132 | inst.operands[0].present = 1; | |
13133 | } | |
13134 | ||
13135 | static void | |
13136 | do_vfp_nsyn_push (void) | |
13137 | { | |
13138 | nsyn_insert_sp (); | |
13139 | if (inst.operands[1].issingle) | |
13140 | do_vfp_nsyn_opcode ("fstmdbs"); | |
13141 | else | |
13142 | do_vfp_nsyn_opcode ("fstmdbd"); | |
13143 | } | |
13144 | ||
13145 | static void | |
13146 | do_vfp_nsyn_pop (void) | |
13147 | { | |
13148 | nsyn_insert_sp (); | |
13149 | if (inst.operands[1].issingle) | |
22b5b651 | 13150 | do_vfp_nsyn_opcode ("fldmias"); |
037e8744 | 13151 | else |
22b5b651 | 13152 | do_vfp_nsyn_opcode ("fldmiad"); |
037e8744 JB |
13153 | } |
13154 | ||
13155 | /* Fix up Neon data-processing instructions, ORing in the correct bits for | |
13156 | ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ | |
13157 | ||
88714cb8 DG |
13158 | static void |
13159 | neon_dp_fixup (struct arm_it* insn) | |
037e8744 | 13160 | { |
88714cb8 DG |
13161 | unsigned int i = insn->instruction; |
13162 | insn->is_neon = 1; | |
13163 | ||
037e8744 JB |
13164 | if (thumb_mode) |
13165 | { | |
13166 | /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ | |
13167 | if (i & (1 << 24)) | |
13168 | i |= 1 << 28; | |
5f4273c7 | 13169 | |
037e8744 | 13170 | i &= ~(1 << 24); |
5f4273c7 | 13171 | |
037e8744 JB |
13172 | i |= 0xef000000; |
13173 | } | |
13174 | else | |
13175 | i |= 0xf2000000; | |
5f4273c7 | 13176 | |
88714cb8 | 13177 | insn->instruction = i; |
037e8744 JB |
13178 | } |
13179 | ||
13180 | /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 | |
13181 | (0, 1, 2, 3). */ | |
13182 | ||
13183 | static unsigned | |
13184 | neon_logbits (unsigned x) | |
13185 | { | |
13186 | return ffs (x) - 4; | |
13187 | } | |
13188 | ||
13189 | #define LOW4(R) ((R) & 0xf) | |
13190 | #define HI1(R) (((R) >> 4) & 1) | |
13191 | ||
13192 | /* Encode insns with bit pattern: | |
13193 | ||
13194 | |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
13195 | | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | | |
5f4273c7 | 13196 | |
037e8744 JB |
13197 | SIZE is passed in bits. -1 means size field isn't changed, in case it has a |
13198 | different meaning for some instruction. */ | |
13199 | ||
13200 | static void | |
13201 | neon_three_same (int isquad, int ubit, int size) | |
13202 | { | |
13203 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13204 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13205 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13206 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13207 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
13208 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
13209 | inst.instruction |= (isquad != 0) << 6; | |
13210 | inst.instruction |= (ubit != 0) << 24; | |
13211 | if (size != -1) | |
13212 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 13213 | |
88714cb8 | 13214 | neon_dp_fixup (&inst); |
037e8744 JB |
13215 | } |
13216 | ||
13217 | /* Encode instructions of the form: | |
13218 | ||
13219 | |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| | |
13220 | | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | | |
5287ad62 JB |
13221 | |
13222 | Don't write size if SIZE == -1. */ | |
13223 | ||
13224 | static void | |
13225 | neon_two_same (int qbit, int ubit, int size) | |
13226 | { | |
13227 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13228 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13229 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13230 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13231 | inst.instruction |= (qbit != 0) << 6; | |
13232 | inst.instruction |= (ubit != 0) << 24; | |
13233 | ||
13234 | if (size != -1) | |
13235 | inst.instruction |= neon_logbits (size) << 18; | |
13236 | ||
88714cb8 | 13237 | neon_dp_fixup (&inst); |
5287ad62 JB |
13238 | } |
13239 | ||
13240 | /* Neon instruction encoders, in approximate order of appearance. */ | |
13241 | ||
13242 | static void | |
13243 | do_neon_dyadic_i_su (void) | |
13244 | { | |
037e8744 | 13245 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13246 | struct neon_type_el et = neon_check_type (3, rs, |
13247 | N_EQK, N_EQK, N_SU_32 | N_KEY); | |
037e8744 | 13248 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13249 | } |
13250 | ||
13251 | static void | |
13252 | do_neon_dyadic_i64_su (void) | |
13253 | { | |
037e8744 | 13254 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13255 | struct neon_type_el et = neon_check_type (3, rs, |
13256 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
037e8744 | 13257 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13258 | } |
13259 | ||
13260 | static void | |
13261 | neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, | |
13262 | unsigned immbits) | |
13263 | { | |
13264 | unsigned size = et.size >> 3; | |
13265 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
13266 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13267 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13268 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
13269 | inst.instruction |= (isquad != 0) << 6; | |
13270 | inst.instruction |= immbits << 16; | |
13271 | inst.instruction |= (size >> 3) << 7; | |
13272 | inst.instruction |= (size & 0x7) << 19; | |
13273 | if (write_ubit) | |
13274 | inst.instruction |= (uval != 0) << 24; | |
13275 | ||
88714cb8 | 13276 | neon_dp_fixup (&inst); |
5287ad62 JB |
13277 | } |
13278 | ||
13279 | static void | |
13280 | do_neon_shl_imm (void) | |
13281 | { | |
13282 | if (!inst.operands[2].isreg) | |
13283 | { | |
037e8744 | 13284 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 13285 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); |
88714cb8 | 13286 | NEON_ENCODE (IMMED, inst); |
037e8744 | 13287 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); |
5287ad62 JB |
13288 | } |
13289 | else | |
13290 | { | |
037e8744 | 13291 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13292 | struct neon_type_el et = neon_check_type (3, rs, |
13293 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
13294 | unsigned int tmp; |
13295 | ||
13296 | /* VSHL/VQSHL 3-register variants have syntax such as: | |
13297 | vshl.xx Dd, Dm, Dn | |
13298 | whereas other 3-register operations encoded by neon_three_same have | |
13299 | syntax like: | |
13300 | vadd.xx Dd, Dn, Dm | |
13301 | (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg | |
13302 | here. */ | |
13303 | tmp = inst.operands[2].reg; | |
13304 | inst.operands[2].reg = inst.operands[1].reg; | |
13305 | inst.operands[1].reg = tmp; | |
88714cb8 | 13306 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13307 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13308 | } |
13309 | } | |
13310 | ||
13311 | static void | |
13312 | do_neon_qshl_imm (void) | |
13313 | { | |
13314 | if (!inst.operands[2].isreg) | |
13315 | { | |
037e8744 | 13316 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 | 13317 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
627907b7 | 13318 | |
88714cb8 | 13319 | NEON_ENCODE (IMMED, inst); |
037e8744 | 13320 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
13321 | inst.operands[2].imm); |
13322 | } | |
13323 | else | |
13324 | { | |
037e8744 | 13325 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13326 | struct neon_type_el et = neon_check_type (3, rs, |
13327 | N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); | |
627907b7 JB |
13328 | unsigned int tmp; |
13329 | ||
13330 | /* See note in do_neon_shl_imm. */ | |
13331 | tmp = inst.operands[2].reg; | |
13332 | inst.operands[2].reg = inst.operands[1].reg; | |
13333 | inst.operands[1].reg = tmp; | |
88714cb8 | 13334 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13335 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); |
5287ad62 JB |
13336 | } |
13337 | } | |
13338 | ||
627907b7 JB |
13339 | static void |
13340 | do_neon_rshl (void) | |
13341 | { | |
13342 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); | |
13343 | struct neon_type_el et = neon_check_type (3, rs, | |
13344 | N_EQK, N_EQK, N_SU_ALL | N_KEY); | |
13345 | unsigned int tmp; | |
13346 | ||
13347 | tmp = inst.operands[2].reg; | |
13348 | inst.operands[2].reg = inst.operands[1].reg; | |
13349 | inst.operands[1].reg = tmp; | |
13350 | neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); | |
13351 | } | |
13352 | ||
5287ad62 JB |
13353 | static int |
13354 | neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) | |
13355 | { | |
036dc3f7 PB |
13356 | /* Handle .I8 pseudo-instructions. */ |
13357 | if (size == 8) | |
5287ad62 | 13358 | { |
5287ad62 JB |
13359 | /* Unfortunately, this will make everything apart from zero out-of-range. |
13360 | FIXME is this the intended semantics? There doesn't seem much point in | |
13361 | accepting .I8 if so. */ | |
13362 | immediate |= immediate << 8; | |
13363 | size = 16; | |
036dc3f7 PB |
13364 | } |
13365 | ||
13366 | if (size >= 32) | |
13367 | { | |
13368 | if (immediate == (immediate & 0x000000ff)) | |
13369 | { | |
13370 | *immbits = immediate; | |
13371 | return 0x1; | |
13372 | } | |
13373 | else if (immediate == (immediate & 0x0000ff00)) | |
13374 | { | |
13375 | *immbits = immediate >> 8; | |
13376 | return 0x3; | |
13377 | } | |
13378 | else if (immediate == (immediate & 0x00ff0000)) | |
13379 | { | |
13380 | *immbits = immediate >> 16; | |
13381 | return 0x5; | |
13382 | } | |
13383 | else if (immediate == (immediate & 0xff000000)) | |
13384 | { | |
13385 | *immbits = immediate >> 24; | |
13386 | return 0x7; | |
13387 | } | |
13388 | if ((immediate & 0xffff) != (immediate >> 16)) | |
13389 | goto bad_immediate; | |
13390 | immediate &= 0xffff; | |
5287ad62 JB |
13391 | } |
13392 | ||
13393 | if (immediate == (immediate & 0x000000ff)) | |
13394 | { | |
13395 | *immbits = immediate; | |
036dc3f7 | 13396 | return 0x9; |
5287ad62 JB |
13397 | } |
13398 | else if (immediate == (immediate & 0x0000ff00)) | |
13399 | { | |
13400 | *immbits = immediate >> 8; | |
036dc3f7 | 13401 | return 0xb; |
5287ad62 JB |
13402 | } |
13403 | ||
13404 | bad_immediate: | |
dcbf9037 | 13405 | first_error (_("immediate value out of range")); |
5287ad62 JB |
13406 | return FAIL; |
13407 | } | |
13408 | ||
13409 | /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits | |
13410 | A, B, C, D. */ | |
13411 | ||
13412 | static int | |
13413 | neon_bits_same_in_bytes (unsigned imm) | |
13414 | { | |
13415 | return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) | |
13416 | && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) | |
13417 | && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) | |
13418 | && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); | |
13419 | } | |
13420 | ||
13421 | /* For immediate of above form, return 0bABCD. */ | |
13422 | ||
13423 | static unsigned | |
13424 | neon_squash_bits (unsigned imm) | |
13425 | { | |
13426 | return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) | |
13427 | | ((imm & 0x01000000) >> 21); | |
13428 | } | |
13429 | ||
136da414 | 13430 | /* Compress quarter-float representation to 0b...000 abcdefgh. */ |
5287ad62 JB |
13431 | |
13432 | static unsigned | |
13433 | neon_qfloat_bits (unsigned imm) | |
13434 | { | |
136da414 | 13435 | return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); |
5287ad62 JB |
13436 | } |
13437 | ||
13438 | /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into | |
13439 | the instruction. *OP is passed as the initial value of the op field, and | |
13440 | may be set to a different value depending on the constant (i.e. | |
13441 | "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not | |
5f4273c7 | 13442 | MVN). If the immediate looks like a repeated pattern then also |
036dc3f7 | 13443 | try smaller element sizes. */ |
5287ad62 JB |
13444 | |
13445 | static int | |
c96612cc JB |
13446 | neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, |
13447 | unsigned *immbits, int *op, int size, | |
13448 | enum neon_el_type type) | |
5287ad62 | 13449 | { |
c96612cc JB |
13450 | /* Only permit float immediates (including 0.0/-0.0) if the operand type is |
13451 | float. */ | |
13452 | if (type == NT_float && !float_p) | |
13453 | return FAIL; | |
13454 | ||
136da414 JB |
13455 | if (type == NT_float && is_quarter_float (immlo) && immhi == 0) |
13456 | { | |
13457 | if (size != 32 || *op == 1) | |
13458 | return FAIL; | |
13459 | *immbits = neon_qfloat_bits (immlo); | |
13460 | return 0xf; | |
13461 | } | |
036dc3f7 PB |
13462 | |
13463 | if (size == 64) | |
5287ad62 | 13464 | { |
036dc3f7 PB |
13465 | if (neon_bits_same_in_bytes (immhi) |
13466 | && neon_bits_same_in_bytes (immlo)) | |
13467 | { | |
13468 | if (*op == 1) | |
13469 | return FAIL; | |
13470 | *immbits = (neon_squash_bits (immhi) << 4) | |
13471 | | neon_squash_bits (immlo); | |
13472 | *op = 1; | |
13473 | return 0xe; | |
13474 | } | |
13475 | ||
13476 | if (immhi != immlo) | |
13477 | return FAIL; | |
5287ad62 | 13478 | } |
036dc3f7 PB |
13479 | |
13480 | if (size >= 32) | |
5287ad62 | 13481 | { |
036dc3f7 PB |
13482 | if (immlo == (immlo & 0x000000ff)) |
13483 | { | |
13484 | *immbits = immlo; | |
13485 | return 0x0; | |
13486 | } | |
13487 | else if (immlo == (immlo & 0x0000ff00)) | |
13488 | { | |
13489 | *immbits = immlo >> 8; | |
13490 | return 0x2; | |
13491 | } | |
13492 | else if (immlo == (immlo & 0x00ff0000)) | |
13493 | { | |
13494 | *immbits = immlo >> 16; | |
13495 | return 0x4; | |
13496 | } | |
13497 | else if (immlo == (immlo & 0xff000000)) | |
13498 | { | |
13499 | *immbits = immlo >> 24; | |
13500 | return 0x6; | |
13501 | } | |
13502 | else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) | |
13503 | { | |
13504 | *immbits = (immlo >> 8) & 0xff; | |
13505 | return 0xc; | |
13506 | } | |
13507 | else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) | |
13508 | { | |
13509 | *immbits = (immlo >> 16) & 0xff; | |
13510 | return 0xd; | |
13511 | } | |
13512 | ||
13513 | if ((immlo & 0xffff) != (immlo >> 16)) | |
13514 | return FAIL; | |
13515 | immlo &= 0xffff; | |
5287ad62 | 13516 | } |
036dc3f7 PB |
13517 | |
13518 | if (size >= 16) | |
5287ad62 | 13519 | { |
036dc3f7 PB |
13520 | if (immlo == (immlo & 0x000000ff)) |
13521 | { | |
13522 | *immbits = immlo; | |
13523 | return 0x8; | |
13524 | } | |
13525 | else if (immlo == (immlo & 0x0000ff00)) | |
13526 | { | |
13527 | *immbits = immlo >> 8; | |
13528 | return 0xa; | |
13529 | } | |
13530 | ||
13531 | if ((immlo & 0xff) != (immlo >> 8)) | |
13532 | return FAIL; | |
13533 | immlo &= 0xff; | |
5287ad62 | 13534 | } |
036dc3f7 PB |
13535 | |
13536 | if (immlo == (immlo & 0x000000ff)) | |
5287ad62 | 13537 | { |
036dc3f7 PB |
13538 | /* Don't allow MVN with 8-bit immediate. */ |
13539 | if (*op == 1) | |
13540 | return FAIL; | |
13541 | *immbits = immlo; | |
13542 | return 0xe; | |
5287ad62 | 13543 | } |
5287ad62 JB |
13544 | |
13545 | return FAIL; | |
13546 | } | |
13547 | ||
13548 | /* Write immediate bits [7:0] to the following locations: | |
13549 | ||
13550 | |28/24|23 19|18 16|15 4|3 0| | |
13551 | | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| | |
13552 | ||
13553 | This function is used by VMOV/VMVN/VORR/VBIC. */ | |
13554 | ||
13555 | static void | |
13556 | neon_write_immbits (unsigned immbits) | |
13557 | { | |
13558 | inst.instruction |= immbits & 0xf; | |
13559 | inst.instruction |= ((immbits >> 4) & 0x7) << 16; | |
13560 | inst.instruction |= ((immbits >> 7) & 0x1) << 24; | |
13561 | } | |
13562 | ||
13563 | /* Invert low-order SIZE bits of XHI:XLO. */ | |
13564 | ||
13565 | static void | |
13566 | neon_invert_size (unsigned *xlo, unsigned *xhi, int size) | |
13567 | { | |
13568 | unsigned immlo = xlo ? *xlo : 0; | |
13569 | unsigned immhi = xhi ? *xhi : 0; | |
13570 | ||
13571 | switch (size) | |
13572 | { | |
13573 | case 8: | |
13574 | immlo = (~immlo) & 0xff; | |
13575 | break; | |
13576 | ||
13577 | case 16: | |
13578 | immlo = (~immlo) & 0xffff; | |
13579 | break; | |
13580 | ||
13581 | case 64: | |
13582 | immhi = (~immhi) & 0xffffffff; | |
13583 | /* fall through. */ | |
13584 | ||
13585 | case 32: | |
13586 | immlo = (~immlo) & 0xffffffff; | |
13587 | break; | |
13588 | ||
13589 | default: | |
13590 | abort (); | |
13591 | } | |
13592 | ||
13593 | if (xlo) | |
13594 | *xlo = immlo; | |
13595 | ||
13596 | if (xhi) | |
13597 | *xhi = immhi; | |
13598 | } | |
13599 | ||
13600 | static void | |
13601 | do_neon_logic (void) | |
13602 | { | |
13603 | if (inst.operands[2].present && inst.operands[2].isreg) | |
13604 | { | |
037e8744 | 13605 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13606 | neon_check_type (3, rs, N_IGNORE_TYPE); |
13607 | /* U bit and size field were set as part of the bitmask. */ | |
88714cb8 | 13608 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13609 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13610 | } |
13611 | else | |
13612 | { | |
4316f0d2 DG |
13613 | const int three_ops_form = (inst.operands[2].present |
13614 | && !inst.operands[2].isreg); | |
13615 | const int immoperand = (three_ops_form ? 2 : 1); | |
13616 | enum neon_shape rs = (three_ops_form | |
13617 | ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL) | |
13618 | : neon_select_shape (NS_DI, NS_QI, NS_NULL)); | |
037e8744 JB |
13619 | struct neon_type_el et = neon_check_type (2, rs, |
13620 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
21d799b5 | 13621 | enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff; |
5287ad62 JB |
13622 | unsigned immbits; |
13623 | int cmode; | |
5f4273c7 | 13624 | |
5287ad62 JB |
13625 | if (et.type == NT_invtype) |
13626 | return; | |
5f4273c7 | 13627 | |
4316f0d2 DG |
13628 | if (three_ops_form) |
13629 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
13630 | _("first and second operands shall be the same register")); | |
13631 | ||
88714cb8 | 13632 | NEON_ENCODE (IMMED, inst); |
5287ad62 | 13633 | |
4316f0d2 | 13634 | immbits = inst.operands[immoperand].imm; |
036dc3f7 PB |
13635 | if (et.size == 64) |
13636 | { | |
13637 | /* .i64 is a pseudo-op, so the immediate must be a repeating | |
13638 | pattern. */ | |
4316f0d2 DG |
13639 | if (immbits != (inst.operands[immoperand].regisimm ? |
13640 | inst.operands[immoperand].reg : 0)) | |
036dc3f7 PB |
13641 | { |
13642 | /* Set immbits to an invalid constant. */ | |
13643 | immbits = 0xdeadbeef; | |
13644 | } | |
13645 | } | |
13646 | ||
5287ad62 JB |
13647 | switch (opcode) |
13648 | { | |
13649 | case N_MNEM_vbic: | |
036dc3f7 | 13650 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13651 | break; |
5f4273c7 | 13652 | |
5287ad62 | 13653 | case N_MNEM_vorr: |
036dc3f7 | 13654 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); |
5287ad62 | 13655 | break; |
5f4273c7 | 13656 | |
5287ad62 JB |
13657 | case N_MNEM_vand: |
13658 | /* Pseudo-instruction for VBIC. */ | |
5287ad62 JB |
13659 | neon_invert_size (&immbits, 0, et.size); |
13660 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13661 | break; | |
5f4273c7 | 13662 | |
5287ad62 JB |
13663 | case N_MNEM_vorn: |
13664 | /* Pseudo-instruction for VORR. */ | |
5287ad62 JB |
13665 | neon_invert_size (&immbits, 0, et.size); |
13666 | cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); | |
13667 | break; | |
5f4273c7 | 13668 | |
5287ad62 JB |
13669 | default: |
13670 | abort (); | |
13671 | } | |
13672 | ||
13673 | if (cmode == FAIL) | |
13674 | return; | |
13675 | ||
037e8744 | 13676 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13677 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13678 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13679 | inst.instruction |= cmode << 8; | |
13680 | neon_write_immbits (immbits); | |
5f4273c7 | 13681 | |
88714cb8 | 13682 | neon_dp_fixup (&inst); |
5287ad62 JB |
13683 | } |
13684 | } | |
13685 | ||
13686 | static void | |
13687 | do_neon_bitfield (void) | |
13688 | { | |
037e8744 | 13689 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 | 13690 | neon_check_type (3, rs, N_IGNORE_TYPE); |
037e8744 | 13691 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13692 | } |
13693 | ||
13694 | static void | |
dcbf9037 JB |
13695 | neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, |
13696 | unsigned destbits) | |
5287ad62 | 13697 | { |
037e8744 | 13698 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
dcbf9037 JB |
13699 | struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, |
13700 | types | N_KEY); | |
5287ad62 JB |
13701 | if (et.type == NT_float) |
13702 | { | |
88714cb8 | 13703 | NEON_ENCODE (FLOAT, inst); |
037e8744 | 13704 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
13705 | } |
13706 | else | |
13707 | { | |
88714cb8 | 13708 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 13709 | neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); |
5287ad62 JB |
13710 | } |
13711 | } | |
13712 | ||
13713 | static void | |
13714 | do_neon_dyadic_if_su (void) | |
13715 | { | |
dcbf9037 | 13716 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13717 | } |
13718 | ||
13719 | static void | |
13720 | do_neon_dyadic_if_su_d (void) | |
13721 | { | |
13722 | /* This version only allow D registers, but that constraint is enforced during | |
13723 | operand parsing so we don't need to do anything extra here. */ | |
dcbf9037 | 13724 | neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); |
5287ad62 JB |
13725 | } |
13726 | ||
5287ad62 JB |
13727 | static void |
13728 | do_neon_dyadic_if_i_d (void) | |
13729 | { | |
428e3f1f PB |
13730 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13731 | affected if we specify unsigned args. */ | |
13732 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
5287ad62 JB |
13733 | } |
13734 | ||
037e8744 JB |
13735 | enum vfp_or_neon_is_neon_bits |
13736 | { | |
13737 | NEON_CHECK_CC = 1, | |
13738 | NEON_CHECK_ARCH = 2 | |
13739 | }; | |
13740 | ||
13741 | /* Call this function if an instruction which may have belonged to the VFP or | |
13742 | Neon instruction sets, but turned out to be a Neon instruction (due to the | |
13743 | operand types involved, etc.). We have to check and/or fix-up a couple of | |
13744 | things: | |
13745 | ||
13746 | - Make sure the user hasn't attempted to make a Neon instruction | |
13747 | conditional. | |
13748 | - Alter the value in the condition code field if necessary. | |
13749 | - Make sure that the arch supports Neon instructions. | |
13750 | ||
13751 | Which of these operations take place depends on bits from enum | |
13752 | vfp_or_neon_is_neon_bits. | |
13753 | ||
13754 | WARNING: This function has side effects! If NEON_CHECK_CC is used and the | |
13755 | current instruction's condition is COND_ALWAYS, the condition field is | |
13756 | changed to inst.uncond_value. This is necessary because instructions shared | |
13757 | between VFP and Neon may be conditional for the VFP variants only, and the | |
13758 | unconditional Neon version must have, e.g., 0xF in the condition field. */ | |
13759 | ||
13760 | static int | |
13761 | vfp_or_neon_is_neon (unsigned check) | |
13762 | { | |
13763 | /* Conditions are always legal in Thumb mode (IT blocks). */ | |
13764 | if (!thumb_mode && (check & NEON_CHECK_CC)) | |
13765 | { | |
13766 | if (inst.cond != COND_ALWAYS) | |
13767 | { | |
13768 | first_error (_(BAD_COND)); | |
13769 | return FAIL; | |
13770 | } | |
13771 | if (inst.uncond_value != -1) | |
13772 | inst.instruction |= inst.uncond_value << 28; | |
13773 | } | |
5f4273c7 | 13774 | |
037e8744 JB |
13775 | if ((check & NEON_CHECK_ARCH) |
13776 | && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) | |
13777 | { | |
13778 | first_error (_(BAD_FPU)); | |
13779 | return FAIL; | |
13780 | } | |
5f4273c7 | 13781 | |
037e8744 JB |
13782 | return SUCCESS; |
13783 | } | |
13784 | ||
5287ad62 JB |
13785 | static void |
13786 | do_neon_addsub_if_i (void) | |
13787 | { | |
037e8744 JB |
13788 | if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) |
13789 | return; | |
13790 | ||
13791 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13792 | return; | |
13793 | ||
5287ad62 JB |
13794 | /* The "untyped" case can't happen. Do this to stop the "U" bit being |
13795 | affected if we specify unsigned args. */ | |
dcbf9037 | 13796 | neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); |
5287ad62 JB |
13797 | } |
13798 | ||
13799 | /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the | |
13800 | result to be: | |
13801 | V<op> A,B (A is operand 0, B is operand 2) | |
13802 | to mean: | |
13803 | V<op> A,B,A | |
13804 | not: | |
13805 | V<op> A,B,B | |
13806 | so handle that case specially. */ | |
13807 | ||
13808 | static void | |
13809 | neon_exchange_operands (void) | |
13810 | { | |
13811 | void *scratch = alloca (sizeof (inst.operands[0])); | |
13812 | if (inst.operands[1].present) | |
13813 | { | |
13814 | /* Swap operands[1] and operands[2]. */ | |
13815 | memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); | |
13816 | inst.operands[1] = inst.operands[2]; | |
13817 | memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); | |
13818 | } | |
13819 | else | |
13820 | { | |
13821 | inst.operands[1] = inst.operands[2]; | |
13822 | inst.operands[2] = inst.operands[0]; | |
13823 | } | |
13824 | } | |
13825 | ||
13826 | static void | |
13827 | neon_compare (unsigned regtypes, unsigned immtypes, int invert) | |
13828 | { | |
13829 | if (inst.operands[2].isreg) | |
13830 | { | |
13831 | if (invert) | |
13832 | neon_exchange_operands (); | |
dcbf9037 | 13833 | neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); |
5287ad62 JB |
13834 | } |
13835 | else | |
13836 | { | |
037e8744 | 13837 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
dcbf9037 JB |
13838 | struct neon_type_el et = neon_check_type (2, rs, |
13839 | N_EQK | N_SIZ, immtypes | N_KEY); | |
5287ad62 | 13840 | |
88714cb8 | 13841 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
13842 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13843 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13844 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
13845 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 13846 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
13847 | inst.instruction |= (et.type == NT_float) << 10; |
13848 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 13849 | |
88714cb8 | 13850 | neon_dp_fixup (&inst); |
5287ad62 JB |
13851 | } |
13852 | } | |
13853 | ||
13854 | static void | |
13855 | do_neon_cmp (void) | |
13856 | { | |
13857 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); | |
13858 | } | |
13859 | ||
13860 | static void | |
13861 | do_neon_cmp_inv (void) | |
13862 | { | |
13863 | neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); | |
13864 | } | |
13865 | ||
13866 | static void | |
13867 | do_neon_ceq (void) | |
13868 | { | |
13869 | neon_compare (N_IF_32, N_IF_32, FALSE); | |
13870 | } | |
13871 | ||
13872 | /* For multiply instructions, we have the possibility of 16-bit or 32-bit | |
13873 | scalars, which are encoded in 5 bits, M : Rm. | |
13874 | For 16-bit scalars, the register is encoded in Rm[2:0] and the index in | |
13875 | M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the | |
13876 | index in M. */ | |
13877 | ||
13878 | static unsigned | |
13879 | neon_scalar_for_mul (unsigned scalar, unsigned elsize) | |
13880 | { | |
dcbf9037 JB |
13881 | unsigned regno = NEON_SCALAR_REG (scalar); |
13882 | unsigned elno = NEON_SCALAR_INDEX (scalar); | |
5287ad62 JB |
13883 | |
13884 | switch (elsize) | |
13885 | { | |
13886 | case 16: | |
13887 | if (regno > 7 || elno > 3) | |
13888 | goto bad_scalar; | |
13889 | return regno | (elno << 3); | |
5f4273c7 | 13890 | |
5287ad62 JB |
13891 | case 32: |
13892 | if (regno > 15 || elno > 1) | |
13893 | goto bad_scalar; | |
13894 | return regno | (elno << 4); | |
13895 | ||
13896 | default: | |
13897 | bad_scalar: | |
dcbf9037 | 13898 | first_error (_("scalar out of range for multiply instruction")); |
5287ad62 JB |
13899 | } |
13900 | ||
13901 | return 0; | |
13902 | } | |
13903 | ||
13904 | /* Encode multiply / multiply-accumulate scalar instructions. */ | |
13905 | ||
13906 | static void | |
13907 | neon_mul_mac (struct neon_type_el et, int ubit) | |
13908 | { | |
dcbf9037 JB |
13909 | unsigned scalar; |
13910 | ||
13911 | /* Give a more helpful error message if we have an invalid type. */ | |
13912 | if (et.type == NT_invtype) | |
13913 | return; | |
5f4273c7 | 13914 | |
dcbf9037 | 13915 | scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); |
5287ad62 JB |
13916 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
13917 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
13918 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
13919 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
13920 | inst.instruction |= LOW4 (scalar); | |
13921 | inst.instruction |= HI1 (scalar) << 5; | |
13922 | inst.instruction |= (et.type == NT_float) << 8; | |
13923 | inst.instruction |= neon_logbits (et.size) << 20; | |
13924 | inst.instruction |= (ubit != 0) << 24; | |
13925 | ||
88714cb8 | 13926 | neon_dp_fixup (&inst); |
5287ad62 JB |
13927 | } |
13928 | ||
13929 | static void | |
13930 | do_neon_mac_maybe_scalar (void) | |
13931 | { | |
037e8744 JB |
13932 | if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) |
13933 | return; | |
13934 | ||
13935 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13936 | return; | |
13937 | ||
5287ad62 JB |
13938 | if (inst.operands[2].isscalar) |
13939 | { | |
037e8744 | 13940 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
13941 | struct neon_type_el et = neon_check_type (3, rs, |
13942 | N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); | |
88714cb8 | 13943 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 13944 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
13945 | } |
13946 | else | |
428e3f1f PB |
13947 | { |
13948 | /* The "untyped" case can't happen. Do this to stop the "U" bit being | |
13949 | affected if we specify unsigned args. */ | |
13950 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13951 | } | |
5287ad62 JB |
13952 | } |
13953 | ||
62f3b8c8 PB |
13954 | static void |
13955 | do_neon_fmac (void) | |
13956 | { | |
13957 | if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS) | |
13958 | return; | |
13959 | ||
13960 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13961 | return; | |
13962 | ||
13963 | neon_dyadic_misc (NT_untyped, N_IF_32, 0); | |
13964 | } | |
13965 | ||
5287ad62 JB |
13966 | static void |
13967 | do_neon_tst (void) | |
13968 | { | |
037e8744 | 13969 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
13970 | struct neon_type_el et = neon_check_type (3, rs, |
13971 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
037e8744 | 13972 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
13973 | } |
13974 | ||
13975 | /* VMUL with 3 registers allows the P8 type. The scalar version supports the | |
13976 | same types as the MAC equivalents. The polynomial type for this instruction | |
13977 | is encoded the same as the integer type. */ | |
13978 | ||
13979 | static void | |
13980 | do_neon_mul (void) | |
13981 | { | |
037e8744 JB |
13982 | if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) |
13983 | return; | |
13984 | ||
13985 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
13986 | return; | |
13987 | ||
5287ad62 JB |
13988 | if (inst.operands[2].isscalar) |
13989 | do_neon_mac_maybe_scalar (); | |
13990 | else | |
dcbf9037 | 13991 | neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); |
5287ad62 JB |
13992 | } |
13993 | ||
13994 | static void | |
13995 | do_neon_qdmulh (void) | |
13996 | { | |
13997 | if (inst.operands[2].isscalar) | |
13998 | { | |
037e8744 | 13999 | enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); |
5287ad62 JB |
14000 | struct neon_type_el et = neon_check_type (3, rs, |
14001 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 14002 | NEON_ENCODE (SCALAR, inst); |
037e8744 | 14003 | neon_mul_mac (et, neon_quad (rs)); |
5287ad62 JB |
14004 | } |
14005 | else | |
14006 | { | |
037e8744 | 14007 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14008 | struct neon_type_el et = neon_check_type (3, rs, |
14009 | N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); | |
88714cb8 | 14010 | NEON_ENCODE (INTEGER, inst); |
5287ad62 | 14011 | /* The U bit (rounding) comes from bit mask. */ |
037e8744 | 14012 | neon_three_same (neon_quad (rs), 0, et.size); |
5287ad62 JB |
14013 | } |
14014 | } | |
14015 | ||
14016 | static void | |
14017 | do_neon_fcmp_absolute (void) | |
14018 | { | |
037e8744 | 14019 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 JB |
14020 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
14021 | /* Size field comes from bit mask. */ | |
037e8744 | 14022 | neon_three_same (neon_quad (rs), 1, -1); |
5287ad62 JB |
14023 | } |
14024 | ||
14025 | static void | |
14026 | do_neon_fcmp_absolute_inv (void) | |
14027 | { | |
14028 | neon_exchange_operands (); | |
14029 | do_neon_fcmp_absolute (); | |
14030 | } | |
14031 | ||
14032 | static void | |
14033 | do_neon_step (void) | |
14034 | { | |
037e8744 | 14035 | enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); |
5287ad62 | 14036 | neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); |
037e8744 | 14037 | neon_three_same (neon_quad (rs), 0, -1); |
5287ad62 JB |
14038 | } |
14039 | ||
14040 | static void | |
14041 | do_neon_abs_neg (void) | |
14042 | { | |
037e8744 JB |
14043 | enum neon_shape rs; |
14044 | struct neon_type_el et; | |
5f4273c7 | 14045 | |
037e8744 JB |
14046 | if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) |
14047 | return; | |
14048 | ||
14049 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14050 | return; | |
14051 | ||
14052 | rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); | |
14053 | et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); | |
5f4273c7 | 14054 | |
5287ad62 JB |
14055 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14056 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14057 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14058 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14059 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14060 | inst.instruction |= (et.type == NT_float) << 10; |
14061 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14062 | |
88714cb8 | 14063 | neon_dp_fixup (&inst); |
5287ad62 JB |
14064 | } |
14065 | ||
14066 | static void | |
14067 | do_neon_sli (void) | |
14068 | { | |
037e8744 | 14069 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14070 | struct neon_type_el et = neon_check_type (2, rs, |
14071 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14072 | int imm = inst.operands[2].imm; | |
14073 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
14074 | _("immediate out of range for insert")); | |
037e8744 | 14075 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14076 | } |
14077 | ||
14078 | static void | |
14079 | do_neon_sri (void) | |
14080 | { | |
037e8744 | 14081 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14082 | struct neon_type_el et = neon_check_type (2, rs, |
14083 | N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14084 | int imm = inst.operands[2].imm; | |
14085 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14086 | _("immediate out of range for insert")); | |
037e8744 | 14087 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); |
5287ad62 JB |
14088 | } |
14089 | ||
14090 | static void | |
14091 | do_neon_qshlu_imm (void) | |
14092 | { | |
037e8744 | 14093 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
14094 | struct neon_type_el et = neon_check_type (2, rs, |
14095 | N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); | |
14096 | int imm = inst.operands[2].imm; | |
14097 | constraint (imm < 0 || (unsigned)imm >= et.size, | |
14098 | _("immediate out of range for shift")); | |
14099 | /* Only encodes the 'U present' variant of the instruction. | |
14100 | In this case, signed types have OP (bit 8) set to 0. | |
14101 | Unsigned types have OP set to 1. */ | |
14102 | inst.instruction |= (et.type == NT_unsigned) << 8; | |
14103 | /* The rest of the bits are the same as other immediate shifts. */ | |
037e8744 | 14104 | neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); |
5287ad62 JB |
14105 | } |
14106 | ||
14107 | static void | |
14108 | do_neon_qmovn (void) | |
14109 | { | |
14110 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14111 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14112 | /* Saturating move where operands can be signed or unsigned, and the | |
14113 | destination has the same signedness. */ | |
88714cb8 | 14114 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14115 | if (et.type == NT_unsigned) |
14116 | inst.instruction |= 0xc0; | |
14117 | else | |
14118 | inst.instruction |= 0x80; | |
14119 | neon_two_same (0, 1, et.size / 2); | |
14120 | } | |
14121 | ||
14122 | static void | |
14123 | do_neon_qmovun (void) | |
14124 | { | |
14125 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14126 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14127 | /* Saturating move with unsigned results. Operands must be signed. */ | |
88714cb8 | 14128 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14129 | neon_two_same (0, 1, et.size / 2); |
14130 | } | |
14131 | ||
14132 | static void | |
14133 | do_neon_rshift_sat_narrow (void) | |
14134 | { | |
14135 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14136 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14137 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14138 | N_EQK | N_HLF, N_SU_16_64 | N_KEY); | |
14139 | int imm = inst.operands[2].imm; | |
14140 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14141 | right. */ | |
14142 | et.size /= 2; | |
5f4273c7 | 14143 | |
5287ad62 JB |
14144 | /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for |
14145 | VQMOVN.I<size> <Dd>, <Qm>. */ | |
14146 | if (imm == 0) | |
14147 | { | |
14148 | inst.operands[2].present = 0; | |
14149 | inst.instruction = N_MNEM_vqmovn; | |
14150 | do_neon_qmovn (); | |
14151 | return; | |
14152 | } | |
5f4273c7 | 14153 | |
5287ad62 JB |
14154 | constraint (imm < 1 || (unsigned)imm > et.size, |
14155 | _("immediate out of range")); | |
14156 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); | |
14157 | } | |
14158 | ||
14159 | static void | |
14160 | do_neon_rshift_sat_narrow_u (void) | |
14161 | { | |
14162 | /* FIXME: Types for narrowing. If operands are signed, results can be signed | |
14163 | or unsigned. If operands are unsigned, results must also be unsigned. */ | |
14164 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14165 | N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); | |
14166 | int imm = inst.operands[2].imm; | |
14167 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14168 | right. */ | |
14169 | et.size /= 2; | |
14170 | ||
14171 | /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for | |
14172 | VQMOVUN.I<size> <Dd>, <Qm>. */ | |
14173 | if (imm == 0) | |
14174 | { | |
14175 | inst.operands[2].present = 0; | |
14176 | inst.instruction = N_MNEM_vqmovun; | |
14177 | do_neon_qmovun (); | |
14178 | return; | |
14179 | } | |
14180 | ||
14181 | constraint (imm < 1 || (unsigned)imm > et.size, | |
14182 | _("immediate out of range")); | |
14183 | /* FIXME: The manual is kind of unclear about what value U should have in | |
14184 | VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it | |
14185 | must be 1. */ | |
14186 | neon_imm_shift (TRUE, 1, 0, et, et.size - imm); | |
14187 | } | |
14188 | ||
14189 | static void | |
14190 | do_neon_movn (void) | |
14191 | { | |
14192 | struct neon_type_el et = neon_check_type (2, NS_DQ, | |
14193 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
88714cb8 | 14194 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14195 | neon_two_same (0, 1, et.size / 2); |
14196 | } | |
14197 | ||
14198 | static void | |
14199 | do_neon_rshift_narrow (void) | |
14200 | { | |
14201 | struct neon_type_el et = neon_check_type (2, NS_DQI, | |
14202 | N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); | |
14203 | int imm = inst.operands[2].imm; | |
14204 | /* This gets the bounds check, size encoding and immediate bits calculation | |
14205 | right. */ | |
14206 | et.size /= 2; | |
5f4273c7 | 14207 | |
5287ad62 JB |
14208 | /* If immediate is zero then we are a pseudo-instruction for |
14209 | VMOVN.I<size> <Dd>, <Qm> */ | |
14210 | if (imm == 0) | |
14211 | { | |
14212 | inst.operands[2].present = 0; | |
14213 | inst.instruction = N_MNEM_vmovn; | |
14214 | do_neon_movn (); | |
14215 | return; | |
14216 | } | |
5f4273c7 | 14217 | |
5287ad62 JB |
14218 | constraint (imm < 1 || (unsigned)imm > et.size, |
14219 | _("immediate out of range for narrowing operation")); | |
14220 | neon_imm_shift (FALSE, 0, 0, et, et.size - imm); | |
14221 | } | |
14222 | ||
14223 | static void | |
14224 | do_neon_shll (void) | |
14225 | { | |
14226 | /* FIXME: Type checking when lengthening. */ | |
14227 | struct neon_type_el et = neon_check_type (2, NS_QDI, | |
14228 | N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); | |
14229 | unsigned imm = inst.operands[2].imm; | |
14230 | ||
14231 | if (imm == et.size) | |
14232 | { | |
14233 | /* Maximum shift variant. */ | |
88714cb8 | 14234 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14235 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14236 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14237 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14238 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14239 | inst.instruction |= neon_logbits (et.size) << 18; | |
5f4273c7 | 14240 | |
88714cb8 | 14241 | neon_dp_fixup (&inst); |
5287ad62 JB |
14242 | } |
14243 | else | |
14244 | { | |
14245 | /* A more-specific type check for non-max versions. */ | |
14246 | et = neon_check_type (2, NS_QDI, | |
14247 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
88714cb8 | 14248 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14249 | neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); |
14250 | } | |
14251 | } | |
14252 | ||
037e8744 | 14253 | /* Check the various types for the VCVT instruction, and return which version |
5287ad62 JB |
14254 | the current instruction is. */ |
14255 | ||
14256 | static int | |
14257 | neon_cvt_flavour (enum neon_shape rs) | |
14258 | { | |
037e8744 JB |
14259 | #define CVT_VAR(C,X,Y) \ |
14260 | et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ | |
14261 | if (et.type != NT_invtype) \ | |
14262 | { \ | |
14263 | inst.error = NULL; \ | |
14264 | return (C); \ | |
5287ad62 JB |
14265 | } |
14266 | struct neon_type_el et; | |
037e8744 JB |
14267 | unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF |
14268 | || rs == NS_FF) ? N_VFP : 0; | |
14269 | /* The instruction versions which take an immediate take one register | |
14270 | argument, which is extended to the width of the full register. Thus the | |
14271 | "source" and "destination" registers must have the same width. Hack that | |
14272 | here by making the size equal to the key (wider, in this case) operand. */ | |
14273 | unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; | |
5f4273c7 | 14274 | |
5287ad62 JB |
14275 | CVT_VAR (0, N_S32, N_F32); |
14276 | CVT_VAR (1, N_U32, N_F32); | |
14277 | CVT_VAR (2, N_F32, N_S32); | |
14278 | CVT_VAR (3, N_F32, N_U32); | |
8e79c3df CM |
14279 | /* Half-precision conversions. */ |
14280 | CVT_VAR (4, N_F32, N_F16); | |
14281 | CVT_VAR (5, N_F16, N_F32); | |
5f4273c7 | 14282 | |
037e8744 | 14283 | whole_reg = N_VFP; |
5f4273c7 | 14284 | |
037e8744 | 14285 | /* VFP instructions. */ |
8e79c3df CM |
14286 | CVT_VAR (6, N_F32, N_F64); |
14287 | CVT_VAR (7, N_F64, N_F32); | |
14288 | CVT_VAR (8, N_S32, N_F64 | key); | |
14289 | CVT_VAR (9, N_U32, N_F64 | key); | |
14290 | CVT_VAR (10, N_F64 | key, N_S32); | |
14291 | CVT_VAR (11, N_F64 | key, N_U32); | |
037e8744 | 14292 | /* VFP instructions with bitshift. */ |
8e79c3df CM |
14293 | CVT_VAR (12, N_F32 | key, N_S16); |
14294 | CVT_VAR (13, N_F32 | key, N_U16); | |
14295 | CVT_VAR (14, N_F64 | key, N_S16); | |
14296 | CVT_VAR (15, N_F64 | key, N_U16); | |
14297 | CVT_VAR (16, N_S16, N_F32 | key); | |
14298 | CVT_VAR (17, N_U16, N_F32 | key); | |
14299 | CVT_VAR (18, N_S16, N_F64 | key); | |
14300 | CVT_VAR (19, N_U16, N_F64 | key); | |
5f4273c7 | 14301 | |
5287ad62 JB |
14302 | return -1; |
14303 | #undef CVT_VAR | |
14304 | } | |
14305 | ||
037e8744 JB |
14306 | /* Neon-syntax VFP conversions. */ |
14307 | ||
5287ad62 | 14308 | static void |
037e8744 | 14309 | do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
5287ad62 | 14310 | { |
037e8744 | 14311 | const char *opname = 0; |
5f4273c7 | 14312 | |
037e8744 | 14313 | if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) |
5287ad62 | 14314 | { |
037e8744 JB |
14315 | /* Conversions with immediate bitshift. */ |
14316 | const char *enc[] = | |
14317 | { | |
14318 | "ftosls", | |
14319 | "ftouls", | |
14320 | "fsltos", | |
14321 | "fultos", | |
14322 | NULL, | |
14323 | NULL, | |
8e79c3df CM |
14324 | NULL, |
14325 | NULL, | |
037e8744 JB |
14326 | "ftosld", |
14327 | "ftould", | |
14328 | "fsltod", | |
14329 | "fultod", | |
14330 | "fshtos", | |
14331 | "fuhtos", | |
14332 | "fshtod", | |
14333 | "fuhtod", | |
14334 | "ftoshs", | |
14335 | "ftouhs", | |
14336 | "ftoshd", | |
14337 | "ftouhd" | |
14338 | }; | |
14339 | ||
14340 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
14341 | { | |
14342 | opname = enc[flavour]; | |
14343 | constraint (inst.operands[0].reg != inst.operands[1].reg, | |
14344 | _("operands 0 and 1 must be the same register")); | |
14345 | inst.operands[1] = inst.operands[2]; | |
14346 | memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); | |
14347 | } | |
5287ad62 JB |
14348 | } |
14349 | else | |
14350 | { | |
037e8744 JB |
14351 | /* Conversions without bitshift. */ |
14352 | const char *enc[] = | |
14353 | { | |
14354 | "ftosis", | |
14355 | "ftouis", | |
14356 | "fsitos", | |
14357 | "fuitos", | |
8e79c3df CM |
14358 | "NULL", |
14359 | "NULL", | |
037e8744 JB |
14360 | "fcvtsd", |
14361 | "fcvtds", | |
14362 | "ftosid", | |
14363 | "ftouid", | |
14364 | "fsitod", | |
14365 | "fuitod" | |
14366 | }; | |
14367 | ||
14368 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) | |
14369 | opname = enc[flavour]; | |
14370 | } | |
14371 | ||
14372 | if (opname) | |
14373 | do_vfp_nsyn_opcode (opname); | |
14374 | } | |
14375 | ||
14376 | static void | |
14377 | do_vfp_nsyn_cvtz (void) | |
14378 | { | |
14379 | enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); | |
14380 | int flavour = neon_cvt_flavour (rs); | |
14381 | const char *enc[] = | |
14382 | { | |
14383 | "ftosizs", | |
14384 | "ftouizs", | |
14385 | NULL, | |
14386 | NULL, | |
14387 | NULL, | |
14388 | NULL, | |
8e79c3df CM |
14389 | NULL, |
14390 | NULL, | |
037e8744 JB |
14391 | "ftosizd", |
14392 | "ftouizd" | |
14393 | }; | |
14394 | ||
14395 | if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) | |
14396 | do_vfp_nsyn_opcode (enc[flavour]); | |
14397 | } | |
f31fef98 | 14398 | |
037e8744 | 14399 | static void |
e3e535bc | 14400 | do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED) |
037e8744 JB |
14401 | { |
14402 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, | |
8e79c3df | 14403 | NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
037e8744 JB |
14404 | int flavour = neon_cvt_flavour (rs); |
14405 | ||
e3e535bc NC |
14406 | /* PR11109: Handle round-to-zero for VCVT conversions. */ |
14407 | if (round_to_zero | |
14408 | && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2) | |
14409 | && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9) | |
14410 | && (rs == NS_FD || rs == NS_FF)) | |
14411 | { | |
14412 | do_vfp_nsyn_cvtz (); | |
14413 | return; | |
14414 | } | |
14415 | ||
037e8744 | 14416 | /* VFP rather than Neon conversions. */ |
8e79c3df | 14417 | if (flavour >= 6) |
037e8744 JB |
14418 | { |
14419 | do_vfp_nsyn_cvt (rs, flavour); | |
14420 | return; | |
14421 | } | |
14422 | ||
14423 | switch (rs) | |
14424 | { | |
14425 | case NS_DDI: | |
14426 | case NS_QQI: | |
14427 | { | |
35997600 NC |
14428 | unsigned immbits; |
14429 | unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; | |
14430 | ||
037e8744 JB |
14431 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) |
14432 | return; | |
14433 | ||
14434 | /* Fixed-point conversion with #0 immediate is encoded as an | |
14435 | integer conversion. */ | |
14436 | if (inst.operands[2].present && inst.operands[2].imm == 0) | |
14437 | goto int_encode; | |
35997600 | 14438 | immbits = 32 - inst.operands[2].imm; |
88714cb8 | 14439 | NEON_ENCODE (IMMED, inst); |
037e8744 JB |
14440 | if (flavour != -1) |
14441 | inst.instruction |= enctab[flavour]; | |
14442 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14443 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14444 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14445 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14446 | inst.instruction |= neon_quad (rs) << 6; | |
14447 | inst.instruction |= 1 << 21; | |
14448 | inst.instruction |= immbits << 16; | |
14449 | ||
88714cb8 | 14450 | neon_dp_fixup (&inst); |
037e8744 JB |
14451 | } |
14452 | break; | |
14453 | ||
14454 | case NS_DD: | |
14455 | case NS_QQ: | |
14456 | int_encode: | |
14457 | { | |
14458 | unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; | |
14459 | ||
88714cb8 | 14460 | NEON_ENCODE (INTEGER, inst); |
037e8744 JB |
14461 | |
14462 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14463 | return; | |
14464 | ||
14465 | if (flavour != -1) | |
14466 | inst.instruction |= enctab[flavour]; | |
14467 | ||
14468 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14469 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14470 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14471 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14472 | inst.instruction |= neon_quad (rs) << 6; | |
14473 | inst.instruction |= 2 << 18; | |
14474 | ||
88714cb8 | 14475 | neon_dp_fixup (&inst); |
037e8744 JB |
14476 | } |
14477 | break; | |
14478 | ||
8e79c3df CM |
14479 | /* Half-precision conversions for Advanced SIMD -- neon. */ |
14480 | case NS_QD: | |
14481 | case NS_DQ: | |
14482 | ||
14483 | if ((rs == NS_DQ) | |
14484 | && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) | |
14485 | { | |
14486 | as_bad (_("operand size must match register width")); | |
14487 | break; | |
14488 | } | |
14489 | ||
14490 | if ((rs == NS_QD) | |
14491 | && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) | |
14492 | { | |
14493 | as_bad (_("operand size must match register width")); | |
14494 | break; | |
14495 | } | |
14496 | ||
14497 | if (rs == NS_DQ) | |
14498 | inst.instruction = 0x3b60600; | |
14499 | else | |
14500 | inst.instruction = 0x3b60700; | |
14501 | ||
14502 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14503 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14504 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14505 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
88714cb8 | 14506 | neon_dp_fixup (&inst); |
8e79c3df CM |
14507 | break; |
14508 | ||
037e8744 JB |
14509 | default: |
14510 | /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ | |
14511 | do_vfp_nsyn_cvt (rs, flavour); | |
5287ad62 | 14512 | } |
5287ad62 JB |
14513 | } |
14514 | ||
e3e535bc NC |
14515 | static void |
14516 | do_neon_cvtr (void) | |
14517 | { | |
14518 | do_neon_cvt_1 (FALSE); | |
14519 | } | |
14520 | ||
14521 | static void | |
14522 | do_neon_cvt (void) | |
14523 | { | |
14524 | do_neon_cvt_1 (TRUE); | |
14525 | } | |
14526 | ||
8e79c3df CM |
14527 | static void |
14528 | do_neon_cvtb (void) | |
14529 | { | |
14530 | inst.instruction = 0xeb20a40; | |
14531 | ||
14532 | /* The sizes are attached to the mnemonic. */ | |
14533 | if (inst.vectype.el[0].type != NT_invtype | |
14534 | && inst.vectype.el[0].size == 16) | |
14535 | inst.instruction |= 0x00010000; | |
14536 | ||
14537 | /* Programmer's syntax: the sizes are attached to the operands. */ | |
14538 | else if (inst.operands[0].vectype.type != NT_invtype | |
14539 | && inst.operands[0].vectype.size == 16) | |
14540 | inst.instruction |= 0x00010000; | |
14541 | ||
14542 | encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); | |
14543 | encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); | |
14544 | do_vfp_cond_or_thumb (); | |
14545 | } | |
14546 | ||
14547 | ||
14548 | static void | |
14549 | do_neon_cvtt (void) | |
14550 | { | |
14551 | do_neon_cvtb (); | |
14552 | inst.instruction |= 0x80; | |
14553 | } | |
14554 | ||
5287ad62 JB |
14555 | static void |
14556 | neon_move_immediate (void) | |
14557 | { | |
037e8744 JB |
14558 | enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); |
14559 | struct neon_type_el et = neon_check_type (2, rs, | |
14560 | N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); | |
5287ad62 | 14561 | unsigned immlo, immhi = 0, immbits; |
c96612cc | 14562 | int op, cmode, float_p; |
5287ad62 | 14563 | |
037e8744 JB |
14564 | constraint (et.type == NT_invtype, |
14565 | _("operand size must be specified for immediate VMOV")); | |
14566 | ||
5287ad62 JB |
14567 | /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ |
14568 | op = (inst.instruction & (1 << 5)) != 0; | |
14569 | ||
14570 | immlo = inst.operands[1].imm; | |
14571 | if (inst.operands[1].regisimm) | |
14572 | immhi = inst.operands[1].reg; | |
14573 | ||
14574 | constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, | |
14575 | _("immediate has bits set outside the operand size")); | |
14576 | ||
c96612cc JB |
14577 | float_p = inst.operands[1].immisfloat; |
14578 | ||
14579 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, | |
136da414 | 14580 | et.size, et.type)) == FAIL) |
5287ad62 JB |
14581 | { |
14582 | /* Invert relevant bits only. */ | |
14583 | neon_invert_size (&immlo, &immhi, et.size); | |
14584 | /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable | |
14585 | with one or the other; those cases are caught by | |
14586 | neon_cmode_for_move_imm. */ | |
14587 | op = !op; | |
c96612cc JB |
14588 | if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, |
14589 | &op, et.size, et.type)) == FAIL) | |
5287ad62 | 14590 | { |
dcbf9037 | 14591 | first_error (_("immediate out of range")); |
5287ad62 JB |
14592 | return; |
14593 | } | |
14594 | } | |
14595 | ||
14596 | inst.instruction &= ~(1 << 5); | |
14597 | inst.instruction |= op << 5; | |
14598 | ||
14599 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14600 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
037e8744 | 14601 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14602 | inst.instruction |= cmode << 8; |
14603 | ||
14604 | neon_write_immbits (immbits); | |
14605 | } | |
14606 | ||
14607 | static void | |
14608 | do_neon_mvn (void) | |
14609 | { | |
14610 | if (inst.operands[1].isreg) | |
14611 | { | |
037e8744 | 14612 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5f4273c7 | 14613 | |
88714cb8 | 14614 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14615 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14616 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14617 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14618 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
037e8744 | 14619 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14620 | } |
14621 | else | |
14622 | { | |
88714cb8 | 14623 | NEON_ENCODE (IMMED, inst); |
5287ad62 JB |
14624 | neon_move_immediate (); |
14625 | } | |
14626 | ||
88714cb8 | 14627 | neon_dp_fixup (&inst); |
5287ad62 JB |
14628 | } |
14629 | ||
14630 | /* Encode instructions of form: | |
14631 | ||
14632 | |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| | |
5f4273c7 | 14633 | | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */ |
5287ad62 JB |
14634 | |
14635 | static void | |
14636 | neon_mixed_length (struct neon_type_el et, unsigned size) | |
14637 | { | |
14638 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14639 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14640 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14641 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14642 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14643 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
14644 | inst.instruction |= (et.type == NT_unsigned) << 24; | |
14645 | inst.instruction |= neon_logbits (size) << 20; | |
5f4273c7 | 14646 | |
88714cb8 | 14647 | neon_dp_fixup (&inst); |
5287ad62 JB |
14648 | } |
14649 | ||
14650 | static void | |
14651 | do_neon_dyadic_long (void) | |
14652 | { | |
14653 | /* FIXME: Type checking for lengthening op. */ | |
14654 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14655 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14656 | neon_mixed_length (et, et.size); | |
14657 | } | |
14658 | ||
14659 | static void | |
14660 | do_neon_abal (void) | |
14661 | { | |
14662 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14663 | N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); | |
14664 | neon_mixed_length (et, et.size); | |
14665 | } | |
14666 | ||
14667 | static void | |
14668 | neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) | |
14669 | { | |
14670 | if (inst.operands[2].isscalar) | |
14671 | { | |
dcbf9037 JB |
14672 | struct neon_type_el et = neon_check_type (3, NS_QDS, |
14673 | N_EQK | N_DBL, N_EQK, regtypes | N_KEY); | |
88714cb8 | 14674 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14675 | neon_mul_mac (et, et.type == NT_unsigned); |
14676 | } | |
14677 | else | |
14678 | { | |
14679 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14680 | N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); | |
88714cb8 | 14681 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14682 | neon_mixed_length (et, et.size); |
14683 | } | |
14684 | } | |
14685 | ||
14686 | static void | |
14687 | do_neon_mac_maybe_scalar_long (void) | |
14688 | { | |
14689 | neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); | |
14690 | } | |
14691 | ||
14692 | static void | |
14693 | do_neon_dyadic_wide (void) | |
14694 | { | |
14695 | struct neon_type_el et = neon_check_type (3, NS_QQD, | |
14696 | N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); | |
14697 | neon_mixed_length (et, et.size); | |
14698 | } | |
14699 | ||
14700 | static void | |
14701 | do_neon_dyadic_narrow (void) | |
14702 | { | |
14703 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14704 | N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); | |
428e3f1f PB |
14705 | /* Operand sign is unimportant, and the U bit is part of the opcode, |
14706 | so force the operand type to integer. */ | |
14707 | et.type = NT_integer; | |
5287ad62 JB |
14708 | neon_mixed_length (et, et.size / 2); |
14709 | } | |
14710 | ||
14711 | static void | |
14712 | do_neon_mul_sat_scalar_long (void) | |
14713 | { | |
14714 | neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); | |
14715 | } | |
14716 | ||
14717 | static void | |
14718 | do_neon_vmull (void) | |
14719 | { | |
14720 | if (inst.operands[2].isscalar) | |
14721 | do_neon_mac_maybe_scalar_long (); | |
14722 | else | |
14723 | { | |
14724 | struct neon_type_el et = neon_check_type (3, NS_QDD, | |
14725 | N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); | |
14726 | if (et.type == NT_poly) | |
88714cb8 | 14727 | NEON_ENCODE (POLY, inst); |
5287ad62 | 14728 | else |
88714cb8 | 14729 | NEON_ENCODE (INTEGER, inst); |
5287ad62 JB |
14730 | /* For polynomial encoding, size field must be 0b00 and the U bit must be |
14731 | zero. Should be OK as-is. */ | |
14732 | neon_mixed_length (et, et.size); | |
14733 | } | |
14734 | } | |
14735 | ||
14736 | static void | |
14737 | do_neon_ext (void) | |
14738 | { | |
037e8744 | 14739 | enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); |
5287ad62 JB |
14740 | struct neon_type_el et = neon_check_type (3, rs, |
14741 | N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); | |
14742 | unsigned imm = (inst.operands[3].imm * et.size) / 8; | |
35997600 NC |
14743 | |
14744 | constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8), | |
14745 | _("shift out of range")); | |
5287ad62 JB |
14746 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14747 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14748 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14749 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14750 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
14751 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
037e8744 | 14752 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 | 14753 | inst.instruction |= imm << 8; |
5f4273c7 | 14754 | |
88714cb8 | 14755 | neon_dp_fixup (&inst); |
5287ad62 JB |
14756 | } |
14757 | ||
14758 | static void | |
14759 | do_neon_rev (void) | |
14760 | { | |
037e8744 | 14761 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
14762 | struct neon_type_el et = neon_check_type (2, rs, |
14763 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
14764 | unsigned op = (inst.instruction >> 7) & 3; | |
14765 | /* N (width of reversed regions) is encoded as part of the bitmask. We | |
14766 | extract it here to check the elements to be reversed are smaller. | |
14767 | Otherwise we'd get a reserved instruction. */ | |
14768 | unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; | |
9c2799c2 | 14769 | gas_assert (elsize != 0); |
5287ad62 JB |
14770 | constraint (et.size >= elsize, |
14771 | _("elements must be smaller than reversal region")); | |
037e8744 | 14772 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
14773 | } |
14774 | ||
14775 | static void | |
14776 | do_neon_dup (void) | |
14777 | { | |
14778 | if (inst.operands[1].isscalar) | |
14779 | { | |
037e8744 | 14780 | enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); |
dcbf9037 JB |
14781 | struct neon_type_el et = neon_check_type (2, rs, |
14782 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
5287ad62 | 14783 | unsigned sizebits = et.size >> 3; |
dcbf9037 | 14784 | unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); |
5287ad62 | 14785 | int logsize = neon_logbits (et.size); |
dcbf9037 | 14786 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; |
037e8744 JB |
14787 | |
14788 | if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) | |
14789 | return; | |
14790 | ||
88714cb8 | 14791 | NEON_ENCODE (SCALAR, inst); |
5287ad62 JB |
14792 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
14793 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14794 | inst.instruction |= LOW4 (dm); | |
14795 | inst.instruction |= HI1 (dm) << 5; | |
037e8744 | 14796 | inst.instruction |= neon_quad (rs) << 6; |
5287ad62 JB |
14797 | inst.instruction |= x << 17; |
14798 | inst.instruction |= sizebits << 16; | |
5f4273c7 | 14799 | |
88714cb8 | 14800 | neon_dp_fixup (&inst); |
5287ad62 JB |
14801 | } |
14802 | else | |
14803 | { | |
037e8744 JB |
14804 | enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); |
14805 | struct neon_type_el et = neon_check_type (2, rs, | |
14806 | N_8 | N_16 | N_32 | N_KEY, N_EQK); | |
5287ad62 | 14807 | /* Duplicate ARM register to lanes of vector. */ |
88714cb8 | 14808 | NEON_ENCODE (ARMREG, inst); |
5287ad62 JB |
14809 | switch (et.size) |
14810 | { | |
14811 | case 8: inst.instruction |= 0x400000; break; | |
14812 | case 16: inst.instruction |= 0x000020; break; | |
14813 | case 32: inst.instruction |= 0x000000; break; | |
14814 | default: break; | |
14815 | } | |
14816 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
14817 | inst.instruction |= LOW4 (inst.operands[0].reg) << 16; | |
14818 | inst.instruction |= HI1 (inst.operands[0].reg) << 7; | |
037e8744 | 14819 | inst.instruction |= neon_quad (rs) << 21; |
5287ad62 JB |
14820 | /* The encoding for this instruction is identical for the ARM and Thumb |
14821 | variants, except for the condition field. */ | |
037e8744 | 14822 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
14823 | } |
14824 | } | |
14825 | ||
14826 | /* VMOV has particularly many variations. It can be one of: | |
14827 | 0. VMOV<c><q> <Qd>, <Qm> | |
14828 | 1. VMOV<c><q> <Dd>, <Dm> | |
14829 | (Register operations, which are VORR with Rm = Rn.) | |
14830 | 2. VMOV<c><q>.<dt> <Qd>, #<imm> | |
14831 | 3. VMOV<c><q>.<dt> <Dd>, #<imm> | |
14832 | (Immediate loads.) | |
14833 | 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> | |
14834 | (ARM register to scalar.) | |
14835 | 5. VMOV<c><q> <Dm>, <Rd>, <Rn> | |
14836 | (Two ARM registers to vector.) | |
14837 | 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> | |
14838 | (Scalar to ARM register.) | |
14839 | 7. VMOV<c><q> <Rd>, <Rn>, <Dm> | |
14840 | (Vector to two ARM registers.) | |
037e8744 JB |
14841 | 8. VMOV.F32 <Sd>, <Sm> |
14842 | 9. VMOV.F64 <Dd>, <Dm> | |
14843 | (VFP register moves.) | |
14844 | 10. VMOV.F32 <Sd>, #imm | |
14845 | 11. VMOV.F64 <Dd>, #imm | |
14846 | (VFP float immediate load.) | |
14847 | 12. VMOV <Rd>, <Sm> | |
14848 | (VFP single to ARM reg.) | |
14849 | 13. VMOV <Sd>, <Rm> | |
14850 | (ARM reg to VFP single.) | |
14851 | 14. VMOV <Rd>, <Re>, <Sn>, <Sm> | |
14852 | (Two ARM regs to two VFP singles.) | |
14853 | 15. VMOV <Sd>, <Se>, <Rn>, <Rm> | |
14854 | (Two VFP singles to two ARM regs.) | |
5f4273c7 | 14855 | |
037e8744 JB |
14856 | These cases can be disambiguated using neon_select_shape, except cases 1/9 |
14857 | and 3/11 which depend on the operand type too. | |
5f4273c7 | 14858 | |
5287ad62 | 14859 | All the encoded bits are hardcoded by this function. |
5f4273c7 | 14860 | |
b7fc2769 JB |
14861 | Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). |
14862 | Cases 5, 7 may be used with VFPv2 and above. | |
5f4273c7 | 14863 | |
5287ad62 | 14864 | FIXME: Some of the checking may be a bit sloppy (in a couple of cases you |
5f4273c7 | 14865 | can specify a type where it doesn't make sense to, and is ignored). */ |
5287ad62 JB |
14866 | |
14867 | static void | |
14868 | do_neon_mov (void) | |
14869 | { | |
037e8744 JB |
14870 | enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, |
14871 | NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, | |
14872 | NS_NULL); | |
14873 | struct neon_type_el et; | |
14874 | const char *ldconst = 0; | |
5287ad62 | 14875 | |
037e8744 | 14876 | switch (rs) |
5287ad62 | 14877 | { |
037e8744 JB |
14878 | case NS_DD: /* case 1/9. */ |
14879 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14880 | /* It is not an error here if no type is given. */ | |
14881 | inst.error = NULL; | |
14882 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14883 | { |
037e8744 JB |
14884 | do_vfp_nsyn_opcode ("fcpyd"); |
14885 | break; | |
5287ad62 | 14886 | } |
037e8744 | 14887 | /* fall through. */ |
5287ad62 | 14888 | |
037e8744 JB |
14889 | case NS_QQ: /* case 0/1. */ |
14890 | { | |
14891 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14892 | return; | |
14893 | /* The architecture manual I have doesn't explicitly state which | |
14894 | value the U bit should have for register->register moves, but | |
14895 | the equivalent VORR instruction has U = 0, so do that. */ | |
14896 | inst.instruction = 0x0200110; | |
14897 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
14898 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
14899 | inst.instruction |= LOW4 (inst.operands[1].reg); | |
14900 | inst.instruction |= HI1 (inst.operands[1].reg) << 5; | |
14901 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
14902 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
14903 | inst.instruction |= neon_quad (rs) << 6; | |
14904 | ||
88714cb8 | 14905 | neon_dp_fixup (&inst); |
037e8744 JB |
14906 | } |
14907 | break; | |
5f4273c7 | 14908 | |
037e8744 JB |
14909 | case NS_DI: /* case 3/11. */ |
14910 | et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); | |
14911 | inst.error = NULL; | |
14912 | if (et.type == NT_float && et.size == 64) | |
5287ad62 | 14913 | { |
037e8744 JB |
14914 | /* case 11 (fconstd). */ |
14915 | ldconst = "fconstd"; | |
14916 | goto encode_fconstd; | |
5287ad62 | 14917 | } |
037e8744 JB |
14918 | /* fall through. */ |
14919 | ||
14920 | case NS_QI: /* case 2/3. */ | |
14921 | if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) | |
14922 | return; | |
14923 | inst.instruction = 0x0800010; | |
14924 | neon_move_immediate (); | |
88714cb8 | 14925 | neon_dp_fixup (&inst); |
5287ad62 | 14926 | break; |
5f4273c7 | 14927 | |
037e8744 JB |
14928 | case NS_SR: /* case 4. */ |
14929 | { | |
14930 | unsigned bcdebits = 0; | |
91d6fa6a | 14931 | int logsize; |
037e8744 JB |
14932 | unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); |
14933 | unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); | |
14934 | ||
91d6fa6a NC |
14935 | et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK); |
14936 | logsize = neon_logbits (et.size); | |
14937 | ||
037e8744 JB |
14938 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14939 | _(BAD_FPU)); | |
14940 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14941 | && et.size != 32, _(BAD_FPU)); | |
14942 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14943 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14944 | ||
14945 | switch (et.size) | |
14946 | { | |
14947 | case 8: bcdebits = 0x8; break; | |
14948 | case 16: bcdebits = 0x1; break; | |
14949 | case 32: bcdebits = 0x0; break; | |
14950 | default: ; | |
14951 | } | |
14952 | ||
14953 | bcdebits |= x << logsize; | |
14954 | ||
14955 | inst.instruction = 0xe000b10; | |
14956 | do_vfp_cond_or_thumb (); | |
14957 | inst.instruction |= LOW4 (dn) << 16; | |
14958 | inst.instruction |= HI1 (dn) << 7; | |
14959 | inst.instruction |= inst.operands[1].reg << 12; | |
14960 | inst.instruction |= (bcdebits & 3) << 5; | |
14961 | inst.instruction |= (bcdebits >> 2) << 21; | |
14962 | } | |
14963 | break; | |
5f4273c7 | 14964 | |
037e8744 | 14965 | case NS_DRR: /* case 5 (fmdrr). */ |
b7fc2769 | 14966 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), |
037e8744 | 14967 | _(BAD_FPU)); |
b7fc2769 | 14968 | |
037e8744 JB |
14969 | inst.instruction = 0xc400b10; |
14970 | do_vfp_cond_or_thumb (); | |
14971 | inst.instruction |= LOW4 (inst.operands[0].reg); | |
14972 | inst.instruction |= HI1 (inst.operands[0].reg) << 5; | |
14973 | inst.instruction |= inst.operands[1].reg << 12; | |
14974 | inst.instruction |= inst.operands[2].reg << 16; | |
14975 | break; | |
5f4273c7 | 14976 | |
037e8744 JB |
14977 | case NS_RS: /* case 6. */ |
14978 | { | |
91d6fa6a | 14979 | unsigned logsize; |
037e8744 JB |
14980 | unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); |
14981 | unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); | |
14982 | unsigned abcdebits = 0; | |
14983 | ||
91d6fa6a NC |
14984 | et = neon_check_type (2, NS_NULL, |
14985 | N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); | |
14986 | logsize = neon_logbits (et.size); | |
14987 | ||
037e8744 JB |
14988 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), |
14989 | _(BAD_FPU)); | |
14990 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) | |
14991 | && et.size != 32, _(BAD_FPU)); | |
14992 | constraint (et.type == NT_invtype, _("bad type for scalar")); | |
14993 | constraint (x >= 64 / et.size, _("scalar index out of range")); | |
14994 | ||
14995 | switch (et.size) | |
14996 | { | |
14997 | case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; | |
14998 | case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; | |
14999 | case 32: abcdebits = 0x00; break; | |
15000 | default: ; | |
15001 | } | |
15002 | ||
15003 | abcdebits |= x << logsize; | |
15004 | inst.instruction = 0xe100b10; | |
15005 | do_vfp_cond_or_thumb (); | |
15006 | inst.instruction |= LOW4 (dn) << 16; | |
15007 | inst.instruction |= HI1 (dn) << 7; | |
15008 | inst.instruction |= inst.operands[0].reg << 12; | |
15009 | inst.instruction |= (abcdebits & 3) << 5; | |
15010 | inst.instruction |= (abcdebits >> 2) << 21; | |
15011 | } | |
15012 | break; | |
5f4273c7 | 15013 | |
037e8744 JB |
15014 | case NS_RRD: /* case 7 (fmrrd). */ |
15015 | constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), | |
15016 | _(BAD_FPU)); | |
15017 | ||
15018 | inst.instruction = 0xc500b10; | |
15019 | do_vfp_cond_or_thumb (); | |
15020 | inst.instruction |= inst.operands[0].reg << 12; | |
15021 | inst.instruction |= inst.operands[1].reg << 16; | |
15022 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15023 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15024 | break; | |
5f4273c7 | 15025 | |
037e8744 JB |
15026 | case NS_FF: /* case 8 (fcpys). */ |
15027 | do_vfp_nsyn_opcode ("fcpys"); | |
15028 | break; | |
5f4273c7 | 15029 | |
037e8744 JB |
15030 | case NS_FI: /* case 10 (fconsts). */ |
15031 | ldconst = "fconsts"; | |
15032 | encode_fconstd: | |
15033 | if (is_quarter_float (inst.operands[1].imm)) | |
5287ad62 | 15034 | { |
037e8744 JB |
15035 | inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); |
15036 | do_vfp_nsyn_opcode (ldconst); | |
5287ad62 JB |
15037 | } |
15038 | else | |
037e8744 JB |
15039 | first_error (_("immediate out of range")); |
15040 | break; | |
5f4273c7 | 15041 | |
037e8744 JB |
15042 | case NS_RF: /* case 12 (fmrs). */ |
15043 | do_vfp_nsyn_opcode ("fmrs"); | |
15044 | break; | |
5f4273c7 | 15045 | |
037e8744 JB |
15046 | case NS_FR: /* case 13 (fmsr). */ |
15047 | do_vfp_nsyn_opcode ("fmsr"); | |
15048 | break; | |
5f4273c7 | 15049 | |
037e8744 JB |
15050 | /* The encoders for the fmrrs and fmsrr instructions expect three operands |
15051 | (one of which is a list), but we have parsed four. Do some fiddling to | |
15052 | make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 | |
15053 | expect. */ | |
15054 | case NS_RRFF: /* case 14 (fmrrs). */ | |
15055 | constraint (inst.operands[3].reg != inst.operands[2].reg + 1, | |
15056 | _("VFP registers must be adjacent")); | |
15057 | inst.operands[2].imm = 2; | |
15058 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
15059 | do_vfp_nsyn_opcode ("fmrrs"); | |
15060 | break; | |
5f4273c7 | 15061 | |
037e8744 JB |
15062 | case NS_FFRR: /* case 15 (fmsrr). */ |
15063 | constraint (inst.operands[1].reg != inst.operands[0].reg + 1, | |
15064 | _("VFP registers must be adjacent")); | |
15065 | inst.operands[1] = inst.operands[2]; | |
15066 | inst.operands[2] = inst.operands[3]; | |
15067 | inst.operands[0].imm = 2; | |
15068 | memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); | |
15069 | do_vfp_nsyn_opcode ("fmsrr"); | |
5287ad62 | 15070 | break; |
5f4273c7 | 15071 | |
5287ad62 JB |
15072 | default: |
15073 | abort (); | |
15074 | } | |
15075 | } | |
15076 | ||
15077 | static void | |
15078 | do_neon_rshift_round_imm (void) | |
15079 | { | |
037e8744 | 15080 | enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); |
5287ad62 JB |
15081 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); |
15082 | int imm = inst.operands[2].imm; | |
15083 | ||
15084 | /* imm == 0 case is encoded as VMOV for V{R}SHR. */ | |
15085 | if (imm == 0) | |
15086 | { | |
15087 | inst.operands[2].present = 0; | |
15088 | do_neon_mov (); | |
15089 | return; | |
15090 | } | |
15091 | ||
15092 | constraint (imm < 1 || (unsigned)imm > et.size, | |
15093 | _("immediate out of range for shift")); | |
037e8744 | 15094 | neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, |
5287ad62 JB |
15095 | et.size - imm); |
15096 | } | |
15097 | ||
15098 | static void | |
15099 | do_neon_movl (void) | |
15100 | { | |
15101 | struct neon_type_el et = neon_check_type (2, NS_QD, | |
15102 | N_EQK | N_DBL, N_SU_32 | N_KEY); | |
15103 | unsigned sizebits = et.size >> 3; | |
15104 | inst.instruction |= sizebits << 19; | |
15105 | neon_two_same (0, et.type == NT_unsigned, -1); | |
15106 | } | |
15107 | ||
15108 | static void | |
15109 | do_neon_trn (void) | |
15110 | { | |
037e8744 | 15111 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15112 | struct neon_type_el et = neon_check_type (2, rs, |
15113 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
88714cb8 | 15114 | NEON_ENCODE (INTEGER, inst); |
037e8744 | 15115 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15116 | } |
15117 | ||
15118 | static void | |
15119 | do_neon_zip_uzp (void) | |
15120 | { | |
037e8744 | 15121 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15122 | struct neon_type_el et = neon_check_type (2, rs, |
15123 | N_EQK, N_8 | N_16 | N_32 | N_KEY); | |
15124 | if (rs == NS_DD && et.size == 32) | |
15125 | { | |
15126 | /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ | |
15127 | inst.instruction = N_MNEM_vtrn; | |
15128 | do_neon_trn (); | |
15129 | return; | |
15130 | } | |
037e8744 | 15131 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15132 | } |
15133 | ||
15134 | static void | |
15135 | do_neon_sat_abs_neg (void) | |
15136 | { | |
037e8744 | 15137 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15138 | struct neon_type_el et = neon_check_type (2, rs, |
15139 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 15140 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15141 | } |
15142 | ||
15143 | static void | |
15144 | do_neon_pair_long (void) | |
15145 | { | |
037e8744 | 15146 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15147 | struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); |
15148 | /* Unsigned is encoded in OP field (bit 7) for these instruction. */ | |
15149 | inst.instruction |= (et.type == NT_unsigned) << 7; | |
037e8744 | 15150 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15151 | } |
15152 | ||
15153 | static void | |
15154 | do_neon_recip_est (void) | |
15155 | { | |
037e8744 | 15156 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15157 | struct neon_type_el et = neon_check_type (2, rs, |
15158 | N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); | |
15159 | inst.instruction |= (et.type == NT_float) << 8; | |
037e8744 | 15160 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15161 | } |
15162 | ||
15163 | static void | |
15164 | do_neon_cls (void) | |
15165 | { | |
037e8744 | 15166 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15167 | struct neon_type_el et = neon_check_type (2, rs, |
15168 | N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); | |
037e8744 | 15169 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15170 | } |
15171 | ||
15172 | static void | |
15173 | do_neon_clz (void) | |
15174 | { | |
037e8744 | 15175 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15176 | struct neon_type_el et = neon_check_type (2, rs, |
15177 | N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); | |
037e8744 | 15178 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15179 | } |
15180 | ||
15181 | static void | |
15182 | do_neon_cnt (void) | |
15183 | { | |
037e8744 | 15184 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
5287ad62 JB |
15185 | struct neon_type_el et = neon_check_type (2, rs, |
15186 | N_EQK | N_INT, N_8 | N_KEY); | |
037e8744 | 15187 | neon_two_same (neon_quad (rs), 1, et.size); |
5287ad62 JB |
15188 | } |
15189 | ||
15190 | static void | |
15191 | do_neon_swp (void) | |
15192 | { | |
037e8744 JB |
15193 | enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); |
15194 | neon_two_same (neon_quad (rs), 1, -1); | |
5287ad62 JB |
15195 | } |
15196 | ||
15197 | static void | |
15198 | do_neon_tbl_tbx (void) | |
15199 | { | |
15200 | unsigned listlenbits; | |
dcbf9037 | 15201 | neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); |
5f4273c7 | 15202 | |
5287ad62 JB |
15203 | if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) |
15204 | { | |
dcbf9037 | 15205 | first_error (_("bad list length for table lookup")); |
5287ad62 JB |
15206 | return; |
15207 | } | |
5f4273c7 | 15208 | |
5287ad62 JB |
15209 | listlenbits = inst.operands[1].imm - 1; |
15210 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15211 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15212 | inst.instruction |= LOW4 (inst.operands[1].reg) << 16; | |
15213 | inst.instruction |= HI1 (inst.operands[1].reg) << 7; | |
15214 | inst.instruction |= LOW4 (inst.operands[2].reg); | |
15215 | inst.instruction |= HI1 (inst.operands[2].reg) << 5; | |
15216 | inst.instruction |= listlenbits << 8; | |
5f4273c7 | 15217 | |
88714cb8 | 15218 | neon_dp_fixup (&inst); |
5287ad62 JB |
15219 | } |
15220 | ||
15221 | static void | |
15222 | do_neon_ldm_stm (void) | |
15223 | { | |
15224 | /* P, U and L bits are part of bitmask. */ | |
15225 | int is_dbmode = (inst.instruction & (1 << 24)) != 0; | |
15226 | unsigned offsetbits = inst.operands[1].imm * 2; | |
15227 | ||
037e8744 JB |
15228 | if (inst.operands[1].issingle) |
15229 | { | |
15230 | do_vfp_nsyn_ldm_stm (is_dbmode); | |
15231 | return; | |
15232 | } | |
15233 | ||
5287ad62 JB |
15234 | constraint (is_dbmode && !inst.operands[0].writeback, |
15235 | _("writeback (!) must be used for VLDMDB and VSTMDB")); | |
15236 | ||
15237 | constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, | |
15238 | _("register list must contain at least 1 and at most 16 " | |
15239 | "registers")); | |
15240 | ||
15241 | inst.instruction |= inst.operands[0].reg << 16; | |
15242 | inst.instruction |= inst.operands[0].writeback << 21; | |
15243 | inst.instruction |= LOW4 (inst.operands[1].reg) << 12; | |
15244 | inst.instruction |= HI1 (inst.operands[1].reg) << 22; | |
15245 | ||
15246 | inst.instruction |= offsetbits; | |
5f4273c7 | 15247 | |
037e8744 | 15248 | do_vfp_cond_or_thumb (); |
5287ad62 JB |
15249 | } |
15250 | ||
15251 | static void | |
15252 | do_neon_ldr_str (void) | |
15253 | { | |
5287ad62 | 15254 | int is_ldr = (inst.instruction & (1 << 20)) != 0; |
5f4273c7 | 15255 | |
6844b2c2 MGD |
15256 | /* Use of PC in vstr in ARM mode is deprecated in ARMv7. |
15257 | And is UNPREDICTABLE in thumb mode. */ | |
15258 | if (!is_ldr | |
15259 | && inst.operands[1].reg == REG_PC | |
15260 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7)) | |
15261 | { | |
15262 | if (!thumb_mode && warn_on_deprecated) | |
15263 | as_warn (_("Use of PC here is deprecated")); | |
15264 | else | |
15265 | inst.error = _("Use of PC here is UNPREDICTABLE"); | |
15266 | } | |
15267 | ||
037e8744 JB |
15268 | if (inst.operands[0].issingle) |
15269 | { | |
cd2f129f JB |
15270 | if (is_ldr) |
15271 | do_vfp_nsyn_opcode ("flds"); | |
15272 | else | |
15273 | do_vfp_nsyn_opcode ("fsts"); | |
5287ad62 JB |
15274 | } |
15275 | else | |
5287ad62 | 15276 | { |
cd2f129f JB |
15277 | if (is_ldr) |
15278 | do_vfp_nsyn_opcode ("fldd"); | |
5287ad62 | 15279 | else |
cd2f129f | 15280 | do_vfp_nsyn_opcode ("fstd"); |
5287ad62 | 15281 | } |
5287ad62 JB |
15282 | } |
15283 | ||
15284 | /* "interleave" version also handles non-interleaving register VLD1/VST1 | |
15285 | instructions. */ | |
15286 | ||
15287 | static void | |
15288 | do_neon_ld_st_interleave (void) | |
15289 | { | |
037e8744 | 15290 | struct neon_type_el et = neon_check_type (1, NS_NULL, |
5287ad62 JB |
15291 | N_8 | N_16 | N_32 | N_64); |
15292 | unsigned alignbits = 0; | |
15293 | unsigned idx; | |
15294 | /* The bits in this table go: | |
15295 | 0: register stride of one (0) or two (1) | |
15296 | 1,2: register list length, minus one (1, 2, 3, 4). | |
15297 | 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). | |
15298 | We use -1 for invalid entries. */ | |
15299 | const int typetable[] = | |
15300 | { | |
15301 | 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ | |
15302 | -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ | |
15303 | -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ | |
15304 | -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ | |
15305 | }; | |
15306 | int typebits; | |
15307 | ||
dcbf9037 JB |
15308 | if (et.type == NT_invtype) |
15309 | return; | |
15310 | ||
5287ad62 JB |
15311 | if (inst.operands[1].immisalign) |
15312 | switch (inst.operands[1].imm >> 8) | |
15313 | { | |
15314 | case 64: alignbits = 1; break; | |
15315 | case 128: | |
e23c0ad8 JZ |
15316 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2 |
15317 | && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) | |
5287ad62 JB |
15318 | goto bad_alignment; |
15319 | alignbits = 2; | |
15320 | break; | |
15321 | case 256: | |
e23c0ad8 | 15322 | if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4) |
5287ad62 JB |
15323 | goto bad_alignment; |
15324 | alignbits = 3; | |
15325 | break; | |
15326 | default: | |
15327 | bad_alignment: | |
dcbf9037 | 15328 | first_error (_("bad alignment")); |
5287ad62 JB |
15329 | return; |
15330 | } | |
15331 | ||
15332 | inst.instruction |= alignbits << 4; | |
15333 | inst.instruction |= neon_logbits (et.size) << 6; | |
15334 | ||
15335 | /* Bits [4:6] of the immediate in a list specifier encode register stride | |
15336 | (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of | |
15337 | VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look | |
15338 | up the right value for "type" in a table based on this value and the given | |
15339 | list style, then stick it back. */ | |
15340 | idx = ((inst.operands[0].imm >> 4) & 7) | |
15341 | | (((inst.instruction >> 8) & 3) << 3); | |
15342 | ||
15343 | typebits = typetable[idx]; | |
5f4273c7 | 15344 | |
5287ad62 JB |
15345 | constraint (typebits == -1, _("bad list type for instruction")); |
15346 | ||
15347 | inst.instruction &= ~0xf00; | |
15348 | inst.instruction |= typebits << 8; | |
15349 | } | |
15350 | ||
15351 | /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. | |
15352 | *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 | |
15353 | otherwise. The variable arguments are a list of pairs of legal (size, align) | |
15354 | values, terminated with -1. */ | |
15355 | ||
15356 | static int | |
15357 | neon_alignment_bit (int size, int align, int *do_align, ...) | |
15358 | { | |
15359 | va_list ap; | |
15360 | int result = FAIL, thissize, thisalign; | |
5f4273c7 | 15361 | |
5287ad62 JB |
15362 | if (!inst.operands[1].immisalign) |
15363 | { | |
15364 | *do_align = 0; | |
15365 | return SUCCESS; | |
15366 | } | |
5f4273c7 | 15367 | |
5287ad62 JB |
15368 | va_start (ap, do_align); |
15369 | ||
15370 | do | |
15371 | { | |
15372 | thissize = va_arg (ap, int); | |
15373 | if (thissize == -1) | |
15374 | break; | |
15375 | thisalign = va_arg (ap, int); | |
15376 | ||
15377 | if (size == thissize && align == thisalign) | |
15378 | result = SUCCESS; | |
15379 | } | |
15380 | while (result != SUCCESS); | |
15381 | ||
15382 | va_end (ap); | |
15383 | ||
15384 | if (result == SUCCESS) | |
15385 | *do_align = 1; | |
15386 | else | |
dcbf9037 | 15387 | first_error (_("unsupported alignment for instruction")); |
5f4273c7 | 15388 | |
5287ad62 JB |
15389 | return result; |
15390 | } | |
15391 | ||
15392 | static void | |
15393 | do_neon_ld_st_lane (void) | |
15394 | { | |
037e8744 | 15395 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
15396 | int align_good, do_align = 0; |
15397 | int logsize = neon_logbits (et.size); | |
15398 | int align = inst.operands[1].imm >> 8; | |
15399 | int n = (inst.instruction >> 8) & 3; | |
15400 | int max_el = 64 / et.size; | |
5f4273c7 | 15401 | |
dcbf9037 JB |
15402 | if (et.type == NT_invtype) |
15403 | return; | |
5f4273c7 | 15404 | |
5287ad62 JB |
15405 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, |
15406 | _("bad list length")); | |
15407 | constraint (NEON_LANE (inst.operands[0].imm) >= max_el, | |
15408 | _("scalar index out of range")); | |
15409 | constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 | |
15410 | && et.size == 8, | |
15411 | _("stride of 2 unavailable when element size is 8")); | |
5f4273c7 | 15412 | |
5287ad62 JB |
15413 | switch (n) |
15414 | { | |
15415 | case 0: /* VLD1 / VST1. */ | |
15416 | align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, | |
15417 | 32, 32, -1); | |
15418 | if (align_good == FAIL) | |
15419 | return; | |
15420 | if (do_align) | |
15421 | { | |
15422 | unsigned alignbits = 0; | |
15423 | switch (et.size) | |
15424 | { | |
15425 | case 16: alignbits = 0x1; break; | |
15426 | case 32: alignbits = 0x3; break; | |
15427 | default: ; | |
15428 | } | |
15429 | inst.instruction |= alignbits << 4; | |
15430 | } | |
15431 | break; | |
15432 | ||
15433 | case 1: /* VLD2 / VST2. */ | |
15434 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, | |
15435 | 32, 64, -1); | |
15436 | if (align_good == FAIL) | |
15437 | return; | |
15438 | if (do_align) | |
15439 | inst.instruction |= 1 << 4; | |
15440 | break; | |
15441 | ||
15442 | case 2: /* VLD3 / VST3. */ | |
15443 | constraint (inst.operands[1].immisalign, | |
15444 | _("can't use alignment with this instruction")); | |
15445 | break; | |
15446 | ||
15447 | case 3: /* VLD4 / VST4. */ | |
15448 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
15449 | 16, 64, 32, 64, 32, 128, -1); | |
15450 | if (align_good == FAIL) | |
15451 | return; | |
15452 | if (do_align) | |
15453 | { | |
15454 | unsigned alignbits = 0; | |
15455 | switch (et.size) | |
15456 | { | |
15457 | case 8: alignbits = 0x1; break; | |
15458 | case 16: alignbits = 0x1; break; | |
15459 | case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; | |
15460 | default: ; | |
15461 | } | |
15462 | inst.instruction |= alignbits << 4; | |
15463 | } | |
15464 | break; | |
15465 | ||
15466 | default: ; | |
15467 | } | |
15468 | ||
15469 | /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ | |
15470 | if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15471 | inst.instruction |= 1 << (4 + logsize); | |
5f4273c7 | 15472 | |
5287ad62 JB |
15473 | inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); |
15474 | inst.instruction |= logsize << 10; | |
15475 | } | |
15476 | ||
15477 | /* Encode single n-element structure to all lanes VLD<n> instructions. */ | |
15478 | ||
15479 | static void | |
15480 | do_neon_ld_dup (void) | |
15481 | { | |
037e8744 | 15482 | struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); |
5287ad62 JB |
15483 | int align_good, do_align = 0; |
15484 | ||
dcbf9037 JB |
15485 | if (et.type == NT_invtype) |
15486 | return; | |
15487 | ||
5287ad62 JB |
15488 | switch ((inst.instruction >> 8) & 3) |
15489 | { | |
15490 | case 0: /* VLD1. */ | |
9c2799c2 | 15491 | gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); |
5287ad62 JB |
15492 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, |
15493 | &do_align, 16, 16, 32, 32, -1); | |
15494 | if (align_good == FAIL) | |
15495 | return; | |
15496 | switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) | |
15497 | { | |
15498 | case 1: break; | |
15499 | case 2: inst.instruction |= 1 << 5; break; | |
dcbf9037 | 15500 | default: first_error (_("bad list length")); return; |
5287ad62 JB |
15501 | } |
15502 | inst.instruction |= neon_logbits (et.size) << 6; | |
15503 | break; | |
15504 | ||
15505 | case 1: /* VLD2. */ | |
15506 | align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, | |
15507 | &do_align, 8, 16, 16, 32, 32, 64, -1); | |
15508 | if (align_good == FAIL) | |
15509 | return; | |
15510 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, | |
15511 | _("bad list length")); | |
15512 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15513 | inst.instruction |= 1 << 5; | |
15514 | inst.instruction |= neon_logbits (et.size) << 6; | |
15515 | break; | |
15516 | ||
15517 | case 2: /* VLD3. */ | |
15518 | constraint (inst.operands[1].immisalign, | |
15519 | _("can't use alignment with this instruction")); | |
15520 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, | |
15521 | _("bad list length")); | |
15522 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15523 | inst.instruction |= 1 << 5; | |
15524 | inst.instruction |= neon_logbits (et.size) << 6; | |
15525 | break; | |
15526 | ||
15527 | case 3: /* VLD4. */ | |
15528 | { | |
15529 | int align = inst.operands[1].imm >> 8; | |
15530 | align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, | |
15531 | 16, 64, 32, 64, 32, 128, -1); | |
15532 | if (align_good == FAIL) | |
15533 | return; | |
15534 | constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, | |
15535 | _("bad list length")); | |
15536 | if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) | |
15537 | inst.instruction |= 1 << 5; | |
15538 | if (et.size == 32 && align == 128) | |
15539 | inst.instruction |= 0x3 << 6; | |
15540 | else | |
15541 | inst.instruction |= neon_logbits (et.size) << 6; | |
15542 | } | |
15543 | break; | |
15544 | ||
15545 | default: ; | |
15546 | } | |
15547 | ||
15548 | inst.instruction |= do_align << 4; | |
15549 | } | |
15550 | ||
15551 | /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those | |
15552 | apart from bits [11:4]. */ | |
15553 | ||
15554 | static void | |
15555 | do_neon_ldx_stx (void) | |
15556 | { | |
b1a769ed DG |
15557 | if (inst.operands[1].isreg) |
15558 | constraint (inst.operands[1].reg == REG_PC, BAD_PC); | |
15559 | ||
5287ad62 JB |
15560 | switch (NEON_LANE (inst.operands[0].imm)) |
15561 | { | |
15562 | case NEON_INTERLEAVE_LANES: | |
88714cb8 | 15563 | NEON_ENCODE (INTERLV, inst); |
5287ad62 JB |
15564 | do_neon_ld_st_interleave (); |
15565 | break; | |
5f4273c7 | 15566 | |
5287ad62 | 15567 | case NEON_ALL_LANES: |
88714cb8 | 15568 | NEON_ENCODE (DUP, inst); |
5287ad62 JB |
15569 | do_neon_ld_dup (); |
15570 | break; | |
5f4273c7 | 15571 | |
5287ad62 | 15572 | default: |
88714cb8 | 15573 | NEON_ENCODE (LANE, inst); |
5287ad62 JB |
15574 | do_neon_ld_st_lane (); |
15575 | } | |
15576 | ||
15577 | /* L bit comes from bit mask. */ | |
15578 | inst.instruction |= LOW4 (inst.operands[0].reg) << 12; | |
15579 | inst.instruction |= HI1 (inst.operands[0].reg) << 22; | |
15580 | inst.instruction |= inst.operands[1].reg << 16; | |
5f4273c7 | 15581 | |
5287ad62 JB |
15582 | if (inst.operands[1].postind) |
15583 | { | |
15584 | int postreg = inst.operands[1].imm & 0xf; | |
15585 | constraint (!inst.operands[1].immisreg, | |
15586 | _("post-index must be a register")); | |
15587 | constraint (postreg == 0xd || postreg == 0xf, | |
15588 | _("bad register for post-index")); | |
15589 | inst.instruction |= postreg; | |
15590 | } | |
15591 | else if (inst.operands[1].writeback) | |
15592 | { | |
15593 | inst.instruction |= 0xd; | |
15594 | } | |
15595 | else | |
5f4273c7 NC |
15596 | inst.instruction |= 0xf; |
15597 | ||
5287ad62 JB |
15598 | if (thumb_mode) |
15599 | inst.instruction |= 0xf9000000; | |
15600 | else | |
15601 | inst.instruction |= 0xf4000000; | |
15602 | } | |
5287ad62 JB |
15603 | \f |
15604 | /* Overall per-instruction processing. */ | |
15605 | ||
15606 | /* We need to be able to fix up arbitrary expressions in some statements. | |
15607 | This is so that we can handle symbols that are an arbitrary distance from | |
15608 | the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), | |
15609 | which returns part of an address in a form which will be valid for | |
15610 | a data instruction. We do this by pushing the expression into a symbol | |
15611 | in the expr_section, and creating a fix for that. */ | |
15612 | ||
15613 | static void | |
15614 | fix_new_arm (fragS * frag, | |
15615 | int where, | |
15616 | short int size, | |
15617 | expressionS * exp, | |
15618 | int pc_rel, | |
15619 | int reloc) | |
15620 | { | |
15621 | fixS * new_fix; | |
15622 | ||
15623 | switch (exp->X_op) | |
15624 | { | |
15625 | case O_constant: | |
6e7ce2cd PB |
15626 | if (pc_rel) |
15627 | { | |
15628 | /* Create an absolute valued symbol, so we have something to | |
15629 | refer to in the object file. Unfortunately for us, gas's | |
15630 | generic expression parsing will already have folded out | |
15631 | any use of .set foo/.type foo %function that may have | |
15632 | been used to set type information of the target location, | |
15633 | that's being specified symbolically. We have to presume | |
15634 | the user knows what they are doing. */ | |
15635 | char name[16 + 8]; | |
15636 | symbolS *symbol; | |
15637 | ||
15638 | sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number); | |
15639 | ||
15640 | symbol = symbol_find_or_make (name); | |
15641 | S_SET_SEGMENT (symbol, absolute_section); | |
15642 | symbol_set_frag (symbol, &zero_address_frag); | |
15643 | S_SET_VALUE (symbol, exp->X_add_number); | |
15644 | exp->X_op = O_symbol; | |
15645 | exp->X_add_symbol = symbol; | |
15646 | exp->X_add_number = 0; | |
15647 | } | |
15648 | /* FALLTHROUGH */ | |
5287ad62 JB |
15649 | case O_symbol: |
15650 | case O_add: | |
15651 | case O_subtract: | |
21d799b5 NC |
15652 | new_fix = fix_new_exp (frag, where, size, exp, pc_rel, |
15653 | (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15654 | break; |
15655 | ||
15656 | default: | |
21d799b5 NC |
15657 | new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0, |
15658 | pc_rel, (enum bfd_reloc_code_real) reloc); | |
5287ad62 JB |
15659 | break; |
15660 | } | |
15661 | ||
15662 | /* Mark whether the fix is to a THUMB instruction, or an ARM | |
15663 | instruction. */ | |
15664 | new_fix->tc_fix_data = thumb_mode; | |
15665 | } | |
15666 | ||
15667 | /* Create a frg for an instruction requiring relaxation. */ | |
15668 | static void | |
15669 | output_relax_insn (void) | |
15670 | { | |
15671 | char * to; | |
15672 | symbolS *sym; | |
0110f2b8 PB |
15673 | int offset; |
15674 | ||
6e1cb1a6 PB |
15675 | /* The size of the instruction is unknown, so tie the debug info to the |
15676 | start of the instruction. */ | |
15677 | dwarf2_emit_insn (0); | |
6e1cb1a6 | 15678 | |
0110f2b8 PB |
15679 | switch (inst.reloc.exp.X_op) |
15680 | { | |
15681 | case O_symbol: | |
15682 | sym = inst.reloc.exp.X_add_symbol; | |
15683 | offset = inst.reloc.exp.X_add_number; | |
15684 | break; | |
15685 | case O_constant: | |
15686 | sym = NULL; | |
15687 | offset = inst.reloc.exp.X_add_number; | |
15688 | break; | |
15689 | default: | |
15690 | sym = make_expr_symbol (&inst.reloc.exp); | |
15691 | offset = 0; | |
15692 | break; | |
15693 | } | |
15694 | to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, | |
15695 | inst.relax, sym, offset, NULL/*offset, opcode*/); | |
15696 | md_number_to_chars (to, inst.instruction, THUMB_SIZE); | |
0110f2b8 PB |
15697 | } |
15698 | ||
15699 | /* Write a 32-bit thumb instruction to buf. */ | |
15700 | static void | |
15701 | put_thumb32_insn (char * buf, unsigned long insn) | |
15702 | { | |
15703 | md_number_to_chars (buf, insn >> 16, THUMB_SIZE); | |
15704 | md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); | |
15705 | } | |
15706 | ||
b99bd4ef | 15707 | static void |
c19d1205 | 15708 | output_inst (const char * str) |
b99bd4ef | 15709 | { |
c19d1205 | 15710 | char * to = NULL; |
b99bd4ef | 15711 | |
c19d1205 | 15712 | if (inst.error) |
b99bd4ef | 15713 | { |
c19d1205 | 15714 | as_bad ("%s -- `%s'", inst.error, str); |
b99bd4ef NC |
15715 | return; |
15716 | } | |
5f4273c7 NC |
15717 | if (inst.relax) |
15718 | { | |
15719 | output_relax_insn (); | |
0110f2b8 | 15720 | return; |
5f4273c7 | 15721 | } |
c19d1205 ZW |
15722 | if (inst.size == 0) |
15723 | return; | |
b99bd4ef | 15724 | |
c19d1205 | 15725 | to = frag_more (inst.size); |
8dc2430f NC |
15726 | /* PR 9814: Record the thumb mode into the current frag so that we know |
15727 | what type of NOP padding to use, if necessary. We override any previous | |
15728 | setting so that if the mode has changed then the NOPS that we use will | |
15729 | match the encoding of the last instruction in the frag. */ | |
cd000bff | 15730 | frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
c19d1205 ZW |
15731 | |
15732 | if (thumb_mode && (inst.size > THUMB_SIZE)) | |
b99bd4ef | 15733 | { |
9c2799c2 | 15734 | gas_assert (inst.size == (2 * THUMB_SIZE)); |
0110f2b8 | 15735 | put_thumb32_insn (to, inst.instruction); |
b99bd4ef | 15736 | } |
c19d1205 | 15737 | else if (inst.size > INSN_SIZE) |
b99bd4ef | 15738 | { |
9c2799c2 | 15739 | gas_assert (inst.size == (2 * INSN_SIZE)); |
c19d1205 ZW |
15740 | md_number_to_chars (to, inst.instruction, INSN_SIZE); |
15741 | md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); | |
b99bd4ef | 15742 | } |
c19d1205 ZW |
15743 | else |
15744 | md_number_to_chars (to, inst.instruction, inst.size); | |
b99bd4ef | 15745 | |
c19d1205 ZW |
15746 | if (inst.reloc.type != BFD_RELOC_UNUSED) |
15747 | fix_new_arm (frag_now, to - frag_now->fr_literal, | |
15748 | inst.size, & inst.reloc.exp, inst.reloc.pc_rel, | |
15749 | inst.reloc.type); | |
b99bd4ef | 15750 | |
c19d1205 | 15751 | dwarf2_emit_insn (inst.size); |
c19d1205 | 15752 | } |
b99bd4ef | 15753 | |
e07e6e58 NC |
15754 | static char * |
15755 | output_it_inst (int cond, int mask, char * to) | |
15756 | { | |
15757 | unsigned long instruction = 0xbf00; | |
15758 | ||
15759 | mask &= 0xf; | |
15760 | instruction |= mask; | |
15761 | instruction |= cond << 4; | |
15762 | ||
15763 | if (to == NULL) | |
15764 | { | |
15765 | to = frag_more (2); | |
15766 | #ifdef OBJ_ELF | |
15767 | dwarf2_emit_insn (2); | |
15768 | #endif | |
15769 | } | |
15770 | ||
15771 | md_number_to_chars (to, instruction, 2); | |
15772 | ||
15773 | return to; | |
15774 | } | |
15775 | ||
c19d1205 ZW |
15776 | /* Tag values used in struct asm_opcode's tag field. */ |
15777 | enum opcode_tag | |
15778 | { | |
15779 | OT_unconditional, /* Instruction cannot be conditionalized. | |
15780 | The ARM condition field is still 0xE. */ | |
15781 | OT_unconditionalF, /* Instruction cannot be conditionalized | |
15782 | and carries 0xF in its ARM condition field. */ | |
15783 | OT_csuffix, /* Instruction takes a conditional suffix. */ | |
037e8744 JB |
15784 | OT_csuffixF, /* Some forms of the instruction take a conditional |
15785 | suffix, others place 0xF where the condition field | |
15786 | would be. */ | |
c19d1205 ZW |
15787 | OT_cinfix3, /* Instruction takes a conditional infix, |
15788 | beginning at character index 3. (In | |
15789 | unified mode, it becomes a suffix.) */ | |
088fa78e KH |
15790 | OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for |
15791 | tsts, cmps, cmns, and teqs. */ | |
e3cb604e PB |
15792 | OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at |
15793 | character index 3, even in unified mode. Used for | |
15794 | legacy instructions where suffix and infix forms | |
15795 | may be ambiguous. */ | |
c19d1205 | 15796 | OT_csuf_or_in3, /* Instruction takes either a conditional |
e3cb604e | 15797 | suffix or an infix at character index 3. */ |
c19d1205 ZW |
15798 | OT_odd_infix_unc, /* This is the unconditional variant of an |
15799 | instruction that takes a conditional infix | |
15800 | at an unusual position. In unified mode, | |
15801 | this variant will accept a suffix. */ | |
15802 | OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 | |
15803 | are the conditional variants of instructions that | |
15804 | take conditional infixes in unusual positions. | |
15805 | The infix appears at character index | |
15806 | (tag - OT_odd_infix_0). These are not accepted | |
15807 | in unified mode. */ | |
15808 | }; | |
b99bd4ef | 15809 | |
c19d1205 ZW |
15810 | /* Subroutine of md_assemble, responsible for looking up the primary |
15811 | opcode from the mnemonic the user wrote. STR points to the | |
15812 | beginning of the mnemonic. | |
15813 | ||
15814 | This is not simply a hash table lookup, because of conditional | |
15815 | variants. Most instructions have conditional variants, which are | |
15816 | expressed with a _conditional affix_ to the mnemonic. If we were | |
15817 | to encode each conditional variant as a literal string in the opcode | |
15818 | table, it would have approximately 20,000 entries. | |
15819 | ||
15820 | Most mnemonics take this affix as a suffix, and in unified syntax, | |
15821 | 'most' is upgraded to 'all'. However, in the divided syntax, some | |
15822 | instructions take the affix as an infix, notably the s-variants of | |
15823 | the arithmetic instructions. Of those instructions, all but six | |
15824 | have the infix appear after the third character of the mnemonic. | |
15825 | ||
15826 | Accordingly, the algorithm for looking up primary opcodes given | |
15827 | an identifier is: | |
15828 | ||
15829 | 1. Look up the identifier in the opcode table. | |
15830 | If we find a match, go to step U. | |
15831 | ||
15832 | 2. Look up the last two characters of the identifier in the | |
15833 | conditions table. If we find a match, look up the first N-2 | |
15834 | characters of the identifier in the opcode table. If we | |
15835 | find a match, go to step CE. | |
15836 | ||
15837 | 3. Look up the fourth and fifth characters of the identifier in | |
15838 | the conditions table. If we find a match, extract those | |
15839 | characters from the identifier, and look up the remaining | |
15840 | characters in the opcode table. If we find a match, go | |
15841 | to step CM. | |
15842 | ||
15843 | 4. Fail. | |
15844 | ||
15845 | U. Examine the tag field of the opcode structure, in case this is | |
15846 | one of the six instructions with its conditional infix in an | |
15847 | unusual place. If it is, the tag tells us where to find the | |
15848 | infix; look it up in the conditions table and set inst.cond | |
15849 | accordingly. Otherwise, this is an unconditional instruction. | |
15850 | Again set inst.cond accordingly. Return the opcode structure. | |
15851 | ||
15852 | CE. Examine the tag field to make sure this is an instruction that | |
15853 | should receive a conditional suffix. If it is not, fail. | |
15854 | Otherwise, set inst.cond from the suffix we already looked up, | |
15855 | and return the opcode structure. | |
15856 | ||
15857 | CM. Examine the tag field to make sure this is an instruction that | |
15858 | should receive a conditional infix after the third character. | |
15859 | If it is not, fail. Otherwise, undo the edits to the current | |
15860 | line of input and proceed as for case CE. */ | |
15861 | ||
15862 | static const struct asm_opcode * | |
15863 | opcode_lookup (char **str) | |
15864 | { | |
15865 | char *end, *base; | |
15866 | char *affix; | |
15867 | const struct asm_opcode *opcode; | |
15868 | const struct asm_cond *cond; | |
e3cb604e | 15869 | char save[2]; |
c19d1205 ZW |
15870 | |
15871 | /* Scan up to the end of the mnemonic, which must end in white space, | |
721a8186 | 15872 | '.' (in unified mode, or for Neon/VFP instructions), or end of string. */ |
c19d1205 | 15873 | for (base = end = *str; *end != '\0'; end++) |
721a8186 | 15874 | if (*end == ' ' || *end == '.') |
c19d1205 | 15875 | break; |
b99bd4ef | 15876 | |
c19d1205 | 15877 | if (end == base) |
c921be7d | 15878 | return NULL; |
b99bd4ef | 15879 | |
5287ad62 | 15880 | /* Handle a possible width suffix and/or Neon type suffix. */ |
c19d1205 | 15881 | if (end[0] == '.') |
b99bd4ef | 15882 | { |
5287ad62 | 15883 | int offset = 2; |
5f4273c7 | 15884 | |
267d2029 JB |
15885 | /* The .w and .n suffixes are only valid if the unified syntax is in |
15886 | use. */ | |
15887 | if (unified_syntax && end[1] == 'w') | |
c19d1205 | 15888 | inst.size_req = 4; |
267d2029 | 15889 | else if (unified_syntax && end[1] == 'n') |
c19d1205 ZW |
15890 | inst.size_req = 2; |
15891 | else | |
5287ad62 JB |
15892 | offset = 0; |
15893 | ||
15894 | inst.vectype.elems = 0; | |
15895 | ||
15896 | *str = end + offset; | |
b99bd4ef | 15897 | |
5f4273c7 | 15898 | if (end[offset] == '.') |
5287ad62 | 15899 | { |
267d2029 JB |
15900 | /* See if we have a Neon type suffix (possible in either unified or |
15901 | non-unified ARM syntax mode). */ | |
dcbf9037 | 15902 | if (parse_neon_type (&inst.vectype, str) == FAIL) |
c921be7d | 15903 | return NULL; |
5287ad62 JB |
15904 | } |
15905 | else if (end[offset] != '\0' && end[offset] != ' ') | |
c921be7d | 15906 | return NULL; |
b99bd4ef | 15907 | } |
c19d1205 ZW |
15908 | else |
15909 | *str = end; | |
b99bd4ef | 15910 | |
c19d1205 | 15911 | /* Look for unaffixed or special-case affixed mnemonic. */ |
21d799b5 NC |
15912 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15913 | end - base); | |
c19d1205 | 15914 | if (opcode) |
b99bd4ef | 15915 | { |
c19d1205 ZW |
15916 | /* step U */ |
15917 | if (opcode->tag < OT_odd_infix_0) | |
b99bd4ef | 15918 | { |
c19d1205 ZW |
15919 | inst.cond = COND_ALWAYS; |
15920 | return opcode; | |
b99bd4ef | 15921 | } |
b99bd4ef | 15922 | |
278df34e | 15923 | if (warn_on_deprecated && unified_syntax) |
c19d1205 ZW |
15924 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
15925 | affix = base + (opcode->tag - OT_odd_infix_0); | |
21d799b5 | 15926 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
9c2799c2 | 15927 | gas_assert (cond); |
b99bd4ef | 15928 | |
c19d1205 ZW |
15929 | inst.cond = cond->value; |
15930 | return opcode; | |
15931 | } | |
b99bd4ef | 15932 | |
c19d1205 ZW |
15933 | /* Cannot have a conditional suffix on a mnemonic of less than two |
15934 | characters. */ | |
15935 | if (end - base < 3) | |
c921be7d | 15936 | return NULL; |
b99bd4ef | 15937 | |
c19d1205 ZW |
15938 | /* Look for suffixed mnemonic. */ |
15939 | affix = end - 2; | |
21d799b5 NC |
15940 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
15941 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, | |
15942 | affix - base); | |
c19d1205 ZW |
15943 | if (opcode && cond) |
15944 | { | |
15945 | /* step CE */ | |
15946 | switch (opcode->tag) | |
15947 | { | |
e3cb604e PB |
15948 | case OT_cinfix3_legacy: |
15949 | /* Ignore conditional suffixes matched on infix only mnemonics. */ | |
15950 | break; | |
15951 | ||
c19d1205 | 15952 | case OT_cinfix3: |
088fa78e | 15953 | case OT_cinfix3_deprecated: |
c19d1205 ZW |
15954 | case OT_odd_infix_unc: |
15955 | if (!unified_syntax) | |
e3cb604e | 15956 | return 0; |
c19d1205 ZW |
15957 | /* else fall through */ |
15958 | ||
15959 | case OT_csuffix: | |
037e8744 | 15960 | case OT_csuffixF: |
c19d1205 ZW |
15961 | case OT_csuf_or_in3: |
15962 | inst.cond = cond->value; | |
15963 | return opcode; | |
15964 | ||
15965 | case OT_unconditional: | |
15966 | case OT_unconditionalF: | |
dfa9f0d5 | 15967 | if (thumb_mode) |
c921be7d | 15968 | inst.cond = cond->value; |
dfa9f0d5 PB |
15969 | else |
15970 | { | |
c921be7d | 15971 | /* Delayed diagnostic. */ |
dfa9f0d5 PB |
15972 | inst.error = BAD_COND; |
15973 | inst.cond = COND_ALWAYS; | |
15974 | } | |
c19d1205 | 15975 | return opcode; |
b99bd4ef | 15976 | |
c19d1205 | 15977 | default: |
c921be7d | 15978 | return NULL; |
c19d1205 ZW |
15979 | } |
15980 | } | |
b99bd4ef | 15981 | |
c19d1205 ZW |
15982 | /* Cannot have a usual-position infix on a mnemonic of less than |
15983 | six characters (five would be a suffix). */ | |
15984 | if (end - base < 6) | |
c921be7d | 15985 | return NULL; |
b99bd4ef | 15986 | |
c19d1205 ZW |
15987 | /* Look for infixed mnemonic in the usual position. */ |
15988 | affix = base + 3; | |
21d799b5 | 15989 | cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2); |
e3cb604e | 15990 | if (!cond) |
c921be7d | 15991 | return NULL; |
e3cb604e PB |
15992 | |
15993 | memcpy (save, affix, 2); | |
15994 | memmove (affix, affix + 2, (end - affix) - 2); | |
21d799b5 NC |
15995 | opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base, |
15996 | (end - base) - 2); | |
e3cb604e PB |
15997 | memmove (affix + 2, affix, (end - affix) - 2); |
15998 | memcpy (affix, save, 2); | |
15999 | ||
088fa78e KH |
16000 | if (opcode |
16001 | && (opcode->tag == OT_cinfix3 | |
16002 | || opcode->tag == OT_cinfix3_deprecated | |
16003 | || opcode->tag == OT_csuf_or_in3 | |
16004 | || opcode->tag == OT_cinfix3_legacy)) | |
b99bd4ef | 16005 | { |
c921be7d | 16006 | /* Step CM. */ |
278df34e | 16007 | if (warn_on_deprecated && unified_syntax |
088fa78e KH |
16008 | && (opcode->tag == OT_cinfix3 |
16009 | || opcode->tag == OT_cinfix3_deprecated)) | |
c19d1205 ZW |
16010 | as_warn (_("conditional infixes are deprecated in unified syntax")); |
16011 | ||
16012 | inst.cond = cond->value; | |
16013 | return opcode; | |
b99bd4ef NC |
16014 | } |
16015 | ||
c921be7d | 16016 | return NULL; |
b99bd4ef NC |
16017 | } |
16018 | ||
e07e6e58 NC |
16019 | /* This function generates an initial IT instruction, leaving its block |
16020 | virtually open for the new instructions. Eventually, | |
16021 | the mask will be updated by now_it_add_mask () each time | |
16022 | a new instruction needs to be included in the IT block. | |
16023 | Finally, the block is closed with close_automatic_it_block (). | |
16024 | The block closure can be requested either from md_assemble (), | |
16025 | a tencode (), or due to a label hook. */ | |
16026 | ||
16027 | static void | |
16028 | new_automatic_it_block (int cond) | |
16029 | { | |
16030 | now_it.state = AUTOMATIC_IT_BLOCK; | |
16031 | now_it.mask = 0x18; | |
16032 | now_it.cc = cond; | |
16033 | now_it.block_length = 1; | |
cd000bff | 16034 | mapping_state (MAP_THUMB); |
e07e6e58 NC |
16035 | now_it.insn = output_it_inst (cond, now_it.mask, NULL); |
16036 | } | |
16037 | ||
16038 | /* Close an automatic IT block. | |
16039 | See comments in new_automatic_it_block (). */ | |
16040 | ||
16041 | static void | |
16042 | close_automatic_it_block (void) | |
16043 | { | |
16044 | now_it.mask = 0x10; | |
16045 | now_it.block_length = 0; | |
16046 | } | |
16047 | ||
16048 | /* Update the mask of the current automatically-generated IT | |
16049 | instruction. See comments in new_automatic_it_block (). */ | |
16050 | ||
16051 | static void | |
16052 | now_it_add_mask (int cond) | |
16053 | { | |
16054 | #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit))) | |
16055 | #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \ | |
16056 | | ((bitvalue) << (nbit))) | |
e07e6e58 | 16057 | const int resulting_bit = (cond & 1); |
c921be7d | 16058 | |
e07e6e58 NC |
16059 | now_it.mask &= 0xf; |
16060 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
16061 | resulting_bit, | |
16062 | (5 - now_it.block_length)); | |
16063 | now_it.mask = SET_BIT_VALUE (now_it.mask, | |
16064 | 1, | |
16065 | ((5 - now_it.block_length) - 1) ); | |
16066 | output_it_inst (now_it.cc, now_it.mask, now_it.insn); | |
16067 | ||
16068 | #undef CLEAR_BIT | |
16069 | #undef SET_BIT_VALUE | |
e07e6e58 NC |
16070 | } |
16071 | ||
16072 | /* The IT blocks handling machinery is accessed through the these functions: | |
16073 | it_fsm_pre_encode () from md_assemble () | |
16074 | set_it_insn_type () optional, from the tencode functions | |
16075 | set_it_insn_type_last () ditto | |
16076 | in_it_block () ditto | |
16077 | it_fsm_post_encode () from md_assemble () | |
16078 | force_automatic_it_block_close () from label habdling functions | |
16079 | ||
16080 | Rationale: | |
16081 | 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (), | |
16082 | initializing the IT insn type with a generic initial value depending | |
16083 | on the inst.condition. | |
16084 | 2) During the tencode function, two things may happen: | |
16085 | a) The tencode function overrides the IT insn type by | |
16086 | calling either set_it_insn_type (type) or set_it_insn_type_last (). | |
16087 | b) The tencode function queries the IT block state by | |
16088 | calling in_it_block () (i.e. to determine narrow/not narrow mode). | |
16089 | ||
16090 | Both set_it_insn_type and in_it_block run the internal FSM state | |
16091 | handling function (handle_it_state), because: a) setting the IT insn | |
16092 | type may incur in an invalid state (exiting the function), | |
16093 | and b) querying the state requires the FSM to be updated. | |
16094 | Specifically we want to avoid creating an IT block for conditional | |
16095 | branches, so it_fsm_pre_encode is actually a guess and we can't | |
16096 | determine whether an IT block is required until the tencode () routine | |
16097 | has decided what type of instruction this actually it. | |
16098 | Because of this, if set_it_insn_type and in_it_block have to be used, | |
16099 | set_it_insn_type has to be called first. | |
16100 | ||
16101 | set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that | |
16102 | determines the insn IT type depending on the inst.cond code. | |
16103 | When a tencode () routine encodes an instruction that can be | |
16104 | either outside an IT block, or, in the case of being inside, has to be | |
16105 | the last one, set_it_insn_type_last () will determine the proper | |
16106 | IT instruction type based on the inst.cond code. Otherwise, | |
16107 | set_it_insn_type can be called for overriding that logic or | |
16108 | for covering other cases. | |
16109 | ||
16110 | Calling handle_it_state () may not transition the IT block state to | |
16111 | OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be | |
16112 | still queried. Instead, if the FSM determines that the state should | |
16113 | be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed | |
16114 | after the tencode () function: that's what it_fsm_post_encode () does. | |
16115 | ||
16116 | Since in_it_block () calls the state handling function to get an | |
16117 | updated state, an error may occur (due to invalid insns combination). | |
16118 | In that case, inst.error is set. | |
16119 | Therefore, inst.error has to be checked after the execution of | |
16120 | the tencode () routine. | |
16121 | ||
16122 | 3) Back in md_assemble(), it_fsm_post_encode () is called to commit | |
16123 | any pending state change (if any) that didn't take place in | |
16124 | handle_it_state () as explained above. */ | |
16125 | ||
16126 | static void | |
16127 | it_fsm_pre_encode (void) | |
16128 | { | |
16129 | if (inst.cond != COND_ALWAYS) | |
16130 | inst.it_insn_type = INSIDE_IT_INSN; | |
16131 | else | |
16132 | inst.it_insn_type = OUTSIDE_IT_INSN; | |
16133 | ||
16134 | now_it.state_handled = 0; | |
16135 | } | |
16136 | ||
16137 | /* IT state FSM handling function. */ | |
16138 | ||
16139 | static int | |
16140 | handle_it_state (void) | |
16141 | { | |
16142 | now_it.state_handled = 1; | |
16143 | ||
16144 | switch (now_it.state) | |
16145 | { | |
16146 | case OUTSIDE_IT_BLOCK: | |
16147 | switch (inst.it_insn_type) | |
16148 | { | |
16149 | case OUTSIDE_IT_INSN: | |
16150 | break; | |
16151 | ||
16152 | case INSIDE_IT_INSN: | |
16153 | case INSIDE_IT_LAST_INSN: | |
16154 | if (thumb_mode == 0) | |
16155 | { | |
c921be7d | 16156 | if (unified_syntax |
e07e6e58 NC |
16157 | && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM)) |
16158 | as_tsktsk (_("Warning: conditional outside an IT block"\ | |
16159 | " for Thumb.")); | |
16160 | } | |
16161 | else | |
16162 | { | |
16163 | if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB) | |
16164 | && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)) | |
16165 | { | |
16166 | /* Automatically generate the IT instruction. */ | |
16167 | new_automatic_it_block (inst.cond); | |
16168 | if (inst.it_insn_type == INSIDE_IT_LAST_INSN) | |
16169 | close_automatic_it_block (); | |
16170 | } | |
16171 | else | |
16172 | { | |
16173 | inst.error = BAD_OUT_IT; | |
16174 | return FAIL; | |
16175 | } | |
16176 | } | |
16177 | break; | |
16178 | ||
16179 | case IF_INSIDE_IT_LAST_INSN: | |
16180 | case NEUTRAL_IT_INSN: | |
16181 | break; | |
16182 | ||
16183 | case IT_INSN: | |
16184 | now_it.state = MANUAL_IT_BLOCK; | |
16185 | now_it.block_length = 0; | |
16186 | break; | |
16187 | } | |
16188 | break; | |
16189 | ||
16190 | case AUTOMATIC_IT_BLOCK: | |
16191 | /* Three things may happen now: | |
16192 | a) We should increment current it block size; | |
16193 | b) We should close current it block (closing insn or 4 insns); | |
16194 | c) We should close current it block and start a new one (due | |
16195 | to incompatible conditions or | |
16196 | 4 insns-length block reached). */ | |
16197 | ||
16198 | switch (inst.it_insn_type) | |
16199 | { | |
16200 | case OUTSIDE_IT_INSN: | |
16201 | /* The closure of the block shall happen immediatelly, | |
16202 | so any in_it_block () call reports the block as closed. */ | |
16203 | force_automatic_it_block_close (); | |
16204 | break; | |
16205 | ||
16206 | case INSIDE_IT_INSN: | |
16207 | case INSIDE_IT_LAST_INSN: | |
16208 | case IF_INSIDE_IT_LAST_INSN: | |
16209 | now_it.block_length++; | |
16210 | ||
16211 | if (now_it.block_length > 4 | |
16212 | || !now_it_compatible (inst.cond)) | |
16213 | { | |
16214 | force_automatic_it_block_close (); | |
16215 | if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN) | |
16216 | new_automatic_it_block (inst.cond); | |
16217 | } | |
16218 | else | |
16219 | { | |
16220 | now_it_add_mask (inst.cond); | |
16221 | } | |
16222 | ||
16223 | if (now_it.state == AUTOMATIC_IT_BLOCK | |
16224 | && (inst.it_insn_type == INSIDE_IT_LAST_INSN | |
16225 | || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN)) | |
16226 | close_automatic_it_block (); | |
16227 | break; | |
16228 | ||
16229 | case NEUTRAL_IT_INSN: | |
16230 | now_it.block_length++; | |
16231 | ||
16232 | if (now_it.block_length > 4) | |
16233 | force_automatic_it_block_close (); | |
16234 | else | |
16235 | now_it_add_mask (now_it.cc & 1); | |
16236 | break; | |
16237 | ||
16238 | case IT_INSN: | |
16239 | close_automatic_it_block (); | |
16240 | now_it.state = MANUAL_IT_BLOCK; | |
16241 | break; | |
16242 | } | |
16243 | break; | |
16244 | ||
16245 | case MANUAL_IT_BLOCK: | |
16246 | { | |
16247 | /* Check conditional suffixes. */ | |
16248 | const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1; | |
16249 | int is_last; | |
16250 | now_it.mask <<= 1; | |
16251 | now_it.mask &= 0x1f; | |
16252 | is_last = (now_it.mask == 0x10); | |
16253 | ||
16254 | switch (inst.it_insn_type) | |
16255 | { | |
16256 | case OUTSIDE_IT_INSN: | |
16257 | inst.error = BAD_NOT_IT; | |
16258 | return FAIL; | |
16259 | ||
16260 | case INSIDE_IT_INSN: | |
16261 | if (cond != inst.cond) | |
16262 | { | |
16263 | inst.error = BAD_IT_COND; | |
16264 | return FAIL; | |
16265 | } | |
16266 | break; | |
16267 | ||
16268 | case INSIDE_IT_LAST_INSN: | |
16269 | case IF_INSIDE_IT_LAST_INSN: | |
16270 | if (cond != inst.cond) | |
16271 | { | |
16272 | inst.error = BAD_IT_COND; | |
16273 | return FAIL; | |
16274 | } | |
16275 | if (!is_last) | |
16276 | { | |
16277 | inst.error = BAD_BRANCH; | |
16278 | return FAIL; | |
16279 | } | |
16280 | break; | |
16281 | ||
16282 | case NEUTRAL_IT_INSN: | |
16283 | /* The BKPT instruction is unconditional even in an IT block. */ | |
16284 | break; | |
16285 | ||
16286 | case IT_INSN: | |
16287 | inst.error = BAD_IT_IT; | |
16288 | return FAIL; | |
16289 | } | |
16290 | } | |
16291 | break; | |
16292 | } | |
16293 | ||
16294 | return SUCCESS; | |
16295 | } | |
16296 | ||
16297 | static void | |
16298 | it_fsm_post_encode (void) | |
16299 | { | |
16300 | int is_last; | |
16301 | ||
16302 | if (!now_it.state_handled) | |
16303 | handle_it_state (); | |
16304 | ||
16305 | is_last = (now_it.mask == 0x10); | |
16306 | if (is_last) | |
16307 | { | |
16308 | now_it.state = OUTSIDE_IT_BLOCK; | |
16309 | now_it.mask = 0; | |
16310 | } | |
16311 | } | |
16312 | ||
16313 | static void | |
16314 | force_automatic_it_block_close (void) | |
16315 | { | |
16316 | if (now_it.state == AUTOMATIC_IT_BLOCK) | |
16317 | { | |
16318 | close_automatic_it_block (); | |
16319 | now_it.state = OUTSIDE_IT_BLOCK; | |
16320 | now_it.mask = 0; | |
16321 | } | |
16322 | } | |
16323 | ||
16324 | static int | |
16325 | in_it_block (void) | |
16326 | { | |
16327 | if (!now_it.state_handled) | |
16328 | handle_it_state (); | |
16329 | ||
16330 | return now_it.state != OUTSIDE_IT_BLOCK; | |
16331 | } | |
16332 | ||
c19d1205 ZW |
16333 | void |
16334 | md_assemble (char *str) | |
b99bd4ef | 16335 | { |
c19d1205 ZW |
16336 | char *p = str; |
16337 | const struct asm_opcode * opcode; | |
b99bd4ef | 16338 | |
c19d1205 ZW |
16339 | /* Align the previous label if needed. */ |
16340 | if (last_label_seen != NULL) | |
b99bd4ef | 16341 | { |
c19d1205 ZW |
16342 | symbol_set_frag (last_label_seen, frag_now); |
16343 | S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); | |
16344 | S_SET_SEGMENT (last_label_seen, now_seg); | |
b99bd4ef NC |
16345 | } |
16346 | ||
c19d1205 ZW |
16347 | memset (&inst, '\0', sizeof (inst)); |
16348 | inst.reloc.type = BFD_RELOC_UNUSED; | |
b99bd4ef | 16349 | |
c19d1205 ZW |
16350 | opcode = opcode_lookup (&p); |
16351 | if (!opcode) | |
b99bd4ef | 16352 | { |
c19d1205 | 16353 | /* It wasn't an instruction, but it might be a register alias of |
dcbf9037 | 16354 | the form alias .req reg, or a Neon .dn/.qn directive. */ |
c921be7d NC |
16355 | if (! create_register_alias (str, p) |
16356 | && ! create_neon_reg_alias (str, p)) | |
c19d1205 | 16357 | as_bad (_("bad instruction `%s'"), str); |
b99bd4ef | 16358 | |
b99bd4ef NC |
16359 | return; |
16360 | } | |
16361 | ||
278df34e | 16362 | if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated) |
088fa78e KH |
16363 | as_warn (_("s suffix on comparison instruction is deprecated")); |
16364 | ||
037e8744 JB |
16365 | /* The value which unconditional instructions should have in place of the |
16366 | condition field. */ | |
16367 | inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; | |
16368 | ||
c19d1205 | 16369 | if (thumb_mode) |
b99bd4ef | 16370 | { |
e74cfd16 | 16371 | arm_feature_set variant; |
8f06b2d8 PB |
16372 | |
16373 | variant = cpu_variant; | |
16374 | /* Only allow coprocessor instructions on Thumb-2 capable devices. */ | |
e74cfd16 PB |
16375 | if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) |
16376 | ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); | |
c19d1205 | 16377 | /* Check that this instruction is supported for this CPU. */ |
62b3e311 PB |
16378 | if (!opcode->tvariant |
16379 | || (thumb_mode == 1 | |
16380 | && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) | |
b99bd4ef | 16381 | { |
bf3eeda7 | 16382 | as_bad (_("selected processor does not support Thumb mode `%s'"), str); |
b99bd4ef NC |
16383 | return; |
16384 | } | |
c19d1205 ZW |
16385 | if (inst.cond != COND_ALWAYS && !unified_syntax |
16386 | && opcode->tencode != do_t_branch) | |
b99bd4ef | 16387 | { |
c19d1205 | 16388 | as_bad (_("Thumb does not support conditional execution")); |
b99bd4ef NC |
16389 | return; |
16390 | } | |
16391 | ||
752d5da4 | 16392 | if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)) |
076d447c | 16393 | { |
7e806470 | 16394 | if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 |
752d5da4 NC |
16395 | && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) |
16396 | || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) | |
16397 | { | |
16398 | /* Two things are addressed here. | |
16399 | 1) Implicit require narrow instructions on Thumb-1. | |
16400 | This avoids relaxation accidentally introducing Thumb-2 | |
16401 | instructions. | |
16402 | 2) Reject wide instructions in non Thumb-2 cores. */ | |
16403 | if (inst.size_req == 0) | |
16404 | inst.size_req = 2; | |
16405 | else if (inst.size_req == 4) | |
16406 | { | |
bf3eeda7 | 16407 | as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str); |
752d5da4 NC |
16408 | return; |
16409 | } | |
16410 | } | |
076d447c PB |
16411 | } |
16412 | ||
c19d1205 ZW |
16413 | inst.instruction = opcode->tvalue; |
16414 | ||
5be8be5d | 16415 | if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE)) |
e07e6e58 NC |
16416 | { |
16417 | /* Prepare the it_insn_type for those encodings that don't set | |
16418 | it. */ | |
16419 | it_fsm_pre_encode (); | |
c19d1205 | 16420 | |
e07e6e58 NC |
16421 | opcode->tencode (); |
16422 | ||
16423 | it_fsm_post_encode (); | |
16424 | } | |
e27ec89e | 16425 | |
0110f2b8 | 16426 | if (!(inst.error || inst.relax)) |
b99bd4ef | 16427 | { |
9c2799c2 | 16428 | gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); |
c19d1205 ZW |
16429 | inst.size = (inst.instruction > 0xffff ? 4 : 2); |
16430 | if (inst.size_req && inst.size_req != inst.size) | |
b99bd4ef | 16431 | { |
c19d1205 | 16432 | as_bad (_("cannot honor width suffix -- `%s'"), str); |
b99bd4ef NC |
16433 | return; |
16434 | } | |
16435 | } | |
076d447c PB |
16436 | |
16437 | /* Something has gone badly wrong if we try to relax a fixed size | |
16438 | instruction. */ | |
9c2799c2 | 16439 | gas_assert (inst.size_req == 0 || !inst.relax); |
076d447c | 16440 | |
e74cfd16 PB |
16441 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
16442 | *opcode->tvariant); | |
ee065d83 | 16443 | /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly |
708587a4 | 16444 | set those bits when Thumb-2 32-bit instructions are seen. ie. |
7e806470 | 16445 | anything other than bl/blx and v6-M instructions. |
ee065d83 | 16446 | This is overly pessimistic for relaxable instructions. */ |
7e806470 PB |
16447 | if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) |
16448 | || inst.relax) | |
e07e6e58 NC |
16449 | && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr) |
16450 | || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))) | |
e74cfd16 PB |
16451 | ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, |
16452 | arm_ext_v6t2); | |
cd000bff | 16453 | |
88714cb8 DG |
16454 | check_neon_suffixes; |
16455 | ||
cd000bff | 16456 | if (!inst.error) |
c877a2f2 NC |
16457 | { |
16458 | mapping_state (MAP_THUMB); | |
16459 | } | |
c19d1205 | 16460 | } |
3e9e4fcf | 16461 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) |
c19d1205 | 16462 | { |
845b51d6 PB |
16463 | bfd_boolean is_bx; |
16464 | ||
16465 | /* bx is allowed on v5 cores, and sometimes on v4 cores. */ | |
16466 | is_bx = (opcode->aencode == do_bx); | |
16467 | ||
c19d1205 | 16468 | /* Check that this instruction is supported for this CPU. */ |
845b51d6 PB |
16469 | if (!(is_bx && fix_v4bx) |
16470 | && !(opcode->avariant && | |
16471 | ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))) | |
b99bd4ef | 16472 | { |
bf3eeda7 | 16473 | as_bad (_("selected processor does not support ARM mode `%s'"), str); |
c19d1205 | 16474 | return; |
b99bd4ef | 16475 | } |
c19d1205 | 16476 | if (inst.size_req) |
b99bd4ef | 16477 | { |
c19d1205 ZW |
16478 | as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); |
16479 | return; | |
b99bd4ef NC |
16480 | } |
16481 | ||
c19d1205 ZW |
16482 | inst.instruction = opcode->avalue; |
16483 | if (opcode->tag == OT_unconditionalF) | |
16484 | inst.instruction |= 0xF << 28; | |
16485 | else | |
16486 | inst.instruction |= inst.cond << 28; | |
16487 | inst.size = INSN_SIZE; | |
5be8be5d | 16488 | if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE)) |
e07e6e58 NC |
16489 | { |
16490 | it_fsm_pre_encode (); | |
16491 | opcode->aencode (); | |
16492 | it_fsm_post_encode (); | |
16493 | } | |
ee065d83 PB |
16494 | /* Arm mode bx is marked as both v4T and v5 because it's still required |
16495 | on a hypothetical non-thumb v5 core. */ | |
845b51d6 | 16496 | if (is_bx) |
e74cfd16 | 16497 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); |
ee065d83 | 16498 | else |
e74cfd16 PB |
16499 | ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, |
16500 | *opcode->avariant); | |
88714cb8 DG |
16501 | |
16502 | check_neon_suffixes; | |
16503 | ||
cd000bff | 16504 | if (!inst.error) |
c877a2f2 NC |
16505 | { |
16506 | mapping_state (MAP_ARM); | |
16507 | } | |
b99bd4ef | 16508 | } |
3e9e4fcf JB |
16509 | else |
16510 | { | |
16511 | as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " | |
16512 | "-- `%s'"), str); | |
16513 | return; | |
16514 | } | |
c19d1205 ZW |
16515 | output_inst (str); |
16516 | } | |
b99bd4ef | 16517 | |
e07e6e58 NC |
16518 | static void |
16519 | check_it_blocks_finished (void) | |
16520 | { | |
16521 | #ifdef OBJ_ELF | |
16522 | asection *sect; | |
16523 | ||
16524 | for (sect = stdoutput->sections; sect != NULL; sect = sect->next) | |
16525 | if (seg_info (sect)->tc_segment_info_data.current_it.state | |
16526 | == MANUAL_IT_BLOCK) | |
16527 | { | |
16528 | as_warn (_("section '%s' finished with an open IT block."), | |
16529 | sect->name); | |
16530 | } | |
16531 | #else | |
16532 | if (now_it.state == MANUAL_IT_BLOCK) | |
16533 | as_warn (_("file finished with an open IT block.")); | |
16534 | #endif | |
16535 | } | |
16536 | ||
c19d1205 ZW |
16537 | /* Various frobbings of labels and their addresses. */ |
16538 | ||
16539 | void | |
16540 | arm_start_line_hook (void) | |
16541 | { | |
16542 | last_label_seen = NULL; | |
b99bd4ef NC |
16543 | } |
16544 | ||
c19d1205 ZW |
16545 | void |
16546 | arm_frob_label (symbolS * sym) | |
b99bd4ef | 16547 | { |
c19d1205 | 16548 | last_label_seen = sym; |
b99bd4ef | 16549 | |
c19d1205 | 16550 | ARM_SET_THUMB (sym, thumb_mode); |
b99bd4ef | 16551 | |
c19d1205 ZW |
16552 | #if defined OBJ_COFF || defined OBJ_ELF |
16553 | ARM_SET_INTERWORK (sym, support_interwork); | |
16554 | #endif | |
b99bd4ef | 16555 | |
e07e6e58 NC |
16556 | force_automatic_it_block_close (); |
16557 | ||
5f4273c7 | 16558 | /* Note - do not allow local symbols (.Lxxx) to be labelled |
c19d1205 ZW |
16559 | as Thumb functions. This is because these labels, whilst |
16560 | they exist inside Thumb code, are not the entry points for | |
16561 | possible ARM->Thumb calls. Also, these labels can be used | |
16562 | as part of a computed goto or switch statement. eg gcc | |
16563 | can generate code that looks like this: | |
b99bd4ef | 16564 | |
c19d1205 ZW |
16565 | ldr r2, [pc, .Laaa] |
16566 | lsl r3, r3, #2 | |
16567 | ldr r2, [r3, r2] | |
16568 | mov pc, r2 | |
b99bd4ef | 16569 | |
c19d1205 ZW |
16570 | .Lbbb: .word .Lxxx |
16571 | .Lccc: .word .Lyyy | |
16572 | ..etc... | |
16573 | .Laaa: .word Lbbb | |
b99bd4ef | 16574 | |
c19d1205 ZW |
16575 | The first instruction loads the address of the jump table. |
16576 | The second instruction converts a table index into a byte offset. | |
16577 | The third instruction gets the jump address out of the table. | |
16578 | The fourth instruction performs the jump. | |
b99bd4ef | 16579 | |
c19d1205 ZW |
16580 | If the address stored at .Laaa is that of a symbol which has the |
16581 | Thumb_Func bit set, then the linker will arrange for this address | |
16582 | to have the bottom bit set, which in turn would mean that the | |
16583 | address computation performed by the third instruction would end | |
16584 | up with the bottom bit set. Since the ARM is capable of unaligned | |
16585 | word loads, the instruction would then load the incorrect address | |
16586 | out of the jump table, and chaos would ensue. */ | |
16587 | if (label_is_thumb_function_name | |
16588 | && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') | |
16589 | && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
b99bd4ef | 16590 | { |
c19d1205 ZW |
16591 | /* When the address of a Thumb function is taken the bottom |
16592 | bit of that address should be set. This will allow | |
16593 | interworking between Arm and Thumb functions to work | |
16594 | correctly. */ | |
b99bd4ef | 16595 | |
c19d1205 | 16596 | THUMB_SET_FUNC (sym, 1); |
b99bd4ef | 16597 | |
c19d1205 | 16598 | label_is_thumb_function_name = FALSE; |
b99bd4ef | 16599 | } |
07a53e5c | 16600 | |
07a53e5c | 16601 | dwarf2_emit_label (sym); |
b99bd4ef NC |
16602 | } |
16603 | ||
c921be7d | 16604 | bfd_boolean |
c19d1205 | 16605 | arm_data_in_code (void) |
b99bd4ef | 16606 | { |
c19d1205 | 16607 | if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) |
b99bd4ef | 16608 | { |
c19d1205 ZW |
16609 | *input_line_pointer = '/'; |
16610 | input_line_pointer += 5; | |
16611 | *input_line_pointer = 0; | |
c921be7d | 16612 | return TRUE; |
b99bd4ef NC |
16613 | } |
16614 | ||
c921be7d | 16615 | return FALSE; |
b99bd4ef NC |
16616 | } |
16617 | ||
c19d1205 ZW |
16618 | char * |
16619 | arm_canonicalize_symbol_name (char * name) | |
b99bd4ef | 16620 | { |
c19d1205 | 16621 | int len; |
b99bd4ef | 16622 | |
c19d1205 ZW |
16623 | if (thumb_mode && (len = strlen (name)) > 5 |
16624 | && streq (name + len - 5, "/data")) | |
16625 | *(name + len - 5) = 0; | |
b99bd4ef | 16626 | |
c19d1205 | 16627 | return name; |
b99bd4ef | 16628 | } |
c19d1205 ZW |
16629 | \f |
16630 | /* Table of all register names defined by default. The user can | |
16631 | define additional names with .req. Note that all register names | |
16632 | should appear in both upper and lowercase variants. Some registers | |
16633 | also have mixed-case names. */ | |
b99bd4ef | 16634 | |
dcbf9037 | 16635 | #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } |
c19d1205 | 16636 | #define REGNUM(p,n,t) REGDEF(p##n, n, t) |
5287ad62 | 16637 | #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) |
c19d1205 ZW |
16638 | #define REGSET(p,t) \ |
16639 | REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ | |
16640 | REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ | |
16641 | REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ | |
16642 | REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) | |
5287ad62 JB |
16643 | #define REGSETH(p,t) \ |
16644 | REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ | |
16645 | REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ | |
16646 | REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ | |
16647 | REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) | |
16648 | #define REGSET2(p,t) \ | |
16649 | REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ | |
16650 | REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ | |
16651 | REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ | |
16652 | REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) | |
90ec0d68 MGD |
16653 | #define SPLRBANK(base,bank,t) \ |
16654 | REGDEF(lr_##bank, 768|((base+0)<<16), t), \ | |
16655 | REGDEF(sp_##bank, 768|((base+1)<<16), t), \ | |
16656 | REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \ | |
16657 | REGDEF(LR_##bank, 768|((base+0)<<16), t), \ | |
16658 | REGDEF(SP_##bank, 768|((base+1)<<16), t), \ | |
16659 | REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t) | |
7ed4c4c5 | 16660 | |
c19d1205 | 16661 | static const struct reg_entry reg_names[] = |
7ed4c4c5 | 16662 | { |
c19d1205 ZW |
16663 | /* ARM integer registers. */ |
16664 | REGSET(r, RN), REGSET(R, RN), | |
7ed4c4c5 | 16665 | |
c19d1205 ZW |
16666 | /* ATPCS synonyms. */ |
16667 | REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), | |
16668 | REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), | |
16669 | REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), | |
7ed4c4c5 | 16670 | |
c19d1205 ZW |
16671 | REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), |
16672 | REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), | |
16673 | REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), | |
7ed4c4c5 | 16674 | |
c19d1205 ZW |
16675 | /* Well-known aliases. */ |
16676 | REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), | |
16677 | REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), | |
16678 | ||
16679 | REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), | |
16680 | REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), | |
16681 | ||
16682 | /* Coprocessor numbers. */ | |
16683 | REGSET(p, CP), REGSET(P, CP), | |
16684 | ||
16685 | /* Coprocessor register numbers. The "cr" variants are for backward | |
16686 | compatibility. */ | |
16687 | REGSET(c, CN), REGSET(C, CN), | |
16688 | REGSET(cr, CN), REGSET(CR, CN), | |
16689 | ||
90ec0d68 MGD |
16690 | /* ARM banked registers. */ |
16691 | REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB), | |
16692 | REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB), | |
16693 | REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB), | |
16694 | REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB), | |
16695 | REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB), | |
16696 | REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB), | |
16697 | REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB), | |
16698 | ||
16699 | REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB), | |
16700 | REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB), | |
16701 | REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB), | |
16702 | REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB), | |
16703 | REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB), | |
16704 | REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB), | |
16705 | REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB), | |
16706 | REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB), | |
16707 | ||
16708 | SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB), | |
16709 | SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB), | |
16710 | SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB), | |
16711 | SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB), | |
16712 | SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB), | |
16713 | REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB), | |
16714 | REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB), | |
16715 | REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB), | |
16716 | REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB), | |
16717 | ||
c19d1205 ZW |
16718 | /* FPA registers. */ |
16719 | REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), | |
16720 | REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), | |
16721 | ||
16722 | REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), | |
16723 | REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), | |
16724 | ||
16725 | /* VFP SP registers. */ | |
5287ad62 JB |
16726 | REGSET(s,VFS), REGSET(S,VFS), |
16727 | REGSETH(s,VFS), REGSETH(S,VFS), | |
c19d1205 ZW |
16728 | |
16729 | /* VFP DP Registers. */ | |
5287ad62 JB |
16730 | REGSET(d,VFD), REGSET(D,VFD), |
16731 | /* Extra Neon DP registers. */ | |
16732 | REGSETH(d,VFD), REGSETH(D,VFD), | |
16733 | ||
16734 | /* Neon QP registers. */ | |
16735 | REGSET2(q,NQ), REGSET2(Q,NQ), | |
c19d1205 ZW |
16736 | |
16737 | /* VFP control registers. */ | |
16738 | REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), | |
16739 | REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), | |
cd2cf30b PB |
16740 | REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), |
16741 | REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), | |
16742 | REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), | |
16743 | REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), | |
c19d1205 ZW |
16744 | |
16745 | /* Maverick DSP coprocessor registers. */ | |
16746 | REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), | |
16747 | REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), | |
16748 | ||
16749 | REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), | |
16750 | REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), | |
16751 | REGDEF(dspsc,0,DSPSC), | |
16752 | ||
16753 | REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), | |
16754 | REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), | |
16755 | REGDEF(DSPSC,0,DSPSC), | |
16756 | ||
16757 | /* iWMMXt data registers - p0, c0-15. */ | |
16758 | REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), | |
16759 | ||
16760 | /* iWMMXt control registers - p1, c0-3. */ | |
16761 | REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), | |
16762 | REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), | |
16763 | REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), | |
16764 | REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), | |
16765 | ||
16766 | /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ | |
16767 | REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), | |
16768 | REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), | |
16769 | REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), | |
16770 | REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), | |
16771 | ||
16772 | /* XScale accumulator registers. */ | |
16773 | REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), | |
16774 | }; | |
16775 | #undef REGDEF | |
16776 | #undef REGNUM | |
16777 | #undef REGSET | |
7ed4c4c5 | 16778 | |
c19d1205 ZW |
16779 | /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled |
16780 | within psr_required_here. */ | |
16781 | static const struct asm_psr psrs[] = | |
16782 | { | |
16783 | /* Backward compatibility notation. Note that "all" is no longer | |
16784 | truly all possible PSR bits. */ | |
16785 | {"all", PSR_c | PSR_f}, | |
16786 | {"flg", PSR_f}, | |
16787 | {"ctl", PSR_c}, | |
16788 | ||
16789 | /* Individual flags. */ | |
16790 | {"f", PSR_f}, | |
16791 | {"c", PSR_c}, | |
16792 | {"x", PSR_x}, | |
16793 | {"s", PSR_s}, | |
59b42a0d | 16794 | |
c19d1205 ZW |
16795 | /* Combinations of flags. */ |
16796 | {"fs", PSR_f | PSR_s}, | |
16797 | {"fx", PSR_f | PSR_x}, | |
16798 | {"fc", PSR_f | PSR_c}, | |
16799 | {"sf", PSR_s | PSR_f}, | |
16800 | {"sx", PSR_s | PSR_x}, | |
16801 | {"sc", PSR_s | PSR_c}, | |
16802 | {"xf", PSR_x | PSR_f}, | |
16803 | {"xs", PSR_x | PSR_s}, | |
16804 | {"xc", PSR_x | PSR_c}, | |
16805 | {"cf", PSR_c | PSR_f}, | |
16806 | {"cs", PSR_c | PSR_s}, | |
16807 | {"cx", PSR_c | PSR_x}, | |
16808 | {"fsx", PSR_f | PSR_s | PSR_x}, | |
16809 | {"fsc", PSR_f | PSR_s | PSR_c}, | |
16810 | {"fxs", PSR_f | PSR_x | PSR_s}, | |
16811 | {"fxc", PSR_f | PSR_x | PSR_c}, | |
16812 | {"fcs", PSR_f | PSR_c | PSR_s}, | |
16813 | {"fcx", PSR_f | PSR_c | PSR_x}, | |
16814 | {"sfx", PSR_s | PSR_f | PSR_x}, | |
16815 | {"sfc", PSR_s | PSR_f | PSR_c}, | |
16816 | {"sxf", PSR_s | PSR_x | PSR_f}, | |
16817 | {"sxc", PSR_s | PSR_x | PSR_c}, | |
16818 | {"scf", PSR_s | PSR_c | PSR_f}, | |
16819 | {"scx", PSR_s | PSR_c | PSR_x}, | |
16820 | {"xfs", PSR_x | PSR_f | PSR_s}, | |
16821 | {"xfc", PSR_x | PSR_f | PSR_c}, | |
16822 | {"xsf", PSR_x | PSR_s | PSR_f}, | |
16823 | {"xsc", PSR_x | PSR_s | PSR_c}, | |
16824 | {"xcf", PSR_x | PSR_c | PSR_f}, | |
16825 | {"xcs", PSR_x | PSR_c | PSR_s}, | |
16826 | {"cfs", PSR_c | PSR_f | PSR_s}, | |
16827 | {"cfx", PSR_c | PSR_f | PSR_x}, | |
16828 | {"csf", PSR_c | PSR_s | PSR_f}, | |
16829 | {"csx", PSR_c | PSR_s | PSR_x}, | |
16830 | {"cxf", PSR_c | PSR_x | PSR_f}, | |
16831 | {"cxs", PSR_c | PSR_x | PSR_s}, | |
16832 | {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, | |
16833 | {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, | |
16834 | {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, | |
16835 | {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, | |
16836 | {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, | |
16837 | {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, | |
16838 | {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, | |
16839 | {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, | |
16840 | {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, | |
16841 | {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, | |
16842 | {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, | |
16843 | {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, | |
16844 | {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, | |
16845 | {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, | |
16846 | {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, | |
16847 | {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, | |
16848 | {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, | |
16849 | {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, | |
16850 | {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, | |
16851 | {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, | |
16852 | {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, | |
16853 | {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, | |
16854 | {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, | |
16855 | {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, | |
16856 | }; | |
16857 | ||
62b3e311 PB |
16858 | /* Table of V7M psr names. */ |
16859 | static const struct asm_psr v7m_psrs[] = | |
16860 | { | |
2b744c99 PB |
16861 | {"apsr", 0 }, {"APSR", 0 }, |
16862 | {"iapsr", 1 }, {"IAPSR", 1 }, | |
16863 | {"eapsr", 2 }, {"EAPSR", 2 }, | |
16864 | {"psr", 3 }, {"PSR", 3 }, | |
16865 | {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, | |
16866 | {"ipsr", 5 }, {"IPSR", 5 }, | |
16867 | {"epsr", 6 }, {"EPSR", 6 }, | |
16868 | {"iepsr", 7 }, {"IEPSR", 7 }, | |
16869 | {"msp", 8 }, {"MSP", 8 }, | |
16870 | {"psp", 9 }, {"PSP", 9 }, | |
16871 | {"primask", 16}, {"PRIMASK", 16}, | |
16872 | {"basepri", 17}, {"BASEPRI", 17}, | |
00bbc0bd NC |
16873 | {"basepri_max", 18}, {"BASEPRI_MAX", 18}, |
16874 | {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */ | |
2b744c99 PB |
16875 | {"faultmask", 19}, {"FAULTMASK", 19}, |
16876 | {"control", 20}, {"CONTROL", 20} | |
62b3e311 PB |
16877 | }; |
16878 | ||
c19d1205 ZW |
16879 | /* Table of all shift-in-operand names. */ |
16880 | static const struct asm_shift_name shift_names [] = | |
b99bd4ef | 16881 | { |
c19d1205 ZW |
16882 | { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, |
16883 | { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, | |
16884 | { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, | |
16885 | { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, | |
16886 | { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, | |
16887 | { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } | |
16888 | }; | |
b99bd4ef | 16889 | |
c19d1205 ZW |
16890 | /* Table of all explicit relocation names. */ |
16891 | #ifdef OBJ_ELF | |
16892 | static struct reloc_entry reloc_names[] = | |
16893 | { | |
16894 | { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, | |
16895 | { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, | |
16896 | { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, | |
16897 | { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, | |
16898 | { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, | |
16899 | { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, | |
16900 | { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, | |
16901 | { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, | |
16902 | { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, | |
16903 | { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, | |
b43420e6 | 16904 | { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}, |
0855e32b NS |
16905 | { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}, |
16906 | { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC}, | |
16907 | { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC}, | |
16908 | { "tlscall", BFD_RELOC_ARM_TLS_CALL}, | |
16909 | { "TLSCALL", BFD_RELOC_ARM_TLS_CALL}, | |
16910 | { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ}, | |
16911 | { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ} | |
c19d1205 ZW |
16912 | }; |
16913 | #endif | |
b99bd4ef | 16914 | |
c19d1205 ZW |
16915 | /* Table of all conditional affixes. 0xF is not defined as a condition code. */ |
16916 | static const struct asm_cond conds[] = | |
16917 | { | |
16918 | {"eq", 0x0}, | |
16919 | {"ne", 0x1}, | |
16920 | {"cs", 0x2}, {"hs", 0x2}, | |
16921 | {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, | |
16922 | {"mi", 0x4}, | |
16923 | {"pl", 0x5}, | |
16924 | {"vs", 0x6}, | |
16925 | {"vc", 0x7}, | |
16926 | {"hi", 0x8}, | |
16927 | {"ls", 0x9}, | |
16928 | {"ge", 0xa}, | |
16929 | {"lt", 0xb}, | |
16930 | {"gt", 0xc}, | |
16931 | {"le", 0xd}, | |
16932 | {"al", 0xe} | |
16933 | }; | |
bfae80f2 | 16934 | |
62b3e311 PB |
16935 | static struct asm_barrier_opt barrier_opt_names[] = |
16936 | { | |
52e7f43d RE |
16937 | { "sy", 0xf }, { "SY", 0xf }, |
16938 | { "un", 0x7 }, { "UN", 0x7 }, | |
16939 | { "st", 0xe }, { "ST", 0xe }, | |
16940 | { "unst", 0x6 }, { "UNST", 0x6 }, | |
16941 | { "ish", 0xb }, { "ISH", 0xb }, | |
16942 | { "sh", 0xb }, { "SH", 0xb }, | |
16943 | { "ishst", 0xa }, { "ISHST", 0xa }, | |
16944 | { "shst", 0xa }, { "SHST", 0xa }, | |
16945 | { "nsh", 0x7 }, { "NSH", 0x7 }, | |
16946 | { "nshst", 0x6 }, { "NSHST", 0x6 }, | |
16947 | { "osh", 0x3 }, { "OSH", 0x3 }, | |
16948 | { "oshst", 0x2 }, { "OSHST", 0x2 } | |
62b3e311 PB |
16949 | }; |
16950 | ||
c19d1205 ZW |
16951 | /* Table of ARM-format instructions. */ |
16952 | ||
16953 | /* Macros for gluing together operand strings. N.B. In all cases | |
16954 | other than OPS0, the trailing OP_stop comes from default | |
16955 | zero-initialization of the unspecified elements of the array. */ | |
16956 | #define OPS0() { OP_stop, } | |
16957 | #define OPS1(a) { OP_##a, } | |
16958 | #define OPS2(a,b) { OP_##a,OP_##b, } | |
16959 | #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } | |
16960 | #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } | |
16961 | #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } | |
16962 | #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } | |
16963 | ||
5be8be5d DG |
16964 | /* These macros are similar to the OPSn, but do not prepend the OP_ prefix. |
16965 | This is useful when mixing operands for ARM and THUMB, i.e. using the | |
16966 | MIX_ARM_THUMB_OPERANDS macro. | |
16967 | In order to use these macros, prefix the number of operands with _ | |
16968 | e.g. _3. */ | |
16969 | #define OPS_1(a) { a, } | |
16970 | #define OPS_2(a,b) { a,b, } | |
16971 | #define OPS_3(a,b,c) { a,b,c, } | |
16972 | #define OPS_4(a,b,c,d) { a,b,c,d, } | |
16973 | #define OPS_5(a,b,c,d,e) { a,b,c,d,e, } | |
16974 | #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, } | |
16975 | ||
c19d1205 ZW |
16976 | /* These macros abstract out the exact format of the mnemonic table and |
16977 | save some repeated characters. */ | |
16978 | ||
16979 | /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ | |
16980 | #define TxCE(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16981 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16982 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
16983 | |
16984 | /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for | |
16985 | a T_MNEM_xyz enumerator. */ | |
16986 | #define TCE(mnem, aop, top, nops, ops, ae, te) \ | |
e07e6e58 | 16987 | TxCE (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 16988 | #define tCE(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 16989 | TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
16990 | |
16991 | /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional | |
16992 | infix after the third character. */ | |
16993 | #define TxC3(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 16994 | { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ |
1887dd22 | 16995 | THUMB_VARIANT, do_##ae, do_##te } |
088fa78e | 16996 | #define TxC3w(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 16997 | { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ |
088fa78e | 16998 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 | 16999 | #define TC3(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 17000 | TxC3 (mnem, aop, 0x##top, nops, ops, ae, te) |
088fa78e | 17001 | #define TC3w(mnem, aop, top, nops, ops, ae, te) \ |
e07e6e58 | 17002 | TxC3w (mnem, aop, 0x##top, nops, ops, ae, te) |
c19d1205 | 17003 | #define tC3(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 17004 | TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
088fa78e | 17005 | #define tC3w(mnem, aop, top, nops, ops, ae, te) \ |
21d799b5 | 17006 | TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
17007 | |
17008 | /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to | |
17009 | appear in the condition table. */ | |
17010 | #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ | |
21d799b5 | 17011 | { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ |
1887dd22 | 17012 | 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
17013 | |
17014 | #define TxCM(m1, m2, op, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
17015 | TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \ |
17016 | TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \ | |
17017 | TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \ | |
17018 | TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \ | |
17019 | TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \ | |
17020 | TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \ | |
17021 | TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \ | |
17022 | TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \ | |
17023 | TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \ | |
17024 | TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \ | |
17025 | TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \ | |
17026 | TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \ | |
17027 | TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \ | |
17028 | TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \ | |
17029 | TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \ | |
17030 | TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \ | |
17031 | TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \ | |
17032 | TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \ | |
17033 | TxCM_ (m1, al, m2, op, top, nops, ops, ae, te) | |
c19d1205 ZW |
17034 | |
17035 | #define TCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
e07e6e58 NC |
17036 | TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te) |
17037 | #define tCM(m1,m2, aop, top, nops, ops, ae, te) \ | |
21d799b5 | 17038 | TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te) |
c19d1205 ZW |
17039 | |
17040 | /* Mnemonic that cannot be conditionalized. The ARM condition-code | |
dfa9f0d5 PB |
17041 | field is still 0xE. Many of the Thumb variants can be executed |
17042 | conditionally, so this is checked separately. */ | |
c19d1205 | 17043 | #define TUE(mnem, op, top, nops, ops, ae, te) \ |
21d799b5 | 17044 | { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 17045 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
17046 | |
17047 | /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM | |
17048 | condition code field. */ | |
17049 | #define TUF(mnem, op, top, nops, ops, ae, te) \ | |
21d799b5 | 17050 | { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ |
1887dd22 | 17051 | THUMB_VARIANT, do_##ae, do_##te } |
c19d1205 ZW |
17052 | |
17053 | /* ARM-only variants of all the above. */ | |
6a86118a | 17054 | #define CE(mnem, op, nops, ops, ae) \ |
21d799b5 | 17055 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
6a86118a NC |
17056 | |
17057 | #define C3(mnem, op, nops, ops, ae) \ | |
17058 | { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } | |
17059 | ||
e3cb604e PB |
17060 | /* Legacy mnemonics that always have conditional infix after the third |
17061 | character. */ | |
17062 | #define CL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17063 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
17064 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
17065 | ||
8f06b2d8 PB |
17066 | /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ |
17067 | #define cCE(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17068 | { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 17069 | |
e3cb604e PB |
17070 | /* Legacy coprocessor instructions where conditional infix and conditional |
17071 | suffix are ambiguous. For consistency this includes all FPA instructions, | |
17072 | not just the potentially ambiguous ones. */ | |
17073 | #define cCL(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17074 | { mnem, OPS##nops ops, OT_cinfix3_legacy, \ |
e3cb604e PB |
17075 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
17076 | ||
17077 | /* Coprocessor, takes either a suffix or a position-3 infix | |
17078 | (for an FPA corner case). */ | |
17079 | #define C3E(mnem, op, nops, ops, ae) \ | |
21d799b5 | 17080 | { mnem, OPS##nops ops, OT_csuf_or_in3, \ |
e3cb604e | 17081 | 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } |
8f06b2d8 | 17082 | |
6a86118a | 17083 | #define xCM_(m1, m2, m3, op, nops, ops, ae) \ |
21d799b5 NC |
17084 | { m1 #m2 m3, OPS##nops ops, \ |
17085 | sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \ | |
6a86118a NC |
17086 | 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } |
17087 | ||
17088 | #define CM(m1, m2, op, nops, ops, ae) \ | |
e07e6e58 NC |
17089 | xCM_ (m1, , m2, op, nops, ops, ae), \ |
17090 | xCM_ (m1, eq, m2, op, nops, ops, ae), \ | |
17091 | xCM_ (m1, ne, m2, op, nops, ops, ae), \ | |
17092 | xCM_ (m1, cs, m2, op, nops, ops, ae), \ | |
17093 | xCM_ (m1, hs, m2, op, nops, ops, ae), \ | |
17094 | xCM_ (m1, cc, m2, op, nops, ops, ae), \ | |
17095 | xCM_ (m1, ul, m2, op, nops, ops, ae), \ | |
17096 | xCM_ (m1, lo, m2, op, nops, ops, ae), \ | |
17097 | xCM_ (m1, mi, m2, op, nops, ops, ae), \ | |
17098 | xCM_ (m1, pl, m2, op, nops, ops, ae), \ | |
17099 | xCM_ (m1, vs, m2, op, nops, ops, ae), \ | |
17100 | xCM_ (m1, vc, m2, op, nops, ops, ae), \ | |
17101 | xCM_ (m1, hi, m2, op, nops, ops, ae), \ | |
17102 | xCM_ (m1, ls, m2, op, nops, ops, ae), \ | |
17103 | xCM_ (m1, ge, m2, op, nops, ops, ae), \ | |
17104 | xCM_ (m1, lt, m2, op, nops, ops, ae), \ | |
17105 | xCM_ (m1, gt, m2, op, nops, ops, ae), \ | |
17106 | xCM_ (m1, le, m2, op, nops, ops, ae), \ | |
17107 | xCM_ (m1, al, m2, op, nops, ops, ae) | |
6a86118a NC |
17108 | |
17109 | #define UE(mnem, op, nops, ops, ae) \ | |
17110 | { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
17111 | ||
17112 | #define UF(mnem, op, nops, ops, ae) \ | |
17113 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } | |
17114 | ||
5287ad62 JB |
17115 | /* Neon data-processing. ARM versions are unconditional with cond=0xf. |
17116 | The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we | |
17117 | use the same encoding function for each. */ | |
17118 | #define NUF(mnem, op, nops, ops, enc) \ | |
17119 | { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ | |
17120 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } | |
17121 | ||
17122 | /* Neon data processing, version which indirects through neon_enc_tab for | |
17123 | the various overloaded versions of opcodes. */ | |
17124 | #define nUF(mnem, op, nops, ops, enc) \ | |
21d799b5 | 17125 | { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
17126 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
17127 | ||
17128 | /* Neon insn with conditional suffix for the ARM version, non-overloaded | |
17129 | version. */ | |
037e8744 JB |
17130 | #define NCE_tag(mnem, op, nops, ops, enc, tag) \ |
17131 | { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ | |
5287ad62 JB |
17132 | THUMB_VARIANT, do_##enc, do_##enc } |
17133 | ||
037e8744 | 17134 | #define NCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 17135 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
17136 | |
17137 | #define NCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 17138 | NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 17139 | |
5287ad62 | 17140 | /* Neon insn with conditional suffix for the ARM version, overloaded types. */ |
037e8744 | 17141 | #define nCE_tag(mnem, op, nops, ops, enc, tag) \ |
21d799b5 | 17142 | { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \ |
5287ad62 JB |
17143 | ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } |
17144 | ||
037e8744 | 17145 | #define nCE(mnem, op, nops, ops, enc) \ |
e07e6e58 | 17146 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffix) |
037e8744 JB |
17147 | |
17148 | #define nCEF(mnem, op, nops, ops, enc) \ | |
e07e6e58 | 17149 | nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF) |
037e8744 | 17150 | |
c19d1205 ZW |
17151 | #define do_0 0 |
17152 | ||
c19d1205 | 17153 | static const struct asm_opcode insns[] = |
bfae80f2 | 17154 | { |
e74cfd16 PB |
17155 | #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ |
17156 | #define THUMB_VARIANT &arm_ext_v4t | |
21d799b5 NC |
17157 | tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c), |
17158 | tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c), | |
17159 | tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c), | |
17160 | tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c), | |
17161 | tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub), | |
17162 | tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub), | |
17163 | tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub), | |
17164 | tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub), | |
17165 | tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c), | |
17166 | tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c), | |
17167 | tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3), | |
17168 | tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3), | |
17169 | tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c), | |
17170 | tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c), | |
17171 | tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3), | |
17172 | tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3), | |
c19d1205 ZW |
17173 | |
17174 | /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism | |
17175 | for setting PSR flag bits. They are obsolete in V6 and do not | |
17176 | have Thumb equivalents. */ | |
21d799b5 NC |
17177 | tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), |
17178 | tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst), | |
17179 | CL("tstp", 110f000, 2, (RR, SH), cmp), | |
17180 | tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
17181 | tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp), | |
17182 | CL("cmpp", 150f000, 2, (RR, SH), cmp), | |
17183 | tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
17184 | tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst), | |
17185 | CL("cmnp", 170f000, 2, (RR, SH), cmp), | |
17186 | ||
17187 | tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp), | |
17188 | tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp), | |
17189 | tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst), | |
17190 | tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst), | |
17191 | ||
17192 | tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), | |
5be8be5d DG |
17193 | tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), |
17194 | tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR, | |
17195 | OP_RRnpc), | |
17196 | OP_ADDRGLDR),ldst, t_ldst), | |
17197 | tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst), | |
21d799b5 NC |
17198 | |
17199 | tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17200 | tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17201 | tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17202 | tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17203 | tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17204 | tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
17205 | ||
17206 | TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi), | |
17207 | TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi), | |
17208 | tCE("b", a000000, _b, 1, (EXPr), branch, t_branch), | |
17209 | TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23), | |
bfae80f2 | 17210 | |
c19d1205 | 17211 | /* Pseudo ops. */ |
21d799b5 | 17212 | tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr), |
2fc8bdac | 17213 | C3(adrl, 28f0000, 2, (RR, EXP), adrl), |
21d799b5 | 17214 | tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop), |
c19d1205 ZW |
17215 | |
17216 | /* Thumb-compatibility pseudo ops. */ | |
21d799b5 NC |
17217 | tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift), |
17218 | tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift), | |
17219 | tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift), | |
17220 | tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift), | |
17221 | tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift), | |
17222 | tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift), | |
17223 | tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift), | |
17224 | tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift), | |
17225 | tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg), | |
17226 | tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg), | |
17227 | tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop), | |
17228 | tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop), | |
c19d1205 | 17229 | |
16a4cf17 | 17230 | /* These may simplify to neg. */ |
21d799b5 NC |
17231 | TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), |
17232 | TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), | |
16a4cf17 | 17233 | |
c921be7d NC |
17234 | #undef THUMB_VARIANT |
17235 | #define THUMB_VARIANT & arm_ext_v6 | |
17236 | ||
21d799b5 | 17237 | TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), |
c19d1205 ZW |
17238 | |
17239 | /* V1 instructions with no Thumb analogue prior to V6T2. */ | |
c921be7d NC |
17240 | #undef THUMB_VARIANT |
17241 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17242 | ||
21d799b5 NC |
17243 | TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), |
17244 | TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), | |
17245 | CL("teqp", 130f000, 2, (RR, SH), cmp), | |
c19d1205 | 17246 | |
5be8be5d DG |
17247 | TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), |
17248 | TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
17249 | TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt), | |
17250 | TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt), | |
c19d1205 | 17251 | |
21d799b5 NC |
17252 | TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
17253 | TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 | 17254 | |
21d799b5 NC |
17255 | TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), |
17256 | TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), | |
c19d1205 ZW |
17257 | |
17258 | /* V1 instructions with no Thumb analogue at all. */ | |
21d799b5 | 17259 | CE("rsc", 0e00000, 3, (RR, oRR, SH), arit), |
c19d1205 ZW |
17260 | C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), |
17261 | ||
17262 | C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), | |
17263 | C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), | |
17264 | C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), | |
17265 | C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), | |
17266 | C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), | |
17267 | C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), | |
17268 | C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), | |
17269 | C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), | |
17270 | ||
c921be7d NC |
17271 | #undef ARM_VARIANT |
17272 | #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */ | |
17273 | #undef THUMB_VARIANT | |
17274 | #define THUMB_VARIANT & arm_ext_v4t | |
17275 | ||
21d799b5 NC |
17276 | tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), |
17277 | tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), | |
c19d1205 | 17278 | |
c921be7d NC |
17279 | #undef THUMB_VARIANT |
17280 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17281 | ||
21d799b5 | 17282 | TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
c19d1205 ZW |
17283 | C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), |
17284 | ||
17285 | /* Generic coprocessor instructions. */ | |
21d799b5 NC |
17286 | TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), |
17287 | TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17288 | TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17289 | TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17290 | TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17291 | TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
db472d6f | 17292 | TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), |
c19d1205 | 17293 | |
c921be7d NC |
17294 | #undef ARM_VARIANT |
17295 | #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */ | |
17296 | ||
21d799b5 | 17297 | CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
c19d1205 ZW |
17298 | C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), |
17299 | ||
c921be7d NC |
17300 | #undef ARM_VARIANT |
17301 | #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */ | |
17302 | #undef THUMB_VARIANT | |
17303 | #define THUMB_VARIANT & arm_ext_msr | |
17304 | ||
d2cd1205 JB |
17305 | TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs), |
17306 | TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr), | |
c19d1205 | 17307 | |
c921be7d NC |
17308 | #undef ARM_VARIANT |
17309 | #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */ | |
17310 | #undef THUMB_VARIANT | |
17311 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17312 | ||
21d799b5 NC |
17313 | TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), |
17314 | CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17315 | TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17316 | CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17317 | TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17318 | CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
17319 | TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), | |
17320 | CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), | |
c19d1205 | 17321 | |
c921be7d NC |
17322 | #undef ARM_VARIANT |
17323 | #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */ | |
17324 | #undef THUMB_VARIANT | |
17325 | #define THUMB_VARIANT & arm_ext_v4t | |
17326 | ||
5be8be5d DG |
17327 | tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), |
17328 | tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17329 | tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17330 | tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17331 | tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
17332 | tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst), | |
c19d1205 | 17333 | |
c921be7d NC |
17334 | #undef ARM_VARIANT |
17335 | #define ARM_VARIANT & arm_ext_v4t_5 | |
17336 | ||
c19d1205 ZW |
17337 | /* ARM Architecture 4T. */ |
17338 | /* Note: bx (and blx) are required on V5, even if the processor does | |
17339 | not support Thumb. */ | |
21d799b5 | 17340 | TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx), |
c19d1205 | 17341 | |
c921be7d NC |
17342 | #undef ARM_VARIANT |
17343 | #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */ | |
17344 | #undef THUMB_VARIANT | |
17345 | #define THUMB_VARIANT & arm_ext_v5t | |
17346 | ||
c19d1205 ZW |
17347 | /* Note: blx has 2 variants; the .value coded here is for |
17348 | BLX(2). Only this variant has conditional execution. */ | |
21d799b5 NC |
17349 | TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx), |
17350 | TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), | |
c19d1205 | 17351 | |
c921be7d NC |
17352 | #undef THUMB_VARIANT |
17353 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17354 | ||
21d799b5 NC |
17355 | TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), |
17356 | TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17357 | TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17358 | TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17359 | TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), | |
17360 | TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), | |
17361 | TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
17362 | TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), | |
c19d1205 | 17363 | |
c921be7d NC |
17364 | #undef ARM_VARIANT |
17365 | #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */ | |
9e3c6df6 PB |
17366 | #undef THUMB_VARIANT |
17367 | #define THUMB_VARIANT &arm_ext_v5exp | |
c921be7d | 17368 | |
21d799b5 NC |
17369 | TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
17370 | TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
17371 | TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
17372 | TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 17373 | |
21d799b5 NC |
17374 | TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), |
17375 | TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), | |
c19d1205 | 17376 | |
21d799b5 NC |
17377 | TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), |
17378 | TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
17379 | TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
17380 | TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), | |
c19d1205 | 17381 | |
21d799b5 NC |
17382 | TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
17383 | TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17384 | TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17385 | TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 17386 | |
21d799b5 NC |
17387 | TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), |
17388 | TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
c19d1205 | 17389 | |
03ee1b7f NC |
17390 | TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), |
17391 | TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
17392 | TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
17393 | TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), | |
c19d1205 | 17394 | |
c921be7d NC |
17395 | #undef ARM_VARIANT |
17396 | #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ | |
9e3c6df6 PB |
17397 | #undef THUMB_VARIANT |
17398 | #define THUMB_VARIANT &arm_ext_v6t2 | |
c921be7d | 17399 | |
21d799b5 | 17400 | TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld), |
5be8be5d DG |
17401 | TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS), |
17402 | ldrd, t_ldstd), | |
17403 | TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp, | |
17404 | ADDRGLDRS), ldrd, t_ldstd), | |
c19d1205 | 17405 | |
21d799b5 NC |
17406 | TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
17407 | TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
c19d1205 | 17408 | |
c921be7d NC |
17409 | #undef ARM_VARIANT |
17410 | #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */ | |
17411 | ||
21d799b5 | 17412 | TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), |
c19d1205 | 17413 | |
c921be7d NC |
17414 | #undef ARM_VARIANT |
17415 | #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */ | |
17416 | #undef THUMB_VARIANT | |
17417 | #define THUMB_VARIANT & arm_ext_v6 | |
17418 | ||
21d799b5 NC |
17419 | TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), |
17420 | TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), | |
17421 | tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17422 | tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17423 | tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), | |
17424 | tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17425 | tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17426 | tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17427 | tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17428 | TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), | |
c19d1205 | 17429 | |
c921be7d NC |
17430 | #undef THUMB_VARIANT |
17431 | #define THUMB_VARIANT & arm_ext_v6t2 | |
17432 | ||
5be8be5d DG |
17433 | TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), |
17434 | TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
17435 | strex, t_strex), | |
21d799b5 NC |
17436 | TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), |
17437 | TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), | |
62b3e311 | 17438 | |
21d799b5 NC |
17439 | TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), |
17440 | TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), | |
62b3e311 | 17441 | |
9e3c6df6 | 17442 | /* ARM V6 not included in V7M. */ |
c921be7d NC |
17443 | #undef THUMB_VARIANT |
17444 | #define THUMB_VARIANT & arm_ext_v6_notm | |
9e3c6df6 PB |
17445 | TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe), |
17446 | UF(rfeib, 9900a00, 1, (RRw), rfe), | |
17447 | UF(rfeda, 8100a00, 1, (RRw), rfe), | |
17448 | TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
17449 | TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe), | |
17450 | UF(rfefa, 9900a00, 1, (RRw), rfe), | |
17451 | UF(rfeea, 8100a00, 1, (RRw), rfe), | |
17452 | TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe), | |
17453 | TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), | |
17454 | UF(srsib, 9c00500, 2, (oRRw, I31w), srs), | |
17455 | UF(srsda, 8400500, 2, (oRRw, I31w), srs), | |
17456 | TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs), | |
c921be7d | 17457 | |
9e3c6df6 PB |
17458 | /* ARM V6 not included in V7M (eg. integer SIMD). */ |
17459 | #undef THUMB_VARIANT | |
17460 | #define THUMB_VARIANT & arm_ext_v6_dsp | |
21d799b5 NC |
17461 | TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps), |
17462 | TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), | |
17463 | TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), | |
17464 | TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17465 | TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17466 | TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17467 | /* Old name for QASX. */ |
21d799b5 NC |
17468 | TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17469 | TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17470 | /* Old name for QSAX. */ |
21d799b5 NC |
17471 | TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17472 | TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17473 | TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17474 | TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17475 | TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17476 | TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17477 | /* Old name for SASX. */ |
21d799b5 NC |
17478 | TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17479 | TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17480 | TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17481 | TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17482 | /* Old name for SHASX. */ |
21d799b5 NC |
17483 | TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17484 | TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17485 | /* Old name for SHSAX. */ |
21d799b5 NC |
17486 | TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17487 | TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17488 | TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17489 | TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17490 | /* Old name for SSAX. */ |
21d799b5 NC |
17491 | TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17492 | TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17493 | TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17494 | TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17495 | TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17496 | TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17497 | /* Old name for UASX. */ |
21d799b5 NC |
17498 | TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17499 | TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17500 | TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17501 | TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17502 | /* Old name for UHASX. */ |
21d799b5 NC |
17503 | TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17504 | TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17505 | /* Old name for UHSAX. */ |
21d799b5 NC |
17506 | TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17507 | TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17508 | TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17509 | TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17510 | TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17511 | TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17512 | /* Old name for UQASX. */ |
21d799b5 NC |
17513 | TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17514 | TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17515 | /* Old name for UQSAX. */ |
21d799b5 NC |
17516 | TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17517 | TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17518 | TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17519 | TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17520 | TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
4f80ef3e | 17521 | /* Old name for USAX. */ |
21d799b5 NC |
17522 | TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), |
17523 | TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
21d799b5 NC |
17524 | TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), |
17525 | TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17526 | TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17527 | TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17528 | TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17529 | TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17530 | TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), | |
17531 | TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), | |
17532 | TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), | |
17533 | TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17534 | TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17535 | TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17536 | TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17537 | TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17538 | TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17539 | TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17540 | TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), | |
17541 | TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17542 | TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17543 | TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17544 | TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17545 | TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17546 | TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17547 | TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17548 | TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17549 | TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17550 | TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
21d799b5 NC |
17551 | TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), |
17552 | TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), | |
17553 | TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), | |
17554 | TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), | |
17555 | TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), | |
c19d1205 | 17556 | |
c921be7d NC |
17557 | #undef ARM_VARIANT |
17558 | #define ARM_VARIANT & arm_ext_v6k | |
17559 | #undef THUMB_VARIANT | |
17560 | #define THUMB_VARIANT & arm_ext_v6k | |
17561 | ||
21d799b5 NC |
17562 | tCE("yield", 320f001, _yield, 0, (), noargs, t_hint), |
17563 | tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint), | |
17564 | tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint), | |
17565 | tCE("sev", 320f004, _sev, 0, (), noargs, t_hint), | |
c19d1205 | 17566 | |
c921be7d NC |
17567 | #undef THUMB_VARIANT |
17568 | #define THUMB_VARIANT & arm_ext_v6_notm | |
5be8be5d DG |
17569 | TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb), |
17570 | ldrexd, t_ldrexd), | |
17571 | TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp, | |
17572 | RRnpcb), strexd, t_strexd), | |
ebdca51a | 17573 | |
c921be7d NC |
17574 | #undef THUMB_VARIANT |
17575 | #define THUMB_VARIANT & arm_ext_v6t2 | |
5be8be5d DG |
17576 | TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), |
17577 | rd_rn, rd_rn), | |
17578 | TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), | |
17579 | rd_rn, rd_rn), | |
17580 | TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), | |
877807f8 | 17581 | strex, t_strexbh), |
5be8be5d | 17582 | TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), |
877807f8 | 17583 | strex, t_strexbh), |
21d799b5 | 17584 | TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs), |
c19d1205 | 17585 | |
c921be7d | 17586 | #undef ARM_VARIANT |
f4c65163 MGD |
17587 | #define ARM_VARIANT & arm_ext_sec |
17588 | #undef THUMB_VARIANT | |
17589 | #define THUMB_VARIANT & arm_ext_sec | |
c921be7d | 17590 | |
21d799b5 | 17591 | TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc), |
c19d1205 | 17592 | |
90ec0d68 MGD |
17593 | #undef ARM_VARIANT |
17594 | #define ARM_VARIANT & arm_ext_virt | |
17595 | #undef THUMB_VARIANT | |
17596 | #define THUMB_VARIANT & arm_ext_virt | |
17597 | ||
17598 | TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc), | |
17599 | TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs), | |
17600 | ||
c921be7d NC |
17601 | #undef ARM_VARIANT |
17602 | #define ARM_VARIANT & arm_ext_v6t2 | |
f4c65163 MGD |
17603 | #undef THUMB_VARIANT |
17604 | #define THUMB_VARIANT & arm_ext_v6t2 | |
c921be7d | 17605 | |
21d799b5 NC |
17606 | TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), |
17607 | TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), | |
17608 | TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
17609 | TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), | |
c19d1205 | 17610 | |
21d799b5 NC |
17611 | TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), |
17612 | TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17613 | TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), | |
17614 | TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), | |
c19d1205 | 17615 | |
5be8be5d DG |
17616 | TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), |
17617 | TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17618 | TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
17619 | TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), | |
c19d1205 | 17620 | |
bf3eeda7 NS |
17621 | /* Thumb-only instructions. */ |
17622 | #undef ARM_VARIANT | |
17623 | #define ARM_VARIANT NULL | |
17624 | TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz), | |
17625 | TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz), | |
c921be7d NC |
17626 | |
17627 | /* ARM does not really have an IT instruction, so always allow it. | |
17628 | The opcode is copied from Thumb in order to allow warnings in | |
17629 | -mimplicit-it=[never | arm] modes. */ | |
17630 | #undef ARM_VARIANT | |
17631 | #define ARM_VARIANT & arm_ext_v1 | |
17632 | ||
21d799b5 NC |
17633 | TUE("it", bf08, bf08, 1, (COND), it, t_it), |
17634 | TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), | |
17635 | TUE("ite", bf04, bf04, 1, (COND), it, t_it), | |
17636 | TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it), | |
17637 | TUE("itet", bf06, bf06, 1, (COND), it, t_it), | |
17638 | TUE("itte", bf0a, bf0a, 1, (COND), it, t_it), | |
17639 | TUE("itee", bf02, bf02, 1, (COND), it, t_it), | |
17640 | TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it), | |
17641 | TUE("itett", bf07, bf07, 1, (COND), it, t_it), | |
17642 | TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it), | |
17643 | TUE("iteet", bf03, bf03, 1, (COND), it, t_it), | |
17644 | TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it), | |
17645 | TUE("itete", bf05, bf05, 1, (COND), it, t_it), | |
17646 | TUE("ittee", bf09, bf09, 1, (COND), it, t_it), | |
17647 | TUE("iteee", bf01, bf01, 1, (COND), it, t_it), | |
1c444d06 | 17648 | /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */ |
21d799b5 NC |
17649 | TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx), |
17650 | TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx), | |
c19d1205 | 17651 | |
92e90b6e | 17652 | /* Thumb2 only instructions. */ |
c921be7d NC |
17653 | #undef ARM_VARIANT |
17654 | #define ARM_VARIANT NULL | |
92e90b6e | 17655 | |
21d799b5 NC |
17656 | TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
17657 | TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), | |
17658 | TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn), | |
17659 | TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn), | |
17660 | TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb), | |
17661 | TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb), | |
92e90b6e | 17662 | |
eea54501 MGD |
17663 | /* Hardware division instructions. */ |
17664 | #undef ARM_VARIANT | |
17665 | #define ARM_VARIANT & arm_ext_adiv | |
c921be7d NC |
17666 | #undef THUMB_VARIANT |
17667 | #define THUMB_VARIANT & arm_ext_div | |
17668 | ||
eea54501 MGD |
17669 | TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div), |
17670 | TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div), | |
62b3e311 | 17671 | |
7e806470 | 17672 | /* ARM V6M/V7 instructions. */ |
c921be7d NC |
17673 | #undef ARM_VARIANT |
17674 | #define ARM_VARIANT & arm_ext_barrier | |
17675 | #undef THUMB_VARIANT | |
17676 | #define THUMB_VARIANT & arm_ext_barrier | |
17677 | ||
52e7f43d RE |
17678 | TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier), |
17679 | TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier), | |
17680 | TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier), | |
7e806470 | 17681 | |
62b3e311 | 17682 | /* ARM V7 instructions. */ |
c921be7d NC |
17683 | #undef ARM_VARIANT |
17684 | #define ARM_VARIANT & arm_ext_v7 | |
17685 | #undef THUMB_VARIANT | |
17686 | #define THUMB_VARIANT & arm_ext_v7 | |
17687 | ||
21d799b5 NC |
17688 | TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld), |
17689 | TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), | |
62b3e311 | 17690 | |
60e5ef9f MGD |
17691 | #undef ARM_VARIANT |
17692 | #define ARM_VARIANT & arm_ext_mp | |
17693 | #undef THUMB_VARIANT | |
17694 | #define THUMB_VARIANT & arm_ext_mp | |
17695 | ||
17696 | TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld), | |
17697 | ||
c921be7d NC |
17698 | #undef ARM_VARIANT |
17699 | #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ | |
17700 | ||
21d799b5 NC |
17701 | cCE("wfs", e200110, 1, (RR), rd), |
17702 | cCE("rfs", e300110, 1, (RR), rd), | |
17703 | cCE("wfc", e400110, 1, (RR), rd), | |
17704 | cCE("rfc", e500110, 1, (RR), rd), | |
17705 | ||
17706 | cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17707 | cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17708 | cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17709 | cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17710 | ||
17711 | cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17712 | cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17713 | cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17714 | cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr), | |
17715 | ||
17716 | cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm), | |
17717 | cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm), | |
17718 | cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm), | |
17719 | cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm), | |
17720 | cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm), | |
17721 | cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm), | |
17722 | cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm), | |
17723 | cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm), | |
17724 | cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm), | |
17725 | cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm), | |
17726 | cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm), | |
17727 | cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm), | |
17728 | ||
17729 | cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm), | |
17730 | cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm), | |
17731 | cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm), | |
17732 | cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm), | |
17733 | cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm), | |
17734 | cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm), | |
17735 | cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm), | |
17736 | cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm), | |
17737 | cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm), | |
17738 | cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm), | |
17739 | cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm), | |
17740 | cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm), | |
17741 | ||
17742 | cCL("abss", e208100, 2, (RF, RF_IF), rd_rm), | |
17743 | cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm), | |
17744 | cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm), | |
17745 | cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm), | |
17746 | cCL("absd", e208180, 2, (RF, RF_IF), rd_rm), | |
17747 | cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm), | |
17748 | cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm), | |
17749 | cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm), | |
17750 | cCL("abse", e288100, 2, (RF, RF_IF), rd_rm), | |
17751 | cCL("absep", e288120, 2, (RF, RF_IF), rd_rm), | |
17752 | cCL("absem", e288140, 2, (RF, RF_IF), rd_rm), | |
17753 | cCL("absez", e288160, 2, (RF, RF_IF), rd_rm), | |
17754 | ||
17755 | cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm), | |
17756 | cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm), | |
17757 | cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm), | |
17758 | cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm), | |
17759 | cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm), | |
17760 | cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm), | |
17761 | cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm), | |
17762 | cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm), | |
17763 | cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm), | |
17764 | cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm), | |
17765 | cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm), | |
17766 | cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm), | |
17767 | ||
17768 | cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm), | |
17769 | cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm), | |
17770 | cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm), | |
17771 | cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm), | |
17772 | cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm), | |
17773 | cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm), | |
17774 | cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm), | |
17775 | cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm), | |
17776 | cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm), | |
17777 | cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm), | |
17778 | cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm), | |
17779 | cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm), | |
17780 | ||
17781 | cCL("logs", e508100, 2, (RF, RF_IF), rd_rm), | |
17782 | cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm), | |
17783 | cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm), | |
17784 | cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm), | |
17785 | cCL("logd", e508180, 2, (RF, RF_IF), rd_rm), | |
17786 | cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm), | |
17787 | cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm), | |
17788 | cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm), | |
17789 | cCL("loge", e588100, 2, (RF, RF_IF), rd_rm), | |
17790 | cCL("logep", e588120, 2, (RF, RF_IF), rd_rm), | |
17791 | cCL("logem", e588140, 2, (RF, RF_IF), rd_rm), | |
17792 | cCL("logez", e588160, 2, (RF, RF_IF), rd_rm), | |
17793 | ||
17794 | cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm), | |
17795 | cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm), | |
17796 | cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm), | |
17797 | cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm), | |
17798 | cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm), | |
17799 | cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm), | |
17800 | cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm), | |
17801 | cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm), | |
17802 | cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm), | |
17803 | cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm), | |
17804 | cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm), | |
17805 | cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm), | |
17806 | ||
17807 | cCL("exps", e708100, 2, (RF, RF_IF), rd_rm), | |
17808 | cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm), | |
17809 | cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm), | |
17810 | cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm), | |
17811 | cCL("expd", e708180, 2, (RF, RF_IF), rd_rm), | |
17812 | cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm), | |
17813 | cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm), | |
17814 | cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm), | |
17815 | cCL("expe", e788100, 2, (RF, RF_IF), rd_rm), | |
17816 | cCL("expep", e788120, 2, (RF, RF_IF), rd_rm), | |
17817 | cCL("expem", e788140, 2, (RF, RF_IF), rd_rm), | |
17818 | cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm), | |
17819 | ||
17820 | cCL("sins", e808100, 2, (RF, RF_IF), rd_rm), | |
17821 | cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm), | |
17822 | cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm), | |
17823 | cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm), | |
17824 | cCL("sind", e808180, 2, (RF, RF_IF), rd_rm), | |
17825 | cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm), | |
17826 | cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm), | |
17827 | cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm), | |
17828 | cCL("sine", e888100, 2, (RF, RF_IF), rd_rm), | |
17829 | cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm), | |
17830 | cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm), | |
17831 | cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm), | |
17832 | ||
17833 | cCL("coss", e908100, 2, (RF, RF_IF), rd_rm), | |
17834 | cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm), | |
17835 | cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm), | |
17836 | cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm), | |
17837 | cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm), | |
17838 | cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm), | |
17839 | cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm), | |
17840 | cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm), | |
17841 | cCL("cose", e988100, 2, (RF, RF_IF), rd_rm), | |
17842 | cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm), | |
17843 | cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm), | |
17844 | cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm), | |
17845 | ||
17846 | cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm), | |
17847 | cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm), | |
17848 | cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm), | |
17849 | cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm), | |
17850 | cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm), | |
17851 | cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm), | |
17852 | cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm), | |
17853 | cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm), | |
17854 | cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm), | |
17855 | cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm), | |
17856 | cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm), | |
17857 | cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm), | |
17858 | ||
17859 | cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm), | |
17860 | cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm), | |
17861 | cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm), | |
17862 | cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm), | |
17863 | cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm), | |
17864 | cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm), | |
17865 | cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm), | |
17866 | cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm), | |
17867 | cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm), | |
17868 | cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm), | |
17869 | cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm), | |
17870 | cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm), | |
17871 | ||
17872 | cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm), | |
17873 | cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm), | |
17874 | cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm), | |
17875 | cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm), | |
17876 | cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm), | |
17877 | cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm), | |
17878 | cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm), | |
17879 | cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm), | |
17880 | cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm), | |
17881 | cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm), | |
17882 | cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm), | |
17883 | cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm), | |
17884 | ||
17885 | cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm), | |
17886 | cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm), | |
17887 | cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm), | |
17888 | cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm), | |
17889 | cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm), | |
17890 | cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm), | |
17891 | cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm), | |
17892 | cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm), | |
17893 | cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm), | |
17894 | cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm), | |
17895 | cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm), | |
17896 | cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm), | |
17897 | ||
17898 | cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm), | |
17899 | cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm), | |
17900 | cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm), | |
17901 | cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm), | |
17902 | cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm), | |
17903 | cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm), | |
17904 | cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm), | |
17905 | cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm), | |
17906 | cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm), | |
17907 | cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm), | |
17908 | cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm), | |
17909 | cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm), | |
17910 | ||
17911 | cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm), | |
17912 | cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm), | |
17913 | cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm), | |
17914 | cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm), | |
17915 | cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm), | |
17916 | cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm), | |
17917 | cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm), | |
17918 | cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm), | |
17919 | cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm), | |
17920 | cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm), | |
17921 | cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm), | |
17922 | cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm), | |
17923 | ||
17924 | cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17925 | cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17926 | cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17927 | cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17928 | cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17929 | cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17930 | cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17931 | cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17932 | cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17933 | cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17934 | cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17935 | cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17936 | ||
17937 | cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17938 | cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17939 | cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17940 | cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17941 | cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17942 | cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17943 | cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17944 | cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17945 | cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17946 | cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17947 | cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17948 | cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17949 | ||
17950 | cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17951 | cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17952 | cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17953 | cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17954 | cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17955 | cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17956 | cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17957 | cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17958 | cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17959 | cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17960 | cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17961 | cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17962 | ||
17963 | cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17964 | cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17965 | cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17966 | cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17967 | cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17968 | cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17969 | cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17970 | cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17971 | cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17972 | cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17973 | cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17974 | cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17975 | ||
17976 | cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17977 | cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17978 | cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17979 | cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17980 | cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17981 | cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17982 | cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17983 | cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17984 | cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17985 | cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17986 | cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17987 | cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17988 | ||
17989 | cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17990 | cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17991 | cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17992 | cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17993 | cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17994 | cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17995 | cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17996 | cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17997 | cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17998 | cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
17999 | cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18000 | cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18001 | ||
18002 | cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18003 | cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18004 | cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18005 | cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18006 | cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18007 | cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18008 | cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18009 | cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18010 | cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18011 | cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18012 | cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18013 | cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18014 | ||
18015 | cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18016 | cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18017 | cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18018 | cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18019 | cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18020 | cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18021 | cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18022 | cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18023 | cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18024 | cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18025 | cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18026 | cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18027 | ||
18028 | cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18029 | cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18030 | cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18031 | cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18032 | cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18033 | cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18034 | cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18035 | cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18036 | cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18037 | cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18038 | cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18039 | cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18040 | ||
18041 | cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18042 | cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18043 | cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18044 | cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18045 | cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18046 | cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18047 | cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18048 | cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18049 | cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18050 | cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18051 | cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18052 | cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18053 | ||
18054 | cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18055 | cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18056 | cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18057 | cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18058 | cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18059 | cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18060 | cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18061 | cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18062 | cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18063 | cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18064 | cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18065 | cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18066 | ||
18067 | cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18068 | cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18069 | cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18070 | cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18071 | cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18072 | cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18073 | cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18074 | cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18075 | cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18076 | cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18077 | cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18078 | cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18079 | ||
18080 | cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18081 | cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18082 | cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18083 | cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18084 | cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18085 | cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18086 | cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18087 | cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18088 | cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18089 | cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18090 | cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18091 | cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), | |
18092 | ||
18093 | cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp), | |
18094 | C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp), | |
18095 | cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp), | |
18096 | C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp), | |
18097 | ||
18098 | cCL("flts", e000110, 2, (RF, RR), rn_rd), | |
18099 | cCL("fltsp", e000130, 2, (RF, RR), rn_rd), | |
18100 | cCL("fltsm", e000150, 2, (RF, RR), rn_rd), | |
18101 | cCL("fltsz", e000170, 2, (RF, RR), rn_rd), | |
18102 | cCL("fltd", e000190, 2, (RF, RR), rn_rd), | |
18103 | cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd), | |
18104 | cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd), | |
18105 | cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd), | |
18106 | cCL("flte", e080110, 2, (RF, RR), rn_rd), | |
18107 | cCL("fltep", e080130, 2, (RF, RR), rn_rd), | |
18108 | cCL("fltem", e080150, 2, (RF, RR), rn_rd), | |
18109 | cCL("fltez", e080170, 2, (RF, RR), rn_rd), | |
b99bd4ef | 18110 | |
c19d1205 ZW |
18111 | /* The implementation of the FIX instruction is broken on some |
18112 | assemblers, in that it accepts a precision specifier as well as a | |
18113 | rounding specifier, despite the fact that this is meaningless. | |
18114 | To be more compatible, we accept it as well, though of course it | |
18115 | does not set any bits. */ | |
21d799b5 NC |
18116 | cCE("fix", e100110, 2, (RR, RF), rd_rm), |
18117 | cCL("fixp", e100130, 2, (RR, RF), rd_rm), | |
18118 | cCL("fixm", e100150, 2, (RR, RF), rd_rm), | |
18119 | cCL("fixz", e100170, 2, (RR, RF), rd_rm), | |
18120 | cCL("fixsp", e100130, 2, (RR, RF), rd_rm), | |
18121 | cCL("fixsm", e100150, 2, (RR, RF), rd_rm), | |
18122 | cCL("fixsz", e100170, 2, (RR, RF), rd_rm), | |
18123 | cCL("fixdp", e100130, 2, (RR, RF), rd_rm), | |
18124 | cCL("fixdm", e100150, 2, (RR, RF), rd_rm), | |
18125 | cCL("fixdz", e100170, 2, (RR, RF), rd_rm), | |
18126 | cCL("fixep", e100130, 2, (RR, RF), rd_rm), | |
18127 | cCL("fixem", e100150, 2, (RR, RF), rd_rm), | |
18128 | cCL("fixez", e100170, 2, (RR, RF), rd_rm), | |
bfae80f2 | 18129 | |
c19d1205 | 18130 | /* Instructions that were new with the real FPA, call them V2. */ |
c921be7d NC |
18131 | #undef ARM_VARIANT |
18132 | #define ARM_VARIANT & fpu_fpa_ext_v2 | |
18133 | ||
21d799b5 NC |
18134 | cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), |
18135 | cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18136 | cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18137 | cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18138 | cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
18139 | cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), | |
c19d1205 | 18140 | |
c921be7d NC |
18141 | #undef ARM_VARIANT |
18142 | #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ | |
18143 | ||
c19d1205 | 18144 | /* Moves and type conversions. */ |
21d799b5 NC |
18145 | cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic), |
18146 | cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp), | |
18147 | cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg), | |
18148 | cCE("fmstat", ef1fa10, 0, (), noargs), | |
f7c21dc7 NC |
18149 | cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs), |
18150 | cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr), | |
21d799b5 NC |
18151 | cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), |
18152 | cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18153 | cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18154 | cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18155 | cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18156 | cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18157 | cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn), | |
18158 | cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd), | |
c19d1205 ZW |
18159 | |
18160 | /* Memory operations. */ | |
21d799b5 NC |
18161 | cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), |
18162 | cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), | |
55881a11 MGD |
18163 | cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), |
18164 | cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18165 | cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18166 | cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18167 | cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18168 | cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18169 | cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18170 | cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18171 | cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18172 | cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia), | |
18173 | cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18174 | cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb), | |
18175 | cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18176 | cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia), | |
18177 | cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
18178 | cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb), | |
bfae80f2 | 18179 | |
c19d1205 | 18180 | /* Monadic operations. */ |
21d799b5 NC |
18181 | cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), |
18182 | cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic), | |
18183 | cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
c19d1205 ZW |
18184 | |
18185 | /* Dyadic operations. */ | |
21d799b5 NC |
18186 | cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), |
18187 | cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18188 | cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18189 | cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18190 | cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18191 | cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18192 | cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18193 | cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18194 | cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
b99bd4ef | 18195 | |
c19d1205 | 18196 | /* Comparisons. */ |
21d799b5 NC |
18197 | cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic), |
18198 | cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z), | |
18199 | cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), | |
18200 | cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z), | |
b99bd4ef | 18201 | |
62f3b8c8 PB |
18202 | /* Double precision load/store are still present on single precision |
18203 | implementations. */ | |
18204 | cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
18205 | cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), | |
55881a11 MGD |
18206 | cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), |
18207 | cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18208 | cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18209 | cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18210 | cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18211 | cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia), | |
18212 | cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
18213 | cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb), | |
62f3b8c8 | 18214 | |
c921be7d NC |
18215 | #undef ARM_VARIANT |
18216 | #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ | |
18217 | ||
c19d1205 | 18218 | /* Moves and type conversions. */ |
21d799b5 NC |
18219 | cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
18220 | cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18221 | cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18222 | cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
18223 | cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd), | |
18224 | cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
18225 | cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn), | |
18226 | cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18227 | cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), | |
18228 | cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18229 | cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18230 | cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
18231 | cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), | |
c19d1205 | 18232 | |
c19d1205 | 18233 | /* Monadic operations. */ |
21d799b5 NC |
18234 | cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), |
18235 | cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), | |
18236 | cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
c19d1205 ZW |
18237 | |
18238 | /* Dyadic operations. */ | |
21d799b5 NC |
18239 | cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), |
18240 | cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18241 | cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18242 | cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18243 | cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18244 | cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18245 | cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18246 | cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18247 | cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
b99bd4ef | 18248 | |
c19d1205 | 18249 | /* Comparisons. */ |
21d799b5 NC |
18250 | cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), |
18251 | cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd), | |
18252 | cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), | |
18253 | cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd), | |
c19d1205 | 18254 | |
c921be7d NC |
18255 | #undef ARM_VARIANT |
18256 | #define ARM_VARIANT & fpu_vfp_ext_v2 | |
18257 | ||
21d799b5 NC |
18258 | cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), |
18259 | cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), | |
18260 | cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), | |
18261 | cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), | |
5287ad62 | 18262 | |
037e8744 JB |
18263 | /* Instructions which may belong to either the Neon or VFP instruction sets. |
18264 | Individual encoder functions perform additional architecture checks. */ | |
c921be7d NC |
18265 | #undef ARM_VARIANT |
18266 | #define ARM_VARIANT & fpu_vfp_ext_v1xd | |
18267 | #undef THUMB_VARIANT | |
18268 | #define THUMB_VARIANT & fpu_vfp_ext_v1xd | |
18269 | ||
037e8744 JB |
18270 | /* These mnemonics are unique to VFP. */ |
18271 | NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), | |
18272 | NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), | |
21d799b5 NC |
18273 | nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), |
18274 | nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18275 | nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18276 | nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
18277 | nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), | |
037e8744 JB |
18278 | NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), |
18279 | NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), | |
18280 | NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), | |
18281 | ||
18282 | /* Mnemonics shared by Neon and VFP. */ | |
21d799b5 NC |
18283 | nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), |
18284 | nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
18285 | nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), | |
037e8744 | 18286 | |
21d799b5 NC |
18287 | nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), |
18288 | nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), | |
037e8744 JB |
18289 | |
18290 | NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
18291 | NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), | |
18292 | ||
55881a11 MGD |
18293 | NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), |
18294 | NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18295 | NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18296 | NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18297 | NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
18298 | NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm), | |
4962c51a MS |
18299 | NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
18300 | NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), | |
037e8744 | 18301 | |
5f1af56b | 18302 | nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt), |
e3e535bc | 18303 | nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr), |
21d799b5 NC |
18304 | nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb), |
18305 | nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt), | |
f31fef98 | 18306 | |
037e8744 JB |
18307 | |
18308 | /* NOTE: All VMOV encoding is special-cased! */ | |
18309 | NCE(vmov, 0, 1, (VMOV), neon_mov), | |
18310 | NCE(vmovq, 0, 1, (VMOV), neon_mov), | |
18311 | ||
c921be7d NC |
18312 | #undef THUMB_VARIANT |
18313 | #define THUMB_VARIANT & fpu_neon_ext_v1 | |
18314 | #undef ARM_VARIANT | |
18315 | #define ARM_VARIANT & fpu_neon_ext_v1 | |
18316 | ||
5287ad62 JB |
18317 | /* Data processing with three registers of the same length. */ |
18318 | /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ | |
18319 | NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), | |
18320 | NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), | |
18321 | NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18322 | NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18323 | NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18324 | NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18325 | NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), | |
18326 | NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), | |
18327 | /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18328 | NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
18329 | NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
18330 | NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), | |
18331 | NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), | |
627907b7 JB |
18332 | NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), |
18333 | NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
18334 | NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), | |
18335 | NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), | |
5287ad62 JB |
18336 | /* If not immediate, fall back to neon_dyadic_i64_su. |
18337 | shl_imm should accept I8 I16 I32 I64, | |
18338 | qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ | |
21d799b5 NC |
18339 | nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), |
18340 | nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), | |
18341 | nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), | |
18342 | nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), | |
5287ad62 | 18343 | /* Logic ops, types optional & ignored. */ |
4316f0d2 DG |
18344 | nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), |
18345 | nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18346 | nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18347 | nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18348 | nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18349 | nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18350 | nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic), | |
18351 | nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic), | |
18352 | nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), | |
18353 | nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic), | |
5287ad62 JB |
18354 | /* Bitfield ops, untyped. */ |
18355 | NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18356 | NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18357 | NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18358 | NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18359 | NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), | |
18360 | NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), | |
18361 | /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ | |
21d799b5 NC |
18362 | nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), |
18363 | nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
18364 | nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
18365 | nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
18366 | nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), | |
18367 | nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), | |
5287ad62 JB |
18368 | /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall |
18369 | back to neon_dyadic_if_su. */ | |
21d799b5 NC |
18370 | nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), |
18371 | nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
18372 | nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), | |
18373 | nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), | |
18374 | nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
18375 | nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
18376 | nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), | |
18377 | nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), | |
428e3f1f | 18378 | /* Comparison. Type I8 I16 I32 F32. */ |
21d799b5 NC |
18379 | nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), |
18380 | nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), | |
5287ad62 | 18381 | /* As above, D registers only. */ |
21d799b5 NC |
18382 | nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), |
18383 | nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), | |
5287ad62 | 18384 | /* Int and float variants, signedness unimportant. */ |
21d799b5 NC |
18385 | nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), |
18386 | nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), | |
18387 | nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), | |
5287ad62 | 18388 | /* Add/sub take types I8 I16 I32 I64 F32. */ |
21d799b5 NC |
18389 | nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), |
18390 | nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), | |
5287ad62 JB |
18391 | /* vtst takes sizes 8, 16, 32. */ |
18392 | NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), | |
18393 | NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), | |
18394 | /* VMUL takes I8 I16 I32 F32 P8. */ | |
21d799b5 | 18395 | nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), |
5287ad62 | 18396 | /* VQD{R}MULH takes S16 S32. */ |
21d799b5 NC |
18397 | nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), |
18398 | nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
18399 | nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), | |
18400 | nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), | |
5287ad62 JB |
18401 | NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), |
18402 | NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
18403 | NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), | |
18404 | NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), | |
92559b5b PB |
18405 | NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), |
18406 | NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
18407 | NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), | |
18408 | NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), | |
5287ad62 JB |
18409 | NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), |
18410 | NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
18411 | NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), | |
18412 | NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), | |
18413 | ||
18414 | /* Two address, int/float. Types S8 S16 S32 F32. */ | |
5287ad62 | 18415 | NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), |
5287ad62 JB |
18416 | NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), |
18417 | ||
18418 | /* Data processing with two registers and a shift amount. */ | |
18419 | /* Right shifts, and variants with rounding. | |
18420 | Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18421 | NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
18422 | NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
18423 | NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), | |
18424 | NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), | |
18425 | NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
18426 | NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
18427 | NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), | |
18428 | NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), | |
18429 | /* Shift and insert. Sizes accepted 8 16 32 64. */ | |
18430 | NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), | |
18431 | NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), | |
18432 | NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), | |
18433 | NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), | |
18434 | /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ | |
18435 | NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), | |
18436 | NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), | |
18437 | /* Right shift immediate, saturating & narrowing, with rounding variants. | |
18438 | Types accepted S16 S32 S64 U16 U32 U64. */ | |
18439 | NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
18440 | NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), | |
18441 | /* As above, unsigned. Types accepted S16 S32 S64. */ | |
18442 | NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
18443 | NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), | |
18444 | /* Right shift narrowing. Types accepted I16 I32 I64. */ | |
18445 | NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
18446 | NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), | |
18447 | /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ | |
21d799b5 | 18448 | nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll), |
5287ad62 | 18449 | /* CVT with optional immediate for fixed-point variant. */ |
21d799b5 | 18450 | nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), |
b7fc2769 | 18451 | |
4316f0d2 DG |
18452 | nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn), |
18453 | nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn), | |
5287ad62 JB |
18454 | |
18455 | /* Data processing, three registers of different lengths. */ | |
18456 | /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ | |
18457 | NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), | |
18458 | NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18459 | NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18460 | NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), | |
18461 | /* If not scalar, fall back to neon_dyadic_long. | |
18462 | Vector types as above, scalar types S16 S32 U16 U32. */ | |
21d799b5 NC |
18463 | nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), |
18464 | nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), | |
5287ad62 JB |
18465 | /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ |
18466 | NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
18467 | NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), | |
18468 | /* Dyadic, narrowing insns. Types I16 I32 I64. */ | |
18469 | NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18470 | NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18471 | NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18472 | NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), | |
18473 | /* Saturating doubling multiplies. Types S16 S32. */ | |
21d799b5 NC |
18474 | nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), |
18475 | nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
18476 | nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), | |
5287ad62 JB |
18477 | /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types |
18478 | S16 S32 U16 U32. */ | |
21d799b5 | 18479 | nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), |
5287ad62 JB |
18480 | |
18481 | /* Extract. Size 8. */ | |
3b8d421e PB |
18482 | NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), |
18483 | NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), | |
5287ad62 JB |
18484 | |
18485 | /* Two registers, miscellaneous. */ | |
18486 | /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ | |
18487 | NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), | |
18488 | NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), | |
18489 | NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), | |
18490 | NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), | |
18491 | NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), | |
18492 | NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), | |
18493 | /* Vector replicate. Sizes 8 16 32. */ | |
21d799b5 NC |
18494 | nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup), |
18495 | nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup), | |
5287ad62 JB |
18496 | /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ |
18497 | NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), | |
18498 | /* VMOVN. Types I16 I32 I64. */ | |
21d799b5 | 18499 | nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn), |
5287ad62 | 18500 | /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ |
21d799b5 | 18501 | nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn), |
5287ad62 | 18502 | /* VQMOVUN. Types S16 S32 S64. */ |
21d799b5 | 18503 | nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun), |
5287ad62 JB |
18504 | /* VZIP / VUZP. Sizes 8 16 32. */ |
18505 | NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
18506 | NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), | |
18507 | NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), | |
18508 | NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), | |
18509 | /* VQABS / VQNEG. Types S8 S16 S32. */ | |
18510 | NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
18511 | NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
18512 | NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), | |
18513 | NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), | |
18514 | /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ | |
18515 | NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), | |
18516 | NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), | |
18517 | NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), | |
18518 | NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), | |
18519 | /* Reciprocal estimates. Types U32 F32. */ | |
18520 | NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), | |
18521 | NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), | |
18522 | NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), | |
18523 | NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), | |
18524 | /* VCLS. Types S8 S16 S32. */ | |
18525 | NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), | |
18526 | NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), | |
18527 | /* VCLZ. Types I8 I16 I32. */ | |
18528 | NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), | |
18529 | NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), | |
18530 | /* VCNT. Size 8. */ | |
18531 | NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), | |
18532 | NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), | |
18533 | /* Two address, untyped. */ | |
18534 | NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), | |
18535 | NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), | |
18536 | /* VTRN. Sizes 8 16 32. */ | |
21d799b5 NC |
18537 | nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn), |
18538 | nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn), | |
5287ad62 JB |
18539 | |
18540 | /* Table lookup. Size 8. */ | |
18541 | NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
18542 | NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), | |
18543 | ||
c921be7d NC |
18544 | #undef THUMB_VARIANT |
18545 | #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext | |
18546 | #undef ARM_VARIANT | |
18547 | #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext | |
18548 | ||
5287ad62 | 18549 | /* Neon element/structure load/store. */ |
21d799b5 NC |
18550 | nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), |
18551 | nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18552 | nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18553 | nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18554 | nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18555 | nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18556 | nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
18557 | nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), | |
5287ad62 | 18558 | |
c921be7d | 18559 | #undef THUMB_VARIANT |
62f3b8c8 PB |
18560 | #define THUMB_VARIANT &fpu_vfp_ext_v3xd |
18561 | #undef ARM_VARIANT | |
18562 | #define ARM_VARIANT &fpu_vfp_ext_v3xd | |
18563 | cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const), | |
18564 | cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18565 | cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18566 | cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18567 | cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18568 | cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18569 | cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18570 | cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), | |
18571 | cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), | |
18572 | ||
18573 | #undef THUMB_VARIANT | |
c921be7d NC |
18574 | #define THUMB_VARIANT & fpu_vfp_ext_v3 |
18575 | #undef ARM_VARIANT | |
18576 | #define ARM_VARIANT & fpu_vfp_ext_v3 | |
18577 | ||
21d799b5 | 18578 | cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const), |
21d799b5 | 18579 | cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18580 | cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18581 | cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18582 | cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18583 | cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18584 | cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
21d799b5 | 18585 | cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), |
21d799b5 | 18586 | cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), |
c19d1205 | 18587 | |
62f3b8c8 PB |
18588 | #undef ARM_VARIANT |
18589 | #define ARM_VARIANT &fpu_vfp_ext_fma | |
18590 | #undef THUMB_VARIANT | |
18591 | #define THUMB_VARIANT &fpu_vfp_ext_fma | |
18592 | /* Mnemonics shared by Neon and VFP. These are included in the | |
18593 | VFP FMA variant; NEON and VFP FMA always includes the NEON | |
18594 | FMA instructions. */ | |
18595 | nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
18596 | nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac), | |
18597 | /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas; | |
18598 | the v form should always be used. */ | |
18599 | cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18600 | cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), | |
18601 | cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18602 | cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), | |
18603 | nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18604 | nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), | |
18605 | ||
5287ad62 | 18606 | #undef THUMB_VARIANT |
c921be7d NC |
18607 | #undef ARM_VARIANT |
18608 | #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */ | |
18609 | ||
21d799b5 NC |
18610 | cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), |
18611 | cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18612 | cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18613 | cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18614 | cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18615 | cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), | |
18616 | cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), | |
18617 | cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), | |
c19d1205 | 18618 | |
c921be7d NC |
18619 | #undef ARM_VARIANT |
18620 | #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */ | |
18621 | ||
21d799b5 NC |
18622 | cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc), |
18623 | cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc), | |
18624 | cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc), | |
18625 | cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd), | |
18626 | cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd), | |
18627 | cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd), | |
18628 | cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc), | |
18629 | cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc), | |
18630 | cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc), | |
18631 | cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18632 | cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18633 | cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18634 | cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18635 | cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18636 | cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), | |
18637 | cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18638 | cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18639 | cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), | |
18640 | cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd), | |
18641 | cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn), | |
18642 | cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18643 | cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18644 | cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18645 | cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18646 | cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18647 | cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), | |
18648 | cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn), | |
18649 | cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn), | |
18650 | cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn), | |
18651 | cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn), | |
18652 | cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm), | |
18653 | cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc), | |
18654 | cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc), | |
18655 | cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc), | |
18656 | cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn), | |
18657 | cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn), | |
18658 | cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn), | |
18659 | cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18660 | cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18661 | cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18662 | cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18663 | cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18664 | cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18665 | cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18666 | cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18667 | cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18668 | cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), | |
18669 | cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18670 | cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18671 | cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18672 | cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18673 | cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18674 | cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18675 | cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18676 | cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18677 | cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18678 | cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18679 | cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18680 | cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18681 | cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18682 | cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18683 | cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18684 | cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18685 | cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18686 | cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18687 | cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18688 | cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18689 | cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18690 | cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18691 | cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18692 | cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18693 | cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18694 | cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18695 | cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18696 | cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18697 | cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18698 | cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18699 | cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18700 | cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18701 | cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18702 | cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18703 | cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18704 | cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18705 | cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18706 | cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18707 | cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18708 | cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18709 | cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18710 | cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov), | |
18711 | cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18712 | cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18713 | cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18714 | cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18715 | cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18716 | cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18717 | cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18718 | cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18719 | cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18720 | cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18721 | cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18722 | cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18723 | cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18724 | cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18725 | cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18726 | cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18727 | cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18728 | cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18729 | cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18730 | cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18731 | cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18732 | cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), | |
18733 | cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18734 | cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18735 | cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18736 | cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18737 | cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18738 | cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18739 | cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18740 | cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18741 | cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18742 | cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18743 | cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18744 | cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18745 | cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18746 | cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18747 | cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18748 | cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18749 | cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), | |
18750 | cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), | |
18751 | cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18752 | cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), | |
18753 | cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), | |
18754 | cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), | |
18755 | cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18756 | cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18757 | cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18758 | cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18759 | cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18760 | cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18761 | cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18762 | cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18763 | cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18764 | cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn), | |
18765 | cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn), | |
18766 | cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn), | |
18767 | cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn), | |
18768 | cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn), | |
18769 | cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn), | |
18770 | cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18771 | cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18772 | cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18773 | cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn), | |
18774 | cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn), | |
18775 | cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn), | |
18776 | cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn), | |
18777 | cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn), | |
18778 | cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn), | |
18779 | cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18780 | cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18781 | cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18782 | cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18783 | cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero), | |
c19d1205 | 18784 | |
c921be7d NC |
18785 | #undef ARM_VARIANT |
18786 | #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ | |
18787 | ||
21d799b5 NC |
18788 | cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc), |
18789 | cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc), | |
18790 | cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc), | |
18791 | cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn), | |
18792 | cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn), | |
18793 | cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn), | |
18794 | cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18795 | cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18796 | cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18797 | cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18798 | cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18799 | cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18800 | cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18801 | cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18802 | cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18803 | cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18804 | cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18805 | cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18806 | cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18807 | cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18808 | cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), | |
18809 | cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18810 | cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18811 | cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18812 | cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18813 | cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18814 | cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18815 | cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18816 | cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18817 | cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18818 | cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18819 | cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18820 | cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18821 | cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18822 | cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18823 | cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18824 | cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18825 | cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18826 | cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18827 | cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18828 | cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18829 | cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18830 | cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18831 | cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18832 | cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18833 | cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18834 | cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18835 | cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18836 | cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18837 | cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18838 | cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18839 | cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18840 | cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18841 | cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18842 | cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18843 | cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
18844 | cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), | |
2d447fca | 18845 | |
c921be7d NC |
18846 | #undef ARM_VARIANT |
18847 | #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */ | |
18848 | ||
21d799b5 NC |
18849 | cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), |
18850 | cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18851 | cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18852 | cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18853 | cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), | |
18854 | cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), | |
18855 | cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), | |
18856 | cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), | |
18857 | cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd), | |
18858 | cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn), | |
18859 | cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd), | |
18860 | cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn), | |
18861 | cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd), | |
18862 | cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn), | |
18863 | cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd), | |
18864 | cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn), | |
18865 | cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd), | |
18866 | cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn), | |
18867 | cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn), | |
18868 | cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn), | |
18869 | cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn), | |
18870 | cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn), | |
18871 | cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn), | |
18872 | cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn), | |
18873 | cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn), | |
18874 | cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn), | |
18875 | cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn), | |
18876 | cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn), | |
18877 | cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc), | |
18878 | cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd), | |
18879 | cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn), | |
18880 | cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn), | |
18881 | cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn), | |
18882 | cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn), | |
18883 | cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn), | |
18884 | cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn), | |
18885 | cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn), | |
18886 | cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn), | |
18887 | cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn), | |
18888 | cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn), | |
18889 | cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn), | |
18890 | cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn), | |
18891 | cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple), | |
18892 | cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple), | |
18893 | cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift), | |
18894 | cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift), | |
18895 | cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm), | |
18896 | cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), | |
18897 | cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), | |
18898 | cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), | |
18899 | cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn), | |
18900 | cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn), | |
18901 | cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn), | |
18902 | cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn), | |
18903 | cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18904 | cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18905 | cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18906 | cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18907 | cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm), | |
18908 | cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm), | |
18909 | cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn), | |
18910 | cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn), | |
18911 | cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn), | |
18912 | cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn), | |
18913 | cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18914 | cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18915 | cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18916 | cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18917 | cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18918 | cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), | |
18919 | cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18920 | cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), | |
18921 | cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18922 | cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), | |
18923 | cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
18924 | cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), | |
c19d1205 ZW |
18925 | }; |
18926 | #undef ARM_VARIANT | |
18927 | #undef THUMB_VARIANT | |
18928 | #undef TCE | |
18929 | #undef TCM | |
18930 | #undef TUE | |
18931 | #undef TUF | |
18932 | #undef TCC | |
8f06b2d8 | 18933 | #undef cCE |
e3cb604e PB |
18934 | #undef cCL |
18935 | #undef C3E | |
c19d1205 ZW |
18936 | #undef CE |
18937 | #undef CM | |
18938 | #undef UE | |
18939 | #undef UF | |
18940 | #undef UT | |
5287ad62 JB |
18941 | #undef NUF |
18942 | #undef nUF | |
18943 | #undef NCE | |
18944 | #undef nCE | |
c19d1205 ZW |
18945 | #undef OPS0 |
18946 | #undef OPS1 | |
18947 | #undef OPS2 | |
18948 | #undef OPS3 | |
18949 | #undef OPS4 | |
18950 | #undef OPS5 | |
18951 | #undef OPS6 | |
18952 | #undef do_0 | |
18953 | \f | |
18954 | /* MD interface: bits in the object file. */ | |
bfae80f2 | 18955 | |
c19d1205 ZW |
18956 | /* Turn an integer of n bytes (in val) into a stream of bytes appropriate |
18957 | for use in the a.out file, and stores them in the array pointed to by buf. | |
18958 | This knows about the endian-ness of the target machine and does | |
18959 | THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) | |
18960 | 2 (short) and 4 (long) Floating numbers are put out as a series of | |
18961 | LITTLENUMS (shorts, here at least). */ | |
b99bd4ef | 18962 | |
c19d1205 ZW |
18963 | void |
18964 | md_number_to_chars (char * buf, valueT val, int n) | |
18965 | { | |
18966 | if (target_big_endian) | |
18967 | number_to_chars_bigendian (buf, val, n); | |
18968 | else | |
18969 | number_to_chars_littleendian (buf, val, n); | |
bfae80f2 RE |
18970 | } |
18971 | ||
c19d1205 ZW |
18972 | static valueT |
18973 | md_chars_to_number (char * buf, int n) | |
bfae80f2 | 18974 | { |
c19d1205 ZW |
18975 | valueT result = 0; |
18976 | unsigned char * where = (unsigned char *) buf; | |
bfae80f2 | 18977 | |
c19d1205 | 18978 | if (target_big_endian) |
b99bd4ef | 18979 | { |
c19d1205 ZW |
18980 | while (n--) |
18981 | { | |
18982 | result <<= 8; | |
18983 | result |= (*where++ & 255); | |
18984 | } | |
b99bd4ef | 18985 | } |
c19d1205 | 18986 | else |
b99bd4ef | 18987 | { |
c19d1205 ZW |
18988 | while (n--) |
18989 | { | |
18990 | result <<= 8; | |
18991 | result |= (where[n] & 255); | |
18992 | } | |
bfae80f2 | 18993 | } |
b99bd4ef | 18994 | |
c19d1205 | 18995 | return result; |
bfae80f2 | 18996 | } |
b99bd4ef | 18997 | |
c19d1205 | 18998 | /* MD interface: Sections. */ |
b99bd4ef | 18999 | |
0110f2b8 PB |
19000 | /* Estimate the size of a frag before relaxing. Assume everything fits in |
19001 | 2 bytes. */ | |
19002 | ||
c19d1205 | 19003 | int |
0110f2b8 | 19004 | md_estimate_size_before_relax (fragS * fragp, |
c19d1205 ZW |
19005 | segT segtype ATTRIBUTE_UNUSED) |
19006 | { | |
0110f2b8 PB |
19007 | fragp->fr_var = 2; |
19008 | return 2; | |
19009 | } | |
19010 | ||
19011 | /* Convert a machine dependent frag. */ | |
19012 | ||
19013 | void | |
19014 | md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) | |
19015 | { | |
19016 | unsigned long insn; | |
19017 | unsigned long old_op; | |
19018 | char *buf; | |
19019 | expressionS exp; | |
19020 | fixS *fixp; | |
19021 | int reloc_type; | |
19022 | int pc_rel; | |
19023 | int opcode; | |
19024 | ||
19025 | buf = fragp->fr_literal + fragp->fr_fix; | |
19026 | ||
19027 | old_op = bfd_get_16(abfd, buf); | |
5f4273c7 NC |
19028 | if (fragp->fr_symbol) |
19029 | { | |
0110f2b8 PB |
19030 | exp.X_op = O_symbol; |
19031 | exp.X_add_symbol = fragp->fr_symbol; | |
5f4273c7 NC |
19032 | } |
19033 | else | |
19034 | { | |
0110f2b8 | 19035 | exp.X_op = O_constant; |
5f4273c7 | 19036 | } |
0110f2b8 PB |
19037 | exp.X_add_number = fragp->fr_offset; |
19038 | opcode = fragp->fr_subtype; | |
19039 | switch (opcode) | |
19040 | { | |
19041 | case T_MNEM_ldr_pc: | |
19042 | case T_MNEM_ldr_pc2: | |
19043 | case T_MNEM_ldr_sp: | |
19044 | case T_MNEM_str_sp: | |
19045 | case T_MNEM_ldr: | |
19046 | case T_MNEM_ldrb: | |
19047 | case T_MNEM_ldrh: | |
19048 | case T_MNEM_str: | |
19049 | case T_MNEM_strb: | |
19050 | case T_MNEM_strh: | |
19051 | if (fragp->fr_var == 4) | |
19052 | { | |
5f4273c7 | 19053 | insn = THUMB_OP32 (opcode); |
0110f2b8 PB |
19054 | if ((old_op >> 12) == 4 || (old_op >> 12) == 9) |
19055 | { | |
19056 | insn |= (old_op & 0x700) << 4; | |
19057 | } | |
19058 | else | |
19059 | { | |
19060 | insn |= (old_op & 7) << 12; | |
19061 | insn |= (old_op & 0x38) << 13; | |
19062 | } | |
19063 | insn |= 0x00000c00; | |
19064 | put_thumb32_insn (buf, insn); | |
19065 | reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; | |
19066 | } | |
19067 | else | |
19068 | { | |
19069 | reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; | |
19070 | } | |
19071 | pc_rel = (opcode == T_MNEM_ldr_pc2); | |
19072 | break; | |
19073 | case T_MNEM_adr: | |
19074 | if (fragp->fr_var == 4) | |
19075 | { | |
19076 | insn = THUMB_OP32 (opcode); | |
19077 | insn |= (old_op & 0xf0) << 4; | |
19078 | put_thumb32_insn (buf, insn); | |
19079 | reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; | |
19080 | } | |
19081 | else | |
19082 | { | |
19083 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
19084 | exp.X_add_number -= 4; | |
19085 | } | |
19086 | pc_rel = 1; | |
19087 | break; | |
19088 | case T_MNEM_mov: | |
19089 | case T_MNEM_movs: | |
19090 | case T_MNEM_cmp: | |
19091 | case T_MNEM_cmn: | |
19092 | if (fragp->fr_var == 4) | |
19093 | { | |
19094 | int r0off = (opcode == T_MNEM_mov | |
19095 | || opcode == T_MNEM_movs) ? 0 : 8; | |
19096 | insn = THUMB_OP32 (opcode); | |
19097 | insn = (insn & 0xe1ffffff) | 0x10000000; | |
19098 | insn |= (old_op & 0x700) << r0off; | |
19099 | put_thumb32_insn (buf, insn); | |
19100 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
19101 | } | |
19102 | else | |
19103 | { | |
19104 | reloc_type = BFD_RELOC_ARM_THUMB_IMM; | |
19105 | } | |
19106 | pc_rel = 0; | |
19107 | break; | |
19108 | case T_MNEM_b: | |
19109 | if (fragp->fr_var == 4) | |
19110 | { | |
19111 | insn = THUMB_OP32(opcode); | |
19112 | put_thumb32_insn (buf, insn); | |
19113 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; | |
19114 | } | |
19115 | else | |
19116 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; | |
19117 | pc_rel = 1; | |
19118 | break; | |
19119 | case T_MNEM_bcond: | |
19120 | if (fragp->fr_var == 4) | |
19121 | { | |
19122 | insn = THUMB_OP32(opcode); | |
19123 | insn |= (old_op & 0xf00) << 14; | |
19124 | put_thumb32_insn (buf, insn); | |
19125 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; | |
19126 | } | |
19127 | else | |
19128 | reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; | |
19129 | pc_rel = 1; | |
19130 | break; | |
19131 | case T_MNEM_add_sp: | |
19132 | case T_MNEM_add_pc: | |
19133 | case T_MNEM_inc_sp: | |
19134 | case T_MNEM_dec_sp: | |
19135 | if (fragp->fr_var == 4) | |
19136 | { | |
19137 | /* ??? Choose between add and addw. */ | |
19138 | insn = THUMB_OP32 (opcode); | |
19139 | insn |= (old_op & 0xf0) << 4; | |
19140 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
19141 | if (opcode == T_MNEM_add_pc) |
19142 | reloc_type = BFD_RELOC_ARM_T32_IMM12; | |
19143 | else | |
19144 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
0110f2b8 PB |
19145 | } |
19146 | else | |
19147 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
19148 | pc_rel = 0; | |
19149 | break; | |
19150 | ||
19151 | case T_MNEM_addi: | |
19152 | case T_MNEM_addis: | |
19153 | case T_MNEM_subi: | |
19154 | case T_MNEM_subis: | |
19155 | if (fragp->fr_var == 4) | |
19156 | { | |
19157 | insn = THUMB_OP32 (opcode); | |
19158 | insn |= (old_op & 0xf0) << 4; | |
19159 | insn |= (old_op & 0xf) << 16; | |
19160 | put_thumb32_insn (buf, insn); | |
16805f35 PB |
19161 | if (insn & (1 << 20)) |
19162 | reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; | |
19163 | else | |
19164 | reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; | |
0110f2b8 PB |
19165 | } |
19166 | else | |
19167 | reloc_type = BFD_RELOC_ARM_THUMB_ADD; | |
19168 | pc_rel = 0; | |
19169 | break; | |
19170 | default: | |
5f4273c7 | 19171 | abort (); |
0110f2b8 PB |
19172 | } |
19173 | fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, | |
21d799b5 | 19174 | (enum bfd_reloc_code_real) reloc_type); |
0110f2b8 PB |
19175 | fixp->fx_file = fragp->fr_file; |
19176 | fixp->fx_line = fragp->fr_line; | |
19177 | fragp->fr_fix += fragp->fr_var; | |
19178 | } | |
19179 | ||
19180 | /* Return the size of a relaxable immediate operand instruction. | |
19181 | SHIFT and SIZE specify the form of the allowable immediate. */ | |
19182 | static int | |
19183 | relax_immediate (fragS *fragp, int size, int shift) | |
19184 | { | |
19185 | offsetT offset; | |
19186 | offsetT mask; | |
19187 | offsetT low; | |
19188 | ||
19189 | /* ??? Should be able to do better than this. */ | |
19190 | if (fragp->fr_symbol) | |
19191 | return 4; | |
19192 | ||
19193 | low = (1 << shift) - 1; | |
19194 | mask = (1 << (shift + size)) - (1 << shift); | |
19195 | offset = fragp->fr_offset; | |
19196 | /* Force misaligned offsets to 32-bit variant. */ | |
19197 | if (offset & low) | |
5e77afaa | 19198 | return 4; |
0110f2b8 PB |
19199 | if (offset & ~mask) |
19200 | return 4; | |
19201 | return 2; | |
19202 | } | |
19203 | ||
5e77afaa PB |
19204 | /* Get the address of a symbol during relaxation. */ |
19205 | static addressT | |
5f4273c7 | 19206 | relaxed_symbol_addr (fragS *fragp, long stretch) |
5e77afaa PB |
19207 | { |
19208 | fragS *sym_frag; | |
19209 | addressT addr; | |
19210 | symbolS *sym; | |
19211 | ||
19212 | sym = fragp->fr_symbol; | |
19213 | sym_frag = symbol_get_frag (sym); | |
19214 | know (S_GET_SEGMENT (sym) != absolute_section | |
19215 | || sym_frag == &zero_address_frag); | |
19216 | addr = S_GET_VALUE (sym) + fragp->fr_offset; | |
19217 | ||
19218 | /* If frag has yet to be reached on this pass, assume it will | |
19219 | move by STRETCH just as we did. If this is not so, it will | |
19220 | be because some frag between grows, and that will force | |
19221 | another pass. */ | |
19222 | ||
19223 | if (stretch != 0 | |
19224 | && sym_frag->relax_marker != fragp->relax_marker) | |
4396b686 PB |
19225 | { |
19226 | fragS *f; | |
19227 | ||
19228 | /* Adjust stretch for any alignment frag. Note that if have | |
19229 | been expanding the earlier code, the symbol may be | |
19230 | defined in what appears to be an earlier frag. FIXME: | |
19231 | This doesn't handle the fr_subtype field, which specifies | |
19232 | a maximum number of bytes to skip when doing an | |
19233 | alignment. */ | |
19234 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
19235 | { | |
19236 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
19237 | { | |
19238 | if (stretch < 0) | |
19239 | stretch = - ((- stretch) | |
19240 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
19241 | else | |
19242 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
19243 | if (stretch == 0) | |
19244 | break; | |
19245 | } | |
19246 | } | |
19247 | if (f != NULL) | |
19248 | addr += stretch; | |
19249 | } | |
5e77afaa PB |
19250 | |
19251 | return addr; | |
19252 | } | |
19253 | ||
0110f2b8 PB |
19254 | /* Return the size of a relaxable adr pseudo-instruction or PC-relative |
19255 | load. */ | |
19256 | static int | |
5e77afaa | 19257 | relax_adr (fragS *fragp, asection *sec, long stretch) |
0110f2b8 PB |
19258 | { |
19259 | addressT addr; | |
19260 | offsetT val; | |
19261 | ||
19262 | /* Assume worst case for symbols not known to be in the same section. */ | |
974da60d NC |
19263 | if (fragp->fr_symbol == NULL |
19264 | || !S_IS_DEFINED (fragp->fr_symbol) | |
77db8e2e NC |
19265 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
19266 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
19267 | return 4; |
19268 | ||
5f4273c7 | 19269 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
19270 | addr = fragp->fr_address + fragp->fr_fix; |
19271 | addr = (addr + 4) & ~3; | |
5e77afaa | 19272 | /* Force misaligned targets to 32-bit variant. */ |
0110f2b8 | 19273 | if (val & 3) |
5e77afaa | 19274 | return 4; |
0110f2b8 PB |
19275 | val -= addr; |
19276 | if (val < 0 || val > 1020) | |
19277 | return 4; | |
19278 | return 2; | |
19279 | } | |
19280 | ||
19281 | /* Return the size of a relaxable add/sub immediate instruction. */ | |
19282 | static int | |
19283 | relax_addsub (fragS *fragp, asection *sec) | |
19284 | { | |
19285 | char *buf; | |
19286 | int op; | |
19287 | ||
19288 | buf = fragp->fr_literal + fragp->fr_fix; | |
19289 | op = bfd_get_16(sec->owner, buf); | |
19290 | if ((op & 0xf) == ((op >> 4) & 0xf)) | |
19291 | return relax_immediate (fragp, 8, 0); | |
19292 | else | |
19293 | return relax_immediate (fragp, 3, 0); | |
19294 | } | |
19295 | ||
19296 | ||
19297 | /* Return the size of a relaxable branch instruction. BITS is the | |
19298 | size of the offset field in the narrow instruction. */ | |
19299 | ||
19300 | static int | |
5e77afaa | 19301 | relax_branch (fragS *fragp, asection *sec, int bits, long stretch) |
0110f2b8 PB |
19302 | { |
19303 | addressT addr; | |
19304 | offsetT val; | |
19305 | offsetT limit; | |
19306 | ||
19307 | /* Assume worst case for symbols not known to be in the same section. */ | |
5f4273c7 | 19308 | if (!S_IS_DEFINED (fragp->fr_symbol) |
77db8e2e NC |
19309 | || sec != S_GET_SEGMENT (fragp->fr_symbol) |
19310 | || S_IS_WEAK (fragp->fr_symbol)) | |
0110f2b8 PB |
19311 | return 4; |
19312 | ||
267bf995 RR |
19313 | #ifdef OBJ_ELF |
19314 | if (S_IS_DEFINED (fragp->fr_symbol) | |
19315 | && ARM_IS_FUNC (fragp->fr_symbol)) | |
19316 | return 4; | |
0d9b4b55 NC |
19317 | |
19318 | /* PR 12532. Global symbols with default visibility might | |
19319 | be preempted, so do not relax relocations to them. */ | |
19320 | if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT) | |
19321 | && (! S_IS_LOCAL (fragp->fr_symbol))) | |
19322 | return 4; | |
267bf995 RR |
19323 | #endif |
19324 | ||
5f4273c7 | 19325 | val = relaxed_symbol_addr (fragp, stretch); |
0110f2b8 PB |
19326 | addr = fragp->fr_address + fragp->fr_fix + 4; |
19327 | val -= addr; | |
19328 | ||
19329 | /* Offset is a signed value *2 */ | |
19330 | limit = 1 << bits; | |
19331 | if (val >= limit || val < -limit) | |
19332 | return 4; | |
19333 | return 2; | |
19334 | } | |
19335 | ||
19336 | ||
19337 | /* Relax a machine dependent frag. This returns the amount by which | |
19338 | the current size of the frag should change. */ | |
19339 | ||
19340 | int | |
5e77afaa | 19341 | arm_relax_frag (asection *sec, fragS *fragp, long stretch) |
0110f2b8 PB |
19342 | { |
19343 | int oldsize; | |
19344 | int newsize; | |
19345 | ||
19346 | oldsize = fragp->fr_var; | |
19347 | switch (fragp->fr_subtype) | |
19348 | { | |
19349 | case T_MNEM_ldr_pc2: | |
5f4273c7 | 19350 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
19351 | break; |
19352 | case T_MNEM_ldr_pc: | |
19353 | case T_MNEM_ldr_sp: | |
19354 | case T_MNEM_str_sp: | |
5f4273c7 | 19355 | newsize = relax_immediate (fragp, 8, 2); |
0110f2b8 PB |
19356 | break; |
19357 | case T_MNEM_ldr: | |
19358 | case T_MNEM_str: | |
5f4273c7 | 19359 | newsize = relax_immediate (fragp, 5, 2); |
0110f2b8 PB |
19360 | break; |
19361 | case T_MNEM_ldrh: | |
19362 | case T_MNEM_strh: | |
5f4273c7 | 19363 | newsize = relax_immediate (fragp, 5, 1); |
0110f2b8 PB |
19364 | break; |
19365 | case T_MNEM_ldrb: | |
19366 | case T_MNEM_strb: | |
5f4273c7 | 19367 | newsize = relax_immediate (fragp, 5, 0); |
0110f2b8 PB |
19368 | break; |
19369 | case T_MNEM_adr: | |
5f4273c7 | 19370 | newsize = relax_adr (fragp, sec, stretch); |
0110f2b8 PB |
19371 | break; |
19372 | case T_MNEM_mov: | |
19373 | case T_MNEM_movs: | |
19374 | case T_MNEM_cmp: | |
19375 | case T_MNEM_cmn: | |
5f4273c7 | 19376 | newsize = relax_immediate (fragp, 8, 0); |
0110f2b8 PB |
19377 | break; |
19378 | case T_MNEM_b: | |
5f4273c7 | 19379 | newsize = relax_branch (fragp, sec, 11, stretch); |
0110f2b8 PB |
19380 | break; |
19381 | case T_MNEM_bcond: | |
5f4273c7 | 19382 | newsize = relax_branch (fragp, sec, 8, stretch); |
0110f2b8 PB |
19383 | break; |
19384 | case T_MNEM_add_sp: | |
19385 | case T_MNEM_add_pc: | |
19386 | newsize = relax_immediate (fragp, 8, 2); | |
19387 | break; | |
19388 | case T_MNEM_inc_sp: | |
19389 | case T_MNEM_dec_sp: | |
19390 | newsize = relax_immediate (fragp, 7, 2); | |
19391 | break; | |
19392 | case T_MNEM_addi: | |
19393 | case T_MNEM_addis: | |
19394 | case T_MNEM_subi: | |
19395 | case T_MNEM_subis: | |
19396 | newsize = relax_addsub (fragp, sec); | |
19397 | break; | |
19398 | default: | |
5f4273c7 | 19399 | abort (); |
0110f2b8 | 19400 | } |
5e77afaa PB |
19401 | |
19402 | fragp->fr_var = newsize; | |
19403 | /* Freeze wide instructions that are at or before the same location as | |
19404 | in the previous pass. This avoids infinite loops. | |
5f4273c7 NC |
19405 | Don't freeze them unconditionally because targets may be artificially |
19406 | misaligned by the expansion of preceding frags. */ | |
5e77afaa | 19407 | if (stretch <= 0 && newsize > 2) |
0110f2b8 | 19408 | { |
0110f2b8 | 19409 | md_convert_frag (sec->owner, sec, fragp); |
5f4273c7 | 19410 | frag_wane (fragp); |
0110f2b8 | 19411 | } |
5e77afaa | 19412 | |
0110f2b8 | 19413 | return newsize - oldsize; |
c19d1205 | 19414 | } |
b99bd4ef | 19415 | |
c19d1205 | 19416 | /* Round up a section size to the appropriate boundary. */ |
b99bd4ef | 19417 | |
c19d1205 ZW |
19418 | valueT |
19419 | md_section_align (segT segment ATTRIBUTE_UNUSED, | |
19420 | valueT size) | |
19421 | { | |
f0927246 NC |
19422 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
19423 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
19424 | { | |
19425 | /* For a.out, force the section size to be aligned. If we don't do | |
19426 | this, BFD will align it for us, but it will not write out the | |
19427 | final bytes of the section. This may be a bug in BFD, but it is | |
19428 | easier to fix it here since that is how the other a.out targets | |
19429 | work. */ | |
19430 | int align; | |
19431 | ||
19432 | align = bfd_get_section_alignment (stdoutput, segment); | |
19433 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
19434 | } | |
c19d1205 | 19435 | #endif |
f0927246 NC |
19436 | |
19437 | return size; | |
bfae80f2 | 19438 | } |
b99bd4ef | 19439 | |
c19d1205 ZW |
19440 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
19441 | of an rs_align_code fragment. */ | |
19442 | ||
19443 | void | |
19444 | arm_handle_align (fragS * fragP) | |
bfae80f2 | 19445 | { |
e7495e45 NS |
19446 | static char const arm_noop[2][2][4] = |
19447 | { | |
19448 | { /* ARMv1 */ | |
19449 | {0x00, 0x00, 0xa0, 0xe1}, /* LE */ | |
19450 | {0xe1, 0xa0, 0x00, 0x00}, /* BE */ | |
19451 | }, | |
19452 | { /* ARMv6k */ | |
19453 | {0x00, 0xf0, 0x20, 0xe3}, /* LE */ | |
19454 | {0xe3, 0x20, 0xf0, 0x00}, /* BE */ | |
19455 | }, | |
19456 | }; | |
19457 | static char const thumb_noop[2][2][2] = | |
19458 | { | |
19459 | { /* Thumb-1 */ | |
19460 | {0xc0, 0x46}, /* LE */ | |
19461 | {0x46, 0xc0}, /* BE */ | |
19462 | }, | |
19463 | { /* Thumb-2 */ | |
19464 | {0x00, 0xbf}, /* LE */ | |
19465 | {0xbf, 0x00} /* BE */ | |
19466 | } | |
19467 | }; | |
19468 | static char const wide_thumb_noop[2][4] = | |
19469 | { /* Wide Thumb-2 */ | |
19470 | {0xaf, 0xf3, 0x00, 0x80}, /* LE */ | |
19471 | {0xf3, 0xaf, 0x80, 0x00}, /* BE */ | |
19472 | }; | |
c921be7d | 19473 | |
e7495e45 | 19474 | unsigned bytes, fix, noop_size; |
c19d1205 ZW |
19475 | char * p; |
19476 | const char * noop; | |
e7495e45 | 19477 | const char *narrow_noop = NULL; |
cd000bff DJ |
19478 | #ifdef OBJ_ELF |
19479 | enum mstate state; | |
19480 | #endif | |
bfae80f2 | 19481 | |
c19d1205 | 19482 | if (fragP->fr_type != rs_align_code) |
bfae80f2 RE |
19483 | return; |
19484 | ||
c19d1205 ZW |
19485 | bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; |
19486 | p = fragP->fr_literal + fragP->fr_fix; | |
19487 | fix = 0; | |
bfae80f2 | 19488 | |
c19d1205 ZW |
19489 | if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) |
19490 | bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; | |
bfae80f2 | 19491 | |
cd000bff | 19492 | gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0); |
8dc2430f | 19493 | |
cd000bff | 19494 | if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED)) |
a737bd4d | 19495 | { |
e7495e45 NS |
19496 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)) |
19497 | { | |
19498 | narrow_noop = thumb_noop[1][target_big_endian]; | |
19499 | noop = wide_thumb_noop[target_big_endian]; | |
19500 | } | |
c19d1205 | 19501 | else |
e7495e45 NS |
19502 | noop = thumb_noop[0][target_big_endian]; |
19503 | noop_size = 2; | |
cd000bff DJ |
19504 | #ifdef OBJ_ELF |
19505 | state = MAP_THUMB; | |
19506 | #endif | |
7ed4c4c5 NC |
19507 | } |
19508 | else | |
19509 | { | |
e7495e45 NS |
19510 | noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0] |
19511 | [target_big_endian]; | |
19512 | noop_size = 4; | |
cd000bff DJ |
19513 | #ifdef OBJ_ELF |
19514 | state = MAP_ARM; | |
19515 | #endif | |
7ed4c4c5 | 19516 | } |
c921be7d | 19517 | |
e7495e45 | 19518 | fragP->fr_var = noop_size; |
c921be7d | 19519 | |
c19d1205 | 19520 | if (bytes & (noop_size - 1)) |
7ed4c4c5 | 19521 | { |
c19d1205 | 19522 | fix = bytes & (noop_size - 1); |
cd000bff DJ |
19523 | #ifdef OBJ_ELF |
19524 | insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix); | |
19525 | #endif | |
c19d1205 ZW |
19526 | memset (p, 0, fix); |
19527 | p += fix; | |
19528 | bytes -= fix; | |
a737bd4d | 19529 | } |
a737bd4d | 19530 | |
e7495e45 NS |
19531 | if (narrow_noop) |
19532 | { | |
19533 | if (bytes & noop_size) | |
19534 | { | |
19535 | /* Insert a narrow noop. */ | |
19536 | memcpy (p, narrow_noop, noop_size); | |
19537 | p += noop_size; | |
19538 | bytes -= noop_size; | |
19539 | fix += noop_size; | |
19540 | } | |
19541 | ||
19542 | /* Use wide noops for the remainder */ | |
19543 | noop_size = 4; | |
19544 | } | |
19545 | ||
c19d1205 | 19546 | while (bytes >= noop_size) |
a737bd4d | 19547 | { |
c19d1205 ZW |
19548 | memcpy (p, noop, noop_size); |
19549 | p += noop_size; | |
19550 | bytes -= noop_size; | |
19551 | fix += noop_size; | |
a737bd4d NC |
19552 | } |
19553 | ||
c19d1205 | 19554 | fragP->fr_fix += fix; |
a737bd4d NC |
19555 | } |
19556 | ||
c19d1205 ZW |
19557 | /* Called from md_do_align. Used to create an alignment |
19558 | frag in a code section. */ | |
19559 | ||
19560 | void | |
19561 | arm_frag_align_code (int n, int max) | |
bfae80f2 | 19562 | { |
c19d1205 | 19563 | char * p; |
7ed4c4c5 | 19564 | |
c19d1205 | 19565 | /* We assume that there will never be a requirement |
6ec8e702 | 19566 | to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */ |
c19d1205 | 19567 | if (max > MAX_MEM_FOR_RS_ALIGN_CODE) |
6ec8e702 NC |
19568 | { |
19569 | char err_msg[128]; | |
19570 | ||
19571 | sprintf (err_msg, | |
19572 | _("alignments greater than %d bytes not supported in .text sections."), | |
19573 | MAX_MEM_FOR_RS_ALIGN_CODE + 1); | |
20203fb9 | 19574 | as_fatal ("%s", err_msg); |
6ec8e702 | 19575 | } |
bfae80f2 | 19576 | |
c19d1205 ZW |
19577 | p = frag_var (rs_align_code, |
19578 | MAX_MEM_FOR_RS_ALIGN_CODE, | |
19579 | 1, | |
19580 | (relax_substateT) max, | |
19581 | (symbolS *) NULL, | |
19582 | (offsetT) n, | |
19583 | (char *) NULL); | |
19584 | *p = 0; | |
19585 | } | |
bfae80f2 | 19586 | |
8dc2430f NC |
19587 | /* Perform target specific initialisation of a frag. |
19588 | Note - despite the name this initialisation is not done when the frag | |
19589 | is created, but only when its type is assigned. A frag can be created | |
19590 | and used a long time before its type is set, so beware of assuming that | |
19591 | this initialisationis performed first. */ | |
bfae80f2 | 19592 | |
cd000bff DJ |
19593 | #ifndef OBJ_ELF |
19594 | void | |
19595 | arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED) | |
19596 | { | |
19597 | /* Record whether this frag is in an ARM or a THUMB area. */ | |
2e98972e | 19598 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; |
cd000bff DJ |
19599 | } |
19600 | ||
19601 | #else /* OBJ_ELF is defined. */ | |
c19d1205 | 19602 | void |
cd000bff | 19603 | arm_init_frag (fragS * fragP, int max_chars) |
c19d1205 | 19604 | { |
8dc2430f NC |
19605 | /* If the current ARM vs THUMB mode has not already |
19606 | been recorded into this frag then do so now. */ | |
cd000bff DJ |
19607 | if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0) |
19608 | { | |
19609 | fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED; | |
19610 | ||
19611 | /* Record a mapping symbol for alignment frags. We will delete this | |
19612 | later if the alignment ends up empty. */ | |
19613 | switch (fragP->fr_type) | |
19614 | { | |
19615 | case rs_align: | |
19616 | case rs_align_test: | |
19617 | case rs_fill: | |
19618 | mapping_state_2 (MAP_DATA, max_chars); | |
19619 | break; | |
19620 | case rs_align_code: | |
19621 | mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars); | |
19622 | break; | |
19623 | default: | |
19624 | break; | |
19625 | } | |
19626 | } | |
bfae80f2 RE |
19627 | } |
19628 | ||
c19d1205 ZW |
19629 | /* When we change sections we need to issue a new mapping symbol. */ |
19630 | ||
19631 | void | |
19632 | arm_elf_change_section (void) | |
bfae80f2 | 19633 | { |
c19d1205 ZW |
19634 | /* Link an unlinked unwind index table section to the .text section. */ |
19635 | if (elf_section_type (now_seg) == SHT_ARM_EXIDX | |
19636 | && elf_linked_to_section (now_seg) == NULL) | |
19637 | elf_linked_to_section (now_seg) = text_section; | |
bfae80f2 RE |
19638 | } |
19639 | ||
c19d1205 ZW |
19640 | int |
19641 | arm_elf_section_type (const char * str, size_t len) | |
e45d0630 | 19642 | { |
c19d1205 ZW |
19643 | if (len == 5 && strncmp (str, "exidx", 5) == 0) |
19644 | return SHT_ARM_EXIDX; | |
e45d0630 | 19645 | |
c19d1205 ZW |
19646 | return -1; |
19647 | } | |
19648 | \f | |
19649 | /* Code to deal with unwinding tables. */ | |
e45d0630 | 19650 | |
c19d1205 | 19651 | static void add_unwind_adjustsp (offsetT); |
e45d0630 | 19652 | |
5f4273c7 | 19653 | /* Generate any deferred unwind frame offset. */ |
e45d0630 | 19654 | |
bfae80f2 | 19655 | static void |
c19d1205 | 19656 | flush_pending_unwind (void) |
bfae80f2 | 19657 | { |
c19d1205 | 19658 | offsetT offset; |
bfae80f2 | 19659 | |
c19d1205 ZW |
19660 | offset = unwind.pending_offset; |
19661 | unwind.pending_offset = 0; | |
19662 | if (offset != 0) | |
19663 | add_unwind_adjustsp (offset); | |
bfae80f2 RE |
19664 | } |
19665 | ||
c19d1205 ZW |
19666 | /* Add an opcode to this list for this function. Two-byte opcodes should |
19667 | be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse | |
19668 | order. */ | |
19669 | ||
bfae80f2 | 19670 | static void |
c19d1205 | 19671 | add_unwind_opcode (valueT op, int length) |
bfae80f2 | 19672 | { |
c19d1205 ZW |
19673 | /* Add any deferred stack adjustment. */ |
19674 | if (unwind.pending_offset) | |
19675 | flush_pending_unwind (); | |
bfae80f2 | 19676 | |
c19d1205 | 19677 | unwind.sp_restored = 0; |
bfae80f2 | 19678 | |
c19d1205 | 19679 | if (unwind.opcode_count + length > unwind.opcode_alloc) |
bfae80f2 | 19680 | { |
c19d1205 ZW |
19681 | unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; |
19682 | if (unwind.opcodes) | |
21d799b5 NC |
19683 | unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes, |
19684 | unwind.opcode_alloc); | |
c19d1205 | 19685 | else |
21d799b5 | 19686 | unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc); |
bfae80f2 | 19687 | } |
c19d1205 | 19688 | while (length > 0) |
bfae80f2 | 19689 | { |
c19d1205 ZW |
19690 | length--; |
19691 | unwind.opcodes[unwind.opcode_count] = op & 0xff; | |
19692 | op >>= 8; | |
19693 | unwind.opcode_count++; | |
bfae80f2 | 19694 | } |
bfae80f2 RE |
19695 | } |
19696 | ||
c19d1205 ZW |
19697 | /* Add unwind opcodes to adjust the stack pointer. */ |
19698 | ||
bfae80f2 | 19699 | static void |
c19d1205 | 19700 | add_unwind_adjustsp (offsetT offset) |
bfae80f2 | 19701 | { |
c19d1205 | 19702 | valueT op; |
bfae80f2 | 19703 | |
c19d1205 | 19704 | if (offset > 0x200) |
bfae80f2 | 19705 | { |
c19d1205 ZW |
19706 | /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ |
19707 | char bytes[5]; | |
19708 | int n; | |
19709 | valueT o; | |
bfae80f2 | 19710 | |
c19d1205 ZW |
19711 | /* Long form: 0xb2, uleb128. */ |
19712 | /* This might not fit in a word so add the individual bytes, | |
19713 | remembering the list is built in reverse order. */ | |
19714 | o = (valueT) ((offset - 0x204) >> 2); | |
19715 | if (o == 0) | |
19716 | add_unwind_opcode (0, 1); | |
bfae80f2 | 19717 | |
c19d1205 ZW |
19718 | /* Calculate the uleb128 encoding of the offset. */ |
19719 | n = 0; | |
19720 | while (o) | |
19721 | { | |
19722 | bytes[n] = o & 0x7f; | |
19723 | o >>= 7; | |
19724 | if (o) | |
19725 | bytes[n] |= 0x80; | |
19726 | n++; | |
19727 | } | |
19728 | /* Add the insn. */ | |
19729 | for (; n; n--) | |
19730 | add_unwind_opcode (bytes[n - 1], 1); | |
19731 | add_unwind_opcode (0xb2, 1); | |
19732 | } | |
19733 | else if (offset > 0x100) | |
bfae80f2 | 19734 | { |
c19d1205 ZW |
19735 | /* Two short opcodes. */ |
19736 | add_unwind_opcode (0x3f, 1); | |
19737 | op = (offset - 0x104) >> 2; | |
19738 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19739 | } |
c19d1205 ZW |
19740 | else if (offset > 0) |
19741 | { | |
19742 | /* Short opcode. */ | |
19743 | op = (offset - 4) >> 2; | |
19744 | add_unwind_opcode (op, 1); | |
19745 | } | |
19746 | else if (offset < 0) | |
bfae80f2 | 19747 | { |
c19d1205 ZW |
19748 | offset = -offset; |
19749 | while (offset > 0x100) | |
bfae80f2 | 19750 | { |
c19d1205 ZW |
19751 | add_unwind_opcode (0x7f, 1); |
19752 | offset -= 0x100; | |
bfae80f2 | 19753 | } |
c19d1205 ZW |
19754 | op = ((offset - 4) >> 2) | 0x40; |
19755 | add_unwind_opcode (op, 1); | |
bfae80f2 | 19756 | } |
bfae80f2 RE |
19757 | } |
19758 | ||
c19d1205 ZW |
19759 | /* Finish the list of unwind opcodes for this function. */ |
19760 | static void | |
19761 | finish_unwind_opcodes (void) | |
bfae80f2 | 19762 | { |
c19d1205 | 19763 | valueT op; |
bfae80f2 | 19764 | |
c19d1205 | 19765 | if (unwind.fp_used) |
bfae80f2 | 19766 | { |
708587a4 | 19767 | /* Adjust sp as necessary. */ |
c19d1205 ZW |
19768 | unwind.pending_offset += unwind.fp_offset - unwind.frame_size; |
19769 | flush_pending_unwind (); | |
bfae80f2 | 19770 | |
c19d1205 ZW |
19771 | /* After restoring sp from the frame pointer. */ |
19772 | op = 0x90 | unwind.fp_reg; | |
19773 | add_unwind_opcode (op, 1); | |
19774 | } | |
19775 | else | |
19776 | flush_pending_unwind (); | |
bfae80f2 RE |
19777 | } |
19778 | ||
bfae80f2 | 19779 | |
c19d1205 ZW |
19780 | /* Start an exception table entry. If idx is nonzero this is an index table |
19781 | entry. */ | |
bfae80f2 RE |
19782 | |
19783 | static void | |
c19d1205 | 19784 | start_unwind_section (const segT text_seg, int idx) |
bfae80f2 | 19785 | { |
c19d1205 ZW |
19786 | const char * text_name; |
19787 | const char * prefix; | |
19788 | const char * prefix_once; | |
19789 | const char * group_name; | |
19790 | size_t prefix_len; | |
19791 | size_t text_len; | |
19792 | char * sec_name; | |
19793 | size_t sec_name_len; | |
19794 | int type; | |
19795 | int flags; | |
19796 | int linkonce; | |
bfae80f2 | 19797 | |
c19d1205 | 19798 | if (idx) |
bfae80f2 | 19799 | { |
c19d1205 ZW |
19800 | prefix = ELF_STRING_ARM_unwind; |
19801 | prefix_once = ELF_STRING_ARM_unwind_once; | |
19802 | type = SHT_ARM_EXIDX; | |
bfae80f2 | 19803 | } |
c19d1205 | 19804 | else |
bfae80f2 | 19805 | { |
c19d1205 ZW |
19806 | prefix = ELF_STRING_ARM_unwind_info; |
19807 | prefix_once = ELF_STRING_ARM_unwind_info_once; | |
19808 | type = SHT_PROGBITS; | |
bfae80f2 RE |
19809 | } |
19810 | ||
c19d1205 ZW |
19811 | text_name = segment_name (text_seg); |
19812 | if (streq (text_name, ".text")) | |
19813 | text_name = ""; | |
19814 | ||
19815 | if (strncmp (text_name, ".gnu.linkonce.t.", | |
19816 | strlen (".gnu.linkonce.t.")) == 0) | |
bfae80f2 | 19817 | { |
c19d1205 ZW |
19818 | prefix = prefix_once; |
19819 | text_name += strlen (".gnu.linkonce.t."); | |
bfae80f2 RE |
19820 | } |
19821 | ||
c19d1205 ZW |
19822 | prefix_len = strlen (prefix); |
19823 | text_len = strlen (text_name); | |
19824 | sec_name_len = prefix_len + text_len; | |
21d799b5 | 19825 | sec_name = (char *) xmalloc (sec_name_len + 1); |
c19d1205 ZW |
19826 | memcpy (sec_name, prefix, prefix_len); |
19827 | memcpy (sec_name + prefix_len, text_name, text_len); | |
19828 | sec_name[prefix_len + text_len] = '\0'; | |
bfae80f2 | 19829 | |
c19d1205 ZW |
19830 | flags = SHF_ALLOC; |
19831 | linkonce = 0; | |
19832 | group_name = 0; | |
bfae80f2 | 19833 | |
c19d1205 ZW |
19834 | /* Handle COMDAT group. */ |
19835 | if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) | |
bfae80f2 | 19836 | { |
c19d1205 ZW |
19837 | group_name = elf_group_name (text_seg); |
19838 | if (group_name == NULL) | |
19839 | { | |
bd3ba5d1 | 19840 | as_bad (_("Group section `%s' has no group signature"), |
c19d1205 ZW |
19841 | segment_name (text_seg)); |
19842 | ignore_rest_of_line (); | |
19843 | return; | |
19844 | } | |
19845 | flags |= SHF_GROUP; | |
19846 | linkonce = 1; | |
bfae80f2 RE |
19847 | } |
19848 | ||
c19d1205 | 19849 | obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); |
bfae80f2 | 19850 | |
5f4273c7 | 19851 | /* Set the section link for index tables. */ |
c19d1205 ZW |
19852 | if (idx) |
19853 | elf_linked_to_section (now_seg) = text_seg; | |
bfae80f2 RE |
19854 | } |
19855 | ||
bfae80f2 | 19856 | |
c19d1205 ZW |
19857 | /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional |
19858 | personality routine data. Returns zero, or the index table value for | |
19859 | and inline entry. */ | |
19860 | ||
19861 | static valueT | |
19862 | create_unwind_entry (int have_data) | |
bfae80f2 | 19863 | { |
c19d1205 ZW |
19864 | int size; |
19865 | addressT where; | |
19866 | char *ptr; | |
19867 | /* The current word of data. */ | |
19868 | valueT data; | |
19869 | /* The number of bytes left in this word. */ | |
19870 | int n; | |
bfae80f2 | 19871 | |
c19d1205 | 19872 | finish_unwind_opcodes (); |
bfae80f2 | 19873 | |
c19d1205 ZW |
19874 | /* Remember the current text section. */ |
19875 | unwind.saved_seg = now_seg; | |
19876 | unwind.saved_subseg = now_subseg; | |
bfae80f2 | 19877 | |
c19d1205 | 19878 | start_unwind_section (now_seg, 0); |
bfae80f2 | 19879 | |
c19d1205 | 19880 | if (unwind.personality_routine == NULL) |
bfae80f2 | 19881 | { |
c19d1205 ZW |
19882 | if (unwind.personality_index == -2) |
19883 | { | |
19884 | if (have_data) | |
5f4273c7 | 19885 | as_bad (_("handlerdata in cantunwind frame")); |
c19d1205 ZW |
19886 | return 1; /* EXIDX_CANTUNWIND. */ |
19887 | } | |
bfae80f2 | 19888 | |
c19d1205 ZW |
19889 | /* Use a default personality routine if none is specified. */ |
19890 | if (unwind.personality_index == -1) | |
19891 | { | |
19892 | if (unwind.opcode_count > 3) | |
19893 | unwind.personality_index = 1; | |
19894 | else | |
19895 | unwind.personality_index = 0; | |
19896 | } | |
bfae80f2 | 19897 | |
c19d1205 ZW |
19898 | /* Space for the personality routine entry. */ |
19899 | if (unwind.personality_index == 0) | |
19900 | { | |
19901 | if (unwind.opcode_count > 3) | |
19902 | as_bad (_("too many unwind opcodes for personality routine 0")); | |
bfae80f2 | 19903 | |
c19d1205 ZW |
19904 | if (!have_data) |
19905 | { | |
19906 | /* All the data is inline in the index table. */ | |
19907 | data = 0x80; | |
19908 | n = 3; | |
19909 | while (unwind.opcode_count > 0) | |
19910 | { | |
19911 | unwind.opcode_count--; | |
19912 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19913 | n--; | |
19914 | } | |
bfae80f2 | 19915 | |
c19d1205 ZW |
19916 | /* Pad with "finish" opcodes. */ |
19917 | while (n--) | |
19918 | data = (data << 8) | 0xb0; | |
bfae80f2 | 19919 | |
c19d1205 ZW |
19920 | return data; |
19921 | } | |
19922 | size = 0; | |
19923 | } | |
19924 | else | |
19925 | /* We get two opcodes "free" in the first word. */ | |
19926 | size = unwind.opcode_count - 2; | |
19927 | } | |
19928 | else | |
19929 | /* An extra byte is required for the opcode count. */ | |
19930 | size = unwind.opcode_count + 1; | |
bfae80f2 | 19931 | |
c19d1205 ZW |
19932 | size = (size + 3) >> 2; |
19933 | if (size > 0xff) | |
19934 | as_bad (_("too many unwind opcodes")); | |
bfae80f2 | 19935 | |
c19d1205 ZW |
19936 | frag_align (2, 0, 0); |
19937 | record_alignment (now_seg, 2); | |
19938 | unwind.table_entry = expr_build_dot (); | |
19939 | ||
19940 | /* Allocate the table entry. */ | |
19941 | ptr = frag_more ((size << 2) + 4); | |
19942 | where = frag_now_fix () - ((size << 2) + 4); | |
bfae80f2 | 19943 | |
c19d1205 | 19944 | switch (unwind.personality_index) |
bfae80f2 | 19945 | { |
c19d1205 ZW |
19946 | case -1: |
19947 | /* ??? Should this be a PLT generating relocation? */ | |
19948 | /* Custom personality routine. */ | |
19949 | fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, | |
19950 | BFD_RELOC_ARM_PREL31); | |
bfae80f2 | 19951 | |
c19d1205 ZW |
19952 | where += 4; |
19953 | ptr += 4; | |
bfae80f2 | 19954 | |
c19d1205 ZW |
19955 | /* Set the first byte to the number of additional words. */ |
19956 | data = size - 1; | |
19957 | n = 3; | |
19958 | break; | |
bfae80f2 | 19959 | |
c19d1205 ZW |
19960 | /* ABI defined personality routines. */ |
19961 | case 0: | |
19962 | /* Three opcodes bytes are packed into the first word. */ | |
19963 | data = 0x80; | |
19964 | n = 3; | |
19965 | break; | |
bfae80f2 | 19966 | |
c19d1205 ZW |
19967 | case 1: |
19968 | case 2: | |
19969 | /* The size and first two opcode bytes go in the first word. */ | |
19970 | data = ((0x80 + unwind.personality_index) << 8) | size; | |
19971 | n = 2; | |
19972 | break; | |
bfae80f2 | 19973 | |
c19d1205 ZW |
19974 | default: |
19975 | /* Should never happen. */ | |
19976 | abort (); | |
19977 | } | |
bfae80f2 | 19978 | |
c19d1205 ZW |
19979 | /* Pack the opcodes into words (MSB first), reversing the list at the same |
19980 | time. */ | |
19981 | while (unwind.opcode_count > 0) | |
19982 | { | |
19983 | if (n == 0) | |
19984 | { | |
19985 | md_number_to_chars (ptr, data, 4); | |
19986 | ptr += 4; | |
19987 | n = 4; | |
19988 | data = 0; | |
19989 | } | |
19990 | unwind.opcode_count--; | |
19991 | n--; | |
19992 | data = (data << 8) | unwind.opcodes[unwind.opcode_count]; | |
19993 | } | |
19994 | ||
19995 | /* Finish off the last word. */ | |
19996 | if (n < 4) | |
19997 | { | |
19998 | /* Pad with "finish" opcodes. */ | |
19999 | while (n--) | |
20000 | data = (data << 8) | 0xb0; | |
20001 | ||
20002 | md_number_to_chars (ptr, data, 4); | |
20003 | } | |
20004 | ||
20005 | if (!have_data) | |
20006 | { | |
20007 | /* Add an empty descriptor if there is no user-specified data. */ | |
20008 | ptr = frag_more (4); | |
20009 | md_number_to_chars (ptr, 0, 4); | |
20010 | } | |
20011 | ||
20012 | return 0; | |
bfae80f2 RE |
20013 | } |
20014 | ||
f0927246 NC |
20015 | |
20016 | /* Initialize the DWARF-2 unwind information for this procedure. */ | |
20017 | ||
20018 | void | |
20019 | tc_arm_frame_initial_instructions (void) | |
20020 | { | |
20021 | cfi_add_CFA_def_cfa (REG_SP, 0); | |
20022 | } | |
20023 | #endif /* OBJ_ELF */ | |
20024 | ||
c19d1205 ZW |
20025 | /* Convert REGNAME to a DWARF-2 register number. */ |
20026 | ||
20027 | int | |
1df69f4f | 20028 | tc_arm_regname_to_dw2regnum (char *regname) |
bfae80f2 | 20029 | { |
1df69f4f | 20030 | int reg = arm_reg_parse (®name, REG_TYPE_RN); |
c19d1205 ZW |
20031 | |
20032 | if (reg == FAIL) | |
20033 | return -1; | |
20034 | ||
20035 | return reg; | |
bfae80f2 RE |
20036 | } |
20037 | ||
f0927246 | 20038 | #ifdef TE_PE |
c19d1205 | 20039 | void |
f0927246 | 20040 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
bfae80f2 | 20041 | { |
91d6fa6a | 20042 | expressionS exp; |
bfae80f2 | 20043 | |
91d6fa6a NC |
20044 | exp.X_op = O_secrel; |
20045 | exp.X_add_symbol = symbol; | |
20046 | exp.X_add_number = 0; | |
20047 | emit_expr (&exp, size); | |
f0927246 NC |
20048 | } |
20049 | #endif | |
bfae80f2 | 20050 | |
c19d1205 | 20051 | /* MD interface: Symbol and relocation handling. */ |
bfae80f2 | 20052 | |
2fc8bdac ZW |
20053 | /* Return the address within the segment that a PC-relative fixup is |
20054 | relative to. For ARM, PC-relative fixups applied to instructions | |
20055 | are generally relative to the location of the fixup plus 8 bytes. | |
20056 | Thumb branches are offset by 4, and Thumb loads relative to PC | |
20057 | require special handling. */ | |
bfae80f2 | 20058 | |
c19d1205 | 20059 | long |
2fc8bdac | 20060 | md_pcrel_from_section (fixS * fixP, segT seg) |
bfae80f2 | 20061 | { |
2fc8bdac ZW |
20062 | offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; |
20063 | ||
20064 | /* If this is pc-relative and we are going to emit a relocation | |
20065 | then we just want to put out any pipeline compensation that the linker | |
53baae48 NC |
20066 | will need. Otherwise we want to use the calculated base. |
20067 | For WinCE we skip the bias for externals as well, since this | |
20068 | is how the MS ARM-CE assembler behaves and we want to be compatible. */ | |
5f4273c7 | 20069 | if (fixP->fx_pcrel |
2fc8bdac | 20070 | && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) |
53baae48 NC |
20071 | || (arm_force_relocation (fixP) |
20072 | #ifdef TE_WINCE | |
20073 | && !S_IS_EXTERNAL (fixP->fx_addsy) | |
20074 | #endif | |
20075 | ))) | |
2fc8bdac | 20076 | base = 0; |
bfae80f2 | 20077 | |
267bf995 | 20078 | |
c19d1205 | 20079 | switch (fixP->fx_r_type) |
bfae80f2 | 20080 | { |
2fc8bdac ZW |
20081 | /* PC relative addressing on the Thumb is slightly odd as the |
20082 | bottom two bits of the PC are forced to zero for the | |
20083 | calculation. This happens *after* application of the | |
20084 | pipeline offset. However, Thumb adrl already adjusts for | |
20085 | this, so we need not do it again. */ | |
c19d1205 | 20086 | case BFD_RELOC_ARM_THUMB_ADD: |
2fc8bdac | 20087 | return base & ~3; |
c19d1205 ZW |
20088 | |
20089 | case BFD_RELOC_ARM_THUMB_OFFSET: | |
20090 | case BFD_RELOC_ARM_T32_OFFSET_IMM: | |
e9f89963 | 20091 | case BFD_RELOC_ARM_T32_ADD_PC12: |
8f06b2d8 | 20092 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
2fc8bdac | 20093 | return (base + 4) & ~3; |
c19d1205 | 20094 | |
2fc8bdac ZW |
20095 | /* Thumb branches are simply offset by +4. */ |
20096 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
20097 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
20098 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
20099 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
2fc8bdac | 20100 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
2fc8bdac | 20101 | return base + 4; |
bfae80f2 | 20102 | |
267bf995 | 20103 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
486499d0 CL |
20104 | if (fixP->fx_addsy |
20105 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20106 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20107 | && ARM_IS_FUNC (fixP->fx_addsy) |
20108 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20109 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
20110 | return base + 4; | |
20111 | ||
00adf2d4 JB |
20112 | /* BLX is like branches above, but forces the low two bits of PC to |
20113 | zero. */ | |
486499d0 CL |
20114 | case BFD_RELOC_THUMB_PCREL_BLX: |
20115 | if (fixP->fx_addsy | |
20116 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20117 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20118 | && THUMB_IS_FUNC (fixP->fx_addsy) |
20119 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20120 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
00adf2d4 JB |
20121 | return (base + 4) & ~3; |
20122 | ||
2fc8bdac ZW |
20123 | /* ARM mode branches are offset by +8. However, the Windows CE |
20124 | loader expects the relocation not to take this into account. */ | |
267bf995 | 20125 | case BFD_RELOC_ARM_PCREL_BLX: |
486499d0 CL |
20126 | if (fixP->fx_addsy |
20127 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20128 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20129 | && ARM_IS_FUNC (fixP->fx_addsy) |
20130 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20131 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 20132 | return base + 8; |
267bf995 | 20133 | |
486499d0 CL |
20134 | case BFD_RELOC_ARM_PCREL_CALL: |
20135 | if (fixP->fx_addsy | |
20136 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 20137 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20138 | && THUMB_IS_FUNC (fixP->fx_addsy) |
20139 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
20140 | base = fixP->fx_where + fixP->fx_frag->fr_address; | |
486499d0 | 20141 | return base + 8; |
267bf995 | 20142 | |
2fc8bdac | 20143 | case BFD_RELOC_ARM_PCREL_BRANCH: |
39b41c9c | 20144 | case BFD_RELOC_ARM_PCREL_JUMP: |
2fc8bdac | 20145 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 20146 | #ifdef TE_WINCE |
5f4273c7 | 20147 | /* When handling fixups immediately, because we have already |
53baae48 NC |
20148 | discovered the value of a symbol, or the address of the frag involved |
20149 | we must account for the offset by +8, as the OS loader will never see the reloc. | |
20150 | see fixup_segment() in write.c | |
20151 | The S_IS_EXTERNAL test handles the case of global symbols. | |
20152 | Those need the calculated base, not just the pipe compensation the linker will need. */ | |
20153 | if (fixP->fx_pcrel | |
20154 | && fixP->fx_addsy != NULL | |
20155 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
20156 | && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) | |
20157 | return base + 8; | |
2fc8bdac | 20158 | return base; |
c19d1205 | 20159 | #else |
2fc8bdac | 20160 | return base + 8; |
c19d1205 | 20161 | #endif |
2fc8bdac | 20162 | |
267bf995 | 20163 | |
2fc8bdac ZW |
20164 | /* ARM mode loads relative to PC are also offset by +8. Unlike |
20165 | branches, the Windows CE loader *does* expect the relocation | |
20166 | to take this into account. */ | |
20167 | case BFD_RELOC_ARM_OFFSET_IMM: | |
20168 | case BFD_RELOC_ARM_OFFSET_IMM8: | |
20169 | case BFD_RELOC_ARM_HWLITERAL: | |
20170 | case BFD_RELOC_ARM_LITERAL: | |
20171 | case BFD_RELOC_ARM_CP_OFF_IMM: | |
20172 | return base + 8; | |
20173 | ||
20174 | ||
20175 | /* Other PC-relative relocations are un-offset. */ | |
20176 | default: | |
20177 | return base; | |
20178 | } | |
bfae80f2 RE |
20179 | } |
20180 | ||
c19d1205 ZW |
20181 | /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. |
20182 | Otherwise we have no need to default values of symbols. */ | |
20183 | ||
20184 | symbolS * | |
20185 | md_undefined_symbol (char * name ATTRIBUTE_UNUSED) | |
bfae80f2 | 20186 | { |
c19d1205 ZW |
20187 | #ifdef OBJ_ELF |
20188 | if (name[0] == '_' && name[1] == 'G' | |
20189 | && streq (name, GLOBAL_OFFSET_TABLE_NAME)) | |
20190 | { | |
20191 | if (!GOT_symbol) | |
20192 | { | |
20193 | if (symbol_find (name)) | |
bd3ba5d1 | 20194 | as_bad (_("GOT already in the symbol table")); |
bfae80f2 | 20195 | |
c19d1205 ZW |
20196 | GOT_symbol = symbol_new (name, undefined_section, |
20197 | (valueT) 0, & zero_address_frag); | |
20198 | } | |
bfae80f2 | 20199 | |
c19d1205 | 20200 | return GOT_symbol; |
bfae80f2 | 20201 | } |
c19d1205 | 20202 | #endif |
bfae80f2 | 20203 | |
c921be7d | 20204 | return NULL; |
bfae80f2 RE |
20205 | } |
20206 | ||
55cf6793 | 20207 | /* Subroutine of md_apply_fix. Check to see if an immediate can be |
c19d1205 ZW |
20208 | computed as two separate immediate values, added together. We |
20209 | already know that this value cannot be computed by just one ARM | |
20210 | instruction. */ | |
20211 | ||
20212 | static unsigned int | |
20213 | validate_immediate_twopart (unsigned int val, | |
20214 | unsigned int * highpart) | |
bfae80f2 | 20215 | { |
c19d1205 ZW |
20216 | unsigned int a; |
20217 | unsigned int i; | |
bfae80f2 | 20218 | |
c19d1205 ZW |
20219 | for (i = 0; i < 32; i += 2) |
20220 | if (((a = rotate_left (val, i)) & 0xff) != 0) | |
20221 | { | |
20222 | if (a & 0xff00) | |
20223 | { | |
20224 | if (a & ~ 0xffff) | |
20225 | continue; | |
20226 | * highpart = (a >> 8) | ((i + 24) << 7); | |
20227 | } | |
20228 | else if (a & 0xff0000) | |
20229 | { | |
20230 | if (a & 0xff000000) | |
20231 | continue; | |
20232 | * highpart = (a >> 16) | ((i + 16) << 7); | |
20233 | } | |
20234 | else | |
20235 | { | |
9c2799c2 | 20236 | gas_assert (a & 0xff000000); |
c19d1205 ZW |
20237 | * highpart = (a >> 24) | ((i + 8) << 7); |
20238 | } | |
bfae80f2 | 20239 | |
c19d1205 ZW |
20240 | return (a & 0xff) | (i << 7); |
20241 | } | |
bfae80f2 | 20242 | |
c19d1205 | 20243 | return FAIL; |
bfae80f2 RE |
20244 | } |
20245 | ||
c19d1205 ZW |
20246 | static int |
20247 | validate_offset_imm (unsigned int val, int hwse) | |
20248 | { | |
20249 | if ((hwse && val > 255) || val > 4095) | |
20250 | return FAIL; | |
20251 | return val; | |
20252 | } | |
bfae80f2 | 20253 | |
55cf6793 | 20254 | /* Subroutine of md_apply_fix. Do those data_ops which can take a |
c19d1205 ZW |
20255 | negative immediate constant by altering the instruction. A bit of |
20256 | a hack really. | |
20257 | MOV <-> MVN | |
20258 | AND <-> BIC | |
20259 | ADC <-> SBC | |
20260 | by inverting the second operand, and | |
20261 | ADD <-> SUB | |
20262 | CMP <-> CMN | |
20263 | by negating the second operand. */ | |
bfae80f2 | 20264 | |
c19d1205 ZW |
20265 | static int |
20266 | negate_data_op (unsigned long * instruction, | |
20267 | unsigned long value) | |
bfae80f2 | 20268 | { |
c19d1205 ZW |
20269 | int op, new_inst; |
20270 | unsigned long negated, inverted; | |
bfae80f2 | 20271 | |
c19d1205 ZW |
20272 | negated = encode_arm_immediate (-value); |
20273 | inverted = encode_arm_immediate (~value); | |
bfae80f2 | 20274 | |
c19d1205 ZW |
20275 | op = (*instruction >> DATA_OP_SHIFT) & 0xf; |
20276 | switch (op) | |
bfae80f2 | 20277 | { |
c19d1205 ZW |
20278 | /* First negates. */ |
20279 | case OPCODE_SUB: /* ADD <-> SUB */ | |
20280 | new_inst = OPCODE_ADD; | |
20281 | value = negated; | |
20282 | break; | |
bfae80f2 | 20283 | |
c19d1205 ZW |
20284 | case OPCODE_ADD: |
20285 | new_inst = OPCODE_SUB; | |
20286 | value = negated; | |
20287 | break; | |
bfae80f2 | 20288 | |
c19d1205 ZW |
20289 | case OPCODE_CMP: /* CMP <-> CMN */ |
20290 | new_inst = OPCODE_CMN; | |
20291 | value = negated; | |
20292 | break; | |
bfae80f2 | 20293 | |
c19d1205 ZW |
20294 | case OPCODE_CMN: |
20295 | new_inst = OPCODE_CMP; | |
20296 | value = negated; | |
20297 | break; | |
bfae80f2 | 20298 | |
c19d1205 ZW |
20299 | /* Now Inverted ops. */ |
20300 | case OPCODE_MOV: /* MOV <-> MVN */ | |
20301 | new_inst = OPCODE_MVN; | |
20302 | value = inverted; | |
20303 | break; | |
bfae80f2 | 20304 | |
c19d1205 ZW |
20305 | case OPCODE_MVN: |
20306 | new_inst = OPCODE_MOV; | |
20307 | value = inverted; | |
20308 | break; | |
bfae80f2 | 20309 | |
c19d1205 ZW |
20310 | case OPCODE_AND: /* AND <-> BIC */ |
20311 | new_inst = OPCODE_BIC; | |
20312 | value = inverted; | |
20313 | break; | |
bfae80f2 | 20314 | |
c19d1205 ZW |
20315 | case OPCODE_BIC: |
20316 | new_inst = OPCODE_AND; | |
20317 | value = inverted; | |
20318 | break; | |
bfae80f2 | 20319 | |
c19d1205 ZW |
20320 | case OPCODE_ADC: /* ADC <-> SBC */ |
20321 | new_inst = OPCODE_SBC; | |
20322 | value = inverted; | |
20323 | break; | |
bfae80f2 | 20324 | |
c19d1205 ZW |
20325 | case OPCODE_SBC: |
20326 | new_inst = OPCODE_ADC; | |
20327 | value = inverted; | |
20328 | break; | |
bfae80f2 | 20329 | |
c19d1205 ZW |
20330 | /* We cannot do anything. */ |
20331 | default: | |
20332 | return FAIL; | |
b99bd4ef NC |
20333 | } |
20334 | ||
c19d1205 ZW |
20335 | if (value == (unsigned) FAIL) |
20336 | return FAIL; | |
20337 | ||
20338 | *instruction &= OPCODE_MASK; | |
20339 | *instruction |= new_inst << DATA_OP_SHIFT; | |
20340 | return value; | |
b99bd4ef NC |
20341 | } |
20342 | ||
ef8d22e6 PB |
20343 | /* Like negate_data_op, but for Thumb-2. */ |
20344 | ||
20345 | static unsigned int | |
16dd5e42 | 20346 | thumb32_negate_data_op (offsetT *instruction, unsigned int value) |
ef8d22e6 PB |
20347 | { |
20348 | int op, new_inst; | |
20349 | int rd; | |
16dd5e42 | 20350 | unsigned int negated, inverted; |
ef8d22e6 PB |
20351 | |
20352 | negated = encode_thumb32_immediate (-value); | |
20353 | inverted = encode_thumb32_immediate (~value); | |
20354 | ||
20355 | rd = (*instruction >> 8) & 0xf; | |
20356 | op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; | |
20357 | switch (op) | |
20358 | { | |
20359 | /* ADD <-> SUB. Includes CMP <-> CMN. */ | |
20360 | case T2_OPCODE_SUB: | |
20361 | new_inst = T2_OPCODE_ADD; | |
20362 | value = negated; | |
20363 | break; | |
20364 | ||
20365 | case T2_OPCODE_ADD: | |
20366 | new_inst = T2_OPCODE_SUB; | |
20367 | value = negated; | |
20368 | break; | |
20369 | ||
20370 | /* ORR <-> ORN. Includes MOV <-> MVN. */ | |
20371 | case T2_OPCODE_ORR: | |
20372 | new_inst = T2_OPCODE_ORN; | |
20373 | value = inverted; | |
20374 | break; | |
20375 | ||
20376 | case T2_OPCODE_ORN: | |
20377 | new_inst = T2_OPCODE_ORR; | |
20378 | value = inverted; | |
20379 | break; | |
20380 | ||
20381 | /* AND <-> BIC. TST has no inverted equivalent. */ | |
20382 | case T2_OPCODE_AND: | |
20383 | new_inst = T2_OPCODE_BIC; | |
20384 | if (rd == 15) | |
20385 | value = FAIL; | |
20386 | else | |
20387 | value = inverted; | |
20388 | break; | |
20389 | ||
20390 | case T2_OPCODE_BIC: | |
20391 | new_inst = T2_OPCODE_AND; | |
20392 | value = inverted; | |
20393 | break; | |
20394 | ||
20395 | /* ADC <-> SBC */ | |
20396 | case T2_OPCODE_ADC: | |
20397 | new_inst = T2_OPCODE_SBC; | |
20398 | value = inverted; | |
20399 | break; | |
20400 | ||
20401 | case T2_OPCODE_SBC: | |
20402 | new_inst = T2_OPCODE_ADC; | |
20403 | value = inverted; | |
20404 | break; | |
20405 | ||
20406 | /* We cannot do anything. */ | |
20407 | default: | |
20408 | return FAIL; | |
20409 | } | |
20410 | ||
16dd5e42 | 20411 | if (value == (unsigned int)FAIL) |
ef8d22e6 PB |
20412 | return FAIL; |
20413 | ||
20414 | *instruction &= T2_OPCODE_MASK; | |
20415 | *instruction |= new_inst << T2_DATA_OP_SHIFT; | |
20416 | return value; | |
20417 | } | |
20418 | ||
8f06b2d8 PB |
20419 | /* Read a 32-bit thumb instruction from buf. */ |
20420 | static unsigned long | |
20421 | get_thumb32_insn (char * buf) | |
20422 | { | |
20423 | unsigned long insn; | |
20424 | insn = md_chars_to_number (buf, THUMB_SIZE) << 16; | |
20425 | insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20426 | ||
20427 | return insn; | |
20428 | } | |
20429 | ||
a8bc6c78 PB |
20430 | |
20431 | /* We usually want to set the low bit on the address of thumb function | |
20432 | symbols. In particular .word foo - . should have the low bit set. | |
20433 | Generic code tries to fold the difference of two symbols to | |
20434 | a constant. Prevent this and force a relocation when the first symbols | |
20435 | is a thumb function. */ | |
c921be7d NC |
20436 | |
20437 | bfd_boolean | |
a8bc6c78 PB |
20438 | arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) |
20439 | { | |
20440 | if (op == O_subtract | |
20441 | && l->X_op == O_symbol | |
20442 | && r->X_op == O_symbol | |
20443 | && THUMB_IS_FUNC (l->X_add_symbol)) | |
20444 | { | |
20445 | l->X_op = O_subtract; | |
20446 | l->X_op_symbol = r->X_add_symbol; | |
20447 | l->X_add_number -= r->X_add_number; | |
c921be7d | 20448 | return TRUE; |
a8bc6c78 | 20449 | } |
c921be7d | 20450 | |
a8bc6c78 | 20451 | /* Process as normal. */ |
c921be7d | 20452 | return FALSE; |
a8bc6c78 PB |
20453 | } |
20454 | ||
4a42ebbc RR |
20455 | /* Encode Thumb2 unconditional branches and calls. The encoding |
20456 | for the 2 are identical for the immediate values. */ | |
20457 | ||
20458 | static void | |
20459 | encode_thumb2_b_bl_offset (char * buf, offsetT value) | |
20460 | { | |
20461 | #define T2I1I2MASK ((1 << 13) | (1 << 11)) | |
20462 | offsetT newval; | |
20463 | offsetT newval2; | |
20464 | addressT S, I1, I2, lo, hi; | |
20465 | ||
20466 | S = (value >> 24) & 0x01; | |
20467 | I1 = (value >> 23) & 0x01; | |
20468 | I2 = (value >> 22) & 0x01; | |
20469 | hi = (value >> 12) & 0x3ff; | |
20470 | lo = (value >> 1) & 0x7ff; | |
20471 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20472 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
20473 | newval |= (S << 10) | hi; | |
20474 | newval2 &= ~T2I1I2MASK; | |
20475 | newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK; | |
20476 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20477 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
20478 | } | |
20479 | ||
c19d1205 | 20480 | void |
55cf6793 | 20481 | md_apply_fix (fixS * fixP, |
c19d1205 ZW |
20482 | valueT * valP, |
20483 | segT seg) | |
20484 | { | |
20485 | offsetT value = * valP; | |
20486 | offsetT newval; | |
20487 | unsigned int newimm; | |
20488 | unsigned long temp; | |
20489 | int sign; | |
20490 | char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
b99bd4ef | 20491 | |
9c2799c2 | 20492 | gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); |
b99bd4ef | 20493 | |
c19d1205 | 20494 | /* Note whether this will delete the relocation. */ |
4962c51a | 20495 | |
c19d1205 ZW |
20496 | if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) |
20497 | fixP->fx_done = 1; | |
b99bd4ef | 20498 | |
adbaf948 | 20499 | /* On a 64-bit host, silently truncate 'value' to 32 bits for |
5f4273c7 | 20500 | consistency with the behaviour on 32-bit hosts. Remember value |
adbaf948 ZW |
20501 | for emit_reloc. */ |
20502 | value &= 0xffffffff; | |
20503 | value ^= 0x80000000; | |
5f4273c7 | 20504 | value -= 0x80000000; |
adbaf948 ZW |
20505 | |
20506 | *valP = value; | |
c19d1205 | 20507 | fixP->fx_addnumber = value; |
b99bd4ef | 20508 | |
adbaf948 ZW |
20509 | /* Same treatment for fixP->fx_offset. */ |
20510 | fixP->fx_offset &= 0xffffffff; | |
20511 | fixP->fx_offset ^= 0x80000000; | |
20512 | fixP->fx_offset -= 0x80000000; | |
20513 | ||
c19d1205 | 20514 | switch (fixP->fx_r_type) |
b99bd4ef | 20515 | { |
c19d1205 ZW |
20516 | case BFD_RELOC_NONE: |
20517 | /* This will need to go in the object file. */ | |
20518 | fixP->fx_done = 0; | |
20519 | break; | |
b99bd4ef | 20520 | |
c19d1205 ZW |
20521 | case BFD_RELOC_ARM_IMMEDIATE: |
20522 | /* We claim that this fixup has been processed here, | |
20523 | even if in fact we generate an error because we do | |
20524 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
20525 | fixP->fx_done = 1; | |
b99bd4ef | 20526 | |
77db8e2e | 20527 | if (fixP->fx_addsy) |
b99bd4ef | 20528 | { |
77db8e2e | 20529 | const char *msg = 0; |
b99bd4ef | 20530 | |
77db8e2e NC |
20531 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
20532 | msg = _("undefined symbol %s used as an immediate value"); | |
20533 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
20534 | msg = _("symbol %s is in a different section"); | |
20535 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
20536 | msg = _("symbol %s is weak and may be overridden later"); | |
20537 | ||
20538 | if (msg) | |
20539 | { | |
20540 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20541 | msg, S_GET_NAME (fixP->fx_addsy)); | |
20542 | break; | |
20543 | } | |
42e5fcbf AS |
20544 | } |
20545 | ||
c19d1205 ZW |
20546 | newimm = encode_arm_immediate (value); |
20547 | temp = md_chars_to_number (buf, INSN_SIZE); | |
20548 | ||
20549 | /* If the instruction will fail, see if we can fix things up by | |
20550 | changing the opcode. */ | |
20551 | if (newimm == (unsigned int) FAIL | |
20552 | && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) | |
b99bd4ef | 20553 | { |
c19d1205 ZW |
20554 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20555 | _("invalid constant (%lx) after fixup"), | |
20556 | (unsigned long) value); | |
20557 | break; | |
b99bd4ef | 20558 | } |
b99bd4ef | 20559 | |
c19d1205 ZW |
20560 | newimm |= (temp & 0xfffff000); |
20561 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
20562 | break; | |
b99bd4ef | 20563 | |
c19d1205 ZW |
20564 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
20565 | { | |
20566 | unsigned int highpart = 0; | |
20567 | unsigned int newinsn = 0xe1a00000; /* nop. */ | |
b99bd4ef | 20568 | |
77db8e2e | 20569 | if (fixP->fx_addsy) |
42e5fcbf | 20570 | { |
77db8e2e | 20571 | const char *msg = 0; |
42e5fcbf | 20572 | |
77db8e2e NC |
20573 | if (! S_IS_DEFINED (fixP->fx_addsy)) |
20574 | msg = _("undefined symbol %s used as an immediate value"); | |
20575 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
20576 | msg = _("symbol %s is in a different section"); | |
20577 | else if (S_IS_WEAK (fixP->fx_addsy)) | |
20578 | msg = _("symbol %s is weak and may be overridden later"); | |
42e5fcbf | 20579 | |
77db8e2e NC |
20580 | if (msg) |
20581 | { | |
20582 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20583 | msg, S_GET_NAME (fixP->fx_addsy)); | |
20584 | break; | |
20585 | } | |
20586 | } | |
20587 | ||
c19d1205 ZW |
20588 | newimm = encode_arm_immediate (value); |
20589 | temp = md_chars_to_number (buf, INSN_SIZE); | |
b99bd4ef | 20590 | |
c19d1205 ZW |
20591 | /* If the instruction will fail, see if we can fix things up by |
20592 | changing the opcode. */ | |
20593 | if (newimm == (unsigned int) FAIL | |
20594 | && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) | |
20595 | { | |
20596 | /* No ? OK - try using two ADD instructions to generate | |
20597 | the value. */ | |
20598 | newimm = validate_immediate_twopart (value, & highpart); | |
b99bd4ef | 20599 | |
c19d1205 ZW |
20600 | /* Yes - then make sure that the second instruction is |
20601 | also an add. */ | |
20602 | if (newimm != (unsigned int) FAIL) | |
20603 | newinsn = temp; | |
20604 | /* Still No ? Try using a negated value. */ | |
20605 | else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) | |
20606 | temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; | |
20607 | /* Otherwise - give up. */ | |
20608 | else | |
20609 | { | |
20610 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20611 | _("unable to compute ADRL instructions for PC offset of 0x%lx"), | |
20612 | (long) value); | |
20613 | break; | |
20614 | } | |
b99bd4ef | 20615 | |
c19d1205 ZW |
20616 | /* Replace the first operand in the 2nd instruction (which |
20617 | is the PC) with the destination register. We have | |
20618 | already added in the PC in the first instruction and we | |
20619 | do not want to do it again. */ | |
20620 | newinsn &= ~ 0xf0000; | |
20621 | newinsn |= ((newinsn & 0x0f000) << 4); | |
20622 | } | |
b99bd4ef | 20623 | |
c19d1205 ZW |
20624 | newimm |= (temp & 0xfffff000); |
20625 | md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); | |
b99bd4ef | 20626 | |
c19d1205 ZW |
20627 | highpart |= (newinsn & 0xfffff000); |
20628 | md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); | |
20629 | } | |
20630 | break; | |
b99bd4ef | 20631 | |
c19d1205 | 20632 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
20633 | if (!fixP->fx_done && seg->use_rela_p) |
20634 | value = 0; | |
20635 | ||
c19d1205 | 20636 | case BFD_RELOC_ARM_LITERAL: |
26d97720 | 20637 | sign = value > 0; |
b99bd4ef | 20638 | |
c19d1205 ZW |
20639 | if (value < 0) |
20640 | value = - value; | |
b99bd4ef | 20641 | |
c19d1205 | 20642 | if (validate_offset_imm (value, 0) == FAIL) |
f03698e6 | 20643 | { |
c19d1205 ZW |
20644 | if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) |
20645 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20646 | _("invalid literal constant: pool needs to be closer")); | |
20647 | else | |
20648 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20649 | _("bad immediate value for offset (%ld)"), | |
20650 | (long) value); | |
20651 | break; | |
f03698e6 RE |
20652 | } |
20653 | ||
c19d1205 | 20654 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
20655 | if (value == 0) |
20656 | newval &= 0xfffff000; | |
20657 | else | |
20658 | { | |
20659 | newval &= 0xff7ff000; | |
20660 | newval |= value | (sign ? INDEX_UP : 0); | |
20661 | } | |
c19d1205 ZW |
20662 | md_number_to_chars (buf, newval, INSN_SIZE); |
20663 | break; | |
b99bd4ef | 20664 | |
c19d1205 ZW |
20665 | case BFD_RELOC_ARM_OFFSET_IMM8: |
20666 | case BFD_RELOC_ARM_HWLITERAL: | |
26d97720 | 20667 | sign = value > 0; |
b99bd4ef | 20668 | |
c19d1205 ZW |
20669 | if (value < 0) |
20670 | value = - value; | |
b99bd4ef | 20671 | |
c19d1205 | 20672 | if (validate_offset_imm (value, 1) == FAIL) |
b99bd4ef | 20673 | { |
c19d1205 ZW |
20674 | if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) |
20675 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20676 | _("invalid literal constant: pool needs to be closer")); | |
20677 | else | |
f9d4405b | 20678 | as_bad (_("bad immediate value for 8-bit offset (%ld)"), |
c19d1205 ZW |
20679 | (long) value); |
20680 | break; | |
b99bd4ef NC |
20681 | } |
20682 | ||
c19d1205 | 20683 | newval = md_chars_to_number (buf, INSN_SIZE); |
26d97720 NS |
20684 | if (value == 0) |
20685 | newval &= 0xfffff0f0; | |
20686 | else | |
20687 | { | |
20688 | newval &= 0xff7ff0f0; | |
20689 | newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); | |
20690 | } | |
c19d1205 ZW |
20691 | md_number_to_chars (buf, newval, INSN_SIZE); |
20692 | break; | |
b99bd4ef | 20693 | |
c19d1205 ZW |
20694 | case BFD_RELOC_ARM_T32_OFFSET_U8: |
20695 | if (value < 0 || value > 1020 || value % 4 != 0) | |
20696 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20697 | _("bad immediate value for offset (%ld)"), (long) value); | |
20698 | value /= 4; | |
b99bd4ef | 20699 | |
c19d1205 | 20700 | newval = md_chars_to_number (buf+2, THUMB_SIZE); |
c19d1205 ZW |
20701 | newval |= value; |
20702 | md_number_to_chars (buf+2, newval, THUMB_SIZE); | |
20703 | break; | |
b99bd4ef | 20704 | |
c19d1205 ZW |
20705 | case BFD_RELOC_ARM_T32_OFFSET_IMM: |
20706 | /* This is a complicated relocation used for all varieties of Thumb32 | |
20707 | load/store instruction with immediate offset: | |
20708 | ||
20709 | 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, | |
20710 | *4, optional writeback(W) | |
20711 | (doubleword load/store) | |
20712 | ||
20713 | 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel | |
20714 | 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit | |
20715 | 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) | |
20716 | 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit | |
20717 | 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit | |
20718 | ||
20719 | Uppercase letters indicate bits that are already encoded at | |
20720 | this point. Lowercase letters are our problem. For the | |
20721 | second block of instructions, the secondary opcode nybble | |
20722 | (bits 8..11) is present, and bit 23 is zero, even if this is | |
20723 | a PC-relative operation. */ | |
20724 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
20725 | newval <<= 16; | |
20726 | newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); | |
b99bd4ef | 20727 | |
c19d1205 | 20728 | if ((newval & 0xf0000000) == 0xe0000000) |
b99bd4ef | 20729 | { |
c19d1205 ZW |
20730 | /* Doubleword load/store: 8-bit offset, scaled by 4. */ |
20731 | if (value >= 0) | |
20732 | newval |= (1 << 23); | |
20733 | else | |
20734 | value = -value; | |
20735 | if (value % 4 != 0) | |
20736 | { | |
20737 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20738 | _("offset not a multiple of 4")); | |
20739 | break; | |
20740 | } | |
20741 | value /= 4; | |
216d22bc | 20742 | if (value > 0xff) |
c19d1205 ZW |
20743 | { |
20744 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20745 | _("offset out of range")); | |
20746 | break; | |
20747 | } | |
20748 | newval &= ~0xff; | |
b99bd4ef | 20749 | } |
c19d1205 | 20750 | else if ((newval & 0x000f0000) == 0x000f0000) |
b99bd4ef | 20751 | { |
c19d1205 ZW |
20752 | /* PC-relative, 12-bit offset. */ |
20753 | if (value >= 0) | |
20754 | newval |= (1 << 23); | |
20755 | else | |
20756 | value = -value; | |
216d22bc | 20757 | if (value > 0xfff) |
c19d1205 ZW |
20758 | { |
20759 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20760 | _("offset out of range")); | |
20761 | break; | |
20762 | } | |
20763 | newval &= ~0xfff; | |
b99bd4ef | 20764 | } |
c19d1205 | 20765 | else if ((newval & 0x00000100) == 0x00000100) |
b99bd4ef | 20766 | { |
c19d1205 ZW |
20767 | /* Writeback: 8-bit, +/- offset. */ |
20768 | if (value >= 0) | |
20769 | newval |= (1 << 9); | |
20770 | else | |
20771 | value = -value; | |
216d22bc | 20772 | if (value > 0xff) |
c19d1205 ZW |
20773 | { |
20774 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20775 | _("offset out of range")); | |
20776 | break; | |
20777 | } | |
20778 | newval &= ~0xff; | |
b99bd4ef | 20779 | } |
c19d1205 | 20780 | else if ((newval & 0x00000f00) == 0x00000e00) |
b99bd4ef | 20781 | { |
c19d1205 | 20782 | /* T-instruction: positive 8-bit offset. */ |
216d22bc | 20783 | if (value < 0 || value > 0xff) |
b99bd4ef | 20784 | { |
c19d1205 ZW |
20785 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20786 | _("offset out of range")); | |
20787 | break; | |
b99bd4ef | 20788 | } |
c19d1205 ZW |
20789 | newval &= ~0xff; |
20790 | newval |= value; | |
b99bd4ef NC |
20791 | } |
20792 | else | |
b99bd4ef | 20793 | { |
c19d1205 ZW |
20794 | /* Positive 12-bit or negative 8-bit offset. */ |
20795 | int limit; | |
20796 | if (value >= 0) | |
b99bd4ef | 20797 | { |
c19d1205 ZW |
20798 | newval |= (1 << 23); |
20799 | limit = 0xfff; | |
20800 | } | |
20801 | else | |
20802 | { | |
20803 | value = -value; | |
20804 | limit = 0xff; | |
20805 | } | |
20806 | if (value > limit) | |
20807 | { | |
20808 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20809 | _("offset out of range")); | |
20810 | break; | |
b99bd4ef | 20811 | } |
c19d1205 | 20812 | newval &= ~limit; |
b99bd4ef | 20813 | } |
b99bd4ef | 20814 | |
c19d1205 ZW |
20815 | newval |= value; |
20816 | md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); | |
20817 | md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); | |
20818 | break; | |
404ff6b5 | 20819 | |
c19d1205 ZW |
20820 | case BFD_RELOC_ARM_SHIFT_IMM: |
20821 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20822 | if (((unsigned long) value) > 32 | |
20823 | || (value == 32 | |
20824 | && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) | |
20825 | { | |
20826 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20827 | _("shift expression is too large")); | |
20828 | break; | |
20829 | } | |
404ff6b5 | 20830 | |
c19d1205 ZW |
20831 | if (value == 0) |
20832 | /* Shifts of zero must be done as lsl. */ | |
20833 | newval &= ~0x60; | |
20834 | else if (value == 32) | |
20835 | value = 0; | |
20836 | newval &= 0xfffff07f; | |
20837 | newval |= (value & 0x1f) << 7; | |
20838 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20839 | break; | |
404ff6b5 | 20840 | |
c19d1205 | 20841 | case BFD_RELOC_ARM_T32_IMMEDIATE: |
16805f35 | 20842 | case BFD_RELOC_ARM_T32_ADD_IMM: |
92e90b6e | 20843 | case BFD_RELOC_ARM_T32_IMM12: |
e9f89963 | 20844 | case BFD_RELOC_ARM_T32_ADD_PC12: |
c19d1205 ZW |
20845 | /* We claim that this fixup has been processed here, |
20846 | even if in fact we generate an error because we do | |
20847 | not have a reloc for it, so tc_gen_reloc will reject it. */ | |
20848 | fixP->fx_done = 1; | |
404ff6b5 | 20849 | |
c19d1205 ZW |
20850 | if (fixP->fx_addsy |
20851 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
20852 | { | |
20853 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20854 | _("undefined symbol %s used as an immediate value"), | |
20855 | S_GET_NAME (fixP->fx_addsy)); | |
20856 | break; | |
20857 | } | |
404ff6b5 | 20858 | |
c19d1205 ZW |
20859 | newval = md_chars_to_number (buf, THUMB_SIZE); |
20860 | newval <<= 16; | |
20861 | newval |= md_chars_to_number (buf+2, THUMB_SIZE); | |
404ff6b5 | 20862 | |
16805f35 PB |
20863 | newimm = FAIL; |
20864 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE | |
20865 | || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
ef8d22e6 PB |
20866 | { |
20867 | newimm = encode_thumb32_immediate (value); | |
20868 | if (newimm == (unsigned int) FAIL) | |
20869 | newimm = thumb32_negate_data_op (&newval, value); | |
20870 | } | |
16805f35 PB |
20871 | if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE |
20872 | && newimm == (unsigned int) FAIL) | |
92e90b6e | 20873 | { |
16805f35 PB |
20874 | /* Turn add/sum into addw/subw. */ |
20875 | if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) | |
20876 | newval = (newval & 0xfeffffff) | 0x02000000; | |
40f246e3 NC |
20877 | /* No flat 12-bit imm encoding for addsw/subsw. */ |
20878 | if ((newval & 0x00100000) == 0) | |
e9f89963 | 20879 | { |
40f246e3 NC |
20880 | /* 12 bit immediate for addw/subw. */ |
20881 | if (value < 0) | |
20882 | { | |
20883 | value = -value; | |
20884 | newval ^= 0x00a00000; | |
20885 | } | |
20886 | if (value > 0xfff) | |
20887 | newimm = (unsigned int) FAIL; | |
20888 | else | |
20889 | newimm = value; | |
e9f89963 | 20890 | } |
92e90b6e | 20891 | } |
cc8a6dd0 | 20892 | |
c19d1205 | 20893 | if (newimm == (unsigned int)FAIL) |
3631a3c8 | 20894 | { |
c19d1205 ZW |
20895 | as_bad_where (fixP->fx_file, fixP->fx_line, |
20896 | _("invalid constant (%lx) after fixup"), | |
20897 | (unsigned long) value); | |
20898 | break; | |
3631a3c8 NC |
20899 | } |
20900 | ||
c19d1205 ZW |
20901 | newval |= (newimm & 0x800) << 15; |
20902 | newval |= (newimm & 0x700) << 4; | |
20903 | newval |= (newimm & 0x0ff); | |
cc8a6dd0 | 20904 | |
c19d1205 ZW |
20905 | md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); |
20906 | md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); | |
20907 | break; | |
a737bd4d | 20908 | |
3eb17e6b | 20909 | case BFD_RELOC_ARM_SMC: |
c19d1205 ZW |
20910 | if (((unsigned long) value) > 0xffff) |
20911 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3eb17e6b | 20912 | _("invalid smc expression")); |
2fc8bdac | 20913 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20914 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); |
20915 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20916 | break; | |
a737bd4d | 20917 | |
90ec0d68 MGD |
20918 | case BFD_RELOC_ARM_HVC: |
20919 | if (((unsigned long) value) > 0xffff) | |
20920 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20921 | _("invalid hvc expression")); | |
20922 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20923 | newval |= (value & 0xf) | ((value & 0xfff0) << 4); | |
20924 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20925 | break; | |
20926 | ||
c19d1205 | 20927 | case BFD_RELOC_ARM_SWI: |
adbaf948 | 20928 | if (fixP->tc_fix_data != 0) |
c19d1205 ZW |
20929 | { |
20930 | if (((unsigned long) value) > 0xff) | |
20931 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20932 | _("invalid swi expression")); | |
2fc8bdac | 20933 | newval = md_chars_to_number (buf, THUMB_SIZE); |
c19d1205 ZW |
20934 | newval |= value; |
20935 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
20936 | } | |
20937 | else | |
20938 | { | |
20939 | if (((unsigned long) value) > 0x00ffffff) | |
20940 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20941 | _("invalid swi expression")); | |
2fc8bdac | 20942 | newval = md_chars_to_number (buf, INSN_SIZE); |
c19d1205 ZW |
20943 | newval |= value; |
20944 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20945 | } | |
20946 | break; | |
a737bd4d | 20947 | |
c19d1205 ZW |
20948 | case BFD_RELOC_ARM_MULTI: |
20949 | if (((unsigned long) value) > 0xffff) | |
20950 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
20951 | _("invalid expression in load/store multiple")); | |
20952 | newval = value | md_chars_to_number (buf, INSN_SIZE); | |
20953 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20954 | break; | |
a737bd4d | 20955 | |
c19d1205 | 20956 | #ifdef OBJ_ELF |
39b41c9c | 20957 | case BFD_RELOC_ARM_PCREL_CALL: |
267bf995 RR |
20958 | |
20959 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
20960 | && fixP->fx_addsy | |
34e77a92 | 20961 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20962 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
20963 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20964 | /* Flip the bl to blx. This is a simple flip | |
20965 | bit here because we generate PCREL_CALL for | |
20966 | unconditional bls. */ | |
20967 | { | |
20968 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20969 | newval = newval | 0x10000000; | |
20970 | md_number_to_chars (buf, newval, INSN_SIZE); | |
20971 | temp = 1; | |
20972 | fixP->fx_done = 1; | |
20973 | } | |
39b41c9c PB |
20974 | else |
20975 | temp = 3; | |
20976 | goto arm_branch_common; | |
20977 | ||
20978 | case BFD_RELOC_ARM_PCREL_JUMP: | |
267bf995 RR |
20979 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
20980 | && fixP->fx_addsy | |
34e77a92 | 20981 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
20982 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
20983 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
20984 | { | |
20985 | /* This would map to a bl<cond>, b<cond>, | |
20986 | b<always> to a Thumb function. We | |
20987 | need to force a relocation for this particular | |
20988 | case. */ | |
20989 | newval = md_chars_to_number (buf, INSN_SIZE); | |
20990 | fixP->fx_done = 0; | |
20991 | } | |
20992 | ||
2fc8bdac | 20993 | case BFD_RELOC_ARM_PLT32: |
c19d1205 | 20994 | #endif |
39b41c9c PB |
20995 | case BFD_RELOC_ARM_PCREL_BRANCH: |
20996 | temp = 3; | |
20997 | goto arm_branch_common; | |
a737bd4d | 20998 | |
39b41c9c | 20999 | case BFD_RELOC_ARM_PCREL_BLX: |
267bf995 | 21000 | |
39b41c9c | 21001 | temp = 1; |
267bf995 RR |
21002 | if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) |
21003 | && fixP->fx_addsy | |
34e77a92 | 21004 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21005 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
21006 | && ARM_IS_FUNC (fixP->fx_addsy)) | |
21007 | { | |
21008 | /* Flip the blx to a bl and warn. */ | |
21009 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
21010 | newval = 0xeb000000; | |
21011 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
21012 | _("blx to '%s' an ARM ISA state function changed to bl"), | |
21013 | name); | |
21014 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21015 | temp = 3; | |
21016 | fixP->fx_done = 1; | |
21017 | } | |
21018 | ||
21019 | #ifdef OBJ_ELF | |
21020 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
21021 | fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL; | |
21022 | #endif | |
21023 | ||
39b41c9c | 21024 | arm_branch_common: |
c19d1205 | 21025 | /* We are going to store value (shifted right by two) in the |
39b41c9c PB |
21026 | instruction, in a 24 bit, signed field. Bits 26 through 32 either |
21027 | all clear or all set and bit 0 must be clear. For B/BL bit 1 must | |
21028 | also be be clear. */ | |
21029 | if (value & temp) | |
c19d1205 | 21030 | as_bad_where (fixP->fx_file, fixP->fx_line, |
2fc8bdac ZW |
21031 | _("misaligned branch destination")); |
21032 | if ((value & (offsetT)0xfe000000) != (offsetT)0 | |
21033 | && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) | |
08f10d51 | 21034 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 21035 | |
2fc8bdac | 21036 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 21037 | { |
2fc8bdac ZW |
21038 | newval = md_chars_to_number (buf, INSN_SIZE); |
21039 | newval |= (value >> 2) & 0x00ffffff; | |
7ae2971b PB |
21040 | /* Set the H bit on BLX instructions. */ |
21041 | if (temp == 1) | |
21042 | { | |
21043 | if (value & 2) | |
21044 | newval |= 0x01000000; | |
21045 | else | |
21046 | newval &= ~0x01000000; | |
21047 | } | |
2fc8bdac | 21048 | md_number_to_chars (buf, newval, INSN_SIZE); |
c19d1205 | 21049 | } |
c19d1205 | 21050 | break; |
a737bd4d | 21051 | |
25fe350b MS |
21052 | case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ |
21053 | /* CBZ can only branch forward. */ | |
a737bd4d | 21054 | |
738755b0 MS |
21055 | /* Attempts to use CBZ to branch to the next instruction |
21056 | (which, strictly speaking, are prohibited) will be turned into | |
21057 | no-ops. | |
21058 | ||
21059 | FIXME: It may be better to remove the instruction completely and | |
21060 | perform relaxation. */ | |
21061 | if (value == -2) | |
2fc8bdac ZW |
21062 | { |
21063 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
738755b0 | 21064 | newval = 0xbf00; /* NOP encoding T1 */ |
2fc8bdac ZW |
21065 | md_number_to_chars (buf, newval, THUMB_SIZE); |
21066 | } | |
738755b0 MS |
21067 | else |
21068 | { | |
21069 | if (value & ~0x7e) | |
08f10d51 | 21070 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
738755b0 MS |
21071 | |
21072 | if (fixP->fx_done || !seg->use_rela_p) | |
21073 | { | |
21074 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21075 | newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); | |
21076 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21077 | } | |
21078 | } | |
c19d1205 | 21079 | break; |
a737bd4d | 21080 | |
c19d1205 | 21081 | case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ |
2fc8bdac | 21082 | if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) |
08f10d51 | 21083 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 21084 | |
2fc8bdac ZW |
21085 | if (fixP->fx_done || !seg->use_rela_p) |
21086 | { | |
21087 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21088 | newval |= (value & 0x1ff) >> 1; | |
21089 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21090 | } | |
c19d1205 | 21091 | break; |
a737bd4d | 21092 | |
c19d1205 | 21093 | case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ |
2fc8bdac | 21094 | if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) |
08f10d51 | 21095 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); |
a737bd4d | 21096 | |
2fc8bdac ZW |
21097 | if (fixP->fx_done || !seg->use_rela_p) |
21098 | { | |
21099 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21100 | newval |= (value & 0xfff) >> 1; | |
21101 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21102 | } | |
c19d1205 | 21103 | break; |
a737bd4d | 21104 | |
c19d1205 | 21105 | case BFD_RELOC_THUMB_PCREL_BRANCH20: |
267bf995 RR |
21106 | if (fixP->fx_addsy |
21107 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21108 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21109 | && ARM_IS_FUNC (fixP->fx_addsy) |
21110 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21111 | { | |
21112 | /* Force a relocation for a branch 20 bits wide. */ | |
21113 | fixP->fx_done = 0; | |
21114 | } | |
08f10d51 | 21115 | if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff)) |
2fc8bdac ZW |
21116 | as_bad_where (fixP->fx_file, fixP->fx_line, |
21117 | _("conditional branch out of range")); | |
404ff6b5 | 21118 | |
2fc8bdac ZW |
21119 | if (fixP->fx_done || !seg->use_rela_p) |
21120 | { | |
21121 | offsetT newval2; | |
21122 | addressT S, J1, J2, lo, hi; | |
404ff6b5 | 21123 | |
2fc8bdac ZW |
21124 | S = (value & 0x00100000) >> 20; |
21125 | J2 = (value & 0x00080000) >> 19; | |
21126 | J1 = (value & 0x00040000) >> 18; | |
21127 | hi = (value & 0x0003f000) >> 12; | |
21128 | lo = (value & 0x00000ffe) >> 1; | |
6c43fab6 | 21129 | |
2fc8bdac ZW |
21130 | newval = md_chars_to_number (buf, THUMB_SIZE); |
21131 | newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21132 | newval |= (S << 10) | hi; | |
21133 | newval2 |= (J1 << 13) | (J2 << 11) | lo; | |
21134 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21135 | md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); | |
21136 | } | |
c19d1205 | 21137 | break; |
6c43fab6 | 21138 | |
c19d1205 | 21139 | case BFD_RELOC_THUMB_PCREL_BLX: |
267bf995 RR |
21140 | /* If there is a blx from a thumb state function to |
21141 | another thumb function flip this to a bl and warn | |
21142 | about it. */ | |
21143 | ||
21144 | if (fixP->fx_addsy | |
34e77a92 | 21145 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21146 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) |
21147 | && THUMB_IS_FUNC (fixP->fx_addsy)) | |
21148 | { | |
21149 | const char *name = S_GET_NAME (fixP->fx_addsy); | |
21150 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
21151 | _("blx to Thumb func '%s' from Thumb ISA state changed to bl"), | |
21152 | name); | |
21153 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21154 | newval = newval | 0x1000; | |
21155 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
21156 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21157 | fixP->fx_done = 1; | |
21158 | } | |
21159 | ||
21160 | ||
21161 | goto thumb_bl_common; | |
21162 | ||
c19d1205 | 21163 | case BFD_RELOC_THUMB_PCREL_BRANCH23: |
267bf995 RR |
21164 | /* A bl from Thumb state ISA to an internal ARM state function |
21165 | is converted to a blx. */ | |
21166 | if (fixP->fx_addsy | |
21167 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg) | |
34e77a92 | 21168 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
267bf995 RR |
21169 | && ARM_IS_FUNC (fixP->fx_addsy) |
21170 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)) | |
21171 | { | |
21172 | newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); | |
21173 | newval = newval & ~0x1000; | |
21174 | md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE); | |
21175 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX; | |
21176 | fixP->fx_done = 1; | |
21177 | } | |
21178 | ||
21179 | thumb_bl_common: | |
21180 | ||
21181 | #ifdef OBJ_ELF | |
21182 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 && | |
21183 | fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) | |
21184 | fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21185 | #endif | |
21186 | ||
2fc8bdac ZW |
21187 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) |
21188 | /* For a BLX instruction, make sure that the relocation is rounded up | |
21189 | to a word boundary. This follows the semantics of the instruction | |
21190 | which specifies that bit 1 of the target address will come from bit | |
21191 | 1 of the base address. */ | |
21192 | value = (value + 1) & ~ 1; | |
404ff6b5 | 21193 | |
4a42ebbc | 21194 | if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) |
08f10d51 NC |
21195 | { |
21196 | if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))) | |
21197 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
21198 | else if ((value & ~0x1ffffff) | |
21199 | && ((value & ~0x1ffffff) != ~0x1ffffff)) | |
21200 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21201 | _("Thumb2 branch out of range")); | |
21202 | } | |
4a42ebbc RR |
21203 | |
21204 | if (fixP->fx_done || !seg->use_rela_p) | |
21205 | encode_thumb2_b_bl_offset (buf, value); | |
21206 | ||
c19d1205 | 21207 | break; |
404ff6b5 | 21208 | |
c19d1205 | 21209 | case BFD_RELOC_THUMB_PCREL_BRANCH25: |
08f10d51 NC |
21210 | if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff)) |
21211 | as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE); | |
6c43fab6 | 21212 | |
2fc8bdac | 21213 | if (fixP->fx_done || !seg->use_rela_p) |
4a42ebbc | 21214 | encode_thumb2_b_bl_offset (buf, value); |
6c43fab6 | 21215 | |
2fc8bdac | 21216 | break; |
a737bd4d | 21217 | |
2fc8bdac ZW |
21218 | case BFD_RELOC_8: |
21219 | if (fixP->fx_done || !seg->use_rela_p) | |
21220 | md_number_to_chars (buf, value, 1); | |
c19d1205 | 21221 | break; |
a737bd4d | 21222 | |
c19d1205 | 21223 | case BFD_RELOC_16: |
2fc8bdac | 21224 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 | 21225 | md_number_to_chars (buf, value, 2); |
c19d1205 | 21226 | break; |
a737bd4d | 21227 | |
c19d1205 | 21228 | #ifdef OBJ_ELF |
0855e32b NS |
21229 | case BFD_RELOC_ARM_TLS_CALL: |
21230 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
21231 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
21232 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
21233 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
21234 | break; | |
21235 | ||
21236 | case BFD_RELOC_ARM_TLS_GOTDESC: | |
c19d1205 ZW |
21237 | case BFD_RELOC_ARM_TLS_GD32: |
21238 | case BFD_RELOC_ARM_TLS_LE32: | |
21239 | case BFD_RELOC_ARM_TLS_IE32: | |
21240 | case BFD_RELOC_ARM_TLS_LDM32: | |
21241 | case BFD_RELOC_ARM_TLS_LDO32: | |
21242 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
21243 | /* fall through */ | |
6c43fab6 | 21244 | |
c19d1205 ZW |
21245 | case BFD_RELOC_ARM_GOT32: |
21246 | case BFD_RELOC_ARM_GOTOFF: | |
2fc8bdac ZW |
21247 | if (fixP->fx_done || !seg->use_rela_p) |
21248 | md_number_to_chars (buf, 0, 4); | |
c19d1205 | 21249 | break; |
b43420e6 NC |
21250 | |
21251 | case BFD_RELOC_ARM_GOT_PREL: | |
21252 | if (fixP->fx_done || !seg->use_rela_p) | |
21253 | md_number_to_chars (buf, value, 4); | |
21254 | break; | |
21255 | ||
9a6f4e97 NS |
21256 | case BFD_RELOC_ARM_TARGET2: |
21257 | /* TARGET2 is not partial-inplace, so we need to write the | |
21258 | addend here for REL targets, because it won't be written out | |
21259 | during reloc processing later. */ | |
21260 | if (fixP->fx_done || !seg->use_rela_p) | |
21261 | md_number_to_chars (buf, fixP->fx_offset, 4); | |
21262 | break; | |
c19d1205 | 21263 | #endif |
6c43fab6 | 21264 | |
c19d1205 ZW |
21265 | case BFD_RELOC_RVA: |
21266 | case BFD_RELOC_32: | |
21267 | case BFD_RELOC_ARM_TARGET1: | |
21268 | case BFD_RELOC_ARM_ROSEGREL32: | |
21269 | case BFD_RELOC_ARM_SBREL32: | |
21270 | case BFD_RELOC_32_PCREL: | |
f0927246 NC |
21271 | #ifdef TE_PE |
21272 | case BFD_RELOC_32_SECREL: | |
21273 | #endif | |
2fc8bdac | 21274 | if (fixP->fx_done || !seg->use_rela_p) |
53baae48 NC |
21275 | #ifdef TE_WINCE |
21276 | /* For WinCE we only do this for pcrel fixups. */ | |
21277 | if (fixP->fx_done || fixP->fx_pcrel) | |
21278 | #endif | |
21279 | md_number_to_chars (buf, value, 4); | |
c19d1205 | 21280 | break; |
6c43fab6 | 21281 | |
c19d1205 ZW |
21282 | #ifdef OBJ_ELF |
21283 | case BFD_RELOC_ARM_PREL31: | |
2fc8bdac | 21284 | if (fixP->fx_done || !seg->use_rela_p) |
c19d1205 ZW |
21285 | { |
21286 | newval = md_chars_to_number (buf, 4) & 0x80000000; | |
21287 | if ((value ^ (value >> 1)) & 0x40000000) | |
21288 | { | |
21289 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21290 | _("rel31 relocation overflow")); | |
21291 | } | |
21292 | newval |= value & 0x7fffffff; | |
21293 | md_number_to_chars (buf, newval, 4); | |
21294 | } | |
21295 | break; | |
c19d1205 | 21296 | #endif |
a737bd4d | 21297 | |
c19d1205 | 21298 | case BFD_RELOC_ARM_CP_OFF_IMM: |
8f06b2d8 | 21299 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: |
c19d1205 ZW |
21300 | if (value < -1023 || value > 1023 || (value & 3)) |
21301 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21302 | _("co-processor offset out of range")); | |
21303 | cp_off_common: | |
26d97720 | 21304 | sign = value > 0; |
c19d1205 ZW |
21305 | if (value < 0) |
21306 | value = -value; | |
8f06b2d8 PB |
21307 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
21308 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
21309 | newval = md_chars_to_number (buf, INSN_SIZE); | |
21310 | else | |
21311 | newval = get_thumb32_insn (buf); | |
26d97720 NS |
21312 | if (value == 0) |
21313 | newval &= 0xffffff00; | |
21314 | else | |
21315 | { | |
21316 | newval &= 0xff7fff00; | |
21317 | newval |= (value >> 2) | (sign ? INDEX_UP : 0); | |
21318 | } | |
8f06b2d8 PB |
21319 | if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
21320 | || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) | |
21321 | md_number_to_chars (buf, newval, INSN_SIZE); | |
21322 | else | |
21323 | put_thumb32_insn (buf, newval); | |
c19d1205 | 21324 | break; |
a737bd4d | 21325 | |
c19d1205 | 21326 | case BFD_RELOC_ARM_CP_OFF_IMM_S2: |
8f06b2d8 | 21327 | case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: |
c19d1205 ZW |
21328 | if (value < -255 || value > 255) |
21329 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21330 | _("co-processor offset out of range")); | |
df7849c5 | 21331 | value *= 4; |
c19d1205 | 21332 | goto cp_off_common; |
6c43fab6 | 21333 | |
c19d1205 ZW |
21334 | case BFD_RELOC_ARM_THUMB_OFFSET: |
21335 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21336 | /* Exactly what ranges, and where the offset is inserted depends | |
21337 | on the type of instruction, we can establish this from the | |
21338 | top 4 bits. */ | |
21339 | switch (newval >> 12) | |
21340 | { | |
21341 | case 4: /* PC load. */ | |
21342 | /* Thumb PC loads are somewhat odd, bit 1 of the PC is | |
21343 | forced to zero for these loads; md_pcrel_from has already | |
21344 | compensated for this. */ | |
21345 | if (value & 3) | |
21346 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21347 | _("invalid offset, target not word aligned (0x%08lX)"), | |
0359e808 NC |
21348 | (((unsigned long) fixP->fx_frag->fr_address |
21349 | + (unsigned long) fixP->fx_where) & ~3) | |
21350 | + (unsigned long) value); | |
a737bd4d | 21351 | |
c19d1205 ZW |
21352 | if (value & ~0x3fc) |
21353 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21354 | _("invalid offset, value too big (0x%08lX)"), | |
21355 | (long) value); | |
a737bd4d | 21356 | |
c19d1205 ZW |
21357 | newval |= value >> 2; |
21358 | break; | |
a737bd4d | 21359 | |
c19d1205 ZW |
21360 | case 9: /* SP load/store. */ |
21361 | if (value & ~0x3fc) | |
21362 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21363 | _("invalid offset, value too big (0x%08lX)"), | |
21364 | (long) value); | |
21365 | newval |= value >> 2; | |
21366 | break; | |
6c43fab6 | 21367 | |
c19d1205 ZW |
21368 | case 6: /* Word load/store. */ |
21369 | if (value & ~0x7c) | |
21370 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21371 | _("invalid offset, value too big (0x%08lX)"), | |
21372 | (long) value); | |
21373 | newval |= value << 4; /* 6 - 2. */ | |
21374 | break; | |
a737bd4d | 21375 | |
c19d1205 ZW |
21376 | case 7: /* Byte load/store. */ |
21377 | if (value & ~0x1f) | |
21378 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21379 | _("invalid offset, value too big (0x%08lX)"), | |
21380 | (long) value); | |
21381 | newval |= value << 6; | |
21382 | break; | |
a737bd4d | 21383 | |
c19d1205 ZW |
21384 | case 8: /* Halfword load/store. */ |
21385 | if (value & ~0x3e) | |
21386 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21387 | _("invalid offset, value too big (0x%08lX)"), | |
21388 | (long) value); | |
21389 | newval |= value << 5; /* 6 - 1. */ | |
21390 | break; | |
a737bd4d | 21391 | |
c19d1205 ZW |
21392 | default: |
21393 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21394 | "Unable to process relocation for thumb opcode: %lx", | |
21395 | (unsigned long) newval); | |
21396 | break; | |
21397 | } | |
21398 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21399 | break; | |
a737bd4d | 21400 | |
c19d1205 ZW |
21401 | case BFD_RELOC_ARM_THUMB_ADD: |
21402 | /* This is a complicated relocation, since we use it for all of | |
21403 | the following immediate relocations: | |
a737bd4d | 21404 | |
c19d1205 ZW |
21405 | 3bit ADD/SUB |
21406 | 8bit ADD/SUB | |
21407 | 9bit ADD/SUB SP word-aligned | |
21408 | 10bit ADD PC/SP word-aligned | |
a737bd4d | 21409 | |
c19d1205 ZW |
21410 | The type of instruction being processed is encoded in the |
21411 | instruction field: | |
a737bd4d | 21412 | |
c19d1205 ZW |
21413 | 0x8000 SUB |
21414 | 0x00F0 Rd | |
21415 | 0x000F Rs | |
21416 | */ | |
21417 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21418 | { | |
21419 | int rd = (newval >> 4) & 0xf; | |
21420 | int rs = newval & 0xf; | |
21421 | int subtract = !!(newval & 0x8000); | |
a737bd4d | 21422 | |
c19d1205 ZW |
21423 | /* Check for HI regs, only very restricted cases allowed: |
21424 | Adjusting SP, and using PC or SP to get an address. */ | |
21425 | if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) | |
21426 | || (rs > 7 && rs != REG_SP && rs != REG_PC)) | |
21427 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21428 | _("invalid Hi register with immediate")); | |
a737bd4d | 21429 | |
c19d1205 ZW |
21430 | /* If value is negative, choose the opposite instruction. */ |
21431 | if (value < 0) | |
21432 | { | |
21433 | value = -value; | |
21434 | subtract = !subtract; | |
21435 | if (value < 0) | |
21436 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21437 | _("immediate value out of range")); | |
21438 | } | |
a737bd4d | 21439 | |
c19d1205 ZW |
21440 | if (rd == REG_SP) |
21441 | { | |
21442 | if (value & ~0x1fc) | |
21443 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21444 | _("invalid immediate for stack address calculation")); | |
21445 | newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; | |
21446 | newval |= value >> 2; | |
21447 | } | |
21448 | else if (rs == REG_PC || rs == REG_SP) | |
21449 | { | |
21450 | if (subtract || value & ~0x3fc) | |
21451 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21452 | _("invalid immediate for address calculation (value = 0x%08lX)"), | |
21453 | (unsigned long) value); | |
21454 | newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); | |
21455 | newval |= rd << 8; | |
21456 | newval |= value >> 2; | |
21457 | } | |
21458 | else if (rs == rd) | |
21459 | { | |
21460 | if (value & ~0xff) | |
21461 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21462 | _("immediate value out of range")); | |
21463 | newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; | |
21464 | newval |= (rd << 8) | value; | |
21465 | } | |
21466 | else | |
21467 | { | |
21468 | if (value & ~0x7) | |
21469 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21470 | _("immediate value out of range")); | |
21471 | newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; | |
21472 | newval |= rd | (rs << 3) | (value << 6); | |
21473 | } | |
21474 | } | |
21475 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21476 | break; | |
a737bd4d | 21477 | |
c19d1205 ZW |
21478 | case BFD_RELOC_ARM_THUMB_IMM: |
21479 | newval = md_chars_to_number (buf, THUMB_SIZE); | |
21480 | if (value < 0 || value > 255) | |
21481 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
4e6e072b | 21482 | _("invalid immediate: %ld is out of range"), |
c19d1205 ZW |
21483 | (long) value); |
21484 | newval |= value; | |
21485 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21486 | break; | |
a737bd4d | 21487 | |
c19d1205 ZW |
21488 | case BFD_RELOC_ARM_THUMB_SHIFT: |
21489 | /* 5bit shift value (0..32). LSL cannot take 32. */ | |
21490 | newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; | |
21491 | temp = newval & 0xf800; | |
21492 | if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) | |
21493 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21494 | _("invalid shift value: %ld"), (long) value); | |
21495 | /* Shifts of zero must be encoded as LSL. */ | |
21496 | if (value == 0) | |
21497 | newval = (newval & 0x003f) | T_OPCODE_LSL_I; | |
21498 | /* Shifts of 32 are encoded as zero. */ | |
21499 | else if (value == 32) | |
21500 | value = 0; | |
21501 | newval |= value << 6; | |
21502 | md_number_to_chars (buf, newval, THUMB_SIZE); | |
21503 | break; | |
a737bd4d | 21504 | |
c19d1205 ZW |
21505 | case BFD_RELOC_VTABLE_INHERIT: |
21506 | case BFD_RELOC_VTABLE_ENTRY: | |
21507 | fixP->fx_done = 0; | |
21508 | return; | |
6c43fab6 | 21509 | |
b6895b4f PB |
21510 | case BFD_RELOC_ARM_MOVW: |
21511 | case BFD_RELOC_ARM_MOVT: | |
21512 | case BFD_RELOC_ARM_THUMB_MOVW: | |
21513 | case BFD_RELOC_ARM_THUMB_MOVT: | |
21514 | if (fixP->fx_done || !seg->use_rela_p) | |
21515 | { | |
21516 | /* REL format relocations are limited to a 16-bit addend. */ | |
21517 | if (!fixP->fx_done) | |
21518 | { | |
39623e12 | 21519 | if (value < -0x8000 || value > 0x7fff) |
b6895b4f | 21520 | as_bad_where (fixP->fx_file, fixP->fx_line, |
ff5075ca | 21521 | _("offset out of range")); |
b6895b4f PB |
21522 | } |
21523 | else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
21524 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
21525 | { | |
21526 | value >>= 16; | |
21527 | } | |
21528 | ||
21529 | if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
21530 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) | |
21531 | { | |
21532 | newval = get_thumb32_insn (buf); | |
21533 | newval &= 0xfbf08f00; | |
21534 | newval |= (value & 0xf000) << 4; | |
21535 | newval |= (value & 0x0800) << 15; | |
21536 | newval |= (value & 0x0700) << 4; | |
21537 | newval |= (value & 0x00ff); | |
21538 | put_thumb32_insn (buf, newval); | |
21539 | } | |
21540 | else | |
21541 | { | |
21542 | newval = md_chars_to_number (buf, 4); | |
21543 | newval &= 0xfff0f000; | |
21544 | newval |= value & 0x0fff; | |
21545 | newval |= (value & 0xf000) << 4; | |
21546 | md_number_to_chars (buf, newval, 4); | |
21547 | } | |
21548 | } | |
21549 | return; | |
21550 | ||
4962c51a MS |
21551 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
21552 | case BFD_RELOC_ARM_ALU_PC_G0: | |
21553 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
21554 | case BFD_RELOC_ARM_ALU_PC_G1: | |
21555 | case BFD_RELOC_ARM_ALU_PC_G2: | |
21556 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
21557 | case BFD_RELOC_ARM_ALU_SB_G0: | |
21558 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
21559 | case BFD_RELOC_ARM_ALU_SB_G1: | |
21560 | case BFD_RELOC_ARM_ALU_SB_G2: | |
9c2799c2 | 21561 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21562 | if (!seg->use_rela_p) |
21563 | { | |
21564 | bfd_vma insn; | |
21565 | bfd_vma encoded_addend; | |
21566 | bfd_vma addend_abs = abs (value); | |
21567 | ||
21568 | /* Check that the absolute value of the addend can be | |
21569 | expressed as an 8-bit constant plus a rotation. */ | |
21570 | encoded_addend = encode_arm_immediate (addend_abs); | |
21571 | if (encoded_addend == (unsigned int) FAIL) | |
21572 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21573 | _("the offset 0x%08lX is not representable"), | |
495bde8e | 21574 | (unsigned long) addend_abs); |
4962c51a MS |
21575 | |
21576 | /* Extract the instruction. */ | |
21577 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21578 | ||
21579 | /* If the addend is positive, use an ADD instruction. | |
21580 | Otherwise use a SUB. Take care not to destroy the S bit. */ | |
21581 | insn &= 0xff1fffff; | |
21582 | if (value < 0) | |
21583 | insn |= 1 << 22; | |
21584 | else | |
21585 | insn |= 1 << 23; | |
21586 | ||
21587 | /* Place the encoded addend into the first 12 bits of the | |
21588 | instruction. */ | |
21589 | insn &= 0xfffff000; | |
21590 | insn |= encoded_addend; | |
5f4273c7 NC |
21591 | |
21592 | /* Update the instruction. */ | |
4962c51a MS |
21593 | md_number_to_chars (buf, insn, INSN_SIZE); |
21594 | } | |
21595 | break; | |
21596 | ||
21597 | case BFD_RELOC_ARM_LDR_PC_G0: | |
21598 | case BFD_RELOC_ARM_LDR_PC_G1: | |
21599 | case BFD_RELOC_ARM_LDR_PC_G2: | |
21600 | case BFD_RELOC_ARM_LDR_SB_G0: | |
21601 | case BFD_RELOC_ARM_LDR_SB_G1: | |
21602 | case BFD_RELOC_ARM_LDR_SB_G2: | |
9c2799c2 | 21603 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21604 | if (!seg->use_rela_p) |
21605 | { | |
21606 | bfd_vma insn; | |
21607 | bfd_vma addend_abs = abs (value); | |
21608 | ||
21609 | /* Check that the absolute value of the addend can be | |
21610 | encoded in 12 bits. */ | |
21611 | if (addend_abs >= 0x1000) | |
21612 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21613 | _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), | |
495bde8e | 21614 | (unsigned long) addend_abs); |
4962c51a MS |
21615 | |
21616 | /* Extract the instruction. */ | |
21617 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21618 | ||
21619 | /* If the addend is negative, clear bit 23 of the instruction. | |
21620 | Otherwise set it. */ | |
21621 | if (value < 0) | |
21622 | insn &= ~(1 << 23); | |
21623 | else | |
21624 | insn |= 1 << 23; | |
21625 | ||
21626 | /* Place the absolute value of the addend into the first 12 bits | |
21627 | of the instruction. */ | |
21628 | insn &= 0xfffff000; | |
21629 | insn |= addend_abs; | |
5f4273c7 NC |
21630 | |
21631 | /* Update the instruction. */ | |
4962c51a MS |
21632 | md_number_to_chars (buf, insn, INSN_SIZE); |
21633 | } | |
21634 | break; | |
21635 | ||
21636 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21637 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21638 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21639 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21640 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21641 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
9c2799c2 | 21642 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21643 | if (!seg->use_rela_p) |
21644 | { | |
21645 | bfd_vma insn; | |
21646 | bfd_vma addend_abs = abs (value); | |
21647 | ||
21648 | /* Check that the absolute value of the addend can be | |
21649 | encoded in 8 bits. */ | |
21650 | if (addend_abs >= 0x100) | |
21651 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21652 | _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), | |
495bde8e | 21653 | (unsigned long) addend_abs); |
4962c51a MS |
21654 | |
21655 | /* Extract the instruction. */ | |
21656 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21657 | ||
21658 | /* If the addend is negative, clear bit 23 of the instruction. | |
21659 | Otherwise set it. */ | |
21660 | if (value < 0) | |
21661 | insn &= ~(1 << 23); | |
21662 | else | |
21663 | insn |= 1 << 23; | |
21664 | ||
21665 | /* Place the first four bits of the absolute value of the addend | |
21666 | into the first 4 bits of the instruction, and the remaining | |
21667 | four into bits 8 .. 11. */ | |
21668 | insn &= 0xfffff0f0; | |
21669 | insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); | |
5f4273c7 NC |
21670 | |
21671 | /* Update the instruction. */ | |
4962c51a MS |
21672 | md_number_to_chars (buf, insn, INSN_SIZE); |
21673 | } | |
21674 | break; | |
21675 | ||
21676 | case BFD_RELOC_ARM_LDC_PC_G0: | |
21677 | case BFD_RELOC_ARM_LDC_PC_G1: | |
21678 | case BFD_RELOC_ARM_LDC_PC_G2: | |
21679 | case BFD_RELOC_ARM_LDC_SB_G0: | |
21680 | case BFD_RELOC_ARM_LDC_SB_G1: | |
21681 | case BFD_RELOC_ARM_LDC_SB_G2: | |
9c2799c2 | 21682 | gas_assert (!fixP->fx_done); |
4962c51a MS |
21683 | if (!seg->use_rela_p) |
21684 | { | |
21685 | bfd_vma insn; | |
21686 | bfd_vma addend_abs = abs (value); | |
21687 | ||
21688 | /* Check that the absolute value of the addend is a multiple of | |
21689 | four and, when divided by four, fits in 8 bits. */ | |
21690 | if (addend_abs & 0x3) | |
21691 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21692 | _("bad offset 0x%08lX (must be word-aligned)"), | |
495bde8e | 21693 | (unsigned long) addend_abs); |
4962c51a MS |
21694 | |
21695 | if ((addend_abs >> 2) > 0xff) | |
21696 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21697 | _("bad offset 0x%08lX (must be an 8-bit number of words)"), | |
495bde8e | 21698 | (unsigned long) addend_abs); |
4962c51a MS |
21699 | |
21700 | /* Extract the instruction. */ | |
21701 | insn = md_chars_to_number (buf, INSN_SIZE); | |
21702 | ||
21703 | /* If the addend is negative, clear bit 23 of the instruction. | |
21704 | Otherwise set it. */ | |
21705 | if (value < 0) | |
21706 | insn &= ~(1 << 23); | |
21707 | else | |
21708 | insn |= 1 << 23; | |
21709 | ||
21710 | /* Place the addend (divided by four) into the first eight | |
21711 | bits of the instruction. */ | |
21712 | insn &= 0xfffffff0; | |
21713 | insn |= addend_abs >> 2; | |
5f4273c7 NC |
21714 | |
21715 | /* Update the instruction. */ | |
4962c51a MS |
21716 | md_number_to_chars (buf, insn, INSN_SIZE); |
21717 | } | |
21718 | break; | |
21719 | ||
845b51d6 PB |
21720 | case BFD_RELOC_ARM_V4BX: |
21721 | /* This will need to go in the object file. */ | |
21722 | fixP->fx_done = 0; | |
21723 | break; | |
21724 | ||
c19d1205 ZW |
21725 | case BFD_RELOC_UNUSED: |
21726 | default: | |
21727 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
21728 | _("bad relocation fixup type (%d)"), fixP->fx_r_type); | |
21729 | } | |
6c43fab6 RE |
21730 | } |
21731 | ||
c19d1205 ZW |
21732 | /* Translate internal representation of relocation info to BFD target |
21733 | format. */ | |
a737bd4d | 21734 | |
c19d1205 | 21735 | arelent * |
00a97672 | 21736 | tc_gen_reloc (asection *section, fixS *fixp) |
a737bd4d | 21737 | { |
c19d1205 ZW |
21738 | arelent * reloc; |
21739 | bfd_reloc_code_real_type code; | |
a737bd4d | 21740 | |
21d799b5 | 21741 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
a737bd4d | 21742 | |
21d799b5 | 21743 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
c19d1205 ZW |
21744 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
21745 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
a737bd4d | 21746 | |
2fc8bdac | 21747 | if (fixp->fx_pcrel) |
00a97672 RS |
21748 | { |
21749 | if (section->use_rela_p) | |
21750 | fixp->fx_offset -= md_pcrel_from_section (fixp, section); | |
21751 | else | |
21752 | fixp->fx_offset = reloc->address; | |
21753 | } | |
c19d1205 | 21754 | reloc->addend = fixp->fx_offset; |
a737bd4d | 21755 | |
c19d1205 | 21756 | switch (fixp->fx_r_type) |
a737bd4d | 21757 | { |
c19d1205 ZW |
21758 | case BFD_RELOC_8: |
21759 | if (fixp->fx_pcrel) | |
21760 | { | |
21761 | code = BFD_RELOC_8_PCREL; | |
21762 | break; | |
21763 | } | |
a737bd4d | 21764 | |
c19d1205 ZW |
21765 | case BFD_RELOC_16: |
21766 | if (fixp->fx_pcrel) | |
21767 | { | |
21768 | code = BFD_RELOC_16_PCREL; | |
21769 | break; | |
21770 | } | |
6c43fab6 | 21771 | |
c19d1205 ZW |
21772 | case BFD_RELOC_32: |
21773 | if (fixp->fx_pcrel) | |
21774 | { | |
21775 | code = BFD_RELOC_32_PCREL; | |
21776 | break; | |
21777 | } | |
a737bd4d | 21778 | |
b6895b4f PB |
21779 | case BFD_RELOC_ARM_MOVW: |
21780 | if (fixp->fx_pcrel) | |
21781 | { | |
21782 | code = BFD_RELOC_ARM_MOVW_PCREL; | |
21783 | break; | |
21784 | } | |
21785 | ||
21786 | case BFD_RELOC_ARM_MOVT: | |
21787 | if (fixp->fx_pcrel) | |
21788 | { | |
21789 | code = BFD_RELOC_ARM_MOVT_PCREL; | |
21790 | break; | |
21791 | } | |
21792 | ||
21793 | case BFD_RELOC_ARM_THUMB_MOVW: | |
21794 | if (fixp->fx_pcrel) | |
21795 | { | |
21796 | code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; | |
21797 | break; | |
21798 | } | |
21799 | ||
21800 | case BFD_RELOC_ARM_THUMB_MOVT: | |
21801 | if (fixp->fx_pcrel) | |
21802 | { | |
21803 | code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; | |
21804 | break; | |
21805 | } | |
21806 | ||
c19d1205 ZW |
21807 | case BFD_RELOC_NONE: |
21808 | case BFD_RELOC_ARM_PCREL_BRANCH: | |
21809 | case BFD_RELOC_ARM_PCREL_BLX: | |
21810 | case BFD_RELOC_RVA: | |
21811 | case BFD_RELOC_THUMB_PCREL_BRANCH7: | |
21812 | case BFD_RELOC_THUMB_PCREL_BRANCH9: | |
21813 | case BFD_RELOC_THUMB_PCREL_BRANCH12: | |
21814 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
21815 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
21816 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
c19d1205 ZW |
21817 | case BFD_RELOC_VTABLE_ENTRY: |
21818 | case BFD_RELOC_VTABLE_INHERIT: | |
f0927246 NC |
21819 | #ifdef TE_PE |
21820 | case BFD_RELOC_32_SECREL: | |
21821 | #endif | |
c19d1205 ZW |
21822 | code = fixp->fx_r_type; |
21823 | break; | |
a737bd4d | 21824 | |
00adf2d4 JB |
21825 | case BFD_RELOC_THUMB_PCREL_BLX: |
21826 | #ifdef OBJ_ELF | |
21827 | if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) | |
21828 | code = BFD_RELOC_THUMB_PCREL_BRANCH23; | |
21829 | else | |
21830 | #endif | |
21831 | code = BFD_RELOC_THUMB_PCREL_BLX; | |
21832 | break; | |
21833 | ||
c19d1205 ZW |
21834 | case BFD_RELOC_ARM_LITERAL: |
21835 | case BFD_RELOC_ARM_HWLITERAL: | |
21836 | /* If this is called then the a literal has | |
21837 | been referenced across a section boundary. */ | |
21838 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21839 | _("literal referenced across section boundary")); | |
21840 | return NULL; | |
a737bd4d | 21841 | |
c19d1205 | 21842 | #ifdef OBJ_ELF |
0855e32b NS |
21843 | case BFD_RELOC_ARM_TLS_CALL: |
21844 | case BFD_RELOC_ARM_THM_TLS_CALL: | |
21845 | case BFD_RELOC_ARM_TLS_DESCSEQ: | |
21846 | case BFD_RELOC_ARM_THM_TLS_DESCSEQ: | |
c19d1205 ZW |
21847 | case BFD_RELOC_ARM_GOT32: |
21848 | case BFD_RELOC_ARM_GOTOFF: | |
b43420e6 | 21849 | case BFD_RELOC_ARM_GOT_PREL: |
c19d1205 ZW |
21850 | case BFD_RELOC_ARM_PLT32: |
21851 | case BFD_RELOC_ARM_TARGET1: | |
21852 | case BFD_RELOC_ARM_ROSEGREL32: | |
21853 | case BFD_RELOC_ARM_SBREL32: | |
21854 | case BFD_RELOC_ARM_PREL31: | |
21855 | case BFD_RELOC_ARM_TARGET2: | |
21856 | case BFD_RELOC_ARM_TLS_LE32: | |
21857 | case BFD_RELOC_ARM_TLS_LDO32: | |
39b41c9c PB |
21858 | case BFD_RELOC_ARM_PCREL_CALL: |
21859 | case BFD_RELOC_ARM_PCREL_JUMP: | |
4962c51a MS |
21860 | case BFD_RELOC_ARM_ALU_PC_G0_NC: |
21861 | case BFD_RELOC_ARM_ALU_PC_G0: | |
21862 | case BFD_RELOC_ARM_ALU_PC_G1_NC: | |
21863 | case BFD_RELOC_ARM_ALU_PC_G1: | |
21864 | case BFD_RELOC_ARM_ALU_PC_G2: | |
21865 | case BFD_RELOC_ARM_LDR_PC_G0: | |
21866 | case BFD_RELOC_ARM_LDR_PC_G1: | |
21867 | case BFD_RELOC_ARM_LDR_PC_G2: | |
21868 | case BFD_RELOC_ARM_LDRS_PC_G0: | |
21869 | case BFD_RELOC_ARM_LDRS_PC_G1: | |
21870 | case BFD_RELOC_ARM_LDRS_PC_G2: | |
21871 | case BFD_RELOC_ARM_LDC_PC_G0: | |
21872 | case BFD_RELOC_ARM_LDC_PC_G1: | |
21873 | case BFD_RELOC_ARM_LDC_PC_G2: | |
21874 | case BFD_RELOC_ARM_ALU_SB_G0_NC: | |
21875 | case BFD_RELOC_ARM_ALU_SB_G0: | |
21876 | case BFD_RELOC_ARM_ALU_SB_G1_NC: | |
21877 | case BFD_RELOC_ARM_ALU_SB_G1: | |
21878 | case BFD_RELOC_ARM_ALU_SB_G2: | |
21879 | case BFD_RELOC_ARM_LDR_SB_G0: | |
21880 | case BFD_RELOC_ARM_LDR_SB_G1: | |
21881 | case BFD_RELOC_ARM_LDR_SB_G2: | |
21882 | case BFD_RELOC_ARM_LDRS_SB_G0: | |
21883 | case BFD_RELOC_ARM_LDRS_SB_G1: | |
21884 | case BFD_RELOC_ARM_LDRS_SB_G2: | |
21885 | case BFD_RELOC_ARM_LDC_SB_G0: | |
21886 | case BFD_RELOC_ARM_LDC_SB_G1: | |
21887 | case BFD_RELOC_ARM_LDC_SB_G2: | |
845b51d6 | 21888 | case BFD_RELOC_ARM_V4BX: |
c19d1205 ZW |
21889 | code = fixp->fx_r_type; |
21890 | break; | |
a737bd4d | 21891 | |
0855e32b | 21892 | case BFD_RELOC_ARM_TLS_GOTDESC: |
c19d1205 ZW |
21893 | case BFD_RELOC_ARM_TLS_GD32: |
21894 | case BFD_RELOC_ARM_TLS_IE32: | |
21895 | case BFD_RELOC_ARM_TLS_LDM32: | |
21896 | /* BFD will include the symbol's address in the addend. | |
21897 | But we don't want that, so subtract it out again here. */ | |
21898 | if (!S_IS_COMMON (fixp->fx_addsy)) | |
21899 | reloc->addend -= (*reloc->sym_ptr_ptr)->value; | |
21900 | code = fixp->fx_r_type; | |
21901 | break; | |
21902 | #endif | |
a737bd4d | 21903 | |
c19d1205 ZW |
21904 | case BFD_RELOC_ARM_IMMEDIATE: |
21905 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21906 | _("internal relocation (type: IMMEDIATE) not fixed up")); | |
21907 | return NULL; | |
a737bd4d | 21908 | |
c19d1205 ZW |
21909 | case BFD_RELOC_ARM_ADRL_IMMEDIATE: |
21910 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21911 | _("ADRL used for a symbol not defined in the same file")); | |
21912 | return NULL; | |
a737bd4d | 21913 | |
c19d1205 | 21914 | case BFD_RELOC_ARM_OFFSET_IMM: |
00a97672 RS |
21915 | if (section->use_rela_p) |
21916 | { | |
21917 | code = fixp->fx_r_type; | |
21918 | break; | |
21919 | } | |
21920 | ||
c19d1205 ZW |
21921 | if (fixp->fx_addsy != NULL |
21922 | && !S_IS_DEFINED (fixp->fx_addsy) | |
21923 | && S_IS_LOCAL (fixp->fx_addsy)) | |
a737bd4d | 21924 | { |
c19d1205 ZW |
21925 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21926 | _("undefined local label `%s'"), | |
21927 | S_GET_NAME (fixp->fx_addsy)); | |
21928 | return NULL; | |
a737bd4d NC |
21929 | } |
21930 | ||
c19d1205 ZW |
21931 | as_bad_where (fixp->fx_file, fixp->fx_line, |
21932 | _("internal_relocation (type: OFFSET_IMM) not fixed up")); | |
21933 | return NULL; | |
a737bd4d | 21934 | |
c19d1205 ZW |
21935 | default: |
21936 | { | |
21937 | char * type; | |
6c43fab6 | 21938 | |
c19d1205 ZW |
21939 | switch (fixp->fx_r_type) |
21940 | { | |
21941 | case BFD_RELOC_NONE: type = "NONE"; break; | |
21942 | case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; | |
21943 | case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; | |
3eb17e6b | 21944 | case BFD_RELOC_ARM_SMC: type = "SMC"; break; |
c19d1205 ZW |
21945 | case BFD_RELOC_ARM_SWI: type = "SWI"; break; |
21946 | case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; | |
21947 | case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; | |
db187cb9 | 21948 | case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break; |
8f06b2d8 | 21949 | case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; |
c19d1205 ZW |
21950 | case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; |
21951 | case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; | |
21952 | case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; | |
21953 | case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; | |
21954 | default: type = _("<unknown>"); break; | |
21955 | } | |
21956 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21957 | _("cannot represent %s relocation in this object file format"), | |
21958 | type); | |
21959 | return NULL; | |
21960 | } | |
a737bd4d | 21961 | } |
6c43fab6 | 21962 | |
c19d1205 ZW |
21963 | #ifdef OBJ_ELF |
21964 | if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) | |
21965 | && GOT_symbol | |
21966 | && fixp->fx_addsy == GOT_symbol) | |
21967 | { | |
21968 | code = BFD_RELOC_ARM_GOTPC; | |
21969 | reloc->addend = fixp->fx_offset = reloc->address; | |
21970 | } | |
21971 | #endif | |
6c43fab6 | 21972 | |
c19d1205 | 21973 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
6c43fab6 | 21974 | |
c19d1205 ZW |
21975 | if (reloc->howto == NULL) |
21976 | { | |
21977 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
21978 | _("cannot represent %s relocation in this object file format"), | |
21979 | bfd_get_reloc_code_name (code)); | |
21980 | return NULL; | |
21981 | } | |
6c43fab6 | 21982 | |
c19d1205 ZW |
21983 | /* HACK: Since arm ELF uses Rel instead of Rela, encode the |
21984 | vtable entry to be used in the relocation's section offset. */ | |
21985 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
21986 | reloc->address = fixp->fx_offset; | |
6c43fab6 | 21987 | |
c19d1205 | 21988 | return reloc; |
6c43fab6 RE |
21989 | } |
21990 | ||
c19d1205 | 21991 | /* This fix_new is called by cons via TC_CONS_FIX_NEW. */ |
6c43fab6 | 21992 | |
c19d1205 ZW |
21993 | void |
21994 | cons_fix_new_arm (fragS * frag, | |
21995 | int where, | |
21996 | int size, | |
21997 | expressionS * exp) | |
6c43fab6 | 21998 | { |
c19d1205 ZW |
21999 | bfd_reloc_code_real_type type; |
22000 | int pcrel = 0; | |
6c43fab6 | 22001 | |
c19d1205 ZW |
22002 | /* Pick a reloc. |
22003 | FIXME: @@ Should look at CPU word size. */ | |
22004 | switch (size) | |
22005 | { | |
22006 | case 1: | |
22007 | type = BFD_RELOC_8; | |
22008 | break; | |
22009 | case 2: | |
22010 | type = BFD_RELOC_16; | |
22011 | break; | |
22012 | case 4: | |
22013 | default: | |
22014 | type = BFD_RELOC_32; | |
22015 | break; | |
22016 | case 8: | |
22017 | type = BFD_RELOC_64; | |
22018 | break; | |
22019 | } | |
6c43fab6 | 22020 | |
f0927246 NC |
22021 | #ifdef TE_PE |
22022 | if (exp->X_op == O_secrel) | |
22023 | { | |
22024 | exp->X_op = O_symbol; | |
22025 | type = BFD_RELOC_32_SECREL; | |
22026 | } | |
22027 | #endif | |
22028 | ||
c19d1205 ZW |
22029 | fix_new_exp (frag, where, (int) size, exp, pcrel, type); |
22030 | } | |
6c43fab6 | 22031 | |
4343666d | 22032 | #if defined (OBJ_COFF) |
c19d1205 ZW |
22033 | void |
22034 | arm_validate_fix (fixS * fixP) | |
6c43fab6 | 22035 | { |
c19d1205 ZW |
22036 | /* If the destination of the branch is a defined symbol which does not have |
22037 | the THUMB_FUNC attribute, then we must be calling a function which has | |
22038 | the (interfacearm) attribute. We look for the Thumb entry point to that | |
22039 | function and change the branch to refer to that function instead. */ | |
22040 | if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 | |
22041 | && fixP->fx_addsy != NULL | |
22042 | && S_IS_DEFINED (fixP->fx_addsy) | |
22043 | && ! THUMB_IS_FUNC (fixP->fx_addsy)) | |
6c43fab6 | 22044 | { |
c19d1205 | 22045 | fixP->fx_addsy = find_real_start (fixP->fx_addsy); |
6c43fab6 | 22046 | } |
c19d1205 ZW |
22047 | } |
22048 | #endif | |
6c43fab6 | 22049 | |
267bf995 | 22050 | |
c19d1205 ZW |
22051 | int |
22052 | arm_force_relocation (struct fix * fixp) | |
22053 | { | |
22054 | #if defined (OBJ_COFF) && defined (TE_PE) | |
22055 | if (fixp->fx_r_type == BFD_RELOC_RVA) | |
22056 | return 1; | |
22057 | #endif | |
6c43fab6 | 22058 | |
267bf995 RR |
22059 | /* In case we have a call or a branch to a function in ARM ISA mode from |
22060 | a thumb function or vice-versa force the relocation. These relocations | |
22061 | are cleared off for some cores that might have blx and simple transformations | |
22062 | are possible. */ | |
22063 | ||
22064 | #ifdef OBJ_ELF | |
22065 | switch (fixp->fx_r_type) | |
22066 | { | |
22067 | case BFD_RELOC_ARM_PCREL_JUMP: | |
22068 | case BFD_RELOC_ARM_PCREL_CALL: | |
22069 | case BFD_RELOC_THUMB_PCREL_BLX: | |
22070 | if (THUMB_IS_FUNC (fixp->fx_addsy)) | |
22071 | return 1; | |
22072 | break; | |
22073 | ||
22074 | case BFD_RELOC_ARM_PCREL_BLX: | |
22075 | case BFD_RELOC_THUMB_PCREL_BRANCH25: | |
22076 | case BFD_RELOC_THUMB_PCREL_BRANCH20: | |
22077 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
22078 | if (ARM_IS_FUNC (fixp->fx_addsy)) | |
22079 | return 1; | |
22080 | break; | |
22081 | ||
22082 | default: | |
22083 | break; | |
22084 | } | |
22085 | #endif | |
22086 | ||
b5884301 PB |
22087 | /* Resolve these relocations even if the symbol is extern or weak. |
22088 | Technically this is probably wrong due to symbol preemption. | |
22089 | In practice these relocations do not have enough range to be useful | |
22090 | at dynamic link time, and some code (e.g. in the Linux kernel) | |
22091 | expects these references to be resolved. */ | |
c19d1205 ZW |
22092 | if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE |
22093 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM | |
b5884301 | 22094 | || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8 |
0110f2b8 | 22095 | || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE |
b5884301 PB |
22096 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM |
22097 | || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2 | |
22098 | || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET | |
16805f35 | 22099 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM |
0110f2b8 PB |
22100 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE |
22101 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 | |
b5884301 PB |
22102 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM |
22103 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12 | |
22104 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM | |
22105 | || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2) | |
c19d1205 | 22106 | return 0; |
a737bd4d | 22107 | |
4962c51a MS |
22108 | /* Always leave these relocations for the linker. */ |
22109 | if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
22110 | && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
22111 | || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
22112 | return 1; | |
22113 | ||
f0291e4c PB |
22114 | /* Always generate relocations against function symbols. */ |
22115 | if (fixp->fx_r_type == BFD_RELOC_32 | |
22116 | && fixp->fx_addsy | |
22117 | && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) | |
22118 | return 1; | |
22119 | ||
c19d1205 | 22120 | return generic_force_reloc (fixp); |
404ff6b5 AH |
22121 | } |
22122 | ||
0ffdc86c | 22123 | #if defined (OBJ_ELF) || defined (OBJ_COFF) |
e28387c3 PB |
22124 | /* Relocations against function names must be left unadjusted, |
22125 | so that the linker can use this information to generate interworking | |
22126 | stubs. The MIPS version of this function | |
c19d1205 ZW |
22127 | also prevents relocations that are mips-16 specific, but I do not |
22128 | know why it does this. | |
404ff6b5 | 22129 | |
c19d1205 ZW |
22130 | FIXME: |
22131 | There is one other problem that ought to be addressed here, but | |
22132 | which currently is not: Taking the address of a label (rather | |
22133 | than a function) and then later jumping to that address. Such | |
22134 | addresses also ought to have their bottom bit set (assuming that | |
22135 | they reside in Thumb code), but at the moment they will not. */ | |
404ff6b5 | 22136 | |
c19d1205 ZW |
22137 | bfd_boolean |
22138 | arm_fix_adjustable (fixS * fixP) | |
404ff6b5 | 22139 | { |
c19d1205 ZW |
22140 | if (fixP->fx_addsy == NULL) |
22141 | return 1; | |
404ff6b5 | 22142 | |
e28387c3 PB |
22143 | /* Preserve relocations against symbols with function type. */ |
22144 | if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) | |
c921be7d | 22145 | return FALSE; |
e28387c3 | 22146 | |
c19d1205 ZW |
22147 | if (THUMB_IS_FUNC (fixP->fx_addsy) |
22148 | && fixP->fx_subsy == NULL) | |
c921be7d | 22149 | return FALSE; |
a737bd4d | 22150 | |
c19d1205 ZW |
22151 | /* We need the symbol name for the VTABLE entries. */ |
22152 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
22153 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
c921be7d | 22154 | return FALSE; |
404ff6b5 | 22155 | |
c19d1205 ZW |
22156 | /* Don't allow symbols to be discarded on GOT related relocs. */ |
22157 | if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 | |
22158 | || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 | |
22159 | || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF | |
22160 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 | |
22161 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 | |
22162 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 | |
22163 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 | |
22164 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 | |
0855e32b NS |
22165 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC |
22166 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL | |
22167 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL | |
22168 | || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ | |
22169 | || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ | |
c19d1205 | 22170 | || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) |
c921be7d | 22171 | return FALSE; |
a737bd4d | 22172 | |
4962c51a MS |
22173 | /* Similarly for group relocations. */ |
22174 | if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC | |
22175 | && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) | |
22176 | || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) | |
c921be7d | 22177 | return FALSE; |
4962c51a | 22178 | |
79947c54 CD |
22179 | /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */ |
22180 | if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW | |
22181 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT | |
22182 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL | |
22183 | || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL | |
22184 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW | |
22185 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT | |
22186 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL | |
22187 | || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL) | |
c921be7d | 22188 | return FALSE; |
79947c54 | 22189 | |
c921be7d | 22190 | return TRUE; |
a737bd4d | 22191 | } |
0ffdc86c NC |
22192 | #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ |
22193 | ||
22194 | #ifdef OBJ_ELF | |
404ff6b5 | 22195 | |
c19d1205 ZW |
22196 | const char * |
22197 | elf32_arm_target_format (void) | |
404ff6b5 | 22198 | { |
c19d1205 ZW |
22199 | #ifdef TE_SYMBIAN |
22200 | return (target_big_endian | |
22201 | ? "elf32-bigarm-symbian" | |
22202 | : "elf32-littlearm-symbian"); | |
22203 | #elif defined (TE_VXWORKS) | |
22204 | return (target_big_endian | |
22205 | ? "elf32-bigarm-vxworks" | |
22206 | : "elf32-littlearm-vxworks"); | |
22207 | #else | |
22208 | if (target_big_endian) | |
22209 | return "elf32-bigarm"; | |
22210 | else | |
22211 | return "elf32-littlearm"; | |
22212 | #endif | |
404ff6b5 AH |
22213 | } |
22214 | ||
c19d1205 ZW |
22215 | void |
22216 | armelf_frob_symbol (symbolS * symp, | |
22217 | int * puntp) | |
404ff6b5 | 22218 | { |
c19d1205 ZW |
22219 | elf_frob_symbol (symp, puntp); |
22220 | } | |
22221 | #endif | |
404ff6b5 | 22222 | |
c19d1205 | 22223 | /* MD interface: Finalization. */ |
a737bd4d | 22224 | |
c19d1205 ZW |
22225 | void |
22226 | arm_cleanup (void) | |
22227 | { | |
22228 | literal_pool * pool; | |
a737bd4d | 22229 | |
e07e6e58 NC |
22230 | /* Ensure that all the IT blocks are properly closed. */ |
22231 | check_it_blocks_finished (); | |
22232 | ||
c19d1205 ZW |
22233 | for (pool = list_of_pools; pool; pool = pool->next) |
22234 | { | |
5f4273c7 | 22235 | /* Put it at the end of the relevant section. */ |
c19d1205 ZW |
22236 | subseg_set (pool->section, pool->sub_section); |
22237 | #ifdef OBJ_ELF | |
22238 | arm_elf_change_section (); | |
22239 | #endif | |
22240 | s_ltorg (0); | |
22241 | } | |
404ff6b5 AH |
22242 | } |
22243 | ||
cd000bff DJ |
22244 | #ifdef OBJ_ELF |
22245 | /* Remove any excess mapping symbols generated for alignment frags in | |
22246 | SEC. We may have created a mapping symbol before a zero byte | |
22247 | alignment; remove it if there's a mapping symbol after the | |
22248 | alignment. */ | |
22249 | static void | |
22250 | check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, | |
22251 | void *dummy ATTRIBUTE_UNUSED) | |
22252 | { | |
22253 | segment_info_type *seginfo = seg_info (sec); | |
22254 | fragS *fragp; | |
22255 | ||
22256 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
22257 | return; | |
22258 | ||
22259 | for (fragp = seginfo->frchainP->frch_root; | |
22260 | fragp != NULL; | |
22261 | fragp = fragp->fr_next) | |
22262 | { | |
22263 | symbolS *sym = fragp->tc_frag_data.last_map; | |
22264 | fragS *next = fragp->fr_next; | |
22265 | ||
22266 | /* Variable-sized frags have been converted to fixed size by | |
22267 | this point. But if this was variable-sized to start with, | |
22268 | there will be a fixed-size frag after it. So don't handle | |
22269 | next == NULL. */ | |
22270 | if (sym == NULL || next == NULL) | |
22271 | continue; | |
22272 | ||
22273 | if (S_GET_VALUE (sym) < next->fr_address) | |
22274 | /* Not at the end of this frag. */ | |
22275 | continue; | |
22276 | know (S_GET_VALUE (sym) == next->fr_address); | |
22277 | ||
22278 | do | |
22279 | { | |
22280 | if (next->tc_frag_data.first_map != NULL) | |
22281 | { | |
22282 | /* Next frag starts with a mapping symbol. Discard this | |
22283 | one. */ | |
22284 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
22285 | break; | |
22286 | } | |
22287 | ||
22288 | if (next->fr_next == NULL) | |
22289 | { | |
22290 | /* This mapping symbol is at the end of the section. Discard | |
22291 | it. */ | |
22292 | know (next->fr_fix == 0 && next->fr_var == 0); | |
22293 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
22294 | break; | |
22295 | } | |
22296 | ||
22297 | /* As long as we have empty frags without any mapping symbols, | |
22298 | keep looking. */ | |
22299 | /* If the next frag is non-empty and does not start with a | |
22300 | mapping symbol, then this mapping symbol is required. */ | |
22301 | if (next->fr_address != next->fr_next->fr_address) | |
22302 | break; | |
22303 | ||
22304 | next = next->fr_next; | |
22305 | } | |
22306 | while (next != NULL); | |
22307 | } | |
22308 | } | |
22309 | #endif | |
22310 | ||
c19d1205 ZW |
22311 | /* Adjust the symbol table. This marks Thumb symbols as distinct from |
22312 | ARM ones. */ | |
404ff6b5 | 22313 | |
c19d1205 ZW |
22314 | void |
22315 | arm_adjust_symtab (void) | |
404ff6b5 | 22316 | { |
c19d1205 ZW |
22317 | #ifdef OBJ_COFF |
22318 | symbolS * sym; | |
404ff6b5 | 22319 | |
c19d1205 ZW |
22320 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
22321 | { | |
22322 | if (ARM_IS_THUMB (sym)) | |
22323 | { | |
22324 | if (THUMB_IS_FUNC (sym)) | |
22325 | { | |
22326 | /* Mark the symbol as a Thumb function. */ | |
22327 | if ( S_GET_STORAGE_CLASS (sym) == C_STAT | |
22328 | || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ | |
22329 | S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); | |
404ff6b5 | 22330 | |
c19d1205 ZW |
22331 | else if (S_GET_STORAGE_CLASS (sym) == C_EXT) |
22332 | S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); | |
22333 | else | |
22334 | as_bad (_("%s: unexpected function type: %d"), | |
22335 | S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); | |
22336 | } | |
22337 | else switch (S_GET_STORAGE_CLASS (sym)) | |
22338 | { | |
22339 | case C_EXT: | |
22340 | S_SET_STORAGE_CLASS (sym, C_THUMBEXT); | |
22341 | break; | |
22342 | case C_STAT: | |
22343 | S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); | |
22344 | break; | |
22345 | case C_LABEL: | |
22346 | S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); | |
22347 | break; | |
22348 | default: | |
22349 | /* Do nothing. */ | |
22350 | break; | |
22351 | } | |
22352 | } | |
a737bd4d | 22353 | |
c19d1205 ZW |
22354 | if (ARM_IS_INTERWORK (sym)) |
22355 | coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; | |
404ff6b5 | 22356 | } |
c19d1205 ZW |
22357 | #endif |
22358 | #ifdef OBJ_ELF | |
22359 | symbolS * sym; | |
22360 | char bind; | |
404ff6b5 | 22361 | |
c19d1205 | 22362 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) |
404ff6b5 | 22363 | { |
c19d1205 ZW |
22364 | if (ARM_IS_THUMB (sym)) |
22365 | { | |
22366 | elf_symbol_type * elf_sym; | |
404ff6b5 | 22367 | |
c19d1205 ZW |
22368 | elf_sym = elf_symbol (symbol_get_bfdsym (sym)); |
22369 | bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); | |
404ff6b5 | 22370 | |
b0796911 PB |
22371 | if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, |
22372 | BFD_ARM_SPECIAL_SYM_TYPE_ANY)) | |
c19d1205 ZW |
22373 | { |
22374 | /* If it's a .thumb_func, declare it as so, | |
22375 | otherwise tag label as .code 16. */ | |
22376 | if (THUMB_IS_FUNC (sym)) | |
35fc36a8 RS |
22377 | elf_sym->internal_elf_sym.st_target_internal |
22378 | = ST_BRANCH_TO_THUMB; | |
3ba67470 | 22379 | else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
c19d1205 ZW |
22380 | elf_sym->internal_elf_sym.st_info = |
22381 | ELF_ST_INFO (bind, STT_ARM_16BIT); | |
22382 | } | |
22383 | } | |
22384 | } | |
cd000bff DJ |
22385 | |
22386 | /* Remove any overlapping mapping symbols generated by alignment frags. */ | |
22387 | bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0); | |
709001e9 MM |
22388 | /* Now do generic ELF adjustments. */ |
22389 | elf_adjust_symtab (); | |
c19d1205 | 22390 | #endif |
404ff6b5 AH |
22391 | } |
22392 | ||
c19d1205 | 22393 | /* MD interface: Initialization. */ |
404ff6b5 | 22394 | |
a737bd4d | 22395 | static void |
c19d1205 | 22396 | set_constant_flonums (void) |
a737bd4d | 22397 | { |
c19d1205 | 22398 | int i; |
404ff6b5 | 22399 | |
c19d1205 ZW |
22400 | for (i = 0; i < NUM_FLOAT_VALS; i++) |
22401 | if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) | |
22402 | abort (); | |
a737bd4d | 22403 | } |
404ff6b5 | 22404 | |
3e9e4fcf JB |
22405 | /* Auto-select Thumb mode if it's the only available instruction set for the |
22406 | given architecture. */ | |
22407 | ||
22408 | static void | |
22409 | autoselect_thumb_from_cpu_variant (void) | |
22410 | { | |
22411 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) | |
22412 | opcode_select (16); | |
22413 | } | |
22414 | ||
c19d1205 ZW |
22415 | void |
22416 | md_begin (void) | |
a737bd4d | 22417 | { |
c19d1205 ZW |
22418 | unsigned mach; |
22419 | unsigned int i; | |
404ff6b5 | 22420 | |
c19d1205 ZW |
22421 | if ( (arm_ops_hsh = hash_new ()) == NULL |
22422 | || (arm_cond_hsh = hash_new ()) == NULL | |
22423 | || (arm_shift_hsh = hash_new ()) == NULL | |
22424 | || (arm_psr_hsh = hash_new ()) == NULL | |
62b3e311 | 22425 | || (arm_v7m_psr_hsh = hash_new ()) == NULL |
c19d1205 | 22426 | || (arm_reg_hsh = hash_new ()) == NULL |
62b3e311 PB |
22427 | || (arm_reloc_hsh = hash_new ()) == NULL |
22428 | || (arm_barrier_opt_hsh = hash_new ()) == NULL) | |
c19d1205 ZW |
22429 | as_fatal (_("virtual memory exhausted")); |
22430 | ||
22431 | for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) | |
d3ce72d0 | 22432 | hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i)); |
c19d1205 | 22433 | for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) |
d3ce72d0 | 22434 | hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i)); |
c19d1205 | 22435 | for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) |
5a49b8ac | 22436 | hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i)); |
c19d1205 | 22437 | for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 | 22438 | hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i)); |
62b3e311 | 22439 | for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) |
d3ce72d0 NC |
22440 | hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name, |
22441 | (void *) (v7m_psrs + i)); | |
c19d1205 | 22442 | for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) |
5a49b8ac | 22443 | hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i)); |
62b3e311 PB |
22444 | for (i = 0; |
22445 | i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); | |
22446 | i++) | |
d3ce72d0 | 22447 | hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name, |
5a49b8ac | 22448 | (void *) (barrier_opt_names + i)); |
c19d1205 | 22449 | #ifdef OBJ_ELF |
3da1d841 NC |
22450 | for (i = 0; i < ARRAY_SIZE (reloc_names); i++) |
22451 | { | |
22452 | struct reloc_entry * entry = reloc_names + i; | |
22453 | ||
22454 | if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32) | |
22455 | /* This makes encode_branch() use the EABI versions of this relocation. */ | |
22456 | entry->reloc = BFD_RELOC_UNUSED; | |
22457 | ||
22458 | hash_insert (arm_reloc_hsh, entry->name, (void *) entry); | |
22459 | } | |
c19d1205 ZW |
22460 | #endif |
22461 | ||
22462 | set_constant_flonums (); | |
404ff6b5 | 22463 | |
c19d1205 ZW |
22464 | /* Set the cpu variant based on the command-line options. We prefer |
22465 | -mcpu= over -march= if both are set (as for GCC); and we prefer | |
22466 | -mfpu= over any other way of setting the floating point unit. | |
22467 | Use of legacy options with new options are faulted. */ | |
e74cfd16 | 22468 | if (legacy_cpu) |
404ff6b5 | 22469 | { |
e74cfd16 | 22470 | if (mcpu_cpu_opt || march_cpu_opt) |
c19d1205 ZW |
22471 | as_bad (_("use of old and new-style options to set CPU type")); |
22472 | ||
22473 | mcpu_cpu_opt = legacy_cpu; | |
404ff6b5 | 22474 | } |
e74cfd16 | 22475 | else if (!mcpu_cpu_opt) |
c19d1205 | 22476 | mcpu_cpu_opt = march_cpu_opt; |
404ff6b5 | 22477 | |
e74cfd16 | 22478 | if (legacy_fpu) |
c19d1205 | 22479 | { |
e74cfd16 | 22480 | if (mfpu_opt) |
c19d1205 | 22481 | as_bad (_("use of old and new-style options to set FPU type")); |
03b1477f RE |
22482 | |
22483 | mfpu_opt = legacy_fpu; | |
22484 | } | |
e74cfd16 | 22485 | else if (!mfpu_opt) |
03b1477f | 22486 | { |
45eb4c1b NS |
22487 | #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \ |
22488 | || defined (TE_NetBSD) || defined (TE_VXWORKS)) | |
39c2da32 RE |
22489 | /* Some environments specify a default FPU. If they don't, infer it |
22490 | from the processor. */ | |
e74cfd16 | 22491 | if (mcpu_fpu_opt) |
03b1477f RE |
22492 | mfpu_opt = mcpu_fpu_opt; |
22493 | else | |
22494 | mfpu_opt = march_fpu_opt; | |
39c2da32 | 22495 | #else |
e74cfd16 | 22496 | mfpu_opt = &fpu_default; |
39c2da32 | 22497 | #endif |
03b1477f RE |
22498 | } |
22499 | ||
e74cfd16 | 22500 | if (!mfpu_opt) |
03b1477f | 22501 | { |
493cb6ef | 22502 | if (mcpu_cpu_opt != NULL) |
e74cfd16 | 22503 | mfpu_opt = &fpu_default; |
493cb6ef | 22504 | else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) |
e74cfd16 | 22505 | mfpu_opt = &fpu_arch_vfp_v2; |
03b1477f | 22506 | else |
e74cfd16 | 22507 | mfpu_opt = &fpu_arch_fpa; |
03b1477f RE |
22508 | } |
22509 | ||
ee065d83 | 22510 | #ifdef CPU_DEFAULT |
e74cfd16 | 22511 | if (!mcpu_cpu_opt) |
ee065d83 | 22512 | { |
e74cfd16 PB |
22513 | mcpu_cpu_opt = &cpu_default; |
22514 | selected_cpu = cpu_default; | |
ee065d83 | 22515 | } |
e74cfd16 PB |
22516 | #else |
22517 | if (mcpu_cpu_opt) | |
22518 | selected_cpu = *mcpu_cpu_opt; | |
ee065d83 | 22519 | else |
e74cfd16 | 22520 | mcpu_cpu_opt = &arm_arch_any; |
ee065d83 | 22521 | #endif |
03b1477f | 22522 | |
e74cfd16 | 22523 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
03b1477f | 22524 | |
3e9e4fcf JB |
22525 | autoselect_thumb_from_cpu_variant (); |
22526 | ||
e74cfd16 | 22527 | arm_arch_used = thumb_arch_used = arm_arch_none; |
ee065d83 | 22528 | |
f17c130b | 22529 | #if defined OBJ_COFF || defined OBJ_ELF |
b99bd4ef | 22530 | { |
7cc69913 NC |
22531 | unsigned int flags = 0; |
22532 | ||
22533 | #if defined OBJ_ELF | |
22534 | flags = meabi_flags; | |
d507cf36 PB |
22535 | |
22536 | switch (meabi_flags) | |
33a392fb | 22537 | { |
d507cf36 | 22538 | case EF_ARM_EABI_UNKNOWN: |
7cc69913 | 22539 | #endif |
d507cf36 PB |
22540 | /* Set the flags in the private structure. */ |
22541 | if (uses_apcs_26) flags |= F_APCS26; | |
22542 | if (support_interwork) flags |= F_INTERWORK; | |
22543 | if (uses_apcs_float) flags |= F_APCS_FLOAT; | |
c19d1205 | 22544 | if (pic_code) flags |= F_PIC; |
e74cfd16 | 22545 | if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) |
7cc69913 NC |
22546 | flags |= F_SOFT_FLOAT; |
22547 | ||
d507cf36 PB |
22548 | switch (mfloat_abi_opt) |
22549 | { | |
22550 | case ARM_FLOAT_ABI_SOFT: | |
22551 | case ARM_FLOAT_ABI_SOFTFP: | |
22552 | flags |= F_SOFT_FLOAT; | |
22553 | break; | |
33a392fb | 22554 | |
d507cf36 PB |
22555 | case ARM_FLOAT_ABI_HARD: |
22556 | if (flags & F_SOFT_FLOAT) | |
22557 | as_bad (_("hard-float conflicts with specified fpu")); | |
22558 | break; | |
22559 | } | |
03b1477f | 22560 | |
e74cfd16 PB |
22561 | /* Using pure-endian doubles (even if soft-float). */ |
22562 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) | |
7cc69913 | 22563 | flags |= F_VFP_FLOAT; |
f17c130b | 22564 | |
fde78edd | 22565 | #if defined OBJ_ELF |
e74cfd16 | 22566 | if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) |
d507cf36 | 22567 | flags |= EF_ARM_MAVERICK_FLOAT; |
d507cf36 PB |
22568 | break; |
22569 | ||
8cb51566 | 22570 | case EF_ARM_EABI_VER4: |
3a4a14e9 | 22571 | case EF_ARM_EABI_VER5: |
c19d1205 | 22572 | /* No additional flags to set. */ |
d507cf36 PB |
22573 | break; |
22574 | ||
22575 | default: | |
22576 | abort (); | |
22577 | } | |
7cc69913 | 22578 | #endif |
b99bd4ef NC |
22579 | bfd_set_private_flags (stdoutput, flags); |
22580 | ||
22581 | /* We have run out flags in the COFF header to encode the | |
22582 | status of ATPCS support, so instead we create a dummy, | |
c19d1205 | 22583 | empty, debug section called .arm.atpcs. */ |
b99bd4ef NC |
22584 | if (atpcs) |
22585 | { | |
22586 | asection * sec; | |
22587 | ||
22588 | sec = bfd_make_section (stdoutput, ".arm.atpcs"); | |
22589 | ||
22590 | if (sec != NULL) | |
22591 | { | |
22592 | bfd_set_section_flags | |
22593 | (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); | |
22594 | bfd_set_section_size (stdoutput, sec, 0); | |
22595 | bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); | |
22596 | } | |
22597 | } | |
7cc69913 | 22598 | } |
f17c130b | 22599 | #endif |
b99bd4ef NC |
22600 | |
22601 | /* Record the CPU type as well. */ | |
2d447fca JM |
22602 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) |
22603 | mach = bfd_mach_arm_iWMMXt2; | |
22604 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) | |
e16bb312 | 22605 | mach = bfd_mach_arm_iWMMXt; |
e74cfd16 | 22606 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) |
b99bd4ef | 22607 | mach = bfd_mach_arm_XScale; |
e74cfd16 | 22608 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) |
fde78edd | 22609 | mach = bfd_mach_arm_ep9312; |
e74cfd16 | 22610 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) |
b99bd4ef | 22611 | mach = bfd_mach_arm_5TE; |
e74cfd16 | 22612 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) |
b99bd4ef | 22613 | { |
e74cfd16 | 22614 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
22615 | mach = bfd_mach_arm_5T; |
22616 | else | |
22617 | mach = bfd_mach_arm_5; | |
22618 | } | |
e74cfd16 | 22619 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) |
b99bd4ef | 22620 | { |
e74cfd16 | 22621 | if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) |
b99bd4ef NC |
22622 | mach = bfd_mach_arm_4T; |
22623 | else | |
22624 | mach = bfd_mach_arm_4; | |
22625 | } | |
e74cfd16 | 22626 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) |
b99bd4ef | 22627 | mach = bfd_mach_arm_3M; |
e74cfd16 PB |
22628 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) |
22629 | mach = bfd_mach_arm_3; | |
22630 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) | |
22631 | mach = bfd_mach_arm_2a; | |
22632 | else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) | |
22633 | mach = bfd_mach_arm_2; | |
22634 | else | |
22635 | mach = bfd_mach_arm_unknown; | |
b99bd4ef NC |
22636 | |
22637 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); | |
22638 | } | |
22639 | ||
c19d1205 | 22640 | /* Command line processing. */ |
b99bd4ef | 22641 | |
c19d1205 ZW |
22642 | /* md_parse_option |
22643 | Invocation line includes a switch not recognized by the base assembler. | |
22644 | See if it's a processor-specific option. | |
b99bd4ef | 22645 | |
c19d1205 ZW |
22646 | This routine is somewhat complicated by the need for backwards |
22647 | compatibility (since older releases of gcc can't be changed). | |
22648 | The new options try to make the interface as compatible as | |
22649 | possible with GCC. | |
b99bd4ef | 22650 | |
c19d1205 | 22651 | New options (supported) are: |
b99bd4ef | 22652 | |
c19d1205 ZW |
22653 | -mcpu=<cpu name> Assemble for selected processor |
22654 | -march=<architecture name> Assemble for selected architecture | |
22655 | -mfpu=<fpu architecture> Assemble for selected FPU. | |
22656 | -EB/-mbig-endian Big-endian | |
22657 | -EL/-mlittle-endian Little-endian | |
22658 | -k Generate PIC code | |
22659 | -mthumb Start in Thumb mode | |
22660 | -mthumb-interwork Code supports ARM/Thumb interworking | |
b99bd4ef | 22661 | |
278df34e | 22662 | -m[no-]warn-deprecated Warn about deprecated features |
267bf995 | 22663 | |
c19d1205 | 22664 | For now we will also provide support for: |
b99bd4ef | 22665 | |
c19d1205 ZW |
22666 | -mapcs-32 32-bit Program counter |
22667 | -mapcs-26 26-bit Program counter | |
22668 | -macps-float Floats passed in FP registers | |
22669 | -mapcs-reentrant Reentrant code | |
22670 | -matpcs | |
22671 | (sometime these will probably be replaced with -mapcs=<list of options> | |
22672 | and -matpcs=<list of options>) | |
b99bd4ef | 22673 | |
c19d1205 ZW |
22674 | The remaining options are only supported for back-wards compatibility. |
22675 | Cpu variants, the arm part is optional: | |
22676 | -m[arm]1 Currently not supported. | |
22677 | -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor | |
22678 | -m[arm]3 Arm 3 processor | |
22679 | -m[arm]6[xx], Arm 6 processors | |
22680 | -m[arm]7[xx][t][[d]m] Arm 7 processors | |
22681 | -m[arm]8[10] Arm 8 processors | |
22682 | -m[arm]9[20][tdmi] Arm 9 processors | |
22683 | -mstrongarm[110[0]] StrongARM processors | |
22684 | -mxscale XScale processors | |
22685 | -m[arm]v[2345[t[e]]] Arm architectures | |
22686 | -mall All (except the ARM1) | |
22687 | FP variants: | |
22688 | -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions | |
22689 | -mfpe-old (No float load/store multiples) | |
22690 | -mvfpxd VFP Single precision | |
22691 | -mvfp All VFP | |
22692 | -mno-fpu Disable all floating point instructions | |
b99bd4ef | 22693 | |
c19d1205 ZW |
22694 | The following CPU names are recognized: |
22695 | arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, | |
22696 | arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, | |
22697 | arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, | |
22698 | arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, | |
22699 | arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, | |
22700 | arm10t arm10e, arm1020t, arm1020e, arm10200e, | |
22701 | strongarm, strongarm110, strongarm1100, strongarm1110, xscale. | |
b99bd4ef | 22702 | |
c19d1205 | 22703 | */ |
b99bd4ef | 22704 | |
c19d1205 | 22705 | const char * md_shortopts = "m:k"; |
b99bd4ef | 22706 | |
c19d1205 ZW |
22707 | #ifdef ARM_BI_ENDIAN |
22708 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
22709 | #define OPTION_EL (OPTION_MD_BASE + 1) | |
b99bd4ef | 22710 | #else |
c19d1205 ZW |
22711 | #if TARGET_BYTES_BIG_ENDIAN |
22712 | #define OPTION_EB (OPTION_MD_BASE + 0) | |
b99bd4ef | 22713 | #else |
c19d1205 ZW |
22714 | #define OPTION_EL (OPTION_MD_BASE + 1) |
22715 | #endif | |
b99bd4ef | 22716 | #endif |
845b51d6 | 22717 | #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2) |
b99bd4ef | 22718 | |
c19d1205 | 22719 | struct option md_longopts[] = |
b99bd4ef | 22720 | { |
c19d1205 ZW |
22721 | #ifdef OPTION_EB |
22722 | {"EB", no_argument, NULL, OPTION_EB}, | |
22723 | #endif | |
22724 | #ifdef OPTION_EL | |
22725 | {"EL", no_argument, NULL, OPTION_EL}, | |
b99bd4ef | 22726 | #endif |
845b51d6 | 22727 | {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX}, |
c19d1205 ZW |
22728 | {NULL, no_argument, NULL, 0} |
22729 | }; | |
b99bd4ef | 22730 | |
c19d1205 | 22731 | size_t md_longopts_size = sizeof (md_longopts); |
b99bd4ef | 22732 | |
c19d1205 | 22733 | struct arm_option_table |
b99bd4ef | 22734 | { |
c19d1205 ZW |
22735 | char *option; /* Option name to match. */ |
22736 | char *help; /* Help information. */ | |
22737 | int *var; /* Variable to change. */ | |
22738 | int value; /* What to change it to. */ | |
22739 | char *deprecated; /* If non-null, print this message. */ | |
22740 | }; | |
b99bd4ef | 22741 | |
c19d1205 ZW |
22742 | struct arm_option_table arm_opts[] = |
22743 | { | |
22744 | {"k", N_("generate PIC code"), &pic_code, 1, NULL}, | |
22745 | {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, | |
22746 | {"mthumb-interwork", N_("support ARM/Thumb interworking"), | |
22747 | &support_interwork, 1, NULL}, | |
22748 | {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, | |
22749 | {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, | |
22750 | {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, | |
22751 | 1, NULL}, | |
22752 | {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, | |
22753 | {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, | |
22754 | {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, | |
22755 | {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, | |
22756 | NULL}, | |
b99bd4ef | 22757 | |
c19d1205 ZW |
22758 | /* These are recognized by the assembler, but have no affect on code. */ |
22759 | {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, | |
22760 | {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, | |
278df34e NS |
22761 | |
22762 | {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL}, | |
22763 | {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"), | |
22764 | &warn_on_deprecated, 0, NULL}, | |
e74cfd16 PB |
22765 | {NULL, NULL, NULL, 0, NULL} |
22766 | }; | |
22767 | ||
22768 | struct arm_legacy_option_table | |
22769 | { | |
22770 | char *option; /* Option name to match. */ | |
22771 | const arm_feature_set **var; /* Variable to change. */ | |
22772 | const arm_feature_set value; /* What to change it to. */ | |
22773 | char *deprecated; /* If non-null, print this message. */ | |
22774 | }; | |
b99bd4ef | 22775 | |
e74cfd16 PB |
22776 | const struct arm_legacy_option_table arm_legacy_opts[] = |
22777 | { | |
c19d1205 ZW |
22778 | /* DON'T add any new processors to this list -- we want the whole list |
22779 | to go away... Add them to the processors table instead. */ | |
e74cfd16 PB |
22780 | {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, |
22781 | {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, | |
22782 | {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
22783 | {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, | |
22784 | {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
22785 | {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, | |
22786 | {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
22787 | {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, | |
22788 | {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22789 | {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, | |
22790 | {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22791 | {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, | |
22792 | {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22793 | {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, | |
22794 | {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22795 | {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, | |
22796 | {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22797 | {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, | |
22798 | {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22799 | {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, | |
22800 | {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22801 | {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, | |
22802 | {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22803 | {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, | |
22804 | {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22805 | {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, | |
22806 | {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22807 | {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, | |
22808 | {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22809 | {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, | |
22810 | {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22811 | {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, | |
22812 | {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22813 | {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, | |
22814 | {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22815 | {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, | |
22816 | {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22817 | {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, | |
22818 | {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22819 | {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, | |
22820 | {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22821 | {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, | |
22822 | {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22823 | {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, | |
22824 | {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22825 | {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, | |
22826 | {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22827 | {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22828 | {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22829 | {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, | |
22830 | {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22831 | {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, | |
22832 | {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22833 | {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, | |
22834 | {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22835 | {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, | |
22836 | {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22837 | {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, | |
22838 | {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22839 | {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, | |
22840 | {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22841 | {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, | |
22842 | {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22843 | {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, | |
22844 | {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22845 | {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, | |
22846 | {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22847 | {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, | |
22848 | {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, | |
22849 | {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, | |
c19d1205 | 22850 | N_("use -mcpu=strongarm110")}, |
e74cfd16 | 22851 | {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22852 | N_("use -mcpu=strongarm1100")}, |
e74cfd16 | 22853 | {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, |
c19d1205 | 22854 | N_("use -mcpu=strongarm1110")}, |
e74cfd16 PB |
22855 | {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, |
22856 | {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, | |
22857 | {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, | |
7ed4c4c5 | 22858 | |
c19d1205 | 22859 | /* Architecture variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22860 | {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, |
22861 | {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, | |
22862 | {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22863 | {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, | |
22864 | {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22865 | {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, | |
22866 | {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22867 | {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, | |
22868 | {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22869 | {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, | |
22870 | {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22871 | {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, | |
22872 | {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22873 | {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, | |
22874 | {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22875 | {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, | |
22876 | {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
22877 | {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, | |
7ed4c4c5 | 22878 | |
c19d1205 | 22879 | /* Floating point variants -- don't add any more to this list either. */ |
e74cfd16 PB |
22880 | {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, |
22881 | {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, | |
22882 | {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, | |
22883 | {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, | |
c19d1205 | 22884 | N_("use either -mfpu=softfpa or -mfpu=softvfp")}, |
7ed4c4c5 | 22885 | |
e74cfd16 | 22886 | {NULL, NULL, ARM_ARCH_NONE, NULL} |
c19d1205 | 22887 | }; |
7ed4c4c5 | 22888 | |
c19d1205 | 22889 | struct arm_cpu_option_table |
7ed4c4c5 | 22890 | { |
c19d1205 | 22891 | char *name; |
f3bad469 | 22892 | size_t name_len; |
e74cfd16 | 22893 | const arm_feature_set value; |
c19d1205 ZW |
22894 | /* For some CPUs we assume an FPU unless the user explicitly sets |
22895 | -mfpu=... */ | |
e74cfd16 | 22896 | const arm_feature_set default_fpu; |
ee065d83 PB |
22897 | /* The canonical name of the CPU, or NULL to use NAME converted to upper |
22898 | case. */ | |
22899 | const char *canonical_name; | |
c19d1205 | 22900 | }; |
7ed4c4c5 | 22901 | |
c19d1205 ZW |
22902 | /* This list should, at a minimum, contain all the cpu names |
22903 | recognized by GCC. */ | |
f3bad469 | 22904 | #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN } |
e74cfd16 | 22905 | static const struct arm_cpu_option_table arm_cpus[] = |
c19d1205 | 22906 | { |
f3bad469 MGD |
22907 | ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL), |
22908 | ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL), | |
22909 | ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL), | |
22910 | ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
22911 | ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL), | |
22912 | ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22913 | ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22914 | ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22915 | ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22916 | ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22917 | ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22918 | ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
22919 | ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22920 | ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
22921 | ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22922 | ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL), | |
22923 | ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22924 | ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22925 | ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22926 | ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22927 | ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
22928 | ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22929 | ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
22930 | ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
22931 | ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22932 | ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22933 | ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22934 | ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL), | |
22935 | ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
22936 | ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
22937 | ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
22938 | ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
22939 | ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
22940 | ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
22941 | ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
22942 | ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
22943 | ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
22944 | ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
22945 | ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
22946 | ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"), | |
22947 | ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
22948 | ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
22949 | ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
22950 | ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL), | |
22951 | ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
22952 | ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL), | |
c19d1205 ZW |
22953 | /* For V5 or later processors we default to using VFP; but the user |
22954 | should really set the FPU type explicitly. */ | |
f3bad469 MGD |
22955 | ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), |
22956 | ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22957 | ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
22958 | ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"), | |
22959 | ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
22960 | ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
22961 | ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"), | |
22962 | ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22963 | ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL), | |
22964 | ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"), | |
22965 | ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22966 | ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22967 | ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
22968 | ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
22969 | ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22970 | ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"), | |
22971 | ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL), | |
22972 | ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22973 | ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22974 | ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, | |
22975 | "ARM1026EJ-S"), | |
22976 | ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL), | |
22977 | ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22978 | ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22979 | ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22980 | ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22981 | ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL), | |
22982 | ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"), | |
22983 | ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL), | |
22984 | ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, | |
22985 | "ARM1136JF-S"), | |
22986 | ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL), | |
22987 | ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"), | |
22988 | ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"), | |
22989 | ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL), | |
22990 | ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL), | |
22991 | ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL), | |
22992 | ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL), | |
22993 | ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC, | |
22994 | FPU_NONE, "Cortex-A5"), | |
22995 | ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT, | |
22996 | FPU_ARCH_NEON_VFP_V4, | |
22997 | "Cortex-A7"), | |
22998 | ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC, | |
22999 | ARM_FEATURE (0, FPU_VFP_V3 | |
5287ad62 | 23000 | | FPU_NEON_EXT_V1), |
f3bad469 MGD |
23001 | "Cortex-A8"), |
23002 | ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC, | |
23003 | ARM_FEATURE (0, FPU_VFP_V3 | |
15290f0a | 23004 | | FPU_NEON_EXT_V1), |
f3bad469 MGD |
23005 | "Cortex-A9"), |
23006 | ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT, | |
23007 | FPU_ARCH_NEON_VFP_V4, | |
23008 | "Cortex-A15"), | |
23009 | ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"), | |
23010 | ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, | |
23011 | "Cortex-R4F"), | |
23012 | ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV, | |
23013 | FPU_NONE, "Cortex-R5"), | |
23014 | ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"), | |
23015 | ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"), | |
23016 | ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"), | |
23017 | ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"), | |
c19d1205 | 23018 | /* ??? XSCALE is really an architecture. */ |
f3bad469 | 23019 | ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), |
c19d1205 | 23020 | /* ??? iwmmxt is not a processor. */ |
f3bad469 MGD |
23021 | ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL), |
23022 | ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL), | |
23023 | ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), | |
c19d1205 | 23024 | /* Maverick */ |
f3bad469 MGD |
23025 | ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), |
23026 | FPU_ARCH_MAVERICK, | |
23027 | "ARM920T"), | |
23028 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } | |
c19d1205 | 23029 | }; |
f3bad469 | 23030 | #undef ARM_CPU_OPT |
7ed4c4c5 | 23031 | |
c19d1205 | 23032 | struct arm_arch_option_table |
7ed4c4c5 | 23033 | { |
c19d1205 | 23034 | char *name; |
f3bad469 | 23035 | size_t name_len; |
e74cfd16 PB |
23036 | const arm_feature_set value; |
23037 | const arm_feature_set default_fpu; | |
c19d1205 | 23038 | }; |
7ed4c4c5 | 23039 | |
c19d1205 ZW |
23040 | /* This list should, at a minimum, contain all the architecture names |
23041 | recognized by GCC. */ | |
f3bad469 | 23042 | #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF } |
e74cfd16 | 23043 | static const struct arm_arch_option_table arm_archs[] = |
c19d1205 | 23044 | { |
f3bad469 MGD |
23045 | ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA), |
23046 | ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA), | |
23047 | ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA), | |
23048 | ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
23049 | ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA), | |
23050 | ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA), | |
23051 | ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA), | |
23052 | ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA), | |
23053 | ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA), | |
23054 | ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA), | |
23055 | ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA), | |
23056 | ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP), | |
23057 | ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP), | |
23058 | ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP), | |
23059 | ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP), | |
23060 | ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP), | |
23061 | ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP), | |
23062 | ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP), | |
23063 | ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP), | |
23064 | ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP), | |
23065 | ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP), | |
23066 | ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP), | |
23067 | ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP), | |
23068 | ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP), | |
23069 | ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP), | |
23070 | ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP), | |
23071 | ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP), | |
23072 | ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP), | |
23073 | ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP), | |
c450d570 PB |
23074 | /* The official spelling of the ARMv7 profile variants is the dashed form. |
23075 | Accept the non-dashed form for compatibility with old toolchains. */ | |
f3bad469 MGD |
23076 | ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP), |
23077 | ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
23078 | ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
23079 | ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP), | |
23080 | ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP), | |
23081 | ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), | |
23082 | ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP), | |
23083 | ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP), | |
23084 | ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP), | |
23085 | ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP), | |
23086 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
c19d1205 | 23087 | }; |
f3bad469 | 23088 | #undef ARM_ARCH_OPT |
7ed4c4c5 | 23089 | |
69133863 MGD |
23090 | /* ISA extensions in the co-processor and main instruction set space. */ |
23091 | struct arm_option_extension_value_table | |
c19d1205 ZW |
23092 | { |
23093 | char *name; | |
f3bad469 | 23094 | size_t name_len; |
e74cfd16 | 23095 | const arm_feature_set value; |
69133863 | 23096 | const arm_feature_set allowed_archs; |
c19d1205 | 23097 | }; |
7ed4c4c5 | 23098 | |
69133863 MGD |
23099 | /* The following table must be in alphabetical order with a NULL last entry. |
23100 | */ | |
f3bad469 | 23101 | #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA } |
69133863 | 23102 | static const struct arm_option_extension_value_table arm_extensions[] = |
c19d1205 | 23103 | { |
f3bad469 MGD |
23104 | ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0), |
23105 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), | |
23106 | ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY), | |
23107 | ARM_EXT_OPT ("iwmmxt2", | |
23108 | ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY), | |
23109 | ARM_EXT_OPT ("maverick", | |
23110 | ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY), | |
23111 | ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0), | |
23112 | ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)), | |
23113 | ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0), | |
23114 | ARM_FEATURE (ARM_EXT_V6M, 0)), | |
23115 | ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0), | |
23116 | ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)), | |
23117 | ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | |
23118 | | ARM_EXT_DIV, 0), | |
23119 | ARM_FEATURE (ARM_EXT_V7A, 0)), | |
23120 | ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY), | |
23121 | { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE } | |
69133863 | 23122 | }; |
f3bad469 | 23123 | #undef ARM_EXT_OPT |
69133863 MGD |
23124 | |
23125 | /* ISA floating-point and Advanced SIMD extensions. */ | |
23126 | struct arm_option_fpu_value_table | |
23127 | { | |
23128 | char *name; | |
23129 | const arm_feature_set value; | |
c19d1205 | 23130 | }; |
7ed4c4c5 | 23131 | |
c19d1205 ZW |
23132 | /* This list should, at a minimum, contain all the fpu names |
23133 | recognized by GCC. */ | |
69133863 | 23134 | static const struct arm_option_fpu_value_table arm_fpus[] = |
c19d1205 ZW |
23135 | { |
23136 | {"softfpa", FPU_NONE}, | |
23137 | {"fpe", FPU_ARCH_FPE}, | |
23138 | {"fpe2", FPU_ARCH_FPE}, | |
23139 | {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ | |
23140 | {"fpa", FPU_ARCH_FPA}, | |
23141 | {"fpa10", FPU_ARCH_FPA}, | |
23142 | {"fpa11", FPU_ARCH_FPA}, | |
23143 | {"arm7500fe", FPU_ARCH_FPA}, | |
23144 | {"softvfp", FPU_ARCH_VFP}, | |
23145 | {"softvfp+vfp", FPU_ARCH_VFP_V2}, | |
23146 | {"vfp", FPU_ARCH_VFP_V2}, | |
23147 | {"vfp9", FPU_ARCH_VFP_V2}, | |
b1cc4aeb | 23148 | {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */ |
c19d1205 ZW |
23149 | {"vfp10", FPU_ARCH_VFP_V2}, |
23150 | {"vfp10-r0", FPU_ARCH_VFP_V1}, | |
23151 | {"vfpxd", FPU_ARCH_VFP_V1xD}, | |
b1cc4aeb PB |
23152 | {"vfpv2", FPU_ARCH_VFP_V2}, |
23153 | {"vfpv3", FPU_ARCH_VFP_V3}, | |
62f3b8c8 | 23154 | {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16}, |
b1cc4aeb | 23155 | {"vfpv3-d16", FPU_ARCH_VFP_V3D16}, |
62f3b8c8 PB |
23156 | {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16}, |
23157 | {"vfpv3xd", FPU_ARCH_VFP_V3xD}, | |
23158 | {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16}, | |
c19d1205 ZW |
23159 | {"arm1020t", FPU_ARCH_VFP_V1}, |
23160 | {"arm1020e", FPU_ARCH_VFP_V2}, | |
23161 | {"arm1136jfs", FPU_ARCH_VFP_V2}, | |
23162 | {"arm1136jf-s", FPU_ARCH_VFP_V2}, | |
23163 | {"maverick", FPU_ARCH_MAVERICK}, | |
5287ad62 | 23164 | {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
8e79c3df | 23165 | {"neon-fp16", FPU_ARCH_NEON_FP16}, |
62f3b8c8 PB |
23166 | {"vfpv4", FPU_ARCH_VFP_V4}, |
23167 | {"vfpv4-d16", FPU_ARCH_VFP_V4D16}, | |
ada65aa3 | 23168 | {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16}, |
62f3b8c8 | 23169 | {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4}, |
e74cfd16 PB |
23170 | {NULL, ARM_ARCH_NONE} |
23171 | }; | |
23172 | ||
23173 | struct arm_option_value_table | |
23174 | { | |
23175 | char *name; | |
23176 | long value; | |
c19d1205 | 23177 | }; |
7ed4c4c5 | 23178 | |
e74cfd16 | 23179 | static const struct arm_option_value_table arm_float_abis[] = |
c19d1205 ZW |
23180 | { |
23181 | {"hard", ARM_FLOAT_ABI_HARD}, | |
23182 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
23183 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
e74cfd16 | 23184 | {NULL, 0} |
c19d1205 | 23185 | }; |
7ed4c4c5 | 23186 | |
c19d1205 | 23187 | #ifdef OBJ_ELF |
3a4a14e9 | 23188 | /* We only know how to output GNU and ver 4/5 (AAELF) formats. */ |
e74cfd16 | 23189 | static const struct arm_option_value_table arm_eabis[] = |
c19d1205 ZW |
23190 | { |
23191 | {"gnu", EF_ARM_EABI_UNKNOWN}, | |
23192 | {"4", EF_ARM_EABI_VER4}, | |
3a4a14e9 | 23193 | {"5", EF_ARM_EABI_VER5}, |
e74cfd16 | 23194 | {NULL, 0} |
c19d1205 ZW |
23195 | }; |
23196 | #endif | |
7ed4c4c5 | 23197 | |
c19d1205 ZW |
23198 | struct arm_long_option_table |
23199 | { | |
23200 | char * option; /* Substring to match. */ | |
23201 | char * help; /* Help information. */ | |
23202 | int (* func) (char * subopt); /* Function to decode sub-option. */ | |
23203 | char * deprecated; /* If non-null, print this message. */ | |
23204 | }; | |
7ed4c4c5 | 23205 | |
c921be7d | 23206 | static bfd_boolean |
f3bad469 | 23207 | arm_parse_extension (char *str, const arm_feature_set **opt_p) |
7ed4c4c5 | 23208 | { |
21d799b5 NC |
23209 | arm_feature_set *ext_set = (arm_feature_set *) |
23210 | xmalloc (sizeof (arm_feature_set)); | |
e74cfd16 | 23211 | |
69133863 MGD |
23212 | /* We insist on extensions being specified in alphabetical order, and with |
23213 | extensions being added before being removed. We achieve this by having | |
23214 | the global ARM_EXTENSIONS table in alphabetical order, and using the | |
23215 | ADDING_VALUE variable to indicate whether we are adding an extension (1) | |
23216 | or removing it (0) and only allowing it to change in the order | |
23217 | -1 -> 1 -> 0. */ | |
23218 | const struct arm_option_extension_value_table * opt = NULL; | |
23219 | int adding_value = -1; | |
23220 | ||
e74cfd16 PB |
23221 | /* Copy the feature set, so that we can modify it. */ |
23222 | *ext_set = **opt_p; | |
23223 | *opt_p = ext_set; | |
23224 | ||
c19d1205 | 23225 | while (str != NULL && *str != 0) |
7ed4c4c5 | 23226 | { |
f3bad469 MGD |
23227 | char *ext; |
23228 | size_t len; | |
7ed4c4c5 | 23229 | |
c19d1205 ZW |
23230 | if (*str != '+') |
23231 | { | |
23232 | as_bad (_("invalid architectural extension")); | |
c921be7d | 23233 | return FALSE; |
c19d1205 | 23234 | } |
7ed4c4c5 | 23235 | |
c19d1205 ZW |
23236 | str++; |
23237 | ext = strchr (str, '+'); | |
7ed4c4c5 | 23238 | |
c19d1205 | 23239 | if (ext != NULL) |
f3bad469 | 23240 | len = ext - str; |
c19d1205 | 23241 | else |
f3bad469 | 23242 | len = strlen (str); |
7ed4c4c5 | 23243 | |
f3bad469 | 23244 | if (len >= 2 && strncmp (str, "no", 2) == 0) |
69133863 MGD |
23245 | { |
23246 | if (adding_value != 0) | |
23247 | { | |
23248 | adding_value = 0; | |
23249 | opt = arm_extensions; | |
23250 | } | |
23251 | ||
f3bad469 | 23252 | len -= 2; |
69133863 MGD |
23253 | str += 2; |
23254 | } | |
f3bad469 | 23255 | else if (len > 0) |
69133863 MGD |
23256 | { |
23257 | if (adding_value == -1) | |
23258 | { | |
23259 | adding_value = 1; | |
23260 | opt = arm_extensions; | |
23261 | } | |
23262 | else if (adding_value != 1) | |
23263 | { | |
23264 | as_bad (_("must specify extensions to add before specifying " | |
23265 | "those to remove")); | |
23266 | return FALSE; | |
23267 | } | |
23268 | } | |
23269 | ||
f3bad469 | 23270 | if (len == 0) |
c19d1205 ZW |
23271 | { |
23272 | as_bad (_("missing architectural extension")); | |
c921be7d | 23273 | return FALSE; |
c19d1205 | 23274 | } |
7ed4c4c5 | 23275 | |
69133863 MGD |
23276 | gas_assert (adding_value != -1); |
23277 | gas_assert (opt != NULL); | |
23278 | ||
23279 | /* Scan over the options table trying to find an exact match. */ | |
23280 | for (; opt->name != NULL; opt++) | |
f3bad469 | 23281 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 23282 | { |
69133863 MGD |
23283 | /* Check we can apply the extension to this architecture. */ |
23284 | if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs)) | |
23285 | { | |
23286 | as_bad (_("extension does not apply to the base architecture")); | |
23287 | return FALSE; | |
23288 | } | |
23289 | ||
23290 | /* Add or remove the extension. */ | |
23291 | if (adding_value) | |
23292 | ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); | |
23293 | else | |
23294 | ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value); | |
23295 | ||
c19d1205 ZW |
23296 | break; |
23297 | } | |
7ed4c4c5 | 23298 | |
c19d1205 ZW |
23299 | if (opt->name == NULL) |
23300 | { | |
69133863 MGD |
23301 | /* Did we fail to find an extension because it wasn't specified in |
23302 | alphabetical order, or because it does not exist? */ | |
23303 | ||
23304 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
f3bad469 | 23305 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
69133863 MGD |
23306 | break; |
23307 | ||
23308 | if (opt->name == NULL) | |
23309 | as_bad (_("unknown architectural extension `%s'"), str); | |
23310 | else | |
23311 | as_bad (_("architectural extensions must be specified in " | |
23312 | "alphabetical order")); | |
23313 | ||
c921be7d | 23314 | return FALSE; |
c19d1205 | 23315 | } |
69133863 MGD |
23316 | else |
23317 | { | |
23318 | /* We should skip the extension we've just matched the next time | |
23319 | round. */ | |
23320 | opt++; | |
23321 | } | |
7ed4c4c5 | 23322 | |
c19d1205 ZW |
23323 | str = ext; |
23324 | }; | |
7ed4c4c5 | 23325 | |
c921be7d | 23326 | return TRUE; |
c19d1205 | 23327 | } |
7ed4c4c5 | 23328 | |
c921be7d | 23329 | static bfd_boolean |
f3bad469 | 23330 | arm_parse_cpu (char *str) |
7ed4c4c5 | 23331 | { |
f3bad469 MGD |
23332 | const struct arm_cpu_option_table *opt; |
23333 | char *ext = strchr (str, '+'); | |
23334 | size_t len; | |
7ed4c4c5 | 23335 | |
c19d1205 | 23336 | if (ext != NULL) |
f3bad469 | 23337 | len = ext - str; |
7ed4c4c5 | 23338 | else |
f3bad469 | 23339 | len = strlen (str); |
7ed4c4c5 | 23340 | |
f3bad469 | 23341 | if (len == 0) |
7ed4c4c5 | 23342 | { |
c19d1205 | 23343 | as_bad (_("missing cpu name `%s'"), str); |
c921be7d | 23344 | return FALSE; |
7ed4c4c5 NC |
23345 | } |
23346 | ||
c19d1205 | 23347 | for (opt = arm_cpus; opt->name != NULL; opt++) |
f3bad469 | 23348 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 23349 | { |
e74cfd16 PB |
23350 | mcpu_cpu_opt = &opt->value; |
23351 | mcpu_fpu_opt = &opt->default_fpu; | |
ee065d83 | 23352 | if (opt->canonical_name) |
5f4273c7 | 23353 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
23354 | else |
23355 | { | |
f3bad469 | 23356 | size_t i; |
c921be7d | 23357 | |
f3bad469 | 23358 | for (i = 0; i < len; i++) |
ee065d83 PB |
23359 | selected_cpu_name[i] = TOUPPER (opt->name[i]); |
23360 | selected_cpu_name[i] = 0; | |
23361 | } | |
7ed4c4c5 | 23362 | |
c19d1205 ZW |
23363 | if (ext != NULL) |
23364 | return arm_parse_extension (ext, &mcpu_cpu_opt); | |
7ed4c4c5 | 23365 | |
c921be7d | 23366 | return TRUE; |
c19d1205 | 23367 | } |
7ed4c4c5 | 23368 | |
c19d1205 | 23369 | as_bad (_("unknown cpu `%s'"), str); |
c921be7d | 23370 | return FALSE; |
7ed4c4c5 NC |
23371 | } |
23372 | ||
c921be7d | 23373 | static bfd_boolean |
f3bad469 | 23374 | arm_parse_arch (char *str) |
7ed4c4c5 | 23375 | { |
e74cfd16 | 23376 | const struct arm_arch_option_table *opt; |
c19d1205 | 23377 | char *ext = strchr (str, '+'); |
f3bad469 | 23378 | size_t len; |
7ed4c4c5 | 23379 | |
c19d1205 | 23380 | if (ext != NULL) |
f3bad469 | 23381 | len = ext - str; |
7ed4c4c5 | 23382 | else |
f3bad469 | 23383 | len = strlen (str); |
7ed4c4c5 | 23384 | |
f3bad469 | 23385 | if (len == 0) |
7ed4c4c5 | 23386 | { |
c19d1205 | 23387 | as_bad (_("missing architecture name `%s'"), str); |
c921be7d | 23388 | return FALSE; |
7ed4c4c5 NC |
23389 | } |
23390 | ||
c19d1205 | 23391 | for (opt = arm_archs; opt->name != NULL; opt++) |
f3bad469 | 23392 | if (opt->name_len == len && strncmp (opt->name, str, len) == 0) |
c19d1205 | 23393 | { |
e74cfd16 PB |
23394 | march_cpu_opt = &opt->value; |
23395 | march_fpu_opt = &opt->default_fpu; | |
5f4273c7 | 23396 | strcpy (selected_cpu_name, opt->name); |
7ed4c4c5 | 23397 | |
c19d1205 ZW |
23398 | if (ext != NULL) |
23399 | return arm_parse_extension (ext, &march_cpu_opt); | |
7ed4c4c5 | 23400 | |
c921be7d | 23401 | return TRUE; |
c19d1205 ZW |
23402 | } |
23403 | ||
23404 | as_bad (_("unknown architecture `%s'\n"), str); | |
c921be7d | 23405 | return FALSE; |
7ed4c4c5 | 23406 | } |
eb043451 | 23407 | |
c921be7d | 23408 | static bfd_boolean |
c19d1205 ZW |
23409 | arm_parse_fpu (char * str) |
23410 | { | |
69133863 | 23411 | const struct arm_option_fpu_value_table * opt; |
b99bd4ef | 23412 | |
c19d1205 ZW |
23413 | for (opt = arm_fpus; opt->name != NULL; opt++) |
23414 | if (streq (opt->name, str)) | |
23415 | { | |
e74cfd16 | 23416 | mfpu_opt = &opt->value; |
c921be7d | 23417 | return TRUE; |
c19d1205 | 23418 | } |
b99bd4ef | 23419 | |
c19d1205 | 23420 | as_bad (_("unknown floating point format `%s'\n"), str); |
c921be7d | 23421 | return FALSE; |
c19d1205 ZW |
23422 | } |
23423 | ||
c921be7d | 23424 | static bfd_boolean |
c19d1205 | 23425 | arm_parse_float_abi (char * str) |
b99bd4ef | 23426 | { |
e74cfd16 | 23427 | const struct arm_option_value_table * opt; |
b99bd4ef | 23428 | |
c19d1205 ZW |
23429 | for (opt = arm_float_abis; opt->name != NULL; opt++) |
23430 | if (streq (opt->name, str)) | |
23431 | { | |
23432 | mfloat_abi_opt = opt->value; | |
c921be7d | 23433 | return TRUE; |
c19d1205 | 23434 | } |
cc8a6dd0 | 23435 | |
c19d1205 | 23436 | as_bad (_("unknown floating point abi `%s'\n"), str); |
c921be7d | 23437 | return FALSE; |
c19d1205 | 23438 | } |
b99bd4ef | 23439 | |
c19d1205 | 23440 | #ifdef OBJ_ELF |
c921be7d | 23441 | static bfd_boolean |
c19d1205 ZW |
23442 | arm_parse_eabi (char * str) |
23443 | { | |
e74cfd16 | 23444 | const struct arm_option_value_table *opt; |
cc8a6dd0 | 23445 | |
c19d1205 ZW |
23446 | for (opt = arm_eabis; opt->name != NULL; opt++) |
23447 | if (streq (opt->name, str)) | |
23448 | { | |
23449 | meabi_flags = opt->value; | |
c921be7d | 23450 | return TRUE; |
c19d1205 ZW |
23451 | } |
23452 | as_bad (_("unknown EABI `%s'\n"), str); | |
c921be7d | 23453 | return FALSE; |
c19d1205 ZW |
23454 | } |
23455 | #endif | |
cc8a6dd0 | 23456 | |
c921be7d | 23457 | static bfd_boolean |
e07e6e58 NC |
23458 | arm_parse_it_mode (char * str) |
23459 | { | |
c921be7d | 23460 | bfd_boolean ret = TRUE; |
e07e6e58 NC |
23461 | |
23462 | if (streq ("arm", str)) | |
23463 | implicit_it_mode = IMPLICIT_IT_MODE_ARM; | |
23464 | else if (streq ("thumb", str)) | |
23465 | implicit_it_mode = IMPLICIT_IT_MODE_THUMB; | |
23466 | else if (streq ("always", str)) | |
23467 | implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS; | |
23468 | else if (streq ("never", str)) | |
23469 | implicit_it_mode = IMPLICIT_IT_MODE_NEVER; | |
23470 | else | |
23471 | { | |
23472 | as_bad (_("unknown implicit IT mode `%s', should be "\ | |
23473 | "arm, thumb, always, or never."), str); | |
c921be7d | 23474 | ret = FALSE; |
e07e6e58 NC |
23475 | } |
23476 | ||
23477 | return ret; | |
23478 | } | |
23479 | ||
c19d1205 ZW |
23480 | struct arm_long_option_table arm_long_opts[] = |
23481 | { | |
23482 | {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), | |
23483 | arm_parse_cpu, NULL}, | |
23484 | {"march=", N_("<arch name>\t assemble for architecture <arch name>"), | |
23485 | arm_parse_arch, NULL}, | |
23486 | {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), | |
23487 | arm_parse_fpu, NULL}, | |
23488 | {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), | |
23489 | arm_parse_float_abi, NULL}, | |
23490 | #ifdef OBJ_ELF | |
7fac0536 | 23491 | {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"), |
c19d1205 ZW |
23492 | arm_parse_eabi, NULL}, |
23493 | #endif | |
e07e6e58 NC |
23494 | {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"), |
23495 | arm_parse_it_mode, NULL}, | |
c19d1205 ZW |
23496 | {NULL, NULL, 0, NULL} |
23497 | }; | |
cc8a6dd0 | 23498 | |
c19d1205 ZW |
23499 | int |
23500 | md_parse_option (int c, char * arg) | |
23501 | { | |
23502 | struct arm_option_table *opt; | |
e74cfd16 | 23503 | const struct arm_legacy_option_table *fopt; |
c19d1205 | 23504 | struct arm_long_option_table *lopt; |
b99bd4ef | 23505 | |
c19d1205 | 23506 | switch (c) |
b99bd4ef | 23507 | { |
c19d1205 ZW |
23508 | #ifdef OPTION_EB |
23509 | case OPTION_EB: | |
23510 | target_big_endian = 1; | |
23511 | break; | |
23512 | #endif | |
cc8a6dd0 | 23513 | |
c19d1205 ZW |
23514 | #ifdef OPTION_EL |
23515 | case OPTION_EL: | |
23516 | target_big_endian = 0; | |
23517 | break; | |
23518 | #endif | |
b99bd4ef | 23519 | |
845b51d6 PB |
23520 | case OPTION_FIX_V4BX: |
23521 | fix_v4bx = TRUE; | |
23522 | break; | |
23523 | ||
c19d1205 ZW |
23524 | case 'a': |
23525 | /* Listing option. Just ignore these, we don't support additional | |
23526 | ones. */ | |
23527 | return 0; | |
b99bd4ef | 23528 | |
c19d1205 ZW |
23529 | default: |
23530 | for (opt = arm_opts; opt->option != NULL; opt++) | |
23531 | { | |
23532 | if (c == opt->option[0] | |
23533 | && ((arg == NULL && opt->option[1] == 0) | |
23534 | || streq (arg, opt->option + 1))) | |
23535 | { | |
c19d1205 | 23536 | /* If the option is deprecated, tell the user. */ |
278df34e | 23537 | if (warn_on_deprecated && opt->deprecated != NULL) |
c19d1205 ZW |
23538 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
23539 | arg ? arg : "", _(opt->deprecated)); | |
b99bd4ef | 23540 | |
c19d1205 ZW |
23541 | if (opt->var != NULL) |
23542 | *opt->var = opt->value; | |
cc8a6dd0 | 23543 | |
c19d1205 ZW |
23544 | return 1; |
23545 | } | |
23546 | } | |
b99bd4ef | 23547 | |
e74cfd16 PB |
23548 | for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) |
23549 | { | |
23550 | if (c == fopt->option[0] | |
23551 | && ((arg == NULL && fopt->option[1] == 0) | |
23552 | || streq (arg, fopt->option + 1))) | |
23553 | { | |
e74cfd16 | 23554 | /* If the option is deprecated, tell the user. */ |
278df34e | 23555 | if (warn_on_deprecated && fopt->deprecated != NULL) |
e74cfd16 PB |
23556 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, |
23557 | arg ? arg : "", _(fopt->deprecated)); | |
e74cfd16 PB |
23558 | |
23559 | if (fopt->var != NULL) | |
23560 | *fopt->var = &fopt->value; | |
23561 | ||
23562 | return 1; | |
23563 | } | |
23564 | } | |
23565 | ||
c19d1205 ZW |
23566 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
23567 | { | |
23568 | /* These options are expected to have an argument. */ | |
23569 | if (c == lopt->option[0] | |
23570 | && arg != NULL | |
23571 | && strncmp (arg, lopt->option + 1, | |
23572 | strlen (lopt->option + 1)) == 0) | |
23573 | { | |
c19d1205 | 23574 | /* If the option is deprecated, tell the user. */ |
278df34e | 23575 | if (warn_on_deprecated && lopt->deprecated != NULL) |
c19d1205 ZW |
23576 | as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, |
23577 | _(lopt->deprecated)); | |
b99bd4ef | 23578 | |
c19d1205 ZW |
23579 | /* Call the sup-option parser. */ |
23580 | return lopt->func (arg + strlen (lopt->option) - 1); | |
23581 | } | |
23582 | } | |
a737bd4d | 23583 | |
c19d1205 ZW |
23584 | return 0; |
23585 | } | |
a394c00f | 23586 | |
c19d1205 ZW |
23587 | return 1; |
23588 | } | |
a394c00f | 23589 | |
c19d1205 ZW |
23590 | void |
23591 | md_show_usage (FILE * fp) | |
a394c00f | 23592 | { |
c19d1205 ZW |
23593 | struct arm_option_table *opt; |
23594 | struct arm_long_option_table *lopt; | |
a394c00f | 23595 | |
c19d1205 | 23596 | fprintf (fp, _(" ARM-specific assembler options:\n")); |
a394c00f | 23597 | |
c19d1205 ZW |
23598 | for (opt = arm_opts; opt->option != NULL; opt++) |
23599 | if (opt->help != NULL) | |
23600 | fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); | |
a394c00f | 23601 | |
c19d1205 ZW |
23602 | for (lopt = arm_long_opts; lopt->option != NULL; lopt++) |
23603 | if (lopt->help != NULL) | |
23604 | fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); | |
a394c00f | 23605 | |
c19d1205 ZW |
23606 | #ifdef OPTION_EB |
23607 | fprintf (fp, _("\ | |
23608 | -EB assemble code for a big-endian cpu\n")); | |
a394c00f NC |
23609 | #endif |
23610 | ||
c19d1205 ZW |
23611 | #ifdef OPTION_EL |
23612 | fprintf (fp, _("\ | |
23613 | -EL assemble code for a little-endian cpu\n")); | |
a737bd4d | 23614 | #endif |
845b51d6 PB |
23615 | |
23616 | fprintf (fp, _("\ | |
23617 | --fix-v4bx Allow BX in ARMv4 code\n")); | |
c19d1205 | 23618 | } |
ee065d83 PB |
23619 | |
23620 | ||
23621 | #ifdef OBJ_ELF | |
62b3e311 PB |
23622 | typedef struct |
23623 | { | |
23624 | int val; | |
23625 | arm_feature_set flags; | |
23626 | } cpu_arch_ver_table; | |
23627 | ||
23628 | /* Mapping from CPU features to EABI CPU arch values. Table must be sorted | |
23629 | least features first. */ | |
23630 | static const cpu_arch_ver_table cpu_arch_ver[] = | |
23631 | { | |
23632 | {1, ARM_ARCH_V4}, | |
23633 | {2, ARM_ARCH_V4T}, | |
23634 | {3, ARM_ARCH_V5}, | |
ee3c0378 | 23635 | {3, ARM_ARCH_V5T}, |
62b3e311 PB |
23636 | {4, ARM_ARCH_V5TE}, |
23637 | {5, ARM_ARCH_V5TEJ}, | |
23638 | {6, ARM_ARCH_V6}, | |
7e806470 | 23639 | {9, ARM_ARCH_V6K}, |
f4c65163 | 23640 | {7, ARM_ARCH_V6Z}, |
91e22acd | 23641 | {11, ARM_ARCH_V6M}, |
b2a5fbdc | 23642 | {12, ARM_ARCH_V6SM}, |
7e806470 | 23643 | {8, ARM_ARCH_V6T2}, |
62b3e311 PB |
23644 | {10, ARM_ARCH_V7A}, |
23645 | {10, ARM_ARCH_V7R}, | |
23646 | {10, ARM_ARCH_V7M}, | |
23647 | {0, ARM_ARCH_NONE} | |
23648 | }; | |
23649 | ||
ee3c0378 AS |
23650 | /* Set an attribute if it has not already been set by the user. */ |
23651 | static void | |
23652 | aeabi_set_attribute_int (int tag, int value) | |
23653 | { | |
23654 | if (tag < 1 | |
23655 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
23656 | || !attributes_set_explicitly[tag]) | |
23657 | bfd_elf_add_proc_attr_int (stdoutput, tag, value); | |
23658 | } | |
23659 | ||
23660 | static void | |
23661 | aeabi_set_attribute_string (int tag, const char *value) | |
23662 | { | |
23663 | if (tag < 1 | |
23664 | || tag >= NUM_KNOWN_OBJ_ATTRIBUTES | |
23665 | || !attributes_set_explicitly[tag]) | |
23666 | bfd_elf_add_proc_attr_string (stdoutput, tag, value); | |
23667 | } | |
23668 | ||
ee065d83 PB |
23669 | /* Set the public EABI object attributes. */ |
23670 | static void | |
23671 | aeabi_set_public_attributes (void) | |
23672 | { | |
23673 | int arch; | |
90ec0d68 | 23674 | int virt_sec = 0; |
e74cfd16 | 23675 | arm_feature_set flags; |
62b3e311 PB |
23676 | arm_feature_set tmp; |
23677 | const cpu_arch_ver_table *p; | |
ee065d83 PB |
23678 | |
23679 | /* Choose the architecture based on the capabilities of the requested cpu | |
23680 | (if any) and/or the instructions actually used. */ | |
e74cfd16 PB |
23681 | ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); |
23682 | ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); | |
23683 | ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); | |
ddd7f988 RE |
23684 | |
23685 | if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)) | |
23686 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1); | |
23687 | ||
23688 | if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any)) | |
23689 | ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t); | |
23690 | ||
23691 | /* Allow the user to override the reported architecture. */ | |
7a1d4c38 PB |
23692 | if (object_arch) |
23693 | { | |
23694 | ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); | |
23695 | ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); | |
23696 | } | |
23697 | ||
251665fc MGD |
23698 | /* We need to make sure that the attributes do not identify us as v6S-M |
23699 | when the only v6S-M feature in use is the Operating System Extensions. */ | |
23700 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os)) | |
23701 | if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only)) | |
23702 | ARM_CLEAR_FEATURE (flags, flags, arm_ext_os); | |
23703 | ||
62b3e311 PB |
23704 | tmp = flags; |
23705 | arch = 0; | |
23706 | for (p = cpu_arch_ver; p->val; p++) | |
23707 | { | |
23708 | if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) | |
23709 | { | |
23710 | arch = p->val; | |
23711 | ARM_CLEAR_FEATURE (tmp, tmp, p->flags); | |
23712 | } | |
23713 | } | |
ee065d83 | 23714 | |
9e3c6df6 PB |
23715 | /* The table lookup above finds the last architecture to contribute |
23716 | a new feature. Unfortunately, Tag13 is a subset of the union of | |
23717 | v6T2 and v7-M, so it is never seen as contributing a new feature. | |
23718 | We can not search for the last entry which is entirely used, | |
23719 | because if no CPU is specified we build up only those flags | |
23720 | actually used. Perhaps we should separate out the specified | |
23721 | and implicit cases. Avoid taking this path for -march=all by | |
23722 | checking for contradictory v7-A / v7-M features. */ | |
23723 | if (arch == 10 | |
23724 | && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a) | |
23725 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m) | |
23726 | && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) | |
23727 | arch = 13; | |
23728 | ||
ee065d83 PB |
23729 | /* Tag_CPU_name. */ |
23730 | if (selected_cpu_name[0]) | |
23731 | { | |
91d6fa6a | 23732 | char *q; |
ee065d83 | 23733 | |
91d6fa6a NC |
23734 | q = selected_cpu_name; |
23735 | if (strncmp (q, "armv", 4) == 0) | |
ee065d83 PB |
23736 | { |
23737 | int i; | |
5f4273c7 | 23738 | |
91d6fa6a NC |
23739 | q += 4; |
23740 | for (i = 0; q[i]; i++) | |
23741 | q[i] = TOUPPER (q[i]); | |
ee065d83 | 23742 | } |
91d6fa6a | 23743 | aeabi_set_attribute_string (Tag_CPU_name, q); |
ee065d83 | 23744 | } |
62f3b8c8 | 23745 | |
ee065d83 | 23746 | /* Tag_CPU_arch. */ |
ee3c0378 | 23747 | aeabi_set_attribute_int (Tag_CPU_arch, arch); |
62f3b8c8 | 23748 | |
62b3e311 PB |
23749 | /* Tag_CPU_arch_profile. */ |
23750 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) | |
ee3c0378 | 23751 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A'); |
62b3e311 | 23752 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) |
ee3c0378 | 23753 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R'); |
7e806470 | 23754 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m)) |
ee3c0378 | 23755 | aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M'); |
62f3b8c8 | 23756 | |
ee065d83 | 23757 | /* Tag_ARM_ISA_use. */ |
ee3c0378 AS |
23758 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1) |
23759 | || arch == 0) | |
23760 | aeabi_set_attribute_int (Tag_ARM_ISA_use, 1); | |
62f3b8c8 | 23761 | |
ee065d83 | 23762 | /* Tag_THUMB_ISA_use. */ |
ee3c0378 AS |
23763 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t) |
23764 | || arch == 0) | |
23765 | aeabi_set_attribute_int (Tag_THUMB_ISA_use, | |
23766 | ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1); | |
62f3b8c8 | 23767 | |
ee065d83 | 23768 | /* Tag_VFP_arch. */ |
62f3b8c8 PB |
23769 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma)) |
23770 | aeabi_set_attribute_int (Tag_VFP_arch, | |
23771 | ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32) | |
23772 | ? 5 : 6); | |
23773 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)) | |
ee3c0378 | 23774 | aeabi_set_attribute_int (Tag_VFP_arch, 3); |
ada65aa3 | 23775 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd)) |
ee3c0378 AS |
23776 | aeabi_set_attribute_int (Tag_VFP_arch, 4); |
23777 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2)) | |
23778 | aeabi_set_attribute_int (Tag_VFP_arch, 2); | |
23779 | else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1) | |
23780 | || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)) | |
23781 | aeabi_set_attribute_int (Tag_VFP_arch, 1); | |
62f3b8c8 | 23782 | |
4547cb56 NC |
23783 | /* Tag_ABI_HardFP_use. */ |
23784 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd) | |
23785 | && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)) | |
23786 | aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1); | |
23787 | ||
ee065d83 | 23788 | /* Tag_WMMX_arch. */ |
ee3c0378 AS |
23789 | if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2)) |
23790 | aeabi_set_attribute_int (Tag_WMMX_arch, 2); | |
23791 | else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt)) | |
23792 | aeabi_set_attribute_int (Tag_WMMX_arch, 1); | |
62f3b8c8 | 23793 | |
ee3c0378 | 23794 | /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */ |
8e79c3df | 23795 | if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) |
62f3b8c8 PB |
23796 | aeabi_set_attribute_int |
23797 | (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma) | |
23798 | ? 2 : 1)); | |
23799 | ||
ee3c0378 | 23800 | /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */ |
62f3b8c8 | 23801 | if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16)) |
ee3c0378 | 23802 | aeabi_set_attribute_int (Tag_VFP_HP_extension, 1); |
4547cb56 NC |
23803 | |
23804 | /* Tag_DIV_use. */ | |
eea54501 MGD |
23805 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)) |
23806 | aeabi_set_attribute_int (Tag_DIV_use, 2); | |
23807 | else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div)) | |
4547cb56 | 23808 | aeabi_set_attribute_int (Tag_DIV_use, 0); |
4547cb56 NC |
23809 | else |
23810 | aeabi_set_attribute_int (Tag_DIV_use, 1); | |
60e5ef9f MGD |
23811 | |
23812 | /* Tag_MP_extension_use. */ | |
23813 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp)) | |
23814 | aeabi_set_attribute_int (Tag_MPextension_use, 1); | |
f4c65163 MGD |
23815 | |
23816 | /* Tag Virtualization_use. */ | |
23817 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec)) | |
90ec0d68 MGD |
23818 | virt_sec |= 1; |
23819 | if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt)) | |
23820 | virt_sec |= 2; | |
23821 | if (virt_sec != 0) | |
23822 | aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec); | |
ee065d83 PB |
23823 | } |
23824 | ||
104d59d1 | 23825 | /* Add the default contents for the .ARM.attributes section. */ |
ee065d83 PB |
23826 | void |
23827 | arm_md_end (void) | |
23828 | { | |
ee065d83 PB |
23829 | if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) |
23830 | return; | |
23831 | ||
23832 | aeabi_set_public_attributes (); | |
ee065d83 | 23833 | } |
8463be01 | 23834 | #endif /* OBJ_ELF */ |
ee065d83 PB |
23835 | |
23836 | ||
23837 | /* Parse a .cpu directive. */ | |
23838 | ||
23839 | static void | |
23840 | s_arm_cpu (int ignored ATTRIBUTE_UNUSED) | |
23841 | { | |
e74cfd16 | 23842 | const struct arm_cpu_option_table *opt; |
ee065d83 PB |
23843 | char *name; |
23844 | char saved_char; | |
23845 | ||
23846 | name = input_line_pointer; | |
5f4273c7 | 23847 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23848 | input_line_pointer++; |
23849 | saved_char = *input_line_pointer; | |
23850 | *input_line_pointer = 0; | |
23851 | ||
23852 | /* Skip the first "all" entry. */ | |
23853 | for (opt = arm_cpus + 1; opt->name != NULL; opt++) | |
23854 | if (streq (opt->name, name)) | |
23855 | { | |
e74cfd16 PB |
23856 | mcpu_cpu_opt = &opt->value; |
23857 | selected_cpu = opt->value; | |
ee065d83 | 23858 | if (opt->canonical_name) |
5f4273c7 | 23859 | strcpy (selected_cpu_name, opt->canonical_name); |
ee065d83 PB |
23860 | else |
23861 | { | |
23862 | int i; | |
23863 | for (i = 0; opt->name[i]; i++) | |
23864 | selected_cpu_name[i] = TOUPPER (opt->name[i]); | |
f3bad469 | 23865 | |
ee065d83 PB |
23866 | selected_cpu_name[i] = 0; |
23867 | } | |
e74cfd16 | 23868 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
23869 | *input_line_pointer = saved_char; |
23870 | demand_empty_rest_of_line (); | |
23871 | return; | |
23872 | } | |
23873 | as_bad (_("unknown cpu `%s'"), name); | |
23874 | *input_line_pointer = saved_char; | |
23875 | ignore_rest_of_line (); | |
23876 | } | |
23877 | ||
23878 | ||
23879 | /* Parse a .arch directive. */ | |
23880 | ||
23881 | static void | |
23882 | s_arm_arch (int ignored ATTRIBUTE_UNUSED) | |
23883 | { | |
e74cfd16 | 23884 | const struct arm_arch_option_table *opt; |
ee065d83 PB |
23885 | char saved_char; |
23886 | char *name; | |
23887 | ||
23888 | name = input_line_pointer; | |
5f4273c7 | 23889 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
23890 | input_line_pointer++; |
23891 | saved_char = *input_line_pointer; | |
23892 | *input_line_pointer = 0; | |
23893 | ||
23894 | /* Skip the first "all" entry. */ | |
23895 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
23896 | if (streq (opt->name, name)) | |
23897 | { | |
e74cfd16 PB |
23898 | mcpu_cpu_opt = &opt->value; |
23899 | selected_cpu = opt->value; | |
5f4273c7 | 23900 | strcpy (selected_cpu_name, opt->name); |
e74cfd16 | 23901 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); |
ee065d83 PB |
23902 | *input_line_pointer = saved_char; |
23903 | demand_empty_rest_of_line (); | |
23904 | return; | |
23905 | } | |
23906 | ||
23907 | as_bad (_("unknown architecture `%s'\n"), name); | |
23908 | *input_line_pointer = saved_char; | |
23909 | ignore_rest_of_line (); | |
23910 | } | |
23911 | ||
23912 | ||
7a1d4c38 PB |
23913 | /* Parse a .object_arch directive. */ |
23914 | ||
23915 | static void | |
23916 | s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) | |
23917 | { | |
23918 | const struct arm_arch_option_table *opt; | |
23919 | char saved_char; | |
23920 | char *name; | |
23921 | ||
23922 | name = input_line_pointer; | |
5f4273c7 | 23923 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
7a1d4c38 PB |
23924 | input_line_pointer++; |
23925 | saved_char = *input_line_pointer; | |
23926 | *input_line_pointer = 0; | |
23927 | ||
23928 | /* Skip the first "all" entry. */ | |
23929 | for (opt = arm_archs + 1; opt->name != NULL; opt++) | |
23930 | if (streq (opt->name, name)) | |
23931 | { | |
23932 | object_arch = &opt->value; | |
23933 | *input_line_pointer = saved_char; | |
23934 | demand_empty_rest_of_line (); | |
23935 | return; | |
23936 | } | |
23937 | ||
23938 | as_bad (_("unknown architecture `%s'\n"), name); | |
23939 | *input_line_pointer = saved_char; | |
23940 | ignore_rest_of_line (); | |
23941 | } | |
23942 | ||
69133863 MGD |
23943 | /* Parse a .arch_extension directive. */ |
23944 | ||
23945 | static void | |
23946 | s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) | |
23947 | { | |
23948 | const struct arm_option_extension_value_table *opt; | |
23949 | char saved_char; | |
23950 | char *name; | |
23951 | int adding_value = 1; | |
23952 | ||
23953 | name = input_line_pointer; | |
23954 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) | |
23955 | input_line_pointer++; | |
23956 | saved_char = *input_line_pointer; | |
23957 | *input_line_pointer = 0; | |
23958 | ||
23959 | if (strlen (name) >= 2 | |
23960 | && strncmp (name, "no", 2) == 0) | |
23961 | { | |
23962 | adding_value = 0; | |
23963 | name += 2; | |
23964 | } | |
23965 | ||
23966 | for (opt = arm_extensions; opt->name != NULL; opt++) | |
23967 | if (streq (opt->name, name)) | |
23968 | { | |
23969 | if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs)) | |
23970 | { | |
23971 | as_bad (_("architectural extension `%s' is not allowed for the " | |
23972 | "current base architecture"), name); | |
23973 | break; | |
23974 | } | |
23975 | ||
23976 | if (adding_value) | |
23977 | ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value); | |
23978 | else | |
23979 | ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value); | |
23980 | ||
23981 | mcpu_cpu_opt = &selected_cpu; | |
23982 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
23983 | *input_line_pointer = saved_char; | |
23984 | demand_empty_rest_of_line (); | |
23985 | return; | |
23986 | } | |
23987 | ||
23988 | if (opt->name == NULL) | |
23989 | as_bad (_("unknown architecture `%s'\n"), name); | |
23990 | ||
23991 | *input_line_pointer = saved_char; | |
23992 | ignore_rest_of_line (); | |
23993 | } | |
23994 | ||
ee065d83 PB |
23995 | /* Parse a .fpu directive. */ |
23996 | ||
23997 | static void | |
23998 | s_arm_fpu (int ignored ATTRIBUTE_UNUSED) | |
23999 | { | |
69133863 | 24000 | const struct arm_option_fpu_value_table *opt; |
ee065d83 PB |
24001 | char saved_char; |
24002 | char *name; | |
24003 | ||
24004 | name = input_line_pointer; | |
5f4273c7 | 24005 | while (*input_line_pointer && !ISSPACE (*input_line_pointer)) |
ee065d83 PB |
24006 | input_line_pointer++; |
24007 | saved_char = *input_line_pointer; | |
24008 | *input_line_pointer = 0; | |
5f4273c7 | 24009 | |
ee065d83 PB |
24010 | for (opt = arm_fpus; opt->name != NULL; opt++) |
24011 | if (streq (opt->name, name)) | |
24012 | { | |
e74cfd16 PB |
24013 | mfpu_opt = &opt->value; |
24014 | ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); | |
ee065d83 PB |
24015 | *input_line_pointer = saved_char; |
24016 | demand_empty_rest_of_line (); | |
24017 | return; | |
24018 | } | |
24019 | ||
24020 | as_bad (_("unknown floating point format `%s'\n"), name); | |
24021 | *input_line_pointer = saved_char; | |
24022 | ignore_rest_of_line (); | |
24023 | } | |
ee065d83 | 24024 | |
794ba86a | 24025 | /* Copy symbol information. */ |
f31fef98 | 24026 | |
794ba86a DJ |
24027 | void |
24028 | arm_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
24029 | { | |
24030 | ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); | |
24031 | } | |
e04befd0 | 24032 | |
f31fef98 | 24033 | #ifdef OBJ_ELF |
e04befd0 AS |
24034 | /* Given a symbolic attribute NAME, return the proper integer value. |
24035 | Returns -1 if the attribute is not known. */ | |
f31fef98 | 24036 | |
e04befd0 AS |
24037 | int |
24038 | arm_convert_symbolic_attribute (const char *name) | |
24039 | { | |
f31fef98 NC |
24040 | static const struct |
24041 | { | |
24042 | const char * name; | |
24043 | const int tag; | |
24044 | } | |
24045 | attribute_table[] = | |
24046 | { | |
24047 | /* When you modify this table you should | |
24048 | also modify the list in doc/c-arm.texi. */ | |
e04befd0 | 24049 | #define T(tag) {#tag, tag} |
f31fef98 NC |
24050 | T (Tag_CPU_raw_name), |
24051 | T (Tag_CPU_name), | |
24052 | T (Tag_CPU_arch), | |
24053 | T (Tag_CPU_arch_profile), | |
24054 | T (Tag_ARM_ISA_use), | |
24055 | T (Tag_THUMB_ISA_use), | |
75375b3e | 24056 | T (Tag_FP_arch), |
f31fef98 NC |
24057 | T (Tag_VFP_arch), |
24058 | T (Tag_WMMX_arch), | |
24059 | T (Tag_Advanced_SIMD_arch), | |
24060 | T (Tag_PCS_config), | |
24061 | T (Tag_ABI_PCS_R9_use), | |
24062 | T (Tag_ABI_PCS_RW_data), | |
24063 | T (Tag_ABI_PCS_RO_data), | |
24064 | T (Tag_ABI_PCS_GOT_use), | |
24065 | T (Tag_ABI_PCS_wchar_t), | |
24066 | T (Tag_ABI_FP_rounding), | |
24067 | T (Tag_ABI_FP_denormal), | |
24068 | T (Tag_ABI_FP_exceptions), | |
24069 | T (Tag_ABI_FP_user_exceptions), | |
24070 | T (Tag_ABI_FP_number_model), | |
75375b3e | 24071 | T (Tag_ABI_align_needed), |
f31fef98 | 24072 | T (Tag_ABI_align8_needed), |
75375b3e | 24073 | T (Tag_ABI_align_preserved), |
f31fef98 NC |
24074 | T (Tag_ABI_align8_preserved), |
24075 | T (Tag_ABI_enum_size), | |
24076 | T (Tag_ABI_HardFP_use), | |
24077 | T (Tag_ABI_VFP_args), | |
24078 | T (Tag_ABI_WMMX_args), | |
24079 | T (Tag_ABI_optimization_goals), | |
24080 | T (Tag_ABI_FP_optimization_goals), | |
24081 | T (Tag_compatibility), | |
24082 | T (Tag_CPU_unaligned_access), | |
75375b3e | 24083 | T (Tag_FP_HP_extension), |
f31fef98 NC |
24084 | T (Tag_VFP_HP_extension), |
24085 | T (Tag_ABI_FP_16bit_format), | |
cd21e546 MGD |
24086 | T (Tag_MPextension_use), |
24087 | T (Tag_DIV_use), | |
f31fef98 NC |
24088 | T (Tag_nodefaults), |
24089 | T (Tag_also_compatible_with), | |
24090 | T (Tag_conformance), | |
24091 | T (Tag_T2EE_use), | |
24092 | T (Tag_Virtualization_use), | |
cd21e546 | 24093 | /* We deliberately do not include Tag_MPextension_use_legacy. */ |
e04befd0 | 24094 | #undef T |
f31fef98 | 24095 | }; |
e04befd0 AS |
24096 | unsigned int i; |
24097 | ||
24098 | if (name == NULL) | |
24099 | return -1; | |
24100 | ||
f31fef98 | 24101 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
c921be7d | 24102 | if (streq (name, attribute_table[i].name)) |
e04befd0 AS |
24103 | return attribute_table[i].tag; |
24104 | ||
24105 | return -1; | |
24106 | } | |
267bf995 RR |
24107 | |
24108 | ||
24109 | /* Apply sym value for relocations only in the case that | |
24110 | they are for local symbols and you have the respective | |
24111 | architectural feature for blx and simple switches. */ | |
24112 | int | |
24113 | arm_apply_sym_value (struct fix * fixP) | |
24114 | { | |
24115 | if (fixP->fx_addsy | |
24116 | && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t) | |
34e77a92 | 24117 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
267bf995 RR |
24118 | { |
24119 | switch (fixP->fx_r_type) | |
24120 | { | |
24121 | case BFD_RELOC_ARM_PCREL_BLX: | |
24122 | case BFD_RELOC_THUMB_PCREL_BRANCH23: | |
24123 | if (ARM_IS_FUNC (fixP->fx_addsy)) | |
24124 | return 1; | |
24125 | break; | |
24126 | ||
24127 | case BFD_RELOC_ARM_PCREL_CALL: | |
24128 | case BFD_RELOC_THUMB_PCREL_BLX: | |
24129 | if (THUMB_IS_FUNC (fixP->fx_addsy)) | |
24130 | return 1; | |
24131 | break; | |
24132 | ||
24133 | default: | |
24134 | break; | |
24135 | } | |
24136 | ||
24137 | } | |
24138 | return 0; | |
24139 | } | |
f31fef98 | 24140 | #endif /* OBJ_ELF */ |