]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - opcodes/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gdb/testsuite: check mmap ret val against MAP_FAILED
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3d205eb4
PB		 12020-05-19 Peter Bergner <bergner@linux.ibm.com>
2
3 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
4 WC values on POWER10 sync, dcbf and wait instructions.
5 (insert_pl, extract_pl): New functions.
6 (L2OPT, LS, WC): Use insert_ls and extract_ls.
7 (LS3): New , 3-bit L for sync.
8 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
9 (SC2, PL): New, 2-bit SC and PL for sync and wait.
10 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
11 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
12 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
13 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
14 <wait>: Enable PL operand on POWER10.
15 <dcbf>: Enable L3OPT operand on POWER10.
16 <sync>: Enable SC2 operand on POWER10.
17
a501eb44
SH		 182020-05-19 Stafford Horne <shorne@gmail.com>
19
20 PR 25184
21 * or1k-asm.c: Regenerate.
22 * or1k-desc.c: Regenerate.
23 * or1k-desc.h: Regenerate.
24 * or1k-dis.c: Regenerate.
25 * or1k-ibld.c: Regenerate.
26 * or1k-opc.c: Regenerate.
27 * or1k-opc.h: Regenerate.
28 * or1k-opinst.c: Regenerate.
29
3b646889
AM		 302020-05-11 Alan Modra <amodra@gmail.com>
31
32 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
33 xsmaxcqp, xsmincqp.
34
9cc4ce88
AM		 352020-05-11 Alan Modra <amodra@gmail.com>
36
37 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
38 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
39
5d57bc3f
AM		 402020-05-11 Alan Modra <amodra@gmail.com>
41
42 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
43
66ef5847
AM		 442020-05-11 Alan Modra <amodra@gmail.com>
45
46 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
47 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
48
4f3e9537
PB		 492020-05-11 Peter Bergner <bergner@linux.ibm.com>
50
51 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
52 mnemonics.
53
ec40e91c
AM		 542020-05-11 Alan Modra <amodra@gmail.com>
55
56 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
57 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
58 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
59 (prefix_opcodes): Add xxeval.
60
d7e97a76
AM		 612020-05-11 Alan Modra <amodra@gmail.com>
62
63 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
64 xxgenpcvwm, xxgenpcvdm.
65
fdefed7c
AM		 662020-05-11 Alan Modra <amodra@gmail.com>
67
68 * ppc-opc.c (MP, VXVAM_MASK): Define.
69 (VXVAPS_MASK): Use VXVA_MASK.
70 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
71 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
72 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
73 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
74
aa3c112f
AM		 752020-05-11 Alan Modra <amodra@gmail.com>
76 Peter Bergner <bergner@linux.ibm.com>
77
78 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
79 New functions.
80 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
81 YMSK2, XA6a, XA6ap, XB6a entries.
82 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
83 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
84 (PPCVSX4): Define.
85 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
86 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
87 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
88 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
89 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
90 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
91 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
92 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
93 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
94 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
95 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
96 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
97 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
98 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
99
6edbfd3b
AM		 1002020-05-11 Alan Modra <amodra@gmail.com>
101
102 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
103 (insert_xts, extract_xts): New functions.
104 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
105 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
106 (VXRC_MASK, VXSH_MASK): Define.
107 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
108 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
109 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
110 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
111 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
112 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
113 xxblendvh, xxblendvw, xxblendvd, xxpermx.
114
c7d7aea2
AM		 1152020-05-11 Alan Modra <amodra@gmail.com>
116
117 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
118 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
119 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
120 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
121 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
122
94ba9882
AM		 1232020-05-11 Alan Modra <amodra@gmail.com>
124
125 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
126 (XTP, DQXP, DQXP_MASK): Define.
127 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
128 (prefix_opcodes): Add plxvp and pstxvp.
129
f4791f1a
AM		 1302020-05-11 Alan Modra <amodra@gmail.com>
131
132 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
133 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
134 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
135
3ff0a5ba
PB		 1362020-05-11 Peter Bergner <bergner@linux.ibm.com>
137
138 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
139
afef4fe9
PB		 1402020-05-11 Peter Bergner <bergner@linux.ibm.com>
141
142 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
143 (L1OPT): Define.
144 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
145
1224c05d
PB		 1462020-05-11 Peter Bergner <bergner@linux.ibm.com>
147
148 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
149
6bbb0c05
AM		 1502020-05-11 Alan Modra <amodra@gmail.com>
151
152 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
153
7c1f4227
AM		 1542020-05-11 Alan Modra <amodra@gmail.com>
155
156 * ppc-dis.c (ppc_opts): Add "power10" entry.
157 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
158 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
159
73199c2b
NC		 1602020-05-11 Nick Clifton <nickc@redhat.com>
161
162 * po/fr.po: Updated French translation.
163
09c1e68a
AC		 1642020-04-30 Alex Coplan <alex.coplan@arm.com>
165
166 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
167 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
168 (operand_general_constraint_met_p): validate
169 AARCH64_OPND_UNDEFINED.
170 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
171 for FLD_imm16_2.
172 * aarch64-asm-2.c: Regenerated.
173 * aarch64-dis-2.c: Regenerated.
174 * aarch64-opc-2.c: Regenerated.
175
9654d51a
NC		 1762020-04-29 Nick Clifton <nickc@redhat.com>
177
178 PR 22699
179 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
180 and SETRC insns.
181
c2e71e57
NC		 1822020-04-29 Nick Clifton <nickc@redhat.com>
183
184 * po/sv.po: Updated Swedish translation.
185
5c936ef5
NC		 1862020-04-29 Nick Clifton <nickc@redhat.com>
187
188 PR 22699
189 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
190 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
191 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
192 IMM0_8U case.
193
bb2a1453
AS		 1942020-04-21 Andreas Schwab <schwab@linux-m68k.org>
195
196 PR 25848
197 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
198 cmpi only on m68020up and cpu32.
199
c2e5c986
SD		 2002020-04-20 Sudakshina Das <sudi.das@arm.com>
201
202 * aarch64-asm.c (aarch64_ins_none): New.
203 * aarch64-asm.h (ins_none): New declaration.
204 * aarch64-dis.c (aarch64_ext_none): New.
205 * aarch64-dis.h (ext_none): New declaration.
206 * aarch64-opc.c (aarch64_print_operand): Update case for
207 AARCH64_OPND_BARRIER_PSB.
208 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
209 (AARCH64_OPERANDS): Update inserter/extracter for
210 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
211 * aarch64-asm-2.c: Regenerated.
212 * aarch64-dis-2.c: Regenerated.
213 * aarch64-opc-2.c: Regenerated.
214
8a6e1d1d
SD		 2152020-04-20 Sudakshina Das <sudi.das@arm.com>
216
217 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
218 (aarch64_feature_ras, RAS): Likewise.
219 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
220 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
221 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
222 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
223 * aarch64-asm-2.c: Regenerated.
224 * aarch64-dis-2.c: Regenerated.
225 * aarch64-opc-2.c: Regenerated.
226
e409955d
FS		 2272020-04-17 Fredrik Strupe <fredrik@strupe.net>
228
229 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
230 (print_insn_neon): Support disassembly of conditional
231 instructions.
232
c54a9b56
DF		 2332020-02-16 David Faust <david.faust@oracle.com>
234
235 * bpf-desc.c: Regenerate.
236 * bpf-desc.h: Likewise.
237 * bpf-opc.c: Regenerate.
238 * bpf-opc.h: Likewise.
239
bb651e8b
CL		 2402020-04-07 Lili Cui <lili.cui@intel.com>
241
242 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
243 (prefix_table): New instructions (see prefixes above).
244 (rm_table): Likewise
245 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
246 CPU_ANY_TSXLDTRK_FLAGS.
247 (cpu_flags): Add CpuTSXLDTRK.
248 * i386-opc.h (enum): Add CpuTSXLDTRK.
249 (i386_cpu_flags): Add cputsxldtrk.
250 * i386-opc.tbl: Add XSUSPLDTRK insns.
251 * i386-init.h: Regenerate.
252 * i386-tbl.h: Likewise.
253
4b27d27c
L		 2542020-04-02 Lili Cui <lili.cui@intel.com>
255
256 * i386-dis.c (prefix_table): New instructions serialize.
257 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
258 CPU_ANY_SERIALIZE_FLAGS.
259 (cpu_flags): Add CpuSERIALIZE.
260 * i386-opc.h (enum): Add CpuSERIALIZE.
261 (i386_cpu_flags): Add cpuserialize.
262 * i386-opc.tbl: Add SERIALIZE insns.
263 * i386-init.h: Regenerate.
264 * i386-tbl.h: Likewise.
265
832a5807
AM		 2662020-03-26 Alan Modra <amodra@gmail.com>
267
268 * disassemble.h (opcodes_assert): Declare.
269 (OPCODES_ASSERT): Define.
270 * disassemble.c: Don't include assert.h. Include opintl.h.
271 (opcodes_assert): New function.
272 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
273 (bfd_h8_disassemble): Reduce size of data array. Correctly
274 calculate maxlen. Omit insn decoding when insn length exceeds
275 maxlen. Exit from nibble loop when looking for E, before
276 accessing next data byte. Move processing of E outside loop.
277 Replace tests of maxlen in loop with assertions.
278
4c4addbe
AM		 2792020-03-26 Alan Modra <amodra@gmail.com>
280
281 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
282
a18cd0ca
AM		 2832020-03-25 Alan Modra <amodra@gmail.com>
284
285 * z80-dis.c (suffix): Init mybuf.
286
57cb32b3
AM		 2872020-03-22 Alan Modra <amodra@gmail.com>
288
289 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
290 successflly read from section.
291
beea5cc1
AM		 2922020-03-22 Alan Modra <amodra@gmail.com>
293
294 * arc-dis.c (find_format): Use ISO C string concatenation rather
295 than line continuation within a string. Don't access needs_limm
296 before testing opcode != NULL.
297
03704c77
AM		 2982020-03-22 Alan Modra <amodra@gmail.com>
299
300 * ns32k-dis.c (print_insn_arg): Update comment.
301 (print_insn_ns32k): Reduce size of index_offset array, and
302 initialize, passing -1 to print_insn_arg for args that are not
303 an index. Don't exit arg loop early. Abort on bad arg number.
304
d1023b5d
AM		 3052020-03-22 Alan Modra <amodra@gmail.com>
306
307 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
308 * s12z-opc.c: Formatting.
309 (operands_f): Return an int.
310 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
311 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
312 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
313 (exg_sex_discrim): Likewise.
314 (create_immediate_operand, create_bitfield_operand),
315 (create_register_operand_with_size, create_register_all_operand),
316 (create_register_all16_operand, create_simple_memory_operand),
317 (create_memory_operand, create_memory_auto_operand): Don't
318 segfault on malloc failure.
319 (z_ext24_decode): Return an int status, negative on fail, zero
320 on success.
321 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
322 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
323 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
324 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
325 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
326 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
327 (loop_primitive_decode, shift_decode, psh_pul_decode),
328 (bit_field_decode): Similarly.
329 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
330 to return value, update callers.
331 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
332 Don't segfault on NULL operand.
333 (decode_operation): Return OP_INVALID on first fail.
334 (decode_s12z): Check all reads, returning -1 on fail.
335
340f3ac8
AM		 3362020-03-20 Alan Modra <amodra@gmail.com>
337
338 * metag-dis.c (print_insn_metag): Don't ignore status from
339 read_memory_func.
340
fe90ae8a
AM		 3412020-03-20 Alan Modra <amodra@gmail.com>
342
343 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
344 Initialize parts of buffer not written when handling a possible
345 2-byte insn at end of section. Don't attempt decoding of such
346 an insn by the 4-byte machinery.
347
833d919c
AM		 3482020-03-20 Alan Modra <amodra@gmail.com>
349
350 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
351 partially filled buffer. Prevent lookup of 4-byte insns when
352 only VLE 2-byte insns are possible due to section size. Print
353 ".word" rather than ".long" for 2-byte leftovers.
354
327ef784
NC		 3552020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
356
357 PR 25641
358 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
359
1673df32
JB		 3602020-03-13 Jan Beulich <jbeulich@suse.com>
361
362 * i386-dis.c (X86_64_0D): Rename to ...
363 (X86_64_0E): ... this.
364
384f3689
L		 3652020-03-09 H.J. Lu <hongjiu.lu@intel.com>
366
367 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
368 * Makefile.in: Regenerated.
369
865e2027
JB		 3702020-03-09 Jan Beulich <jbeulich@suse.com>
371
372 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
373 3-operand pseudos.
374 * i386-tbl.h: Re-generate.
375
2f13234b
JB		 3762020-03-09 Jan Beulich <jbeulich@suse.com>
377
378 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
379 vprot*, vpsha*, and vpshl*.
380 * i386-tbl.h: Re-generate.
381
3fabc179
JB		 3822020-03-09 Jan Beulich <jbeulich@suse.com>
383
384 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
385 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
386 * i386-tbl.h: Re-generate.
387
3677e4c1
JB		 3882020-03-09 Jan Beulich <jbeulich@suse.com>
389
390 * i386-gen.c (set_bitfield): Ignore zero-length field names.
391 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
392 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
393 * i386-tbl.h: Re-generate.
394
4c4898e8
JB		 3952020-03-09 Jan Beulich <jbeulich@suse.com>
396
397 * i386-gen.c (struct template_arg, struct template_instance,
398 struct template_param, struct template, templates,
399 parse_template, expand_templates): New.
400 (process_i386_opcodes): Various local variables moved to
401 expand_templates. Call parse_template and expand_templates.
402 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
403 * i386-tbl.h: Re-generate.
404
bc49bfd8
JB		 4052020-03-06 Jan Beulich <jbeulich@suse.com>
406
407 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
408 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
409 register and memory source templates. Replace VexW= by VexW*
410 where applicable.
411 * i386-tbl.h: Re-generate.
412
4873e243
JB		 4132020-03-06 Jan Beulich <jbeulich@suse.com>
414
415 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
416 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
417 * i386-tbl.h: Re-generate.
418
672a349b
JB		 4192020-03-06 Jan Beulich <jbeulich@suse.com>
420
421 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
422 * i386-tbl.h: Re-generate.
423
4ed21b58
JB		 4242020-03-06 Jan Beulich <jbeulich@suse.com>
425
426 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
427 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
428 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
429 VexW0 on SSE2AVX variants.
430 (vmovq): Drop NoRex64 from XMM/XMM variants.
431 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
432 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
433 applicable use VexW0.
434 * i386-tbl.h: Re-generate.
435
643bb870
JB		 4362020-03-06 Jan Beulich <jbeulich@suse.com>
437
438 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
439 * i386-opc.h (Rex64): Delete.
440 (struct i386_opcode_modifier): Remove rex64 field.
441 * i386-opc.tbl (crc32): Drop Rex64.
442 Replace Rex64 with Size64 everywhere else.
443 * i386-tbl.h: Re-generate.
444
a23b33b3
JB		 4452020-03-06 Jan Beulich <jbeulich@suse.com>
446
447 * i386-dis.c (OP_E_memory): Exclude recording of used address
448 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
449 addressed memory operands for MPX insns.
450
a0497384
JB		 4512020-03-06 Jan Beulich <jbeulich@suse.com>
452
453 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
454 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
455 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
456 (ptwrite): Split into non-64-bit and 64-bit forms.
457 * i386-tbl.h: Re-generate.
458
b630c145
JB		 4592020-03-06 Jan Beulich <jbeulich@suse.com>
460
461 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
462 template.
463 * i386-tbl.h: Re-generate.
464
a847e322
JB		 4652020-03-04 Jan Beulich <jbeulich@suse.com>
466
467 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
468 (prefix_table): Move vmmcall here. Add vmgexit.
469 (rm_table): Replace vmmcall entry by prefix_table[] escape.
470 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
471 (cpu_flags): Add CpuSEV_ES entry.
472 * i386-opc.h (CpuSEV_ES): New.
473 (union i386_cpu_flags): Add cpusev_es field.
474 * i386-opc.tbl (vmgexit): New.
475 * i386-init.h, i386-tbl.h: Re-generate.
476
3cd7f3e3
L		 4772020-03-03 H.J. Lu <hongjiu.lu@intel.com>
478
479 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
480 with MnemonicSize.
481 * i386-opc.h (IGNORESIZE): New.
482 (DEFAULTSIZE): Likewise.
483 (IgnoreSize): Removed.
484 (DefaultSize): Likewise.
485 (MnemonicSize): New.
486 (i386_opcode_modifier): Replace ignoresize/defaultsize with
487 mnemonicsize.
488 * i386-opc.tbl (IgnoreSize): New.
489 (DefaultSize): Likewise.
490 * i386-tbl.h: Regenerated.
491
b8ba1385
SB		 4922020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
493
494 PR 25627
495 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
496 instructions.
497
10d97a0f
L		 4982020-03-03 H.J. Lu <hongjiu.lu@intel.com>
499
500 PR gas/25622
501 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
502 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
503 * i386-tbl.h: Regenerated.
504
dc1e8a47
AM		 5052020-02-26 Alan Modra <amodra@gmail.com>
506
507 * aarch64-asm.c: Indent labels correctly.
508 * aarch64-dis.c: Likewise.
509 * aarch64-gen.c: Likewise.
510 * aarch64-opc.c: Likewise.
511 * alpha-dis.c: Likewise.
512 * i386-dis.c: Likewise.
513 * nds32-asm.c: Likewise.
514 * nfp-dis.c: Likewise.
515 * visium-dis.c: Likewise.
516
265b4673
CZ		 5172020-02-25 Claudiu Zissulescu <claziss@gmail.com>
518
519 * arc-regs.h (int_vector_base): Make it available for all ARC
520 CPUs.
521
bd0cf5a6
NC		 5222020-02-20 Nelson Chu <nelson.chu@sifive.com>
523
524 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
525 changed.
526
fa164239
JW		 5272020-02-19 Nelson Chu <nelson.chu@sifive.com>
528
529 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
530 c.mv/c.li if rs1 is zero.
531
272a84b1
L		 5322020-02-17 H.J. Lu <hongjiu.lu@intel.com>
533
534 * i386-gen.c (cpu_flag_init): Replace CpuABM with
535 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
536 CPU_POPCNT_FLAGS.
537 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
538 * i386-opc.h (CpuABM): Removed.
539 (CpuPOPCNT): New.
540 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
541 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
542 popcnt. Remove CpuABM from lzcnt.
543 * i386-init.h: Regenerated.
544 * i386-tbl.h: Likewise.
545
1f730c46
JB		 5462020-02-17 Jan Beulich <jbeulich@suse.com>
547
548 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
549 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
550 VexW1 instead of open-coding them.
551 * i386-tbl.h: Re-generate.
552
c8f8eebc
JB		 5532020-02-17 Jan Beulich <jbeulich@suse.com>
554
555 * i386-opc.tbl (AddrPrefixOpReg): Define.
556 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
557 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
558 templates. Drop NoRex64.
559 * i386-tbl.h: Re-generate.
560
b9915cbc
JB		 5612020-02-17 Jan Beulich <jbeulich@suse.com>
562
563 PR gas/6518
564 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
565 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
566 into Intel syntax instance (with Unpsecified) and AT&T one
567 (without).
568 (vcvtneps2bf16): Likewise, along with folding the two so far
569 separate ones.
570 * i386-tbl.h: Re-generate.
571
ce504911
L		 5722020-02-16 H.J. Lu <hongjiu.lu@intel.com>
573
574 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
575 CPU_ANY_SSE4A_FLAGS.
576
dabec65d
AM		 5772020-02-17 Alan Modra <amodra@gmail.com>
578
579 * i386-gen.c (cpu_flag_init): Correct last change.
580
af5c13b0
L		 5812020-02-16 H.J. Lu <hongjiu.lu@intel.com>
582
583 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
584 CPU_ANY_SSE4_FLAGS.
585
6867aac0
L		 5862020-02-14 H.J. Lu <hongjiu.lu@intel.com>
587
588 * i386-opc.tbl (movsx): Remove Intel syntax comments.
589 (movzx): Likewise.
590
65fca059
JB		 5912020-02-14 Jan Beulich <jbeulich@suse.com>
592
593 PR gas/25438
594 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
595 destination for Cpu64-only variant.
596 (movzx): Fold patterns.
597 * i386-tbl.h: Re-generate.
598
7deea9aa
JB		 5992020-02-13 Jan Beulich <jbeulich@suse.com>
600
601 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
602 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
603 CPU_ANY_SSE4_FLAGS entry.
604 * i386-init.h: Re-generate.
605
6c0946d0
JB		 6062020-02-12 Jan Beulich <jbeulich@suse.com>
607
608 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
609 with Unspecified, making the present one AT&T syntax only.
610 * i386-tbl.h: Re-generate.
611
ddb56fe6
JB		 6122020-02-12 Jan Beulich <jbeulich@suse.com>
613
614 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
615 * i386-tbl.h: Re-generate.
616
5990e377
JB		 6172020-02-12 Jan Beulich <jbeulich@suse.com>
618
619 PR gas/24546
620 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
621 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
622 Amd64 and Intel64 templates.
623 (call, jmp): Likewise for far indirect variants. Dro
624 Unspecified.
625 * i386-tbl.h: Re-generate.
626
50128d0c
JB		 6272020-02-11 Jan Beulich <jbeulich@suse.com>
628
629 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
630 * i386-opc.h (ShortForm): Delete.
631 (struct i386_opcode_modifier): Remove shortform field.
632 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
633 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
634 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
635 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
636 Drop ShortForm.
637 * i386-tbl.h: Re-generate.
638
1e05b5c4
JB		 6392020-02-11 Jan Beulich <jbeulich@suse.com>
640
641 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
642 fucompi): Drop ShortForm from operand-less templates.
643 * i386-tbl.h: Re-generate.
644
2f5dd314
AM		 6452020-02-11 Alan Modra <amodra@gmail.com>
646
647 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
648 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
649 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
650 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
651 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
652
5aae9ae9
MM		 6532020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
654
655 * arm-dis.c (print_insn_cde): Define 'V' parse character.
656 (cde_opcodes): Add VCX* instructions.
657
4934a27c
MM		 6582020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
659 Matthew Malcomson <matthew.malcomson@arm.com>
660
661 * arm-dis.c (struct cdeopcode32): New.
662 (CDE_OPCODE): New macro.
663 (cde_opcodes): New disassembly table.
664 (regnames): New option to table.
665 (cde_coprocs): New global variable.
666 (print_insn_cde): New
667 (print_insn_thumb32): Use print_insn_cde.
668 (parse_arm_disassembler_options): Parse coprocN args.
669
4b5aaf5f
L		 6702020-02-10 H.J. Lu <hongjiu.lu@intel.com>
671
672 PR gas/25516
673 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
674 with ISA64.
675 * i386-opc.h (AMD64): Removed.
676 (Intel64): Likewose.
677 (AMD64): New.
678 (INTEL64): Likewise.
679 (INTEL64ONLY): Likewise.
680 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
681 * i386-opc.tbl (Amd64): New.
682 (Intel64): Likewise.
683 (Intel64Only): Likewise.
684 Replace AMD64 with Amd64. Update sysenter/sysenter with
685 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
686 * i386-tbl.h: Regenerated.
687
9fc0b501
SB		 6882020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
689
690 PR 25469
691 * z80-dis.c: Add support for GBZ80 opcodes.
692
c5d7be0c
AM		 6932020-02-04 Alan Modra <amodra@gmail.com>
694
695 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
696
44e4546f
AM		 6972020-02-03 Alan Modra <amodra@gmail.com>
698
699 * m32c-ibld.c: Regenerate.
700
b2b1453a
AM		 7012020-02-01 Alan Modra <amodra@gmail.com>
702
703 * frv-ibld.c: Regenerate.
704
4102be5c
JB		 7052020-01-31 Jan Beulich <jbeulich@suse.com>
706
707 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
708 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
709 (OP_E_memory): Replace xmm_mdq_mode case label by
710 vex_scalar_w_dq_mode one.
711 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
712
825bd36c
JB		 7132020-01-31 Jan Beulich <jbeulich@suse.com>
714
715 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
716 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
717 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
718 (intel_operand_size): Drop vex_w_dq_mode case label.
719
c3036ed0
RS		 7202020-01-31 Richard Sandiford <richard.sandiford@arm.com>
721
722 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
723 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
724
0c115f84
AM		 7252020-01-30 Alan Modra <amodra@gmail.com>
726
727 * m32c-ibld.c: Regenerate.
728
bd434cc4
JM		 7292020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
730
731 * bpf-opc.c: Regenerate.
732
aeab2b26
JB		 7332020-01-30 Jan Beulich <jbeulich@suse.com>
734
735 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
736 (dis386): Use them to replace C2/C3 table entries.
737 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
738 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
739 ones. Use Size64 instead of DefaultSize on Intel64 ones.
740 * i386-tbl.h: Re-generate.
741
62b3f548
JB		 7422020-01-30 Jan Beulich <jbeulich@suse.com>
743
744 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
745 forms.
746 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
747 DefaultSize.
748 * i386-tbl.h: Re-generate.
749
1bd8ae10
AM		 7502020-01-30 Alan Modra <amodra@gmail.com>
751
752 * tic4x-dis.c (tic4x_dp): Make unsigned.
753
bc31405e
L		 7542020-01-27 H.J. Lu <hongjiu.lu@intel.com>
755 Jan Beulich <jbeulich@suse.com>
756
757 PR binutils/25445
758 * i386-dis.c (MOVSXD_Fixup): New function.
759 (movsxd_mode): New enum.
760 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
761 (intel_operand_size): Handle movsxd_mode.
762 (OP_E_register): Likewise.
763 (OP_G): Likewise.
764 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
765 register on movsxd. Add movsxd with 16-bit destination register
766 for AMD64 and Intel64 ISAs.
767 * i386-tbl.h: Regenerated.
768
7568c93b
TC		 7692020-01-27 Tamar Christina <tamar.christina@arm.com>
770
771 PR 25403
772 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
773 * aarch64-asm-2.c: Regenerate
774 * aarch64-dis-2.c: Likewise.
775 * aarch64-opc-2.c: Likewise.
776
c006a730
JB		 7772020-01-21 Jan Beulich <jbeulich@suse.com>
778
779 * i386-opc.tbl (sysret): Drop DefaultSize.
780 * i386-tbl.h: Re-generate.
781
c906a69a
JB		 7822020-01-21 Jan Beulich <jbeulich@suse.com>
783
784 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
785 Dword.
786 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
787 * i386-tbl.h: Re-generate.
788
26916852
NC		 7892020-01-20 Nick Clifton <nickc@redhat.com>
790
791 * po/de.po: Updated German translation.
792 * po/pt_BR.po: Updated Brazilian Portuguese translation.
793 * po/uk.po: Updated Ukranian translation.
794
4d6cbb64
AM		 7952020-01-20 Alan Modra <amodra@gmail.com>
796
797 * hppa-dis.c (fput_const): Remove useless cast.
798
2bddb71a
AM		 7992020-01-20 Alan Modra <amodra@gmail.com>
800
801 * arm-dis.c (print_insn_arm): Wrap 'T' value.
802
1b1bb2c6
NC		 8032020-01-18 Nick Clifton <nickc@redhat.com>
804
805 * configure: Regenerate.
806 * po/opcodes.pot: Regenerate.
807
ae774686
NC		 8082020-01-18 Nick Clifton <nickc@redhat.com>
809
810 Binutils 2.34 branch created.
811
07f1f3aa
CB		 8122020-01-17 Christian Biesinger <cbiesinger@google.com>
813
814 * opintl.h: Fix spelling error (seperate).
815
42e04b36
L		 8162020-01-17 H.J. Lu <hongjiu.lu@intel.com>
817
818 * i386-opc.tbl: Add {vex} pseudo prefix.
819 * i386-tbl.h: Regenerated.
820
2da2eaf4
AV		 8212020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
822
823 PR 25376
824 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
825 (neon_opcodes): Likewise.
826 (select_arm_features): Make sure we enable MVE bits when selecting
827 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
828 any architecture.
829
d0849eed
JB		 8302020-01-16 Jan Beulich <jbeulich@suse.com>
831
832 * i386-opc.tbl: Drop stale comment from XOP section.
833
9cf70a44
JB		 8342020-01-16 Jan Beulich <jbeulich@suse.com>
835
836 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
837 (extractps): Add VexWIG to SSE2AVX forms.
838 * i386-tbl.h: Re-generate.
839
4814632e
JB		 8402020-01-16 Jan Beulich <jbeulich@suse.com>
841
842 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
843 Size64 from and use VexW1 on SSE2AVX forms.
844 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
845 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
846 * i386-tbl.h: Re-generate.
847
aad09917
AM		 8482020-01-15 Alan Modra <amodra@gmail.com>
849
850 * tic4x-dis.c (tic4x_version): Make unsigned long.
851 (optab, optab_special, registernames): New file scope vars.
852 (tic4x_print_register): Set up registernames rather than
853 malloc'd registertable.
854 (tic4x_disassemble): Delete optable and optable_special. Use
855 optab and optab_special instead. Throw away old optab,
856 optab_special and registernames when info->mach changes.
857
7a6bf3be
SB		 8582020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
859
860 PR 25377
861 * z80-dis.c (suffix): Use .db instruction to generate double
862 prefix.
863
ca1eaac0
AM		 8642020-01-14 Alan Modra <amodra@gmail.com>
865
866 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
867 values to unsigned before shifting.
868
1d67fe3b
TT		 8692020-01-13 Thomas Troeger <tstroege@gmx.de>
870
871 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
872 flow instructions.
873 (print_insn_thumb16, print_insn_thumb32): Likewise.
874 (print_insn): Initialize the insn info.
875 * i386-dis.c (print_insn): Initialize the insn info fields, and
876 detect jumps.
877
5e4f7e05
CZ		 8782012-01-13 Claudiu Zissulescu <claziss@gmail.com>
879
880 * arc-opc.c (C_NE): Make it required.
881
b9fe6b8a
CZ		 8822012-01-13 Claudiu Zissulescu <claziss@gmail.com>
883
884 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
885 reserved register name.
886
90dee485
AM		 8872020-01-13 Alan Modra <amodra@gmail.com>
888
889 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
890 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
891
febda64f
AM		 8922020-01-13 Alan Modra <amodra@gmail.com>
893
894 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
895 result of wasm_read_leb128 in a uint64_t and check that bits
896 are not lost when copying to other locals. Use uint32_t for
897 most locals. Use PRId64 when printing int64_t.
898
df08b588
AM		 8992020-01-13 Alan Modra <amodra@gmail.com>
900
901 * score-dis.c: Formatting.
902 * score7-dis.c: Formatting.
903
b2c759ce
AM		 9042020-01-13 Alan Modra <amodra@gmail.com>
905
906 * score-dis.c (print_insn_score48): Use unsigned variables for
907 unsigned values. Don't left shift negative values.
908 (print_insn_score32): Likewise.
909 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
910
5496abe1
AM		 9112020-01-13 Alan Modra <amodra@gmail.com>
912
913 * tic4x-dis.c (tic4x_print_register): Remove dead code.
914
202e762b
AM		 9152020-01-13 Alan Modra <amodra@gmail.com>
916
917 * fr30-ibld.c: Regenerate.
918
7ef412cf
AM		 9192020-01-13 Alan Modra <amodra@gmail.com>
920
921 * xgate-dis.c (print_insn): Don't left shift signed value.
922 (ripBits): Formatting, use 1u.
923
7f578b95
AM		 9242020-01-10 Alan Modra <amodra@gmail.com>
925
926 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
927 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
928
441af85b
AM		 9292020-01-10 Alan Modra <amodra@gmail.com>
930
931 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
932 and XRREG value earlier to avoid a shift with negative exponent.
933 * m10200-dis.c (disassemble): Similarly.
934
bce58db4
NC		 9352020-01-09 Nick Clifton <nickc@redhat.com>
936
937 PR 25224
938 * z80-dis.c (ld_ii_ii): Use correct cast.
939
40c75bc8
SB		 9402020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
941
942 PR 25224
943 * z80-dis.c (ld_ii_ii): Use character constant when checking
944 opcode byte value.
945
d835a58b
JB		 9462020-01-09 Jan Beulich <jbeulich@suse.com>
947
948 * i386-dis.c (SEP_Fixup): New.
949 (SEP): Define.
950 (dis386_twobyte): Use it for sysenter/sysexit.
951 (enum x86_64_isa): Change amd64 enumerator to value 1.
952 (OP_J): Compare isa64 against intel64 instead of amd64.
953 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
954 forms.
955 * i386-tbl.h: Re-generate.
956
030a2e78
AM		 9572020-01-08 Alan Modra <amodra@gmail.com>
958
959 * z8k-dis.c: Include libiberty.h
960 (instr_data_s): Make max_fetched unsigned.
961 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
962 Don't exceed byte_info bounds.
963 (output_instr): Make num_bytes unsigned.
964 (unpack_instr): Likewise for nibl_count and loop.
965 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
966 idx unsigned.
967 * z8k-opc.h: Regenerate.
968
bb82aefe
SV		 9692020-01-07 Shahab Vahedi <shahab@synopsys.com>
970
971 * arc-tbl.h (llock): Use 'LLOCK' as class.
972 (llockd): Likewise.
973 (scond): Use 'SCOND' as class.
974 (scondd): Likewise.
975 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
976 (scondd): Likewise.
977
cc6aa1a6
AM		 9782020-01-06 Alan Modra <amodra@gmail.com>
979
980 * m32c-ibld.c: Regenerate.
981
660e62b1
AM		 9822020-01-06 Alan Modra <amodra@gmail.com>
983
984 PR 25344
985 * z80-dis.c (suffix): Don't use a local struct buffer copy.
986 Peek at next byte to prevent recursion on repeated prefix bytes.
987 Ensure uninitialised "mybuf" is not accessed.
988 (print_insn_z80): Don't zero n_fetch and n_used here,..
989 (print_insn_z80_buf): ..do it here instead.
990
c9ae58fe
AM		 9912020-01-04 Alan Modra <amodra@gmail.com>
992
993 * m32r-ibld.c: Regenerate.
994
5f57d4ec
AM		 9952020-01-04 Alan Modra <amodra@gmail.com>
996
997 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
998
2c5c1196
AM		 9992020-01-04 Alan Modra <amodra@gmail.com>
1000
1001 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1002
2e98c6c5
AM		 10032020-01-04 Alan Modra <amodra@gmail.com>
1004
1005 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1006
567dfba2
JB		 10072020-01-03 Jan Beulich <jbeulich@suse.com>
1008
5437a02a
JB		 1009 * aarch64-tbl.h (aarch64_opcode_table): Use
1010 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1011
10122020-01-03 Jan Beulich <jbeulich@suse.com>
1013
1014 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1015 forms of SUDOT and USDOT.
1016
8c45011a
JB		 10172020-01-03 Jan Beulich <jbeulich@suse.com>
1018
5437a02a 1019 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1020 uzip{1,2}.
1021 * opcodes/aarch64-dis-2.c: Re-generate.
1022
f4950f76
JB		 10232020-01-03 Jan Beulich <jbeulich@suse.com>
1024
5437a02a 1025 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1026 FMMLA encoding.
1027 * opcodes/aarch64-dis-2.c: Re-generate.
1028
6655dba2
SB		 10292020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1030
1031 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1032
b14ce8bf
AM		 10332020-01-01 Alan Modra <amodra@gmail.com>
1034
1035 Update year range in copyright notice of all files.
1036
0b114740 1037For older changes see ChangeLog-2019
3499769a 1038\f
0b114740 1039Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1040
1041Copying and distribution of this file, with or without modification,
1042are permitted in any medium without royalty provided the copyright
1043notice and this notice are preserved.
1044
1045Local Variables:
1046mode: change-log
1047left-margin: 8
1048fill-column: 74
1049version-control: never
1050End:
A mirror of the official binutils-gdb repository