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* ldlang.c (section_already_linked): Call bfd_discard_group. Typo fix.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
0f154cbd
CD		 12002-06-03 Chris Demetriou <cgd@broadcom.com>
2
3 * cp1.c (Min, Max): Remove #if 0'd functions.
4 * sim-main.h (Min, Max): Remove.
5
e80fc152
CD		 62002-06-03 Chris Demetriou <cgd@broadcom.com>
7
8 * cp1.c: fix formatting of switch case and default labels.
9 * interp.c: Likewise.
10 * sim-main.c: Likewise.
11
bad673a9
CD		 122002-06-03 Chris Demetriou <cgd@broadcom.com>
13
14 * cp1.c: Clean up comments which describe FP formats.
15 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
16
7cbea089
CD		 172002-06-03 Chris Demetriou <cgd@broadcom.com>
18 Ed Satterthwaite <ehs@broadcom.com>
19
20 * configure.in (mipsisa64sb1*-*-*): New target for supporting
21 Broadcom SiByte SB-1 processor configurations.
22 * configure: Regenerate.
23 * sb1.igen: New file.
24 * mips.igen: Include sb1.igen.
25 (sb1): New model.
26 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
27 * mdmx.igen: Add "sb1" model to all appropriate functions and
28 instructions.
29 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
30 (ob_func, ob_acc): Reference the above.
31 (qh_acc): Adjust to keep the same size as ob_acc.
32 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
33 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
34
909daa82
CD		 352002-06-03 Chris Demetriou <cgd@broadcom.com>
36
37 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
38
f4f1b9f1
CD		 392002-06-02 Chris Demetriou <cgd@broadcom.com>
40 Ed Satterthwaite <ehs@broadcom.com>
41
42 * mips.igen (mdmx): New (pseudo-)model.
43 * mdmx.c, mdmx.igen: New files.
44 * Makefile.in (SIM_OBJS): Add mdmx.o.
45 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
46 New typedefs.
47 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
48 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
49 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
50 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
51 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
52 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
53 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
54 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
55 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
56 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
57 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
58 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
59 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
60 (qh_fmtsel): New macros.
61 (_sim_cpu): New member "acc".
62 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
63 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
64
5accf1ff
CD		 652002-05-01 Chris Demetriou <cgd@broadcom.com>
66
67 * interp.c: Use 'deprecated' rather than 'depreciated.'
68 * sim-main.h: Likewise.
69
402586aa
CD		 702002-05-01 Chris Demetriou <cgd@broadcom.com>
71
72 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
73 which wouldn't compile anyway.
74 * sim-main.h (unpredictable_action): New function prototype.
75 (Unpredictable): Define to call igen function unpredictable().
76 (NotWordValue): New macro to call igen function not_word_value().
77 (UndefinedResult): Remove.
78 * interp.c (undefined_result): Remove.
79 (unpredictable_action): New function.
80 * mips.igen (not_word_value, unpredictable): New functions.
81 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
82 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
83 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
84 NotWordValue() to check for unpredictable inputs, then
85 Unpredictable() to handle them.
86
c9b9995a
CD		 872002-02-24 Chris Demetriou <cgd@broadcom.com>
88
89 * mips.igen: Fix formatting of calls to Unpredictable().
90
e1015982
AC		 912002-04-20 Andrew Cagney <ac131313@redhat.com>
92
93 * interp.c (sim_open): Revert previous change.
94
b882a66b
AO		 952002-04-18 Alexandre Oliva <aoliva@redhat.com>
96
97 * interp.c (sim_open): Disable chunk of code that wrote code in
98 vector table entries.
99
c429b7dd
CD		 1002002-03-19 Chris Demetriou <cgd@broadcom.com>
101
102 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
103 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
104 unused definitions.
105
37d146fa
CD		 1062002-03-19 Chris Demetriou <cgd@broadcom.com>
107
108 * cp1.c: Fix many formatting issues.
109
07892c0b
CD		 1102002-03-19 Chris G. Demetriou <cgd@broadcom.com>
111
112 * cp1.c (fpu_format_name): New function to replace...
113 (DOFMT): This. Delete, and update all callers.
114 (fpu_rounding_mode_name): New function to replace...
115 (RMMODE): This. Delete, and update all callers.
116
487f79b7
CD		 1172002-03-19 Chris G. Demetriou <cgd@broadcom.com>
118
119 * interp.c: Move FPU support routines from here to...
120 * cp1.c: Here. New file.
121 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
122 (cp1.o): New target.
123
1e799e28
CD		 1242002-03-12 Chris Demetriou <cgd@broadcom.com>
125
126 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
127 * mips.igen (mips32, mips64): New models, add to all instructions
128 and functions as appropriate.
129 (loadstore_ea, check_u64): New variant for model mips64.
130 (check_fmt_p): New variant for models mipsV and mips64, remove
131 mipsV model marking fro other variant.
132 (SLL) Rename to...
133 (SLLa) this.
134 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
135 for mips32 and mips64.
136 (DCLO, DCLZ): New instructions for mips64.
137
82f728db
CD		 1382002-03-07 Chris Demetriou <cgd@broadcom.com>
139
140 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
141 immediate or code as a hex value with the "%#lx" format.
142 (ANDI): Likewise, and fix printed instruction name.
143
b96e7ef1
CD		 1442002-03-05 Chris Demetriou <cgd@broadcom.com>
145
146 * sim-main.h (UndefinedResult, Unpredictable): New macros
147 which currently do nothing.
148
d35d4f70
CD		 1492002-03-05 Chris Demetriou <cgd@broadcom.com>
150
151 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
152 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
153 (status_CU3): New definitions.
154
155 * sim-main.h (ExceptionCause): Add new values for MIPS32
156 and MIPS64: MDMX, MCheck, CacheErr. Update comments
157 for DebugBreakPoint and NMIReset to note their status in
158 MIPS32 and MIPS64.
159 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
160 (SignalExceptionCacheErr): New exception macros.
161
3ad6f714
CD		 1622002-03-05 Chris Demetriou <cgd@broadcom.com>
163
164 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
165 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
166 is always enabled.
167 (SignalExceptionCoProcessorUnusable): Take as argument the
168 unusable coprocessor number.
169
86b77b47
CD		 1702002-03-05 Chris Demetriou <cgd@broadcom.com>
171
172 * mips.igen: Fix formatting of all SignalException calls.
173
97a88e93 1742002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 175
176 * sim-main.h (SIGNEXTEND): Remove.
177
97a88e93 1782002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 179
180 * mips.igen: Remove gencode comment from top of file, fix
181 spelling in another comment.
182
97a88e93 1832002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 184
185 * mips.igen (check_fmt, check_fmt_p): New functions to check
186 whether specific floating point formats are usable.
187 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
188 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
189 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
190 Use the new functions.
191 (do_c_cond_fmt): Remove format checks...
192 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
193
97a88e93 1942002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 195
196 * mips.igen: Fix formatting of check_fpu calls.
197
41774c9d
CD		 1982002-03-03 Chris Demetriou <cgd@broadcom.com>
199
200 * mips.igen (FLOOR.L.fmt): Store correct destination register.
201
4a0bd876
CD		 2022002-03-03 Chris Demetriou <cgd@broadcom.com>
203
204 * mips.igen: Remove whitespace at end of lines.
205
09297648
CD		 2062002-03-02 Chris Demetriou <cgd@broadcom.com>
207
208 * mips.igen (loadstore_ea): New function to do effective
209 address calculations.
210 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
211 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
212 CACHE): Use loadstore_ea to do effective address computations.
213
043b7057
CD		 2142002-03-02 Chris Demetriou <cgd@broadcom.com>
215
216 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
217 * mips.igen (LL, CxC1, MxC1): Likewise.
218
c1e8ada4
CD		 2192002-03-02 Chris Demetriou <cgd@broadcom.com>
220
221 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
222 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
223 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
224 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
225 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
226 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
227 Don't split opcode fields by hand, use the opcode field values
228 provided by igen.
229
3e1dca16
CD		 2302002-03-01 Chris Demetriou <cgd@broadcom.com>
231
232 * mips.igen (do_divu): Fix spacing.
233
234 * mips.igen (do_dsllv): Move to be right before DSLLV,
235 to match the rest of the do_<shift> functions.
236
fff8d27d
CD		 2372002-03-01 Chris Demetriou <cgd@broadcom.com>
238
239 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
240 DSRL32, do_dsrlv): Trace inputs and results.
241
0d3e762b
CD		 2422002-03-01 Chris Demetriou <cgd@broadcom.com>
243
244 * mips.igen (CACHE): Provide instruction-printing string.
245
246 * interp.c (signal_exception): Comment tokens after #endif.
247
eb5fcf93
CD		 2482002-02-28 Chris Demetriou <cgd@broadcom.com>
249
250 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
251 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
252 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
253 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
254 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
255 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
256 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
257 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
258
bb22bd7d
CD		 2592002-02-28 Chris Demetriou <cgd@broadcom.com>
260
261 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
262 instruction-printing string.
263 (LWU): Use '64' as the filter flag.
264
91a177cf
CD		 2652002-02-28 Chris Demetriou <cgd@broadcom.com>
266
267 * mips.igen (SDXC1): Fix instruction-printing string.
268
387f484a
CD		 2692002-02-28 Chris Demetriou <cgd@broadcom.com>
270
271 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
272 filter flags "32,f".
273
3d81f391
CD		 2742002-02-27 Chris Demetriou <cgd@broadcom.com>
275
276 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
277 as the filter flag.
278
af5107af
CD		 2792002-02-27 Chris Demetriou <cgd@broadcom.com>
280
281 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
282 add a comma) so that it more closely match the MIPS ISA
283 documentation opcode partitioning.
284 (PREF): Put useful names on opcode fields, and include
285 instruction-printing string.
286
ca971540
CD		 2872002-02-27 Chris Demetriou <cgd@broadcom.com>
288
289 * mips.igen (check_u64): New function which in the future will
290 check whether 64-bit instructions are usable and signal an
291 exception if not. Currently a no-op.
292 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
293 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
294 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
295 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
296
297 * mips.igen (check_fpu): New function which in the future will
298 check whether FPU instructions are usable and signal an exception
299 if not. Currently a no-op.
300 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
301 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
302 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
303 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
304 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
305 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
306 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
307 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
308
1c47a468
CD		 3092002-02-27 Chris Demetriou <cgd@broadcom.com>
310
311 * mips.igen (do_load_left, do_load_right): Move to be immediately
312 following do_load.
313 (do_store_left, do_store_right): Move to be immediately following
314 do_store.
315
603a98e7
CD		 3162002-02-27 Chris Demetriou <cgd@broadcom.com>
317
318 * mips.igen (mipsV): New model name. Also, add it to
319 all instructions and functions where it is appropriate.
320
c5d00cc7
CD		 3212002-02-18 Chris Demetriou <cgd@broadcom.com>
322
323 * mips.igen: For all functions and instructions, list model
324 names that support that instruction one per line.
325
074e9cb8
CD		 3262002-02-11 Chris Demetriou <cgd@broadcom.com>
327
328 * mips.igen: Add some additional comments about supported
329 models, and about which instructions go where.
330 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
331 order as is used in the rest of the file.
332
9805e229
CD		 3332002-02-11 Chris Demetriou <cgd@broadcom.com>
334
335 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
336 indicating that ALU32_END or ALU64_END are there to check
337 for overflow.
338 (DADD): Likewise, but also remove previous comment about
339 overflow checking.
340
f701dad2
CD		 3412002-02-10 Chris Demetriou <cgd@broadcom.com>
342
343 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
344 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
345 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
346 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
347 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
348 fields (i.e., add and move commas) so that they more closely
349 match the MIPS ISA documentation opcode partitioning.
350
3512002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 352
353 * mips.igen (ADDI): Print immediate value.
354 (BREAK): Print code.
355 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
356 (SLL): Print "nop" specially, and don't run the code
357 that does the shift for the "nop" case.
358
9e52972e
FF		 3592001-11-17 Fred Fish <fnf@redhat.com>
360
361 * sim-main.h (float_operation): Move enum declaration outside
362 of _sim_cpu struct declaration.
363
c0efbca4
JB		 3642001-04-12 Jim Blandy <jimb@redhat.com>
365
366 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
367 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
368 set of the FCSR.
369 * sim-main.h (COCIDX): Remove definition; this isn't supported by
370 PENDING_FILL, and you can get the intended effect gracefully by
371 calling PENDING_SCHED directly.
372
fb891446
BE		 3732001-02-23 Ben Elliston <bje@redhat.com>
374
375 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
376 already defined elsewhere.
377
8030f857
BE		 3782001-02-19 Ben Elliston <bje@redhat.com>
379
380 * sim-main.h (sim_monitor): Return an int.
381 * interp.c (sim_monitor): Add return values.
382 (signal_exception): Handle error conditions from sim_monitor.
383
56b48a7a
CD		 3842001-02-08 Ben Elliston <bje@redhat.com>
385
386 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
387 (store_memory): Likewise, pass cia to sim_core_write*.
388
d3ee60d9
FCE		 3892000-10-19 Frank Ch. Eigler <fche@redhat.com>
390
391 On advice from Chris G. Demetriou <cgd@sibyte.com>:
392 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
393
071da002
AC		 394Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
395
396 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
397 * Makefile.in: Don't delete *.igen when cleaning directory.
398
a28c02cd
AC		 399Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
400
401 * m16.igen (break): Call SignalException not sim_engine_halt.
402
80ee11fa
AC		 403Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
404
405 From Jason Eckhardt:
406 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
407
673388c0
AC		 408Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
409
410 * mips.igen (MxC1, DMxC1): Fix printf formatting.
411
4c0deff4
NC		 4122000-05-24 Michael Hayes <mhayes@cygnus.com>
413
414 * mips.igen (do_dmultx): Fix typo.
415
eb2d80b4
AC		 416Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
417
418 * configure: Regenerated to track ../common/aclocal.m4 changes.
419
dd37a34b
AC		 420Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
421
422 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
423
4c0deff4
NC		 4242000-04-12 Frank Ch. Eigler <fche@redhat.com>
425
426 * sim-main.h (GPR_CLEAR): Define macro.
427
e30db738
AC		 428Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
429
430 * interp.c (decode_coproc): Output long using %lx and not %s.
431
cb7450ea
FCE		 4322000-03-21 Frank Ch. Eigler <fche@redhat.com>
433
434 * interp.c (sim_open): Sort & extend dummy memory regions for
435 --board=jmr3904 for eCos.
436
a3027dd7
FCE		 4372000-03-02 Frank Ch. Eigler <fche@redhat.com>
438
439 * configure: Regenerated.
440
441Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
442
443 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
444 calls, conditional on the simulator being in verbose mode.
445
dfcd3bfb
JM		 446Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
447
448 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
449 cache don't get ReservedInstruction traps.
450
c2d11a7d
JM		 4511999-11-29 Mark Salter <msalter@cygnus.com>
452
453 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
454 to clear status bits in sdisr register. This is how the hardware works.
455
456 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
457 being used by cygmon.
458
4ce44c66
JM		 4591999-11-11 Andrew Haley <aph@cygnus.com>
460
461 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
462 instructions.
463
cff3e48b
JM		 464Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
465
466 * mips.igen (MULT): Correct previous mis-applied patch.
467
d4f3574e
SS		 468Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
469
470 * mips.igen (delayslot32): Handle sequence like
471 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
472 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
473 (MULT): Actually pass the third register...
474
4751999-09-03 Mark Salter <msalter@cygnus.com>
476
477 * interp.c (sim_open): Added more memory aliases for additional
478 hardware being touched by cygmon on jmr3904 board.
479
480Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
481
482 * configure: Regenerated to track ../common/aclocal.m4 changes.
483
a0b3c4fd
JM		 484Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
485
486 * interp.c (sim_store_register): Handle case where client - GDB -
487 specifies that a 4 byte register is 8 bytes in size.
488 (sim_fetch_register): Ditto.
489
adf40b2e
JM		 4901999-07-14 Frank Ch. Eigler <fche@cygnus.com>
491
492 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
493 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
494 (idt_monitor_base): Base address for IDT monitor traps.
495 (pmon_monitor_base): Ditto for PMON.
496 (lsipmon_monitor_base): Ditto for LSI PMON.
497 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
498 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
499 (sim_firmware_command): New function.
500 (mips_option_handler): Call it for OPTION_FIRMWARE.
501 (sim_open): Allocate memory for idt_monitor region. If "--board"
502 option was given, add no monitor by default. Add BREAK hooks only if
503 monitors are also there.
504
43e526b9
JM		 505Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
506
507 * interp.c (sim_monitor): Flush output before reading input.
508
509Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
510
511 * tconfig.in (SIM_HANDLES_LMA): Always define.
512
513Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
514
515 From Mark Salter <msalter@cygnus.com>:
516 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
517 (sim_open): Add setup for BSP board.
518
9846de1b
JM		 519Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
520
521 * mips.igen (MULT, MULTU): Add syntax for two operand version.
522 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
523 them as unimplemented.
524
cd0fc7c3
SS		 5251999-05-08 Felix Lee <flee@cygnus.com>
526
527 * configure: Regenerated to track ../common/aclocal.m4 changes.
528
7a292a7a
SS		 5291999-04-21 Frank Ch. Eigler <fche@cygnus.com>
530
531 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
532
533Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
534
535 * configure.in: Any mips64vr5*-*-* target should have
536 -DTARGET_ENABLE_FR=1.
537 (default_endian): Any mips64vr*el-*-* target should default to
538 LITTLE_ENDIAN.
539 * configure: Re-generate.
540
5411999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
542
543 * mips.igen (ldl): Extend from _16_, not 32.
544
545Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
546
547 * interp.c (sim_store_register): Force registers written to by GDB
548 into an un-interpreted state.
549
c906108c
SS		 5501999-02-05 Frank Ch. Eigler <fche@cygnus.com>
551
552 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
553 CPU, start periodic background I/O polls.
554 (tx3904sio_poll): New function: periodic I/O poller.
555
5561998-12-30 Frank Ch. Eigler <fche@cygnus.com>
557
558 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
559
560Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
561
562 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
563 case statement.
564
5651998-12-29 Frank Ch. Eigler <fche@cygnus.com>
566
567 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
568 (load_word): Call SIM_CORE_SIGNAL hook on error.
569 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
570 starting. For exception dispatching, pass PC instead of NULL_CIA.
571 (decode_coproc): Use COP0_BADVADDR to store faulting address.
572 * sim-main.h (COP0_BADVADDR): Define.
573 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
574 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
575 (_sim_cpu): Add exc_* fields to store register value snapshots.
576 * mips.igen (*): Replace memory-related SignalException* calls
577 with references to SIM_CORE_SIGNAL hook.
578
579 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
580 fix.
581 * sim-main.c (*): Minor warning cleanups.
582
5831998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
584
585 * m16.igen (DADDIU5): Correct type-o.
586
587Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
588
589 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
590 variables.
591
592Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
593
594 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
595 to include path.
596 (interp.o): Add dependency on itable.h
597 (oengine.c, gencode): Delete remaining references.
598 (BUILT_SRC_FROM_GEN): Clean up.
599
6001998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
601
602 * vr4run.c: New.
603 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
604 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
605 tmp-run-hack) : New.
606 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
607 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
608 Drop the "64" qualifier to get the HACK generator working.
609 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
610 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
611 qualifier to get the hack generator working.
612 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
613 (DSLL): Use do_dsll.
614 (DSLLV): Use do_dsllv.
615 (DSRA): Use do_dsra.
616 (DSRL): Use do_dsrl.
617 (DSRLV): Use do_dsrlv.
618 (BC1): Move *vr4100 to get the HACK generator working.
619 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
620 get the HACK generator working.
621 (MACC) Rename to get the HACK generator working.
622 (DMACC,MACCS,DMACCS): Add the 64.
623
6241998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
625
626 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
627 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
628
6291998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
630
631 * mips/interp.c (DEBUG): Cleanups.
632
6331998-12-10 Frank Ch. Eigler <fche@cygnus.com>
634
635 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
636 (tx3904sio_tickle): fflush after a stdout character output.
637
6381998-12-03 Frank Ch. Eigler <fche@cygnus.com>
639
640 * interp.c (sim_close): Uninstall modules.
641
642Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
643
644 * sim-main.h, interp.c (sim_monitor): Change to global
645 function.
646
647Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
648
649 * configure.in (vr4100): Only include vr4100 instructions in
650 simulator.
651 * configure: Re-generate.
652 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
653
654Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
655
656 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
657 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
658 true alternative.
659
660 * configure.in (sim_default_gen, sim_use_gen): Replace with
661 sim_gen.
662 (--enable-sim-igen): Delete config option. Always using IGEN.
663 * configure: Re-generate.
664
665 * Makefile.in (gencode): Kill, kill, kill.
666 * gencode.c: Ditto.
667
668Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
669
670 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
671 bit mips16 igen simulator.
672 * configure: Re-generate.
673
674 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
675 as part of vr4100 ISA.
676 * vr.igen: Mark all instructions as 64 bit only.
677
678Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
679
680 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
681 Pacify GCC.
682
683Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
684
685 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
686 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
687 * configure: Re-generate.
688
689 * m16.igen (BREAK): Define breakpoint instruction.
690 (JALX32): Mark instruction as mips16 and not r3900.
691 * mips.igen (C.cond.fmt): Fix typo in instruction format.
692
693 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
694
695Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
696
697 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
698 insn as a debug breakpoint.
699
700 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
701 pending.slot_size.
702 (PENDING_SCHED): Clean up trace statement.
703 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
704 (PENDING_FILL): Delay write by only one cycle.
705 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
706
707 * sim-main.c (pending_tick): Clean up trace statements. Add trace
708 of pending writes.
709 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
710 32 & 64.
711 (pending_tick): Move incrementing of index to FOR statement.
712 (pending_tick): Only update PENDING_OUT after a write has occured.
713
714 * configure.in: Add explicit mips-lsi-* target. Use gencode to
715 build simulator.
716 * configure: Re-generate.
717
718 * interp.c (sim_engine_run OLD): Delete explicit call to
719 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
720
721Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
722
723 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
724 interrupt level number to match changed SignalExceptionInterrupt
725 macro.
726
727Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
728
729 * interp.c: #include "itable.h" if WITH_IGEN.
730 (get_insn_name): New function.
731 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
732 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
733
734Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
735
736 * configure: Rebuilt to inhale new common/aclocal.m4.
737
738Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
739
740 * dv-tx3904sio.c: Include sim-assert.h.
741
742Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
743
744 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
745 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
746 Reorganize target-specific sim-hardware checks.
747 * configure: rebuilt.
748 * interp.c (sim_open): For tx39 target boards, set
749 OPERATING_ENVIRONMENT, add tx3904sio devices.
750 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
751 ROM executables. Install dv-sockser into sim-modules list.
752
753 * dv-tx3904irc.c: Compiler warning clean-up.
754 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
755 frequent hw-trace messages.
756
757Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
758
759 * vr.igen (MulAcc): Identify as a vr4100 specific function.
760
761Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
762
763 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
764
765 * vr.igen: New file.
766 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
767 * mips.igen: Define vr4100 model. Include vr.igen.
768Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
769
770 * mips.igen (check_mf_hilo): Correct check.
771
772Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
773
774 * sim-main.h (interrupt_event): Add prototype.
775
776 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
777 register_ptr, register_value.
778 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
779
780 * sim-main.h (tracefh): Make extern.
781
782Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
783
784 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
785 Reduce unnecessarily high timer event frequency.
786 * dv-tx3904cpu.c: Ditto for interrupt event.
787
788Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
789
790 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
791 to allay warnings.
792 (interrupt_event): Made non-static.
793
794 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
795 interchange of configuration values for external vs. internal
796 clock dividers.
797
798Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
799
800 * mips.igen (BREAK): Moved code to here for
801 simulator-reserved break instructions.
802 * gencode.c (build_instruction): Ditto.
803 * interp.c (signal_exception): Code moved from here. Non-
804 reserved instructions now use exception vector, rather
805 than halting sim.
806 * sim-main.h: Moved magic constants to here.
807
808Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
809
810 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
811 register upon non-zero interrupt event level, clear upon zero
812 event value.
813 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
814 by passing zero event value.
815 (*_io_{read,write}_buffer): Endianness fixes.
816 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
817 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
818
819 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
820 serial I/O and timer module at base address 0xFFFF0000.
821
822Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
823
824 * mips.igen (SWC1) : Correct the handling of ReverseEndian
825 and BigEndianCPU.
826
827Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
828
829 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
830 parts.
831 * configure: Update.
832
833Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
834
835 * dv-tx3904tmr.c: New file - implements tx3904 timer.
836 * dv-tx3904{irc,cpu}.c: Mild reformatting.
837 * configure.in: Include tx3904tmr in hw_device list.
838 * configure: Rebuilt.
839 * interp.c (sim_open): Instantiate three timer instances.
840 Fix address typo of tx3904irc instance.
841
842Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
843
844 * interp.c (signal_exception): SystemCall exception now uses
845 the exception vector.
846
847Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
848
849 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
850 to allay warnings.
851
852Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
853
854 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
855
856Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
857
858 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
859
860 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
861 sim-main.h. Declare a struct hw_descriptor instead of struct
862 hw_device_descriptor.
863
864Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
865
866 * mips.igen (do_store_left, do_load_left): Compute nr of left and
867 right bits and then re-align left hand bytes to correct byte
868 lanes. Fix incorrect computation in do_store_left when loading
869 bytes from second word.
870
871Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
872
873 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
874 * interp.c (sim_open): Only create a device tree when HW is
875 enabled.
876
877 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
878 * interp.c (signal_exception): Ditto.
879
880Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
881
882 * gencode.c: Mark BEGEZALL as LIKELY.
883
884Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
885
886 * sim-main.h (ALU32_END): Sign extend 32 bit results.
887 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
888
889Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
890
891 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
892 modules. Recognize TX39 target with "mips*tx39" pattern.
893 * configure: Rebuilt.
894 * sim-main.h (*): Added many macros defining bits in
895 TX39 control registers.
896 (SignalInterrupt): Send actual PC instead of NULL.
897 (SignalNMIReset): New exception type.
898 * interp.c (board): New variable for future use to identify
899 a particular board being simulated.
900 (mips_option_handler,mips_options): Added "--board" option.
901 (interrupt_event): Send actual PC.
902 (sim_open): Make memory layout conditional on board setting.
903 (signal_exception): Initial implementation of hardware interrupt
904 handling. Accept another break instruction variant for simulator
905 exit.
906 (decode_coproc): Implement RFE instruction for TX39.
907 (mips.igen): Decode RFE instruction as such.
908 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
909 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
910 bbegin to implement memory map.
911 * dv-tx3904cpu.c: New file.
912 * dv-tx3904irc.c: New file.
913
914Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
915
916 * mips.igen (check_mt_hilo): Create a separate r3900 version.
917
918Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
919
920 * tx.igen (madd,maddu): Replace calls to check_op_hilo
921 with calls to check_div_hilo.
922
923Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
924
925 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
926 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
927 Add special r3900 version of do_mult_hilo.
928 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
929 with calls to check_mult_hilo.
930 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
931 with calls to check_div_hilo.
932
933Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
934
935 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
936 Document a replacement.
937
938Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
939
940 * interp.c (sim_monitor): Make mon_printf work.
941
942Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
943
944 * sim-main.h (INSN_NAME): New arg `cpu'.
945
946Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
947
948 * configure: Regenerated to track ../common/aclocal.m4 changes.
949
950Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
951
952 * configure: Regenerated to track ../common/aclocal.m4 changes.
953 * config.in: Ditto.
954
955Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
956
957 * acconfig.h: New file.
958 * configure.in: Reverted change of Apr 24; use sinclude again.
959
960Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
961
962 * configure: Regenerated to track ../common/aclocal.m4 changes.
963 * config.in: Ditto.
964
965Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
966
967 * configure.in: Don't call sinclude.
968
969Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
970
971 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
972
973Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
974
975 * mips.igen (ERET): Implement.
976
977 * interp.c (decode_coproc): Return sign-extended EPC.
978
979 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
980
981 * interp.c (signal_exception): Do not ignore Trap.
982 (signal_exception): On TRAP, restart at exception address.
983 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
984 (signal_exception): Update.
985 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
986 so that TRAP instructions are caught.
987
988Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
989
990 * sim-main.h (struct hilo_access, struct hilo_history): Define,
991 contains HI/LO access history.
992 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
993 (HIACCESS, LOACCESS): Delete, replace with
994 (HIHISTORY, LOHISTORY): New macros.
995 (CHECKHILO): Delete all, moved to mips.igen
996
997 * gencode.c (build_instruction): Do not generate checks for
998 correct HI/LO register usage.
999
1000 * interp.c (old_engine_run): Delete checks for correct HI/LO
1001 register usage.
1002
1003 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1004 check_mf_cycles): New functions.
1005 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1006 do_divu, domultx, do_mult, do_multu): Use.
1007
1008 * tx.igen ("madd", "maddu"): Use.
1009
1010Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1011
1012 * mips.igen (DSRAV): Use function do_dsrav.
1013 (SRAV): Use new function do_srav.
1014
1015 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1016 (B): Sign extend 11 bit immediate.
1017 (EXT-B*): Shift 16 bit immediate left by 1.
1018 (ADDIU*): Don't sign extend immediate value.
1019
1020Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1021
1022 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1023
1024 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1025 functions.
1026
1027 * mips.igen (delayslot32, nullify_next_insn): New functions.
1028 (m16.igen): Always include.
1029 (do_*): Add more tracing.
1030
1031 * m16.igen (delayslot16): Add NIA argument, could be called by a
1032 32 bit MIPS16 instruction.
1033
1034 * interp.c (ifetch16): Move function from here.
1035 * sim-main.c (ifetch16): To here.
1036
1037 * sim-main.c (ifetch16, ifetch32): Update to match current
1038 implementations of LH, LW.
1039 (signal_exception): Don't print out incorrect hex value of illegal
1040 instruction.
1041
1042Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1043
1044 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1045 instruction.
1046
1047 * m16.igen: Implement MIPS16 instructions.
1048
1049 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1050 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1051 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1052 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1053 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1054 bodies of corresponding code from 32 bit insn to these. Also used
1055 by MIPS16 versions of functions.
1056
1057 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1058 (IMEM16): Drop NR argument from macro.
1059
1060Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1061
1062 * Makefile.in (SIM_OBJS): Add sim-main.o.
1063
1064 * sim-main.h (address_translation, load_memory, store_memory,
1065 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1066 as INLINE_SIM_MAIN.
1067 (pr_addr, pr_uword64): Declare.
1068 (sim-main.c): Include when H_REVEALS_MODULE_P.
1069
1070 * interp.c (address_translation, load_memory, store_memory,
1071 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1072 from here.
1073 * sim-main.c: To here. Fix compilation problems.
1074
1075 * configure.in: Enable inlining.
1076 * configure: Re-config.
1077
1078Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1079
1080 * configure: Regenerated to track ../common/aclocal.m4 changes.
1081
1082Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1083
1084 * mips.igen: Include tx.igen.
1085 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1086 * tx.igen: New file, contains MADD and MADDU.
1087
1088 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1089 the hardwired constant `7'.
1090 (store_memory): Ditto.
1091 (LOADDRMASK): Move definition to sim-main.h.
1092
1093 mips.igen (MTC0): Enable for r3900.
1094 (ADDU): Add trace.
1095
1096 mips.igen (do_load_byte): Delete.
1097 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1098 do_store_right): New functions.
1099 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1100
1101 configure.in: Let the tx39 use igen again.
1102 configure: Update.
1103
1104Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1105
1106 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1107 not an address sized quantity. Return zero for cache sizes.
1108
1109Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1110
1111 * mips.igen (r3900): r3900 does not support 64 bit integer
1112 operations.
1113
1114Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1115
1116 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1117 than igen one.
1118 * configure : Rebuild.
1119
1120Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1121
1122 * configure: Regenerated to track ../common/aclocal.m4 changes.
1123
1124Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1125
1126 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1127
1128Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1129
1130 * configure: Regenerated to track ../common/aclocal.m4 changes.
1131 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1132
1133Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1134
1135 * configure: Regenerated to track ../common/aclocal.m4 changes.
1136
1137Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1138
1139 * interp.c (Max, Min): Comment out functions. Not yet used.
1140
1141Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1142
1143 * configure: Regenerated to track ../common/aclocal.m4 changes.
1144
1145Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1146
1147 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1148 configurable settings for stand-alone simulator.
1149
1150 * configure.in: Added X11 search, just in case.
1151
1152 * configure: Regenerated.
1153
1154Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1155
1156 * interp.c (sim_write, sim_read, load_memory, store_memory):
1157 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1158
1159Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1160
1161 * sim-main.h (GETFCC): Return an unsigned value.
1162
1163Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1164
1165 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1166 (DADD): Result destination is RD not RT.
1167
1168Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1169
1170 * sim-main.h (HIACCESS, LOACCESS): Always define.
1171
1172 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1173
1174 * interp.c (sim_info): Delete.
1175
1176Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1177
1178 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1179 (mips_option_handler): New argument `cpu'.
1180 (sim_open): Update call to sim_add_option_table.
1181
1182Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1183
1184 * mips.igen (CxC1): Add tracing.
1185
1186Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1187
1188 * sim-main.h (Max, Min): Declare.
1189
1190 * interp.c (Max, Min): New functions.
1191
1192 * mips.igen (BC1): Add tracing.
1193
1194Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1195
1196 * interp.c Added memory map for stack in vr4100
1197
1198Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1199
1200 * interp.c (load_memory): Add missing "break"'s.
1201
1202Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1203
1204 * interp.c (sim_store_register, sim_fetch_register): Pass in
1205 length parameter. Return -1.
1206
1207Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1208
1209 * interp.c: Added hardware init hook, fixed warnings.
1210
1211Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1212
1213 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1214
1215Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1216
1217 * interp.c (ifetch16): New function.
1218
1219 * sim-main.h (IMEM32): Rename IMEM.
1220 (IMEM16_IMMED): Define.
1221 (IMEM16): Define.
1222 (DELAY_SLOT): Update.
1223
1224 * m16run.c (sim_engine_run): New file.
1225
1226 * m16.igen: All instructions except LB.
1227 (LB): Call do_load_byte.
1228 * mips.igen (do_load_byte): New function.
1229 (LB): Call do_load_byte.
1230
1231 * mips.igen: Move spec for insn bit size and high bit from here.
1232 * Makefile.in (tmp-igen, tmp-m16): To here.
1233
1234 * m16.dc: New file, decode mips16 instructions.
1235
1236 * Makefile.in (SIM_NO_ALL): Define.
1237 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1238
1239Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1240
1241 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1242 point unit to 32 bit registers.
1243 * configure: Re-generate.
1244
1245Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1246
1247 * configure.in (sim_use_gen): Make IGEN the default simulator
1248 generator for generic 32 and 64 bit mips targets.
1249 * configure: Re-generate.
1250
1251Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1252
1253 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1254 bitsize.
1255
1256 * interp.c (sim_fetch_register, sim_store_register): Read/write
1257 FGR from correct location.
1258 (sim_open): Set size of FGR's according to
1259 WITH_TARGET_FLOATING_POINT_BITSIZE.
1260
1261 * sim-main.h (FGR): Store floating point registers in a separate
1262 array.
1263
1264Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1265
1266 * configure: Regenerated to track ../common/aclocal.m4 changes.
1267
1268Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1269
1270 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1271
1272 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1273
1274 * interp.c (pending_tick): New function. Deliver pending writes.
1275
1276 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1277 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1278 it can handle mixed sized quantites and single bits.
1279
1280Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1281
1282 * interp.c (oengine.h): Do not include when building with IGEN.
1283 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1284 (sim_info): Ditto for PROCESSOR_64BIT.
1285 (sim_monitor): Replace ut_reg with unsigned_word.
1286 (*): Ditto for t_reg.
1287 (LOADDRMASK): Define.
1288 (sim_open): Remove defunct check that host FP is IEEE compliant,
1289 using software to emulate floating point.
1290 (value_fpr, ...): Always compile, was conditional on HASFPU.
1291
1292Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1293
1294 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1295 size.
1296
1297 * interp.c (SD, CPU): Define.
1298 (mips_option_handler): Set flags in each CPU.
1299 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1300 (sim_close): Do not clear STATE, deleted anyway.
1301 (sim_write, sim_read): Assume CPU zero's vm should be used for
1302 data transfers.
1303 (sim_create_inferior): Set the PC for all processors.
1304 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1305 argument.
1306 (mips16_entry): Pass correct nr of args to store_word, load_word.
1307 (ColdReset): Cold reset all cpu's.
1308 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1309 (sim_monitor, load_memory, store_memory, signal_exception): Use
1310 `CPU' instead of STATE_CPU.
1311
1312
1313 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1314 SD or CPU_.
1315
1316 * sim-main.h (signal_exception): Add sim_cpu arg.
1317 (SignalException*): Pass both SD and CPU to signal_exception.
1318 * interp.c (signal_exception): Update.
1319
1320 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1321 Ditto
1322 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1323 address_translation): Ditto
1324 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1325
1326Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1327
1328 * configure: Regenerated to track ../common/aclocal.m4 changes.
1329
1330Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1331
1332 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1333
1334 * mips.igen (model): Map processor names onto BFD name.
1335
1336 * sim-main.h (CPU_CIA): Delete.
1337 (SET_CIA, GET_CIA): Define
1338
1339Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1340
1341 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1342 regiser.
1343
1344 * configure.in (default_endian): Configure a big-endian simulator
1345 by default.
1346 * configure: Re-generate.
1347
1348Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1349
1350 * configure: Regenerated to track ../common/aclocal.m4 changes.
1351
1352Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1353
1354 * interp.c (sim_monitor): Handle Densan monitor outbyte
1355 and inbyte functions.
1356
13571997-12-29 Felix Lee <flee@cygnus.com>
1358
1359 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1360
1361Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1362
1363 * Makefile.in (tmp-igen): Arrange for $zero to always be
1364 reset to zero after every instruction.
1365
1366Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1367
1368 * configure: Regenerated to track ../common/aclocal.m4 changes.
1369 * config.in: Ditto.
1370
1371Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1372
1373 * mips.igen (MSUB): Fix to work like MADD.
1374 * gencode.c (MSUB): Similarly.
1375
1376Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1377
1378 * configure: Regenerated to track ../common/aclocal.m4 changes.
1379
1380Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1381
1382 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1383
1384Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1385
1386 * sim-main.h (sim-fpu.h): Include.
1387
1388 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1389 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1390 using host independant sim_fpu module.
1391
1392Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1393
1394 * interp.c (signal_exception): Report internal errors with SIGABRT
1395 not SIGQUIT.
1396
1397 * sim-main.h (C0_CONFIG): New register.
1398 (signal.h): No longer include.
1399
1400 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1401
1402Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1403
1404 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1405
1406Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1407
1408 * mips.igen: Tag vr5000 instructions.
1409 (ANDI): Was missing mipsIV model, fix assembler syntax.
1410 (do_c_cond_fmt): New function.
1411 (C.cond.fmt): Handle mips I-III which do not support CC field
1412 separatly.
1413 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1414 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1415 in IV3.2 spec.
1416 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1417 vr5000 which saves LO in a GPR separatly.
1418
1419 * configure.in (enable-sim-igen): For vr5000, select vr5000
1420 specific instructions.
1421 * configure: Re-generate.
1422
1423Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1424
1425 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1426
1427 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1428 fmt_uninterpreted_64 bit cases to switch. Convert to
1429 fmt_formatted,
1430
1431 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1432
1433 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1434 as specified in IV3.2 spec.
1435 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1436
1437Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1438
1439 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1440 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1441 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1442 PENDING_FILL versions of instructions. Simplify.
1443 (X): New function.
1444 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1445 instructions.
1446 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1447 a signed value.
1448 (MTHI, MFHI): Disable code checking HI-LO.
1449
1450 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1451 global.
1452 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1453
1454Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1455
1456 * gencode.c (build_mips16_operands): Replace IPC with cia.
1457
1458 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1459 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1460 IPC to `cia'.
1461 (UndefinedResult): Replace function with macro/function
1462 combination.
1463 (sim_engine_run): Don't save PC in IPC.
1464
1465 * sim-main.h (IPC): Delete.
1466
1467
1468 * interp.c (signal_exception, store_word, load_word,
1469 address_translation, load_memory, store_memory, cache_op,
1470 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1471 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1472 current instruction address - cia - argument.
1473 (sim_read, sim_write): Call address_translation directly.
1474 (sim_engine_run): Rename variable vaddr to cia.
1475 (signal_exception): Pass cia to sim_monitor
1476
1477 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1478 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1479 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1480
1481 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1482 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1483 SIM_ASSERT.
1484
1485 * interp.c (signal_exception): Pass restart address to
1486 sim_engine_restart.
1487
1488 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1489 idecode.o): Add dependency.
1490
1491 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1492 Delete definitions
1493 (DELAY_SLOT): Update NIA not PC with branch address.
1494 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1495
1496 * mips.igen: Use CIA not PC in branch calculations.
1497 (illegal): Call SignalException.
1498 (BEQ, ADDIU): Fix assembler.
1499
1500Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1501
1502 * m16.igen (JALX): Was missing.
1503
1504 * configure.in (enable-sim-igen): New configuration option.
1505 * configure: Re-generate.
1506
1507 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1508
1509 * interp.c (load_memory, store_memory): Delete parameter RAW.
1510 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1511 bypassing {load,store}_memory.
1512
1513 * sim-main.h (ByteSwapMem): Delete definition.
1514
1515 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1516
1517 * interp.c (sim_do_command, sim_commands): Delete mips specific
1518 commands. Handled by module sim-options.
1519
1520 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1521 (WITH_MODULO_MEMORY): Define.
1522
1523 * interp.c (sim_info): Delete code printing memory size.
1524
1525 * interp.c (mips_size): Nee sim_size, delete function.
1526 (power2): Delete.
1527 (monitor, monitor_base, monitor_size): Delete global variables.
1528 (sim_open, sim_close): Delete code creating monitor and other
1529 memory regions. Use sim-memopts module, via sim_do_commandf, to
1530 manage memory regions.
1531 (load_memory, store_memory): Use sim-core for memory model.
1532
1533 * interp.c (address_translation): Delete all memory map code
1534 except line forcing 32 bit addresses.
1535
1536Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1537
1538 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1539 trace options.
1540
1541 * interp.c (logfh, logfile): Delete globals.
1542 (sim_open, sim_close): Delete code opening & closing log file.
1543 (mips_option_handler): Delete -l and -n options.
1544 (OPTION mips_options): Ditto.
1545
1546 * interp.c (OPTION mips_options): Rename option trace to dinero.
1547 (mips_option_handler): Update.
1548
1549Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1550
1551 * interp.c (fetch_str): New function.
1552 (sim_monitor): Rewrite using sim_read & sim_write.
1553 (sim_open): Check magic number.
1554 (sim_open): Write monitor vectors into memory using sim_write.
1555 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1556 (sim_read, sim_write): Simplify - transfer data one byte at a
1557 time.
1558 (load_memory, store_memory): Clarify meaning of parameter RAW.
1559
1560 * sim-main.h (isHOST): Defete definition.
1561 (isTARGET): Mark as depreciated.
1562 (address_translation): Delete parameter HOST.
1563
1564 * interp.c (address_translation): Delete parameter HOST.
1565
1566Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1567
1568 * mips.igen:
1569
1570 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1571 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1572
1573Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1574
1575 * mips.igen: Add model filter field to records.
1576
1577Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1578
1579 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1580
1581 interp.c (sim_engine_run): Do not compile function sim_engine_run
1582 when WITH_IGEN == 1.
1583
1584 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1585 target architecture.
1586
1587 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1588 igen. Replace with configuration variables sim_igen_flags /
1589 sim_m16_flags.
1590
1591 * m16.igen: New file. Copy mips16 insns here.
1592 * mips.igen: From here.
1593
1594Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1595
1596 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1597 to top.
1598 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1599
1600Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1601
1602 * gencode.c (build_instruction): Follow sim_write's lead in using
1603 BigEndianMem instead of !ByteSwapMem.
1604
1605Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1606
1607 * configure.in (sim_gen): Dependent on target, select type of
1608 generator. Always select old style generator.
1609
1610 configure: Re-generate.
1611
1612 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1613 targets.
1614 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1615 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1616 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1617 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1618 SIM_@sim_gen@_*, set by autoconf.
1619
1620Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1621
1622 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1623
1624 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1625 CURRENT_FLOATING_POINT instead.
1626
1627 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1628 (address_translation): Raise exception InstructionFetch when
1629 translation fails and isINSTRUCTION.
1630
1631 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1632 sim_engine_run): Change type of of vaddr and paddr to
1633 address_word.
1634 (address_translation, prefetch, load_memory, store_memory,
1635 cache_op): Change type of vAddr and pAddr to address_word.
1636
1637 * gencode.c (build_instruction): Change type of vaddr and paddr to
1638 address_word.
1639
1640Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641
1642 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1643 macro to obtain result of ALU op.
1644
1645Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1646
1647 * interp.c (sim_info): Call profile_print.
1648
1649Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1652
1653 * sim-main.h (WITH_PROFILE): Do not define, defined in
1654 common/sim-config.h. Use sim-profile module.
1655 (simPROFILE): Delete defintion.
1656
1657 * interp.c (PROFILE): Delete definition.
1658 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1659 (sim_close): Delete code writing profile histogram.
1660 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1661 Delete.
1662 (sim_engine_run): Delete code profiling the PC.
1663
1664Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1665
1666 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1667
1668 * interp.c (sim_monitor): Make register pointers of type
1669 unsigned_word*.
1670
1671 * sim-main.h: Make registers of type unsigned_word not
1672 signed_word.
1673
1674Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1675
1676 * interp.c (sync_operation): Rename from SyncOperation, make
1677 global, add SD argument.
1678 (prefetch): Rename from Prefetch, make global, add SD argument.
1679 (decode_coproc): Make global.
1680
1681 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1682
1683 * gencode.c (build_instruction): Generate DecodeCoproc not
1684 decode_coproc calls.
1685
1686 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1687 (SizeFGR): Move to sim-main.h
1688 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1689 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1690 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1691 sim-main.h.
1692 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1693 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1694 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1695 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1696 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1697 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1698
1699 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1700 exception.
1701 (sim-alu.h): Include.
1702 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1703 (sim_cia): Typedef to instruction_address.
1704
1705Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1706
1707 * Makefile.in (interp.o): Rename generated file engine.c to
1708 oengine.c.
1709
1710 * interp.c: Update.
1711
1712Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1713
1714 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1715
1716Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1717
1718 * gencode.c (build_instruction): For "FPSQRT", output correct
1719 number of arguments to Recip.
1720
1721Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1722
1723 * Makefile.in (interp.o): Depends on sim-main.h
1724
1725 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1726
1727 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1728 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1729 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1730 STATE, DSSTATE): Define
1731 (GPR, FGRIDX, ..): Define.
1732
1733 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1734 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1735 (GPR, FGRIDX, ...): Delete macros.
1736
1737 * interp.c: Update names to match defines from sim-main.h
1738
1739Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1740
1741 * interp.c (sim_monitor): Add SD argument.
1742 (sim_warning): Delete. Replace calls with calls to
1743 sim_io_eprintf.
1744 (sim_error): Delete. Replace calls with sim_io_error.
1745 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1746 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1747 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1748 argument.
1749 (mips_size): Rename from sim_size. Add SD argument.
1750
1751 * interp.c (simulator): Delete global variable.
1752 (callback): Delete global variable.
1753 (mips_option_handler, sim_open, sim_write, sim_read,
1754 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1755 sim_size,sim_monitor): Use sim_io_* not callback->*.
1756 (sim_open): ZALLOC simulator struct.
1757 (PROFILE): Do not define.
1758
1759Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1760
1761 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1762 support.h with corresponding code.
1763
1764 * sim-main.h (word64, uword64), support.h: Move definition to
1765 sim-main.h.
1766 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1767
1768 * support.h: Delete
1769 * Makefile.in: Update dependencies
1770 * interp.c: Do not include.
1771
1772Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1773
1774 * interp.c (address_translation, load_memory, store_memory,
1775 cache_op): Rename to from AddressTranslation et.al., make global,
1776 add SD argument
1777
1778 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1779 CacheOp): Define.
1780
1781 * interp.c (SignalException): Rename to signal_exception, make
1782 global.
1783
1784 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1785
1786 * sim-main.h (SignalException, SignalExceptionInterrupt,
1787 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1788 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1789 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1790 Define.
1791
1792 * interp.c, support.h: Use.
1793
1794Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1795
1796 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1797 to value_fpr / store_fpr. Add SD argument.
1798 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1799 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1800
1801 * sim-main.h (ValueFPR, StoreFPR): Define.
1802
1803Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1804
1805 * interp.c (sim_engine_run): Check consistency between configure
1806 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1807 and HASFPU.
1808
1809 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1810 (mips_fpu): Configure WITH_FLOATING_POINT.
1811 (mips_endian): Configure WITH_TARGET_ENDIAN.
1812 * configure: Update.
1813
1814Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1815
1816 * configure: Regenerated to track ../common/aclocal.m4 changes.
1817
1818Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1819
1820 * configure: Regenerated.
1821
1822Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1823
1824 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1825
1826Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1827
1828 * gencode.c (print_igen_insn_models): Assume certain architectures
1829 include all mips* instructions.
1830 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1831 instruction.
1832
1833 * Makefile.in (tmp.igen): Add target. Generate igen input from
1834 gencode file.
1835
1836 * gencode.c (FEATURE_IGEN): Define.
1837 (main): Add --igen option. Generate output in igen format.
1838 (process_instructions): Format output according to igen option.
1839 (print_igen_insn_format): New function.
1840 (print_igen_insn_models): New function.
1841 (process_instructions): Only issue warnings and ignore
1842 instructions when no FEATURE_IGEN.
1843
1844Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1845
1846 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1847 MIPS targets.
1848
1849Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1850
1851 * configure: Regenerated to track ../common/aclocal.m4 changes.
1852
1853Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1856 SIM_RESERVED_BITS): Delete, moved to common.
1857 (SIM_EXTRA_CFLAGS): Update.
1858
1859Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1860
1861 * configure.in: Configure non-strict memory alignment.
1862 * configure: Regenerated to track ../common/aclocal.m4 changes.
1863
1864Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1865
1866 * configure: Regenerated to track ../common/aclocal.m4 changes.
1867
1868Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1869
1870 * gencode.c (SDBBP,DERET): Added (3900) insns.
1871 (RFE): Turn on for 3900.
1872 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1873 (dsstate): Made global.
1874 (SUBTARGET_R3900): Added.
1875 (CANCELDELAYSLOT): New.
1876 (SignalException): Ignore SystemCall rather than ignore and
1877 terminate. Add DebugBreakPoint handling.
1878 (decode_coproc): New insns RFE, DERET; and new registers Debug
1879 and DEPC protected by SUBTARGET_R3900.
1880 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1881 bits explicitly.
1882 * Makefile.in,configure.in: Add mips subtarget option.
1883 * configure: Update.
1884
1885Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1886
1887 * gencode.c: Add r3900 (tx39).
1888
1889
1890Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1891
1892 * gencode.c (build_instruction): Don't need to subtract 4 for
1893 JALR, just 2.
1894
1895Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1896
1897 * interp.c: Correct some HASFPU problems.
1898
1899Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1900
1901 * configure: Regenerated to track ../common/aclocal.m4 changes.
1902
1903Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1904
1905 * interp.c (mips_options): Fix samples option short form, should
1906 be `x'.
1907
1908Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1909
1910 * interp.c (sim_info): Enable info code. Was just returning.
1911
1912Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1913
1914 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1915 MFC0.
1916
1917Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1918
1919 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1920 constants.
1921 (build_instruction): Ditto for LL.
1922
1923Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1924
1925 * configure: Regenerated to track ../common/aclocal.m4 changes.
1926
1927Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1928
1929 * configure: Regenerated to track ../common/aclocal.m4 changes.
1930 * config.in: Ditto.
1931
1932Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1933
1934 * interp.c (sim_open): Add call to sim_analyze_program, update
1935 call to sim_config.
1936
1937Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1938
1939 * interp.c (sim_kill): Delete.
1940 (sim_create_inferior): Add ABFD argument. Set PC from same.
1941 (sim_load): Move code initializing trap handlers from here.
1942 (sim_open): To here.
1943 (sim_load): Delete, use sim-hload.c.
1944
1945 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1946
1947Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1948
1949 * configure: Regenerated to track ../common/aclocal.m4 changes.
1950 * config.in: Ditto.
1951
1952Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1953
1954 * interp.c (sim_open): Add ABFD argument.
1955 (sim_load): Move call to sim_config from here.
1956 (sim_open): To here. Check return status.
1957
1958Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1959
1960 * gencode.c (build_instruction): Two arg MADD should
1961 not assign result to $0.
1962
1963Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1964
1965 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1966 * sim/mips/configure.in: Regenerate.
1967
1968Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1969
1970 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1971 signed8, unsigned8 et.al. types.
1972
1973 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1974 hosts when selecting subreg.
1975
1976Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1977
1978 * interp.c (sim_engine_run): Reset the ZERO register to zero
1979 regardless of FEATURE_WARN_ZERO.
1980 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1981
1982Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1983
1984 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1985 (SignalException): For BreakPoints ignore any mode bits and just
1986 save the PC.
1987 (SignalException): Always set the CAUSE register.
1988
1989Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1990
1991 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1992 exception has been taken.
1993
1994 * interp.c: Implement the ERET and mt/f sr instructions.
1995
1996Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1997
1998 * interp.c (SignalException): Don't bother restarting an
1999 interrupt.
2000
2001Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2002
2003 * interp.c (SignalException): Really take an interrupt.
2004 (interrupt_event): Only deliver interrupts when enabled.
2005
2006Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2007
2008 * interp.c (sim_info): Only print info when verbose.
2009 (sim_info) Use sim_io_printf for output.
2010
2011Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2012
2013 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2014 mips architectures.
2015
2016Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2017
2018 * interp.c (sim_do_command): Check for common commands if a
2019 simulator specific command fails.
2020
2021Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2022
2023 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2024 and simBE when DEBUG is defined.
2025
2026Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2027
2028 * interp.c (interrupt_event): New function. Pass exception event
2029 onto exception handler.
2030
2031 * configure.in: Check for stdlib.h.
2032 * configure: Regenerate.
2033
2034 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2035 variable declaration.
2036 (build_instruction): Initialize memval1.
2037 (build_instruction): Add UNUSED attribute to byte, bigend,
2038 reverse.
2039 (build_operands): Ditto.
2040
2041 * interp.c: Fix GCC warnings.
2042 (sim_get_quit_code): Delete.
2043
2044 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2045 * Makefile.in: Ditto.
2046 * configure: Re-generate.
2047
2048 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2049
2050Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2051
2052 * interp.c (mips_option_handler): New function parse argumes using
2053 sim-options.
2054 (myname): Replace with STATE_MY_NAME.
2055 (sim_open): Delete check for host endianness - performed by
2056 sim_config.
2057 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2058 (sim_open): Move much of the initialization from here.
2059 (sim_load): To here. After the image has been loaded and
2060 endianness set.
2061 (sim_open): Move ColdReset from here.
2062 (sim_create_inferior): To here.
2063 (sim_open): Make FP check less dependant on host endianness.
2064
2065 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2066 run.
2067 * interp.c (sim_set_callbacks): Delete.
2068
2069 * interp.c (membank, membank_base, membank_size): Replace with
2070 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2071 (sim_open): Remove call to callback->init. gdb/run do this.
2072
2073 * interp.c: Update
2074
2075 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2076
2077 * interp.c (big_endian_p): Delete, replaced by
2078 current_target_byte_order.
2079
2080Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2081
2082 * interp.c (host_read_long, host_read_word, host_swap_word,
2083 host_swap_long): Delete. Using common sim-endian.
2084 (sim_fetch_register, sim_store_register): Use H2T.
2085 (pipeline_ticks): Delete. Handled by sim-events.
2086 (sim_info): Update.
2087 (sim_engine_run): Update.
2088
2089Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2090
2091 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2092 reason from here.
2093 (SignalException): To here. Signal using sim_engine_halt.
2094 (sim_stop_reason): Delete, moved to common.
2095
2096Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2097
2098 * interp.c (sim_open): Add callback argument.
2099 (sim_set_callbacks): Delete SIM_DESC argument.
2100 (sim_size): Ditto.
2101
2102Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2103
2104 * Makefile.in (SIM_OBJS): Add common modules.
2105
2106 * interp.c (sim_set_callbacks): Also set SD callback.
2107 (set_endianness, xfer_*, swap_*): Delete.
2108 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2109 Change to functions using sim-endian macros.
2110 (control_c, sim_stop): Delete, use common version.
2111 (simulate): Convert into.
2112 (sim_engine_run): This function.
2113 (sim_resume): Delete.
2114
2115 * interp.c (simulation): New variable - the simulator object.
2116 (sim_kind): Delete global - merged into simulation.
2117 (sim_load): Cleanup. Move PC assignment from here.
2118 (sim_create_inferior): To here.
2119
2120 * sim-main.h: New file.
2121 * interp.c (sim-main.h): Include.
2122
2123Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2124
2125 * configure: Regenerated to track ../common/aclocal.m4 changes.
2126
2127Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2128
2129 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2130
2131Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2132
2133 * gencode.c (build_instruction): DIV instructions: check
2134 for division by zero and integer overflow before using
2135 host's division operation.
2136
2137Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2138
2139 * Makefile.in (SIM_OBJS): Add sim-load.o.
2140 * interp.c: #include bfd.h.
2141 (target_byte_order): Delete.
2142 (sim_kind, myname, big_endian_p): New static locals.
2143 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2144 after argument parsing. Recognize -E arg, set endianness accordingly.
2145 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2146 load file into simulator. Set PC from bfd.
2147 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2148 (set_endianness): Use big_endian_p instead of target_byte_order.
2149
2150Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2151
2152 * interp.c (sim_size): Delete prototype - conflicts with
2153 definition in remote-sim.h. Correct definition.
2154
2155Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2156
2157 * configure: Regenerated to track ../common/aclocal.m4 changes.
2158 * config.in: Ditto.
2159
2160Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2161
2162 * interp.c (sim_open): New arg `kind'.
2163
2164 * configure: Regenerated to track ../common/aclocal.m4 changes.
2165
2166Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2167
2168 * configure: Regenerated to track ../common/aclocal.m4 changes.
2169
2170Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2171
2172 * interp.c (sim_open): Set optind to 0 before calling getopt.
2173
2174Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2175
2176 * configure: Regenerated to track ../common/aclocal.m4 changes.
2177
2178Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2179
2180 * interp.c : Replace uses of pr_addr with pr_uword64
2181 where the bit length is always 64 independent of SIM_ADDR.
2182 (pr_uword64) : added.
2183
2184Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2185
2186 * configure: Re-generate.
2187
2188Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2189
2190 * configure: Regenerate to track ../common/aclocal.m4 changes.
2191
2192Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2193
2194 * interp.c (sim_open): New SIM_DESC result. Argument is now
2195 in argv form.
2196 (other sim_*): New SIM_DESC argument.
2197
2198Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2199
2200 * interp.c: Fix printing of addresses for non-64-bit targets.
2201 (pr_addr): Add function to print address based on size.
2202
2203Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2204
2205 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2206
2207Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2208
2209 * gencode.c (build_mips16_operands): Correct computation of base
2210 address for extended PC relative instruction.
2211
2212Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2213
2214 * interp.c (mips16_entry): Add support for floating point cases.
2215 (SignalException): Pass floating point cases to mips16_entry.
2216 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2217 registers.
2218 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2219 or fmt_word.
2220 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2221 and then set the state to fmt_uninterpreted.
2222 (COP_SW): Temporarily set the state to fmt_word while calling
2223 ValueFPR.
2224
2225Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2226
2227 * gencode.c (build_instruction): The high order may be set in the
2228 comparison flags at any ISA level, not just ISA 4.
2229
2230Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2231
2232 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2233 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2234 * configure.in: sinclude ../common/aclocal.m4.
2235 * configure: Regenerated.
2236
2237Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2238
2239 * configure: Rebuild after change to aclocal.m4.
2240
2241Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2242
2243 * configure configure.in Makefile.in: Update to new configure
2244 scheme which is more compatible with WinGDB builds.
2245 * configure.in: Improve comment on how to run autoconf.
2246 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2247 * Makefile.in: Use autoconf substitution to install common
2248 makefile fragment.
2249
2250Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2251
2252 * gencode.c (build_instruction): Use BigEndianCPU instead of
2253 ByteSwapMem.
2254
2255Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2256
2257 * interp.c (sim_monitor): Make output to stdout visible in
2258 wingdb's I/O log window.
2259
2260Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2261
2262 * support.h: Undo previous change to SIGTRAP
2263 and SIGQUIT values.
2264
2265Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2266
2267 * interp.c (store_word, load_word): New static functions.
2268 (mips16_entry): New static function.
2269 (SignalException): Look for mips16 entry and exit instructions.
2270 (simulate): Use the correct index when setting fpr_state after
2271 doing a pending move.
2272
2273Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2274
2275 * interp.c: Fix byte-swapping code throughout to work on
2276 both little- and big-endian hosts.
2277
2278Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2279
2280 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2281 with gdb/config/i386/xm-windows.h.
2282
2283Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2284
2285 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2286 that messes up arithmetic shifts.
2287
2288Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2289
2290 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2291 SIGTRAP and SIGQUIT for _WIN32.
2292
2293Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2294
2295 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2296 force a 64 bit multiplication.
2297 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2298 destination register is 0, since that is the default mips16 nop
2299 instruction.
2300
2301Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2302
2303 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2304 (build_endian_shift): Don't check proc64.
2305 (build_instruction): Always set memval to uword64. Cast op2 to
2306 uword64 when shifting it left in memory instructions. Always use
2307 the same code for stores--don't special case proc64.
2308
2309 * gencode.c (build_mips16_operands): Fix base PC value for PC
2310 relative operands.
2311 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2312 jal instruction.
2313 * interp.c (simJALDELAYSLOT): Define.
2314 (JALDELAYSLOT): Define.
2315 (INDELAYSLOT, INJALDELAYSLOT): Define.
2316 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2317
2318Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2319
2320 * interp.c (sim_open): add flush_cache as a PMON routine
2321 (sim_monitor): handle flush_cache by ignoring it
2322
2323Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2324
2325 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2326 BigEndianMem.
2327 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2328 (BigEndianMem): Rename to ByteSwapMem and change sense.
2329 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2330 BigEndianMem references to !ByteSwapMem.
2331 (set_endianness): New function, with prototype.
2332 (sim_open): Call set_endianness.
2333 (sim_info): Use simBE instead of BigEndianMem.
2334 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2335 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2336 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2337 ifdefs, keeping the prototype declaration.
2338 (swap_word): Rewrite correctly.
2339 (ColdReset): Delete references to CONFIG. Delete endianness related
2340 code; moved to set_endianness.
2341
2342Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2343
2344 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2345 * interp.c (CHECKHILO): Define away.
2346 (simSIGINT): New macro.
2347 (membank_size): Increase from 1MB to 2MB.
2348 (control_c): New function.
2349 (sim_resume): Rename parameter signal to signal_number. Add local
2350 variable prev. Call signal before and after simulate.
2351 (sim_stop_reason): Add simSIGINT support.
2352 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2353 functions always.
2354 (sim_warning): Delete call to SignalException. Do call printf_filtered
2355 if logfh is NULL.
2356 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2357 a call to sim_warning.
2358
2359Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2360
2361 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2362 16 bit instructions.
2363
2364Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2365
2366 Add support for mips16 (16 bit MIPS implementation):
2367 * gencode.c (inst_type): Add mips16 instruction encoding types.
2368 (GETDATASIZEINSN): Define.
2369 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2370 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2371 mtlo.
2372 (MIPS16_DECODE): New table, for mips16 instructions.
2373 (bitmap_val): New static function.
2374 (struct mips16_op): Define.
2375 (mips16_op_table): New table, for mips16 operands.
2376 (build_mips16_operands): New static function.
2377 (process_instructions): If PC is odd, decode a mips16
2378 instruction. Break out instruction handling into new
2379 build_instruction function.
2380 (build_instruction): New static function, broken out of
2381 process_instructions. Check modifiers rather than flags for SHIFT
2382 bit count and m[ft]{hi,lo} direction.
2383 (usage): Pass program name to fprintf.
2384 (main): Remove unused variable this_option_optind. Change
2385 ``*loptarg++'' to ``loptarg++''.
2386 (my_strtoul): Parenthesize && within ||.
2387 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2388 (simulate): If PC is odd, fetch a 16 bit instruction, and
2389 increment PC by 2 rather than 4.
2390 * configure.in: Add case for mips16*-*-*.
2391 * configure: Rebuild.
2392
2393Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2394
2395 * interp.c: Allow -t to enable tracing in standalone simulator.
2396 Fix garbage output in trace file and error messages.
2397
2398Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2399
2400 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2401 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2402 * configure.in: Simplify using macros in ../common/aclocal.m4.
2403 * configure: Regenerated.
2404 * tconfig.in: New file.
2405
2406Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2407
2408 * interp.c: Fix bugs in 64-bit port.
2409 Use ansi function declarations for msvc compiler.
2410 Initialize and test file pointer in trace code.
2411 Prevent duplicate definition of LAST_EMED_REGNUM.
2412
2413Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2414
2415 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2416
2417Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2418
2419 * interp.c (SignalException): Check for explicit terminating
2420 breakpoint value.
2421 * gencode.c: Pass instruction value through SignalException()
2422 calls for Trap, Breakpoint and Syscall.
2423
2424Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2425
2426 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2427 only used on those hosts that provide it.
2428 * configure.in: Add sqrt() to list of functions to be checked for.
2429 * config.in: Re-generated.
2430 * configure: Re-generated.
2431
2432Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2433
2434 * gencode.c (process_instructions): Call build_endian_shift when
2435 expanding STORE RIGHT, to fix swr.
2436 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2437 clear the high bits.
2438 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2439 Fix float to int conversions to produce signed values.
2440
2441Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2442
2443 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2444 (process_instructions): Correct handling of nor instruction.
2445 Correct shift count for 32 bit shift instructions. Correct sign
2446 extension for arithmetic shifts to not shift the number of bits in
2447 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2448 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2449 Fix madd.
2450 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2451 It's OK to have a mult follow a mult. What's not OK is to have a
2452 mult follow an mfhi.
2453 (Convert): Comment out incorrect rounding code.
2454
2455Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2456
2457 * interp.c (sim_monitor): Improved monitor printf
2458 simulation. Tidied up simulator warnings, and added "--log" option
2459 for directing warning message output.
2460 * gencode.c: Use sim_warning() rather than WARNING macro.
2461
2462Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2463
2464 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2465 getopt1.o, rather than on gencode.c. Link objects together.
2466 Don't link against -liberty.
2467 (gencode.o, getopt.o, getopt1.o): New targets.
2468 * gencode.c: Include <ctype.h> and "ansidecl.h".
2469 (AND): Undefine after including "ansidecl.h".
2470 (ULONG_MAX): Define if not defined.
2471 (OP_*): Don't define macros; now defined in opcode/mips.h.
2472 (main): Call my_strtoul rather than strtoul.
2473 (my_strtoul): New static function.
2474
2475Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2476
2477 * gencode.c (process_instructions): Generate word64 and uword64
2478 instead of `long long' and `unsigned long long' data types.
2479 * interp.c: #include sysdep.h to get signals, and define default
2480 for SIGBUS.
2481 * (Convert): Work around for Visual-C++ compiler bug with type
2482 conversion.
2483 * support.h: Make things compile under Visual-C++ by using
2484 __int64 instead of `long long'. Change many refs to long long
2485 into word64/uword64 typedefs.
2486
2487Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2488
2489 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2490 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2491 (docdir): Removed.
2492 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2493 (AC_PROG_INSTALL): Added.
2494 (AC_PROG_CC): Moved to before configure.host call.
2495 * configure: Rebuilt.
2496
2497Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2498
2499 * configure.in: Define @SIMCONF@ depending on mips target.
2500 * configure: Rebuild.
2501 * Makefile.in (run): Add @SIMCONF@ to control simulator
2502 construction.
2503 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2504 * interp.c: Remove some debugging, provide more detailed error
2505 messages, update memory accesses to use LOADDRMASK.
2506
2507Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2508
2509 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2510 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2511 stamp-h.
2512 * configure: Rebuild.
2513 * config.in: New file, generated by autoheader.
2514 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2515 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2516 HAVE_ANINT and HAVE_AINT, as appropriate.
2517 * Makefile.in (run): Use @LIBS@ rather than -lm.
2518 (interp.o): Depend upon config.h.
2519 (Makefile): Just rebuild Makefile.
2520 (clean): Remove stamp-h.
2521 (mostlyclean): Make the same as clean, not as distclean.
2522 (config.h, stamp-h): New targets.
2523
2524Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2525
2526 * interp.c (ColdReset): Fix boolean test. Make all simulator
2527 globals static.
2528
2529Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2530
2531 * interp.c (xfer_direct_word, xfer_direct_long,
2532 swap_direct_word, swap_direct_long, xfer_big_word,
2533 xfer_big_long, xfer_little_word, xfer_little_long,
2534 swap_word,swap_long): Added.
2535 * interp.c (ColdReset): Provide function indirection to
2536 host<->simulated_target transfer routines.
2537 * interp.c (sim_store_register, sim_fetch_register): Updated to
2538 make use of indirected transfer routines.
2539
2540Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2541
2542 * gencode.c (process_instructions): Ensure FP ABS instruction
2543 recognised.
2544 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2545 system call support.
2546
2547Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2548
2549 * interp.c (sim_do_command): Complain if callback structure not
2550 initialised.
2551
2552Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2553
2554 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2555 support for Sun hosts.
2556 * Makefile.in (gencode): Ensure the host compiler and libraries
2557 used for cross-hosted build.
2558
2559Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2560
2561 * interp.c, gencode.c: Some more (TODO) tidying.
2562
2563Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2564
2565 * gencode.c, interp.c: Replaced explicit long long references with
2566 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2567 * support.h (SET64LO, SET64HI): Macros added.
2568
2569Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2570
2571 * configure: Regenerate with autoconf 2.7.
2572
2573Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2574
2575 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2576 * support.h: Remove superfluous "1" from #if.
2577 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2578
2579Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2580
2581 * interp.c (StoreFPR): Control UndefinedResult() call on
2582 WARN_RESULT manifest.
2583
2584Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2585
2586 * gencode.c: Tidied instruction decoding, and added FP instruction
2587 support.
2588
2589 * interp.c: Added dineroIII, and BSD profiling support. Also
2590 run-time FP handling.
2591
2592Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2593
2594 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2595 gencode.c, interp.c, support.h: created.
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