]>
Commit | Line | Data |
---|---|---|
0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
4 | * (C) Copyright 2008 Armadeus Systems nc | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <malloc.h> | |
26 | #include <net.h> | |
27 | #include <miiphy.h> | |
28 | #include "fec_mxc.h" | |
29 | ||
30 | #include <asm/arch/clock.h> | |
31 | #include <asm/arch/imx-regs.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/errno.h> | |
e2a66e60 | 34 | #include <linux/compiler.h> |
0b23fb36 IY |
35 | |
36 | DECLARE_GLOBAL_DATA_PTR; | |
37 | ||
bc1ce150 MV |
38 | /* |
39 | * Timeout the transfer after 5 mS. This is usually a bit more, since | |
40 | * the code in the tightloops this timeout is used in adds some overhead. | |
41 | */ | |
42 | #define FEC_XFER_TIMEOUT 5000 | |
43 | ||
0b23fb36 IY |
44 | #ifndef CONFIG_MII |
45 | #error "CONFIG_MII has to be defined!" | |
46 | #endif | |
47 | ||
5c1ad3e6 EN |
48 | #ifndef CONFIG_FEC_XCV_TYPE |
49 | #define CONFIG_FEC_XCV_TYPE MII100 | |
392b8502 MV |
50 | #endif |
51 | ||
be7e87e2 MV |
52 | /* |
53 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
54 | * sending and after receiving. | |
55 | */ | |
5c1ad3e6 EN |
56 | #ifdef CONFIG_MX28 |
57 | #define CONFIG_FEC_MXC_SWAP_PACKET | |
58 | #endif | |
59 | ||
60 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) | |
61 | ||
62 | /* Check various alignment issues at compile time */ | |
63 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) | |
64 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" | |
65 | #endif | |
66 | ||
67 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ | |
68 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) | |
69 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" | |
be7e87e2 MV |
70 | #endif |
71 | ||
0b23fb36 IY |
72 | #undef DEBUG |
73 | ||
74 | struct nbuf { | |
75 | uint8_t data[1500]; /**< actual data */ | |
76 | int length; /**< actual length */ | |
77 | int used; /**< buffer in use or not */ | |
78 | uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ | |
79 | }; | |
80 | ||
5c1ad3e6 | 81 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
82 | static void swap_packet(uint32_t *packet, int length) |
83 | { | |
84 | int i; | |
85 | ||
86 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
87 | packet[i] = __swab32(packet[i]); | |
88 | } | |
89 | #endif | |
90 | ||
0b23fb36 IY |
91 | /* |
92 | * MII-interface related functions | |
93 | */ | |
13947f43 TK |
94 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, |
95 | uint8_t regAddr) | |
0b23fb36 | 96 | { |
0b23fb36 IY |
97 | uint32_t reg; /* convenient holder for the PHY register */ |
98 | uint32_t phy; /* convenient holder for the PHY */ | |
99 | uint32_t start; | |
13947f43 | 100 | int val; |
0b23fb36 IY |
101 | |
102 | /* | |
103 | * reading from any PHY's register is done by properly | |
104 | * programming the FEC's MII data register. | |
105 | */ | |
d133b881 | 106 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
107 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; |
108 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
109 | ||
110 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 111 | phy | reg, ð->mii_data); |
0b23fb36 IY |
112 | |
113 | /* | |
114 | * wait for the related interrupt | |
115 | */ | |
a60d1e5b | 116 | start = get_timer(0); |
d133b881 | 117 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
118 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
119 | printf("Read MDIO failed...\n"); | |
120 | return -1; | |
121 | } | |
122 | } | |
123 | ||
124 | /* | |
125 | * clear mii interrupt bit | |
126 | */ | |
d133b881 | 127 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
128 | |
129 | /* | |
130 | * it's now safe to read the PHY's register | |
131 | */ | |
13947f43 TK |
132 | val = (unsigned short)readl(ð->mii_data); |
133 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, | |
134 | regAddr, val); | |
135 | return val; | |
0b23fb36 IY |
136 | } |
137 | ||
575c5cc0 | 138 | static void fec_mii_setspeed(struct ethernet_regs *eth) |
4294b248 SB |
139 | { |
140 | /* | |
141 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
142 | * and do not drop the Preamble. | |
143 | */ | |
144 | writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, | |
575c5cc0 TK |
145 | ð->mii_speed); |
146 | debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); | |
4294b248 | 147 | } |
0b23fb36 | 148 | |
13947f43 TK |
149 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, |
150 | uint8_t regAddr, uint16_t data) | |
151 | { | |
0b23fb36 IY |
152 | uint32_t reg; /* convenient holder for the PHY register */ |
153 | uint32_t phy; /* convenient holder for the PHY */ | |
154 | uint32_t start; | |
155 | ||
156 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; | |
157 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
158 | ||
159 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 160 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 IY |
161 | |
162 | /* | |
163 | * wait for the MII interrupt | |
164 | */ | |
a60d1e5b | 165 | start = get_timer(0); |
d133b881 | 166 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
167 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
168 | printf("Write MDIO failed...\n"); | |
169 | return -1; | |
170 | } | |
171 | } | |
172 | ||
173 | /* | |
174 | * clear MII interrupt bit | |
175 | */ | |
d133b881 | 176 | writel(FEC_IEVENT_MII, ð->ievent); |
13947f43 | 177 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, |
0b23fb36 IY |
178 | regAddr, data); |
179 | ||
180 | return 0; | |
181 | } | |
182 | ||
13947f43 TK |
183 | int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr) |
184 | { | |
185 | return fec_mdio_read(bus->priv, phyAddr, regAddr); | |
186 | } | |
187 | ||
188 | int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr, | |
189 | u16 data) | |
190 | { | |
191 | return fec_mdio_write(bus->priv, phyAddr, regAddr, data); | |
192 | } | |
193 | ||
194 | #ifndef CONFIG_PHYLIB | |
0b23fb36 IY |
195 | static int miiphy_restart_aneg(struct eth_device *dev) |
196 | { | |
b774fe9d SB |
197 | int ret = 0; |
198 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) | |
9e27e9dc | 199 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 200 | struct ethernet_regs *eth = fec->bus->priv; |
9e27e9dc | 201 | |
0b23fb36 IY |
202 | /* |
203 | * Wake up from sleep if necessary | |
204 | * Reset PHY, then delay 300ns | |
205 | */ | |
cb17b92d | 206 | #ifdef CONFIG_MX27 |
13947f43 | 207 | fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); |
cb17b92d | 208 | #endif |
13947f43 | 209 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
0b23fb36 IY |
210 | udelay(1000); |
211 | ||
212 | /* | |
213 | * Set the auto-negotiation advertisement register bits | |
214 | */ | |
13947f43 | 215 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
8ef583a0 MF |
216 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
217 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
13947f43 | 218 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
8ef583a0 | 219 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
220 | |
221 | if (fec->mii_postcall) | |
222 | ret = fec->mii_postcall(fec->phy_id); | |
223 | ||
b774fe9d | 224 | #endif |
2e5f4421 | 225 | return ret; |
0b23fb36 IY |
226 | } |
227 | ||
228 | static int miiphy_wait_aneg(struct eth_device *dev) | |
229 | { | |
230 | uint32_t start; | |
13947f43 | 231 | int status; |
9e27e9dc | 232 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 233 | struct ethernet_regs *eth = fec->bus->priv; |
0b23fb36 IY |
234 | |
235 | /* | |
236 | * Wait for AN completion | |
237 | */ | |
a60d1e5b | 238 | start = get_timer(0); |
0b23fb36 IY |
239 | do { |
240 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
241 | printf("%s: Autonegotiation timeout\n", dev->name); | |
242 | return -1; | |
243 | } | |
244 | ||
13947f43 TK |
245 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
246 | if (status < 0) { | |
247 | printf("%s: Autonegotiation failed. status: %d\n", | |
0b23fb36 IY |
248 | dev->name, status); |
249 | return -1; | |
250 | } | |
8ef583a0 | 251 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
252 | |
253 | return 0; | |
254 | } | |
13947f43 TK |
255 | #endif |
256 | ||
0b23fb36 IY |
257 | static int fec_rx_task_enable(struct fec_priv *fec) |
258 | { | |
c0b5a3bb | 259 | writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); |
0b23fb36 IY |
260 | return 0; |
261 | } | |
262 | ||
263 | static int fec_rx_task_disable(struct fec_priv *fec) | |
264 | { | |
265 | return 0; | |
266 | } | |
267 | ||
268 | static int fec_tx_task_enable(struct fec_priv *fec) | |
269 | { | |
c0b5a3bb | 270 | writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); |
0b23fb36 IY |
271 | return 0; |
272 | } | |
273 | ||
274 | static int fec_tx_task_disable(struct fec_priv *fec) | |
275 | { | |
276 | return 0; | |
277 | } | |
278 | ||
279 | /** | |
280 | * Initialize receive task's buffer descriptors | |
281 | * @param[in] fec all we know about the device yet | |
282 | * @param[in] count receive buffer count to be allocated | |
5c1ad3e6 | 283 | * @param[in] dsize desired size of each receive buffer |
0b23fb36 IY |
284 | * @return 0 on success |
285 | * | |
286 | * For this task we need additional memory for the data buffers. And each | |
287 | * data buffer requires some alignment. Thy must be aligned to a specific | |
5c1ad3e6 | 288 | * boundary each. |
0b23fb36 | 289 | */ |
5c1ad3e6 | 290 | static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
0b23fb36 | 291 | { |
5c1ad3e6 EN |
292 | uint32_t size; |
293 | int i; | |
294 | ||
0b23fb36 | 295 | /* |
5c1ad3e6 EN |
296 | * Allocate memory for the buffers. This allocation respects the |
297 | * alignment | |
0b23fb36 | 298 | */ |
5c1ad3e6 EN |
299 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
300 | for (i = 0; i < count; i++) { | |
301 | uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); | |
302 | if (data_ptr == 0) { | |
303 | uint8_t *data = memalign(ARCH_DMA_MINALIGN, | |
304 | size); | |
305 | if (!data) { | |
306 | printf("%s: error allocating rxbuf %d\n", | |
307 | __func__, i); | |
308 | goto err; | |
309 | } | |
310 | writel((uint32_t)data, &fec->rbd_base[i].data_pointer); | |
311 | } /* needs allocation */ | |
312 | writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status); | |
313 | writew(0, &fec->rbd_base[i].data_length); | |
314 | } | |
315 | ||
316 | /* Mark the last RBD to close the ring. */ | |
317 | writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status); | |
0b23fb36 IY |
318 | fec->rbd_index = 0; |
319 | ||
320 | return 0; | |
5c1ad3e6 EN |
321 | |
322 | err: | |
323 | for (; i >= 0; i--) { | |
324 | uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); | |
325 | free((void *)data_ptr); | |
326 | } | |
327 | ||
328 | return -ENOMEM; | |
0b23fb36 IY |
329 | } |
330 | ||
331 | /** | |
332 | * Initialize transmit task's buffer descriptors | |
333 | * @param[in] fec all we know about the device yet | |
334 | * | |
335 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
336 | * Note: There is a race condition in the hardware. When only one BD is in | |
337 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
338 | * This bit in combination with the READY bit results into double transmit | |
339 | * of each data buffer. It seems the state machine checks READY earlier then | |
340 | * resetting it after the first transfer. | |
341 | * Using two BDs solves this issue. | |
342 | */ | |
343 | static void fec_tbd_init(struct fec_priv *fec) | |
344 | { | |
5c1ad3e6 EN |
345 | unsigned addr = (unsigned)fec->tbd_base; |
346 | unsigned size = roundup(2 * sizeof(struct fec_bd), | |
347 | ARCH_DMA_MINALIGN); | |
0b23fb36 IY |
348 | writew(0x0000, &fec->tbd_base[0].status); |
349 | writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); | |
350 | fec->tbd_index = 0; | |
5c1ad3e6 | 351 | flush_dcache_range(addr, addr+size); |
0b23fb36 IY |
352 | } |
353 | ||
354 | /** | |
355 | * Mark the given read buffer descriptor as free | |
356 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
357 | * @param[in] pRbd buffer descriptor to mark free again | |
358 | */ | |
359 | static void fec_rbd_clean(int last, struct fec_bd *pRbd) | |
360 | { | |
5c1ad3e6 | 361 | unsigned short flags = FEC_RBD_EMPTY; |
0b23fb36 | 362 | if (last) |
5c1ad3e6 EN |
363 | flags |= FEC_RBD_WRAP; |
364 | writew(flags, &pRbd->status); | |
0b23fb36 IY |
365 | writew(0, &pRbd->data_length); |
366 | } | |
367 | ||
be252b65 FE |
368 | static int fec_get_hwaddr(struct eth_device *dev, int dev_id, |
369 | unsigned char *mac) | |
0b23fb36 | 370 | { |
be252b65 | 371 | imx_get_mac_from_fuse(dev_id, mac); |
2e236bf2 | 372 | return !is_valid_ether_addr(mac); |
0b23fb36 IY |
373 | } |
374 | ||
4294b248 | 375 | static int fec_set_hwaddr(struct eth_device *dev) |
0b23fb36 | 376 | { |
4294b248 | 377 | uchar *mac = dev->enetaddr; |
0b23fb36 IY |
378 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
379 | ||
380 | writel(0, &fec->eth->iaddr1); | |
381 | writel(0, &fec->eth->iaddr2); | |
382 | writel(0, &fec->eth->gaddr1); | |
383 | writel(0, &fec->eth->gaddr2); | |
384 | ||
385 | /* | |
386 | * Set physical address | |
387 | */ | |
388 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], | |
389 | &fec->eth->paddr1); | |
390 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
a5990b26 MV |
395 | /* |
396 | * Do initial configuration of the FEC registers | |
397 | */ | |
398 | static void fec_reg_setup(struct fec_priv *fec) | |
399 | { | |
400 | uint32_t rcntrl; | |
401 | ||
402 | /* | |
403 | * Set interrupt mask register | |
404 | */ | |
405 | writel(0x00000000, &fec->eth->imask); | |
406 | ||
407 | /* | |
408 | * Clear FEC-Lite interrupt event register(IEVENT) | |
409 | */ | |
410 | writel(0xffffffff, &fec->eth->ievent); | |
411 | ||
412 | ||
413 | /* | |
414 | * Set FEC-Lite receive control register(R_CNTRL): | |
415 | */ | |
416 | ||
417 | /* Start with frame length = 1518, common for all modes. */ | |
418 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
9d2d924a | 419 | if (fec->xcv_type != SEVENWIRE) /* xMII modes */ |
420 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
421 | if (fec->xcv_type == RGMII) | |
a5990b26 MV |
422 | rcntrl |= FEC_RCNTRL_RGMII; |
423 | else if (fec->xcv_type == RMII) | |
424 | rcntrl |= FEC_RCNTRL_RMII; | |
a5990b26 MV |
425 | |
426 | writel(rcntrl, &fec->eth->r_cntrl); | |
427 | } | |
428 | ||
0b23fb36 IY |
429 | /** |
430 | * Start the FEC engine | |
431 | * @param[in] dev Our device to handle | |
432 | */ | |
433 | static int fec_open(struct eth_device *edev) | |
434 | { | |
435 | struct fec_priv *fec = (struct fec_priv *)edev->priv; | |
28774cba | 436 | int speed; |
5c1ad3e6 EN |
437 | uint32_t addr, size; |
438 | int i; | |
0b23fb36 IY |
439 | |
440 | debug("fec_open: fec_open(dev)\n"); | |
441 | /* full-duplex, heartbeat disabled */ | |
442 | writel(1 << 2, &fec->eth->x_cntrl); | |
443 | fec->rbd_index = 0; | |
444 | ||
5c1ad3e6 EN |
445 | /* Invalidate all descriptors */ |
446 | for (i = 0; i < FEC_RBD_NUM - 1; i++) | |
447 | fec_rbd_clean(0, &fec->rbd_base[i]); | |
448 | fec_rbd_clean(1, &fec->rbd_base[i]); | |
449 | ||
450 | /* Flush the descriptors into RAM */ | |
451 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
452 | ARCH_DMA_MINALIGN); | |
453 | addr = (uint32_t)fec->rbd_base; | |
454 | flush_dcache_range(addr, addr + size); | |
455 | ||
28774cba | 456 | #ifdef FEC_QUIRK_ENET_MAC |
2ef2b950 JL |
457 | /* Enable ENET HW endian SWAP */ |
458 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
459 | &fec->eth->ecntrl); | |
460 | /* Enable ENET store and forward mode */ | |
461 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
462 | &fec->eth->x_wmrk); | |
463 | #endif | |
0b23fb36 IY |
464 | /* |
465 | * Enable FEC-Lite controller | |
466 | */ | |
cb17b92d JR |
467 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
468 | &fec->eth->ecntrl); | |
96912453 | 469 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) |
740d6ae5 JR |
470 | udelay(100); |
471 | /* | |
472 | * setup the MII gasket for RMII mode | |
473 | */ | |
474 | ||
475 | /* disable the gasket */ | |
476 | writew(0, &fec->eth->miigsk_enr); | |
477 | ||
478 | /* wait for the gasket to be disabled */ | |
479 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
480 | udelay(2); | |
481 | ||
482 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
483 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
484 | ||
485 | /* re-enable the gasket */ | |
486 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
487 | ||
488 | /* wait until MII gasket is ready */ | |
489 | int max_loops = 10; | |
490 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
491 | if (--max_loops <= 0) { | |
492 | printf("WAIT for MII Gasket ready timed out\n"); | |
493 | break; | |
494 | } | |
495 | } | |
496 | #endif | |
0b23fb36 | 497 | |
13947f43 | 498 | #ifdef CONFIG_PHYLIB |
4dc27eed | 499 | { |
13947f43 | 500 | /* Start up the PHY */ |
11af8d65 TT |
501 | int ret = phy_startup(fec->phydev); |
502 | ||
503 | if (ret) { | |
504 | printf("Could not initialize PHY %s\n", | |
505 | fec->phydev->dev->name); | |
506 | return ret; | |
507 | } | |
13947f43 | 508 | speed = fec->phydev->speed; |
13947f43 TK |
509 | } |
510 | #else | |
0b23fb36 | 511 | miiphy_wait_aneg(edev); |
28774cba | 512 | speed = miiphy_speed(edev->name, fec->phy_id); |
9e27e9dc | 513 | miiphy_duplex(edev->name, fec->phy_id); |
13947f43 | 514 | #endif |
0b23fb36 | 515 | |
28774cba TK |
516 | #ifdef FEC_QUIRK_ENET_MAC |
517 | { | |
518 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; | |
519 | u32 rcr = (readl(&fec->eth->r_cntrl) & | |
520 | ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | | |
521 | FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; | |
522 | if (speed == _1000BASET) | |
523 | ecr |= FEC_ECNTRL_SPEED; | |
524 | else if (speed != _100BASET) | |
525 | rcr |= FEC_RCNTRL_RMII_10T; | |
526 | writel(ecr, &fec->eth->ecntrl); | |
527 | writel(rcr, &fec->eth->r_cntrl); | |
528 | } | |
529 | #endif | |
530 | debug("%s:Speed=%i\n", __func__, speed); | |
531 | ||
0b23fb36 IY |
532 | /* |
533 | * Enable SmartDMA receive task | |
534 | */ | |
535 | fec_rx_task_enable(fec); | |
536 | ||
537 | udelay(100000); | |
538 | return 0; | |
539 | } | |
540 | ||
541 | static int fec_init(struct eth_device *dev, bd_t* bd) | |
542 | { | |
0b23fb36 | 543 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
9e27e9dc | 544 | uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; |
5c1ad3e6 EN |
545 | uint32_t size; |
546 | int i, ret; | |
0b23fb36 | 547 | |
e9319f11 JR |
548 | /* Initialize MAC address */ |
549 | fec_set_hwaddr(dev); | |
550 | ||
0b23fb36 | 551 | /* |
5c1ad3e6 EN |
552 | * Allocate transmit descriptors, there are two in total. This |
553 | * allocation respects cache alignment. | |
0b23fb36 | 554 | */ |
5c1ad3e6 EN |
555 | if (!fec->tbd_base) { |
556 | size = roundup(2 * sizeof(struct fec_bd), | |
557 | ARCH_DMA_MINALIGN); | |
558 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
559 | if (!fec->tbd_base) { | |
560 | ret = -ENOMEM; | |
561 | goto err1; | |
562 | } | |
563 | memset(fec->tbd_base, 0, size); | |
564 | fec_tbd_init(fec); | |
565 | flush_dcache_range((unsigned)fec->tbd_base, size); | |
0b23fb36 | 566 | } |
0b23fb36 | 567 | |
5c1ad3e6 EN |
568 | /* |
569 | * Allocate receive descriptors. This allocation respects cache | |
570 | * alignment. | |
571 | */ | |
572 | if (!fec->rbd_base) { | |
573 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
574 | ARCH_DMA_MINALIGN); | |
575 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
576 | if (!fec->rbd_base) { | |
577 | ret = -ENOMEM; | |
578 | goto err2; | |
579 | } | |
580 | memset(fec->rbd_base, 0, size); | |
581 | /* | |
582 | * Initialize RxBD ring | |
583 | */ | |
584 | if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { | |
585 | ret = -ENOMEM; | |
586 | goto err3; | |
587 | } | |
588 | flush_dcache_range((unsigned)fec->rbd_base, | |
589 | (unsigned)fec->rbd_base + size); | |
590 | } | |
0b23fb36 | 591 | |
a5990b26 | 592 | fec_reg_setup(fec); |
9eb3770b | 593 | |
f41471e6 | 594 | if (fec->xcv_type != SEVENWIRE) |
575c5cc0 | 595 | fec_mii_setspeed(fec->bus->priv); |
9eb3770b | 596 | |
0b23fb36 IY |
597 | /* |
598 | * Set Opcode/Pause Duration Register | |
599 | */ | |
600 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ | |
601 | writel(0x2, &fec->eth->x_wmrk); | |
602 | /* | |
603 | * Set multicast address filter | |
604 | */ | |
605 | writel(0x00000000, &fec->eth->gaddr1); | |
606 | writel(0x00000000, &fec->eth->gaddr2); | |
607 | ||
608 | ||
609 | /* clear MIB RAM */ | |
9e27e9dc MV |
610 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) |
611 | writel(0, i); | |
0b23fb36 IY |
612 | |
613 | /* FIFO receive start register */ | |
614 | writel(0x520, &fec->eth->r_fstart); | |
615 | ||
616 | /* size and address of each buffer */ | |
617 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
618 | writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); | |
619 | writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); | |
620 | ||
13947f43 | 621 | #ifndef CONFIG_PHYLIB |
0b23fb36 IY |
622 | if (fec->xcv_type != SEVENWIRE) |
623 | miiphy_restart_aneg(dev); | |
13947f43 | 624 | #endif |
0b23fb36 IY |
625 | fec_open(dev); |
626 | return 0; | |
5c1ad3e6 EN |
627 | |
628 | err3: | |
629 | free(fec->rbd_base); | |
630 | err2: | |
631 | free(fec->tbd_base); | |
632 | err1: | |
633 | return ret; | |
0b23fb36 IY |
634 | } |
635 | ||
636 | /** | |
637 | * Halt the FEC engine | |
638 | * @param[in] dev Our device to handle | |
639 | */ | |
640 | static void fec_halt(struct eth_device *dev) | |
641 | { | |
9e27e9dc | 642 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
0b23fb36 IY |
643 | int counter = 0xffff; |
644 | ||
645 | /* | |
646 | * issue graceful stop command to the FEC transmitter if necessary | |
647 | */ | |
cb17b92d | 648 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
0b23fb36 IY |
649 | &fec->eth->x_cntrl); |
650 | ||
651 | debug("eth_halt: wait for stop regs\n"); | |
652 | /* | |
653 | * wait for graceful stop to register | |
654 | */ | |
655 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) | |
cb17b92d | 656 | udelay(1); |
0b23fb36 IY |
657 | |
658 | /* | |
659 | * Disable SmartDMA tasks | |
660 | */ | |
661 | fec_tx_task_disable(fec); | |
662 | fec_rx_task_disable(fec); | |
663 | ||
664 | /* | |
665 | * Disable the Ethernet Controller | |
666 | * Note: this will also reset the BD index counter! | |
667 | */ | |
740d6ae5 JR |
668 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
669 | &fec->eth->ecntrl); | |
0b23fb36 IY |
670 | fec->rbd_index = 0; |
671 | fec->tbd_index = 0; | |
0b23fb36 IY |
672 | debug("eth_halt: done\n"); |
673 | } | |
674 | ||
675 | /** | |
676 | * Transmit one frame | |
677 | * @param[in] dev Our ethernet device to handle | |
678 | * @param[in] packet Pointer to the data to be transmitted | |
679 | * @param[in] length Data count in bytes | |
680 | * @return 0 on success | |
681 | */ | |
442dac4c | 682 | static int fec_send(struct eth_device *dev, void *packet, int length) |
0b23fb36 IY |
683 | { |
684 | unsigned int status; | |
efe24d2e | 685 | uint32_t size, end; |
5c1ad3e6 | 686 | uint32_t addr; |
bc1ce150 MV |
687 | int timeout = FEC_XFER_TIMEOUT; |
688 | int ret = 0; | |
0b23fb36 IY |
689 | |
690 | /* | |
691 | * This routine transmits one frame. This routine only accepts | |
692 | * 6-byte Ethernet addresses. | |
693 | */ | |
694 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
695 | ||
696 | /* | |
697 | * Check for valid length of data. | |
698 | */ | |
699 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 700 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
701 | return -1; |
702 | } | |
703 | ||
704 | /* | |
5c1ad3e6 EN |
705 | * Setup the transmit buffer. We are always using the first buffer for |
706 | * transmission, the second will be empty and only used to stop the DMA | |
707 | * engine. We also flush the packet to RAM here to avoid cache trouble. | |
0b23fb36 | 708 | */ |
5c1ad3e6 | 709 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
710 | swap_packet((uint32_t *)packet, length); |
711 | #endif | |
5c1ad3e6 EN |
712 | |
713 | addr = (uint32_t)packet; | |
efe24d2e MV |
714 | end = roundup(addr + length, ARCH_DMA_MINALIGN); |
715 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
716 | flush_dcache_range(addr, end); | |
5c1ad3e6 | 717 | |
0b23fb36 | 718 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
5c1ad3e6 EN |
719 | writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
720 | ||
0b23fb36 IY |
721 | /* |
722 | * update BD's status now | |
723 | * This block: | |
724 | * - is always the last in a chain (means no chain) | |
725 | * - should transmitt the CRC | |
726 | * - might be the last BD in the list, so the address counter should | |
727 | * wrap (-> keep the WRAP flag) | |
728 | */ | |
729 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
730 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
731 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
732 | ||
5c1ad3e6 EN |
733 | /* |
734 | * Flush data cache. This code flushes both TX descriptors to RAM. | |
735 | * After this code, the descriptors will be safely in RAM and we | |
736 | * can start DMA. | |
737 | */ | |
738 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
739 | addr = (uint32_t)fec->tbd_base; | |
740 | flush_dcache_range(addr, addr + size); | |
741 | ||
0b23fb36 IY |
742 | /* |
743 | * Enable SmartDMA transmit task | |
744 | */ | |
745 | fec_tx_task_enable(fec); | |
746 | ||
747 | /* | |
5c1ad3e6 EN |
748 | * Wait until frame is sent. On each turn of the wait cycle, we must |
749 | * invalidate data cache to see what's really in RAM. Also, we need | |
750 | * barrier here. | |
0b23fb36 | 751 | */ |
67449098 | 752 | while (--timeout) { |
c0b5a3bb | 753 | if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) |
bc1ce150 | 754 | break; |
0b23fb36 | 755 | } |
5c1ad3e6 | 756 | |
67449098 MV |
757 | if (!timeout) |
758 | ret = -EINVAL; | |
759 | ||
760 | invalidate_dcache_range(addr, addr + size); | |
761 | if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) | |
762 | ret = -EINVAL; | |
763 | ||
764 | debug("fec_send: status 0x%x index %d ret %i\n", | |
0b23fb36 | 765 | readw(&fec->tbd_base[fec->tbd_index].status), |
67449098 | 766 | fec->tbd_index, ret); |
0b23fb36 IY |
767 | /* for next transmission use the other buffer */ |
768 | if (fec->tbd_index) | |
769 | fec->tbd_index = 0; | |
770 | else | |
771 | fec->tbd_index = 1; | |
772 | ||
bc1ce150 | 773 | return ret; |
0b23fb36 IY |
774 | } |
775 | ||
776 | /** | |
777 | * Pull one frame from the card | |
778 | * @param[in] dev Our ethernet device to handle | |
779 | * @return Length of packet read | |
780 | */ | |
781 | static int fec_recv(struct eth_device *dev) | |
782 | { | |
783 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
784 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; | |
785 | unsigned long ievent; | |
786 | int frame_length, len = 0; | |
787 | struct nbuf *frame; | |
788 | uint16_t bd_status; | |
efe24d2e | 789 | uint32_t addr, size, end; |
5c1ad3e6 | 790 | int i; |
e2a66e60 | 791 | uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN); |
0b23fb36 IY |
792 | |
793 | /* | |
794 | * Check if any critical events have happened | |
795 | */ | |
796 | ievent = readl(&fec->eth->ievent); | |
797 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 798 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 IY |
799 | if (ievent & FEC_IEVENT_BABR) { |
800 | fec_halt(dev); | |
801 | fec_init(dev, fec->bd); | |
802 | printf("some error: 0x%08lx\n", ievent); | |
803 | return 0; | |
804 | } | |
805 | if (ievent & FEC_IEVENT_HBERR) { | |
806 | /* Heartbeat error */ | |
807 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
808 | &fec->eth->x_cntrl); | |
809 | } | |
810 | if (ievent & FEC_IEVENT_GRA) { | |
811 | /* Graceful stop complete */ | |
812 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
813 | fec_halt(dev); | |
814 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), | |
815 | &fec->eth->x_cntrl); | |
816 | fec_init(dev, fec->bd); | |
817 | } | |
818 | } | |
819 | ||
820 | /* | |
5c1ad3e6 EN |
821 | * Read the buffer status. Before the status can be read, the data cache |
822 | * must be invalidated, because the data in RAM might have been changed | |
823 | * by DMA. The descriptors are properly aligned to cachelines so there's | |
824 | * no need to worry they'd overlap. | |
825 | * | |
826 | * WARNING: By invalidating the descriptor here, we also invalidate | |
827 | * the descriptors surrounding this one. Therefore we can NOT change the | |
828 | * contents of this descriptor nor the surrounding ones. The problem is | |
829 | * that in order to mark the descriptor as processed, we need to change | |
830 | * the descriptor. The solution is to mark the whole cache line when all | |
831 | * descriptors in the cache line are processed. | |
0b23fb36 | 832 | */ |
5c1ad3e6 EN |
833 | addr = (uint32_t)rbd; |
834 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
835 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
836 | invalidate_dcache_range(addr, addr + size); | |
837 | ||
0b23fb36 IY |
838 | bd_status = readw(&rbd->status); |
839 | debug("fec_recv: status 0x%x\n", bd_status); | |
840 | ||
841 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
842 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
843 | ((readw(&rbd->data_length) - 4) > 14)) { | |
844 | /* | |
845 | * Get buffer address and size | |
846 | */ | |
847 | frame = (struct nbuf *)readl(&rbd->data_pointer); | |
848 | frame_length = readw(&rbd->data_length) - 4; | |
5c1ad3e6 EN |
849 | /* |
850 | * Invalidate data cache over the buffer | |
851 | */ | |
852 | addr = (uint32_t)frame; | |
efe24d2e MV |
853 | end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); |
854 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
855 | invalidate_dcache_range(addr, end); | |
5c1ad3e6 | 856 | |
0b23fb36 IY |
857 | /* |
858 | * Fill the buffer and pass it to upper layers | |
859 | */ | |
5c1ad3e6 | 860 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
861 | swap_packet((uint32_t *)frame->data, frame_length); |
862 | #endif | |
0b23fb36 IY |
863 | memcpy(buff, frame->data, frame_length); |
864 | NetReceive(buff, frame_length); | |
865 | len = frame_length; | |
866 | } else { | |
867 | if (bd_status & FEC_RBD_ERR) | |
868 | printf("error frame: 0x%08lx 0x%08x\n", | |
869 | (ulong)rbd->data_pointer, | |
870 | bd_status); | |
871 | } | |
5c1ad3e6 | 872 | |
0b23fb36 | 873 | /* |
5c1ad3e6 EN |
874 | * Free the current buffer, restart the engine and move forward |
875 | * to the next buffer. Here we check if the whole cacheline of | |
876 | * descriptors was already processed and if so, we mark it free | |
877 | * as whole. | |
0b23fb36 | 878 | */ |
5c1ad3e6 EN |
879 | size = RXDESC_PER_CACHELINE - 1; |
880 | if ((fec->rbd_index & size) == size) { | |
881 | i = fec->rbd_index - size; | |
882 | addr = (uint32_t)&fec->rbd_base[i]; | |
883 | for (; i <= fec->rbd_index ; i++) { | |
884 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), | |
885 | &fec->rbd_base[i]); | |
886 | } | |
887 | flush_dcache_range(addr, | |
888 | addr + ARCH_DMA_MINALIGN); | |
889 | } | |
890 | ||
0b23fb36 IY |
891 | fec_rx_task_enable(fec); |
892 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
893 | } | |
894 | debug("fec_recv: stop\n"); | |
895 | ||
896 | return len; | |
897 | } | |
898 | ||
ef8e3a3b TK |
899 | static void fec_set_dev_name(char *dest, int dev_id) |
900 | { | |
901 | sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); | |
902 | } | |
903 | ||
fe428b90 TK |
904 | #ifdef CONFIG_PHYLIB |
905 | int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
906 | struct mii_dev *bus, struct phy_device *phydev) | |
907 | #else | |
908 | static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
909 | struct mii_dev *bus, int phy_id) | |
910 | #endif | |
0b23fb36 | 911 | { |
0b23fb36 | 912 | struct eth_device *edev; |
9e27e9dc | 913 | struct fec_priv *fec; |
0b23fb36 | 914 | unsigned char ethaddr[6]; |
e382fb48 MV |
915 | uint32_t start; |
916 | int ret = 0; | |
0b23fb36 IY |
917 | |
918 | /* create and fill edev struct */ | |
919 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
920 | if (!edev) { | |
9e27e9dc | 921 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
e382fb48 MV |
922 | ret = -ENOMEM; |
923 | goto err1; | |
9e27e9dc MV |
924 | } |
925 | ||
926 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); | |
927 | if (!fec) { | |
928 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); | |
e382fb48 MV |
929 | ret = -ENOMEM; |
930 | goto err2; | |
0b23fb36 | 931 | } |
9e27e9dc | 932 | |
de0b9576 | 933 | memset(edev, 0, sizeof(*edev)); |
9e27e9dc MV |
934 | memset(fec, 0, sizeof(*fec)); |
935 | ||
0b23fb36 IY |
936 | edev->priv = fec; |
937 | edev->init = fec_init; | |
938 | edev->send = fec_send; | |
939 | edev->recv = fec_recv; | |
940 | edev->halt = fec_halt; | |
fb57ec97 | 941 | edev->write_hwaddr = fec_set_hwaddr; |
0b23fb36 | 942 | |
9e27e9dc | 943 | fec->eth = (struct ethernet_regs *)base_addr; |
0b23fb36 IY |
944 | fec->bd = bd; |
945 | ||
392b8502 | 946 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
0b23fb36 IY |
947 | |
948 | /* Reset chip. */ | |
cb17b92d | 949 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
e382fb48 MV |
950 | start = get_timer(0); |
951 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
952 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
953 | printf("FEC MXC: Timeout reseting chip\n"); | |
954 | goto err3; | |
955 | } | |
0b23fb36 | 956 | udelay(10); |
e382fb48 | 957 | } |
0b23fb36 | 958 | |
a5990b26 | 959 | fec_reg_setup(fec); |
ef8e3a3b TK |
960 | fec_set_dev_name(edev->name, dev_id); |
961 | fec->dev_id = (dev_id == -1) ? 0 : dev_id; | |
fe428b90 TK |
962 | fec->bus = bus; |
963 | fec_mii_setspeed(bus->priv); | |
964 | #ifdef CONFIG_PHYLIB | |
965 | fec->phydev = phydev; | |
966 | phy_connect_dev(phydev, edev); | |
967 | /* Configure phy */ | |
968 | phy_config(phydev); | |
969 | #else | |
9e27e9dc | 970 | fec->phy_id = phy_id; |
fe428b90 TK |
971 | #endif |
972 | eth_register(edev); | |
973 | ||
974 | if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { | |
975 | debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); | |
976 | memcpy(edev->enetaddr, ethaddr, 6); | |
977 | } | |
978 | return ret; | |
979 | err3: | |
980 | free(fec); | |
981 | err2: | |
982 | free(edev); | |
983 | err1: | |
984 | return ret; | |
985 | } | |
986 | ||
987 | struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) | |
988 | { | |
989 | struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; | |
990 | struct mii_dev *bus; | |
991 | int ret; | |
0b23fb36 | 992 | |
13947f43 TK |
993 | bus = mdio_alloc(); |
994 | if (!bus) { | |
995 | printf("mdio_alloc failed\n"); | |
fe428b90 | 996 | return NULL; |
13947f43 TK |
997 | } |
998 | bus->read = fec_phy_read; | |
999 | bus->write = fec_phy_write; | |
fe428b90 | 1000 | bus->priv = eth; |
ef8e3a3b | 1001 | fec_set_dev_name(bus->name, dev_id); |
fe428b90 TK |
1002 | |
1003 | ret = mdio_register(bus); | |
1004 | if (ret) { | |
1005 | printf("mdio_register failed\n"); | |
1006 | free(bus); | |
1007 | return NULL; | |
1008 | } | |
1009 | fec_mii_setspeed(eth); | |
1010 | return bus; | |
1011 | } | |
1012 | ||
1013 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) | |
1014 | { | |
1015 | uint32_t base_mii; | |
1016 | struct mii_dev *bus = NULL; | |
1017 | #ifdef CONFIG_PHYLIB | |
1018 | struct phy_device *phydev = NULL; | |
1019 | #endif | |
1020 | int ret; | |
1021 | ||
5c1ad3e6 | 1022 | #ifdef CONFIG_MX28 |
13947f43 TK |
1023 | /* |
1024 | * The i.MX28 has two ethernet interfaces, but they are not equal. | |
1025 | * Only the first one can access the MDIO bus. | |
1026 | */ | |
fe428b90 | 1027 | base_mii = MXS_ENET0_BASE; |
13947f43 | 1028 | #else |
fe428b90 | 1029 | base_mii = addr; |
13947f43 | 1030 | #endif |
fe428b90 TK |
1031 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); |
1032 | bus = fec_get_miibus(base_mii, dev_id); | |
1033 | if (!bus) | |
1034 | return -ENOMEM; | |
4dc27eed | 1035 | #ifdef CONFIG_PHYLIB |
fe428b90 | 1036 | phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); |
4dc27eed TK |
1037 | if (!phydev) { |
1038 | free(bus); | |
fe428b90 | 1039 | return -ENOMEM; |
4dc27eed | 1040 | } |
fe428b90 TK |
1041 | ret = fec_probe(bd, dev_id, addr, bus, phydev); |
1042 | #else | |
1043 | ret = fec_probe(bd, dev_id, addr, bus, phy_id); | |
4dc27eed | 1044 | #endif |
fe428b90 TK |
1045 | if (ret) { |
1046 | #ifdef CONFIG_PHYLIB | |
1047 | free(phydev); | |
1048 | #endif | |
1049 | free(bus); | |
1050 | } | |
e382fb48 | 1051 | return ret; |
eef24480 | 1052 | } |
0b23fb36 | 1053 | |
eef24480 TK |
1054 | #ifdef CONFIG_FEC_MXC_PHYADDR |
1055 | int fecmxc_initialize(bd_t *bd) | |
1056 | { | |
1057 | return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, | |
1058 | IMX_FEC_BASE); | |
0b23fb36 | 1059 | } |
eef24480 | 1060 | #endif |
2e5f4421 | 1061 | |
13947f43 | 1062 | #ifndef CONFIG_PHYLIB |
2e5f4421 MV |
1063 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) |
1064 | { | |
1065 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
1066 | fec->mii_postcall = cb; | |
1067 | return 0; | |
1068 | } | |
13947f43 | 1069 | #endif |